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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const unsigned long long inf = 1e18; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<unsigned long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } unsigned long long ans = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { for (int k = j; k < n; k++) { ans = max(ans, (a[i] | a[j] | a[k])); } } } cout << ans << n ; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : rf_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Two port register file
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module rf_2p (
clka ,
cena_i ,
addra_i ,
dataa_o ,
clkb ,
cenb_i ,
wenb_i ,
addrb_i ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input [Addr_Width-1:0] addra_i; // address input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if (!cena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> vec[1000006], V; struct Node { int x, y, w; bool operator<(const Node& a) const { return y < a.y; } } node[500006]; int n; struct Info { long long len, mx, w; int p; Info() {} Info(long long _len, long long _mx, long long _w, int _p) { len = _len; mx = _mx; w = _w; p = _p; } Info operator+(const Info& a) { Info ret; ret.len = len + a.len; ret.w = w + a.w; if (a.mx >= a.w + mx - a.len) { ret.mx = a.mx; ret.p = a.p; } else { ret.mx = a.w + mx - a.len; ret.p = p; } return ret; } void pr() { printf( %lld %lld %lld %d n , len, mx, w, p); } } info[1000006 << 2]; void build(int p, int l, int r) { if (l == r) { int len = 0; if (l > 1) len = V[l - 1] - V[l - 2]; info[p] = Info(len, 0, 0, l); return; } int mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); info[p] = info[p << 1] + info[p << 1 | 1]; } void update(int p, int l, int r, int aim, long long w) { if (l == r) { info[p].w += w; info[p].mx += w; return; } int mid = (l + r) >> 1; if (aim <= mid) update(p << 1, l, mid, aim, w); else update(p << 1 | 1, mid + 1, r, aim, w); info[p] = info[p << 1] + info[p << 1 | 1]; } Info query(int p, int l, int r, int L, int R) { if (L <= l && r <= R) { return info[p]; } int mid = (l + r) >> 1; if (L <= mid && R > mid) return query(p << 1, l, mid, L, R) + query(p << 1 | 1, mid + 1, r, L, R); else if (L <= mid) return query(p << 1, l, mid, L, R); else if (R > mid) return query(p << 1 | 1, mid + 1, r, L, R); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &node[i].x, &node[i].y, &node[i].w); if (node[i].x > node[i].y) swap(node[i].x, node[i].y); V.push_back(node[i].x); V.push_back(node[i].y); } sort(node + 1, node + n + 1); sort(V.begin(), V.end()); V.resize(unique(V.begin(), V.end()) - V.begin()); for (int i = 1; i <= n; i++) { node[i].x = lower_bound(V.begin(), V.end(), node[i].x) - V.begin(); node[i].y = lower_bound(V.begin(), V.end(), node[i].y) - V.begin(); vec[node[i].y].push_back(i); } int End = V.size(); build(1, 1, End); long long ans = -1e15; int ansl, ansr; for (int i = 0; i < End; i++) { int siz = (int)vec[i].size(); for (int j = 0; j < siz; j++) update(1, 1, End, node[vec[i][j]].x + 1, node[vec[i][j]].w); Info tmp = query(1, 1, End, 1, i + 1); if (tmp.mx > ans) { ans = tmp.mx; ansl = V[tmp.p - 1]; ansr = V[i]; } } if (ans < 0) ans = 0, ansl = ansr = 2e9; printf( %lld n%d %d %d %d , ans, ansl, ansl, ansr, ansr); return 0; }
|
//====================================================
// This is FSM demo program using single always
// for both seq and combo logic
// Design Name : fsm_using_single_always
// File Name : fsm_using_single_always.v
//=====================================================
module fsm_using_single_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//=============Input Ports=============================
input clock,reset,req_0,req_1;
//=============Output Ports===========================
output gnt_0,gnt_1;
//=============Input ports Data Type===================
wire clock,reset,req_0,req_1;
//=============Output Ports Data Type==================
reg gnt_0,gnt_1;
//=============Internal Constants======================
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//=============Internal Variables======================
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//==========Code startes Here==========================
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT1;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT1;
end else begin
gnt_1 <= 0;
state <= #1 IDLE;
end
default : state <= #1 IDLE;
endcase
end
endmodule // End of Module arbiter
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int x; cin >> x; cout << x / 2 << endl; } }
|
#include <bits/stdc++.h> const long long int maxn = 2e7 + 5; const long long mod = 1e9 + 7; using namespace std; long long int power(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b % 2 == 1) res = res * a; a = a * a; b = b / 2; } return res; } long long po(long long x, long long y) { long long res = 1; x = x % mod; while (y > 0) { if (y & 1) res = ((res % mod) * (x % mod)) % mod; y = y >> 1; x = ((x % mod) * (x % mod)) % mod; } return res; } int dp[3001][3001]; int n; vector<pair<long long int, long long int> > p(3001); int fun(int i, int pp) { if (i >= n) return 0; if (dp[i][pp] != -1) return dp[i][pp]; return dp[i][pp] = min(p[i].second + fun(i + 1, i), abs(p[i].first - p[pp].first) + fun(i + 1, pp)); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { memset(dp, -1, sizeof(dp)); cin >> n; for (int i = 0; i < n; i++) cin >> p[i].first >> p[i].second; p.resize(n); sort((p).begin(), (p).end()); cout << p[0].second + fun(1, 0) << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_1_V
`define SKY130_FD_SC_LS__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_1_V
|
#include <bits/stdc++.h> using namespace std; template <class T> using vec = vector<T>; template <class T> using vvec = vector<vec<T>>; struct fast_ios { fast_ios() { cin.tie(0); ios::sync_with_stdio(false); cout << fixed << setprecision(20); }; } fast_ios_; template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } template <typename T> istream &operator>>(istream &is, vector<T> &vec) { for (T &x : vec) is >> x; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << [ ; for (auto _ : v) os << _ << , ; os << ] ; return os; }; template <typename T> ostream &operator<<(ostream &os, set<T> &st) { os << ( ; for (auto _ : st) { os << _ << , ; } os << ) ; return os; } template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { os << { << p.first << , << p.second << } ; return os; } template <typename T, typename U> ostream &operator<<(ostream &os, const map<T, U> &mp) { os << [ ; for (auto _ : mp) { os << _ << , ; } os << ] << endl; return os; } void dump_func() { cerr << endl; } template <class Head, class... Tail> void dump_func(Head &&head, Tail &&...tail) { cerr << head; if (sizeof...(Tail) > 0) { cerr << , ; } dump_func(std::move(tail)...); } const int INF = (long long)1e9; const long long INFLL = (long long)1e18 + 1; const long long MOD = 1000000007; const long double PI = acos(-1.0); struct mint { long long x; mint(long long _x = 0) : x((_x % MOD + MOD) % MOD) {} mint operator-() const { return mint(-x); } mint &operator+=(const mint a) { if ((x += a.x) >= MOD) x -= MOD; return *this; } mint &operator-=(const mint a) { if ((x += MOD - a.x) >= MOD) x -= MOD; return *this; } mint &operator*=(const mint a) { (x *= a.x) %= MOD; return *this; } mint operator+(const mint a) const { mint res(*this); return res += a; } mint operator-(const mint a) const { mint res(*this); return res -= a; } mint operator*(const mint a) const { mint res(*this); return res *= a; } mint modpow(long long t) const { if (!t) return 1; mint a = modpow(t >> 1); a *= a; if (t & 1) a *= *this; return a; } mint inv() const { return modpow(MOD - 2); } mint &operator/=(const mint a) { return (*this) *= a.inv(); } mint operator/(const mint a) const { mint res(*this); return res /= a; } friend std::ostream &operator<<(std::ostream &os, const mint &a) { os << a.x; return os; } }; int main() { int N; cin >> N; string S; cin >> S; vector<mint> dp(4, 0); dp[0] = 1; for (int i = 0; i < int(N); ++i) { vector<mint> nxt(4, 0); if (S[i] == ? ) { for (int _ = 0; _ < int(3); ++_) for (int j = 0; j < int(4); ++j) nxt[j] += dp[j]; nxt[1] += dp[0]; nxt[2] += dp[1]; nxt[3] += dp[2]; } else { for (int j = 0; j < int(4); ++j) nxt[j] += dp[j]; int from = 0; if (S[i] == b ) from += 1; if (S[i] == c ) from += 2; nxt[from + 1] += dp[from]; } swap(dp, nxt); } cout << dp[3] << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_FUNCTIONAL_PP_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_dma # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input pcie_tx_cmd_wr_en,
input [33:0] pcie_tx_cmd_wr_data,
output pcie_tx_cmd_full_n,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output dma_tx_done_wr_en,
output [20:0] dma_tx_done_wr_data,
input dma_tx_done_wr_rdy_n,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n
);
wire w_pcie_tx_cmd_rd_en;
wire [33:0] w_pcie_tx_cmd_rd_data;
wire w_pcie_tx_cmd_empty_n;
wire w_pcie_tx_fifo_free_en;
wire [9:4] w_pcie_tx_fifo_free_len;
wire w_pcie_tx_fifo_empty_n;
pcie_tx_cmd_fifo
pcie_tx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_tx_cmd_wr_en),
.wr_data (pcie_tx_cmd_wr_data),
.full_n (pcie_tx_cmd_full_n),
.rd_en (w_pcie_tx_cmd_rd_en),
.rd_data (w_pcie_tx_cmd_rd_data),
.empty_n (w_pcie_tx_cmd_empty_n)
);
pcie_tx_fifo
pcie_tx_fifo_inst0
(
.wr_clk (dma_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.alloc_en (pcie_tx_fifo_alloc_en),
.alloc_len (pcie_tx_fifo_alloc_len),
.wr_en (pcie_tx_fifo_wr_en),
.wr_data (pcie_tx_fifo_wr_data),
.full_n (pcie_tx_fifo_full_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_tx_dma_fifo_rd_en),
.rd_data (pcie_tx_dma_fifo_rd_data),
.free_en (w_pcie_tx_fifo_free_en),
.free_len (w_pcie_tx_fifo_free_len),
.empty_n (w_pcie_tx_fifo_empty_n)
);
pcie_tx_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_tx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_rd_en (w_pcie_tx_cmd_rd_en),
.pcie_tx_cmd_rd_data (w_pcie_tx_cmd_rd_data),
.pcie_tx_cmd_empty_n (w_pcie_tx_cmd_empty_n),
.pcie_tx_fifo_free_en (w_pcie_tx_fifo_free_en),
.pcie_tx_fifo_free_len (w_pcie_tx_fifo_free_len),
.pcie_tx_fifo_empty_n (w_pcie_tx_fifo_empty_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.dma_tx_done_wr_en (dma_tx_done_wr_en),
.dma_tx_done_wr_data (dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (dma_tx_done_wr_rdy_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long int> v(n); for (long long int i = 0; i < n; i++) { cin >> v[i]; } sort((v).begin(), (v).end()); set<long long> s; if (n == 1) { cout << -1; } else if (n == 2) { s.insert(v[1] + (v[1] - v[0])); s.insert(v[0] - (v[1] - v[0])); if ((v[1] - v[0]) % 2 == 0) { s.insert(v[0] + (v[1] - v[0]) / 2); } cout << s.size() << n ; for (auto i : s) { cout << i << ; } } else { long long d = INT_MAX; for (long long i = 0; i < n - 1; i++) { d = min(d, v[i + 1] - v[i]); } bool missed = false; bool noap = false; for (long long i = 0; i < n - 1; i++) { if (v[i + 1] == v[i] + d) continue; else { if (v[i + 1] == v[i] + (d * 2)) { if (missed == false) { missed = true; s.insert(v[i] + d); } else { noap = true; break; } } else { noap = true; break; } } } if (noap) { cout << 0; } else if (missed) { cout << 1 << n ; cout << (*s.begin()); } else { s.insert(v[0] - d); s.insert(v[n - 1] + d); cout << s.size() << n ; for (auto i : s) { cout << i << ; } } } }
|
#include <bits/stdc++.h> typedef int iarrN[100003][35]; struct IO { template <typename T> inline IO operator>>(T &n) { n = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) n = (n << 3) + (n << 1) + (c ^ 48), c = getchar(); return *this; } } cin; constexpr int MX = 33, inf = 0x3f3f3f3f; int N, son[100003][35], mnw[100003][35]; long long K, sw[100003][35]; void init() { cin >> N >> K; for (int i = 1; i <= N; ++i) cin >> son[i][0], ++son[i][0]; for (int i = 1; i <= N; ++i) cin >> mnw[i][0], sw[i][0] = mnw[i][0]; for (int j = 1; j <= MX; ++j) for (int i = 1; i <= N; ++i) { son[i][j] = son[son[i][j - 1]][j - 1]; sw[i][j] = sw[i][j - 1] + sw[son[i][j - 1]][j - 1]; mnw[i][j] = std::min(mnw[i][j - 1], mnw[son[i][j - 1]][j - 1]); } } inline void query(int u) { int ansmn = inf; long long k = K, anss = 0; for (int i = MX; i >= 0; --i) if (k >= (1ll << i)) { k -= 1ll << i; anss += sw[u][i]; ansmn = std::min(ansmn, mnw[u][i]); u = son[u][i]; } printf( %I64d %d n , anss, ansmn); } int main() { init(); for (int i = 1; i <= N; ++i) query(i); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void input() {} const int N = 1e5 + 4, mod = 1e9 + 7; int t, k, l, r; long long dp[N]; int solve(int i = 1e5) { if (i < 0) return 0; if (i == 0) return 1; long long &ret = dp[i]; if (~ret) return ret; ret = solve(i - 1) % mod; ret += solve(i - k) % mod; return ret % mod; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); input(); cin >> t >> k; memset(dp, -1, sizeof dp); int x = solve(); dp[0] = 0; for (int i = 1; i <= 1e5; i++) dp[i] += dp[i - 1]; while (t--) { cin >> l >> r; cout << (dp[r] - dp[l - 1]) % mod << endl; } }
|
// AUTOGEN
module iobus_6_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_iob_poweron,
input wire m_iob_reset,
input wire m_datao_clear,
input wire m_datao_set,
input wire m_cono_clear,
input wire m_cono_set,
input wire m_iob_fm_datai,
input wire m_iob_fm_status,
input wire m_rdi_pulse,
input wire [3:9] m_ios,
input wire [0:35] m_iob_write,
output wire [1:7] m_pi_req,
output wire [0:35] m_iob_read,
output wire m_dr_split,
output wire m_rdi_data,
// Slave 0
output wire s0_iob_poweron,
output wire s0_iob_reset,
output wire s0_datao_clear,
output wire s0_datao_set,
output wire s0_cono_clear,
output wire s0_cono_set,
output wire s0_iob_fm_datai,
output wire s0_iob_fm_status,
output wire s0_rdi_pulse,
output wire [3:9] s0_ios,
output wire [0:35] s0_iob_write,
input wire [1:7] s0_pi_req,
input wire [0:35] s0_iob_read,
input wire s0_dr_split,
input wire s0_rdi_data,
// Slave 1
output wire s1_iob_poweron,
output wire s1_iob_reset,
output wire s1_datao_clear,
output wire s1_datao_set,
output wire s1_cono_clear,
output wire s1_cono_set,
output wire s1_iob_fm_datai,
output wire s1_iob_fm_status,
output wire s1_rdi_pulse,
output wire [3:9] s1_ios,
output wire [0:35] s1_iob_write,
input wire [1:7] s1_pi_req,
input wire [0:35] s1_iob_read,
input wire s1_dr_split,
input wire s1_rdi_data,
// Slave 2
output wire s2_iob_poweron,
output wire s2_iob_reset,
output wire s2_datao_clear,
output wire s2_datao_set,
output wire s2_cono_clear,
output wire s2_cono_set,
output wire s2_iob_fm_datai,
output wire s2_iob_fm_status,
output wire s2_rdi_pulse,
output wire [3:9] s2_ios,
output wire [0:35] s2_iob_write,
input wire [1:7] s2_pi_req,
input wire [0:35] s2_iob_read,
input wire s2_dr_split,
input wire s2_rdi_data,
// Slave 3
output wire s3_iob_poweron,
output wire s3_iob_reset,
output wire s3_datao_clear,
output wire s3_datao_set,
output wire s3_cono_clear,
output wire s3_cono_set,
output wire s3_iob_fm_datai,
output wire s3_iob_fm_status,
output wire s3_rdi_pulse,
output wire [3:9] s3_ios,
output wire [0:35] s3_iob_write,
input wire [1:7] s3_pi_req,
input wire [0:35] s3_iob_read,
input wire s3_dr_split,
input wire s3_rdi_data,
// Slave 4
output wire s4_iob_poweron,
output wire s4_iob_reset,
output wire s4_datao_clear,
output wire s4_datao_set,
output wire s4_cono_clear,
output wire s4_cono_set,
output wire s4_iob_fm_datai,
output wire s4_iob_fm_status,
output wire s4_rdi_pulse,
output wire [3:9] s4_ios,
output wire [0:35] s4_iob_write,
input wire [1:7] s4_pi_req,
input wire [0:35] s4_iob_read,
input wire s4_dr_split,
input wire s4_rdi_data,
// Slave 5
output wire s5_iob_poweron,
output wire s5_iob_reset,
output wire s5_datao_clear,
output wire s5_datao_set,
output wire s5_cono_clear,
output wire s5_cono_set,
output wire s5_iob_fm_datai,
output wire s5_iob_fm_status,
output wire s5_rdi_pulse,
output wire [3:9] s5_ios,
output wire [0:35] s5_iob_write,
input wire [1:7] s5_pi_req,
input wire [0:35] s5_iob_read,
input wire s5_dr_split,
input wire s5_rdi_data
);
assign m_pi_req = 0 | s0_pi_req | s1_pi_req | s2_pi_req | s3_pi_req | s4_pi_req | s5_pi_req;
assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read | s2_iob_read | s3_iob_read | s4_iob_read | s5_iob_read;
assign m_dr_split = 0 | s0_dr_split | s1_dr_split | s2_dr_split | s3_dr_split | s4_dr_split | s5_dr_split;
assign m_rdi_data = 0 | s0_rdi_data | s1_rdi_data | s2_rdi_data | s3_rdi_data | s4_rdi_data | s5_rdi_data;
assign s0_iob_poweron = m_iob_poweron;
assign s0_iob_reset = m_iob_reset;
assign s0_datao_clear = m_datao_clear;
assign s0_datao_set = m_datao_set;
assign s0_cono_clear = m_cono_clear;
assign s0_cono_set = m_cono_set;
assign s0_iob_fm_datai = m_iob_fm_datai;
assign s0_iob_fm_status = m_iob_fm_status;
assign s0_rdi_pulse = m_rdi_pulse;
assign s0_ios = m_ios;
assign s0_iob_write = m_iob_write;
assign s1_iob_poweron = m_iob_poweron;
assign s1_iob_reset = m_iob_reset;
assign s1_datao_clear = m_datao_clear;
assign s1_datao_set = m_datao_set;
assign s1_cono_clear = m_cono_clear;
assign s1_cono_set = m_cono_set;
assign s1_iob_fm_datai = m_iob_fm_datai;
assign s1_iob_fm_status = m_iob_fm_status;
assign s1_rdi_pulse = m_rdi_pulse;
assign s1_ios = m_ios;
assign s1_iob_write = m_iob_write;
assign s2_iob_poweron = m_iob_poweron;
assign s2_iob_reset = m_iob_reset;
assign s2_datao_clear = m_datao_clear;
assign s2_datao_set = m_datao_set;
assign s2_cono_clear = m_cono_clear;
assign s2_cono_set = m_cono_set;
assign s2_iob_fm_datai = m_iob_fm_datai;
assign s2_iob_fm_status = m_iob_fm_status;
assign s2_rdi_pulse = m_rdi_pulse;
assign s2_ios = m_ios;
assign s2_iob_write = m_iob_write;
assign s3_iob_poweron = m_iob_poweron;
assign s3_iob_reset = m_iob_reset;
assign s3_datao_clear = m_datao_clear;
assign s3_datao_set = m_datao_set;
assign s3_cono_clear = m_cono_clear;
assign s3_cono_set = m_cono_set;
assign s3_iob_fm_datai = m_iob_fm_datai;
assign s3_iob_fm_status = m_iob_fm_status;
assign s3_rdi_pulse = m_rdi_pulse;
assign s3_ios = m_ios;
assign s3_iob_write = m_iob_write;
assign s4_iob_poweron = m_iob_poweron;
assign s4_iob_reset = m_iob_reset;
assign s4_datao_clear = m_datao_clear;
assign s4_datao_set = m_datao_set;
assign s4_cono_clear = m_cono_clear;
assign s4_cono_set = m_cono_set;
assign s4_iob_fm_datai = m_iob_fm_datai;
assign s4_iob_fm_status = m_iob_fm_status;
assign s4_rdi_pulse = m_rdi_pulse;
assign s4_ios = m_ios;
assign s4_iob_write = m_iob_write;
assign s5_iob_poweron = m_iob_poweron;
assign s5_iob_reset = m_iob_reset;
assign s5_datao_clear = m_datao_clear;
assign s5_datao_set = m_datao_set;
assign s5_cono_clear = m_cono_clear;
assign s5_cono_set = m_cono_set;
assign s5_iob_fm_datai = m_iob_fm_datai;
assign s5_iob_fm_status = m_iob_fm_status;
assign s5_rdi_pulse = m_rdi_pulse;
assign s5_ios = m_ios;
assign s5_iob_write = m_iob_write;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_TB_V
`define SKY130_FD_SC_HS__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int manx = 1e5 + 100; const int INF = 0x3f3f3f3f; int main() { int n, a[200], b[200], cnt = 0, numb1 = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i]) cnt++; } for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); if (b[i]) { if (a[i]) cnt--; else numb1++; } } if (!cnt) printf( -1 n ); else printf( %d n , numb1 / cnt + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 1e5 + 10; long long power(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret *= a; a *= a; if (ret >= MOD) ret %= MOD; if (a >= MOD) a %= MOD; b >>= 1; } return ret; } long long invmod(long long x) { return power(x, MOD - 2); } long long dp[55][2]; long long a[55]; long long n; long long go(long long pos, long long check) { if (pos == n + 1) return 0; if (dp[pos][check] != -1) return dp[pos][check]; long long ans = 0; if (check == 0) { ans += max(a[pos] + go(pos + 1, check ^ 1), go(pos + 1, check)); } else { ans += min(go(pos + 1, check ^ 1), a[pos] + go(pos + 1, check)); } dp[pos][check] = ans; return ans; } int32_t main() { cin >> n; long long sum = 0; for (long long i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; } memset(dp, -1, sizeof(dp)); long long k = go(1, 0); cout << sum - k << << k << endl; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable left shift in always block
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
wire [7:0] value;
assign value = var1 << var2;
initial
begin
error = 0;
#1 ;
var1 = 8'h1;
var2 = 8'h0;
#2;
if(value !== 8'h1)
begin
error = 1;
$display ("FAILED - 1 << 0 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h1;
#2;
if(value !== 8'h2)
begin
error = 1;
$display ("FAILED - 1 << 1 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h2;
#2;
if(value !== 8'h4)
begin
error = 1;
$display ("FAILED - 1 << 2 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h3;
#2;
if(value !== 8'h8)
begin
error = 1;
$display ("FAILED - 1 << 3 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h4;
#2;
if(value !== 8'h10)
begin
error = 1;
$display ("FAILED - 1 << 4 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h5;
#2;
if(value !== 8'h20)
begin
error = 1;
$display ("FAILED - 1 << 5 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h6;
#2;
if(value !== 8'h40)
begin
error = 1;
$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h7;
#2;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h7;
#2;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - a5 << 7 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h1;
#2;
if(value !== 8'h4a)
begin
error = 1;
$display ("FAILED - aa << 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int INPUT_MAXCHARS = 1 << 16; char buffer[INPUT_MAXCHARS]; struct FastReader { char *p; FastReader() { fread(buffer, 1, sizeof buffer, stdin); p = buffer; } int next() { int remchars = INPUT_MAXCHARS - (p - buffer); if (remchars < 25) { memcpy(buffer, p, remchars); size_t cnt = fread(buffer + remchars, 1, sizeof buffer - remchars, stdin); if (remchars + cnt < sizeof buffer) { buffer[remchars + cnt] = 0; } p = buffer; } while (*p < 0 ) { ++p; } int val = 0; while (*p >= 0 ) { val = val * 10 + (*p - 0 ); ++p; } return val; } }; const int inf = 1234567890; const int MAXN = 100000; vector<int> arrivals[MAXN]; int arr_idx[MAXN]; vector<pair<int, int> > adj[MAXN]; int best[MAXN]; bool done[MAXN]; int main() { FastReader reader; int n = reader.next(); int m = reader.next(); for (int i = 0; i < m; ++i) { int a = reader.next(); int b = reader.next(); int c = reader.next(); adj[a - 1].push_back(make_pair(b - 1, c)); adj[b - 1].push_back(make_pair(a - 1, c)); } for (int i = 0; i < n; ++i) { int k = reader.next(); arrivals[i].reserve(k + 1); for (int j = 0; j < k; ++j) { int t = reader.next(); arrivals[i].push_back(t); } arrivals[i].push_back(inf); } for (int i = 0; i < n; ++i) { best[i] = inf; } priority_queue<pair<int, int> > PQ; PQ.push(make_pair(0, 0)); best[0] = 0; while (!PQ.empty()) { const pair<int, int> tmp = PQ.top(); PQ.pop(); int t = -tmp.first; int at = tmp.second; if (done[at] || best[at] < t) { continue; } done[at] = true; if (at == n - 1) { printf( %d n , t); return 0; } while (arrivals[at][arr_idx[at]] < t) { ++arr_idx[at]; } if (arrivals[at][arr_idx[at]] == t) { done[at] = false; best[at] = t + 1; PQ.push(make_pair(-t - 1, at)); } else { for (int i = 0; i < (int)adj[at].size(); ++i) { const pair<int, int> e = adj[at][i]; if (t + e.second < best[e.first]) { best[e.first] = t + e.second; PQ.push(make_pair(-best[e.first], e.first)); } } } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; string ans[10] = { , , 2 , 3 , 223 , 5 , 53 , 7 , 7222 , 7332 }; int main() { int n; string s, a = ; cin >> n; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == 0 || s[i] == 1 ) continue; a += ans[(s[i] - 0 )]; } sort(a.begin(), a.end()); reverse(a.begin(), a.end()); cout << a << endl; }
|
`timescale 1ns / 1ps
//File: hsyncModule2015fall.v
//Author: Jianjian Song
//Date: November 1, 2015
//to generate hsync signal and x position coordinate for VGA video display
//Rose-Hulman Institute of Technology
//PixelClock provides the reference time for pixel duration
//Restart is not synchronized with PixelClock
//synch pulse is generated at the end of the line: Active Video-BackPorch-SynchPulse-FrontPorch
//this is how it is done by the video timer of the pong game
// x coordinate has to cover the whole line from 0 to 800 for the game module to work
module hsyncModule(PixelClock, SynchPulse, BackPorch, ActiveVideo, FrontPorch, hsync, LineEnd, xposition, reset, clock);
parameter xresolution=10;
input [xresolution-1:0] SynchPulse, FrontPorch, ActiveVideo, BackPorch;
input PixelClock, reset, clock;
output hsync, LineEnd;
output reg [xresolution-1:0] xposition;
wire [xresolution-1:0] xcount;
ClockedNegativeOneShot PixelClockUnit(PixelClock, PixelClockOneShot, reset, clock);
assign LineEnd=xcount==EndCount; //reset counter
wire [xresolution-1:0] EndCount=SynchPulse+FrontPorch+ActiveVideo+BackPorch;
//synch pulse appears at the end of the line and after front porch to mimic the pong video_timer
//hsync <= ~(xpos > 664 && xpos <= 760); // active for 95 clocks
assign hsync = ~(xcount>=(ActiveVideo+FrontPorch)&&xcount<=(ActiveVideo+FrontPorch+SynchPulse));
always@(xcount, SynchPulse, BackPorch, ActiveVideo, FrontPorch)
xposition<=xcount; //the game circuit does not work if xposition does not run from 0 to 800. JJS
//module UniversalCounter10bitsV5(P,BeginCount, EndCount, Q,S1,S0,TerminalCount, Reset, CLOCK);
UniversalCounter10bitsV5 XPositionCounter(10'd0,10'd0, EndCount, xcount, LineEnd,LineEnd||PixelClockOneShot, , reset, clock) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4000 + 5, mod = 1000000009; int n, x, y; long long P[N], d[N][N]; int main() { scanf( %d , &n); scanf( %d , &x); scanf( %d , &y); for (int i = 0; i <= max(x, y); i++) d[i][0] = 1; for (int i = 1; i <= max(x, y); i++) for (int j = 1; j <= min(n, i); j++) d[i][j] = (d[i - 1][j] + d[i - 1][j - 1]) % mod; P[0] = 1; for (int i = 1; i <= max(x, y); i++) P[i] = (P[i - 1] * i) % mod; long long ans = 0; for (int l = 2; l <= n - 1; l++) for (int r = l; r <= n - 1; r++) ans = (ans + (d[y - 1][r - l] * d[x - 1][n - (r - l + 2)]) % mod) % mod; ans = ans * ((P[x] * P[y]) % mod) % mod; printf( %I64d n , ans); return 0; }
|
`timescale 100 ps / 100 ps
module tb_FFT_Mag();
reg clk, reset, next;
wire next_out;
integer i, j, k, l, m;
reg [15:0] counter;
reg [11:0] in [3:0];
wire [11:0] X0;
wire [11:0] Y0;
wire [11:0] X1;
wire [11:0] Y1;
wire [11:0] X2;
wire [11:0] Y2;
wire [11:0] X3;
wire [11:0] Y3;
reg clrCnt;
assign X0 = in[0];
assign X1 = in[1];
assign X2 = in[2];
assign X3 = in[3];
reg [11:0] input_vector [0:2047];
integer file;
initial clk = 0;
always #10000 clk = ~clk;
wire [11:0] mag1, mag2;
// Instantiate top-level module of core 'X' signals are system inputs
// and 'Y' signals are system outputs
FFT_Mag FFT_Mag_instance (.clk(clk), .reset(reset), .next(next), .next_out(next_out),
.X0(X0), .X1(X1), .X2(X2), .X3(X3), .mag1(mag1), .mag2(mag2));
// You can use this counter to verify that the gap and latency are as expected.
always @(posedge clk) begin
if (clrCnt) counter <= 0;
else counter <= counter+1;
if(counter % 500 == 0)
$display("Counter = %d.", counter);
end
initial begin
@(posedge clk);
@(posedge clk);
// On the next cycle, begin loading input vector.
next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
$readmemb("FFT_Input.txt", input_vector);
for (j=0; j < 2046; j = j+2) begin
in[0] <= input_vector[j];
in[1] <= 0;
in[2] <= input_vector[j+1];
in[3] <= 0;
//output the values read from .txt file
$display("%d, counter = %d", input_vector[j],counter);
$display("%d", input_vector[j+1]);
@(posedge clk);
end
j = 2046;
in[0] <= input_vector[j];
in[1] <= 0;
in[2] <= input_vector[j+1];
in[3] <= 0;
$display("Done input vector, counter = %d", counter);
end
initial begin
// set initial values
in[0] <= 0;
in[1] <= 0;
in[2] <= 0;
in[3] <= 0;
next <= 0;
reset <= 0;
@(posedge clk);
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
// Wait until next_out goes high, then wait one clock cycle and begin receiving data
@(posedge next_out);
@(posedge clk); #1000;
$display("--- begin output ---");
file = $fopen("FFT_output.txt") ;
for(m = 0; m < 1023; m = m + 1) begin
$fdisplay(file, "%b", mag1) ;
$fdisplay(file, "%b", mag2) ;
@(posedge clk); #1000;
end
$fdisplay(file, "%b", mag1) ;
$fdisplay(file, "%b", mag2) ;
$fclose(file) ;
$display("--- done output ---");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { register T sum = 0; register char cc = getchar(); int sym = 1; while (cc != - && (cc > 9 || cc < 0 )) cc = getchar(); if (cc == - ) sym = -1, cc = getchar(); sum = sum * 10 + cc - 0 ; cc = getchar(); while (cc >= 0 && cc <= 9 ) sum = sum * 10 + cc - 0 , cc = getchar(); return sym * sum; } template <typename T> inline T read(T& a) { a = read<T>(); return a; } template <typename T, typename... Others> inline void read(T& a, Others&... b) { a = read(a); read(b...); } int n, ans = 0x7fffffff, b[200010], prim[1000010]; long long a[200010]; set<long long> s; void init() { for (int i = 2; i <= 1000000; i++) { if (!prim[i]) prim[++prim[0]] = i; for (int j = 1; j <= prim[0] && i * prim[j] <= 1000000; j++) { prim[i * prim[j]] = true; if (i % prim[j]) break; } } } void div(long long x) { for (int i = 1; i <= prim[0]; i++) { if (x % prim[i]) continue; s.insert(prim[i]); while (x % prim[i] == 0) x /= prim[i]; } if (x != 1) s.insert(x); } int solve(long long p) { long long res = 0; for (int i = 1; i <= n; i++) { long long d = a[i] < p ? p - a[i] : min(a[i] % p, p - a[i] % p); res = min(1ll * n, res + d); } return res; } int main() { srand(time(NULL)); init(); read(n); for (int i = 1; i <= n; i++) { read(a[i]); b[i] = i; } random_shuffle(b + 1, b + 1 + n); for (int i = 1; i <= 100 && i <= n; i++) { long long t = a[b[i]]; div(t); div(t + 1); if (t > 1) div(t - 1); } for (auto i : s) ans = min(ans, solve(i)); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int n, res = 1e9, a[5][N][N]; void calc(int a[N][N], int b[N][N], int c[N][N], int d[N][N]) { int tmp = 0, tmp2 = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { if (a[i][j] != (i + j) % 2) ++tmp; else ++tmp2; if (c[i][j] != (i + j) % 2) ++tmp; else ++tmp2; if (b[i][j] != (i + j) % 2) ++tmp2; else ++tmp; if (d[i][j] != (i + j) % 2) ++tmp2; else ++tmp; } res = min(res, min(tmp, tmp2)); } int main() { cin >> n; for (int i = 1; i <= 4; ++i) for (int j = 1; j <= n; ++j) for (int k = 1; k <= n; ++k) { char z; cin >> z; a[i][j][k] = (int)(z - 0 ); } vector<int> v; v.push_back(1); v.push_back(2); v.push_back(3); v.push_back(4); do { calc(a[v[0]], a[v[1]], a[v[2]], a[v[3]]); } while (next_permutation(v.begin(), v.end())); cout << res << n ; }
|
#include <bits/stdc++.h> inline int rd(int f = 1, int x = 0, char ch = ) { while (!isdigit(ch = getchar())) if (ch == - ) f = -1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } const int N = 1e5 + 5; int n, a[N], ans; int main() { for (int T = rd(); T--;) { n = rd(), ans = 0; for (int i = 1; i <= n; ++i) a[i] = rd(); for (int i = 2; i <= n; ++i) ans |= a[i - 1] <= a[i]; puts(ans ? YES : NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, s, s1, m, k, sum = 0, l, r, a, a1, p; const int N = 1e5 + 1; int main() { int q; cin >> q; while (q--) { cin >> l >> r; if (l % 2) { if (r % 2) { p = (r / 2) - (l / 2) + 1; s = (l + r) * p; s /= 2; a = l + 1; a1 = r - 1; p--; s1 = (a + a1) * p; s1 /= 2; sum = s1 - s; cout << sum << endl; } else { a1 = r - 1; p = (r / 2) - (l / 2); s = (l + a1) * p; s /= 2; a = l + 1; s1 = (a + r) * p; s1 /= 2; sum = s1 - s; cout << sum << endl; } } else { if (r % 2) { a = l + 1; a1 = r; p = (r / 2) + 1; p = p - (l / 2); s = (a + a1) * p; s /= 2; a1 = r - 1; s1 = (l + a1) * p; s1 /= 2; sum = s1 - s; cout << sum << endl; } else { p = (r / 2) - (l / 2) + 1; s1 = (l + r) * p; s1 /= 2; p--; l++; r--; s = (l + r) * p; s /= 2; sum = s1 - s; cout << sum << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, -1, 0, 1}; const int dx8[] = {-1, 0, 1, 0, 1, 1, -1, -1}; const int dy8[] = {0, -1, 0, 1, 1, -1, 1, -1}; void solve() { long long n; cin >> n; vector<long long> a(n); vector<vector<long long>> dp(n, vector<long long>(n)); vector<vector<long long>> sum(n, vector<long long>(n)); for (long long i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); vector<long long> s(n), l(n); for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (a[i] >= 2 * a[j]) { l[i] = j; s[i]++; } } } for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (j == 0) { dp[i][j] = 1; long long x = i - 1 >= 0 ? sum[i - 1][j] : 0; sum[i][j] = x + dp[i][j]; sum[i][j] %= 998244353; continue; } if (s[i] - j + 1 > 0) { dp[i][j] = (dp[i][j - 1] * (s[i] - j + 1)) % 998244353 + sum[l[i]][j - 1]; dp[i][j] %= 998244353; } else dp[i][j] = 0; long long x = i - 1 >= 0 ? sum[i - 1][j] : 0; sum[i][j] = x + dp[i][j]; sum[i][j] %= 998244353; } } cout << dp[n - 1][n - 1] << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 2e5 + 10; int n; int d[maxn]; int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); d[u]++; d[v]++; } for (int i = 1; i <= n; i++) { if (d[i] == 2) { puts( NO ); return 0; } } puts( YES ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 1) cout << 5; else cout << 25; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_eclbyplog_rs1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_eclbyplog_rs1
// Description: This block implements the bypass logic for a single
// operand. It takes the destination registers of all
// four forwarding sources and the rs. It also has the
// thread for the instruction in each stage and whether
// the instruction writes to the register file. It won't
// bypass if bypass_enable is low or rs =0. This is for the
// special case of rs1 which has two bypass sets. One uses
// the pc as an input (other) and one does not.
*/
module sparc_exu_eclbyplog_rs1 (/*AUTOARG*/
// Outputs
rs_sel_mux1_m, rs_sel_mux1_w, rs_sel_mux1_w2, rs_sel_mux1_other,
rs_sel_mux2_usemux1, rs_sel_mux2_rf, rs_sel_mux2_e,
rs_sel_mux2_ld, rs_sel_longmux_g2, rs_sel_longmux_w2,
rs_sel_longmux_ldxa, ecl_byp_rcc_mux1_sel_m,
ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2,
ecl_byp_rcc_mux1_sel_other, ecl_byp_rcc_mux2_sel_usemux1,
ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_e,
ecl_byp_rcc_mux2_sel_ld,
// Inputs
sehold, use_other, rs, rd_e, rd_m, ecl_irf_rd_w, ld_rd_g,
wb_byplog_rd_w2, wb_byplog_rd_g2, tid_d, thr_match_de,
thr_match_dm, ecl_irf_tid_w, ld_thr_match_dg, wb_byplog_tid_w2,
ld_thr_match_dg2, ifu_exu_kill_e, wb_e, bypass_m,
lsu_exu_dfill_vld_g, bypass_w, wb_byplog_wen_w2, wb_byplog_wen_g2,
ecl_byp_ldxa_g
) ;
input sehold;
input use_other;
input [4:0] rs; // source register
input [4:0] rd_e; // destination regs for all stages
input [4:0] rd_m;
input [4:0] ecl_irf_rd_w;
input [4:0] ld_rd_g;
input [4:0] wb_byplog_rd_w2;
input [4:0] wb_byplog_rd_g2;
input [1:0] tid_d;
input thr_match_de;
input thr_match_dm;
input [1:0] ecl_irf_tid_w;
input ld_thr_match_dg;
input [1:0] wb_byplog_tid_w2;
input ld_thr_match_dg2;
input ifu_exu_kill_e;
input wb_e; // whether each stage writes to reg
input bypass_m; // file
input lsu_exu_dfill_vld_g;
input bypass_w;
input wb_byplog_wen_w2;
input wb_byplog_wen_g2;
input ecl_byp_ldxa_g;
output rs_sel_mux1_m;
output rs_sel_mux1_w;
output rs_sel_mux1_w2;
output rs_sel_mux1_other;
output rs_sel_mux2_usemux1;
output rs_sel_mux2_rf;
output rs_sel_mux2_e;
output rs_sel_mux2_ld;
output rs_sel_longmux_g2;
output rs_sel_longmux_w2;
output rs_sel_longmux_ldxa;
output ecl_byp_rcc_mux1_sel_m;
output ecl_byp_rcc_mux1_sel_w;
output ecl_byp_rcc_mux1_sel_w2;
output ecl_byp_rcc_mux1_sel_other;
output ecl_byp_rcc_mux2_sel_usemux1;
output ecl_byp_rcc_mux2_sel_rf;
output ecl_byp_rcc_mux2_sel_e;
output ecl_byp_rcc_mux2_sel_ld;
wire use_e, use_m, use_w, use_w2, use_rf, use_ld, use_ldxa;
wire match_e, match_m, match_w, match_w2, match_ld; // outputs of comparison
wire match_g2;
wire bypass; // boolean that allows bypassing
wire rs_is_nonzero;
wire rcc_bypass;
// Don't bypass if rs == 0 or we are supposed to use other
assign rs_is_nonzero = rs[0]|rs[1]|rs[2]|rs[3]|rs[4];
assign bypass = rs_is_nonzero & ~use_other & ~sehold;
// Normal pipe priority: E, M, W, RF
// Ld priority: LD, RF
// W2 priority: W2, RF
assign use_e = match_e & wb_e & ~ifu_exu_kill_e;
assign use_m = match_m & bypass_m & ~use_e;
assign use_w = match_w & bypass_w & ~use_m & ~use_e;
assign use_ld = match_ld & lsu_exu_dfill_vld_g & ~ecl_byp_ldxa_g;
assign use_ldxa = match_ld & ecl_byp_ldxa_g;
assign use_w2 = (match_w2 & wb_byplog_wen_w2 | match_g2 & wb_byplog_wen_g2) & ~use_e & ~use_m;
assign use_rf = ~use_w2 & ~use_w & ~use_m & ~use_e & ~use_ld & ~use_ldxa;
// mux1[M, W, W2, OTHER(optional)]
// mux2[mux1, RF, E, LD]
assign rs_sel_mux2_e = (use_e & bypass);
assign rs_sel_mux2_rf = ((use_rf | ~bypass) & ~use_other);
assign rs_sel_mux2_ld = (use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & bypass);
assign rs_sel_mux2_usemux1 = (use_other & ~sehold) | (~rs_sel_mux1_other & ~use_e);
assign rs_sel_mux1_other = ~((use_m | use_w | use_w2 | use_ldxa) & bypass);
assign rs_sel_mux1_w2 = ((use_ldxa | use_w2) & bypass);
assign rs_sel_mux1_w = (use_w & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_mux1_m = (use_m & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_longmux_ldxa = use_ldxa;
assign rs_sel_longmux_g2 = match_g2 & wb_byplog_wen_g2 & ~use_ldxa;
assign rs_sel_longmux_w2 = ~use_ldxa & ~(match_g2 & wb_byplog_wen_g2);
// Bypassing for cc generation (don't use other input)
assign rcc_bypass = rs_is_nonzero;
assign ecl_byp_rcc_mux2_sel_e = use_e & rcc_bypass;
assign ecl_byp_rcc_mux2_sel_rf = use_rf | ~rcc_bypass;
assign ecl_byp_rcc_mux2_sel_ld = use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & rcc_bypass;
assign ecl_byp_rcc_mux2_sel_usemux1 = (use_m | use_w | use_w2 | use_ldxa) & rcc_bypass & ~use_e;
assign ecl_byp_rcc_mux1_sel_other = ~(use_m | use_w | use_w2 | use_ldxa);
assign ecl_byp_rcc_mux1_sel_w2 = use_w2 | use_ldxa;
assign ecl_byp_rcc_mux1_sel_w = use_w & ~use_w2 & ~use_ldxa;
assign ecl_byp_rcc_mux1_sel_m = use_m & ~use_w2 & ~use_ldxa;
// Comparisons
assign match_e = thr_match_de & (rs[4:0] == rd_e[4:0]);
// sparc_exu_eclcomp7 e_comp7(.out(match_e), .in1({tid_d[1:0],rs[4:0]}),
// .in2({ecl_rml_tid_e[1:0],rd_e[4:0]}));
assign match_m = thr_match_dm & (rs[4:0] == rd_m[4:0]);
// sparc_exu_eclcomp7 m_comp7(.out(match_m), .in1({tid_d[1:0],rs[4:0]}),
// .in2({tid_m[1:0],rd_m[4:0]}));
sparc_exu_eclcomp7 w_comp7(.out(match_w), .in1({tid_d[1:0],rs[4:0]}),
.in2({ecl_irf_tid_w[1:0],ecl_irf_rd_w[4:0]}));
sparc_exu_eclcomp7 w2_comp7(.out(match_w2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_w2[1:0],wb_byplog_rd_w2[4:0]}));
assign match_ld = ld_thr_match_dg & (rs[4:0] == ld_rd_g[4:0]);
assign match_g2 = ld_thr_match_dg2 & (rs[4:0] == wb_byplog_rd_g2[4:0]);
/* -----\/----- EXCLUDED -----\/-----
sparc_exu_eclcomp7 ld_comp7(.out(match_ld), .in1({tid_d[1:0],rs[4:0]}),
.in2({ld_tid_g[1:0],ld_rd_g[4:0]}));
sparc_exu_eclcomp7 g2_comp7(.out(match_g2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_g2[1:0],wb_byplog_rd_g2[4:0]}));
-----/\----- EXCLUDED -----/\----- */
endmodule // sparc_exu_eclbyplog
|
#include <bits/stdc++.h> using namespace std; long long n, a, b, c; long long d; long long cnt1, cnt2; long long r; int main() { cin >> n >> a >> b >> c; d = b - c; if (n >= a) { cnt1 = n / a; r = n % a; if (r >= b) cnt1 += (r - b) / d + 1; } if (n >= b) { r = n - b; long long cnt = r / d + 1; cnt2 += cnt; cnt2 += (n - cnt * d) / a; } printf( %lld n , max(cnt1, cnt2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using D = double; using uint = unsigned int; template <typename T> using pair2 = pair<T, T>; const long double pi = acos((ld)-1.0); const int maxn = 1 << 16; complex<double> oddc[maxn], evenc[maxn], tmp[maxn]; complex<double> w[maxn], invw[maxn]; ll odd[maxn], even[maxn]; int oldodd[maxn], oldeven[maxn]; int btr[maxn]; int n, A, mod; int st2; int answer; inline int bitrev(int x) { return btr[x]; } void fft(complex<double> *a, int n, complex<double> *w, complex<double> *res) { for (int i = 0; i < n; i++) res[bitrev(i)] = a[i]; for (int len = 2; len <= n; len *= 2) { int step = n / len; for (int i = 0; i < n; i += len) { int curw = 0; for (int j = 0; j < len / 2; j++) { complex<double> x = res[i + j]; complex<double> y = res[i + len / 2 + j] * w[curw]; res[i + j] = x + y; res[i + len / 2 + j] = x - y; curw += step; } } } } void preparefft(int n) { for (int i = 0; i < n; i++) { int cur = i; for (int j = 0; (1 << j) < n; j++) { btr[i] = (btr[i] << 1) | (cur & 1); cur >>= 1; } } for (int i = 0; i < n; i++) { w[i] = complex<double>(cos(2 * pi / n * i), sin(2 * pi / n * i)); invw[i] = w[i]; } reverse(invw + 1, invw + n); } void conv(ll *from, complex<double> *to) { for (int i = n + 1; i < st2; i++) tmp[i] = 0; for (int i = 0; i <= n; i++) tmp[i] = from[i]; fft(tmp, st2, w, to); } void convback(complex<double> *from, ll *to) { fft(from, st2, invw, tmp); for (int i = 0; i < st2; i++) tmp[i] /= st2; for (int i = 0; i <= n; i++) { to[i] = (ll)(tmp[i].real() + 0.5); assert(abs(tmp[i].imag()) < 0.1); } } void addans() { for (int i = 1; i <= n; i += 2) answer = (answer + odd[i]) % mod; } void go(int A) { if (A == 1) { even[0] = 1; odd[0] = 0; odd[1] = 1; addans(); return; } go(A / 2); for (int i = 0; i <= n; i++) oldodd[i] = odd[i]; for (int i = 0; i <= n; i++) oldeven[i] = even[i]; conv(even, evenc); conv(odd, oddc); for (int i = 0; i < st2; i++) { if ((A / 2) % 2 == 0) { tie(oddc[i], evenc[i]) = make_pair((oddc[i] + evenc[i]) * oddc[i], (oddc[i] + evenc[i]) * (evenc[i] - (complex<double>)1)); } else { tie(evenc[i], oddc[i]) = make_pair((oddc[i] + evenc[i]) * oddc[i], (oddc[i] + evenc[i]) * (evenc[i] - (complex<double>)1)); } } convback(oddc, odd); convback(evenc, even); for (int i = n + 1; i <= 2 * n; i++) { odd[i] = 0; even[i] = 0; } for (int i = 0; i <= n; i++) { odd[i] = (odd[i] + oldodd[i]) % mod; even[i] = (even[i] + oldeven[i]) % mod; } if (A % 2 == 1) { for (int i = n; i >= 1; i--) { odd[i] = (odd[i] + odd[i - 1] + even[i - 1]) % mod; } } addans(); } int main() { cin >> n >> A >> mod; if (A == 1) { cout << 0 << endl; return 0; } st2 = 0; while ((1 << st2) <= n) st2++; st2++; st2 = 1 << st2; preparefft(st2); go(A / 2); cout << answer << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long gcd(long long x, long long y) { return x ? gcd(y % x, x) : y; } const long long mod = 1e9 + 7; inline signed rd() { signed ans = 0; char last = , ch = getchar(); while (!(ch >= 0 && ch <= 9 )) last = ch, ch = getchar(); while (ch >= 0 && ch <= 9 ) ans = ans * 10 + ch - 0 , ch = getchar(); if (last == - ) ans = -ans; return ans; } inline long long QPow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } inline long long QPow(long long a, long long b, const long long &mod) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } long long exgcd(long long a, long long b, long long &x, long long &y) { long long d = a; if (b == 0) x = 1, y = 0; else { d = exgcd(b, a % b, y, x), y -= a / b * x; } return d; } const long double PI = 3.141592653589793115997963468544185161590576171875; const long long maxn = 100005; struct Req { long long s, a, b; bool friend operator<(const Req &a, const Req &b) { return (a.b - a.a) > (b.b - b.a); } } reqs[maxn]; long long arr[maxn]; long long rarr[maxn]; long long cnt[maxn]; signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long t, m, n, R, s; long long k; cin >> n >> s; for (long long i = 1; i <= n; i++) cin >> reqs[i].s >> reqs[i].a >> reqs[i].b; long long ans = 0; long long sum = 0; for (long long i = 1; i <= n; i++) ans += reqs[i].a * reqs[i].s, sum += reqs[i].s; sort(reqs + 1, reqs + 1 + n); for (long long i = 1; i <= n; i++) arr[i] = reqs[i].b - reqs[i].a, cnt[i] = reqs[i].s; for (long long i = 1; i <= n; i++) rarr[i] = arr[n - i + 1]; signed id = 1; while (arr[id] > 0) id++; id--; long long tot = 0; long long tmp = ans; for (long long i = 1; i <= id; i++) { tot += cnt[i]; tmp += arr[i] * cnt[i]; } long long num = (tot + s - 1) / s; num *= s; long long tmp3 = tmp; long long re = sum % s; num -= tot; num -= (s - re) % s; for (long long i = id + 1; i <= n; i++) { if (num <= 0) break; long long tmp1 = min(num, cnt[i]); num -= tmp1; tmp3 += tmp1 * arr[i]; if (num <= 0) break; } num = (tot + s - 1) / s; num *= s; num -= s; long long tmp4 = ans; for (long long i = 1; i <= n; i++) { if (num <= 0) break; long long tmp2 = min(cnt[i], num); num -= tmp2; tmp4 += tmp2 * arr[i]; if (num == 0) break; } ans = max(ans, max(tmp4, tmp3)); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const unsigned long long INF = 1000 * 1000 * 1000; const double eps = 1e-9; int main() { string s; cin >> s; int pos = 0; for (char c = z ; c >= a ; c--) { int tek = pos; for (int i = tek; i < s.size(); i++) if (s[i] == c) { cout << s[i]; pos = i; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 1; int bit[N] = {0}; void update(int x, int val) { for (; x <= N; x += x & (-x)) bit[x] += val; } int query(int x) { int sum = 0; for (; x >= 1; x -= x & (-x)) sum += bit[x]; return sum; } int a[N]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int ans = 0; for (int i = n - 1; i >= 0; i--) { int ele = a[i]; ans += query(a[i]); update(a[i], 1); } int q; cin >> q; while (q--) { int a, b; cin >> a >> b; int r = b - a; int x = r * (r + 1); x /= 2; ans += x; if (ans % 2 == 0) cout << even n ; else cout << odd n ; } return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef (two) with interior not defined
//
`define DOUBLE
module ifdef1;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`endif // NOCODE
`endif // DOUBLE
initial
begin
#1;
error = 0;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int dfn[2100], low[2100], tim, dis[2100], n, i, x, y, M, be[2100], m, j, ans, du[2100]; vector<int> E[2100], e[2100], q; void tarjan(int x, int ff) { dfn[x] = low[x] = ++tim; q.push_back(x); for (int i = 0; i < e[x].size(); ++i) if (e[x][i] != ff) { if (!dfn[e[x][i]]) { tarjan(e[x][i], x); low[x] = min(low[x], low[e[x][i]]); } else low[x] = min(low[x], dfn[e[x][i]]); } if (low[x] == dfn[x]) { ++M; for (;;) { int t = q.back(); q.pop_back(); be[t] = M; if (t == x) break; } } } void dfs(int p, int ff, int dis) { dfn[p] = 1; if (dis > y) y = dis, x = p; for (int i = 0; i < E[p].size(); ++i) if (E[p][i] != ff) dfs(E[p][i], p, dis + 1); } int main() { scanf( %d%d , &n, &m); for (i = 1; i <= m; ++i) { scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } for (i = 1; i <= n; ++i) if (!dfn[i]) tarjan(i, 0); for (i = 1; i <= n; ++i) for (j = 0; j < e[i].size(); ++j) if (be[i] != be[e[i][j]]) E[be[i]].push_back(be[e[i][j]]), du[be[i]]++; memset(dfn, 0, sizeof(dfn)); for (i = 1; i <= M; ++i) { if (!dfn[i]) { y = 0; dfs(i, 0, 1); y = 0; dfs(x, 0, 1); if (y == 1) ans--; else ans += y - 2 - 1; } if (du[i] <= 1) ans++; } printf( %d n , n - ans - 1); }
|
#include <bits/stdc++.h> using namespace std; const int MX = 100000; long long l[MX], a[MX + 1], mn[MX + 1]; char s[MX + 1]; int main() { int n; ignore = scanf( %d , &n); for (int i = 0; i < n; i++) ignore = scanf( %lld , l + i); ignore = scanf( %s , s); long long e = 0, ans = 0; for (int i = 0, p = 5; i < n; i++) { a[i] = e; if (s[i] == G ) { ans += 5 * l[i]; e += l[i]; } else if (s[i] == W ) { ans += 3 * l[i]; e += l[i]; p = 3; } else { long long f = min(l[i], e); ans += l[i] + (l[i] - f) * p; e -= f; } a[i + 1] = e; } auto opt = [&](char c, int t) { mn[n] = a[n]; for (int i = n - 1; i >= 0; i--) mn[i] = min(mn[i + 1], a[i]); long long delta = 0; for (int i = 0; i < n; i++) { if (s[i] == c) { long long x = min(mn[i + 1] - delta, 2 * l[i]); ans -= x * (t - 1) / 2; delta += x; } a[i + 1] -= delta; } }; opt( G , 5); opt( W , 3); printf( %lld n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_TB_V
`define SKY130_FD_SC_HDLL__NOR4B_TB_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
`ifndef VERILATOR
`error "Only Verilator supports PLI-ish DPI calls and sformat conversion."
`endif
import "DPI-C" context dpii_display_call
= function void \$dpii_display (input string formatted /*verilator sformat*/ );
integer a;
initial begin
// Check variable width constant string conversions
$dpii_display("");
$dpii_display("c");
$dpii_display("co");
$dpii_display("cons");
$dpii_display("constant");
$dpii_display("constant_value");
a = $c("10"); // Don't optimize away "a"
$display ("one10=%x",a); // Check single arg
$dpii_display("one10=%x",a);
$display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg
$dpii_display("Mod=%m 16=%d 10=%x",a,a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void setIO() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long double PI = 4 * atan((long double)1); const int INF = 1e9 + 7; const long long _INF = 1e18; int main() { setIO(); int t; cin >> t; while (t--) { int x, k = 0; cin >> x; int y = x; while (y) { y /= 10; k++; } cout << 10 * (x % 10 - 1) + k * (k + 1) / 2 << endl; } }
|
/* Module from the schematic_gui program written by Andreas Ehliar <>
This Verilog file is licensed under the CC0 license. */
module add #(parameter WIREWIDTH = 1) (input wire ci,
input wire [WIREWIDTH:0] op1, op2,
output reg [WIREWIDTH:0] res,
output reg co);
initial begin
$schematic_boundingbox(60,180);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(50,50);
$schematic_coord(50,130);
$schematic_coord(10,170);
$schematic_coord(10,95);
$schematic_coord(15,90);
$schematic_coord(10,85);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(30,29);
$schematic_coord(30,10);
$schematic_lineend;
$schematic_linestart;
$schematic_coord(30,151);
$schematic_coord(30,170);
$schematic_lineend;
$schematic_connector(op1,0,50);
$schematic_connector(op2,0,130);
$schematic_connector(res,60,90);
$schematic_connector(ci,30,0);
$schematic_connector(co,30,180);
end
always @* begin
{co,res} = {1'b0,op1} + {1'b0,op2} + ci;
end
endmodule
|
//--------------------------------------------------------------------------------------------
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.0
// \ \ Application : NULL MGT Tile
// / / Filename : null_pair_example.v
// /___/ /\ Date : 10/07/2005
// \ \ / \
// \___\/\___\
//
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
`timescale 1 ns / 1 ps
module null_pair_example
(
clk,
rx1n,
rx1p,
tx1n,
tx1p
);
input clk;
input [1:0] rx1n;
input [1:0] rx1p;
output [1:0] tx1n;
output [1:0] tx1p;
//-----------------------------------------------------------------
//
// NULL_PAIR wire declarations
//
//-----------------------------------------------------------------
wire clk;
wire [1:0] rx1n;
wire [1:0] rx1p;
wire [1:0] tx1n;
wire [1:0] tx1p;
wire global_sig;
//-----------------------------------------------------------------
//
// NULL_PAIR core instance
//
//-----------------------------------------------------------------
NULL_PAIR null_pair_inst
(
.GREFCLK_IN (global_sig),
.RX1N_IN (rx1n),
.RX1P_IN (rx1p),
.TX1N_OUT (tx1n),
.TX1P_OUT (tx1p)
);
//-----------------------------------------------------------------
//
// GREFCLK_IN port needs to be driven with any global signal
// (any BUFG output, even a BUFG with ground for input will work).
//
//-----------------------------------------------------------------
BUFG global_sig_i
(
.I (clk),
.O (global_sig)
);
endmodule
//-------------------------------------------------------------------
//
// NULL_PAIR core module declaration
//
//-------------------------------------------------------------------
module NULL_PAIR(
GREFCLK_IN,
RX1N_IN,
RX1P_IN,
TX1N_OUT,
TX1P_OUT);
input GREFCLK_IN;
input [1:0] RX1N_IN;
input [1:0] RX1P_IN;
output [1:0] TX1N_OUT;
output [1:0] TX1P_OUT;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: MarioScore24x1
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module is ROM with some fancy strings
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MarioScore24x1 (
input wire [7:0] char_xy,
input wire [3:0] mario_lives,
input wire [3:0] level,
input wire [11:0] coins,
output wire [7:0] char_code
);
reg [7:0] char_code_nxt;
reg [3:0] bcd0, bcd1, bcd2;
reg [3:0] hex1, hex2, hex3, hex4, hex5;
integer i;
always @(coins)
begin
bcd0 = 0;
bcd1 = 0;
bcd2 = 0;
for ( i = 11; i >= 0; i = i - 1 )
begin
if( bcd0 > 4 ) bcd0 = bcd0 + 3;
if( bcd1 > 4 ) bcd1 = bcd1 + 3;
if( bcd2 > 4 ) bcd2 = bcd2 + 3;
{ bcd2[3:0], bcd1[3:0], bcd0[3:0] } =
{ bcd2[2:0], bcd1[3:0], bcd0[3:0],coins[i] };
end
end
always @(*)
begin
case(mario_lives)
0: hex1 = 8'h00;
1: hex1 = 8'h01;
2: hex1 = 8'h02;
3: hex1 = 8'h03;
4: hex1 = 8'h04;
5: hex1 = 8'h05;
6: hex1 = 8'h06;
7: hex1 = 8'h07;
8: hex1 = 8'h08;
9: hex1 = 8'h09;
default: hex1 = 8'h00;
endcase
case(level)
0: hex2 = 8'h00;
1: hex2 = 8'h01;
2: hex2 = 8'h02;
3: hex2 = 8'h03;
4: hex2 = 8'h04;
5: hex2 = 8'h05;
6: hex2 = 8'h06;
7: hex2 = 8'h07;
8: hex2 = 8'h08;
9: hex2 = 8'h09;
default: hex2 = 8'h00;
endcase
case(bcd0)
0: hex3 = 8'h00;
1: hex3 = 8'h01;
2: hex3 = 8'h02;
3: hex3 = 8'h03;
4: hex3 = 8'h04;
5: hex3 = 8'h05;
6: hex3 = 8'h06;
7: hex3 = 8'h07;
8: hex3 = 8'h08;
9: hex3 = 8'h09;
default: hex3 = 8'h00;
endcase
case(bcd1)
0: hex4 = 8'h00;
1: hex4 = 8'h01;
2: hex4 = 8'h02;
3: hex4 = 8'h03;
4: hex4 = 8'h04;
5: hex4 = 8'h05;
6: hex4 = 8'h06;
7: hex4 = 8'h07;
8: hex4 = 8'h08;
9: hex4 = 8'h09;
default: hex4 = 8'h00;
endcase
case(bcd2)
0: hex5 = 8'h00;
1: hex5 = 8'h01;
2: hex5 = 8'h02;
3: hex5 = 8'h03;
4: hex5 = 8'h04;
5: hex5 = 8'h05;
6: hex5 = 8'h06;
7: hex5 = 8'h07;
8: hex5 = 8'h08;
9: hex5 = 8'h09;
default: hex5 = 8'h00;
endcase
end
always @* begin
case(char_xy)
8'h00: char_code_nxt = 8'h0A; // M
8'h01: char_code_nxt = 8'h0B; // A
8'h02: char_code_nxt = 8'h0C; // R
8'h03: char_code_nxt = 8'h0D; // I
8'h04: char_code_nxt = 8'h0E; // O
8'h05: char_code_nxt = 8'h0F; //
8'h06: char_code_nxt = 8'h10; // x
8'h07: char_code_nxt = hex1; // liczba zyc
8'h08: char_code_nxt = 8'h0F; //
8'h09: char_code_nxt = 8'h0F; //
8'h0a: char_code_nxt = 8'h0F; //
8'h0b: char_code_nxt = 8'h0F; //
8'h0c: char_code_nxt = 8'h0F; //
8'h0d: char_code_nxt = 8'h0F; //
8'h0e: char_code_nxt = 8'h0F; //
8'h0f: char_code_nxt = 8'h0F; //
8'h10: char_code_nxt = 8'h0F; //
8'h11: char_code_nxt = 8'h0F; //
8'h12: char_code_nxt = 8'h0F; //
8'h13: char_code_nxt = 8'h0F; //
8'h14: char_code_nxt = 8'h0F; //
8'h15: char_code_nxt = 8'h0F; //
8'h16: char_code_nxt = 8'h0F; //
8'h17: char_code_nxt = 8'h0F; //
8'h18: char_code_nxt = 8'h0F; //
8'h19: char_code_nxt = 8'h0F; //
8'h1a: char_code_nxt = 8'h0F; //
8'h1b: char_code_nxt = 8'h0F; //
8'h1c: char_code_nxt = 8'h0F; //
8'h1d: char_code_nxt = 8'h0F; //
8'h1e: char_code_nxt = 8'h0F; //
8'h1f: char_code_nxt = 8'h0F; //
8'h20: char_code_nxt = 8'h11; // moneta
8'h21: char_code_nxt = 8'h0F; //
8'h22: char_code_nxt = 8'h10; // x
8'h23: char_code_nxt = hex5; // liczba monet
8'h24: char_code_nxt = hex4; // liczba monet
8'h25: char_code_nxt = hex3; // liczba monet
8'h26: char_code_nxt = 8'h0F; //
8'h27: char_code_nxt = 8'h0F; //
8'h28: char_code_nxt = 8'h0F; //
8'h29: char_code_nxt = 8'h0F; //
8'h2a: char_code_nxt = 8'h0F; //
8'h2b: char_code_nxt = 8'h0F; //
8'h2c: char_code_nxt = 8'h0F; //
8'h2d: char_code_nxt = 8'h0F; //
8'h2e: char_code_nxt = 8'h0F; //
8'h2f: char_code_nxt = 8'h0F; //
8'h30: char_code_nxt = 8'h0F; //
8'h31: char_code_nxt = 8'h0F; //
8'h32: char_code_nxt = 8'h0F; //
8'h33: char_code_nxt = 8'h0F; //
8'h34: char_code_nxt = 8'h0F; //
8'h35: char_code_nxt = 8'h0F; //
8'h36: char_code_nxt = 8'h0F; //
8'h37: char_code_nxt = 8'h0F; //
8'h38: char_code_nxt = 8'h0F; //
8'h39: char_code_nxt = 8'h0F; //
8'h3a: char_code_nxt = 8'h0F; //
8'h3b: char_code_nxt = 8'h0F; //
8'h3c: char_code_nxt = 8'h0F; //
8'h3d: char_code_nxt = 8'h0F; //
8'h3e: char_code_nxt = 8'h12; // L
8'h3f: char_code_nxt = 8'h13; // E
8'h40: char_code_nxt = 8'h14; // V
8'h41: char_code_nxt = 8'h13; // E
8'h42: char_code_nxt = 8'h12; // L
8'h43: char_code_nxt = 8'h0F; //
8'h44: char_code_nxt = hex2; // numer levelu
default: char_code_nxt = 8'hff;
endcase
end
assign char_code = char_code_nxt;
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main(signed argc, const char* argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int cnt = 0; for (int i = 0; cnt < n; ++i) { cout << 3 << << i << endl; ++cnt; if (cnt == n) break; if (i % 2) { ++cnt; cout << 0 << << i << endl; } } }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_lvt_reg.v: Multiported-RAM based on register-based binary-coded LVT //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_lvt_reg
#( parameter MEMD = 16, // memory depth
parameter DATAW = 32, // data width
parameter nRPORTS = 2 , // number of reading ports
parameter nWPORTS = 2 , // number of writing ports
parameter RDW = 0 , // new data for Read-During-Write (WAW and RAW are OK in register-based RAM)
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nWPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output reg [DATAW *nRPORTS-1:0] RData); // read data - packed from nRPORTS read ports
localparam ADDRW = `log2(MEMD ); // address width
localparam LVTW = `log2(nWPORTS); // LVT width
// unpacked/pack addresses/data
reg [ADDRW -1:0] WAddr2D [nWPORTS-1:0] ; // write addresses / 2D
reg [DATAW -1:0] WData2D [nWPORTS-1:0] ; // write data / 2D
wire [DATAW*nRPORTS-1:0] RData2Di [nWPORTS-1:0] ; // read data / internal / 2D
reg [DATAW -1:0] RData3Di [nWPORTS-1:0][nRPORTS-1:0]; // read data / internal / 3D
reg [DATAW -1:0] RData2D [nRPORTS-1:0] ; // read data / output / 2D
wire [LVTW *nRPORTS-1:0] RBank ; // read bank selector / 1D
reg [LVTW -1:0] RBank2D [nRPORTS-1:0] ; // read bank selector / 2D
`ARRINIT;
always @* begin
`ARR1D2D(nWPORTS, ADDRW,WAddr ,WAddr2D );
`ARR1D2D(nWPORTS, DATAW,WData ,WData2D );
`ARR2D3D(nWPORTS,nRPORTS,DATAW,RData2Di,RData3Di);
`ARR2D1D(nRPORTS, DATAW,RData2D ,RData );
`ARR1D2D(nRPORTS, LVTW ,RBank ,RBank2D );
end
// instantiate LVT
lvt_reg #( .MEMD (MEMD ), // memory depth
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.RDW (RDW ), // new data for Read-During-Write
.IZERO (IFILE!=""), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE ("" )) // initialization file, optional
lvt_reg_ins ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPORTS-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - in : [ADDRW*nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [ADDRW*nRPORTS-1:0]
.RBank (RBank )); // read bank selector - packed from nRPORTS read ports - out: [LVTW *nRPORTS-1:0]
// generate and instantiate mulriread RAM blocks
genvar wpi;
generate
for (wpi=0 ; wpi<nWPORTS ; wpi=wpi+1) begin: RPORTwpi
// ram_multiread instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.BYPASS (RDW ), // bypass? 0:none; 1:single-stage; 2:two-stages
.IZERO (0 ), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE (wpi?"":IFILE )) // initialization file, optional
mrram_ins ( .clk (clk ), // clock - in
.WEnb (WEnb[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D[wpi] ), // write address (1 port) - in : [ADDRW -1:0]
.WData (WData2D[wpi] ), // write data (1 port) - in : [DATAW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [ADDRW*nRPORTS-1:0]
.RData (RData2Di[wpi])); // read data - packed from nRPORTS read ports - out: [DATAW*nRPORTS-1:0]
end
endgenerate
// combinatorial logic for output muxes
integer i;
always @* for(i=0;i<nRPORTS;i=i+1) RData2D[i] = RData3Di[RBank2D[i]][i];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0)
module t (/*AUTOARG*/);
bit fail;
// IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below.
initial begin
// NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21
$display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
// NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed)
$display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
// NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321
$display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
$display("\n");
`checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21);
`checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730
`checkh( (-4'd1 ** -4'd2), 4'h1);
`checkh( (4'd15 ** 4'd14), 4'h1);
`checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
`checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27)
`checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0
`checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1
`checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b
`checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
`checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug
`checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1
// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug
`checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1
`checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
`checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
if (fail) $stop;
else $write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 110, size = 1 << 20, mod = 998244353, inf = 2e9; const long long INF = 1e15; template <class o> void qr(o& x) { char c = getchar(); x = 0; int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); x *= f; } template <class o> void qw(o x) { if (x / 10) qw(x / 10); putchar(x % 10 + 0 ); } template <class o> void pr1(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar( ); } template <class o> void pr2(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar( n ); } long long gcd(long long a, long long b) { return !a ? b : gcd(b % a, a); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long power(long long a, long long b = mod - 2, long long p = mod) { long long c = 1; while (b) { if (b & 1) c = c * a % p; b /= 2; a = a * a % p; } return c; } template <class o> void cmax(o& x, o y) { if (x < y) x = y; } template <class o> void cmin(o& x, o y) { if (x > y) x = y; } template <typename t1, typename t2> void ad(t1& x, t2 y) { x += y; if (x >= mod) x -= mod; } template <typename t1, typename t2> void dl(t1& x, t2 y) { x -= y; if (x < 0) x += mod; } template <typename T> struct BIT { T* c; int n; BIT(int _n) : n(_n) { c = new T[n]; c--; for (int i = 1; i <= n; i++) c[i] = T(0); } void add(int x, T y) { for (; x <= n; x += x & -x) c[x] = c[x] + y; } T sum(int x) { T y = T(0); for (; x; x &= x - 1) y = y + c[x]; return y; } }; long long jc[N], inv[N]; void jc_init(int n) { jc[0] = 1; for (int i = 1; i <= n; i++) jc[i] = jc[i - 1] * i % mod; inv[n] = power(jc[n]); for (int i = n; i; i--) inv[i - 1] = inv[i] * i % mod; } long long C(int x, int y) { if (x < y || y < 0) return 0; return jc[x] * inv[y] % mod * inv[x - y] % mod; } int n, m; char s[N][N]; void solve() { qr(n); qr(m); vector<vector<pair<int, int> > > v; for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i <= n - 2; i++) for (int j = 1; j <= m; j++) if (s[i][j] == 1 ) { s[i][j] ^= 1; vector<pair<int, int> > o; o.push_back(make_pair(i, j)); o.push_back(make_pair(i + 1, j)); s[i + 1][j] ^= 1; if (j < m) o.push_back(make_pair(i + 1, j + 1)), s[i + 1][j + 1] ^= 1; else o.push_back(make_pair(i + 1, j - 1)), s[i + 1][j - 1] ^= 1; v.push_back(o); assert(((int)o.size()) == 3); } for (int j = 1; j <= m - 2; j++) { vector<pair<int, int> > o; if (s[n][j] == 1 ) o.push_back(make_pair(n, j)), s[n][j] = 0 ; if (s[n - 1][j] == 1 ) o.push_back(make_pair(n - 1, j)), s[n - 1][j] = 0 ; if (((int)o.size())) { o.push_back(make_pair(n, j + 1)); s[n][j + 1] ^= 1; if (((int)o.size()) < 3) o.push_back(make_pair(n - 1, j + 1)), s[n - 1][j + 1] ^= 1; v.push_back(o); } } vector<pair<int, int> > o; char &x = s[n - 1][m - 1], &y = s[n - 1][m], &u = s[n][m - 1], &vv = s[n][m]; if (x == 1 ) o.push_back(make_pair(n - 1, m - 1)), x = 0 ; if (y == 1 ) o.push_back(make_pair(n - 1, m)), y = 0 ; if (((int)o.size())) { for (int j = m - 1; j <= m; j++) if (((int)o.size()) < 3) o.push_back(make_pair(n, j)), s[n][j] ^= 1; v.push_back(o); } o.clear(); if (u == 1 && vv == 1 ) { o.push_back(make_pair(n - 1, m - 1)); o.push_back(make_pair(n - 1, m)); o.push_back(make_pair(n, m)); v.push_back(o); o[2] = make_pair(n, m - 1); v.push_back(o); } else if (u == 1 ) { o.push_back(make_pair(n, m - 1)); o.push_back(make_pair(n - 1, m)); o.push_back(make_pair(n, m)); v.push_back(o); o[0] = make_pair(n - 1, m - 1); o[1] = make_pair(n, m - 1); o[2] = make_pair(n - 1, m); v.push_back(o); o[2] = make_pair(n, m); v.push_back(o); } else if (vv == 1 ) { o.push_back(make_pair(n, m)); o.push_back(make_pair(n - 1, m - 1)); o.push_back(make_pair(n, m - 1)); v.push_back(o); o.clear(); o.push_back(make_pair(n - 1, m - 1)); o.push_back(make_pair(n - 1, m)); o.push_back(make_pair(n, m)); v.push_back(o); o[0] = make_pair(n, m - 1); v.push_back(o); } pr2(((int)v.size())); for (auto i : v) { for (auto j : i) pr1(j.first), pr1(j.second); puts( ); } } int main() { int T = 1; qr(T); while (T--) solve(); return 0; }
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Coq.Logic.Eqdep Coq.Lists.List.
Require Import Omega.
Set Implicit Arguments.
Generalizable All Variables.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => try rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
#include<iostream> #include<cstdio> #include<cstring> #include<algorithm> #include<vector> using namespace std; int n,m; char s[200009],t[200009]; int f[200009],g[200009]; vector<int> p[30]; int main() { scanf( %d%d ,&n,&m); scanf( %s%s ,s+1,t+1); for(int i=1;i<=n;i++) s[i]-= a -1; for(int i=1;i<=m;i++) t[i]-= a -1; for(int i=1;i<=n;i++) p[s[i]].push_back(i); for(int i=1;i<=m;i++) f[i]=*upper_bound(p[t[i]].begin(),p[t[i]].end(),f[i-1]); g[m+1]=n+1; for(int i=m;i>=1;i--) g[i]=*(lower_bound(p[t[i]].begin(),p[t[i]].end(),g[i+1])-1); int ans=0; for(int i=1;i<=m-1;i++) ans=max(ans,g[i+1]-f[i]); printf( %d ,ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, loc[250] = {}, isi[250] = {}, idx = 0; int kosong() { for (int i = 0, _n = (n); i < _n; i++) if (isi[i] == -1) return i; return -111; } int main() { memset(isi, -1, sizeof isi); scanf( %d %d , &n, &m); for (int i = 0, _n = (m); i < _n; i++) { int a; scanf( %d , &a); for (int j = 0, _n = (a); j < _n; j++) { int x; scanf( %d , &x); x--; isi[x] = idx; loc[idx] = x; idx++; } } vector<pair<int, int> > ans; for (int i = 0, _n = (idx); i < _n; i++) if (isi[i] != i) { if (isi[i] == -1) { ans.push_back(make_pair(loc[i], i)); isi[loc[i]] = -1; loc[i] = i; isi[i] = i; } else { int k = kosong(); ans.push_back(make_pair(i, k)); isi[k] = isi[i]; loc[isi[i]] = k; isi[i] = -1; i--; } } printf( %d n , ans.size()); for (int i = 0, _n = (ans.size()); i < _n; i++) printf( %d %d n , ans[i].first + 1, ans[i].second + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[400010]; int a[200]; vector<int> S; vector<int> d, q; int main() { int n; scanf( %d %s , &n, s); for (int i = 0; i < n; i++) a[s[i]]++; int p = 0; for (int i = 0; i < 128; i++) { if (a[i] % 2) p++, a[i]--, S.push_back(i); if (a[i]) { d.push_back(i); q.push_back(a[i]); } } if (p == 0) { int cn = 0; for (int i = 0; i < 128; i++) { while (a[i]) s[cn++] = i, a[i] -= 2; } for (int i = 0; i < cn; i++) s[cn + i] = s[cn - i - 1]; s[n] = 0 ; printf( 1 n%s n , s); } else { int Min = n; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { if (i % 2 && n / i >= p && (n / i - p) % 2 == 0) Min = min(Min, n / i); if (n / i % 2 && i >= p && (i - p) % 2 == 0) Min = min(Min, i); } } printf( %d n , Min); int L = n / Min; int pi = L / 2; int now = 0; for (int i = 0; i < Min; i++) { int x = pi + i * L; if (S.size() > i) s[x] = S[i]; else { while (!q[now]) now++; s[x] = d[now]; S.push_back(d[now]); S.push_back(d[now]); q[now] -= 2; } for (int i = 0; i < L / 2; i++) { while (!q[now]) now++; s[x - i - 1] = d[now]; s[x + i + 1] = d[now]; q[now] -= 2; } } for (int i = 0; i < n; i++) { printf( %c , s[i]); if (i % L == L - 1 && i != n - 1) printf( ); } printf( n ); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:55:41 12/10/2012
// Design Name:
// Module Name: spis
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spis(
input clk,
input rst,
input SCLK,
input SSbar,
input MOSI,
output reg[7:0] dout,
output reg data_present,
input rd
);
reg clear;
always @(posedge clk or posedge rst) begin
if(rst) clear <= 1;
else if(rd) clear <= 1;
else clear <= 0;
end
always @(posedge rst or posedge SCLK) begin
if(rst) dout <= 0;
else if (SSbar==0 & ~data_present) dout <= { dout[6:0] , MOSI};
end
reg data_present_temp;
always @(posedge SSbar or posedge clear) begin
if(clear) data_present_temp <= 0;
else data_present_temp <= 1;
end
always @(posedge clk or posedge rst) begin
if(rst) data_present <= 0;
else data_present <= data_present_temp;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct dato { int i, j, val; }; int main() { int n, m, k; cin >> n >> m >> k; vector<dato> input(k); for (int t = 0; t < k; t++) { dato &d = input[t]; cin >> d.i >> d.j >> d.val; d.i--; d.j--; } long long int p; cin >> p; if (n > m) { for (int t = 0; t < k; t++) { dato &d = input[t]; swap(d.i, d.j); } swap(n, m); } vector<int> numcol(m, 0); vector<int> prodcol(m, 1); for (int t = 0; t < k; t++) { dato &d = input[t]; numcol[d.j]++; prodcol[d.j] *= d.val; } bool error = false; for (int j = 0; j < m and not error; j++) error = numcol[j] == n and prodcol[j] == 1; if (error or n % 2 != m % 2) cout << 0 << endl; else { int numllenas = 0; for (int j = 0; j < m; j++) if (numcol[j] == n) numllenas++; int e = (n - 1) * (m - 1) - k + numllenas; long long int r = 2; long long int a = 1; while (e > 0) { if (e % 2 == 0) { r = (r * r) % p; e /= 2; } else { a = (a * r) % p; e--; } } cout << a << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long b, c, m, n, k, l; cin >> m >> k; l = k; for (int i = 0; i < k; i++) { if (m % 10 == 0) m /= 10; else m--; } cout << m; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void ckmax(T& x, T y) { x = (y > x ? y : x); } template <typename T> inline void ckmin(T& x, T y) { x = (y < x ? y : x); } namespace Fread { const int SIZE = 1 << 21; char buf[SIZE], *S, *T; inline char getchar() { if (S == T) { T = (S = buf) + fread(buf, 1, SIZE, stdin); if (S == T) return EOF; } return *S++; } } // namespace Fread namespace Fwrite { const int SIZE = 1 << 21; char buf[SIZE], *S = buf, *T = buf + SIZE; inline void flush() { fwrite(buf, 1, S - buf, stdout); S = buf; } inline void putchar(char c) { *S++ = c; if (S == T) flush(); } struct NTR { ~NTR() { flush(); } } ztr; } // namespace Fwrite namespace Fastio { struct Reader { template <typename T> Reader& operator>>(T& x) { char c = Fread ::getchar(); T f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = Fread ::getchar(); } x = 0; while (c >= 0 && c <= 9 ) { x = x * 10 + (c - 0 ); c = Fread ::getchar(); } x *= f; return *this; } Reader& operator>>(char& c) { c = Fread ::getchar(); while (c == n || c == ) c = Fread ::getchar(); return *this; } Reader& operator>>(char* str) { int len = 0; char c = Fread ::getchar(); while (c == n || c == ) c = Fread ::getchar(); while (c != n && c != ) { str[len++] = c; c = Fread ::getchar(); } str[len] = 0 ; return *this; } Reader() {} } cin; const char endl = n ; struct Writer { template <typename T> Writer& operator<<(T x) { if (x == 0) { Fwrite ::putchar( 0 ); return *this; } if (x < 0) { Fwrite ::putchar( - ); x = -x; } static int sta[45]; int top = 0; while (x) { sta[++top] = x % 10; x /= 10; } while (top) { Fwrite ::putchar(sta[top] + 0 ); --top; } return *this; } Writer& operator<<(char c) { Fwrite ::putchar(c); return *this; } Writer& operator<<(char* str) { int cur = 0; while (str[cur]) Fwrite ::putchar(str[cur++]); return *this; } Writer& operator<<(const char* str) { int cur = 0; while (str[cur]) Fwrite ::putchar(str[cur++]); return *this; } Writer() {} } cout; } // namespace Fastio const int MAXN = 2e5; int n; void solve_case() { Fastio ::cin >> n; int ans = n; for (int i = n - 1; i >= 1; --i) { ans = (ans + i + 1) / 2; } Fastio ::cout << ans << Fastio ::endl; ans = n; for (int i = n - 1; i >= 1; --i) { Fastio ::cout << ans << << i << Fastio ::endl; ans = (ans + i + 1) / 2; } } int main() { int T; Fastio ::cin >> T; while (T--) { solve_case(); } return 0; }
|
#include <bits/stdc++.h> int main() { long long n, x; int q, i; scanf( %lld %i , &n, &q); while (q--) { scanf( %lld , &x); while (!(x & 1)) { x += (n - (x >> 1)); } printf( %lld n , (x + 1) / 2); } return 0; }
|
#include <bits/stdc++.h> int x[10]; int cp, dp; using namespace std; void print() { for (int i = 0; i < 10; ++i) { cout << x[i]; if (i == 9) cout << n ; else cout << ; } } int pp(char a, int &dp) { if (a == < ) { dp = -1; return -2; } else if (a == > ) { dp = 1; return -2; } else return a - 0 ; } void work(int l, int r, string ch1) { cp = l; dp = 1; int temp; bool ins = true; while (cp >= l && cp <= r) { temp = pp(ch1[cp], dp); if (temp >= 0) { x[temp]++; ch1[cp]--; cp += dp; } else { if (temp == -1) cp += dp; if (temp == -2) { int cpt = cp; cp += dp; if (cp < l || cp > r) break; int temp1 = pp(ch1[cp], dp); while (temp1 == -1) { cp += dp; temp1 = pp(ch1[cp], dp); } if (cp < l || cp > r) break; if (temp1 == -2) ch1[cpt] = 0 - 1; if (temp1 >= 0) x[temp1]++, ch1[cp]--, cp += dp; } } } print(); } int main() { int n, q; string ch; cin >> n >> q; cin >> ch; for (int i = 0; i < q; ++i) { int l, r; cin >> l >> r; l--, r--; memset(x, 0, sizeof(x)); if (l == r) { int pk = ch[l]; if (pk == < || pk == > ) print(); else x[pk - 0 ]++, print(); } else work(l, r, ch); } return 0; }
|
`include "timescale.v"
module fb_rxcounters
(
MRxClk, Reset, MRxDV, RxValid,
StateIdle, StateFFS, StatePreamble, StateData, StateFrmCrc,
MRxDEqDataSoC, TotalRecvNibCntEq0, TotalRecvNibCnt, RxRamAddr, FrmCrcNibCnt, FrmCrcStateEnd
);
input MRxClk;
input Reset;
input MRxDV;
input RxValid;
input StateIdle;
input StateFFS;
input StatePreamble;
input [1:0] StateData;
input StateFrmCrc;
input MRxDEqDataSoC;
output TotalRecvNibCntEq0; // Received Nibble counter = 0
output [15:0] TotalRecvNibCnt; // Received Nibble counter
output [7: 0] RxRamAddr;
output [3: 0] FrmCrcNibCnt;
output FrmCrcStateEnd;
reg [15:0] TotalRecvNibCnt;
reg [7:0] RxRamAddr;
reg [3: 0] FrmCrcNibCnt;
wire ResetTotalRecvNibCnt;
wire IncrementTotalRecvNibCnt;
assign ResetTotalRecvNibCnt = StateIdle & ~MRxDV;
assign IncrementTotalRecvNibCnt = MRxDV ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalRecvNibCnt[15:0] <= 16'd0;
else
begin
if(ResetTotalRecvNibCnt)
TotalRecvNibCnt[15:0] <= 16'd0;
else
if(IncrementTotalRecvNibCnt)
TotalRecvNibCnt[15:0] <= TotalRecvNibCnt[15:0] + 16'd1;
end
end
assign TotalRecvNibCntEq0 = TotalRecvNibCnt == 16'd0;
wire ResetRxRamAddr;
wire IncrementRxRamAddr;
assign ResetRxRamAddr = StateIdle | StateFFS | StatePreamble;
assign IncrementRxRamAddr = RxValid ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxRamAddr[7:0] <= 8'd0;
else
begin
if(ResetRxRamAddr)
RxRamAddr[7:0] <= 8'd0;
else
if(IncrementRxRamAddr)
RxRamAddr[7:0] <= RxRamAddr[7:0] + 8'd1;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateIdle ;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ; // CRC always has two nibbles
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; const int inf = 1e9; int n, l[maxn], c[maxn], ans, cnt, pri[maxn], lst, cur, p[maxn], st[maxn], f[maxn]; bool tf[maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , l + i); for (int i = 1; i <= n; i++) scanf( %d , c + i); for (int i = 2; i <= 100000; i++) { if (!tf[i]) pri[++cnt] = i; for (int j = 1; j <= cnt && i * pri[j] <= 100000; j++) { tf[i * pri[j]] = true; if (i % pri[j] == 0) break; } } ans = inf; for (int i = 1; i <= n; i++) { lst = l[i]; cur = 0; for (int j = 1; j <= cnt && pri[j] * pri[j] <= lst; j++) if (lst % pri[j] == 0) { p[++cur] = pri[j]; while (lst % pri[j] == 0) lst /= pri[j]; } if (lst != 1) p[++cur] = lst; for (int j = 1; j <= n; j++) { st[j] = 0; for (int k = 1; k <= cur; k++) if (l[j] % p[k] == 0) st[j] |= (1 << (k - 1)); } for (int i = 0; i < (1 << 10); i++) f[i] = inf; f[(1 << cur) - 1] = c[i]; for (int i = 1; i <= n; i++) for (int j = 0; j < (1 << cur); j++) f[st[i] & j] = min(f[st[i] & j], f[j] + c[i]); ans = min(ans, f[0]); } if (ans >= inf) printf( -1 n ); else printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_test.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { , } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
//// and Physical Medium Attachment (PMA) sublayer, type ////
//// 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause/Section 36. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module ge_1000baseX_test
(
// --- Resets ---
input reset_pin,
// --- GE 125MHz reference clock ---
input GE_125MHz_ref_ckpin,
// --- FO TBI 125MHz Rx clk ---
input tbi_rx_ckpin,
// --- Fibre-Optic (fo) GE TBI Interface ---
input [9:0] tbi_rxd,
output [9:0] tbi_txd,
// --- GMII interface ---
output [7:0] gmii_rxd,
output gmii_rx_dv,
output gmii_rx_er,
output gmii_col,
output gmii_cs,
input [7:0] gmii_txd,
input gmii_tx_en,
input gmii_tx_er,
// --- Fibre-Optic (fo) ctrl signals ---
output sync_en,
output loop_en,
output prbs_en,
input signal_detect,
input sync,
// --- MDIO interface
inout mdio,
input mdio_ckpin
);
assign sync_en = 1'b0;
assign loop_en = 1'b0;
assign prbs_en = 1'b0;
//----------------------------------------------------------------------------
// MDIO/MDC clock buffering
//----------------------------------------------------------------------------
IBUFG mdio_ckpin_bufi(.I(mdio_ckpin), .O(mdio_ckpin_buf));
BUFG mdio_ck_bufi(.I(mdio_ckpin_buf), .O(mdc));
//----------------------------------------------------------------------------
// GE 125MHz reference clock
//----------------------------------------------------------------------------
IBUFG GE_125MHz_ref_ckpin_bufi(.I(GE_125MHz_ref_ckpin), .O(GE_125MHz_ref_ckpin_buf));
wire GE_125MHz_ref_ck_locked;
DCM #(
.CLKIN_PERIOD(8.0), // Specify period of input clock in ns
.CLKFX_MULTIPLY(5),
.CLKFX_DIVIDE(8)
) GE_125MHz_ref_ck_DCMi(
.CLK0(GE_125MHz_ref_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(GE_125MHz_ref_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(GE_125MHz_ref_ck),
.CLKIN(GE_125MHz_ref_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
//----------------------------------------------------------------------------
// 125MHz refence clock
//----------------------------------------------------------------------------
`ifdef MODEL_TECH
BUFG GE_125MHz_ref_ck_bufi(.I(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck));
`else
BUFGMUX GE_125MHz_ref_ck_bufi(.I1(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck), .S(1'b1));
`endif
//----------------------------------------------------------------------------
// Fibre-Optic (FO) TBI RX clock.
//----------------------------------------------------------------------------
IBUFG tbi_rx_ckpin_bufi(.I(tbi_rx_ckpin), .O(tbi_rx_ckpin_buf));
DCM #(
.CLKIN_PERIOD(8.0)
) tbi_rx_ck_DCMi(
.CLK0(tbi_rx_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(tbi_rx_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(tbi_rx_ck),
.CLKIN(tbi_rx_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
// FO TBI 125MHz rx clock
BUFG tbi_rx_ck_bufi( .I(tbi_rx_ck_unbuf), .O(tbi_rx_ck));
//----------------------------------------------------------------------------
// Reset Cleaners
//----------------------------------------------------------------------------
wire main_clocks_locked = GE_125MHz_ref_ck_locked;
wire tbi_rxck_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset_in = reset_pin | ~main_clocks_locked;
wire mdc_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset, tbi_rx_reset;
clean_rst GE_125MHz_reset_cleaneri(.clk(GE_125MHz_ref_ck), .rsti(GE_125MHz_reset_in), .rsto(GE_125MHz_reset));
clean_rst tbi_rx_reset_cleaneri( .clk(tbi_rx_ck), .rsti(tbi_rxck_reset_in), .rsto(tbi_rx_reset));
clean_rst mdc_reset_cleaneri( .clk(mdc), .rsti(mdc_reset_in), .rsto(mdc_reset));
//-------------------------------------------------------------------------------
// --- IEEE 802.3-2008 1000baseX PCS ---
//-------------------------------------------------------------------------------
ge_1000baseX ge_1000baseX_i(
// --- Clocks ---
.rx_ck(tbi_rx_ck), .tx_ck(GE_125MHz_ref_ck),
// --- resets ---
.tx_reset(GE_125MHz_reset), .rx_reset(tbi_rx_reset),
// --- Startup interface. ---
.startup_enable(~GE_125MHz_reset),
// --- Signal detect from FO transceiver
.signal_detect(signal_detect),
// --- Receive GMII bus ---
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_col(gmii_col),
.gmii_cs(gmii_cs),
// --- Transmit GMII bus ---
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.gmii_txd(gmii_txd),
// --- Receive 8B10B bus ---
.tbi_rxd(tbi_rxd),
// --- Transmit 8B10B bus ---
.tbi_txd(tbi_txd),
// --- Mode of operation ---
.repeater_mode(1'b0),
// --- MDIO interface ---
.mdc_reset(mdc_reset),
.mdc(mdc),
.mdio(mdio)/* synthesis xc_pullup = 1 */
);
endmodule
|
/******************************************************************************
* File Name : jhash_in.v
* Version : 0.1
* Date : 2008 08 29
* Description: jash in module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module jhash_in(/*AUTOARG*/
// Outputs
m_src_getn, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left,
// Inputs
ce, clk, fi, fo_full, m_last, rst, src_empty, stream_ack
);
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output m_src_getn;
input stream_ack;
output [31:0] stream_data0,
stream_data1,
stream_data2;
output stream_valid;
output stream_done;
output [1:0] stream_left;
/*AUTOREG*/
reg pull_n;
assign m_src_getn = ce ? ~(pull_n) : 1'bz;
reg [31:0] stream_data0_n,
stream_data1_n,
stream_data2_n;
reg [2:0] state,
state_n;
reg stream_valid_n;
parameter [2:0]
S_IDLE = 3'b100,
S_RUN_01 = 3'b001,
S_RUN_01_N= 3'b101,
S_RUN_10 = 3'b010,
S_RUN_10_N= 3'b110,
S_DONE = 3'b111;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [1:0] dstart, dstart_n;
reg [31:0] d0, d1,
d0_n, d1_n;
always @(posedge clk)
begin
d0 <= #1 d0_n;
d1 <= #1 d1_n;
dstart <= #1 dstart_n;
end
always @(/*AS*/ce or d0 or d1 or dstart or fi or m_last
or src_empty or state or stream_ack)
begin
state_n = state;
pull_n = 1'b0;
d0_n = d0;
d1_n = d1;
dstart_n = dstart;
case (state)
S_IDLE: if (~src_empty && ce) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10: if (stream_ack) begin
if (~src_empty && ~m_last) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end else
state_n = S_RUN_01_N;
end
S_RUN_01_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end
S_RUN_01: if (stream_ack) begin
if (~src_empty && ~m_last) begin
state_n = S_RUN_10_N;
pull_n = 1'b1;
end if (m_last)
state_n = S_DONE;
end
S_DONE: ;
endcase
end // always @ (...
assign stream_left = dstart;
assign stream_valid= ~state[2] && ~src_empty;
assign stream_data0= d0;
assign stream_data1= state[1] ? d1 : fi[31:00];
assign stream_data2= state[1] ? fi[31:0]: fi[63:32];
assign stream_done = m_last;
endmodule // jhash
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, k1, k2, m1 = INT_MIN, m2 = INT_MIN, tmp; cin >> n >> k1 >> k2; for (long long int i = 0; i < k1; i++) { cin >> tmp; m1 = max(m1, tmp); } for (long long int i = 0; i < k2; i++) { cin >> tmp; m2 = max(m2, tmp); } if (m1 > m2) { cout << YES << endl; } else cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2.5 * 1e5 + 5; int n, m, k; int d[N]; struct Edge { int num; int next; } edge[4 * N]; int tot, last[N]; vector<int> q; vector<int> ans[N]; vector<int> path; int anss; bool flag; void Add(int i, int j) { tot++; edge[tot].num = j; edge[tot].next = last[i]; last[i] = tot; } void dfs(int i, int deep) { if (flag) return; d[i] = deep; q.push_back(i); if (deep > n / k) { flag = 1; for (int j = q.size() - 1; j >= 0; j--) path.push_back(q[j]); return; } bool flag = 0; for (int k = last[i]; k != 0; k = edge[k].next) { int v = edge[k].num; if (d[v] == 0) { dfs(v, deep + 1); flag = 1; } } if (flag == 0) { anss++; int sign1 = 0, sign2 = 0; bool sign = 0; for (int k = last[i]; k != 0; k = edge[k].next) { int v = edge[k].num; if (d[v] + 1 == d[i]) continue; if ((d[i] - d[v]) % 3 == 2) { if (sign1 == 0) sign1 = v; else sign2 = v; } else { for (int k = q.size() - 1; k >= 0; k--) { ans[anss].push_back(q[k]); if (q[k] == v) break; } sign = 1; break; } } if (sign == 0) { bool en = 0; ans[anss].push_back(i); for (int k = q.size() - 1; k >= 0; k--) { if ((q[k] == sign1 || q[k] == sign2) && en == 0) { en = 1; ans[anss].push_back(q[k]); continue; } if (en) ans[anss].push_back(q[k]); if ((q[k] == sign1 || q[k] == sign2) && en == 1) { en = 0; break; } } } } q.pop_back(); } int main() { std::ios::sync_with_stdio(0); cin >> n >> m >> k; for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; Add(u, v); Add(v, u); } dfs(1, 1); if (flag) { cout << PATH n << path.size() << endl; for (int j = path.size() - 1; j >= 0; j--) cout << path[j] << ; } else { cout << CYCLES n ; for (int i = 1; i <= k; i++) { cout << ans[i].size() << endl; ; for (int j = 0; j <= ans[i].size() - 1; j++) cout << ans[i][j] << ; cout << endl; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int maxn = 1e5 + 6; const long long int MOD = 1e9 + 7; vector<int> prim(1000005, 1); int fact[maxn]; long long int binomialCoeff(long long int n, long long int k) { long long int res = 1; if (k > n - k) k = n - k; for (long long int i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); } return res; } bool isVowel(char ch) { if (ch == a || ch == i || ch == e || ch == u || ch == o ) { return true; } return false; } long long int power(long long int x, long long int i, long long int mod) { long long int ans = 1; while (i > 0) { if (i & 1) ans = (ans * x) % mod; i >>= 1; x = (x * x) % mod; } return ans; } long long int modInverse(long long int x, long long int mod) { return power(x, mod - 2, mod); } int nCr(int n, int r) { if (n < r) { return 0; } return (((fact[n] * modInverse(fact[n - r], MOD)) % MOD) * modInverse(fact[r], MOD)) % MOD; } long long int power(int x, unsigned int y) { long long int temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else return x * temp * temp; } void erath(int n) { prim[1] = 0; prim[0] = 0; prim[2] = 1; for (int i = 2; i * i <= n; i++) { if (prim[i]) { for (int j = i * i; j <= n; j += i) { prim[j] = 0; } } } } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int a, long long int b) { return (a / gcd(a, b)) * b; } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int n, m, k; int getmid(int l, int r) { return (l + (r - l) / 2); } struct segtree { int siz; vector<pair<long long int, long long int> > sums; void init(int n) { siz = 1; while (siz < n) siz *= 2; sums.assign(2 * siz, {LONG_MAX, 0}); } void set(int i, int v, int cur, int l, int r) { if (r - l == 1) { sums[cur].first = v; sums[cur].second = 1; return; } int m = getmid(l, r); if (i < m) { set(i, v, 2 * cur + 1, l, m); } else set(i, v, 2 * cur + 2, m, r); sums[cur].first = min(sums[2 * cur + 1].first, sums[2 * cur + 2].first); if (sums[2 * cur + 1].first == sums[cur].first && sums[2 * cur + 2].first == sums[cur].first) { sums[cur].second = sums[cur * 2 + 1].second + sums[cur * 2 + 2].second; } else if (sums[2 * cur + 1].first == sums[cur].first) { sums[cur].second = sums[cur * 2 + 1].second; } else { sums[cur].second = sums[cur * 2 + 2].second; } } void set(int i, int v) { set(i, v, 0, 0, siz); } pair<long long int, long long int> sum(int l, int r, int cur, int lx, int rx) { if (lx >= r || l >= rx) return {LONG_MAX, 0}; if (lx >= l && rx <= r) return {sums[cur].first, sums[cur].second}; int mid = getmid(lx, rx); pair<long long int, long long int> s1 = sum(l, r, 2 * cur + 1, lx, mid), s2 = sum(l, r, 2 * cur + 2, mid, rx); if (s1.first < s2.first) { return s1; } else if (s1.first > s2.first) return s2; else return {s1.first, s1.second + s2.second}; } pair<long long int, long long int> sum(int l, int r) { return sum(l, r, 0, 0, siz); } }; int nCrModp(int n, int r, int p) { if (r > n - r) r = n - r; int C[r + 1]; memset(C, 0, sizeof(C)); C[0] = 1; for (int i = 1; i <= n; i++) { for (int j = min(i, r); j > 0; j--) C[j] = (C[j] + C[j - 1]) % p; } return C[r]; } void ans(int top) { cin >> n >> m >> k; long long int mx = max(n, m), mn = min(m, n); if ((mn + (mx - mn)) > k) { cout << -1 << endl; return; } if (m == n) { long long int add = k + 1 - n; if (add % 2 == 0) add -= 2; cout << (mn - 1 + add) << endl; return; } long long int rem = mx - mn; k -= mn; if (rem & 1) { cout << (mn + k - 1) << endl; } else { if (k & 1) k -= 2; cout << (mn + k) << endl; } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1, co = 1; cin >> t; while (t--) { ans(co); co++; } return 0; }
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// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
wire REN = EN & !WE;
wire WEN = EN & WE;
altsyncram
#(
.width_a (DATA_WIDTH),
.widthad_a (ADDR_WIDTH),
.numwords_a (MEMSIZE),
.outdata_reg_a ((PIPELINED) ? "CLOCK0" : "UNREGISTERED"),
.address_aclr_a ("NONE"),
.outdata_aclr_a ("NONE"),
.indata_aclr_a ("NONE"),
.wrcontrol_aclr_a ("NONE"),
.byteena_aclr_a ("NONE"),
.width_byteena_a (1),
.width_b (1),//
.widthad_b (1),//
.numwords_b (0),//
.rdcontrol_reg_b ("CLOCK1"),//
.address_reg_b ("CLOCK1"),//
.outdata_reg_b ("UNREGISTERED"),//
.outdata_aclr_b ("NONE"),//
.rdcontrol_aclr_b ("NONE"),//
.indata_reg_b ("CLOCK1"),//
.wrcontrol_wraddress_reg_b ("CLOCK1"),//
.byteena_reg_b ("CLOCK1"),//
.indata_aclr_b ("NONE"),//
.wrcontrol_aclr_b ("NONE"),//
.address_aclr_b ("NONE"),//
.byteena_aclr_b ("NONE"),//
.width_byteena_b (1),//
.clock_enable_input_a ("BYPASS"),
.clock_enable_output_a ("BYPASS"),
.clock_enable_input_b ("NORMAL"),//
.clock_enable_output_b ("NORMAL"),//
.clock_enable_core_a ("USE_INPUT_CLKEN"),//
.clock_enable_core_b ("USE_INPUT_CLKEN"),//
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"),
.read_during_write_mode_port_b ("NEW_DATA_NO_NBE_READ"),
.enable_ecc ("FALSE"),//
.width_eccstatus (3),//
.ecc_pipeline_stage_enabled ("FALSE"),//
.operation_mode ("SINGLE_PORT"),
.byte_size (8),//
.read_during_write_mode_mixed_ports ("DONT_CARE"),//
.ram_block_type ("AUTO"),//
.init_file ("UNUSED"),//
.init_file_layout ("UNUSED"),//
.maximum_depth (MEMSIZE), // number of elements in memory
.intended_device_family ("Stratix"),//
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"),
.lpm_type ("altsyncram"),//
.implement_in_les ("OFF"), //
.power_up_uninitialized ("FALSE")
)
RAM
(
.wren_a (WEN),
.rden_a (REN),
.data_a (DI),
.address_a (ADDR),
.clock0 (CLK),
.clocken0 (1'b1),
.clocken1 (1'b1),
.aclr0 (1'b0),
.byteena_a (1'b1),
.addressstall_a (1'b0),
.q_a (DO),
.wren_b (1'b0),
.rden_b (1'b1),
.data_b (1'b1),
.address_b (1'b1),
.clock1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.aclr1 (1'b0),
.byteena_b (1'b1),
.addressstall_b (1'b0),
.q_b (),
.eccstatus ()
);
endmodule // BRAM1
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#include <bits/stdc++.h> using namespace std; const int inf = 1e9; int n, m, dis[55][55], fast[55], slow[55], g1, g2, s1, s2; long long f[55][55][55]; bool cang[55], cans[55], canb[55]; long long work(int g, int b, int su, int sd) { memset(f, 0, sizeof(f)); memset(cang, false, sizeof(cang)); memset(cans, false, sizeof(cans)); memset(canb, false, sizeof(canb)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) { continue; } if (dis[i][j] <= g) { cang[i] = true; } if (dis[i][j] > su && dis[i][j] < sd) { cans[i] = true; } if (dis[i][j] >= b) { canb[i] = true; } } } f[0][0][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= i; j++) { for (int k = 0; j + k <= i; k++) { if (cang[i]) { f[i][j + 1][k] += f[i - 1][j][k]; } if (cans[i]) { f[i][j][k + 1] += f[i - 1][j][k]; } if (canb[i]) { f[i][j][k] += f[i - 1][j][k]; } } } } long long res = 0; for (int i = g1; i <= g2; i++) { for (int j = s1; j <= s2; j++) { res += f[n][i][j]; } } return res; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i < n; i++) { for (int j = i + 1; j <= n; j++) { dis[i][j] = dis[j][i] = inf; } } for (int i = 0; i < m; i++) { int x, y, w; scanf( %d%d%d , &x, &y, &w); dis[x][y] = dis[y][x] = w; } scanf( %d%d%d%d , &g1, &g2, &s1, &s2); for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dis[i][j] = min(dis[i][j], dis[i][k] + dis[k][j]); } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (dis[i][j] < inf) { dis[i][j] = dis[i][j] * n + i; } } } for (int i = 1; i <= n; i++) { fast[i] = inf; slow[i] = -inf; for (int j = 1; j <= n; j++) { if (i == j) { continue; } fast[i] = min(fast[i], dis[i][j]); slow[i] = max(slow[i], dis[i][j]); } } long long ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { ans += work(fast[i], slow[j], fast[i], slow[j]) - work(fast[i] - 1, slow[j], fast[i], slow[j]) - work(fast[i], slow[j] + 1, fast[i], slow[j]) + work(fast[i] - 1, slow[j] + 1, fast[i], slow[j]); } } cout << ans << endl; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : CLOCK_TRNG.v
// /___/ /\ Timestamp : 07/12/2014 01:11:23
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st C:\Users\Siam\Dropbox\PUF\Design_PUF\PUF_Praveen\ipcore_dir\.\CLOCK_TRNG.xaw C:\Users\Siam\Dropbox\PUF\Design_PUF\PUF_Praveen\ipcore_dir\.\CLOCK_TRNG
//Design Name: CLOCK_TRNG
//Device: xc5vlx110t-1ff1136
//
// Module CLOCK_TRNG
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.193 ns
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.221 ns
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT2 = 0.127 ns
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT3 = 0.120 ns
`timescale 1ns / 1ps
module CLOCK_TRNG(CLKIN1_IN,
CLKOUT0_OUT,
CLKOUT1_OUT,
CLKOUT2_OUT,
CLKOUT3_OUT);
input CLKIN1_IN;
output CLKOUT0_OUT;
output CLKOUT1_OUT;
output CLKOUT2_OUT;
output CLKOUT3_OUT;
wire CLKFBOUT_CLKFBIN;
wire CLKIN1_IBUFG;
wire CLKOUT0_BUF;
wire CLKOUT1_BUF;
wire CLKOUT2_BUF;
wire CLKOUT3_BUF;
wire GND_BIT;
wire [4:0] GND_BUS_5;
wire [15:0] GND_BUS_16;
wire VCC_BIT;
assign GND_BIT = 0;
assign GND_BUS_5 = 5'b00000;
assign GND_BUS_16 = 16'b0000000000000000;
assign VCC_BIT = 1;
IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN),
.O(CLKIN1_IBUFG));
BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF),
.O(CLKOUT0_OUT));
BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF),
.O(CLKOUT1_OUT));
BUFG CLKOUT2_BUFG_INST (.I(CLKOUT2_BUF),
.O(CLKOUT2_OUT));
BUFG CLKOUT3_BUFG_INST (.I(CLKOUT3_BUF),
.O(CLKOUT3_OUT));
PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(6.000),
.CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(32), .CLKOUT1_DIVIDE(64),
.CLKOUT2_DIVIDE(4), .CLKOUT3_DIVIDE(3), .CLKOUT0_PHASE(0.000),
.CLKOUT1_PHASE(0.000), .CLKOUT2_PHASE(0.000), .CLKOUT3_PHASE(0.000),
.CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500),
.CLKOUT2_DUTY_CYCLE(0.500), .CLKOUT3_DUTY_CYCLE(0.500),
.COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1),
.CLKFBOUT_MULT(3), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) )
PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN),
.CLKINSEL(VCC_BIT),
.CLKIN1(CLKIN1_IBUFG),
.CLKIN2(GND_BIT),
.DADDR(GND_BUS_5[4:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.REL(GND_BIT),
.RST(GND_BIT),
.CLKFBDCM(),
.CLKFBOUT(CLKFBOUT_CLKFBIN),
.CLKOUTDCM0(),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.CLKOUT0(CLKOUT0_BUF),
.CLKOUT1(CLKOUT1_BUF),
.CLKOUT2(CLKOUT2_BUF),
.CLKOUT3(CLKOUT3_BUF),
.CLKOUT4(),
.CLKOUT5(),
.DO(),
.DRDY(),
.LOCKED());
endmodule
|
// This file is part of Verilog-65c816.
//
// Copyright 2017 by FPGApeeps
//
// Verilog-65c816 is free software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// Verilog-65c816 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with Verilog-65c816. If not, see <http://www.gnu.org/licenses/>.
`include "src/inc/test_ram_defines.v"
`include "src/inc/cpu_defines.v"
`include "src/inc/cpu_enums.v"
module TestBench;
// Parameters
`include "src/inc/generic_params.v"
parameter __counter_msb = 2;
// Test bench variables
reg [__counter_msb:0] __counter;
reg __init_done;
// Connections
reg __clk, __rst;
//reg __half_clk;
//reg __cpu_enable;
wire __cpu_enable;
wire [`CPU_DATA_MSB_POS:0] __cpu_data_in;
wire __cpu_req_rdwr, __cpu_which_rdwr;
wire [`CPU_ACTUAL_ADDR_MSB_POS:0] __cpu_addr;
wire [`CPU_DATA_MSB_POS:0] __cpu_data_out;
wire __ram_we;
wire [`TR_ADDR_MSB_POS:0] __ram_addr;
wire [`TR_DATA_MSB_POS:0] __ram_data_in;
wire [`TR_DATA_MSB_POS:0] __ram_data_out;
wire __ram_data_ready;
// Connect the CPU and RAM together
assign __ram_we = ((__cpu_req_rdwr)
&& (__cpu_which_rdwr == `ENUM__CPU_WH_RDWR__WRITE));
assign __ram_addr = __cpu_addr;
assign __ram_data_in = __cpu_data_out;
assign __cpu_data_in = __ram_data_out;
//assign __cpu_enable = ((!__rst) && (__cpu_req_rdwr
// && __ram_data_ready));
assign __cpu_enable = ((!__rst)
&& (__cpu_req_rdwr ? __ram_data_ready : __true));
initial
begin
__init_done = __false;
__clk = 0;
//__half_clk = 0;
// Reset the CPU
__rst = __true;
//__cpu_enable = __false;
__counter = 0;
end
// Clock signal generators
always
begin
#1 __clk <= !__clk;
//#2 __half_clk <= !__half_clk;
end
// Wait to clear __rst in this test bench.
//
// This always block will stop doing anything important after clearing
// the CPU's rst input.
always @ (posedge __clk)
begin
if (!__counter[__counter_msb])
begin
//__init_done <= __false;
__counter <= __counter + 1;
end
//else if (__counter[__counter_msb] && !__counter[0])
else if (!__init_done)
begin
__init_done <= __true;
__rst <= __false;
//__cpu_enable <= __true;
end
end
always @ (posedge __clk)
begin
end
TestRam ram(.clk(__clk), .we(__ram_we),
.addr(__ram_addr),
.data_in(__ram_data_in),
.data_out(__ram_data_out),
.data_ready(__ram_data_ready));
//Cpu cpu(.clk(__half_clk), .rst(__rst), .enable(__cpu_enable),
// .data_in(__cpu_data_in), .req_rdwr(__cpu_req_rdwr),
// .which_rdwr(__cpu_which_rdwr), .addr(__cpu_addr),
// .data_out(__cpu_data_out));
Cpu cpu(.clk(__clk), .rst(__rst), .enable(__cpu_enable),
.data_in(__cpu_data_in), .req_rdwr(__cpu_req_rdwr),
.which_rdwr(__cpu_which_rdwr), .addr(__cpu_addr),
.data_out(__cpu_data_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; int Read() { char c; while (c = getchar(), (c != - ) && (c < 0 || c > 9 )) ; bool neg = (c == - ); int ret = (neg ? 0 : c - 48); while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + c - 48; return neg ? -ret : ret; } const int MAXN = 300005; const long double eps = 1e-10; struct node { long double l, r, a, b, c, dx, da, db, dc; int fa, son[2]; long double F(long double x) { return (a * x + b) * x + c; } } t[MAXN << 1]; int N, Q, A, B, root, cnt; long double ans[MAXN], apex[MAXN]; inline int CreateNew(long double l, long double r, long double a = 0, long double b = 0, long double c = 0, int c0 = 0, int c1 = 0) { return t[++cnt].l = l, t[cnt].r = r, t[cnt].a = a, t[cnt].b = b, t[cnt].c = c, t[cnt].son[0] = c0, t[cnt].son[1] = c1, cnt; } inline void MarkX(int x, long double dx) { t[x].c += (t[x].a * dx - t[x].b) * dx; t[x].dc += (t[x].da * dx - t[x].db) * dx; t[x].b += -2 * t[x].a * dx, t[x].db += -2 * t[x].da * dx; t[x].l += dx, t[x].r += dx, t[x].dx += dx; } inline void MarkY(int x, long double da, long double db, long double dc) { t[x].a += da, t[x].b += db, t[x].c += dc; t[x].da += da, t[x].db += db, t[x].dc += dc; } inline void Pushdown(int x) { if (t[x].son[0]) MarkX(t[x].son[0], t[x].dx), MarkY(t[x].son[0], t[x].da, t[x].db, t[x].dc); if (t[x].son[1]) MarkX(t[x].son[1], t[x].dx), MarkY(t[x].son[1], t[x].da, t[x].db, t[x].dc); t[x].dx = t[x].da = t[x].db = t[x].dc = 0; } inline void Rotate(int x, int tp) { int y = t[x].fa; Pushdown(y), Pushdown(x); t[y].son[!tp] = t[x].son[tp]; t[x].fa = t[y].fa; if (t[x].son[tp]) t[t[x].son[tp]].fa = y; if (t[y].fa) t[t[y].fa].son[t[t[y].fa].son[1] == y] = x; else root = x; t[y].fa = x, t[x].son[tp] = y; } inline void Splay(int x) { for (Pushdown(x); t[x].fa;) if (t[x].fa == root) Rotate(x, t[t[x].fa].son[0] == x); else { int y = t[x].fa, z = t[y].fa; if (y == t[z].son[0]) if (x == t[y].son[0]) Rotate(y, 1), Rotate(x, 1); else Rotate(x, 0), Rotate(x, 1); else if (x == t[y].son[1]) Rotate(y, 0), Rotate(x, 0); else Rotate(x, 1), Rotate(x, 0); } } inline long double FindOpt(int x) { for (;;) { Pushdown(x); long double opt = min(-t[x].b * 0.5 / t[x].a, (long double)Q); if (opt < t[x].l - eps) if (t[x].son[0]) x = t[x].son[0]; else return Splay(x), t[x].l; else if (opt > t[x].r + eps) if (t[x].son[1]) x = t[x].son[1]; else return Splay(x), t[x].r; else return Splay(x), opt; } } int main() { scanf( %d%d%d%d , &N, &Q, &A, &B); memset(t, 0, sizeof(t)); root = CreateNew(1, Q); for (int i = 1; i <= N; i++) { if (i > 1) { if (A < B) { long double opt = FindOpt(root); apex[i] = opt; int l(t[root].son[0]), r(t[root].son[1]); if (opt - t[root].l > eps) { l = CreateNew(t[root].l, opt, t[root].a, t[root].b, t[root].c, t[root].son[0], 0); if (t[root].son[0]) t[t[root].son[0]].fa = l; t[l].fa = root; } if (t[root].r - opt > eps) { r = CreateNew(opt, t[root].r, t[root].a, t[root].b, t[root].c, 0, t[root].son[1]); if (t[root].son[1]) t[t[root].son[1]].fa = r; t[r].fa = root; } if (l) MarkX(l, A); if (r) MarkX(r, B); t[root].c = t[root].F(opt); t[root].son[0] = l, t[root].son[1] = r, t[root].l = opt + A, t[root].r = opt + B; t[root].a = t[root].b = t[root].da = t[root].db = t[root].dc = t[root].dx = 0; } else MarkX(root, A); } double x = Read(); MarkY(root, 1, -2 * x, x * x); } long double opt = FindOpt(root); double sum = t[root].F(opt); for (int i = N; i >= 1; i--) { ans[i] = opt; if (opt > apex[i] + B) opt -= B; else if (opt < apex[i] + A) opt -= A; else opt = apex[i]; } for (int i = 1; i <= N; i++) printf( %.10f%c , (double)ans[i], i < N ? : n ); printf( %.10f n , sum); return 0; }
|
/*******************************************************************************
* Module: dly01_16
* Date:2014-05-30
* Author: Andrey Filippov
* Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
*
* Copyright (c) 2014 Elphel, Inc.
* dly01_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dly01_16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module dly01_16(
input clk,
input rst,
input [3:0] dly,
input din,
output dout
);
reg [15:0] sr=0;
`ifdef SHREG_SEQUENTIAL_RESET
always @ (posedge clk) begin
sr <= {sr[14:0], din & ~rst};
end
`else
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) sr <=0;
else sr <= {sr[14:0],din};
end
`endif
`ifdef SIMULATION
assign dout = (|sr) ? ((&sr) ? 1'b1 : sr[dly]) : 1'b0 ;
`else
assign dout =sr[dly];
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; unsigned long long sum{}; int cur{1}; for (int i{}; i < m; i++) { int x; cin >> x; if (cur < x) { sum += x - cur; cur = x; } else if (cur > x) { sum += n - cur + x; cur = x; } else continue; } cout << sum; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
`ifndef INCLUDE_ISA
`include "ISA.v"
`endif
module HazardDetect (
input [`WIDTH - 1:0] IR_ID,
input [`WIDTH - 1:0] IR_EXE,
input [`WIDTH - 1:0] IR_MEM,
output reg IsStall_IF,
output reg IsStall_ID
);
wire [4:0] Rs;
wire [4:0] Rt;
assign Rs = IR_ID[20:16];
assign Rt = IR_ID[15:11];
wire [4:0] Rd1;
assign Rd1 = IR_EXE[25:21];
wire [4:0] Rd2;
assign Rd2 = IR_MEM[25:21];
wire [5:0] Op1;
assign Op1 = IR_ID[31:26];
wire [5:0] Op2;
assign Op2 = IR_EXE[31:26];
wire [5:0] Op3;
assign Op3 = IR_MEM[31:26];
always @(IR_ID, IR_MEM, IR_EXE) begin
Stall(0);
if(shouldCheckID(Op1) && shouldCheckEXE(Op2)) begin
if(Rs == Rd1 || Rt == Rd1)
Stall(1);
end else if(shouldCheckID(Op1) && shouldCheckMEM(Op3)) begin
if(Rs == Rd2 || Rt == Rd2)
Stall(1);
end
end
function shouldCheckID(
input [5:0] Op);
begin
case(Op)
`J, `JAL, `NOP, `HALT: shouldCheckID = 0;
default: shouldCheckID = 1;
endcase
end
endfunction
function shouldCheckEXE(
input [5:0] Op);
begin
case(Op)
`J, `JAL, `NOP, `HALT: shouldCheckEXE = 0;
default: shouldCheckEXE = 1;
endcase
end
endfunction
function shouldCheckMEM(
input [5:0] Op);
begin
case(Op)
`J, `JAL, `NOP, `HALT: shouldCheckMEM = 0;
default: shouldCheckMEM = 1;
endcase
end
endfunction
task Stall(input in);
begin
IsStall_ID = in;
IsStall_IF = in;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, crush[100005], ans = -1; bool exi[100005]; long long ms(int o, int x, int p) { if (p > 2 * n) return -1; if (crush[x] == x) return p ? -1 : 0; if ((x == o) && p) return 0; int t = ms(o, crush[x], p + 1); return (t < 0 ? t : t + 1); } long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } long long lcm(long long x, long long y) { return x / gcd(x, y) * y; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &crush[i]); exi[crush[i]] = 1; } for (int i = 1; i <= n; i++) { if (!exi[i]) { ans = -1; break; } long long tmp = ms(i, i, 0); if (tmp <= 0) tmp = 1; tmp /= (2 - (tmp & 1)); ans = ans < 0 ? tmp : lcm(ans, tmp); } cout << ans; return 0; }
|
module top;
reg pass;
reg result;
reg [3:0] expr;
initial begin
pass = 1'b1;
result = $onehot0(1'b0);
if (result != 1) begin
$display("FAILED: for 1'b0 expected 1, got %b", result);
pass = 1'b0;
end
result = $onehot0(1'b1);
if (result != 1) begin
$display("FAILED: for 1'b1 expected 1, got %b", result);
pass = 1'b0;
end
result = $onehot0(2'b01);
if (result != 1) begin
$display("FAILED: for 2'b01 expected 1, got %b", result);
pass = 1'b0;
end
result = $onehot0(4'b0x11);
if (result != 0) begin
$display("FAILED: for 4'b0x11 expected 0, got %b", result);
pass = 1'b0;
end
expr = 4'b1100;
result = $onehot0(expr);
if (result != 0) begin
$display("FAILED: for 4'b1100 expected 0, got %b", result);
pass = 1'b0;
end
result = $onehot0(34'b1100000000000000000000000000000001);
if (result != 0) begin
$display("FAILED: for 34'1100000000000000000000000000000001 expected 0, got %b", result);
pass = 1'b0;
end
result = $onehot0(34'b1000000000000000000000000000000000);
if (result != 1) begin
$display("FAILED: for 34'1000000000000000000000000000000000 expected 1, got %b", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[6005], q[6005]; bool check(int a, int b, int x) { return x > a && x < b; } bool check2(int a, int b, int x) { return x >= a && x <= b; } bool isOK(int a, int b) { return a == b; } int sx[1005], sy[1005]; int main() { int n, t, i, j, a, x, k; memset(p, 0, sizeof p); memset(q, 0, sizeof q); scanf( %d%d , &n, &t); for (i = 0; i < n; ++i) { scanf( %d%d , &x, &a); x *= 2; sx[i] = x - a; sy[i] = x + a; for (j = 6000; j > 0; --j) { k = -j; if (p[j] == -1) continue; if (check2(x - a, x + a, k) || check(x - a, x + a, k - t) || check(x - a, x + a, k + t)) { p[j] = -1; continue; } if (p[j] == 0) { if (isOK(x - a, k + t) || isOK(x + a, k - t)) { p[j] = 1; } } } for (j = 0; j <= 6000; ++j) { k = j; if (q[j] == -1) continue; if (check2(x - a, x + a, k) || check(x - a, x + a, k - t) || check(x - a, x + a, k + t)) { q[j] = -1; continue; } if (q[j] == 0) { if (isOK(x - a, k + t) || isOK(x + a, k - t)) q[j] = 1; } } } for (j = 0, i = 1; i <= 6000; ++i) if (p[i] == 1) { for (k = 0; k < n; ++k) { if (check(-i - t, -i + t, sx[k]) || check(-i - t, -i + t, sy[k])) break; } if (k == n) ++j; } for (i = 0; i <= 6000; ++i) if (q[i] == 1) { for (k = 0; k < n; ++k) { if (check(i - t, i + t, sx[k]) || check(i - t, i + t, sy[k])) break; } if (k == n) ++j; } printf( %d n , j); return 0; }
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sd_wishbone (
input wire clk_50,
input wire reset_n,
// dma bus to MGR
input wire ext_read_act,
output reg ext_read_go,
input wire [31:0] ext_read_addr,
input wire ext_read_stop,
input wire ext_write_act,
output reg ext_write_done,
input wire [31:0] ext_write_addr,
output wire bram_rd_ext_clk,
output reg [6:0] bram_rd_ext_addr,
output reg bram_rd_ext_wren,
output reg [31:0] bram_rd_ext_data,
input wire [31:0] bram_rd_ext_q,
output wire bram_wr_ext_clk,
output reg [6:0] bram_wr_ext_addr,
output wire bram_wr_ext_wren,
output wire [31:0] bram_wr_ext_data,
input wire [31:0] bram_wr_ext_q,
// wishbone bus
output wire wbm_clk_o, // clock - bus clock
output reg [31:0] wbm_adr_o, // addr - bus address
input wire [31:0] wbm_dat_i, // data - write data input
output wire [31:0] wbm_dat_o, // data - write data output
output reg [3:0] wbm_sel_o, // select - 8-bit enable for data bus
output reg wbm_cyc_o, // cycle - valid bus cycle is in progress
output reg wbm_stb_o, // strobe - slave is selected
output reg wbm_we_o, // write - bus cycle is in write mode
input wire wbm_ack_i, // ack - end of a normal bus cycle
output reg [2:0] wbm_cti_o, // cti - cycle type identifier
output reg [1:0] wbm_bte_o // bte - burst type
);
assign wbm_clk_o = clk_50;
assign wbm_dat_o = bram_wr_ext_q;
assign bram_rd_ext_clk = wbm_clk_o;
assign bram_wr_ext_clk = wbm_clk_o;
reg [4:0] state;
parameter [4:0] ST_RESET = 'd0,
ST_IDLE = 'd4,
ST_WB_READ_0 = 'd8,
ST_WB_READ_1 = 'd9,
ST_WB_READ_2 = 'd10,
ST_WB_READ_3 = 'd11,
ST_WB_READ_4 = 'd12,
ST_WB_WRITE_0 = 'd13,
ST_WB_WRITE_1 = 'd14,
ST_WB_WRITE_2 = 'd15,
ST_WB_WRITE_3 = 'd16,
ST_WB_WRITE_4 = 'd17,
ST_LAST = 'd31;
wire [6:0] bram_rd_ext_addr_next = bram_rd_ext_addr + 1'b1;
reg [15:0] bytes_done;
reg [31:0] ext_read_addr_latch;
reg [31:0] ext_write_addr_latch;
reg ext_read_act_last;
reg ext_write_act_last;
reg wbm_ack_i_last;
wire reset_s;
synch_3 a(reset_n, reset_s, clk_50);
always @(posedge wbm_clk_o) begin
ext_read_act_last <= ext_read_act;
ext_write_act_last <= ext_write_act;
wbm_ack_i_last <= wbm_ack_i;
wbm_sel_o <= 4'b1111;
wbm_cyc_o <= 0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
wbm_cti_o <= 3'b000;
wbm_bte_o <= 2'b00;
bram_rd_ext_wren <= 0;
ext_read_go <= 0;
case(state)
ST_RESET: begin
state <= ST_IDLE;
end
ST_IDLE: begin
if(~ext_read_act_last & ext_read_act) begin
ext_read_addr_latch <= ext_read_addr;
bytes_done <= 0;
bram_rd_ext_addr <= -1;
state <= ST_WB_READ_0;
end
if(~ext_write_act_last & ext_write_act) begin
ext_write_addr_latch <= ext_write_addr;
bytes_done <= 0;
bram_wr_ext_addr <= 0;
ext_write_done <= 0;
state <= ST_WB_WRITE_0;
end
end
ST_WB_READ_0: begin
wbm_cyc_o <= 1;
if(~wbm_ack_i) begin
wbm_adr_o <= ext_read_addr_latch * 512 + bram_rd_ext_addr_next * 4;
wbm_stb_o <= 1;
end
if(wbm_ack_i & ~wbm_ack_i_last) begin
// latch incoming data from wishbone slave
bram_rd_ext_addr <= bram_rd_ext_addr_next;
bram_rd_ext_data <= wbm_dat_i;
bram_rd_ext_wren <= 1;
wbm_stb_o <= 0;
bytes_done <= bytes_done + 16'h4;
if(bytes_done + 16'h4 == 512) begin
// done
state <= ST_WB_READ_1;
end
end
end
ST_WB_READ_1: begin
// signal MGR that bram is filled and wait for completion
ext_read_go <= 1;
if(ext_read_stop) state <= ST_IDLE;
end
ST_WB_WRITE_0: begin
wbm_cyc_o <= 1;
wbm_we_o <= 1;
if(~wbm_ack_i) begin
wbm_adr_o <= ext_write_addr_latch * 512 + bram_wr_ext_addr * 4;
wbm_stb_o <= 1;
end
if(wbm_ack_i & ~wbm_ack_i_last) begin
// increment bram read pointer
bram_wr_ext_addr <= bram_wr_ext_addr + 1;
wbm_stb_o <= 0;
bytes_done <= bytes_done + 16'h4;
if(bytes_done + 16'h4 == 512) begin
// done
state <= ST_WB_WRITE_1;
end
end
end
ST_WB_WRITE_1: begin
// signal MGR that bram was read
ext_write_done <= 1;
state <= ST_IDLE;
end
endcase
if(~reset_s) begin
state <= ST_RESET;
end
end
endmodule
|
`ifndef _lineto_v_
`define _lineto_v_
/**
* Bresenham's Line Drawing algorithm.
* Generate straight lines from the current point to the
* destination. x_in/y_in can be reset at any time with the strobe.
*/
module lineto(
input clk,
input reset,
input strobe,
input [BITS-1:0] x_in,
input [BITS-1:0] y_in,
output ready, // set when done
output axis, // did the x or y value change
output [BITS-1:0] x_out,
output [BITS-1:0] y_out
);
parameter BITS = 16;
reg [BITS-1:0] err;
reg [BITS-1:0] x_dst;
reg [BITS-1:0] y_dst;
reg [BITS-1:0] x_out;
reg [BITS-1:0] y_out;
// once the output reaches the dstination, it is ready
// for a new point.
assign ready = (x_dst == x_out) && (y_dst == y_out);
reg axis;
reg sx;
reg sy;
reg signed [BITS-1:0] dx;
reg signed [BITS-1:0] dy;
wire signed [BITS:0] err2 = err << 1;
always @(posedge clk)
begin
//$monitor("%d %d %d %d %d", x_out, y_out, dx, dy, err);
if (reset) begin
// reset will latch the current inputs
x_dst <= x_in;
y_dst <= y_in;
x_out <= x_in;
y_out <= y_in;
err <= 0;
axis <= 0;
end else
if (strobe) begin
x_dst <= x_in;
y_dst <= y_in;
axis <= 0;
if (x_in > x_out) begin
sx <= 1;
dx <= x_in - x_out;
end else begin
sx <= 0;
dx <= x_out - x_in;
end
if (y_in > y_out) begin
sy <= 1;
dy <= y_in - y_out;
end else begin
sy <= 0;
dy <= y_out - y_in;
end
err <= ((x_in > x_out) ? (x_in - x_out) : (x_out - x_in))
-
((y_in > y_out) ? (y_in - y_out) : (y_out - y_in));
end else
if (!ready) begin
// move towards the dstination point
if (err2 > -dy)
begin
err <= err - dy;
x_out <= x_out + (sx ? 1 : -1);
axis <= 0;
end else
if (err2 < dx)
begin
err <= err + dx;
y_out <= y_out + (sy ? 1 : -1);
axis <= 1;
end
end
end
endmodule
`ifdef IVERILOG
module lineto_test;
reg clk = 0;
reg reset = 1;
parameter BITS = 16;
reg strobe = 0;
reg [BITS-1:0] x_in = 0;
reg [BITS-1:0] y_in = 0;
wire ready;
wire [BITS-1:0] x_out;
wire [BITS-1:0] y_out;
always #5 clk = !clk;
always begin
# 50 reset <= 0;
# 50 x_in <= 10000; y_in <= 3000; strobe <= 1;
# 10 strobe <= 0;
# x_in <= 3000; y_in <= 10000; strobe <= 1;
# 10 strobe <= 0;
# x_in <= 3000; y_in <= 3000; strobe <= 1;
# 10 strobe <= 0;
# x_in <= 8000; y_in <= 3000; strobe <= 1;
# 10 strobe <= 0;
# x_in <= 0; y_in <= 0; strobe <= 1;
# 10 strobe <= 0;
# $finish;
end
lineto #(.BITS(BITS)) l_inst(
.clk(clk),
.reset(reset),
.strobe(strobe),
.x_in(x_in),
.y_in(y_in),
.ready(ready),
.x_out(x_out),
.y_out(y_out)
);
initial $monitor("%d %d %d %d", $time, x_out, y_out, ready);
endmodule
`endif
`endif
|
#include <bits/stdc++.h> const int INF = 1e9 + 100; const long long lINF = 4e18; const double EPS = 1e-12; using namespace std; const int N = 5e5 + 100; int n, k, h[N], s[N], mn = INF, mxh[N], should = INF; vector<int> graph[N]; vector<int> can, need; void dfs1(int v, int par = -1, int mx = INF) { mxh[v] = mx; mx = min(mx, h[v]); can.push_back(mx); for (auto j : graph[v]) { if (j != par) dfs1(j, v, mx); } } void dfs2(int v, int par, map<int, int>& ans) { map<int, int> ans2; for (auto j : graph[v]) { if (j != par) { dfs2(j, v, ans2); if (ans.size() < ans2.size()) { swap(ans, ans2); } for (auto k : ans2) { ans[k.first] += k.second; } ans2.clear(); } } if (mxh[v] >= need[0] && h[v] <= should) { bool flag = true; ans[need[0]]++; map<int, int>::reverse_iterator j = ans.rbegin(); for (int i = 0; i < (int)need.size(); i++) { while (j != ans.rend() && j->second == 0) { j++; } if (j == ans.rend() || j->first < need[i]) { flag = false; } else { j->second--; } } if (flag) { mn = min(mn, need[0] - h[v]); } ans.clear(); } else { while (ans.size() > 0 && ans.rbegin()->first > h[v]) { int p = ans.rbegin()->second; ans.erase(ans.rbegin()->first); ans[h[v]] += p; } ans[h[v]]++; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &h[i]); } for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); graph[a].push_back(b); graph[b].push_back(a); } scanf( %d , &k); for (int i = 0; i < k; i++) { scanf( %d , &s[i]); } dfs1(1); sort(s, s + k); reverse(s, s + k); sort((can).begin(), (can).end()); reverse((can).begin(), (can).end()); for (int i = 0, j = 0, delta = 0; i < k; i++) { delta--; while (j < (int)can.size() && can[j] >= s[i]) { j++; delta++; } if (j < i + 1) { should = min(should, s[i] - 1); } if (delta < 0) { need.push_back(s[i]); delta++; } } if (need.size() == 0) { cout << 0 << endl; } else { map<int, int> res; dfs2(1, -1, res); if (mn == INF) { cout << -1 << endl; } else { cout << mn << endl; } } return 0; }
|
// +UEFSHDR---------------------------------------------------------------------
// FILE NAME : sp_rom.v
// AUTHOR : João Carlos Nunes Bittencourt
// AUTHOR'S E-MAIL :
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-02-15 joaocarlos initial version
// -----------------------------------------------------------------------------
// KEYWORDS: memory, rom, single-port, altera
// -----------------------------------------------------------------------------
// PURPOSE: read hexadecimal values stored in a INPUT_FILE.
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy: N/A
// Clock Domains: system clk
// Critical Timing: N/A
// Test Features: N/A
// Asynchronous I/F: N/A
// Instantiations: N/A
// Synthesizable (y/n): y
// Other: N/A
// -UEFSHDR---------------------------------------------------------------------
// Define Input File if it isnt iet
`ifndef ROM_FILE
`define ROM_FILE "rom.out"
`endif
module sp_rom #(
parameter ADDRESS_WIDTH = 16,
parameter DATA_WIDTH = 16
)(
clk,
address, // Address input
data, // Data output
ren, // Read Enable
cen // Chip Enable
) /* synthesis romstyle = "M9K" */;
input clk;
input [ADDRESS_WIDTH-1:0] sink_address;
output [DATA_WIDTH-1:0] src_data;
input sink_ren, sink_cen;
// Specify rom style for ALTERA memory block
(* romstyle = "M9K" *) reg [DATA_WIDTH-1:0] mem [0:(2**ADDRESS_WIDTH)-1] ;
reg [DATA_WIDTH-1:0] src_data;
reg [8*40:1] infile;
initial
begin
$readmemh(`ROM_FILE, mem); // read memory file
data = {DATA_WIDTH{1'b0}};
end
// Funcional read block
always @ (posedge clk)
begin
if (cen && ren)
data <= mem[address];
end
endmodule
// Thats all folks!
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or |(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ^(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xor ^(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:11:35 03/19/2015
// Design Name: fsm2
// Module Name: /home/lsriw/SR/Wojciech Gumula/repo/fsm2/tb_fsm2.v
// Project Name: fsm2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fsm2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module load_file
(
output [7:0] out,
output send
);
integer file;
reg [7:0] c;
reg s;
reg [7:0] i = 0;
initial
begin
file=$fopen("data/input.data", "r");
for(i = 0; i < 16; i = i + 1)
begin
c=$fgetc(file);
s = 1;
#4;
s = 0;
#44;
end
$fclose(file);
end
assign out = c;
assign send = s;
endmodule
module save_file
(
input [7:0] c,
input received
);
integer file;
initial
begin
file=$fopen("data/output.ise", "wb");
repeat (16) begin
@(posedge received);
$fwrite(file, "%c", c);
end
$fwrite(file, "\n");
$fclose(file);
end
endmodule
module tb_fsm2;
// Inputs
reg clk;
reg rst; //reset jest wspólny dla uproszczenia układu
// Outputs
wire rxd;
wire [7:0] data;
wire [7:0] data_out;
wire received;
// Instantiate the Unit Under Test (UUT)
fsm2 uut (
.clk(clk),
.rst(rst),
.rxd(rxd),
.data(data_out),
.received(received)
);
fsm serial (
.clk(clk),
.send(send),
.data(data),
.txd(rxd),
.rst(rst)
);
load_file load (
.out(data),
.send(send)
);
save_file save (
.c(data_out),
.received(received)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
end
always #2 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); string s; cin >> s; long long i; bool flag = true; for (i = 0; i < s.length(); i++) { if (s[i] == 0 ) { s.erase(i, 1); flag = false; break; } } if (flag) { s.erase(s.begin()); } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long int n, max = 0; cin >> n; map<string, long long int> m; string s; while (n--) { cin >> s; m[s]++; } for (auto it = m.begin(); it != m.end(); it++) { if (it->second > max) { max = it->second; s = it->first; } } cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; char s1[200100], s2[200100]; vector<int> pos[26]; long long sum1[27][200100]; long long sum2[27][200100]; int main() { int n; scanf( %d , &n); long long res2 = 0; for (int i = (1); i < (n + 1); ++i) res2 += (n - i + 1) * 1ll * (n - i + 1); scanf( %s%s , &s1, &s2); for (int i = (0); i < (n); ++i) pos[s2[i] - A ].push_back(i); for (int i = (0); i < (26); ++i) { for (int j = (0); j < (pos[i].size()); ++j) { sum1[i][j] += pos[i][j] + 1; if (j) sum1[i][j] += sum1[i][j - 1]; } for (int j = (int)pos[i].size() - 1; j >= 0; --j) { sum2[i][j] += n - pos[i][j]; if (j != (int)pos[i].size() - 1) sum2[i][j] += sum2[i][j + 1]; } } double res1 = 0; for (int i = (0); i < (n); ++i) { int v = s1[i] - A ; int l = 0; int r = (int)pos[v].size() - 1; int best = -1; while (l <= r) { int m = (l + r) / 2; if (pos[v][m] <= i) { best = m; l = m + 1; } else r = m - 1; } if (best != -1) res1 += (sum1[v][best]) * 1ll * (n - i); if (res1 < 0) cout << FAIL << endl; best++; if (best != pos[v].size()) res1 += (sum2[v][best]) * 1ll * (i + 1); if (res1 < 0) cout << FAIL << endl; } double res = res1 / (double)res2; printf( %.15lf n , res); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:22:31 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.250000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(12.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter2.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module prog_counter2tb();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
prog_counter2 pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#19
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module MC6502Accumulator(
i_a,
i_m,
i_c,
i_d,
i_s,
o_a,
o_n,
o_z,
o_c,
o_v);
input [7:0] i_a;
input [7:0] i_m;
input i_c;
input i_d;
input i_s;
output [7:0] o_a;
output o_n;
output o_z;
output o_c;
output o_v;
wire [7:0] w_m;
wire [4:0] w_bsum_lo;
wire [4:0] w_dsum_lo;
wire [4:0] w_bsum_hi;
wire [4:0] w_dsum_hi;
wire [4:0] w_sum_low;
wire [4:0] w_sum_high;
wire w_dover_lo;
wire w_carry;
wire [3:0] w_fix;
assign w_m = i_s ? ~i_m : i_m;
assign w_fix = i_s ? 4'ha : 4'h6;
assign w_bsum_lo = i_a[3:0] + w_m[3:0] + { 3'b000, i_c };
assign w_dover_lo = w_bsum_lo > 5'h9;
assign w_dsum_lo = w_dover_lo ? (w_bsum_lo + w_fix) : w_bsum_lo;
assign w_sum_low = i_d ? w_dsum_lo : w_bsum_lo;
assign w_carry = i_d ? w_dover_lo ^ i_s : w_sum_low[4];
assign w_bsum_hi = i_a[7:4] + w_m[7:4] + { 3'b000, w_carry };
assign w_dsum_hi = (w_bsum_hi[3:0] < 4'ha) ? w_bsum_hi : (w_bsum_hi + w_fix);
assign w_sum_high = i_d ? w_dsum_hi : w_bsum_hi;
assign o_a = { w_sum_high[3:0], w_sum_low[3:0] };
assign o_n = o_a[7];
assign o_z = o_a == 8'h00;
assign o_c = w_sum_high[4];
assign o_v = (!(i_a[7] ^ w_m[7]) & (i_a[7] ^ o_a[7]));
endmodule // MC6502Accumulator
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode
//
// This file is part of PVS.
//
// PVS is free software: you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the Free Software
// Foundation, either version 3 of the License, or (at your option) any later
// version.
//
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// PVS. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns / 1 ns
// receives mode to switch via serial
// bit order:
// first 15-bits: SA_rest (little-endian)
// next 1-bit: pace_en
// next 14-bits: AV_forw (little-endian)
// next 1-bit: PACen
// next 1-bit: PVCen
// total: 32-bits, 4 byte transmission
// DEFAULT CONFIGURATION
// SA_rest = 700
// pace_en = 1
// AV_forw = 200
// PACen = 0
// PVCen = 0
// KEEP IN MIND THE VHM DOES NOT REGISTER THESE INPUTS! (so this should!)
module mode_setter
(
clk_fast,
clk_slow,
rx,
recv_pulse,
pace_en,
SA_rest,
AV_forw,
PACen,
PVCen,
);
//////////// INPUTS & OUTPUTS ////////////
input clk_fast;
input clk_slow;
input rx;
output recv_pulse;
output pace_en;
output [15:0] SA_rest;
output [15:0] AV_forw;
output PACen;
output PVCen;
//////////// PARAMETERS ////////////
parameter s_idle = 1'b0;
parameter s_out = 1'b1;
parameter CLOCK_RATIO = 16'd33334; // 50MHz / 1.5kHz
parameter NUM_BYTES = 4'd4; // two for SA_rest, two for AV_forw
//////////// SIGNALS & REGS ////////////
wire [7:0] recv_data; // data from receiver
wire recv_data_ready; // data ready from receiver (1 clock pulse)
reg [7:0] recv_data_reg; // data latched from reg
reg state; // state machine for determining if output is ready
reg recv_pulse_reg = 1'b0; // output ready pulse, used for reset by heart
reg [15:0] SA_rest_reg = 16'd900; // DEFAULT CASE
reg [15:0] SA_rest_temp_reg = 16'd900;
reg pace_en_reg = 1'b1; // DEFAULT CASE
reg pace_en_temp_reg = 1'b1;
reg [15:0] AV_forw_reg = 16'd50; // DEFAULT CASE
reg [15:0] AV_forw_temp_reg = 16'd50;
reg PACen_reg = 1'd0; // DEFAULT CASE
reg PACen_temp_reg = 1'd0;
reg PVCen_reg = 1'd0; // DEFAULT CASE
reg PVCen_temp_reg = 1'd0;
reg [15:0] cnt = 16'd0; // counter to keep signals stable
reg [3:0] byte_cnt = 4'd0; // cnt of bytes received so far
//////////// LOGIC ////////////
async_receiver receiver
(
.clk(clk_fast),
.RxD(rx),
.RxD_data_ready(recv_data_ready),
.RxD_data(recv_data),
//.RxD_endofpacket,
//.RxD_idle
);
always @(posedge clk_fast) begin
case(state)
s_idle:
begin
state <= (byte_cnt >= NUM_BYTES) ? s_out : s_idle;
// recv_pulse, PACen, and PVCen should only be 1 cycle wide
recv_pulse_reg <= 1'b0;
PACen_reg <= 1'b0;
PVCen_reg <= 1'b0;
// = instead of <= on purpose from here
recv_data_reg = recv_data;
if (recv_data_ready && byte_cnt == 4'd0) begin
SA_rest_temp_reg[7:0] = recv_data_reg;
end
else if (recv_data_ready && byte_cnt == 4'd1) begin
SA_rest_temp_reg[14:8] = recv_data_reg[6:0];
SA_rest_temp_reg[15] = 1'b0;
pace_en_temp_reg = recv_data_reg[7];
end
else if (recv_data_ready && byte_cnt == 4'd2) begin
AV_forw_temp_reg[7:0] = recv_data_reg;
end
else if (recv_data_ready && byte_cnt == 4'd3) begin
AV_forw_temp_reg[15:8] = {2'b0,recv_data_reg[5:0]};
PACen_temp_reg = recv_data_reg[6];
PVCen_temp_reg = recv_data_reg[7];
end
cnt <= 16'd0;
if (recv_data_ready)
byte_cnt <= byte_cnt + 4'd1;
end
s_out:
begin
state <= (cnt >= CLOCK_RATIO) ? s_idle : s_out;
recv_pulse_reg <= 1'b1;
SA_rest_reg <= SA_rest_temp_reg;
pace_en_reg <= pace_en_temp_reg;
AV_forw_reg <= AV_forw_temp_reg;
PACen_reg <= PACen_temp_reg;
PVCen_reg <= PVCen_temp_reg;
cnt <= cnt + 16'd1;
byte_cnt <= 4'd0;
end
endcase
end
//////////// OUTPUT ASSIGNS ////////////
assign recv_pulse = recv_pulse_reg;
assign pace_en = pace_en_reg;
assign SA_rest = SA_rest_reg;
assign AV_forw = AV_forw_reg;
assign PACen = PACen_reg;
assign PVCen = PVCen_reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_TB_V
`define SKY130_FD_SC_MS__OR2B_TB_V
/**
* or2b: 2-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__or2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_TB_V
|
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