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/*
* This program tests the synthesis of small memories, including
* aysnchronous read w/ synchronous write.
*/
module main;
reg [1:0] mem;
reg D;
reg rst, clk, wr, wadr, radr;
/*
* This implements the synchronous write port to the memory.
* Asynchronous reset? In this case, yes, even though that is
* not normally the case for RAM devices.
*/
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
if (rst) begin
mem[0] <= 0;
mem[1] <= 0;
end else if (wr) begin
mem[wadr] <= D;
end else begin
end
/* This is the asynchronous read port from the memory. */
wire Q = mem[radr];
(* ivl_synthesis_off *)
initial begin
rst = 0;
clk = 0;
wadr = 0;
radr = 0;
wr = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure reset works.
rst = 1;
#1 if (mem[0] !== 0 || mem[1] !== 0) begin
$display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
$finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
radr = 1;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure memory remembers value.
if (mem[0] !== 0 || mem[1] !== 0) begin
$display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
$finish;
end
D = 1;
wr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
D = 0;
wadr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
wr = 0;
D = 1;
// Make sure memory remembers written values.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 9; int a[N], b[N]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; int ok = 1; if (a[1] != b[1]) ok = 0; map<int, int> cnt; cnt[a[1]]++; for (int i = 2; i <= n; i++) { if (a[i] < b[i] && cnt[1] == 0) ok = 0; if (a[i] > b[i] && cnt[-1] == 0) ok = 0; cnt[a[i]] = 1; } if (ok) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int M[52][52]; int main() { int n; cin >> n; for (int i = 0; i < n * (n - 1) / 2 - 1; i++) { int a, b; cin >> a >> b; a--, b--; M[a][b]++; } int _x = -1, _y = -1, x, y; bool enc = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { for (int k = 0; k < n; k++) { if ((M[i][j] == 0) && (M[j][i] == 0) && (i != j)) { x = i + 1; y = j + 1; } if ((M[i][j] == 1) && (M[j][k] == 1) && (M[i][k] == 0)) { _x = i + 1; _y = k + 1; enc = 1; } } } } if (enc) { cout << _x << << _y << endl; } else { cout << x << << y << endl; } }
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#include <bits/stdc++.h> using namespace std; void DBG() { cerr << endl; } template <class Head, class... Tail> void DBG(Head H, Tail... T) { cerr << << H; DBG(T...); } using ll = long long; using ld = long double; template <class T> using vec = vector<T>; template <class... Args> inline void read(Args&... args) { ((cin >> args), ...); } template <class... Args> inline void show(Args... args) { ((cout << args << ), ...); } template <class T1, class T2> inline bool ckmin(T1& a, T2 b) { return a > b ? a = b, 1 : 0; } template <class T1, class T2> inline bool ckmax(T1& a, T2 b) { return a < b ? a = b, 1 : 0; } template <class T> inline void operator>>(istream& in, vector<T>& v) { for (auto i = 0; i < int(v.size()); i++) in >> v[i]; } template <class T> inline void operator<<(ostream& out, const vector<T>& v) { for (auto i = 0; i < int(v.size()); i++) out << v[i] << n [i + 1 == int(v.size())]; } const int MOD = 7340033; ll dp[31][4][1001]; void solve() { int n, k; read(n, k); function<ll(int, int, int)> F = [&](int part, int idx, int rem) { if (part == 0 || idx == 4) return rem == 0 ? 1ll : 0ll; if (idx == 0 && rem == 0) return 1ll; if (~dp[part][idx][rem]) return dp[part][idx][rem]; ll cnt = 0; int new_rem = idx == 0 ? rem - 1 : rem; for (auto i = 0; i < new_rem + 1; i++) { cnt += F(part, idx + 1, i) * F(part - 1, 0, new_rem - i); cnt %= MOD; } return dp[part][idx][rem] = cnt; }; int part = 0; while (n > 1 && n % 2) n /= 2, part++; cout << F(part, 0, k) << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(12); cerr << fixed << setprecision(12); memset(dp, -1, sizeof(dp)); int _ = 1; cin >> _; for (auto i = 1; i < _ + 1; i++) { solve(); } return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_window (clock, reset, enable, start_event, test_expr, end_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event, test_expr, end_event;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WINDOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_window_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_window_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_window_psl_logic.v"
`else
`endmodule // ovl_window
`endif
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 1e5 + 10; long long power(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret *= a; a *= a; if (ret >= MOD) ret %= MOD; if (a >= MOD) a %= MOD; b >>= 1; } return ret; } long long invmod(long long x) { return power(x, MOD - 2); } long long dp[55][2]; long long a[55]; long long n; long long go(long long pos, long long check) { if (pos == n + 1) return 0; if (dp[pos][check] != -1) return dp[pos][check]; long long ans = 0; if (check == 0) { ans += max(a[pos] + go(pos + 1, check ^ 1), go(pos + 1, check)); } else { ans += min(go(pos + 1, check ^ 1), a[pos] + go(pos + 1, check)); } dp[pos][check] = ans; return ans; } long long go1(long long pos, long long check) { if (pos == n + 1) return 0; if (dp[pos][check] != -1) return dp[pos][check]; long long ans = 0; if (check == 0) { ans += min(go1(pos + 1, check ^ 1), a[pos] + go1(pos + 1, check)); } else { ans += max(a[pos] + go1(pos + 1, check ^ 1), go1(pos + 1, check)); } dp[pos][check] = ans; return ans; } int32_t main() { cin >> n; long long sum = 0; for (long long i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; } memset(dp, -1, sizeof(dp)); long long k = go1(1, 0); cout << k << << sum - k << endl; }
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#include <bits/stdc++.h> using namespace std; void imprimirVector(vector<long long> v) { if (!v.empty()) { int p = v.size(); cout << [ ; for (int i = 0; i < (int)(p - 1); i++) cout << v[i] << , ; cout << v[p - 1] << ] << endl; } else cout << [] << endl; } long long toNumber(string s) { long long Number; if (!(istringstream(s) >> Number)) Number = 0; return Number; } string toString(long long number) { ostringstream ostr; ostr << number; return ostr.str(); } int main() { ios_base::sync_with_stdio(0); unsigned long long n; cin >> n; cout << (n * (n - 1) * (n - 2) * (n - 3) * (n - 4) / 120) * n * (n - 1) * (n - 2) * (n - 3) * (n - 4) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 7; long long a[N]; long long l[N]; long long r[N]; int32_t main() { long long ans = 0, n, i; for (i = 1, scanf( %I64d , &n); i <= n; scanf( %I64d , &a[i++])) ; for (i = 1; i <= n; l[i] = r[i] = i, i++) ; for (i = 2; i <= n; i++) { long long num = i; while (num > 1 && a[num - 1] <= a[i]) num = l[num - 1]; l[i] = num; } for (i = n - 1; i >= 1; i--) { long long num = i; while (num < n && a[num + 1] < a[i]) num = r[num + 1]; r[i] = num; } for (i = 1; i <= n; ans += (i - l[i] + 1) * (r[i] - i + 1) * a[i], i++) ; for (i = 1; i <= n; l[i] = r[i] = i, i++) ; for (i = 2; i <= n; i++) { long long num = i; while (num > 1 && a[num - 1] >= a[i]) num = l[num - 1]; l[i] = num; } for (i = n - 1; i >= 1; i--) { long long num = i; while (num < n && a[num + 1] > a[i]) num = r[num + 1]; r[i] = num; } for (i = 1; i <= n; i++) { ans -= (i - l[i] + 1) * (r[i] - i + 1) * a[i]; } printf( %I64d n , ans); }
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#include <bits/stdc++.h> using namespace std; const int MN = 200000, INF = 1100000000; int main() { int n; scanf( %d , &n); static int x1[MN], y1[MN], x2[MN], y2[MN]; for (int i = 0; i < n; i++) { scanf( %d%d%d%d , x1 + i, y1 + i, x2 + i, y2 + i); } static int x1l[MN], y1l[MN], x2l[MN], y2l[MN]; x1l[0] = y1l[0] = -INF; x2l[0] = y2l[0] = INF; for (int i = 0; i < n; i++) { x1l[i + 1] = max(x1l[i], x1[i]); y1l[i + 1] = max(y1l[i], y1[i]); x2l[i + 1] = min(x2l[i], x2[i]); y2l[i + 1] = min(y2l[i], y2[i]); } static int x1r[MN], y1r[MN], x2r[MN], y2r[MN]; x1r[n] = y1r[n] = -INF; x2r[n] = y2r[n] = INF; for (int i = n - 1; i >= 0; i--) { x1r[i] = max(x1r[i + 1], x1[i]); y1r[i] = max(y1r[i + 1], y1[i]); x2r[i] = min(x2r[i + 1], x2[i]); y2r[i] = min(y2r[i + 1], y2[i]); } for (int i = 0; i < n; i++) { int X1 = max(x1l[i], x1r[i + 1]); int Y1 = max(y1l[i], y1r[i + 1]); int X2 = min(x2l[i], x2r[i + 1]); int Y2 = min(y2l[i], y2r[i + 1]); if (X1 <= X2 && Y1 <= Y2) { printf( %d %d n , X1, Y1); break; } } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_1_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_1_V
|
#include <bits/stdc++.h> using namespace std; int abso(int a, int b) { if (a < b) return b - a; else return a - b; } long long power(long long x, long long e) { long long temp; if (e == 0) return 1; if (e % 2 == 0) { temp = power(x, e / 2); return temp * temp; } else { temp = power(x, e / 2); return temp * temp * x; } } bool cmp(pair<pair<int, int>, int> x, pair<pair<int, int>, int> y) { if (x.first.first == y.first.first) { if (x.first.second == y.first.second) return x.second < y.second; else return x.first.second > y.first.second; } return x.first.first > y.first.first; } bool cmp1(pair<int, int> x, pair<int, int> y) { if (x.second == y.second) return x.first < y.first; return x.second < y.second; } int main() { int n; cin >> n; string str; cin >> str; int arr[n + 1]; for (int i = 1; i <= n; i++) cin >> arr[i]; int cur = 1; int visit[n + 1]; memset(visit, 0, sizeof visit); int flag = 0, next; visit[cur] = 1; while (1) { if (str[cur - 1] == < ) { next = cur - arr[cur]; if (next < 1) { flag = 1; break; } else { if (visit[next] == 1) { flag = 2; break; } else { visit[next] = 1; cur = next; } } } else { next = cur + arr[cur]; if (next > n) { flag = 1; break; } else { if (visit[next] == 1) { flag = 2; break; } else { visit[next] = 1; cur = next; } } } } if (flag == 1) cout << FINITE << endl; else cout << INFINITE << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_PP_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_PP_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: obc_lower.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module obc_lower (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:02:13 12/18/2014
// Design Name:
// Module Name: MUX8_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX8_1(
input [2:0] address,
//Ports inside
output reg rd_en0,
output reg rd_en1,
output reg rd_en2,
output reg rd_en3,
output reg rd_en4,
output reg rd_en5,
output reg rd_en6,
output reg rd_en7,
input [127:0] dout0,
input [127:0] dout1,
input [127:0] dout2,
input [127:0] dout3,
input [127:0] dout4,
input [127:0] dout5,
input [127:0] dout6,
input [127:0] dout7,
input empty0,
input empty1,
input empty2,
input empty3,
input empty4,
input empty5,
input empty6,
input empty7,
//Ports with scheduler module
input rd_en,
output reg empty,
output reg [127:0] dout
);
always@(*)
begin
case(address)
3'h0:begin
rd_en0=rd_en;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty0;
dout = dout0;
end
3'h1:begin
rd_en0=1'b0;
rd_en1=rd_en;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty1;
dout = dout1;
end
3'h2:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=rd_en;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty2;
dout = dout2;
end
3'h3:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=rd_en;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty3;
dout = dout3;
end
3'h4:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=rd_en;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty4;
dout = dout4;
end
3'h5:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=rd_en;
rd_en6=1'b0;
rd_en7=1'b0;
empty=empty5;
dout = dout5;
end
3'h6:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=rd_en;
rd_en7=1'b0;
empty=empty6;
dout = dout6;
end
3'h7:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=rd_en;
empty=empty7;
dout = dout7;
end
default:begin
rd_en0=1'b0;
rd_en1=1'b0;
rd_en2=1'b0;
rd_en3=1'b0;
rd_en4=1'b0;
rd_en5=1'b0;
rd_en6=1'b0;
rd_en7=1'b0;
empty =1'b1;
dout =128'b0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:19:01 03/29/2015
// Design Name: regfileparam
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW2/regfileparam_test.v
// Project Name: HW2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: regfileparam
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module regfileparam_test;
// Inputs
reg [3:0] ra;
reg [3:0] rb;
reg [3:0] rw;
reg [15:0] wdat;
reg wren;
reg clk;
reg rst;
// Outputs
wire [15:0] adat, adat2;
wire [15:0] bdat, bdat2;
wire [15:0] acompare;
wire [15:0] bcompare;
assign acompare = adat ^ adat2;
assign bcompare = bdat ^ bdat2;
// Instantiate the Unit Under Test (UUT)
regfileparam #(.BITSIZE(16), .ADDSIZE(4)) uut (
.adat(adat),
.bdat(bdat),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
// Instantiate the Unit Under Test (UUT)
regfileparam_behav #(.BITSIZE(16), .ADDSIZE(4)) uut2 (
.adat(adat2),
.bdat(bdat2),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
integer i;
always begin
clk = 1;
#10;
clk = 0;
#10;
end
initial begin
// Initialize Inputs
$display($time,,,"Simulation is started.");
ra = 0;
rb = 0;
rw = 0;
wdat = 0;
wren = 0;
rst = 0;
#10 rst = 1;
$display($time,,,"Reset is Asserted");
#15;
// First read from each location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"Now we will write to each register location some random data.");
#20;
// Write to each location.
for(i=0; i<16; i=i+1) begin
rw = i; wren = 1; wdat = $random;
#20; // Progress time.
$display($time,,,"Write Address = %d, Written Value = %d", rw, wdat);
end
$display($time,,,"Now we will read from each register location the data that we have written from each port.");
#20;
// Now Read Again From Each Location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"End of Simulation.");
#20;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, tmp; bool b; cin >> n >> m; vector<int> t(n, -1); while (m--) { cin >> tmp; t[tmp - 1]++; } m = 1000; for (int i = 0; i < n; i++) { m = min(m, t[i]); } cout << m + 1; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V
|
module PIO32(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_gpio_writedata,
output [31:0] avs_gpio_readdata,
input [2:0] avs_gpio_address,
input [3:0] avs_gpio_byteenable,
input avs_gpio_write,
input avs_gpio_read,
output avs_gpio_waitrequest,
inout coe_P0,
inout coe_P1,
inout coe_P2,
inout coe_P3,
inout coe_P4,
inout coe_P5,
inout coe_P6,
inout coe_P7,
inout coe_P8,
inout coe_P9,
inout coe_P10,
inout coe_P11,
inout coe_P12,
inout coe_P13,
inout coe_P14,
inout coe_P15,
inout coe_P16,
inout coe_P17,
inout coe_P18,
inout coe_P19,
inout coe_P20,
inout coe_P21,
inout coe_P22,
inout coe_P23,
inout coe_P24,
inout coe_P25,
inout coe_P26,
inout coe_P27,
inout coe_P28,
inout coe_P29,
inout coe_P30,
inout coe_P31
);
reg [31:0] io_data;
reg [31:0] io_out_en;
reg [31:0] read_data;
assign avs_gpio_readdata = read_data;
assign avs_gpio_waitrequest = 1'b0;
assign coe_P0 = (io_out_en[0]) ? io_data[0] : 1'bz;
assign coe_P1 = (io_out_en[1]) ? io_data[1] : 1'bz;
assign coe_P2 = (io_out_en[2]) ? io_data[2] : 1'bz;
assign coe_P3 = (io_out_en[3]) ? io_data[3] : 1'bz;
assign coe_P4 = (io_out_en[4]) ? io_data[4] : 1'bz;
assign coe_P5 = (io_out_en[5]) ? io_data[5] : 1'bz;
assign coe_P6 = (io_out_en[6]) ? io_data[6] : 1'bz;
assign coe_P7 = (io_out_en[7]) ? io_data[7] : 1'bz;
assign coe_P8 = (io_out_en[8]) ? io_data[8] : 1'bz;
assign coe_P9 = (io_out_en[9]) ? io_data[9] : 1'bz;
assign coe_P10 = (io_out_en[10]) ? io_data[10] : 1'bz;
assign coe_P11 = (io_out_en[11]) ? io_data[11] : 1'bz;
assign coe_P12 = (io_out_en[12]) ? io_data[12] : 1'bz;
assign coe_P13 = (io_out_en[13]) ? io_data[13] : 1'bz;
assign coe_P14 = (io_out_en[14]) ? io_data[14] : 1'bz;
assign coe_P15 = (io_out_en[15]) ? io_data[15] : 1'bz;
assign coe_P16 = (io_out_en[16]) ? io_data[16] : 1'bz;
assign coe_P17 = (io_out_en[17]) ? io_data[17] : 1'bz;
assign coe_P18 = (io_out_en[18]) ? io_data[18] : 1'bz;
assign coe_P19 = (io_out_en[19]) ? io_data[19] : 1'bz;
assign coe_P20 = (io_out_en[20]) ? io_data[20] : 1'bz;
assign coe_P21 = (io_out_en[21]) ? io_data[21] : 1'bz;
assign coe_P22 = (io_out_en[22]) ? io_data[22] : 1'bz;
assign coe_P23 = (io_out_en[23]) ? io_data[23] : 1'bz;
assign coe_P24 = (io_out_en[24]) ? io_data[24] : 1'bz;
assign coe_P25 = (io_out_en[25]) ? io_data[25] : 1'bz;
assign coe_P26 = (io_out_en[26]) ? io_data[26] : 1'bz;
assign coe_P27 = (io_out_en[27]) ? io_data[27] : 1'bz;
assign coe_P28 = (io_out_en[28]) ? io_data[28] : 1'bz;
assign coe_P29 = (io_out_en[29]) ? io_data[29] : 1'bz;
assign coe_P30 = (io_out_en[30]) ? io_data[30] : 1'bz;
assign coe_P31 = (io_out_en[31]) ? io_data[31] : 1'bz;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_gpio_address)
// 0: read_data <= 8;
// 1: read_data <= 32'hEA680001;
2: read_data <= {coe_P31, coe_P30, coe_P29, coe_P28, coe_P27, coe_P26, coe_P25, coe_P24,coe_P23, coe_P22, coe_P21, coe_P20, coe_P19, coe_P18, coe_P17, coe_P16,
coe_P15, coe_P14, coe_P13, coe_P12, coe_P11, coe_P10, coe_P9, coe_P8, coe_P7, coe_P6, coe_P5, coe_P4, coe_P3, coe_P2, coe_P1, coe_P0};
4: read_data <= io_out_en;
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_data <= 0;
io_out_en <= 0;
end
else begin
if(avs_gpio_write) begin
case(avs_gpio_address)
2: begin
io_data <= avs_gpio_writedata;
end
4: begin
io_out_en <= avs_gpio_writedata;
end
default: begin end
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int bs(int a[], int l, int u, int x) { int m, p = -1; while (l <= u) { m = (l + u) / 2; if (a[m] == x || (a[m] < x && m + 1 <= u && a[m + 1] >= x)) return m; else if (a[m] < x) { p = m; l = m + 1; } else { u = m - 1; } } return p; } int gc(int a, int b) { if (!a) return b; return gc(b % a, a); } bool isP(unsigned long long int x) { if (x == 2) return true; if (x % 2 == 0 || x <= 1) return false; for (int i = 3; i <= sqrt(x); i += 2) { if ((x % i) == 0) return false; } return true; } int main() { int n, j, g, g1, pre, i, uc, f4, l, v, li, ri, a4, e1, ind, t3, n9, t, r, f, c1, p, p1, p3, y, x, z, t1, t2, t3n, m, k; int a[100000]; unordered_map<string, int> mp; priority_queue<pair<int, int>> pq; int ty = 0, ty1; set<int> st; set<int> sto; ty = INT_MAX; g = 0; vector<int> ar; cin >> n >> k; for (i = 0; i < n; i++) { cin >> a[i]; g += a[i]; } f = 1; if (g % k != 0) cout << No n ; else { g1 = 0; ind = 0; for (i = 0; i < n; i++) { g1 += a[i]; ind++; if (g1 == (g / k)) { ar.push_back(ind); g1 = 0; ind = 0; } else if (g1 > (g / k)) { f = 0; cout << No n ; break; } } if (f) { cout << Yes n ; for (i = 0; i < ar.size(); i++) cout << ar[i] << ; cout << n ; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5; const long long int inf64 = 1e18 + 5; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, i; pair<long long int, long long int> fr; cin >> n; vector<pair<long long int, long long int> > v; cin >> fr.first >> fr.second; for (i = 0; i < n - 1; i++) { long long int a, b; cin >> a >> b; v.push_back({a, b}); } sort(v.begin(), v.end(), greater<pair<long long int, long long int> >()); int ans = 0; for (i = 0; i < n - 1; i++) { if (v[i].first <= fr.first) break; ++ans; } priority_queue<long long int, vector<long long int>, greater<long long int> > pq; for (int i = 0, j = 0; i < v.size(); i = j) { while (j < v.size() && v[j].first > fr.first) { pq.push(v[j].second - v[j].first + 1); ++j; } if (pq.empty()) break; ans = min(ans, (int)pq.size()); long long int p = pq.top(); if (p > fr.first) break; pq.pop(); fr.first -= p; } ans = min(ans, (int)pq.size()); while (!pq.empty() && fr.first >= pq.top()) { fr.first -= pq.top(); pq.pop(); ans = min(ans, (int)pq.size()); } cout << ans + 1; }
|
`timescale 1ns / 1ps
/*
* File : EXMEM_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Execute and Memory stages.
*/
module EXMEM_Stage(
input clock,
input reset,
input EX_Flush,
input EX_Stall,
input M_Stall,
// Control Signals
input EX_Movn,
input EX_Movz,
input EX_BZero,
input EX_RegWrite, // Future Control to WB
input EX_MemtoReg, // Future Control to WB
input EX_ReverseEndian,
input EX_LLSC,
input EX_MemRead,
input EX_MemWrite,
input EX_MemByte,
input EX_MemHalf,
input EX_MemSignExtend,
input EX_Left,
input EX_Right,
// Exception Control/Info
input EX_KernelMode,
input [31:0] EX_RestartPC,
input EX_IsBDS,
input EX_Trap,
input EX_TrapCond,
input EX_M_CanErr,
// Data Signals
input [31:0] EX_ALU_Result,
input [31:0] EX_ReadData2,
input [4:0] EX_RtRd,
// Voter Signals for Registers
input M_RegWrite,
input M_MemtoReg,
input M_ReverseEndian,
input M_LLSC,
input M_MemRead,
input M_MemWrite,
input M_MemByte,
input M_MemHalf,
input M_MemSignExtend,
input M_Left,
input M_Right,
input M_KernelMode,
input [31:0] M_RestartPC,
input M_IsBDS,
input M_Trap,
input M_TrapCond,
input M_M_CanErr,
input [31:0] M_ALU_Result,
input [31:0] M_ReadData2,
input [4:0] M_RtRd,
output reg vote_M_RegWrite,
output reg vote_M_MemtoReg,
output reg vote_M_ReverseEndian,
output reg vote_M_LLSC,
output reg vote_M_MemRead,
output reg vote_M_MemWrite,
output reg vote_M_MemByte,
output reg vote_M_MemHalf,
output reg vote_M_MemSignExtend,
output reg vote_M_Left,
output reg vote_M_Right,
output reg vote_M_KernelMode,
output reg [31:0] vote_M_RestartPC,
output reg vote_M_IsBDS,
output reg vote_M_Trap,
output reg vote_M_TrapCond,
output reg vote_M_M_CanErr,
output reg [31:0] vote_M_ALU_Result,
output reg [31:0] vote_M_ReadData2,
output reg [4:0] vote_M_RtRd
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
// Mask of RegWrite if a Move Conditional failed.
wire MovcRegWrite = (EX_Movn & ~EX_BZero) | (EX_Movz & EX_BZero);
always @(posedge clock) begin
vote_M_RegWrite <= (reset) ? 1'b0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 1'b0 : ((EX_Movn | EX_Movz) ? MovcRegWrite : EX_RegWrite)));
vote_M_MemtoReg <= (reset) ? 1'b0 : ((M_Stall) ? M_MemtoReg : EX_MemtoReg);
vote_M_ReverseEndian <= (reset) ? 1'b0 : ((M_Stall) ? M_ReverseEndian : EX_ReverseEndian);
vote_M_LLSC <= (reset) ? 1'b0 : ((M_Stall) ? M_LLSC : EX_LLSC);
vote_M_MemRead <= (reset) ? 1'b0 : ((M_Stall) ? M_MemRead : ((EX_Stall | EX_Flush) ? 1'b0 : EX_MemRead));
vote_M_MemWrite <= (reset) ? 1'b0 : ((M_Stall) ? M_MemWrite : ((EX_Stall | EX_Flush) ? 1'b0 : EX_MemWrite));
vote_M_MemByte <= (reset) ? 1'b0 : ((M_Stall) ? M_MemByte : EX_MemByte);
vote_M_MemHalf <= (reset) ? 1'b0 : ((M_Stall) ? M_MemHalf : EX_MemHalf);
vote_M_MemSignExtend <= (reset) ? 1'b0 : ((M_Stall) ? M_MemSignExtend : EX_MemSignExtend);
vote_M_Left <= (reset) ? 1'b0 : ((M_Stall) ? M_Left : EX_Left);
vote_M_Right <= (reset) ? 1'b0 : ((M_Stall) ? M_Right : EX_Right);
vote_M_KernelMode <= (reset) ? 1'b0 : ((M_Stall) ? M_KernelMode : EX_KernelMode);
vote_M_RestartPC <= (reset) ? 32'b0 : ((M_Stall) ? M_RestartPC : EX_RestartPC);
vote_M_IsBDS <= (reset) ? 1'b0 : ((M_Stall) ? M_IsBDS : EX_IsBDS);
vote_M_Trap <= (reset) ? 1'b0 : ((M_Stall) ? M_Trap : ((EX_Stall | EX_Flush) ? 1'b0 : EX_Trap));
vote_M_TrapCond <= (reset) ? 1'b0 : ((M_Stall) ? M_TrapCond : EX_TrapCond);
vote_M_M_CanErr <= (reset) ? 1'b0 : ((M_Stall) ? M_M_CanErr : ((EX_Stall | EX_Flush) ? 1'b0 : EX_M_CanErr));
vote_M_ALU_Result <= (reset) ? 32'b0 : ((M_Stall) ? M_ALU_Result : EX_ALU_Result);
vote_M_ReadData2 <= (reset) ? 32'b0 : ((M_Stall) ? M_ReadData2 : EX_ReadData2);
vote_M_RtRd <= (reset) ? 5'b0 : ((M_Stall) ? M_RtRd : EX_RtRd);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; long long arr[200010]; long long factorial[200010]; long long factinv[200010]; long long fact[200010]; long long ans; long long pw(long long a, long long b) { a %= 1000000007; if (b == 0) { return 1ll; } if (b == 1) { return a; } long long res = pw(a, b / 2); if (b % 2) { return (((res * res) % 1000000007) * a) % 1000000007; } return (res * res) % 1000000007; } long long inv(long long a) { return pw(a, 1000000007 - 2); } long long choose(long long a, long long b) { return ((factorial[a] * factinv[b] % 1000000007) * factinv[a - b]) % 1000000007; } int32_t main() { ios_base::sync_with_stdio(false); if (fopen( cf815b.in , r )) { freopen( cf815b.in , r , stdin); freopen( cf815b.out , w , stdout); } cin >> N; for (int i = 0; i < N; i++) { cin >> arr[i]; arr[i] %= 1000000007; } factorial[0] = 1; for (int i = 1; i <= N; i++) { factorial[i] = factorial[i - 1] * i; factorial[i] %= 1000000007; } for (int i = 0; i <= N; i++) { factinv[i] = inv(factorial[i]); } if (N % 4 == 0) { long long choosev = (N - 2) / 2; for (int i = 0; i < N; i++) { fact[i] = choose(choosev, i / 2); if (i % 2) { fact[i] *= (1000000007 - 1); } fact[i] %= 1000000007; } } if (N % 4 == 1) { long long choosev = (N - 1) / 2; for (int i = 0; i < N; i += 2) { fact[i] = choose(choosev, i / 2); } } if (N % 4 == 2) { long long choosev = (N - 2) / 2; for (int i = 0; i < N; i++) { fact[i] = choose(choosev, i / 2); } } if (N % 4 == 3) { long long choosev = (N - 3) / 2; fact[0] = 1; fact[N - 1] = 1000000007 - 1; for (int i = 1; i < N - 1; i++) { if (i % 2) { fact[i] = choose(choosev, (i - 1) / 2) + choose(choosev, (i - 1) / 2); } else { fact[i] = choose(choosev, (i / 2)) - choose(choosev, (i - 1) / 2); } fact[i] %= 1000000007; fact[i] += 1000000007; fact[i] %= 1000000007; } } for (int i = 0; i < N; i++) { cerr << fact[i] << ; ans += fact[i] * arr[i]; ans %= 1000000007; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k; cin >> n >> m >> k; long long l = 0, h = n * m + 2; while (l < h) { long long md = (l + h) / 2; long long rs = 0; for (int i = 1; i <= n; i++) rs += min(m, md / i); if (rs < k) l = md + 1; else h = md; } cout << l << endl; }
|
#include <bits/stdc++.h> using namespace std; const int bigp = 1000000007; int main() { int x[103], y[103], z[103]; x[1] = 1; y[1] = 2; z[1] = 0; x[2] = 3; y[2] = 3; z[2] = 1; x[3] = 4; y[3] = 4; z[3] = 2; x[4] = 5; y[4] = 6; z[4] = 1; x[5] = 7; y[5] = 8; z[5] = 2; x[6] = 9; y[6] = 12; z[6] = 0; x[7] = 13; y[7] = 14; z[7] = 1; x[8] = 15; y[8] = 18; z[8] = 2; x[9] = 19; y[9] = 26; z[9] = 0; x[10] = 27; y[10] = 38; z[10] = 1; x[11] = 39; y[11] = 39; z[11] = 2; x[12] = 40; y[12] = 56; z[12] = 0; x[13] = 57; y[13] = 57; z[13] = 2; x[14] = 58; y[14] = 80; z[14] = 1; x[15] = 81; y[15] = 84; z[15] = 2; x[16] = 85; y[16] = 119; z[16] = 0; x[17] = 120; y[17] = 120; z[17] = 2; x[18] = 121; y[18] = 173; z[18] = 1; x[19] = 174; y[19] = 178; z[19] = 2; x[20] = 179; y[20] = 254; z[20] = 0; x[21] = 255; y[21] = 259; z[21] = 2; x[22] = 260; y[22] = 362; z[22] = 1; x[23] = 363; y[23] = 381; z[23] = 2; x[24] = 382; y[24] = 536; z[24] = 0; x[25] = 537; y[25] = 543; z[25] = 2; x[26] = 544; y[26] = 779; z[26] = 1; x[27] = 780; y[27] = 804; z[27] = 2; x[28] = 805; y[28] = 1145; z[28] = 0; x[29] = 1146; y[29] = 1168; z[29] = 2; x[30] = 1169; y[30] = 1631; z[30] = 1; x[31] = 1632; y[31] = 1717; z[31] = 2; x[32] = 1718; y[32] = 2414; z[32] = 0; x[33] = 2415; y[33] = 2446; z[33] = 2; x[34] = 2447; y[34] = 3506; z[34] = 1; x[35] = 3507; y[35] = 3621; z[35] = 2; x[36] = 3622; y[36] = 5153; z[36] = 0; x[37] = 5154; y[37] = 5259; z[37] = 2; x[38] = 5260; y[38] = 7340; z[38] = 1; x[39] = 7341; y[39] = 7729; z[39] = 2; x[40] = 7730; y[40] = 10865; z[40] = 0; x[41] = 10866; y[41] = 11010; z[41] = 2; x[42] = 11011; y[42] = 15779; z[42] = 1; x[43] = 15780; y[43] = 16297; z[43] = 2; x[44] = 16298; y[44] = 23189; z[44] = 0; x[45] = 23190; y[45] = 23668; z[45] = 2; x[46] = 23669; y[46] = 33032; z[46] = 1; x[47] = 33033; y[47] = 34783; z[47] = 2; x[48] = 34784; y[48] = 48893; z[48] = 0; x[49] = 48894; y[49] = 49548; z[49] = 2; x[50] = 49549; y[50] = 71006; z[50] = 1; x[51] = 71007; y[51] = 73339; z[51] = 2; x[52] = 73340; y[52] = 104351; z[52] = 0; x[53] = 104352; y[53] = 106509; z[53] = 2; x[54] = 106510; y[54] = 148646; z[54] = 1; x[55] = 148647; y[55] = 156526; z[55] = 2; x[56] = 156527; y[56] = 220019; z[56] = 0; x[57] = 220020; y[57] = 222969; z[57] = 2; x[58] = 222970; y[58] = 319529; z[58] = 1; x[59] = 319530; y[59] = 330028; z[59] = 2; x[60] = 330029; y[60] = 469580; z[60] = 0; x[61] = 469581; y[61] = 479293; z[61] = 2; x[62] = 479294; y[62] = 668909; z[62] = 1; x[63] = 668910; y[63] = 704370; z[63] = 2; x[64] = 704371; y[64] = 990086; z[64] = 0; x[65] = 990087; y[65] = 1003363; z[65] = 2; x[66] = 1003364; y[66] = 1437881; z[66] = 1; x[67] = 1437882; y[67] = 1485129; z[67] = 2; x[68] = 1485130; y[68] = 2113112; z[68] = 0; x[69] = 2113113; y[69] = 2156821; z[69] = 2; x[70] = 2156822; y[70] = 3010091; z[70] = 1; x[71] = 3010092; y[71] = 3169668; z[71] = 2; x[72] = 3169669; y[72] = 4455389; z[72] = 0; x[73] = 4455390; y[73] = 4515136; z[73] = 2; x[74] = 4515137; y[74] = 6470465; z[74] = 1; x[75] = 6470466; y[75] = 6683083; z[75] = 2; x[76] = 6683084; y[76] = 9509006; z[76] = 0; x[77] = 9509007; y[77] = 9705697; z[77] = 2; x[78] = 9705698; y[78] = 13545410; z[78] = 1; x[79] = 13545411; y[79] = 14263509; z[79] = 2; x[80] = 14263510; y[80] = 20049251; z[80] = 0; x[81] = 20049252; y[81] = 20318115; z[81] = 2; x[82] = 20318116; y[82] = 29117093; z[82] = 1; x[83] = 29117094; y[83] = 30073876; z[83] = 2; x[84] = 30073877; y[84] = 42790529; z[84] = 0; x[85] = 42790530; y[85] = 43675639; z[85] = 2; x[86] = 43675640; y[86] = 60954347; z[86] = 1; x[87] = 60954348; y[87] = 64185793; z[87] = 2; x[88] = 64185794; y[88] = 90221630; z[88] = 0; x[89] = 90221631; y[89] = 91431520; z[89] = 2; x[90] = 91431521; y[90] = 131026919; z[90] = 1; x[91] = 131026920; y[91] = 135332445; z[91] = 2; x[92] = 135332446; y[92] = 192557381; z[92] = 0; x[93] = 192557382; y[93] = 196540378; z[93] = 2; x[94] = 196540379; y[94] = 274294562; z[94] = 1; x[95] = 274294563; y[95] = 288836071; z[95] = 2; x[96] = 288836072; y[96] = 405997337; z[96] = 0; x[97] = 405997338; y[97] = 411441843; z[97] = 2; x[98] = 411441844; y[98] = 589621136; z[98] = 1; x[99] = 589621137; y[99] = 608996005; z[99] = 2; x[100] = 608996006; y[100] = 866508215; z[100] = 0; x[101] = 866508216; y[101] = 884431704; z[101] = 2; x[102] = 884431705; y[102] = 1000000000; z[102] = 1; int n, p, o, ex, ey, tt[4], f[1005][4]; scanf( %d %d , &n, &p); o = 0; for (int i = 1; i <= 102; i++) if (y[i] >= p) { y[i] = p; o = i; break; } memset(tt, 0, sizeof(tt)); for (int i = 1; i <= o; i++) { ex = p - x[i]; ey = p - y[i]; tt[z[i]] = (tt[z[i]] + (long long)(ex + ey) * (ex - ey + 1) / 2) % bigp; } memset(f, 0, sizeof(f)); f[0][0] = 1; for (int i = 0; i < n; i++) for (int j = 0; j <= 3; j++) for (int k = 0; k <= 2; k++) f[i + 1][j ^ k] = (f[i + 1][j ^ k] + (long long)f[i][j] * tt[k]) % bigp; printf( %d n , ((long long)f[n][1] + f[n][2] + f[n][3]) % bigp); return 0; }
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#include <bits/stdc++.h> using namespace std; int M[33][33]; int S[33][33]; int m; int n; int solve(int sid) { memcpy(S, M, sizeof(int) * 33 * 33); for (int i = 0; i < m; i++) { if ((1 << i) & sid) { for (int k = m - 1; k < n; k++) { for (int l = i; l < i + m; l++) { S[k][l] *= -1; } } } } int ret = 0; for (int i = 0; i < n; i++) ret += S[m - 1][i]; for (int i = 0; i < m - 1; i++) { for (int j = 0; j < n; j++) { S[i][j] += S[m + i][j]; } } for (int i = 0; i < m - 1; i++) { int row1 = S[i][m - 1], row2 = S[i][m - 1] * -1; for (int j = 0; j < m - 1; j++) { row1 += abs(S[i][j] + S[i][m + j]); row2 += abs(S[i][j] - S[i][m + j]); } ret += max(row1, row2); } return ret; } int main() { cin >> n; m = (n + 1) / 2; for (size_t i = 0; i < n; ++i) { for (size_t j = 0; j < n; ++j) { cin >> M[i][j]; } } int sol = -10000000; for (size_t i = 0; i < (1 << m); ++i) { sol = max(solve(i), sol); } cout << sol << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; namespace Solve { const int MAXN = 3005; inline int mymin(int a, int b) { return a < b ? a : b; } inline int mymax(int a, int b) { return a > b ? a : b; } int Log[MAXN], maxid[MAXN][20]; void getLog() { Log[1] = 0; for (int i = 2; i <= 3000; i++) { if (i & 1) Log[i] = Log[i - 1]; else Log[i] = Log[i >> 1] + 1; } return; } void getST(int *A, int n) { for (int i = 1; i <= n; i++) maxid[i][0] = i; for (int k = 1; k <= 12; k++) { for (int i = 1; i + (1 << k) - 1 <= n; i++) { int f = i + (1 << (k - 1)); if (A[maxid[i][k - 1]] > A[maxid[f][k - 1]]) maxid[i][k] = maxid[i][k - 1]; else maxid[i][k] = maxid[f][k - 1]; } } return; } struct Data { int id, val; Data(int a = 0, int b = 0) : id(a), val(b) {} bool operator<(const Data &B) const { return val > B.val; } } A[MAXN]; int N, D[MAXN], awd[MAXN]; int Qmaxid(int l, int r) { if (l > r) return 0; int k = Log[r - l + 1]; int f = r - (1 << k) + 1; if (D[maxid[l][k]] > D[maxid[f][k]]) return maxid[l][k]; return maxid[f][k]; } void work() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &A[i].val), A[i].id = i; sort(A + 1, A + N + 1); A[0].val = 0; for (int i = 1; i <= N; i++) D[i] = A[i - 1].val - A[i].val; D[N + 1] = A[N].val; getLog(); getST(D, N + 1); int mxi = -1, mxj = -1, mxk = -1, ansi = -1, ansj = -1, ansk = -1; for (int i = 1; i < N; i++) { if (A[i].val - A[i + 1].val < mxi) continue; for (int j = i + 1; j < N; j++) { if (i > 2 * (j - i)) continue; if (j - i > 2 * i) break; if (A[i].val - A[i + 1].val == mxi && A[j].val - A[j + 1].val < mxj) continue; int milen = mymin(i, j - i); int mxlen = mymax(i, j - i); int low = j + ((mxlen + 1) >> 1) + 1, upp = j + (milen << 1) + 1; if (low > N + 1) continue; if (upp > N + 1) upp = N + 1; int mxid = Qmaxid(low, upp); if (A[i].val - A[i + 1].val == mxi && A[j].val - A[j + 1].val == mxj && D[mxid] < mxk) continue; mxi = A[i].val - A[i + 1].val; mxj = A[j].val - A[j + 1].val; mxk = D[mxid]; ansi = i, ansj = j, ansk = mxid - 1; } } for (int i = 1; i <= ansi; i++) awd[A[i].id] = 1; for (int i = ansi + 1; i <= ansj; i++) awd[A[i].id] = 2; for (int i = ansj + 1; i <= ansk; i++) awd[A[i].id] = 3; for (int i = ansk + 1; i <= N; i++) awd[A[i].id] = -1; for (int i = 1; i <= N; i++) printf( %d , awd[i]); printf( n ); return; } } // namespace Solve int main() { Solve::work(); return 0; }
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#include <bits/stdc++.h> using namespace std; long long v2[34]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; for (int i = 0; i <= 33; ++i) { if (i == 0) { v2[i] = 1; } else { v2[i] = 2 * v2[i - 1]; } } while (t--) { int n; cin >> n; vector<long long> v(n); for (int i = 0; i < n; ++i) { cin >> v[i]; } int ans = 0; for (int i = 1; i < n; ++i) { if (v[i] < v[i - 1]) { long long aux = 0; int k = 0; long long dif = v[i - 1] - v[i]; for (int j = 0; j < 34; ++j) { aux += v2[j]; if (aux >= dif) { ans = max(ans, j + 1); k = j; break; } } v[i] += dif; } } cout << ans << endl; } return 0; }
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// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module udp_reg_master
#(
parameter SRC_ADDR = 0,
parameter TIMEOUT = 127,
parameter TIMEOUT_RESULT = 'h dead_0000,
parameter UDP_REG_SRC_WIDTH = 2
)
(
// Core register interface signals
input core_reg_req,
output reg core_reg_ack,
input core_reg_rd_wr_L,
input [`UDP_REG_ADDR_WIDTH - 1:0] core_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH - 1:0]core_reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] core_reg_wr_data,
// UDP register interface signals (output)
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH - 1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH - 1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH - 1:0] reg_src_out,
// UDP register interface signals (input)
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH - 1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH - 1:0] reg_src_in,
//
input clk,
input reset
);
localparam WAIT = 'd0;
localparam PROCESSING = 'd1;
localparam DONE = 'd2;
reg [1:0] state;
reg [7:0] count;
wire result_valid = reg_req_in && reg_src_in == SRC_ADDR;
// ==============================================
// State machine for core signals
always @(posedge clk)
begin
if (reset) begin
core_reg_ack <= 1'b0;
core_reg_rd_data <= 'h0;
state <= WAIT;
count <= 'h0;
end
else begin
case (state)
WAIT : begin
if (core_reg_req && !reg_req_in) begin
state <= PROCESSING;
count <= TIMEOUT;
end
end
PROCESSING : begin
if (!core_reg_req) begin
state <= WAIT;
end
else if (result_valid || count == 'h0) begin
state <= DONE;
core_reg_ack <= 1'b1;
if (result_valid && reg_ack_in)
core_reg_rd_data <= reg_data_in;
else if (count == 'h0)
core_reg_rd_data <= TIMEOUT_RESULT;
else
core_reg_rd_data <= 'h dead_beef;
end
count <= count - 'h1;
end
DONE : begin
core_reg_ack <= 1'b0;
if (!core_reg_req)
state <= WAIT;
end
default : begin
// synthesis translate_off
if ($time > 3000)
$display($time, " ERROR: invalid state: %x", state);
// synthesis translate_on
end
endcase
end
end
// ==============================================
// State machine for UDP signals
always @(posedge clk)
begin
if (reset) begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 1'b0;
reg_addr_out <= 'h0;
reg_data_out <= 'h0;
reg_src_out <= 'h0;
end
else begin
// Forward requests that aren't destined to us
if (reg_req_in && reg_src_in != SRC_ADDR) begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_data_out <= reg_data_in;
reg_src_out <= reg_src_in;
end
// Put new requests on the bus
else if (state == WAIT && core_reg_req && !reg_req_in) begin
reg_req_out <= 1'b1;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= core_reg_rd_wr_L;
reg_addr_out <= core_reg_addr;
reg_data_out <= core_reg_wr_data;
reg_src_out <= SRC_ADDR;
end
// Twiddle our thumbs -- nothing to do
else begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 1'b0;
reg_addr_out <= 'h0;
reg_data_out <= 'h0;
reg_src_out <= 'h0;
end
end
end
endmodule // unused_reg
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_4_V
`define SKY130_FD_SC_HDLL__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_4_V
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; long long c[100005]; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); a[i] -= k; } long long A; scanf( %lld , &A); priority_queue<long long, vector<long long>, greater<long long> > P; long long cnt = 0; long long ans = 0; long long now = 0; for (int i = 1; i <= n; i++) { scanf( %lld , &c[i]); } for (int i = 1; i <= n; i++) { P.push(c[i]); if (a[i] > cnt) { long long t; if (a[i] < now) t = 0; else t = ((a[i] - now) % A == 0 ? (a[i] - now) / A : (a[i] - now) / A + 1); for (int j = 1; j <= t; j++) { if (P.empty()) { ans = -1; break; } ans += P.top(); now += A; P.pop(); } cnt = a[i]; if (ans == -1) break; } } printf( %lld , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, j, ans; cin >> n >> k; int arr[n]; for (i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); ans = 0; for (i = n - 1; i >= 0; i = i - k) { ans += 2 * (arr[i] - 1); } cout << ans; }
|
// this module handles the hold and modify mode (HAM)
// the module has its own colour pallete bank, this is to let
// the sprites run simultaneously with a HAM playfield
module denise_hamgenerator
(
input wire clk, // 28MHz clock
input wire clk7_en, // 7MHz clock enable
input wire [ 9-1:1] reg_address_in, // register adress inputs
input wire [ 12-1:0] data_in, // bus data in
input wire [ 8-1:0] select, // colour select input
input wire [ 8-1:0] bplxor, // clut address xor value
input wire [ 3-1:0] bank, // color bank select
input wire loct, // 12-bit pallete select
input wire ham8, // HAM8 mode
output reg [ 24-1:0] rgb // RGB output
);
// register names and adresses
parameter COLORBASE = 9'h180; // colour table base address
// select xor
wire [ 8-1:0] select_xored = select ^ bplxor;
// color ram
wire [ 8-1:0] wr_adr = {bank[2:0], reg_address_in[5:1]};
wire wr_en = (reg_address_in[8:6] == COLORBASE[8:6]) && clk7_en;
wire [32-1:0] wr_dat = {4'b0, data_in[11:0], 4'b0, data_in[11:0]};
wire [ 4-1:0] wr_bs = loct ? 4'b0011 : 4'b1111;
wire [ 8-1:0] rd_adr = ham8 ? {2'b00, select_xored[7:2]} : select_xored;
wire [32-1:0] rd_dat;
reg [24-1:0] rgb_prev;
reg [ 8-1:0] select_r;
// color lut
denise_colortable_ram_mf clut
(
.clock (clk ),
.enable (1'b1 ),
.wraddress (wr_adr ),
.wren (wr_en ),
.byteena_a (wr_bs ),
.data (wr_dat ),
.rdaddress (rd_adr ),
.q (rd_dat )
);
// pack color values
wire [12-1:0] color_hi = rd_dat[12-1+16:0+16];
wire [12-1:0] color_lo = rd_dat[12-1+ 0:0+ 0];
wire [24-1:0] color = {color_hi[11:8], color_lo[11:8], color_hi[7:4], color_lo[7:4], color_hi[3:0], color_lo[3:0]};
// register previous rgb value
always @ (posedge clk) begin
rgb_prev <= #1 rgb;
end
// register previous select
always @ (posedge clk) begin
select_r <= #1 select_xored;
end
// HAM instruction decoder/processor
always @ (*) begin
if (ham8) begin
case (select_r[1:0])
2'b00: // load rgb output with colour from table
rgb = color;
2'b01: // hold green and red, modify blue
rgb = {rgb_prev[23:8],select_r[7:2],rgb_prev[1:0]};
2'b10: // hold green and blue, modify red
rgb = {select_r[7:2],rgb_prev[17:16],rgb_prev[15:0]};
2'b11: // hold blue and red, modify green
rgb = {rgb_prev[23:16],select_r[7:2],rgb_prev[9:8],rgb_prev[7:0]};
default:
rgb = color;
endcase
end else begin
case (select_r[5:4])
2'b00: // load rgb output with colour from table
rgb = color;
2'b01: // hold green and red, modify blue
rgb = {rgb_prev[23:8],select_r[3:0],select_r[3:0]};
2'b10: // hold green and blue, modify red
rgb = {select_r[3:0],select_r[3:0],rgb_prev[15:0]};
2'b11: // hold blue and red, modify green
rgb = {rgb_prev[23:16],select_r[3:0],select_r[3:0],rgb_prev[7:0]};
default:
rgb = color;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> int n, K; int ch[60000][26]; int val[60000]; char st[1000]; int f[60000][1000]; int knum; void add(char *st) { int m = strlen(st + 1); int u = 0; for (int i = 1; i <= m; i++) { if (!ch[u][st[i] - a ]) { knum++; ch[u][st[i] - a ] = knum; } u = ch[u][st[i] - a ]; } val[u]++; } void dfs(int u) { for (int i = 0; i < 26; i++) { int v = ch[u][i]; if (v) { dfs(v); } } for (int i = 0; i <= K; i++) { f[u][i] = -1000000000; } f[u][0] = 0; for (int i = 0; i < 26; i++) { int v = ch[u][i]; if (v) { for (int j = K; j >= 0; j--) { for (int k = 0; k <= j; k++) { f[u][j] = std::max(f[u][j], f[u][j - k] + f[v][k] + k * (k - 1) / 2); } } } } for (int i = K; i >= 0; i--) { for (int j = 0; j <= std::min(i, val[u]); j++) { f[u][i] = std::max(f[u][i], f[u][i - j]); } } } int main() { knum = 0; scanf( %d%d , &n, &K); for (int i = 1; i <= n; i++) { scanf( %s , st + 1); add(st); } dfs(0); printf( %d n , f[0][K]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; const long long mod = (long long)1e9 + 7; const double eps = (double)1e-9; const double pi = acos(-1.0); const int dx[] = {0, 0, 1, 0, -1}; const int dy[] = {0, 1, 0, -1, 0}; const int N = 500500; int n, k; vector<pair<int, int> > g[N]; long long dp[N], W[N]; void dfs(int v, int pr = -1) { dp[v] = 0; vector<long long> u; for (auto to : g[v]) { if (to.first == pr) continue; dfs(to.first, v); dp[v] += dp[to.first] + W[to.first]; if (-W[to.first] + to.second > 0) u.push_back(-W[to.first] + to.second); } sort(u.begin(), u.end()); reverse(u.begin(), u.end()); for (int i = 0; i < min(k - 1, (int)u.size()); ++i) dp[v] += u[i]; if (k <= (int)u.size()) W[v] = u[k - 1]; else W[v] = 0; } void solve() { cin >> n >> k; for (int i = 1; i <= n; ++i) g[i].clear(); for (int i = 1; i < n; ++i) { int x, y, w; cin >> x >> y >> w; g[x].push_back(make_pair(y, w)); g[y].push_back(make_pair(x, w)); } dfs(1); cout << dp[1] + W[1] << endl; } int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); int T; cin >> T; while (T--) solve(); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_req.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_req.v //
// Description : Instantiates the request buffer primitives; 8KB Dual Port //
// Request FIFO //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_req #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] waddr0_i, // write address
input [8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
input wen2_i, // write enable
input wen3_i, // write enable
input [8:0] raddr0_i, // write address
input [8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input ren0_i, // read enable
input ren1_i, // read enable
input ren2_i, // read enable
input ren3_i // read enable
);
pcie3_7x_0_pcie_bram_7vx_8k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.waddr0_i (waddr0_i[8:0]),
.waddr1_i (waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i (raddr0_i[8:0]),
.raddr1_i (raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
endmodule // pcie_bram_7vx_req
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:53:27 11/22/2016
// Design Name:
// Module Name: number_in
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module number_in(
input [31:0] num_a,
input [31:0] num_b,
input [31:0] result,
input [4:0] code,
input btnm,
output reg [32:0] num_out
);
reg [31:0] new;
reg [6:0] i;
reg [1:0] state;
reg b_state;
parameter [1:0] numA = 2'b00;
parameter [1:0] numB = 2'b01;
parameter [1:0] numC = 2'b10;
initial state = 2'b00;
initial b_state = 0;
always @(*)
begin
if(btnm)
begin
if(~b_state)
begin
b_state = 1;
if(state == numA) //Estado A
begin
if(code > 9 && code < 15) //Cambia estado
begin
state = numB;
end
end
else if(state == numB) //Estado B
begin
if(code == 15) //Cambia estado
begin
state = numC;
end
end
else
begin
if(code == 16) //Cambia estado
begin
state = numA;
end
end
end
end
else
begin
b_state = 0;
end
end
always @(state)
begin
case (state)
numA: new = num_a;
numB: new = num_b;
numC: new = result;
default: new = num_a;
endcase
if(new[31])
begin
for(i = 0; i < 32; i = i + 1)
num_out[i] = ~new[i];
num_out = num_out + 1'b1;
num_out[32] = 1'b1;
end
else
begin
num_out = new;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } vector<string> getWords(string s) { string cur = ; vector<string> vec; for (int i = 0; i < s.size(); i++) { if (s[i] == ) { vec.push_back(cur); cur = ; } else cur += s[i]; } vec.push_back(cur); return vec; } int dist[213456], sz[213456]; vector<vector<int> > vec; void dfs(int n, int p) { sz[n] = 1; for (auto x : vec[n]) { if (x != p) { dist[x] = dist[n] + 1; dfs(x, n); sz[n] += sz[x]; } } } int main() { int n, k; cin >> n >> k; vec.resize(n + 1); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; vec[u].push_back(v); vec[v].push_back(u); } dfs(1, 0); vector<long long> vec1; for (int i = 2; i <= n; i++) { int val = dist[i] - (sz[i] - 1); vec1.push_back(val); } sort(vec1.begin(), vec1.end()); reverse(vec1.begin(), vec1.end()); long long ans = 0; for (int i = 0; i < k; i++) ans += vec1[i]; cout << ans; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mux
*/
module test_eth_mux_64_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT-1:0] s_eth_hdr_valid = 0;
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
reg [S_COUNT*16-1:0] s_eth_type = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg [S_COUNT-1:0] s_eth_payload_axis_tvalid = 0;
reg [S_COUNT-1:0] s_eth_payload_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_eth_hdr_ready;
wire [S_COUNT-1:0] s_eth_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire [ID_WIDTH-1:0] m_eth_payload_axis_tid;
wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tid,
s_eth_payload_axis_tdest,
s_eth_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
enable,
select
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tid,
m_eth_payload_axis_tdest,
m_eth_payload_axis_tuser
);
// dump file
$dumpfile("test_eth_mux_64_4.lxt");
$dumpvars(0, test_eth_mux_64_4);
end
eth_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame inputs
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tid(m_eth_payload_axis_tid),
.m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the select of a bit from a parameter.
*/
module test;
reg [4:0] a;
wire o;
RAM dut(o, a[3:0]);
defparam test.dut.INIT = 16'h55aa;
initial begin
for (a = 0 ; a[4] == 0 ; a = a + 1) begin
#1 $display("dut[%h] = %b", a, o);
end
end
endmodule // test
module RAM (O, A);
parameter INIT = 16'h0000;
output O;
input [3:0] A;
reg mem [15:0];
reg [4:0] count;
wire [3:0] adr;
buf (O, mem[A]);
initial
begin
for (count = 0; count < 16; count = count + 1)
mem[count] <= INIT[count];
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb_fifo64to16(
input sys_clk,
input vga_rst,
input stb,
input [63:0] di,
output do_valid,
output reg [15:0] do,
input next /* should only be asserted when do_valid = 1 */
);
/*
* FIFO can hold 4 64-bit words
* that is 16 16-bit words.
*/
reg [63:0] storage[0:3];
reg [1:0] produce; /* in 64-bit words */
reg [3:0] consume; /* in 16-bit words */
/*
* 16-bit words stored in the FIFO, 0-16 (17 possible values)
*/
reg [4:0] level;
wire [63:0] do64;
assign do64 = storage[consume[3:2]];
always @(*) begin
case(consume[1:0])
2'd0: do <= do64[63:48];
2'd1: do <= do64[47:32];
2'd2: do <= do64[31:16];
2'd3: do <= do64[15:0];
endcase
end
always @(posedge sys_clk) begin
if(vga_rst) begin
produce = 2'd0;
consume = 4'd0;
level = 5'd0;
end else begin
if(stb) begin
storage[produce] = di;
produce = produce + 2'd1;
level = level + 5'd4;
end
if(next) begin /* next should only be asserted when do_valid = 1 */
consume = consume + 4'd1;
level = level - 5'd1;
end
end
end
assign do_valid = ~(level == 5'd0);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 12, mod = 1e9 + 7; long long dp[maxn][2][maxn]; int num[maxn]; long long dfs(int pos, bool bnd, int ned) { if (ned < 0) return 0; if (pos < 0) return ned == 0; long long& ndp = dp[pos][bnd][ned]; if (~ndp) return ndp; ndp = 0; int bound = bnd ? num[pos] : 9; for (int i = 0; i <= bound; i++) ndp += dfs(pos - 1, bnd && i == bound, ned - (i == 4 || i == 7)); return ndp; } long long cnt[maxn]; int init(long long x) { int len = 0; while (x) { num[len++] = x % 10; x /= 10; } memset(dp, -1, sizeof(dp)); for (int i = len; i >= 0; i--) { cnt[i] = dfs(len - 1, true, i); } cnt[0]--; return len; } long long ans; void dfs(int st, long long v, int len, int adder) { if (st == 7) { for (int i = adder + 1; i <= len; i++) { (ans += v * cnt[i] % mod) %= mod; } return; } if (adder >= len) return; for (int i = 0; i <= len; i++) { if (cnt[i] == 0) continue; long long mid = v * cnt[i] % mod; cnt[i]--; dfs(st + 1, mid, len, adder + i); cnt[i]++; } } int main() { long long n; scanf( %I64d , &n); int len = init(n); ans = 0; dfs(1, 1, len, 0); printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long M = 1000000007; long long bigMod(long long n, long long power, long long mod = M) { if (power == 0) return 1; if (power == 1) return n % mod; else if (power % 2 == 0) { long long v = bigMod(n, power / 2, mod); return ((v % mod) * (v % mod)) % mod; } else { long long v = bigMod(n, power - 1, mod) % mod; return ((v % mod) * (n % mod)) % mod; } } int main() { long long n; scanf( %lld , &n); long long number = bigMod(2, n); cout << ((number * (number + 1)) / 2) % M << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, ans = INT_MAX; cin >> n >> k; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; if (k % x == 0) { ans = min(ans, k / x); } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_random.v,v $
// Revision 1.4 2003/06/13 11:26:08 mohor
// Binary operator used instead of unary (xnor).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [7:0] r_poke_1, r_poke_2, r_poke_3, r_poke_4, r_poke_5;
reg [7:0] r_peek_1, r_peek_2, r_peek_3, r_peek_4, r_peek_5;
task f_copy;
begin
// twizzle copy
r_peek_1 = r_poke_2;
r_peek_2 = r_poke_3;
r_peek_3 = r_poke_4;
r_peek_4 = r_poke_5;
r_peek_5 = r_poke_1;
end
endtask
task f_dump;
integer i;
begin
$display("Verilog compare r_poke <=> r_peek");
$display (" 'b_%b <=> 'b_%b%s",
r_poke_1, r_peek_5, r_poke_1 !== r_peek_5 ? " - ERROR" : "");
$display (" 'b_%b <=> 'b_%b%s",
r_poke_2, r_peek_1, r_poke_2 !== r_peek_1 ? " - ERROR" : "");
$display (" 'b_%b <=> 'b_%b%s",
r_poke_3, r_peek_2, r_poke_3 !== r_peek_2 ? " - ERROR" : "");
$display (" 'b_%b <=> 'b_%b%s",
r_poke_4, r_peek_3, r_poke_4 !== r_peek_3 ? " - ERROR" : "");
$display (" 'b_%b <=> 'b_%b%s",
r_poke_5, r_peek_4, r_poke_5 !== r_peek_4 ? " - ERROR" : "");
end
endtask
initial begin
#0;
$regpoke;
#10;
f_copy;
#10;
$regpeek;
#10;
f_dump;
end
endmodule
|
/*Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
input clk, reset, start;
input [7:0] din;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
reg ready;
reg temp_ready;
reg [6:0] finite_counter;
wire count0;
input iir_start;
output iir_done;
wire iir_done;
reg del_count0;
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
//wire [23:0] b0t, b1t, b2t;
wire [22:0] b0t, b1t, b2t;
wire [22:0] b0tpaj, b1tpaj, b2tpaj;
reg [3:0] obf_state, obf_next_state ;
reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
reg [28:0] temp_ysum ;
reg [26:0] temp_yk ;
reg [22:0] temp_utmp;
reg [7:0] temp_dout;
reg [3:0] temp_wait_counter ;
parameter
idle = 4'b0001 ,
load_a2 = 4'b0010 ,
load_b0 = 4'b0011 ,
load_b1 = 4'b0100 ,
load_b2 = 4'b0101 ,
wait4_start = 4'b0110 ,
latch_din = 4'b0111 ,
compute_a = 4'b1000 ,
compute_b = 4'b1001 ,
compute_yk = 4'b1010 ,
wait4_count = 4'b1011 ,
latch_dout = 4'b1100 ;
always @(obf_state or start or din or wait_counter or iir_start or count0)
begin
case (obf_state )
idle :
begin
if (iir_start)
obf_next_state = load_a2 ;
else
obf_next_state = idle;
temp_a1 = params ;
end
load_a2 :
begin
obf_next_state = load_b0 ;
temp_a2 = params ;
end
load_b0 :
begin
obf_next_state = load_b1 ;
temp_b0 = params ;
end
load_b1 :
begin
obf_next_state = load_b2 ;
temp_b1 = params ;
end
load_b2 :
begin
obf_next_state = wait4_start ;
temp_b2 = params ;
end
wait4_start :
begin
if (start)
begin
obf_next_state = latch_din ;
temp_uk = din ;
end
else
begin
obf_next_state = wait4_start ;
temp_uk = uk;
end
temp_ready = wait4_start;
end
latch_din :
begin
obf_next_state = compute_a ;
end
compute_a :
begin
obf_next_state = compute_b ;
temp_ysum = yo1[31:3] + yo2[31:3];
end
compute_b :
begin
obf_next_state = compute_yk ;
// temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0];
temp_utmp = b0t + b1t + b2t;
end
compute_yk :
begin
obf_next_state = wait4_count ;
temp_uk1 = uk ;
temp_uk2 = uk1 ;
temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
temp_wait_counter = 4 ;
end
wait4_count :
begin
if (wait_counter==0 )
begin
obf_next_state = latch_dout ;
temp_dout = yk[26:19];
temp_yk1 = yk[26:11] ;
temp_yk2 = yk1 ;
end
else
begin
obf_next_state = wait4_count ;
temp_dout = dout;
temp_yk1 = yk1;
//temp_yk2 = yk2;
end
temp_wait_counter = wait_counter - 1;
end
latch_dout :
if (count0)
obf_next_state = idle;
else
obf_next_state = wait4_start ;
endcase
end
//assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo1 = yk1 + a1;
//assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign yo2 = yk2 + a2;
//assign b0t = mul_tc_8_16(uk, b0, clk);
//assign b1t = mul_tc_8_16(uk1, b1, clk);
//assign b2t = mul_tc_8_16(uk2, b2, clk);
assign b0t = uk*b0;
assign b1t = uk1*b1;
assign b2t = uk2*b2;
// paj added to solve unused high order bit
assign b0tpaj = b0t;
assign b1tpaj = b1t;
assign b2tpaj = b2t;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
obf_state <= idle ;
ready <= 0;
end
else begin
obf_state <= obf_next_state ;
uk1 <= temp_uk1;
uk2 <= temp_uk2;
yk <= temp_yk;
uk <= temp_uk ;
a1 <= temp_a1 ;
a2 <= temp_a2 ;
b0 <= temp_b0 ;
b1 <= temp_b1 ;
b2 <= temp_b2 ;
ysum <= temp_ysum;
utmp <= temp_utmp;
dout <= temp_dout;
yk1 <= temp_yk1;
yk2 <= temp_yk2;
ready <= temp_ready;
end
end
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
wait_counter <= temp_wait_counter ;
end
end
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
assign count0=finite_counter==7'b0;
always @(posedge clk) begin
del_count0 <= count0;
end
assign iir_done = (count0 && ~del_count0);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char str[100005]; scanf( %s , str); int l = strlen(str); int pr = -1, i, j; for (i = z ; i >= a ; i--) for (j = 0; j < l; j++) { if (str[j] == i && j > pr) { cout << str[j]; pr = j; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MN = 1000 * 100 + 100; int arr[MN], n, s_l, s_r; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; s_r += arr[i]; } s_r -= arr[0]; s_l = arr[0]; int cnt = 0; for (int i = 1; i < n; i++) { if (s_l == s_r) cnt++; s_r -= arr[i]; s_l += arr[i]; } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; vector<long long int> dp(2e5 + 1, 1); int main() { long long int t, q = 1, n, k; ; while (q--) { for (long long int i = 1; i < 2e5 + 1; i++) dp[i] = ((dp[i - 1] % 998244353) * 10) % 998244353; cin >> n; for (int i = 1; i < n; i++) { long long int ans = 0; ans = 2 * 10 * 9 * dp[n - i - 1]; ans %= 998244353; ans += (n - i - 1) * 10 * 9 * 9 * dp[n - i - 2]; ans %= 998244353; cout << ans << ; } cout << 10 ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRBP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int A[(1 << 17)]; int A0[(1 << 17)]; int A1[(1 << 17)]; int C[(1 << 17)]; int RMQ[2 << 20]; int I[32]; void Add(int a, int b) { int i; for (i = (0); i < (20); ++i) RMQ[I[i] + (a >> i)] += b; } int Sum(int a) { int res = 0; int i; for (i = (0); i < (20); ++i) { if (a & 1) res += RMQ[I[i] + a - 1]; a >>= 1; } return res; } int main() { int N, M; scanf( %d%d , &N, &M); vector<int> v; int i; for (i = (0); i < (M); ++i) { scanf( %d , &A[i]); if (A[i] == 0) scanf( %d%d , &A0[i], &A1[i]); else v.push_back(A[i]); } sort((v).begin(), (v).end()); v.resize(unique((v).begin(), (v).end()) - v.begin()); for (i = (0); i < (M); ++i) if (A[i] != 0) A[i] = int(lower_bound((v).begin(), (v).end(), A[i]) - v.begin()) + 1; set<pair<int, int> > bl, lb; bl.insert(pair<int, int>(-1, -N)); lb.insert(pair<int, int>(-N, -1)); v.clear(); memset(C, -1, sizeof(C)); for (i = (0); i < (M); ++i) if (A[i] != 0) if (C[A[i]] == -1) { pair<int, int> t = *lb.begin(); lb.erase(lb.begin()); bl.erase(pair<int, int>(t.second, t.first)); int l = -t.second; int r = -t.second - t.first; int m = (l + r) / 2; bl.insert(pair<int, int>(-l, l - m)); lb.insert(pair<int, int>(l - m, -l)); bl.insert(pair<int, int>(-(m + 1), (m + 1) - r)); lb.insert(pair<int, int>((m + 1) - r, -(m + 1))); A0[i] = m; C[A[i]] = m; v.push_back(m); } else { pair<int, int> t(-C[A[i]], 0); set<pair<int, int> >::iterator it0 = bl.lower_bound(t); set<pair<int, int> >::iterator it1 = it0; --it1; pair<int, int> r = *it1; pair<int, int> l = *it0; bl.erase(l); bl.erase(r); lb.erase(pair<int, int>(l.second, l.first)); lb.erase(pair<int, int>(r.second, r.first)); l.second += r.second - 1; bl.insert(l); lb.insert(pair<int, int>(l.second, l.first)); A0[i] = -C[A[i]]; C[A[i]] = -1; } for (i = (0); i < (M); ++i) if (A[i] == 0) { ++A1[i]; v.push_back(A0[i]); v.push_back(A1[i]); } sort((v).begin(), (v).end()); v.resize(unique((v).begin(), (v).end()) - v.begin()); memset(RMQ, 0, sizeof(RMQ)); I[0] = 0; for (i = (1); i < (20); ++i) I[i] = I[i - 1] + (1 << (21 - i)); for (i = (0); i < (M); ++i) if (A[i] == 0) { A0[i] = lower_bound((v).begin(), (v).end(), A0[i]) - v.begin(); A1[i] = lower_bound((v).begin(), (v).end(), A1[i]) - v.begin(); printf( %d n , Sum(A1[i]) - Sum(A0[i])); } else if (A0[i] < 0) { A0[i] = lower_bound((v).begin(), (v).end(), -A0[i]) - v.begin(); Add(A0[i], -1); } else { A0[i] = lower_bound((v).begin(), (v).end(), A0[i]) - v.begin(); Add(A0[i], 1); } return 0; };
|
/*
File: ewrapper_link_transmitter.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_link_transmitter(/*AUTOARG*/
// Outputs
emesh_wr_wait_inb, emesh_rd_wait_inb, tx_in,
// Inputs
reset, txo_lclk, emesh_clk_inb, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
txo_wr_wait, txo_rd_wait, burst_en
);
//#########
//# INPUTS
//#########
input reset; //reset input
input txo_lclk; //transmitter clock
input emesh_clk_inb; // clock of the incoming emesh transaction
//# From the Emesh
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
//# From the receiver
input txo_wr_wait; //wait indicator
input txo_rd_wait; //wait indicator
input burst_en; // Burst enable control
//##########
//# OUTPUTS
//##########
//# To the Emesh
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//# To the lvds-serdes
output [71:0] tx_in;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg wrfifo_rd_en;
//#########
//# Wires
//#########
wire [1:0] txo_wait;
wire [1:0] txo_wait_sync;
wire txo_wr_wait_sync;
wire txo_rd_wait_sync;
wire [103:0] fifo_in;
wire [103:0] fifo_out;
wire [107:0] wrfifo_out;
wire [107:0] rdfifo_out;
wire wrfifo_wait;
wire rdfifo_wait;
wire wrfifo_rd_int;
wire rdfifo_rd_int;
wire wrfifo_rd;
wire rdfifo_rd;
wire wrfifo_wr;
wire rdfifo_wr;
wire rdfifo_empty;
wire wrfifo_empty;
wire txo_emesh_wait;
wire txo_emesh_access;
wire txo_emesh_write;
wire [1:0] txo_emesh_datamode;
wire [3:0] txo_emesh_ctrlmode;
wire [31:0] txo_emesh_dstaddr;
wire [31:0] txo_emesh_srcaddr;
wire [31:0] txo_emesh_data;
//############################
//# txo_wait synchronization
//############################
assign txo_wait[1:0] = {txo_rd_wait,txo_wr_wait};
assign txo_wr_wait_sync = txo_wait_sync[0];
assign txo_rd_wait_sync = txo_wait_sync[1];
synchronizer #(.DW(2)) synchronizer(.out (txo_wait_sync[1:0]),
.in (txo_wait[1:0]),
.clk (txo_lclk),
.reset (reset));
//#####################################
//# lvds_link_txo instantiation
//#####################################
ewrapper_link_txo txo(/*AUTOINST*/
// Outputs
.txo_emesh_wait (txo_emesh_wait),
.tx_in (tx_in[71:0]),
// Inputs
.reset (reset),
.txo_lclk (txo_lclk),
.txo_emesh_access (txo_emesh_access),
.txo_emesh_write (txo_emesh_write),
.txo_emesh_datamode (txo_emesh_datamode[1:0]),
.txo_emesh_ctrlmode (txo_emesh_ctrlmode[3:0]),
.txo_emesh_dstaddr (txo_emesh_dstaddr[31:0]),
.txo_emesh_srcaddr (txo_emesh_srcaddr[31:0]),
.txo_emesh_data (txo_emesh_data[31:0]),
.burst_en (burst_en));
//#####################################
//# synchronization FIFOs (read/write)
//#####################################
//# FIFO writes
assign wrfifo_wr = emesh_access_outb & emesh_write_outb & ~emesh_wr_wait_inb;
assign rdfifo_wr = emesh_access_outb &~emesh_write_outb & ~emesh_rd_wait_inb;
//# FIFO reads
assign wrfifo_rd_int = ~(wrfifo_empty | txo_wr_wait_sync | txo_emesh_wait);
assign rdfifo_rd_int = ~(rdfifo_empty | txo_rd_wait_sync | txo_emesh_wait);
//# arbitration
always @ (posedge txo_lclk or posedge reset)
if(reset)
wrfifo_rd_en <= 1'b0;
else
wrfifo_rd_en <= ~wrfifo_rd_en;
assign wrfifo_rd = wrfifo_rd_int & ( wrfifo_rd_en | ~rdfifo_rd_int);
assign rdfifo_rd = rdfifo_rd_int & (~wrfifo_rd_en | ~wrfifo_rd_int);
//# FIFO input
assign fifo_in[103:0] = {emesh_srcaddr_outb[31:0],
emesh_data_outb[31:0],
emesh_dstaddr_outb[31:0],
emesh_ctrlmode_outb[3:0],
emesh_datamode_outb[1:0],
emesh_write_outb,
emesh_access_outb};
//# FIFO output
assign fifo_out[103:0] = wrfifo_rd ? wrfifo_out[103:0] : rdfifo_out[103:0];
assign txo_emesh_access = wrfifo_rd | rdfifo_rd;
assign txo_emesh_write = fifo_out[1];
assign txo_emesh_datamode[1:0] = fifo_out[3:2];
assign txo_emesh_ctrlmode[3:0] = fifo_out[7:4];
assign txo_emesh_dstaddr[31:0] = fifo_out[39:8];
assign txo_emesh_data[31:0] = fifo_out[71:40];
assign txo_emesh_srcaddr[31:0] = fifo_out[103:72];
/*fifo AUTO_TEMPLATE(.rd_clk (txo_lclk),
.wr_clk (emesh_clk_inb),
.wr_data (fifo_in[103:0]),
.rd_data (wrfifo_out[103:0]),
.rd_fifo_empty (wrfifo_empty),
.wr_fifo_full (emesh_wr_wait_inb),
.wr_write (wrfifo_wr),
.rd_read (wrfifo_rd),
);
*/
//# We have 4 entries of 104 bits each
fifo #(.DW(104), .AW(2)) wrfifo_txo(/*AUTOINST*/
// Outputs
.rd_data (wrfifo_out[103:0]), // Templated
.rd_fifo_empty (wrfifo_empty), // Templated
.wr_fifo_full (emesh_wr_wait_inb), // Templated
// Inputs
.reset (reset),
.wr_clk (emesh_clk_inb), // Templated
.rd_clk (txo_lclk), // Templated
.wr_write (wrfifo_wr), // Templated
.wr_data (fifo_in[103:0]), // Templated
.rd_read (wrfifo_rd)); // Templated
/*fifo AUTO_TEMPLATE(.rd_clk (txo_lclk),
.wr_clk (emesh_clk_inb),
.wr_data (fifo_in[103:0]),
.rd_data (rdfifo_out[103:0]),
.rd_fifo_empty (rdfifo_empty),
.wr_fifo_full (emesh_rd_wait_inb),
.wr_write (rdfifo_wr),
.rd_read (rdfifo_rd),
);
*/
//# We have 4 entries of 104 bits each
fifo #(.DW(104), .AW(2)) rdfifo_txo(/*AUTOINST*/
// Outputs
.rd_data (rdfifo_out[103:0]), // Templated
.rd_fifo_empty (rdfifo_empty), // Templated
.wr_fifo_full (emesh_rd_wait_inb), // Templated
// Inputs
.reset (reset),
.wr_clk (emesh_clk_inb), // Templated
.rd_clk (txo_lclk), // Templated
.wr_write (rdfifo_wr), // Templated
.wr_data (fifo_in[103:0]), // Templated
.rd_read (rdfifo_rd)); // Templated
endmodule // ewrapper_link_transmitter
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const double pi = acos(-1.0); void cp(); long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } long long fact(long long n) { if (n <= 1) return n; return n * fact(n - 1); } bool prime[100001]; void sieve() { int n = 10000; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } } void solve() { int n, i; cin >> n; string s; cin >> s; for (i = 0; i <= (2 * n) - 1; i++) { if (i % 2 == 0) cout << s[i]; } cout << n ; } int main() { cp(); int t; cin >> t; while (t--) solve(); return 0; } void cp() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer j;
reg [63:0] cam_lookup_hit_vector;
integer hit_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count = 0;
for (j=0; j < 64; j=j+1) begin
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count2;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count2 = 0;
for (j=63; j >= 0; j=j-1) begin
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count3;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count3 = 0;
for (j=63; j > 0; j=j-1) begin
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
end
end
reg [127:0] wide_for_index;
reg [31:0] wide_for_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
wide_for_count = 0;
for (wide_for_index = 128'hff_00000000_00000000;
wide_for_index < 128'hff_00000000_00000100;
wide_for_index = wide_for_index + 2) begin
wide_for_count = wide_for_count+32'h1;
end
end
// While loop
integer w;
initial begin
while (w<10) w=w+1;
if (w!=10) $stop;
while (w<20) begin w=w+2; end
while (w<20) begin w=w+99999; end // NEVER
if (w!=20) $stop;
end
// Do-While loop
integer dw;
initial begin
do dw=dw+1; while (dw<10);
if (dw!=10) $stop;
do dw=dw+2; while (dw<20);
if (dw!=20) $stop;
do dw=dw+5; while (dw<20); // Once
if (dw!=25) $stop;
end
always @ (posedge clk) begin
cam_lookup_hit_vector <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
cam_lookup_hit_vector <= 64'h00010000_00010000;
end
if (cyc==2) begin
if (hit_count != 32'd2) $stop;
if (hit_count2 != 32'd2) $stop;
if (hit_count3 != 32'd2) $stop;
cam_lookup_hit_vector <= 64'h01010010_00010001;
end
if (cyc==3) begin
if (hit_count != 32'd5) $stop;
if (hit_count2 != 32'd5) $stop;
if (hit_count3 != 32'd4) $stop;
if (wide_for_count != 32'h80) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, cntu[1000006], cntd[1000006], preu[1000006], pred[1000006]; string s; vector<long long> lisu, lisd; int main() { ios::sync_with_stdio(0); cin >> n >> s; lisd.push_back(0); lisu.push_back(0); for (int i = 1; i <= n; i++) { if (s[i - 1] == D ) cntd[i]++; else cntu[i]++; cntd[i] += cntd[i - 1]; cntu[i] += cntu[i - 1]; if (s[i - 1] == D ) pred[i] += i; else preu[i] += i; pred[i] += pred[i - 1]; preu[i] += preu[i - 1]; if (s[i - 1] == D ) { lisd.push_back(lisd.back() + i); } else { lisu.push_back(lisu.back() + i); } } for (int i = 1; i <= n; i++) { if (s[i - 1] == U ) { long long down_after = cntd[n] - cntd[i]; long long up_before = cntu[i - 1]; if (down_after <= up_before) cout << 2 * (pred[n] - pred[i]) + 2 * (-lisu[cntu[i - 1]] + lisu[cntu[i - 1] - down_after]) + n - i + 1 << ; else cout << 2 * (lisd[cntd[i] + up_before + 1] - i - lisd[cntd[i]] - lisu[cntu[i - 1]] + lisu[cntu[i - 1] - up_before]) + i << ; } else { long long down_after = cntd[n] - cntd[i]; long long up_before = cntu[i - 1]; if (up_before <= down_after) cout << 2 * (lisd[cntd[i] + up_before] - lisd[cntd[i]] - lisu[cntu[i - 1]] + lisu[cntu[i - 1] - up_before]) + i << ; else cout << 2 * (lisd[cntd[i] + down_after] - lisd[cntd[i]] - lisu[cntu[i - 1]] + lisu[cntu[i - 1] - down_after - 1] + i) + n - i + 1 << ; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0); string s; cin >> s; sort(s.begin(), s.end()); reverse(s.begin(), s.end()); cout << s[0]; for (long long int(i) = (1); (i) < (s.length()); (i)++) { if (s[i] == s[i - 1]) cout << s[i]; else break; } cout << n ; }
|
`timescale 1ns / 1ps
module cpu_ctl(op,func,equal_result,JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,BJ,Aluc
);
input wire [5:0] op, func;
input wire equal_result;
output wire JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,BJ;
output wire [4:0] Aluc;
wire r_type, i_jr, i_sll, i_srl, i_sra; //i_mfhi,i_mflo,i_mthi,i_mtlo;
wire i_addi,i_andi,i_ori,i_xori,i_slti,i_type,i_lw,i_sw,i_j,i_jal;//i_lh,i_sh,i_mul,i_div,
wire i_beq,i_bgez,i_bgtz,i_blez,i_bltz,i_bne;
/* R_type */
and(r_type,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]);
and(i_jr, r_type, ~func[5], ~func[4], func[3], ~func[2], ~func[1], ~func[0]); //func:001000
and(i_sll, r_type, ~func[5], ~func[4], ~func[3], ~func[2], ~func[1], ~func[0]); //func:000000
and(i_srl, r_type, ~func[5], ~func[4], ~func[3], ~func[2], func[1], ~func[0]); //func:000010
and(i_sra, r_type, ~func[5], ~func[4], ~func[3], ~func[2], func[1], func[0]); //func:000011
/* I_type */
or(i_type, i_addi, i_andi, i_ori, i_xori, i_slti, b_type, i_lw, i_sw );
and(i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); //001000
and(i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]); //001100
and(i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]);
and(i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]);
and(i_slti,~op[5],~op[4], op[3], ~op[2], op[1],~op[0]);
and(i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]);
and(i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]);
/* I_type(B) */
or(b_type, i_beq, i_bgez, i_bgtz, i_blez, i_bltz, i_bne);
and(i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); //000100
and(i_bgez,~op[5],~op[4],~op[3], ~op[2],~op[1],op[0]); //000001
and(i_bgtz,~op[5],~op[4],~op[3], op[2],op[1],op[0]); //000111
and(i_blez,~op[5],~op[4],~op[3], op[2],op[1],~op[0]); //000110
and(i_bltz,~op[5],~op[4],op[3], ~op[2],~op[1],op[0]); //001001
and(i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); //000101
/* J_type */
and(i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]);
and(i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]);
/* JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,AluCtl£¬BJ */
assign JR = i_jr;
assign J = i_j;
assign JAL = i_jal;
assign LW = i_lw;
assign WREG = i_jal | (IorR & ~i_sw) | (r_type & ~i_jr);
assign WMEM = i_sw;
assign RDorRT = r_type & ~i_jr;
assign SE = i_addi | i_lw |i_sw;//i_andi i_ori zero_extend
assign SA = i_sll | i_srl | i_sra;
// assign IR =( r_type | i_type ) & ~i_jr & ~b_type & ~i_lw & ~i_sw;
assign IorR = i_type & ~b_type;
alt_ctl AC(.op(op),.func(func),.aluc(Aluc));
assign BJ = ( i_beq & equal_result ) | ( i_bne & ~equal_result );
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
// simulate the always on register file which holds the assigned address
module mbus_addr_rf(
input RESETn,
`ifdef POWER_GATING
input RELEASE_ISO_FROM_SLEEP_CTRL,
`endif
output reg [`DYNA_WIDTH-1:0] ADDR_OUT,
input [`DYNA_WIDTH-1:0] ADDR_IN,
output reg ADDR_VALID,
input ADDR_WR_EN,
input ADDR_CLRn
);
wire RESETn_local = (RESETn & ADDR_CLRn);
`ifdef POWER_GATING
wire ADDR_UPDATE = (ADDR_WR_EN & (~RELEASE_ISO_FROM_SLEEP_CTRL));
`else
wire ADDR_UPDATE = ADDR_WR_EN;
`endif
always @ (posedge ADDR_UPDATE or negedge RESETn_local)
begin
if (~RESETn_local)
begin
ADDR_OUT <= {`DYNA_WIDTH{1'b1}};
ADDR_VALID <= 0;
end
else
begin
ADDR_OUT <= ADDR_IN;
ADDR_VALID <= 1;
end
end
endmodule
|
#include <bits/stdc++.h> using std::max; using std::min; const int inf = 0x3f3f3f3f, Inf = 0x7fffffff; const long long INF = 0x3f3f3f3f3f3f3f3f; __inline__ __attribute__((always_inline)) unsigned int rnd() { static unsigned int seed = 416; return seed ^= seed >> 5, seed ^= seed << 17, seed ^= seed >> 13; } template <typename _Tp> _Tp gcd(const _Tp &a, const _Tp &b) { return (!b) ? a : gcd(b, a % b); } template <typename _Tp> __inline__ __attribute__((always_inline)) _Tp abs(const _Tp &a) { return a >= 0 ? a : -a; } template <typename _Tp> __inline__ __attribute__((always_inline)) void chmax(_Tp &a, const _Tp &b) { (a < b) && (a = b); } template <typename _Tp> __inline__ __attribute__((always_inline)) void chmin(_Tp &a, const _Tp &b) { (b < a) && (a = b); } template <typename _Tp> __inline__ __attribute__((always_inline)) void read(_Tp &x) { char ch(getchar()); bool f(false); while (!isdigit(ch)) f |= ch == 45, ch = getchar(); x = ch & 15, ch = getchar(); while (isdigit(ch)) x = (((x << 2) + x) << 1) + (ch & 15), ch = getchar(); f && (x = -x); } template <typename _Tp, typename... Args> __inline__ __attribute__((always_inline)) void read(_Tp &t, Args &...args) { read(t); read(args...); } template <typename _Tp, typename... Args> __inline__ __attribute__((always_inline)) _Tp min(const _Tp &a, const _Tp &b, const Args &...args) { return a < b ? min(a, args...) : min(b, args...); } template <typename _Tp, typename... Args> __inline__ __attribute__((always_inline)) _Tp max(const _Tp &a, const _Tp &b, const Args &...args) { return a < b ? max(b, args...) : max(a, args...); } __inline__ __attribute__((always_inline)) int read_str(char *s) { char ch(getchar()); while (ch == || ch == r || ch == n ) ch = getchar(); char *tar = s; *tar = ch, ch = getchar(); while (ch != && ch != r && ch != n && ch != EOF) *(++tar) = ch, ch = getchar(); return tar - s + 1; } const int N = 100005; const int MAXN = 10000005; bool pr[MAXN]; int _p[MAXN >> 3], _pos; int md[MAXN]; void sieve() { for (int i = 2; i < MAXN; ++i) { if (!pr[i]) { _p[++_pos] = i; md[i] = i; } for (int j = 1; j <= _pos && i * _p[j] < MAXN; ++j) { pr[i * _p[j]] = true; md[i * _p[j]] = _p[j]; if (!(i % _p[j])) break; } } } std::vector<int> p[N], d[N]; int c[MAXN], cnt[1 << 8], mul[1 << 8]; int calc(int id) { int siz = ((int)p[id].size()), ans = 0; for (int i = 0; i < siz; ++i) mul[1 << i] = p[id][i]; for (int i = 1; i < 1 << siz; ++i) { cnt[i] = cnt[i >> 1] + (i & 1); mul[i] = mul[i ^ ((i) & (-(i)))] * mul[((i) & (-(i)))]; if (cnt[i] & 1) ans += c[mul[i]]; else ans -= c[mul[i]]; } return ans; } int a[N]; int _val[11], _cnt[11], pos, cur_id; void dfs(int dep, int val) { if (dep == pos + 1) { d[cur_id].push_back(val); return; } for (int i = 0; i <= _cnt[dep]; ++i) { dfs(dep + 1, val); if (i < _cnt[dep]) val *= _val[dep]; } } bool ban[N], vis[N]; int deg[N]; int f(int mid) { while (ban[mid]) --mid; if (!mid) return false; int qwq = 0; for (int i = 1; i <= mid; ++i) if (!ban[i]) { ++qwq; for (auto it : d[i]) ++c[it]; } int ans = 0; for (int i = 1; i <= mid; ++i) if (!ban[i] && calc(i) != qwq) ++ans; for (int i = 1; i <= mid; ++i) if (!ban[i]) for (auto it : d[i]) --c[it]; return ans; } std::vector<int> getnodes(int mid) { while (ban[mid]) --mid; std::vector<int> nd; int qwq = 0; for (int i = 1; i <= mid; ++i) if (!ban[i]) { ++qwq; for (auto it : d[i]) ++c[it]; } for (int i = 1; i <= mid; ++i) if (!ban[i] && calc(i) != qwq) nd.push_back(i); for (int i = 1; i <= mid; ++i) if (!ban[i]) for (auto it : d[i]) --c[it]; return nd; } int main() { mul[0] = 1; sieve(); int n, k; read(n, k); for (int i = 1; i <= n; ++i) { read(a[i]); ++c[a[i]]; int cur = a[i], last = 0; pos = 0; while (cur > 1) { if (md[cur] != last) p[i].push_back(md[cur]), _val[++pos] = md[cur], _cnt[pos] = 1; else ++_cnt[pos]; last = md[cur]; cur /= last; } cur_id = i; dfs(1, 1); } for (int j = 1; j <= _pos; ++j) for (int i = (MAXN - 1) / _p[j]; i >= 1; --i) c[i] += c[i * _p[j]]; std::vector<int> nd; for (int i = 1; i <= n; ++i) { if ((deg[i] = calc(i)) <= n - 2) { nd.push_back(i); for (int j = 1; j <= n && ((int)nd.size()) < 3; ++j) if (i != j && gcd(a[i], a[j]) == 1) nd.push_back(j); break; } } if (nd.empty()) { std::vector<int> clique, rest; for (int i = 1; i <= n; ++i) if (deg[i] == n) clique.push_back(i); else rest.push_back(i); if (((int)clique.size()) > k) clique.resize(k); for (int i = 1; i <= n && ((int)clique.size()) < k; ++i) { if (!vis[i] && deg[i] == n - 1) { clique.push_back(i); for (auto it : rest) if (gcd(a[it], a[i]) == 1) vis[it] = true; } } for (auto it : clique) printf( %d , it); printf( n ); return 0; } assert(((int)nd.size()) == 3); if (k == 3) { for (auto it : nd) printf( %d , it); printf( n ); return 0; } for (auto it : nd) ban[it] = true; for (auto id : nd) for (auto it : d[id]) --c[it]; std::vector<int> clique; for (int i = 1; i <= n; ++i) if (!ban[i] && ((deg[i] = calc(i)) == n - 3)) clique.push_back(i); if (((int)clique.size()) >= k) { clique.resize(k); for (auto it : clique) printf( %d , it); printf( n ); return 0; } memset(c, 0, sizeof(c)); int l = 1, r = n; while (l < r) { int mid = (l + r) >> 1; if (f(mid) + 3 >= k) r = mid; else l = mid + 1; } std::vector<int> v1 = getnodes(l - 1); std::vector<int> v2 = getnodes(l); assert(f(l - 1) == ((int)v1.size())); assert(f(l) == ((int)v2.size())); assert(((int)v1.size()) + 3 < k); assert(((int)v2.size()) + 3 >= k); std::sort(v1.begin(), v1.end()); std::vector<int> qwq; for (auto it : v2) { auto _ = std::lower_bound(v1.begin(), v1.end(), it); if (_ == v1.end() || *_ != it) qwq.push_back(it); } std::sort(qwq.begin(), qwq.end()); assert(((int)v1.size()) + ((int)qwq.size()) == ((int)v2.size())); if (((int)v1.size()) + 3 + 1 == k && ((int)qwq.size()) != 1) v1.push_back(nd[0]), v1.push_back(nd[1]); else v1.push_back(nd[0]), v1.push_back(nd[1]), v1.push_back(nd[2]); while (((int)v1.size()) < k) { v1.push_back(qwq.back()); qwq.pop_back(); } assert(((int)v1.size()) == k); for (auto it : v1) printf( %d , it); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[502][502]; int n, m; int ds[502][502][251]; int dfs(int i, int j, int x, int y, int st) { if (i > x || j > y) { return 0; } if (a[i][j] == * || a[x][y] == * || a[i][j] != a[x][y]) { return 0; } if (ds[i][x][st] != -1) { return ds[i][x][st]; } if ((i == x && j == y - 1) || (i == x - 1 && j == y)) { return 1; } if (i == x && j == y) { return 1; } long long int ans = 0; ans += dfs(i + 1, j, x - 1, y, st + 1); ans %= 1000000007; ans += dfs(i, j + 1, x - 1, y, st + 1); ans %= 1000000007; ans += dfs(i + 1, j, x, y - 1, st + 1); ans %= 1000000007; ans += dfs(i, j + 1, x, y - 1, st + 1); ans %= 1000000007; ds[i][x][st] = ans; return ans; } int main() { cin >> n >> m; for (int i = 0; i < 502; i++) { for (int j = 0; j < 502; j++) { a[i][j] = * ; for (int k = 0; k < 251; k++) { ds[i][j][k] = -1; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } int ans = dfs(1, 1, n, m, 0); ans %= 1000000007; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Z = (int)1e5 + 111; const int inf = (int)1e9 + 111; const long long llinf = (long long)1e18 + 5; const int MOD = (int)1e9 + 7; vector<int> ans[Z]; int a[Z]; pair<int, int> b[Z]; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; b[i].first = a[i]; b[i].second = i; } int cnt = 0; sort(b + 1, b + 1 + n); for (int i = 1; i <= n; ++i) { if (a[i] == -inf) continue; set<int> cur_pos; cur_pos.insert(i); int pos = lower_bound(b + 1, b + 1 + n, make_pair(a[i], -inf)) - b; while (!cur_pos.count(pos)) { int x = pos; cur_pos.insert(pos); pos = lower_bound(b + 1, b + 1 + n, make_pair(a[pos], -inf)) - b; a[x] = -inf; } cnt++; for (int to : cur_pos) { ans[cnt].push_back(to); } } cout << cnt << n ; for (int i = 1; i <= cnt; ++i) { cout << (int)ans[i].size() << ; for (int j = 0; j < (int)ans[i].size(); ++j) { cout << ans[i][j] << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, t; cin >> t; while (t--) { cin >> a >> b; int num = abs(a - b); if (a > b && num % 2 != 0) cout << 2 << endl; else if (a < b && num % 2 != 0) cout << 1 << endl; else if (a > b && num % 2 == 0) cout << 1 << endl; else if (a < b && num % 2 == 0) cout << 2 << endl; else if (a == b) cout << 0 << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ebufn (
VPWR,
VGND,
Z ,
A ,
TE_B
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE_B;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BLACKBOX_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module spi_cfg_tb();
reg aclk;
reg [32-1:0] s_axis_tdata;
reg s_axis_tvalid;
reg [8-1:0] cmd;
wire sclk;
wire [4-1:0] cs;
wire sdi;
wire s_axis_tready;
spi_cfg DUT (
.aclk(aclk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.cmd(cmd),
.cs(cs),
.sdi(sdi),
.sclk(sclk),
.s_axis_tready(s_axis_tready)
);
parameter CLK_PERIOD = 8;
initial begin
aclk = 1;
s_axis_tvalid = 0;
cmd = 8'b000001010;
s_axis_tdata = 32'b11000000000000011110100000000001;
#(100*CLK_PERIOD)
s_axis_tvalid = 1;
#(10*CLK_PERIOD)
s_axis_tvalid = 0;
#(2000*CLK_PERIOD)
cmd = 8'b000001010;
s_axis_tdata = 32'b11101000000000110000000000000001;
#(10*CLK_PERIOD)
s_axis_tvalid = 1;
#(100000*CLK_PERIOD)
$finish;
end
always #(CLK_PERIOD/2) aclk = ~aclk;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
/////////////////////////////////////////////////////////////////////////////////////
//
// Module DESCRAMBLER_64B66B
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
//***********************************Entity Declaration*******************************
module aurora_64b66b_25p4G_DESCRAMBLER_64B66B #
(
parameter SCRAMBLER_SEED = 58'h2AA_AAAA_AAAA_AAAA,
parameter RX_DATA_WIDTH = 64
)
(
// User Interface
SCRAMBLED_DATA_IN,
UNSCRAMBLED_DATA_OUT,
DATA_VALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
input [0:(RX_DATA_WIDTH-1)] SCRAMBLED_DATA_IN;
input DATA_VALID_IN;
output [(RX_DATA_WIDTH-1):0] UNSCRAMBLED_DATA_OUT;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************Internal Register Declarations********************
reg [57:0] descrambler;
integer i;
reg [57:0] poly;
reg [0:(RX_DATA_WIDTH-1)] tempData;
reg [(RX_DATA_WIDTH-1):0] unscrambled_data_i;
reg xorBit;
//*********************************Main Body of Code***************************
always @(descrambler,SCRAMBLED_DATA_IN)
begin
poly = descrambler;
for (i=0;i<=(RX_DATA_WIDTH-1);i=i+1)
begin
xorBit = SCRAMBLED_DATA_IN[i] ^ poly[38] ^ poly[57];
poly = {poly[56:0],SCRAMBLED_DATA_IN[i]};
tempData[i] = xorBit;
end
end
always @(posedge USER_CLK)
begin
if (SYSTEM_RESET)
begin
unscrambled_data_i <= `DLY 'h0;
descrambler <= `DLY SCRAMBLER_SEED;
end
else if (DATA_VALID_IN)
begin
unscrambled_data_i <= `DLY tempData;
descrambler <= `DLY poly;
end
end
//________________ Scrambled Data assignment to output port _______________
assign UNSCRAMBLED_DATA_OUT = unscrambled_data_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int ans[401] = { 0, 1, 9, 245, 126565, 54326037, 321837880, 323252721, 754868154, 328083248, 838314395, 220816781, 893672292, 166441208, 251255697, 114256285, 118775501, 482714697, 11784725, 460862131, 550384565, 106742050, 425241115, 626692854, 674266678, 320014275, 345949512, 527320049, 897822749, 137190263, 491039182, 810384961, 482023334, 658099864, 886790989, 845381174, 371433224, 278969124, 420088324, 696766322, 388302635, 141033366, 46387851, 932125021, 278342766, 371131134, 922501918, 110778457, 506223573, 806353719, 391845991, 923507761, 780307355, 109951115, 830090230, 605558495, 344686604, 988110893, 944684429, 715019947, 799898820, 384672708, 907325090, 758952329, 550672104, 368337206, 394915145, 401744167, 923781939, 831857516, 407845661, 329267374, 927004007, 891609656, 897919613, 481297880, 737337940, 651873737, 287246681, 973133651, 679864988, 784719328, 820504764, 875613823, 806512665, 164851642, 500228957, 951814419, 447763649, 273141670, 979349615, 964027956, 809510400, 276634497, 116631976, 426739449, 175282420, 885948162, 62270880, 974395255, 675165056, 759589968, 837957573, 931897605, 152352780, 585420109, 1772087, 333401718, 898833639, 745874265, 786209423, 691982338, 498790927, 473374639, 274302623, 971280670, 241671319, 13070005, 302088807, 550276351, 436592588, 631667314, 548656698, 730626984, 146295220, 674398632, 400383348, 454138904, 786220712, 118620797, 233440672, 217349271, 274853536, 310607544, 105221205, 769566615, 853585061, 800665807, 695377419, 924327065, 388199705, 551624811, 721435546, 501720515, 308465454, 825369234, 396065729, 451899519, 295058424, 142088952, 473485086, 378771634, 734511215, 462404399, 959198328, 337668263, 794122911, 38911400, 951992982, 472696081, 373904752, 105884826, 630251717, 28980684, 845136347, 353665773, 691661192, 19922354, 231463797, 757917231, 242739918, 979036950, 713722080, 234689388, 2243164, 209872853, 240808787, 539523346, 425797848, 913772061, 224613100, 421742777, 222232478, 92712941, 215137570, 949901408, 274827432, 15162482, 593145989, 274574232, 239282092, 762720192, 804146934, 500629424, 565985054, 81127381, 671811155, 655565571, 890331075, 237994348, 743647404, 667160634, 713914299, 668506729, 741341289, 277636808, 762781382, 14272789, 902864131, 567443405, 149113383, 648844381, 825489976, 933016723, 192288078, 734493315, 240985733, 861817693, 762711459, 525904609, 532463481, 377133989, 620711079, 772561562, 980733194, 227599811, 162774370, 209512798, 787116594, 3509258, 748795368, 378035466, 612938915, 802091952, 857679599, 481748937, 493370392, 358420805, 48301629, 412001241, 463126722, 509578422, 967799131, 994766554, 687287243, 863623583, 771554899, 690911527, 855314994, 923686429, 246862514, 192479791, 133487041, 703444043, 295281758, 801816257, 920762934, 749306433, 973004841, 848644684, 560026478, 952127278, 616654635, 839390326, 975154012, 409583672, 635350249, 343228425, 335331602, 223826406, 952341037, 589677800, 249747234, 555694261, 137143500, 628190328, 461598392, 431912756, 29349807, 759199489, 783281228, 781971312, 915823407, 388508707, 718062705, 27424111, 309999451, 963383322, 831185229, 132910888, 347028136, 850484840, 223055285, 142335980, 144754000, 772005560, 81796039, 167696020, 79454283, 172772542, 201056991, 484957644, 716630285, 763194701, 211505841, 903448791, 926964672, 257752668, 482951716, 411539070, 620249847, 592476107, 170473128, 814662613, 898000271, 57354872, 361106091, 488697643, 889007954, 138725767, 684860983, 36248116, 304610143, 137633385, 413715776, 99010024, 779653665, 100387568, 286328069, 564731826, 621740468, 943513219, 506666491, 249987886, 553719884, 769853086, 337485319, 702455584, 809637762, 755400257, 892290368, 502180086, 364275817, 118162370, 873374339, 261271695, 970132574, 744105500, 434447173, 117975095, 383088393, 625447969, 180281249, 545367713, 133236931, 360175662, 148087453, 806871297, 498529036, 886076476, 65645000, 465138299, 967109895, 331362616, 472283705, 796894900, 199697765, 503759892, 472807906, 187586706, 941198065, 782234442, 57693411, 18678611, 82626204, 395317191, 570588915, 152519440, 449852456, 63696518, 763741345, 878748386, 494317541, 444782633, 93316211, 929164666, 529288371, 165769871, 730546850, 955877127, 994202767, 492009567, 275683011, 415902127, 95725776, 718047399, 786963365, 73091278, 986172399, 174591541, 913259286}; signed main() { int k; scanf( %d , &k); printf( %d , ans[k]); return 0; }
|
module myassert(input clk,
input reset,
input [15:0] data);
property myproperty;
@(posedge clk)
$rose(reset) |-> data == 16'h0;
endproperty
//Assert, cover, and assume property statements
//support begin/end keywords. The else begin/end
//clause below is getting indented improperly.
myassert0: assert property(myproperty) begin
$display("myassert0 was successful");
a;
b;
c;
d;
end // myassert0: assert property (myproperty)
else begin
$fatal("myassert0 was unsuccessful");
end // else: !assert property(myproperty)
if (a) begin
b;
c;
end // if (a)
else begin
o;
end // else: !if(a)
assert (a) begin
o;
end // assert (a)
else begin
o;
end // else: !assert (a)
assert (statement) begin
$display("assertion passed"); //this code is correctly indented
end // assert (statement)
else begin // this whole section should be moved to the left
$error("assertion failed");
end // else: !assert (statement)
//Also, any statements following the assert,
//cover, and assume property statements get
// indented too far to the right.
always @(posedge clk) begin
a;
end // always @ (posedge clk)
endmodule
|
`include "DEF.v"
module register(data1, reg_number1, /*enable1,*/ read1,
data2, reg_number2, /*enable2,*/ read2,
data3, reg_number3, /*enable3,*/ write3,
data4, reg_number4, /*enable1,*/ read4,
data5, reg_number5, /*enable2,*/ read5,
data6, reg_number6, /*enable3,*/ write6,
data7, reg_number7, /*enable1,*/ read7,
data8, reg_number8, /*enable2,*/ read8,
data9, reg_number9, /*enable3,*/ write9,
data10, reg_number10, /*enable1,*/ read10,
data11, reg_number11, /*enable2,*/ read11,
data12, reg_number12, /*enable3,*/ write12,
data13, reg_number13, write13
);
output [31:0] data1, data2, data4, data5, data7, data8, data10, data11;
input [31:0] data3, data6, data9, data12, data13;
input [4:0] reg_number1, reg_number2, reg_number3, reg_number4, reg_number5, reg_number6,
reg_number7, reg_number8, reg_number9, reg_number10, reg_number11, reg_number12,
reg_number13;
//input enable1, enable2, enable3;
input read1, read2, read4, read5, read7, read8, read10, read11;
input write3, write6, write9, write12, write13;
reg signed [31:0] register [31:0];
assign data1 = (/*enable1 &&*/ read1) ? register[reg_number1] : 32'hz;
assign data2 = (/*enable2 &&*/ read2) ? register[reg_number2] : 32'hz;
assign data4 = (/*enable1 &&*/ read4) ? register[reg_number4] : 32'hz;
assign data5 = (/*enable2 &&*/ read5) ? register[reg_number5] : 32'hz;
assign data7 = (/*enable1 &&*/ read7) ? register[reg_number7] : 32'hz;
assign data8 = (/*enable2 &&*/ read8) ? register[reg_number8] : 32'hz;
assign data10 = (/*enable1 &&*/ read10) ? register[reg_number10] : 32'hz;
assign data11 = (/*enable2 &&*/ read11) ? register[reg_number11] : 32'hz;
always @(posedge write3)
begin
//$display("reg%d data:%d\n", reg_number3, data3);
/*
if(data3 === 'bx)
begin
$display("reg%d: %d\n", reg_number3, data3);
$stop;
end
*/
/*
if(reg_number3 === 31)
$display("reg ra data: %d\n", data3);
*/
register[reg_number3] <= data3;
end
always @(posedge write6)
begin
//$display("reg%d data:%d\n", reg_number6, data6);
register[reg_number6] <= data6;
end
always @(posedge write9)
begin
//$display("reg%d data:%d\n", reg_number9, data9);
register[reg_number9] <= data9;
end
always @(posedge write12)
begin
//$display("reg%d data:%d\n", reg_number12, data12);
register[reg_number12] <= data12;
end
always @(posedge write13)
begin
//$display("reg%d data:%d\n", reg_number13, data13);
register[reg_number13] <= data13;
end
endmodule
|
#include <bits/stdc++.h> int a[100001], p[100001], N, Q; int T[2100001], ls[2100001], rs[2100001], n, root[100001]; int end[100001], steps[100001]; int build(int l, int r) { int p = ++n; T[p] = r - l + 1; if (l < r) { int m = l + r >> 1; ls[p] = build(l, m); rs[p] = build(m + 1, r); } return p; } int get_kth(int p, int x) { int l = 1, r = N; while (l < r) { int m = l + r >> 1; if (x <= T[ls[p]]) p = ls[p], r = m; else x -= T[ls[p]], p = rs[p], l = m + 1; } return l; } int P(int p, int x, int w) { int l = 1, r = N, root; T[root = ++n] = T[p] + w; while (l < r) { int m = l + r >> 1; if (x <= m) ls[n] = n + 1, rs[n] = rs[p], p = ls[p], r = m; else rs[n] = n + 1, ls[n] = ls[p], p = rs[p], l = m + 1; T[++n] = T[p] + w; } return root; } int G(int p, int x) { int l = 1, r = N, ans = 0; while (l < r) { int m = l + r >> 1; if (x <= m) p = ls[p], r = m; else ans += T[ls[p]], p = rs[p], l = m + 1; } return ans + T[p]; } int main() { scanf( %d%d , &N, &Q); for (int i = 1; i <= N; i++) scanf( %d , a + i); end[0] = a[1] - 1; steps[0] = 0; for (int i = 1; i < N; i++) { int add = (a[i + 1] - end[i - 1] - 1) / i; end[i] = end[i - 1] + i * add; steps[i] = steps[i - 1] + add; } for (int i = 2; i <= N; i++) p[i] = (p[i - 1] + a[i] - a[i - 1]) % (i - 1); root[N] = build(1, N); for (int i = N; i; i--) { p[i] = get_kth(root[i], p[i] + 1); root[i - 1] = P(root[i], p[i], -1); } while (Q--) { int x, k; scanf( %d%d , &x, &k); if (x < a[1]) { printf( %d n , x); continue; } int belong = std::lower_bound(end + 1, end + N, x) - end; k += steps[belong - 1] + (x - end[belong - 1] - 1) / belong + 1; int ord = (x - end[belong - 1] - 1) % belong + 1; ord = get_kth(root[belong], ord); belong = std::lower_bound(steps + 1, steps + N, k) - steps; printf( %lld n , end[belong - 1] + (long long)(k - steps[belong - 1] - 1) * belong + G(root[belong], ord)); } return 0; }
|
#include <bits/stdc++.h> const int N = 1000005; using namespace std; int n, m, t = 0, tot = 0, cnt = 0, q[N]; int dl[N], dr[N], vis[N][27]; int edge[N], nxt[N], lst[N], pt[N], fail[N], val[N], nm[N], vvis[N]; string s; struct nn { int lx, rx, num; } tr[N << 2]; void add(int x, int y) { edge[++t] = y; nxt[t] = lst[x]; lst[x] = t; } void insert(string s, int id) { int len = s.length(), pos = 0; for (int i = 0; i < len; i++) { int c = s[i] - a + 1; if (!vis[pos][c]) tot++, vis[pos][c] = tot; pos = vis[pos][c]; } pt[id] = pos; val[pos] = 1; } void build_trie() { int pos = 0, l = 0, r = 0; for (int i = 1; i <= 26; i++) if (vis[pos][i]) { r++; q[r] = vis[pos][i]; fail[vis[pos][i]] = pos; add(pos, vis[pos][i]); } while (l < r) { l++; pos = q[l]; for (int i = 1; i <= 26; i++) { if (vis[pos][i]) { int f = fail[pos]; while (f && !vis[f][i]) f = fail[f]; fail[vis[pos][i]] = vis[f][i]; add(vis[f][i], vis[pos][i]); r++; q[r] = vis[pos][i]; } else vis[pos][i] = vis[fail[pos]][i]; } } } void build_tree(int x, int num) { cnt++; dl[x] = dr[x] = cnt; nm[dl[x]] = num; for (int r = lst[x]; r; r = nxt[r]) { build_tree(edge[r], num + val[edge[r]]); dr[x] = max(dr[x], dr[edge[r]]); } } void chang(int x, int l, int r, int l1, int r1, int yh) { if (l1 <= l && r <= r1) { tr[x].num += yh; return; } int mid = (l + r) >> 1; if (l1 > mid) chang(tr[x].rx, mid + 1, r, l1, r1, yh); else if (r1 <= mid) chang(tr[x].lx, l, mid, l1, r1, yh); else { chang(tr[x].lx, l, mid, l1, mid, yh); chang(tr[x].rx, mid + 1, r, mid + 1, r1, yh); } return; } void build_segtree(int x, int l, int r) { if (l == r) { tr[x].num = nm[l]; return; } int mid = (l + r) >> 1; tr[x].lx = x + 1; tr[x].rx = (mid - l + 1) * 2 + x; build_segtree(tr[x].lx, l, mid); build_segtree(tr[x].rx, mid + 1, r); } int chk(int x, int l, int r, int goal) { int res = 0; if (l == r) return tr[x].num; res += tr[x].num; int mid = (l + r) >> 1; if (goal > mid) return res + chk(tr[x].rx, mid + 1, r, goal); return res + chk(tr[x].lx, l, mid, goal); } int search(string s) { int len = s.length(), pos = 0, ans = 0; for (int i = 1; i < len; i++) { int c = s[i] - a + 1; pos = vis[pos][c]; ans += chk(1, 1, cnt, dl[pos]); } return ans; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { cin >> s; insert(s, i); } build_trie(); build_tree(0, 0); build_segtree(1, 1, cnt); for (int i = 1; i <= n; i++) { cin >> s; if (s[0] == - || s[0] == + ) { int yh = 0, len = s.length(); for (int i = 1; i < len; i++) { yh = yh * 10 + s[i] - 0 ; } if (s[0] == - ) if (vvis[yh] == 0) chang(1, 1, cnt, dl[pt[yh]], dr[pt[yh]], -1), vvis[yh] = 1; if (s[0] == + ) if (vvis[yh] == 1) chang(1, 1, cnt, dl[pt[yh]], dr[pt[yh]], 1), vvis[yh] = 0; } else { printf( %d n , search(s)); } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 10, MAXM = 2e5 + 10; pair<int, int> v[MAXM]; int l[MAXM], r[MAXM], s[MAXM], t[MAXM]; vector<int> qv[MAXM]; bool ans[MAXM]; int last[MAXN][MAXN]; int main() { int n, m, q; scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= m; i++) scanf( %d %d , &v[i].first, &v[i].second); for (int i = 0; i < q; i++) scanf( %d %d %d %d , l + i, r + i, s + i, t + i), qv[l[i]].push_back(i); for (int i = 0; i <= n; i++) for (int k = 0; k <= n; k++) last[i][k] = m + 1; for (int time = m; time > 0; time--) { int x, y; x = v[time].first, y = v[time].second; last[x][y] = last[y][x] = time; for (int vx = 1; vx <= n; vx++) { if (last[x][vx] < last[y][vx]) last[y][vx] = last[x][vx]; else last[x][vx] = last[y][vx]; } for (int ix : qv[time]) ans[ix] = (last[s[ix]][t[ix]] <= r[ix]); } for (int i = 0; i < q; i++) if (ans[i]) printf( Yes n ); else printf( No n ); }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; double b[10], a[10], c[10] = {500, 1000, 1500, 2000, 2500}; double Max(double x, double y) { return x > y ? x : y; } int main() { int n, m1, m2, m3, m4, m5, i, j, k; while (~scanf( %lf , &a[0])) { for (i = 1; i < 5; i++) scanf( %lf , &a[i]); for (i = 0; i < 5; i++) scanf( %lf , &b[i]); double ans = 0; for (i = 0; i < 5; i++) { ans += Max(0.3 * c[i], (1 - (a[i] * 1.0 / (250 * 1.0))) * c[i] - 50 * b[i]); } int x, y; scanf( %d %d , &x, &y); ans += x * 100; ans -= y * 50; printf( %.0lf n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 4e5 + 5; const int MAXM = 2e5 + 5; const int MOD = 998244353; const int INF = 0x3f3f3f3f; int a[MAXN], sum[MAXN]; vector<int> v; map<int, int> mp; int main() { int n, I; scanf( %d%d , &n, &I); mp.clear(); memset(sum, 0, sizeof(sum)); int B = I * 8; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); if (mp.find(a[i]) == mp.end()) { mp[a[i]] = 1; } else { ++mp[a[i]]; } v.emplace_back(a[i]); } sort(a + 1, a + n + 1); sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); int sz = v.size(), K; for (int i = sz; i >= 1; --i) { if (n * int(ceil(log2(i))) <= B) { K = i; break; } } for (int i = 0; i < sz; ++i) { if (i == 0) sum[i] = mp[v[i]]; else sum[i] = sum[i - 1] + mp[v[i]]; } int ans = n, tmp = 0; for (int i = 0; i <= max(sz - K, 0); ++i) { tmp = 0; if (i != 0) tmp += sum[i - 1]; tmp += sum[sz - 1] - sum[min(i + K - 1, sz - 1)]; ans = min(tmp, ans); } printf( %d n , ans); return 0; }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocm_mem.v
*
* Date : 2012-11
*
* Description : Mimics OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocm_mem();
`include "processing_system7_bfm_v2_0_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
rd_data = ocm_memory[addr];
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; const long double eps = 1e-07; int n, m; int a[2000]; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { int x, y; scanf( %d %d , &x, &y); ++a[x]; ++a[y]; } for (int i = 0; i < n; ++i) if (a[i + 1] == 0) { printf( %d n , n - 1); for (int j = 1; j <= n; ++j) { if (j != (i + 1)) printf( %d %d n , i + 1, j); } return 0; } return 0; }
|
module xyz (/*AUTOARG*/
// Inputs
signal_e, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire signal_c; // From u_abc of abc.v
wire signal_f; // From u_def of def.v
// End of automatics
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e})); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e
);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; vector<int> ind; int num = 0, add = 0; for (int i = 0; i < n; ++i) { if (a[i] == i) ++num; else if (a[a[i]] == i) add = 2; } if (!add) add = 1; if (num == n) add = 0; cout << num + add << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_1_V
`define SKY130_FD_SC_HD__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_1_V
|
#include <bits/stdc++.h> using namespace std; int a[17][17]; int main() { int n, m, k, need; scanf( %d%d%d%d , &n, &m, &k, &need); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { int x, y; scanf( %d%d , &x, &y); a[x][y] = 1; } } int ans = 0; for (int x1 = 1; x1 <= n; x1++) { for (int y1 = 1; y1 <= m; y1++) { for (int x2 = x1; x2 <= n; x2++) { for (int y2 = 1; y2 <= m; y2++) { int tot = 0; for (int x = x1; x <= x2; x++) { for (int y = y1; y <= y2; y++) { tot += a[x][y]; } } if (tot >= need) ans++; } } } } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int N = 303; int n; bool eq[N][N]; int dp[N][N]; string s[N]; int main() { cin >> n; int allsum = n - 1; for (int i = 0; i < n; ++i) { cin >> s[i]; allsum += s[i].size(); } for (int i = 0; i < n; ++i) { eq[i][i] = true; for (int j = 0; j < i; ++j) eq[i][j] = eq[j][i] = s[i] == s[j]; } for (int i = n - 1; i >= 0; --i) { for (int j = n - 1; j >= 0; --j) { if (eq[i][j]) { if (i + 1 < n && j + 1 < n) dp[i][j] = dp[i + 1][j + 1] + 1; else dp[i][j] = 1; } } } int ans = allsum; for (int i = 0; i < n; ++i) { int sum = 0; for (int j = 0; i + j < n; ++j) { sum += s[i + j].size(); int cnt = 1; for (int pos = i + j + 1; pos < n; ++pos) { if (dp[i][pos] > j) { ++cnt; pos += j; } } int cur = allsum - sum * cnt + (j + 1) * cnt - j * cnt; if (cnt > 1 && ans > cur) { ans = cur; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10, MAXM = 2e6 + 10, INF = INT_MAX; const int MOD = 1e9 + 7, mod = 998244353; char s[MAXN]; char p[] = twone ; char k[] = two ; char z[] = one ; int main() { int t; scanf( %d , &t); while (t--) { scanf( %s , s + 1); vector<int> ans; int sz = strlen(s + 1); for (int i = 1; i <= sz; i++) { if (s[i] == o ) { if (i > 2 && i < sz - 1) { bool f = 0; for (int j = 0; j < 5; j++) { if (s[i - 2 + j] != p[j]) f = 1; } if (!f) { ans.push_back(i); continue; } } if (i < sz - 1) { bool f = 0; for (int j = 0; j < 3; j++) if (s[i + j] != z[j]) f = 1; if (!f) { ans.push_back(i + 1); continue; } } if (i > 2) { bool f = 0; for (int j = 0; j < 3; j++) if (s[i - 2 + j] != k[j]) f = 1; if (!f) { ans.push_back(i - 1); continue; } } } } printf( %d n , (int)ans.size()); for (auto j : ans) printf( %d , j); puts( ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
`define SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; template <class T> struct RMQ { const int STEP_P = 5; const int STEP = 1 << STEP_P; vector<T> data; const T INF; vector<vector<T> > small_powers; vector<vector<T> > group_powers; int N; RMQ(vector<T> data_, T INF_) : data(data_), INF(INF_){}; void init() { N = int((data).size()); small_powers = vector<vector<T> >(STEP_P + 1, vector<T>(N)); small_powers[0] = data; for (int p = (0); p < (STEP_P); p++) for (int n = (0); n < (N); n++) { small_powers[p + 1][n] = min(small_powers[p][n], small_powers[p][min(n + (1 << p), N - 1)]); } int GN = (N + STEP - 1) / STEP; int GP = 1; while (GN > (1 << GP)) ++GP; group_powers = vector<vector<T> >(GP + 1, vector<T>(GN)); for (int i = (0); i < (GN); i++) group_powers[0][i] = small_powers[STEP_P][i << STEP_P]; for (int p = (0); p < (GP); p++) for (int n = (0); n < (GN); n++) { group_powers[p + 1][n] = min(group_powers[p][n], group_powers[p][min(n + (1 << p), GN - 1)]); } } int largest_bit(int n) { return 31 - __builtin_clz(max(1, n - 1)); } T query(int f, int t) { assert(f >= 0 && t <= N); if (f >= t) return INF; int p = min(STEP_P, largest_bit(t - f)); auto res = min(small_powers[p][f], small_powers[p][t - (1 << p)]); if (t - f > STEP + STEP) { int g_f = f / STEP + 1, g_t = t / STEP; p = largest_bit(g_t - g_f); res = min(res, min(group_powers[p][g_f], group_powers[p][g_t - (1 << p)])); } return res; } }; const int MAXN = 5e5; int A[MAXN]; vector<int> adj[MAXN]; vector<long long> dp_only[MAXN]; vector<long long> dp_not[MAXN]; long long dp_all[MAXN]; int todo[MAXN]; int xo[MAXN]; long long cost[MAXN]; int etox[MAXN][2]; int edgeval[MAXN][2]; int N, Q; long long calc_not(int n, int eid) { int xid = etox[eid][0]; if (int((adj[n]).size()) <= xid || adj[n][xid] != eid) xid = etox[eid][1]; if (dp_not[n][xid] == -1) { if (dp_all[n] == -1) { dp_all[n] = A[n]; todo[n] = xid; for (int i = (0); i < (int((adj[n]).size())); i++) if (i != xid) { int neid = adj[n][i]; dp_only[n][i] = max(0ll, calc_not(xo[neid] ^ n, neid) - cost[neid] * 2ll); dp_all[n] += dp_only[n][i]; } dp_not[n][xid] = dp_all[n]; } else if (todo[n] != -1) { int neid = adj[n][todo[n]]; dp_only[n][todo[n]] = max(0ll, calc_not(xo[neid] ^ n, neid) - cost[neid] * 2ll); dp_all[n] += dp_only[n][todo[n]]; assert(dp_only[n][xid] != -1); dp_not[n][xid] = dp_all[n] - dp_only[n][xid]; todo[n] = -1; } else { assert(dp_only[n][xid] != -1); dp_not[n][xid] = dp_all[n] - dp_only[n][xid]; } } return dp_not[n][xid]; } long long calc_only(int n, int eid) { int xid = etox[eid][0]; if (adj[n][xid] != eid) xid = etox[eid][1]; assert(adj[n][xid] == eid); assert(dp_only[n][xid] != -1); return dp_only[n][xid]; } int parent_edge[MAXN]; int depth[MAXN]; long long dp_acc[MAXN]; pair<int, int> tmp_rmqdata[MAXN * 2]; int rmqposition[MAXN]; int TMP_RMQDATA; void calc_accumulate(int n) { rmqposition[n] = TMP_RMQDATA; tmp_rmqdata[TMP_RMQDATA++] = make_pair(depth[n], n); for (auto eid : adj[n]) if (eid != parent_edge[n]) { int to = xo[eid] ^ n; dp_acc[to] = dp_acc[n] - calc_only(n, eid) - cost[eid] + calc_not(to, eid); depth[to] = depth[n] + 1; parent_edge[to] = eid; calc_accumulate(to); tmp_rmqdata[TMP_RMQDATA++] = make_pair(depth[n], n); } } int main() { ios::sync_with_stdio(false); cin >> N >> Q; for (int i = (1); i < (N + 1); i++) cin >> A[i]; for (int i = (0); i < (N + 1); i++) adj[i].clear(); for (int i = (1); i < (N); i++) { int a, b; long long c; cin >> a >> b >> c; etox[i][0] = int((adj[a]).size()); etox[i][1] = int((adj[b]).size()); adj[a].push_back(i); adj[b].push_back(i); xo[i] = a ^ b; cost[i] = c; edgeval[i][0] = a; edgeval[i][1] = b; } for (int i = (1); i < (N + 1); i++) dp_not[i] = dp_only[i] = vector<long long>(int((adj[i]).size()), -1); for (int i = (1); i < (N + 1); i++) dp_all[i] = -1; for (int i = (1); i < (N + 1); i++) for (auto e : adj[i]) calc_not(i, e); for (int n = (1); n < (N + 1); n++) { assert(dp_all[n] != -1); if (todo[n] != -1) { int neid = adj[n][todo[n]]; dp_only[n][todo[n]] = max(0ll, calc_not(xo[neid] ^ n, neid) - cost[neid] * 2ll); dp_all[n] += dp_only[n][todo[n]]; todo[n] = -1; } for (int i = (0); i < (int((adj[i]).size())); i++) assert(dp_only[n][i] != -1); for (int i = (0); i < (int((adj[i]).size())); i++) assert(dp_not[n][i] != -1); } parent_edge[1] = -1; dp_acc[1] = dp_all[1]; depth[1] = 0; TMP_RMQDATA = 0; calc_accumulate(1); vector<pair<int, int> > rmqdata(tmp_rmqdata, tmp_rmqdata + TMP_RMQDATA); cerr << TMP_RMQDATA << endl; RMQ<pair<int, int> > rmq(rmqdata, make_pair(N + 1, N + 1)); rmq.init(); for (int q = (0); q < (Q); q++) { int a, b; cin >> a >> b; if (rmqposition[b] < rmqposition[a]) swap(a, b); int lc = rmq.query(rmqposition[a], rmqposition[b] + 1).second; assert(lc > 0 && lc <= N); long long ares = dp_acc[a] + dp_acc[b] - 2 * dp_acc[lc] + dp_all[lc]; cout << ares << endl; } return 0; for (int i = (1); i < (N + 1); i++) { cout << i << : all= << dp_all[i]; for (auto eid : adj[i]) { cout << ( << i << -> << (xo[eid] ^ i) << ):not= << calc_not(i, eid) << only= << calc_only(i, eid); } cout << endl; } for (int i = (1); i < (N + 1); i++) { cout << i << dp= << dp_acc[i] << depth= << depth[i]; if (parent_edge[i] != -1) cout << parent= << (xo[parent_edge[i]] ^ i); cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_SYMBOL_V
`define SKY130_FD_SC_MS__MUX4_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux4 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_BEHAVIORAL_PP_V
|
/**************************************************************************
UART Transmitter Module
-Clock Rate
x4
-parameter BAUDRATE_COUNTER
Uart Baudrate Parameter (Clock / Baudrate)/4-1
BAUDRATE_COUNTER is must be greater than 4. (BAUDRATE_COUNTER >= 20'h4)
Example : Clock : 50MHz
9600bps : 13'd1301
115.2Kbps : 13'd108
-SDF Settings
Asynchronus Clock : b_bd_clock
-Make : 2013/2/21
-Update : 2013/10/13
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_uart_transmitter #(
parameter BAUDRATE_FIXED = 1'b1, //0:Use iEXTBAUD_COUNT | 1:Use Parameter BAUDRATE_COUNTER
parameter BAUDRATE_COUNTER = 20'd108 //(Clock / Baudrate) / 4 - 1
)(
//Clock
input wire iCLOCK,
input wire inRESET,
//External Baudrate Timing
input wire [19:0] iEXTBAUD_COUNT,
//Request
input wire iTX_REQ,
output wire oTX_BUSY,
input wire [7:0] iTX_DATA,
//UART
output wire oUART_TXD
);
/**************************************************************
Parameter & Wire & Register
**************************************************************/
localparam TXD_IDLE = 1'h0;
localparam TXD_WORKING = 1'h1;
localparam IF_IDLE = 2'h0;
localparam IF_START = 2'h1;
localparam IF_WORKING = 2'h2;
//Interface Latch
reg [1:0] b_if_state;
reg [7:0] b_if_data;
reg b_if_start;
//Metastable Cancel
wire dflipflop_if_start;
//Async 2 Sync
wire async2sync_if_start;
//TxD Module
reg b_txd_state;
reg [5:0] b_txd_counter;
reg b_txd_ack;
reg b_txd_end;
//Baudrate
reg [19:0] b_bd_wait_counter;
reg b_bd_clock;
/**************************************************************
Interface
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_start <= 1'b0;
end
else begin
case(b_if_state)
IF_IDLE:
begin
if(iTX_REQ)begin
b_if_state <= IF_START;
b_if_data <= iTX_DATA;
b_if_start <= 1'b1;
end
end
IF_START:
begin
if(b_txd_ack)begin
b_if_state <= IF_WORKING;
b_if_start <= 1'b0;
end
end
IF_WORKING:
begin
if(b_txd_end)begin
b_if_state <= IF_IDLE;
end
end
endcase
end
end
/**************************************************************
TxD Module
**************************************************************/
function func_txd;
input [3:0] func_counter;
input [7:0] func_data;
begin
case(func_counter)
4'h0: func_txd = 1'b0;
4'h1: func_txd = func_data[0];
4'h2: func_txd = func_data[1];
4'h3: func_txd = func_data[2];
4'h4: func_txd = func_data[3];
4'h5: func_txd = func_data[4];
4'h6: func_txd = func_data[5];
4'h7: func_txd = func_data[6];
4'h8: func_txd = func_data[7];
default: func_txd = 1'b1;
endcase
end
endfunction
//Metastable Cancel
mist1032sa_uart_transmitter_double_flipflop #(1) DOUBLE_FLIPFLOP(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Input
.iREQ_DATA(b_if_start),
//Output
.oOUT_DATA(dflipflop_if_start)
);
//Async 2 Sync
mist1032sa_uart_transmitter_async2sync #(1) ASYNC2SYNC(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Ena-Signal
.iSIGNAL(dflipflop_if_start),
.oSIGNAL(async2sync_if_start)
);
//State
always@(posedge b_bd_clock or negedge inRESET)begin
if(!inRESET)begin
b_txd_state <= TXD_IDLE;
b_txd_counter <= 6'h0;
b_txd_ack <= 1'b0;
b_txd_end <= 1'b0;
end
else begin
case(b_txd_state)
TXD_IDLE:
begin
if(async2sync_if_start)begin
b_txd_state <= TXD_WORKING;
b_txd_ack <= 1'b1;
end
b_txd_counter <= 6'h0;
b_txd_end <= 1'b0;
end
TXD_WORKING:
begin
b_txd_ack <= 1'b0;
if(b_txd_counter == 6'd36)begin
b_txd_state <= TXD_IDLE;
b_txd_end <= 1'b1;
end
else begin
b_txd_counter <= b_txd_counter + 6'h1;
end
end
endcase
end
end
/**************************************************************
Baudrate Clock
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b0;
end
else begin
if((BAUDRATE_FIXED && b_bd_wait_counter == BAUDRATE_COUNTER) || (!BAUDRATE_FIXED && b_bd_wait_counter == iEXTBAUD_COUNT))begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b1;
end
else begin
b_bd_wait_counter <= b_bd_wait_counter + 20'h1;
b_bd_clock <= 1'b0;
end
end
end
/**************************************************************
Assign
**************************************************************/
assign oUART_TXD = (b_txd_state == TXD_WORKING)? func_txd(b_txd_counter[5:2], b_if_data) : 1'b1;
assign oTX_BUSY = (b_if_state == IF_IDLE)? 1'b0 : 1'b1;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; struct row { long long base, limit; row(long long t = 0, long long d = 0) : base(t + d), limit(t) {} long long push(long long t) const { return t <= limit ? base : base + (t - limit); } row operator*(const row &o) const { row ans; ans.base = o.push(base); ans.limit = limit; if (o.limit > base) ans.limit += o.limit - base; return ans; } }; struct query { char op; int t, d; } qs[N]; row ZERO(0, 0); row st[1 << 20]; vector<int> ts; int sz; void init() { for (int i = sz - 1; i >= 1; i--) st[i] = st[i + i] * st[i + i + 1]; } void upd(int t, int d) { int pos = lower_bound(ts.begin(), ts.end(), t) - ts.begin(); int u = sz + pos; st[u] = row(t, d); while (u > 1) { u /= 2; st[u] = st[u + u] * st[u + u + 1]; } } void del(int t) { int pos = lower_bound(ts.begin(), ts.end(), t) - ts.begin(); int u = sz + pos; st[u] = ZERO; while (u > 1) { u /= 2; st[u] = st[u + u] * st[u + u + 1]; } } long long query(long long t) { int l = 0, r = upper_bound(ts.begin(), ts.end(), t) - ts.begin(); l += sz; r += sz; auto L = ZERO, R = ZERO; while (l < r) { if (l & 1) L = L * st[l++]; if (r & 1) R = st[--r] * R; l /= 2; r /= 2; } return max(0LL, (L * R).push(0) - t); } int main() { int q; cin >> q; for (int i = 0; i < q; i++) { cin >> qs[i].op >> qs[i].t; if (qs[i].op == + ) { cin >> qs[i].d; ts.push_back(qs[i].t); } } sort(ts.begin(), ts.end()); ts.erase(unique(ts.begin(), ts.end()), ts.end()); sz = ts.size(); while (sz & (sz - 1)) sz++; fill_n(st, sz, ZERO); for (int i = 0; i < q; i++) { auto qi = qs[i]; if (qi.op == + ) upd(qi.t, qi.d); else if (qi.op == - ) { auto prev = qs[qi.t - 1]; del(prev.t); } else cout << query(qi.t) << n ; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:58:43 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/system_vga_buffer_0_0_stub.v
// Design : system_vga_buffer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_0_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_2_V
`define SKY130_FD_SC_MS__O22AI_2_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_SYMBOL_V
`define SKY130_FD_SC_MS__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:35:10 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_stub.v
// Design : design_1_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 100005; struct ban { long long s, a, b; }; bool operator<(const ban& a, const ban& b) { return (a.a - a.b) > (b.a - b.b); } int n; long long s; ban a[N]; long long sum; long long ans; int main() { ios_base::sync_with_stdio(false); cin >> n >> s; for (int i = 0; i < n; ++i) { cin >> a[i].s >> a[i].a >> a[i].b; sum += a[i].s; } sort(a, a + n); long long t = 0; for (int i = 0; i < n; ++i) { if (a[i].a - a[i].b > 0) t += a[i].s; } long long yans = 0; for (int i = 0; i < n; ++i) { if (a[i].a - a[i].b > 0) yans += (a[i].a * a[i].s); } long long tt = (((sum / s) + !!(sum % s)) - ((t / s) + !!(t % s))) * s; for (int i = n - 1; i >= 0; --i) { if (a[i].a - a[i].b <= 0) { if (tt > a[i].s) { tt -= a[i].s; yans += (a[i].b * a[i].s); } else { yans += (a[i].b * tt); yans += (a[i].a * (a[i].s - tt)); tt = 0; } } } ans = yans; t = 0; for (int i = n - 1; i >= 0; --i) { if (a[i].b - a[i].a > 0) t += a[i].s; } yans = 0; for (int i = n - 1; i >= 0; --i) { if (a[i].b - a[i].a > 0) yans += (a[i].b * a[i].s); } tt = (((sum / s) + !!(sum % s)) - ((t / s) + !!(t % s))) * s; for (int i = 0; i < n; ++i) { if (a[i].b - a[i].a <= 0) { if (tt > a[i].s) { tt -= a[i].s; yans += (a[i].a * a[i].s); } else { yans += (a[i].a * tt); yans += (a[i].b * (a[i].s - tt)); tt = 0; } } } ans = max(ans, yans); cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; vector<pair<long long, long long> > arr; long long n = s.length(); for (int i = 0; i < n; i++) { for (int j = 1; i + (2 * j) < n; j++) { if (s[i] == s[i + j] && s[i] == s[i + (2 * j)]) { arr.push_back(make_pair(i + (2 * j), i)); break; } } } sort(arr.begin(), arr.end()); long long cnt = 0; for (int i = 0, j = 0; i < n; i++) { while (j < arr.size() && arr[j].second < i) j++; if (j == arr.size()) break; cnt += (n - arr[j].first); } cout << cnt << endl; }
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#include <bits/stdc++.h> using namespace std; string s; int stx, sty, i; int f[2000][2000]; int main() { cin >> s; stx = 100; sty = 100; f[stx][sty] = 1; for (i = 0; i < s.size(); i++) { if (s[i] == U ) stx--; if (s[i] == D ) stx++; if (s[i] == L ) sty--; if (s[i] == R ) sty++; f[stx][sty]++; if (f[stx - 1][sty] + f[stx + 1][sty] + f[stx][sty - 1] + f[stx][sty + 1] + f[stx][sty] >= 3) { cout << BUG << endl; return 0; } } cout << OK << endl; }
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#include <bits/stdc++.h> using namespace std; void dfs(long long a, vector<long long>& d, vector<vector<long long>>& adj, vector<long long>& vis, long long dist) { d[a] = dist; vis[a]++; for (auto b : adj[a]) { if (!vis[b]) { dfs(b, d, adj, vis, dist + 1); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n, a, b, da, db; cin >> n >> a >> b >> da >> db; vector<vector<long long>> adj(n + 1); for (long long i = 0; i < n - 1; i++) { long long u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } if (da * 2 >= db) { cout << Alice n ; continue; } vector<long long> d(n + 1); vector<long long> vis(n + 1); dfs(b, d, adj, vis, 0); if (d[a] <= da) { cout << Alice n ; continue; } long long mx = 0; for (long long i = 1; i < n + 1; i++) { mx = max(mx, d[i]); } vector<long long> d2(n + 1); vector<long long> vis2(n + 1); for (long long i = 1; i < n + 1; i++) { if (d[i] == mx) { dfs(i, d2, adj, vis2, 0); break; } } long long mx2 = 0; for (long long i = 1; i < n + 1; i++) { mx2 = max(mx2, d2[i]); } long long di = mx2; if (di > 2 * da) cout << Bob n ; else cout << Alice n ; } return 0; }
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