text
stringlengths 59
71.4k
|
|---|
module i2s_audio
(
input bus_clk,
input quiesce,
input clk_100,
output reg audio_mclk,
output reg audio_dac,
input audio_adc,
input audio_bclk,
input audio_lrclk,
input user_w_audio_wren,
input [31:0] user_w_audio_data,
output user_w_audio_full,
input user_w_audio_open,
input user_r_audio_rden,
output [31:0] user_r_audio_data,
output user_r_audio_empty,
output user_r_audio_eof,
input user_r_audio_open
);
reg audio_adc_reg;
reg audio_bclk_reg;
reg audio_lrclk_reg;
reg audio_lrclk_reg_d;
reg [1:0] clk_div;
reg [15:0] play_shreg;
reg [1:0] bclk_d;
reg fifo_rd_en;
wire bclk_rising, bclk_falling;
wire [31:0] play_fifo_data;
reg [31:0] record_shreg;
reg [4:0] record_count;
reg write_when_done;
reg fifo_wr_en;
// synthesis attribute IOB of audio_mclk is TRUE
// synthesis attribute IOB of audio_dac is TRUE
// synthesis attribute IOB of audio_adc_reg is TRUE
// synthesis attribute IOB of audio_bclk_reg is TRUE
// synthesis attribute IOB of audio_lrclk_reg is TRUE
assign user_r_audio_eof = 0;
// Produce a 25 MHz clock for MCLK
always @(posedge clk_100)
begin
clk_div <= clk_div + 1;
audio_mclk <= clk_div[1];
end
assign bclk_rising = (bclk_d == 2'b01);
assign bclk_falling = (bclk_d == 2'b10);
// BCLK runs at 3.072 MHz, so the signals are sampled and handled
// synchronously, with an obvious delay, which is negligble compared
// with a BCLK clock cycle.
always @(posedge bus_clk)
begin
audio_adc_reg <= audio_adc;
audio_bclk_reg <= audio_bclk;
audio_lrclk_reg <= audio_lrclk;
bclk_d <= { bclk_d, audio_bclk_reg };
if (bclk_rising)
audio_lrclk_reg_d <= audio_lrclk_reg;
// Playback
fifo_rd_en <= 0; // Possibly overridden below
if (bclk_rising && !audio_lrclk_reg && audio_lrclk_reg_d)
play_shreg <= play_fifo_data[31:16]; // Left channel
else if (bclk_rising && audio_lrclk_reg && !audio_lrclk_reg_d)
begin
play_shreg <= play_fifo_data[15:0]; // Right channel
fifo_rd_en <= 1;
end
else if (bclk_falling)
begin
audio_dac <= play_shreg[15];
play_shreg <= { play_shreg, 1'b0 };
end
// Recording
fifo_wr_en <= 0; // Possibly overridden below
if (bclk_rising && (record_count != 0))
begin
record_shreg <= { record_shreg, audio_adc_reg };
record_count <= record_count - 1;
if (record_count == 1)
begin
fifo_wr_en <= write_when_done;
write_when_done <= 0;
end
end
if (bclk_rising && !audio_lrclk_reg && audio_lrclk_reg_d)
begin
record_count <= 16;
write_when_done <= 0;
end
else if (bclk_rising && audio_lrclk_reg && !audio_lrclk_reg_d)
begin
record_count <= 16;
write_when_done <= 1;
end
end
// Note that there is no check on the empty line. If the FIFO is empty,
// it will emit the same output all the time, so the audio output will be
// silent, which is fairly OK for an underrun.
fifo_32x512 playback_fifo
(
.clk(bus_clk),
.srst(!user_w_audio_open),
.din(user_w_audio_data), // Bus [31 : 0]
.wr_en(user_w_audio_wren),
.rd_en(fifo_rd_en),
.dout(play_fifo_data), // Bus [31 : 0]
.full(user_w_audio_full),
.empty());
// The full lines isn't checked. Not much to do on an overrun
fifo_32x512 record_fifo
(
.clk(bus_clk),
.srst(!user_r_audio_open),
.din(record_shreg), // Bus [31 : 0]
.wr_en(fifo_wr_en),
.rd_en(user_r_audio_rden),
.dout(user_r_audio_data), // Bus [31 : 0]
.full(),
.empty(user_r_audio_empty));
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module array_io_acc_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./array_io_acc_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module array_io_acc(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
array_io_acc_ram array_io_acc_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dp[200000][3]; string s; signed main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); cin >> s; long long l = s.size(); vector<vector<bool> > in(l, vector<bool>(3)); dp[0][0] = dp[0][1] = dp[0][2] = 10000000000; if ((s[0] - 0 ) % 3 == 0) { dp[0][0] = 0; in[0][0] = 1; } else { long long d = (s[0] - 0 ) % 3; dp[0][d] = 0; in[0][d] = 1; dp[0][0] = 1; } for (long long i = 1; i < l; i++) { long long d = (s[i] - 0 ) % 3; for (long long j = 0; j < 3; j++) { if (s[i] != 0 ) dp[i][j] = min(dp[i - 1][(j + 3 - d) % 3], dp[i - 1][j] + 1), in[i][j] = (dp[i][j] != dp[i - 1][j] + 1); else { dp[i][j] = dp[i - 1][j] + (dp[i - 1][j] == i); in[i][j] = (dp[i - 1][j] != i); } } } if (dp[l - 1][0] == l) { for (long long i = 0; i < l; i++) { if (s[i] == 0 ) return cout << 0 n , 0; } return cout << -1, 0; } string ans = ; long long sm = 0; for (long long i = l - 1; i >= 0; i--) { if (in[i][sm]) { ans += s[i]; sm += 3 - (s[i] - 0 ) % 3; sm %= 3; } } reverse(ans.begin(), ans.end()); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3E4 + 7; int x[N], y[N]; void solve() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; x[0] = a[0], y[0] = 0; for (int i = 1; i < n; i++) { x[i] = min(x[i - 1], a[i]), y[i] = a[i] - x[i]; if (y[i] >= y[i - 1]) continue; y[i] = y[i - 1], x[i] = a[i] - y[i]; if (x[i] < 0) { cout << NO n ; return; } } cout << YES n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) solve(); return 0; }
|
//#pragma GCC optimize( Ofast ) #include <bits/stdc++.h> using namespace std; typedef long long int ll; typedef unsigned long long ull; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); ll myRand(ll B) { return (ull)rng() % B; } int main(){ cin.tie(nullptr); ios::sync_with_stdio(false); int n,k; cin >> n >> k; vector<int> l(n); for(int i=0;i<n;i++){ cin >> l[i]; } sort(l.rbegin(), l.rend()); const int N=5e5; vector<int> a(N); a[0]=1,a[1]=-1; int ans=1e9; int sum=0; for(int i=0,j=0;i<N-1;i++){ sum+=a[i]; a[i+1]+=a[i]; if(sum+a[i+1]>=k){ ans=i+1; break; } while(a[i]>0 and j<n){ int u=(l[j]-1)/2; int v=l[j]-1-u; a[i+2]++; a[i+2+u]--; a[i+2]++; a[i+2+v]--; a[i]--; sum--; j++; } } if(ans==1e9){ ans=-1; } cout << ans << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_sync #(
parameter ADDRESS_WIDTH = 4
) (
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
reg [ADDRESS_WIDTH:0] level = 'h00;
reg [ADDRESS_WIDTH:0] level_next;
assign s_axis_room = room;
assign m_axis_level = level;
wire read = m_axis_ready & m_axis_valid;
wire write = s_axis_ready & s_axis_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= MAX_ROOM;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= MAX_ROOM - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != MAX_ROOM;
s_axis_empty <= level_next == 0;
end
end
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder.syn.v"
`include "decoder.syn.v"
`include "pipelinedec.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [8:0] c;
// Output of stage 2
wire [8:0] cx;
// Output of stage 3
wire [2:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [2:0] b;
reg [2:0] r_b;
reg [8:0] e;
reg [8:0] r_e;
// 2nd stage
reg [8:0] r_c;
reg [8:0] rr_e;
reg [2:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [8:0] r_qx;
reg [2:0] rb;
reg clk,reset;
reg [8:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/encoder.sdf",enc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
$sdf_annotate("../sdf/decoder.sdf",dec,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000001000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000010000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b001000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e= 9'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
module top;
reg pass;
reg [2:0] res [0:7];
reg [2:0] in [0:7];
reg [7:0] dummy [0:6];
time run_time [0:7];
time exp_time [0:7];
integer i;
initial begin
pass = 1'b1;
#1;
// Initialize the input array.
for (i=0; i<8; i=i+1) begin
in[i] = i[2:0];
end
#1;
for (i=0; i<8; i=i+1) begin
exp_time[i] = $time-1;
end
check;
// We only have 6 dummy items, check that each triggers correctly.
for (i=0; i<7; i=i+1) begin
dummy[i] = 1'b0;
#1;
exp_time[i] = $time-1;
check;
end
if (pass) $display("PASSED");
end
// Check that the value and time are correct.
task check;
integer j;
begin
for (j=0; j<8; j=j+1) begin
if (res[j] !== j[2:0]) begin
$display("FAILED: index %0d value, at %t, expexted %b, got %b.",
j, $time, j[2:0], res[j]);
pass = 1'b0;
end
if (run_time[j] !== exp_time[j]) begin
$display("FAILED: index %0d time, at %t, expexted %t, got %t.",
j, $time, exp_time[j], run_time[j]);
pass = 1'b0;
end
end
end
endtask
genvar m;
generate
for (m=0; m<=7; m=m+1) begin: idac_loop
// This should complain that dummy[7] is out of bounds.
always @ (in[m] or dummy[m]) begin
res[m] = in[m];
run_time[m] = $time;
end
end
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter (
// data interface
clk,
valid,
data,
valid_out,
data_out,
// control interface
dcfilt_enb,
dcfilt_coeff,
dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
// internal registers
reg [47:0] dc_offset = 'd0;
reg [47:0] dc_offset_d = 'd0;
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg [15:0] data_dcfilt = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [47:0] dc_offset_s;
// cancelling the dc offset
always @(posedge clk) begin
dc_offset <= dc_offset_s;
dc_offset_d <= dc_offset;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d;
data_dcfilt <= data_d - dc_offset[32:17];
if (dcfilt_enb == 1'b1) begin
valid_out <= valid_2d;
data_out <= data_dcfilt;
end else begin
valid_out <= valid_2d;
data_out <= data_2d;
end
end
// dsp slice instance ((D-A)*B)+C
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (0),
.AREG (1),
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1),
.B_INPUT ("DIRECT"),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (1),
.DREG (0),
.INMODEREG (0),
.MASK (48'h3fffffffffff),
.MREG (1),
.OPMODEREG (0),
.PATTERN (48'h000000000000),
.PREG (0),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48"))
i_dsp48e1 (
.CLK (clk),
.A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
.B ({{2{dcfilt_coeff[15]}}, dcfilt_coeff}),
.C (dc_offset_d),
.D ({{9{data_d[15]}}, data_d}),
.MULTSIGNIN (1'd0),
.CARRYIN (1'd0),
.CARRYCASCIN (1'd0),
.ACIN (30'd0),
.BCIN (18'd0),
.PCIN (48'd0),
.P (dc_offset_s),
.MULTSIGNOUT (),
.CARRYOUT (),
.CARRYCASCOUT (),
.ACOUT (),
.BCOUT (),
.PCOUT (),
.ALUMODE (4'd0),
.CARRYINSEL (3'd0),
.INMODE (5'b01100),
.OPMODE (7'b0110101),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.OVERFLOW (),
.UNDERFLOW (),
.CEA1 (1'd0),
.CEA2 (1'd1),
.CEAD (1'd1),
.CEALUMODE (1'd0),
.CEB1 (1'd0),
.CEB2 (1'd1),
.CEC (1'd1),
.CECARRYIN (1'd0),
.CECTRL (1'd0),
.CED (1'd1),
.CEINMODE (1'd0),
.CEM (1'd1),
.CEP (1'd0),
.RSTA (1'd0),
.RSTALLCARRYIN (1'd0),
.RSTALUMODE (1'd0),
.RSTB (1'd0),
.RSTC (1'd0),
.RSTCTRL (1'd0),
.RSTD (1'd0),
.RSTINMODE (1'd0),
.RSTM (1'd0),
.RSTP (1'd0));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
limbus_cpu_jtag_debug_module_tck the_limbus_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
limbus_cpu_jtag_debug_module_sysclk the_limbus_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic limbus_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam limbus_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// limbus_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// limbus_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// limbus_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// limbus_cpu_jtag_debug_module_phy.sld_sim_action = "",
// limbus_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// limbus_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// limbus_cpu_jtag_debug_module_phy.sld_type_id = 34,
// limbus_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2000; int N; int board[MAX_N][MAX_N]; int cur[MAX_N][MAX_N]; int row[MAX_N], col[MAX_N]; char buf[MAX_N + 10]; void pb(int arr[MAX_N][MAX_N]) { for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { printf( %d , arr[i][j]); } puts( ); } } int solve() { int ans = 0; for (int i = N - 1; i > 0; i--) { for (int j = 0; j < N - i; j++) { int y = i + j, x = j; cur[y][x] = row[y] ^ col[x]; if (cur[y][x] ^ board[y][x]) { ans++; cur[y][x] ^= 1; row[y] ^= 1; col[x] ^= 1; } } } for (int i = 0; i < N; i++) { if (col[i] ^ row[i]) { board[i][i] ^= 1; } } memset(col, 0, sizeof(col)); memset(row, 0, sizeof(row)); for (int j = N - 1; j > 0; j--) { for (int i = 0; i < N - j; i++) { int y = i, x = j + i; cur[y][x] = row[y] ^ col[x]; if (cur[y][x] ^ board[y][x]) { ans++; cur[y][x] ^= 1; row[y] ^= 1; col[x] ^= 1; } } } for (int i = 0; i < N; i++) { if (row[i] ^ col[i] ^ board[i][i]) { ans++; } } return ans; } int main() { scanf( %d , &N); for (int i = 0; i < N; i++) { scanf( %s , buf); for (int j = 0; j < N; j++) { board[i][j] = buf[j] & 1; } } printf( %d n , solve()); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; pair<long long, long long> h2md_logl[100000][19]; pair<long long, long long> h2md_logr[100000][19]; long long dist_log[100000][19]; long long h[100000]; int max_2h_minus_d(int from, int to, int dir, long long& dist, long long& alldist) { long long curd = 0; long long dmark = 0; long long curtree = from; int curind = from; int l = 0; if (dir == 1) { l = to - from; if (l < 0) l += n; } else if (dir == 0) { l = from - to; if (l < 0) l += n; } l++; int l2 = 1; int deg = 0; while (l > 0) { if (l % 2 == 1) { pair<long long, long long> pret; if (dir == 0) pret = h2md_logl[curtree][deg]; else pret = h2md_logr[curtree][deg]; long long dist_bw_marks = 0; int newtree = curtree; if (dir == 1) { newtree += l2; if (newtree >= n) newtree -= n; } else { newtree -= l2; if (newtree < 0) newtree += n; } if (dir == 1) dist_bw_marks = dist_log[curtree][deg]; else { dist_bw_marks = dist_log[newtree][deg]; } int pret_ind = pret.first; if (pret.second - 2 * h[curind] - dmark > 0) { dmark = dist_bw_marks + pret.second - 2 * h[pret_ind]; curind = pret_ind; } else { dmark += dist_bw_marks; } curtree = newtree; curd += dist_bw_marks; } l /= 2; l2 *= 2; deg += 1; } dist = curd - dmark; if (dir == 0) alldist = curd - dist_log[curtree][0]; else { curtree--; if (curtree < 0) curtree += n; alldist = curd - dist_log[curtree][0]; } return curind; } int main() { int m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> dist_log[i][0]; } for (int i = 0; i < n; i++) { cin >> h[i]; h2md_logl[i][0] = make_pair(i, 2 * h[i]); h2md_logr[i][0] = make_pair(i, 2 * h[i]); } int n2 = 2; int deg = 1; while (n2 < 2 * n) { int half = n2 / 2; for (int i = 0; i < n; i++) { int mid = i + half; int midl = i - half; if (midl < 0) midl += n; if (mid >= n) mid -= n; long long disttohalf = dist_log[i][deg - 1]; long long disttohalfl = dist_log[midl][deg - 1]; dist_log[i][deg] = disttohalf + dist_log[mid][deg - 1]; if (h2md_logr[i][deg - 1].second > h2md_logr[mid][deg - 1].second - disttohalf) { h2md_logr[i][deg] = h2md_logr[i][deg - 1]; } else { h2md_logr[i][deg] = make_pair(h2md_logr[mid][deg - 1].first, h2md_logr[mid][deg - 1].second - disttohalf); } if (h2md_logl[i][deg - 1].second > h2md_logl[midl][deg - 1].second - disttohalfl) { h2md_logl[i][deg] = h2md_logl[i][deg - 1]; } else { h2md_logl[i][deg] = make_pair(h2md_logl[midl][deg - 1].first, h2md_logl[midl][deg - 1].second - disttohalfl); } } deg++; n2 *= 2; } long long distl, distr, alldist; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; int f, t; f = b; if (f >= n) f -= n; t = a - 2; if (t < 0) t += n; int indf = max_2h_minus_d(f, t, 1, distl, alldist); int indt = max_2h_minus_d(t, f, 0, distr, alldist); if (indf != indt) { cout << alldist + 2 * (h[indf] + h[indt]) - distl - distr; } else if (indf == f) { int newindt = indt + 1; if (newindt == n) newindt = 0; long long ndr, nar; int indtt = max_2h_minus_d(t, newindt, 0, ndr, nar); cout << alldist + 2 * (h[indf] + h[indtt]) - distl - ndr; } else if (indt == t) { int newindf = indf - 1; if (newindf < 0) newindf = n - 1; long long ndl, nal; int indff = max_2h_minus_d(f, newindf, 1, ndl, nal); cout << alldist + 2 * (h[indff] + h[indt]) - ndl - distr; } else { int newindf = indf - 1; int newindt = indt + 1; if (newindf < 0) newindf = n - 1; if (newindt == n) newindt = 0; long long ndl, ndr; long long nal, nar; int indff = max_2h_minus_d(f, newindf, 1, ndl, nal); int indtt = max_2h_minus_d(t, newindt, 0, ndr, nar); cout << max(alldist + 2 * (h[indff] + h[indt]) - ndl - distr, alldist + 2 * (h[indf] + h[indtt]) - distl - ndr); } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e2 + 5; const int INF = 1e9 + 5; const int mod = 1000000007; const double eps = 1e-7; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { long long a, b, k; while (cin >> k >> a >> b) { if (b <= 0) { a = -a; b = -b; swap(a, b); } long long ans = b / k - a / k; if (a % k == 0 || a < 0) ans++; cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; void solve() { long long n, k; cin >> n >> k; if (n == k) { cout << -1 << endl; return; }; if (k == 0) { cout << n << ; for (__typeof((n)) i = (1); i < (n); i++) cout << i << ; return; } if (k == n - 1) { for (__typeof((n + 1)) i = (1); i < (n + 1); i++) cout << i << ; return; } k = n - k; if (k % 2) cout << k << ; for (__typeof((k / 2)) i = (0); i < (k / 2); i++) cout << 2 * i + 2 - k % 2 << << 2 * i + 1 + k % 2 << ; for (__typeof((n + 1)) i = (k + 1); i < (n + 1); i++) cout << i << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000006; const long long mod = 1000000000 + 7; long long x, y; long long fact[MAXN + 25], inv_fact[MAXN + 25]; long long fast_pow(long long base, long long exp) { if (exp == 0) return 1; if (exp == 1) return base; long long ret = fast_pow(base, exp / 2) % mod; ret = (ret * ret) % mod; if (exp % 2 == 1) ret = (ret * base) % mod; return ret % mod; } void init() { fact[0] = 1; for (long long i = 1; i < MAXN + 25; i++) fact[i] = (i * fact[i - 1]) % mod; inv_fact[0] = 1; for (long long i = 1; i < MAXN + 25; i++) inv_fact[i] = (inv_fact[i - 1] * fast_pow(i, mod - 2)) % mod; } int main() { init(); int q; scanf( %d , &q); while (q--) { scanf( %lld %lld , &x, &y); long long ans = fast_pow(2, y - 1) % mod; long long X = x; for (int d = 2; d * d <= X; d++) { if (X % d) continue; long long m = 0; while (x % d == 0) { x /= d, m++; } long long aux = (fact[m + y - 1] * inv_fact[m]) % mod; aux = (aux * inv_fact[y - 1]) % mod; ans = (ans * aux) % mod; } if (x > 1) { long long m = 1; long long aux = (fact[m + y - 1] * inv_fact[m]) % mod; aux = (aux * inv_fact[y - 1]) % mod; ans = (ans * aux) % mod; } printf( %lld n , (ans + mod) % mod); } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, k, num, count = 0, i, j; cin >> n >> k; bitset<32> b[6]; for (i = 1; i < 3; i++) { for (j = i + 1; j <= 3; j++) { cout << or << i << << j << n << flush; cin >> num; b[count] = num; count++; cout << and << i << << j << n << flush; cin >> num; b[count] = num; count++; } } bitset<32> b1, b2; for (i = 0; i < 32; i++) { if (b[0][i] == b[1][i]) { b1[i] = b[0][i]; b2[i] = b[0][i]; } else { if (b[2][i] != b[4][i]) { b1[i] = b[2][i]; b2[i] = b[4][i]; } else { b1[i] = b[3][i]; b2[i] = b[5][i]; } } } bitset<32> r, ans; r = b1; vector<int> vec; vec.push_back(b1.to_ulong()); vec.push_back(b2.to_ulong()); b1 = b[2]; b2 = b[3]; for (i = 3; i <= n; i++) { if (i > 3) { cout << or << 1 << << i << n << flush; cin >> num; b1 = num; cout << and << 1 << << i << n << flush; cin >> num; b2 = num; } for (j = 0; j < 32; j++) { if (r[j] == 0 && b1[j] == 0) ans[j] = 0; else if (r[j] == 0 && b1[j] == 1) ans[j] = 1; } for (j = 0; j < 32; j++) { if (r[j] == 1 && b2[j] == 0) ans[j] = 0; else if (r[j] == 1 && b2[j] == 1) ans[j] = 1; } vec.push_back(ans.to_ulong()); } sort(vec.begin(), vec.end()); cout << finish << vec[k - 1] << n << flush; return 0; }
|
#include <bits/stdc++.h> namespace IO { template <typename Tp> inline Tp input() { Tp x = 0, y = 1; char c = getchar(); while ((c < 0 || 9 < c) && c != EOF) { if (c == - ) y = -1; c = getchar(); } if (c == EOF) return 0; while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x *= y; } template <typename Tp> inline void read(Tp &x) { x = input<Tp>(); } }; // namespace IO using namespace IO; namespace modular { const int MOD = 1000000007; inline int add(int x, int y) { return (x += y) >= MOD ? x -= MOD : x; } inline void inc(int &x, int y) { (x += y) >= MOD ? x -= MOD : 0; } inline int mul(int x, int y) { return 1LL * x * y % MOD; } inline int qpow(int x, int y) { int ans = 1; for (; y; y >>= 1, x = mul(x, x)) if (y & 1) ans = mul(ans, x); return ans; } }; // namespace modular int N, top, tot; int a[2007], b[2007], c[3]; std::pair<int, int> ans[2007 * 2007]; bool cmp(int x, int y) { return a[x] < a[y]; } int main() { srand(0x66ccf); read(N); for (int i = 1; i <= N; ++i) read(a[i]); top = N; for (int i = 1; i <= top; ++i) b[i] = i; std::sort(b + 1, b + N + 1, cmp); std::reverse(b + 1, b + N + 1); while (top && !a[b[top]]) top--; if (top < 2) return puts( -1 ), 0; while (top > 2) { for (int i = 0; i <= 2; ++i) { c[i] = rand() % (top - i) + i + 1; std::swap(b[i + 1], b[c[i]]); c[i] = b[i + 1]; } std::sort(c, c + 3, cmp); int k = a[c[1]] / a[c[0]], mx = 0; for (int i = 0; i <= 21; ++i) if (k >> i & 1) mx = i; for (int i = 0; i <= 2; ++i) b[i + 1] = c[i]; for (int i = 0; i <= mx; ++i) { if (k >> i & 1) { ans[++tot] = std::pair<int, int>(c[0], c[1]); a[c[1]] -= a[c[0]]; a[c[0]] *= 2; } else { ans[++tot] = std::pair<int, int>(c[0], c[2]); a[c[2]] -= a[c[0]]; a[c[0]] *= 2; } } if (!a[c[1]]) { std::swap(b[top], b[2]); top--; } } printf( %d n , tot); for (int i = 1; i <= tot; ++i) printf( %d %d n , ans[i].first, ans[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, INF = 0x3f3f3f3f, MOD = 1e9 + 7; struct P { long long x, y; P() {} P(long long x, long long y) : x(x), y(y) {} P rotate() { return P(-y, x); } P operator-(const P& rhs) const { return P(x - rhs.x, y - rhs.y); } long long operator*(const P& rhs) const { return x * rhs.x + y * rhs.y; } bool operator==(const P& rhs) const { return x == rhs.x && y == rhs.y; } }; bool judge(P& u, P& v) { if (v == P(0, 0)) return u == P(0, 0); long long w = v.x * v.x + v.y * v.y; return u * v % w == 0 && u * v.rotate() % w == 0; } P a, b, c; int main() { ios_base::sync_with_stdio(0); while (cin >> a.x >> a.y >> b.x >> b.y >> c.x >> c.y) { bool ok = false; for (int i = 0; i < 4; ++i) { P d = b - a; if (judge(d, c)) { ok = true; break; } a = a.rotate(); } cout << (ok ? YES : NO ) << n ; } return 0; }
|
`timescale 1ns/1ps
module tb_sram_ctrl();
reg clk;
reg [7:0] address;
wire [15:0] data_read;
reg [15:0] data_write;
inout [15:0] data;
reg chip_enable;
reg write_enable;
reg output_enable;
reg reset;
assign data = (!write_enable && !chip_enable && output_enable) ? data_write : 'bz;
// assign data_read = (write_enable && chip_enable && output_enable) ? data : 'bz;
assign data_read = data;
sram SRAM1(
.address(address),
.data(data),
.chip_enable(chip_enable),
.write_enable(write_enable),
.output_enable(output_enable),
.reset(reset)
);
always begin
#1 clk = ~clk;
end
initial begin
$dumpfile("tb_sram_testcase1.vcd");
$dumpvars;
// $vcdplusfile("tb_sram_v3.vpd");
// $vcdpluson;
chip_enable = 1;
write_enable = 0;
data_write =0;
output_enable =0;
address=0;
clk = 0;
reset = 0;
#1
reset = 1;
// TestCase: Writing to SRAM.
#1
output_enable = 1;
chip_enable = 0;
write_enable = 0; // write (active low)
data_write = 24;
address = 28;
// TestCase: Reading the sram.
#1
output_enable = 0;
chip_enable = 0;
write_enable = 1; // read (active low)
data_write = 26; // dummy test to make sure data is not read
address = 28;
// TestCase: Writing to memory location 28;
#1
output_enable = 1;
chip_enable = 0;
write_enable = 0;
data_write = 30;
address = 28;
// TestCase: Memory location 28 should be the same as before.
#1
output_enable = 0;
chip_enable = 0;
write_enable = 1;
data_write = 40;
address = 28;
// TestCase: Memory location 28 should be the same as before.
#1
output_enable = 0;
chip_enable = 0;
write_enable = 1;
data_write = 40;
address = 242;
#1
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, tot, X, Y, a[25][25], d[25], id[25][25]; double p[25], b[500][2], c[500][500], ans[25]; void work() { scanf( %d %d %d %d , &n, &m, &X, &Y); if (X == Y) { for (int i = 1; i <= n; i++) printf( %.10lf , 1.0 * int(i == X)); return; } for (int i = 1, x, y; i <= m; i++) scanf( %d %d , &x, &y), a[x][y] = a[y][x] = 1, d[x]++, d[y]++; for (int i = 1; i <= n; i++) scanf( %lf , &p[i]); for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) id[i][j] = id[j][i] = ++tot; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { int x = id[i][j]; double q = 1 - p[i] * p[j]; for (int k = 1; k <= n; k++) if (a[i][k]) for (int l = 1; l <= n; l++) if (a[j][l]) c[x][id[k][l]] += (1 - p[i]) * (1 - p[j]) / d[i] / d[j] / q; for (int k = 1; k <= n; k++) if (a[i][k]) c[x][id[k][j]] += (1 - p[i]) * p[j] / d[i] / q; for (int k = 1; k <= n; k++) if (a[j][k]) c[x][id[i][k]] += p[i] * (1 - p[j]) / d[j] / q; } b[id[X][Y]][0] = 1; for (int T = 5000; T; T--) { for (int i = 1; i <= tot; i++) for (int j = 1; j <= tot; j++) b[j][1] += b[i][0] * c[i][j]; for (int i = 1; i <= tot; i++) b[i][0] = b[i][1], b[i][1] = 0; for (int i = 1; i <= n; i++) ans[i] += b[id[i][i]][0]; } for (int i = 1; i <= n; i++) printf( %.10lf , ans[i]); } int main() { work(); return 0; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module ddr3_s4_uniphy_example_if0_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
reset_request_n,
ctl_reset_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
input csr_soft_reset_req;
output reset_request_n;
output ctl_reset_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign reset_request_n = pll_locked;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n & (!csr_soft_reset_req);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (ctl_reset_n)
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, a[2000 + 10][2000 + 10], ans[2000 + 10][2000 + 10], viz[30]; pair<int, int> fs[30], ls[30]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> t; while (t--) { int n, m, l = 0; pair<int, int> aux = {0, 0}; cin >> n >> m; for (int i = 1; i <= 26; i++) viz[i] = 0, fs[i] = {0, 0}, ls[i] = {0, 0}; for (int i = 1; i <= n; i++) { string s; cin >> s; for (int j = 0; j < m; j++) { if (s[j] >= a && s[j] <= z ) a[i][j + 1] = s[j] - a + 1; else a[i][j + 1] = 0; } } for (int ch = 1; ch <= 26; ch++) for (int i = 1; i <= n && !viz[ch]; i++) for (int j = 1; j <= m && !viz[ch]; j++) if (a[i][j] == ch) { viz[ch] = 1; fs[ch] = {i, j}; int j1 = j + 1, i1 = i + 1, ok = 0; while (j1 <= m) { if (a[i][j1] == ch) ok = 1, ls[ch] = {i, j1}; j1++; } while (i1 <= n) { if (a[i1][j] == ch) ok = 1, ls[ch] = {i1, j}; i1++; } if (!ok) ls[ch] = fs[ch]; l = ch; aux = fs[ch]; } for (int i = 1; i <= l; i++) { if (!fs[i].first) { fs[i] = aux; ls[i] = aux; } for (int i1 = fs[i].first; i1 <= ls[i].first; i1++) for (int j1 = fs[i].second; j1 <= ls[i].second; j1++) ans[i1][j1] = i; } int ok = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (ans[i][j] != a[i][j]) ok = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) a[i][j] = ans[i][j] = 0; if (!ok) { cout << NO << n ; continue; } cout << YES << n ; cout << l << n ; for (int i = 1; i <= l; i++) cout << fs[i].first << << fs[i].second << << ls[i].first << << ls[i].second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<string> s; set<string> ss; string a, b, res; int n, cnt_a = 0, cnt_b = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a; ss.insert(a); s.push_back(a); } if (ss.size() == 1) cout << s[0] << endl; else { sort(s.begin(), s.end()); a = s[0]; b = s[n - 1]; for (int i = 0; i < n; i++) { if (s[i].compare(a) == 0) cnt_a++; else cnt_b++; } res = (cnt_a > cnt_b) ? a : b; cout << res << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, mem[505][505]; string s; int dp(int i, int j) { if (i > j) return 0; int &ans = mem[i][j]; if (ans != -1) return ans; ans = dp(i + 1, j) + 1; for (int k = i + 1; k <= j; k++) if (s[i] == s[k]) ans = min(ans, dp(i + 1, k - 1) + dp(k, j)); return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); memset(mem, -1, sizeof(mem)); cin >> n >> s; cout << dp(0, n - 1) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, last = 0, count = 0, sum, sum1; cin >> n; while (n >= 10) { last = n / 10; n = n / 10; count += 1; } if (count + 1 == 1) sum1 = 1; else if (count + 1 == 2) sum1 = 3; else if (count + 1 == 3) sum1 = 6; else if (count + 1 == 4) sum1 = 10; sum = (last - 1) * 10 + sum1; if (n > 10) cout << sum << endl; else { last = n; sum = (last - 1) * 10 + sum1; cout << sum << endl; } } }
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > v; map<long long, long long> m; int qpow(long long a, long long b, long long m) { long long c = 1; while (b) { if (b & 1) c = c * a % m; b >>= 1; a = a * a % m; } return c; } int main() { ios::sync_with_stdio(false); long long num, n, s, t; cin >> n >> s; if (8 * s / n < 63) { num = pow(2, 8 * s / n); } else { num = 0x7fffffffffffffff; } for (int i = (0); i < (n); ++i) { cin >> t; if (m.count(t) == 0) { v.push_back(make_pair(t, 0)); m[t] = 1; } else { m[t]++; } } int len = v.size(); for (int i = (0); i < (len); ++i) { v[i].second = m[v[i].first]; } sort(v.begin(), v.end()); long long l = -1, r = len; long long ans = 0; while (l < r && len > num) { l++; ans += v[l].second; len--; } long long minn = ans; while (l >= 0) { if (l >= r) { cout << n; return 0; } ans -= v[l].second; len++; l--; while (len > num) { r--; ans += v[r].second; len--; } minn = min(ans, minn); } cout << minn; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, SQ = 780; const long long inf = 1e18; long long dp[2][SQ]; vector<int> v[maxn]; int n, m; long long ans; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int a, b; scanf( %d%d , &a, &b); if ((a = n + 1 - a) >= (SQ - 1)) ans += 3; else v[b].push_back(a); } for (int i = 1; i < SQ; i++) dp[0][i] = inf; dp[0][0] = 0; for (int i = 1; i <= n; i++) { dp[i & 1][SQ - 1] = inf; sort(v[i].begin(), v[i].end()); int num = 0; for (int j = SQ - 2; j >= 0; j--) { dp[i & 1][j] = min(dp[i & 1][j + 1], num + min(dp[(i + 1) & 1][0] + (j == 0 ? 0 : 2) + 1ll * ((j * (j + 1)) / 2), dp[(i + 1) & 1][j + 1])); if (!v[i].empty() && v[i].back() == j) num += 3, v[i].pop_back(); } } ans += dp[n & 1][0]; printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; int count1[100005], count2[100005], count3[100005]; bool can_be_palin(int *a, int size) { int i, no_of_odd = 0; for (i = 0; i < size; i++) no_of_odd += a[i] % 2; return (no_of_odd <= 1); } bool is_palin(int *a, int l, int r) { for (int i = l; i <= (l + r) / 2; i++) if (a[i] != a[r + l - i]) return false; return true; } bool func(int *a, int n, int end, int l, int r) { int i; fill(count1, count1 + n + 1, 0); fill(count2, count2 + n + 1, 0); if (end - l + 1 >= r - end) { for (i = l; i <= end; i++) count1[a[i]]++; for (i = r; i > end; i--) count2[a[i]]++; for (i = 1; i <= n; i++) { if (count2[i] > count1[i]) return false; count1[i] -= count2[i]; } return can_be_palin(count1, n + 1); } else { for (i = l; i <= end; i++) count1[a[i]]++; for (i = r; i >= r - end + l; i--) count2[a[i]]++; for (i = 1; i <= n; i++) { if (count2[i] > count1[i]) return false; count1[i] -= count2[i]; } return can_be_palin(count1, n + 1) && is_palin(a, end + 1, r - end + l - 1); } } bool func2(int *a, int n, int end, int l, int r) { int i; fill(count1, count1 + n + 1, 0); fill(count2, count2 + n + 1, 0); if (r - end + 1 >= end - l) { for (i = r; i >= end; i--) count1[a[i]]++; for (i = l; i < end; i++) count2[a[i]]++; for (i = 1; i <= n; i++) { if (count2[i] > count1[i]) return false; count1[i] -= count2[i]; } return can_be_palin(count1, n + 1); } else { for (i = r; i >= end; i--) count1[a[i]]++; for (i = l; i <= l + r - end; i++) count2[a[i]]++; for (i = 1; i <= n; i++) { if (count2[i] > count1[i]) return false; count1[i] -= count2[i]; } return can_be_palin(count1, n + 1) && is_palin(a, r - end + l + 1, end - 1); } } int main() { int n, i; scanf( %d , &n); long long ans = 0; int a[n]; for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n / 2 && a[i] == a[n - 1 - i]; i++) ; if (i == n / 2) { printf( %I64d , (long long)n * (n + 1) / 2); return 0; } int l = i, r = n - 1 - i, left_prev = l, right_prev = r, end = (l + r) / 2; int prev_pos = -1; while (left_prev < end - 1 && end < right_prev - 1) { bool flag = true; flag = func(a, n, end, l, r); int mid1 = (end + left_prev) / 2; int mid2 = (end + right_prev) / 2; if (flag == false) { left_prev = end; end = mid2; } else { right_prev = end; prev_pos = end; end = mid1; } } for (int k = left_prev; k < r && k < right_prev; k++) if (func(a, n, k, l, r) == true) prev_pos = (prev_pos == -1) ? k : min(prev_pos, k); if (prev_pos != -1) ans += (long long)(l + 1) * (r - prev_pos); right_prev = r, left_prev = l, end = (l + r) / 2; prev_pos = -1; while (end < right_prev - 1 && left_prev < end - 1) { bool flag = true; flag = func2(a, n, end, l, r); int mid1 = (end + right_prev) / 2; int mid2 = (end + left_prev) / 2; if (flag == false) { right_prev = end; end = mid2; } else { left_prev = end; prev_pos = end; end = mid1; } } for (int k = right_prev; k > l && k > left_prev; k--) if (func2(a, n, k, l, r) == true) prev_pos = (prev_pos == -1) ? k : max(prev_pos, k); if (prev_pos != -1) ans += (long long)(n - r) * (prev_pos - l); fill(count1, count1 + n + 1, 0); for (i = l; i <= r; i++) count1[a[i]]++; if (can_be_palin(count1, n + 1) == true) ans += (long long)(l + 1) * (n - r); printf( %I64d , ans); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; class SegTree { private: const ll NEUT = 4 * (ll)1e18; vector<ll> seg, tag; int h = 1; void apply(int i, ll v) { seg[i] += v; if (i < h) tag[i] += v; } void push(int i) { if (tag[i] == 0) return; apply(2 * i, tag[i]); apply(2 * i + 1, tag[i]); tag[i] = 0; } ll combine(ll a, ll b) { return min(a, b); } ll recGet(int a, int b, int i, int ia, int ib) { if (ib <= a || b <= ia) return NEUT; if (a <= ia && ib <= b) return seg[i]; push(i); int im = (ia + ib) >> 1; return combine(recGet(a, b, 2 * i, ia, im), recGet(a, b, 2 * i + 1, im, ib)); } void recApply(int a, int b, ll v, int i, int ia, int ib) { if (ib <= a || b <= ia) return; if (a <= ia && ib <= b) apply(i, v); else { push(i); int im = (ia + ib) >> 1; recApply(a, b, v, 2 * i, ia, im); recApply(a, b, v, 2 * i + 1, im, ib); seg[i] = combine(seg[2 * i], seg[2 * i + 1]); } } int recFind(int a, int b, ll v, int i, int ia, int ib) { if (seg[i] > v) return b; if (b <= ia || ib <= a) return b; if (ib == ia + 1) return ia; push(i); int im = (ia + ib) >> 1; int off = recFind(a, b, v, 2 * i, ia, im); if (off < b) return off; else return recFind(a, b, v, 2 * i + 1, im, ib); } public: SegTree(int n) { while (h < n) h *= 2; seg.resize(2 * h, 0); tag.resize(h, 0); } ll rangeMin(int a, int b) { return recGet(a, b + 1, 1, 0, h); } void rangeAdd(int a, int b, ll v) { recApply(a, b + 1, v, 1, 0, h); } int findNext(int a, int b, ll v) { return recFind(a, b + 1, v, 1, 0, h); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> inv(n); for (int i = 0; i < n; ++i) { int v; cin >> v; inv[v - 1] = i; } int res = n - 1; SegTree seg(n); seg.rangeAdd(0, inv[n - 1], -1); for (int i = 0; i < n; ++i) { while (seg.rangeMin(0, n - 1) >= 0) { seg.rangeAdd(0, inv[res - 1], -1); --res; } cout << res + 1 << ; int q; cin >> q; seg.rangeAdd(0, q - 1, 1); } cout << n ; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eda_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eda_e.v,v 1.1 2006/04/10 15:42:07 wig Exp $
// $Date: 2006/04/10 15:42:07 $
// $Log: inst_eda_e.v,v $
// Revision 1.1 2006/04/10 15:42:07 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eda_e
//
// No user `defines in this module
module inst_eda_e
//
// Generated module inst_eda
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eda_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long m; inline long long Nr(long long n) { long long cnt = 0, k, lim, put; for (k = 2; 1LL * k * k * k <= n; ++k) { put = 1LL * k * k * k; lim = n / put; if (1LL * lim * put > n) --lim; if (1LL * (lim + 1) * put <= n) ++lim; cnt += lim; } return cnt; } int main() { int i, j, x, y; cin >> m; long long st = 0, dr = 100000000000000000LL, mij, sol = -1; while (st <= dr) { mij = (st + dr) / 2; long long x = Nr(mij); if (x > m) dr = mij - 1; else if (x < m) st = mij + 1; else { sol = mij; dr = mij - 1; } } cout << sol; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007LL; long long N; vector<long long> E[100000]; long long dp[100000][2]; long long ans = 0; long long mod_inv(long long n) { long long t = MOD - 2, p = 1, q = n; while (t > 0) { if (t % 2 == 1) p = (p * q) % MOD; q = (q * q) % MOD; t /= 2; } return p % MOD; } void dfs(long long v, long long p) { bool leaf = true; for (long long u : E[v]) if (u != p) { dfs(u, v); leaf = false; } if (leaf) { dp[v][0] = 1; dp[v][1] = 1; } else { long long ev = 1, od = 1; for (long long u : E[v]) if (u != p) { (ev *= dp[u][0]) %= MOD; (od *= dp[u][1]) %= MOD; } dp[v][0] = (ev + od) % MOD; dp[v][1] = (od + ev) % MOD; } } void dfs2(long long v, long long p, long long ev, long long od) { long long _ev = 1, _od = 1; for (long long u : E[v]) if (u != p) { (_ev *= dp[u][0]) %= MOD; (_od *= dp[u][1]) %= MOD; } if (p != -1) { long long d = _ev * ev % MOD + _od * od % MOD; ans += d; ans %= MOD; } else { ans += dp[v][0]; ans %= MOD; } long long cnt = 0; for (long long u : E[v]) if (u != p) { cnt++; } for (long long u : E[v]) if (u != p) { long long nev, nod, s; if (cnt == 1) { s = ev + od; nev = s; nod = s; } else if (p == -1) { s = _ev * mod_inv(dp[u][0]) % MOD + _od * mod_inv(dp[u][1]) % MOD; nev = s; nod = s; } else { s = _ev * mod_inv(dp[u][0]) % MOD * ev % MOD + _od * mod_inv(dp[u][1]) % MOD * od % MOD; nev = s; nod = s; } nev %= MOD; nod %= MOD; dfs2(u, v, nev, nod); } } int main(void) { cin >> N; for (long long i = ((long long)0); i < ((long long)N - 1); i++) { long long A, B; cin >> A >> B; A--; B--; E[A].push_back(B); E[B].push_back(A); } dfs(0, -1); dfs2(0, -1, 1, 0); cout << ans << endl; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_rate_limit
*/
module test_axis_rate_limit_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
rate_num,
rate_denom,
rate_by_frame
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_rate_limit_64.lxt");
$dumpvars(0, test_axis_rate_limit_64);
end
axis_rate_limit #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
|
#include <iostream> #include <string> #include <cmath> #include <vector> #include <algorithm> #include <utility> #include <bitset> #include <climits> #include <set> #include <map> #include <iomanip> #include <queue> #include <cstring> using namespace std; #define ll long long #define pll pair<ll,ll> #define F first #define S second #define pll pair<ll,ll> #define mp make_pair #define pb push_back const ll N=1e9+7; ll gcd(ll a,ll b){ if(b==0) return a; return gcd(b,a%b); } int main(){ ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); ll t; cin >>t; while(t--){ ll n; cin >> n; ll cur=1,ans=0; for(ll i=2;i<43;i++){ ans+=i*((n/cur)-(n/cur)/(i/gcd(cur,i))); ans%=N; cur*=i/gcd(cur,i); } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, l, r, x, mid; cin >> n >> m; int a[n][2]; for (int i = 0; i < n; i++) cin >> a[i][0] >> a[i][1]; int b[m]; for (int i = 0; i < m; i++) cin >> b[i]; int music[n]; for (int i = 0; i < n; i++) music[i] = 0; music[0] = a[0][0] * a[0][1]; for (int i = 1; i < n; i++) music[i] = music[i - 1] + a[i][0] * a[i][1]; for (int i = 0; i < m; i++) { x = b[i]; l = -1; r = n - 1; while (r - l > 1) { mid = (l + r) / 2; if (x <= music[mid]) r = mid; else l = mid; } cout << r + 1 << endl; } return 0; }
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sounder(clk_i, saddr_i, sdata_i, s_strobe_i,
tx_strobe_o, tx_dac_i_o, tx_dac_q_o,
rx_adc_i_i,rx_adc_q_i,
rx_strobe_o, rx_imp_i_o,rx_imp_q_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Transmit subsystem
output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
// Receive subsystem
output rx_strobe_o; // Indicates output samples ready for Rx FIFO
input [15:0] rx_adc_i_i; // I channel input from ADC interface module
input [15:0] rx_adc_q_i; // Q channel input from ADC interface module
output [15:0] rx_imp_i_o; // I channel impulse response to Rx FIFO
output [15:0] rx_imp_q_o; // Q channel impulse response to Rx FIFO
// Internal variables
wire reset;
wire transmit;
wire receive;
wire loopback;
wire [4:0] degree;
wire [13:0] ampl;
wire [15:0] mask;
wire ref_strobe;
wire sum_strobe;
sounder_ctrl master(.clk_i(clk_i),.rst_i(reset),.saddr_i(saddr_i),
.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
.reset_o(reset),.transmit_o(transmit),.receive_o(receive),.loopback_o(loopback),
.degree_o(degree),.ampl_o(ampl),.mask_o(mask),.tx_strobe_o(tx_strobe_o),
.rx_strobe_o(rx_strobe_o),.sum_strobe_o(sum_strobe),.ref_strobe_o(ref_strobe));
// Loopback implementation
wire [13:0] tx_i, tx_q;
wire [15:0] tx_i_ext, tx_q_ext;
wire [15:0] rx_i, rx_q;
sign_extend #(14,16) tx_i_extender(tx_i, tx_i_ext);
sign_extend #(14,16) tx_q_extender(tx_q, tx_q_ext);
assign tx_dac_i_o = loopback ? 14'b0 : tx_i;
assign tx_dac_q_o = loopback ? 14'b0 : tx_q;
assign rx_i = loopback ? tx_i_ext : rx_adc_i_i;
assign rx_q = loopback ? tx_q_ext : rx_adc_q_i;
sounder_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(transmit),
.strobe_i(tx_strobe_o),.mask_i(mask),.ampl_i(ampl),
.tx_i_o(tx_i),.tx_q_o(tx_q) );
sounder_rx receiver
( .clk_i(clk_i),.rst_i(reset),.ena_i(receive),
.sum_strobe_i(sum_strobe),.ref_strobe_i(ref_strobe),
.mask_i(mask),.degree_i(degree),
.rx_in_i_i(rx_i),.rx_in_q_i(rx_q),.rx_i_o(rx_imp_i_o),.rx_q_o(rx_imp_q_o));
endmodule // sounder
|
#include <bits/stdc++.h> using namespace std; long long n, m; int main() { cin >> n >> m; if (n > m) { swap(n, m); } if (n % 2 == 0 && m % 2 == 0) { if (n == 2 && m == 2) cout << 0 << endl; else cout << n * m << endl; return 0; } if (n + m <= 4) { cout << 0 << endl; return 0; } if (n == 1) { if (m % 6 == 1 || m % 6 == 5) { cout << m - 1 << endl; } else if (m % 6 == 2 || m % 6 == 4) { cout << m - 2 << endl; } else if (m % 6 == 3) { cout << m - 3 << endl; } else { cout << m << endl; } return 0; } if (n % 2 == 1 && m % 2 == 0) { swap(n, m); } if (n % 2 == 0) { if (m == 3) { if (n >= 4) cout << m * n << endl; else cout << 4 << endl; return 0; } if (n == 2) { if (m == 7) cout << 12 << endl; else if (m == 3) cout << 4 << endl; else cout << m * n << endl; return 0; } if (n >= 4) { cout << m * n << endl; return 0; } } if (n > m) swap(n, m); cout << m * n - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; void solve() { int n; cin >> n; string s; cin >> s; long long ans = 0; long long ca = 0, cab = 0, cabc = 0, slen = 1; for (char c : s) { if (c == a ) ca = (slen + ca) % mod; else if (c == b ) cab = (ca + cab) % mod; else if (c == c ) cabc = (cabc + cab) % mod; else { cabc = (3 * cabc + cab) % mod; cab = (ca + 3 * cab) % mod; ca = (slen + 3 * ca) % mod; slen = (3 * slen) % mod; } } cout << cabc << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module medfifo
#(parameter WIDTH=32,
parameter DEPTH=1)
(input clk, input rst,
input [WIDTH-1:0] datain,
output [WIDTH-1:0] dataout,
input read,
input write,
input clear,
output full,
output empty,
output [7:0] space,
output [7:0] occupied);
localparam NUM_FIFOS = (1<<DEPTH);
wire [WIDTH-1:0] dout [0:NUM_FIFOS-1];
wire [0:NUM_FIFOS-1] full_x;
wire [0:NUM_FIFOS-1] empty_x;
shortfifo #(.WIDTH(WIDTH))
head (.clk(clk),.rst(rst),
.datain(datain),.write(write),.full(full),
.dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]),
.clear(clear),.space(space[4:0]),.occupied() );
shortfifo #(.WIDTH(WIDTH))
tail (.clk(clk),.rst(rst),
.datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & ~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]),
.dataout(dataout),.read(read),.empty(empty),
.clear(clear),.space(),.occupied(occupied[4:0]) );
genvar i;
generate
for(i = 1; i < NUM_FIFOS-1 ; i = i + 1)
begin : gen_depth
shortfifo #(.WIDTH(WIDTH))
shortfifo (.clk(clk),.rst(rst),
.datain(dout[i-1]),.write(~full_x[i] & ~empty_x[i-1]),.full(full_x[i]),
.dataout(dout[i]),.read(~full_x[i+1] & ~empty_x[i]),.empty(empty_x[i]),
.clear(clear),.space(),.occupied() );
end
endgenerate
assign space[7:5] = 0;
assign occupied[7:5] = 0;
endmodule // medfifo
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_1_V
`define SKY130_FD_SC_HD__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_1_V
|
#include <bits/stdc++.h> using namespace std; struct edge { int to, next, w; edge(int _to = 0, int _next = 0, int _w = 0) : to(_to), next(_next), w(_w) {} } e[300010 << 1]; int n, m; int g[300010], nume = 0; int d[300010]; int f[300010][2]; vector<int> ans; namespace LCT { int f[300010]; void init() { for (int i = 1; i <= n; i++) f[i] = i; } int getf(int x) { if (f[x] == x) return x; return f[x] = getf(f[x]); } int merge(int x, int y) { f[f[x]] = f[y]; } } // namespace LCT void addEdge(int u, int v, int w) { e[nume] = edge(v, g[u], w); g[u] = nume++; } void dfs(int x, int p) { for (int i = g[x]; ~i; i = e[i].next) if (e[i].to ^ p) dfs(e[i].to, x); int numch = 0; static int ch[300010][2]; int c0 = 0, c1 = 0; for (int i = g[x]; ~i; i = e[i].next) if (e[i].to ^ p) { ++numch; ch[numch][0] = f[e[i].to][0]; ch[numch][1] = f[e[i].to][1]; if (!ch[numch][0] && !ch[numch][1]) { f[x][0] = f[x][1] = 0; return; } if (ch[numch][0] && ch[numch][1]) { f[x][0] = f[x][1] = 1; return; } if (ch[numch][0]) c0++; if (ch[numch][1]) c1++; } if (d[x] == -1) { f[x][0] = f[x][1] = 1; return; } if (d[x] == 0) { if (c1 & 1) { f[x][1] = 1; f[x][0] = 0; } else { f[x][1] = 0; f[x][0] = 1; } } else { if (c1 & 1) { f[x][1] = 0; f[x][0] = 1; } else { f[x][1] = 1; f[x][0] = 0; } } } void dfs2(int x, int p, int fx) { if (f[x][0] != f[x][1]) { for (int i = g[x]; ~i; i = e[i].next) if (e[i].to ^ p) if (f[e[i].to][0]) { dfs2(e[i].to, x, 0); } else { ans.push_back(e[i].w); dfs2(e[i].to, x, 1); } } else { int temp = -1, c1 = 0; for (int i = g[x]; ~i; i = e[i].next) if (e[i].to ^ p) { if (f[e[i].to][0] == f[e[i].to][1] && temp == -1) { temp = i; } else { if (f[e[i].to][0]) dfs2(e[i].to, x, 0); else { dfs2(e[i].to, x, 1); ans.push_back(e[i].w); c1++; } } } if (temp == -1) return; if ((c1 & 1) == fx ^ d[x]) dfs2(e[temp].to, x, 0); else { dfs2(e[temp].to, x, 1); ans.push_back(e[temp].w); } } } int main() { memset(g, -1, sizeof g); scanf( %d%d , &n, &m); LCT::init(); for (int i = 1; i <= n; i++) scanf( %d , d + i); for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); if (LCT::getf(u) ^ LCT::getf(v)) { addEdge(u, v, i); addEdge(v, u, i); LCT::merge(u, v); } } dfs(1, 0); if (!f[1][0]) { puts( -1 ); return 0; } dfs2(1, 0, 0); int numans = ans.size(); printf( %d n , numans); for (int i = 0; i < numans; i++) printf( %d n , ans[i]); return 0; }
|
module ARM_CU_ALU;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);
always@(IR)
begin
RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
reg S;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, MOD = 1e9 + 7; int main() { vector<int> a(27, -1), b(27, -1), c(27, -1); string str; cin >> str; for (int i = 0; i < (int)str.size(); i++) { if (a[str[i] - a ] == -1) { a[str[i] - a ] = i; c[str[i] - a ] = i; } else { b[str[i] - a ] = max(i - a[str[i] - a ], b[str[i] - a ]); a[str[i] - a ] = i; } } int x = (int)str.size() - 1; int ans = (int)str.size() / 2 + 1; for (int i = 0; i < 27; i++) { if (b[i] != -1) { b[i] = max({b[i], x - a[i] + 1, c[i] + 1}); ans = min(b[i], ans); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n, k; scanf( %d %d , &n, &k); while (k > 0) { if (n % 10 == 0) n /= 10; else n--; k--; } printf( %d , n); }
|
// hub
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// RR20140816 Remove unscrambling ROM code (now not scrambled)
`include "hub_mem.v"
module hub
(
input clk_cog,
input ena_bus,
input nres,
input [7:0] bus_sel,
input bus_r,
input bus_e,
input bus_w,
input [1:0] bus_s,
input [15:0] bus_a,
input [31:0] bus_d,
output reg [31:0] bus_q,
output bus_c,
output [7:0] bus_ack,
output reg [7:0] cog_ena,
output [7:0] ptr_w,
output [27:0] ptr_d,
output reg [7:0] cfg
);
// latch bus signals from cog[n]
reg rc;
reg ec;
reg wc;
reg [1:0] sc;
reg [15:0] ac;
reg [31:0] dc;
always @(posedge clk_cog)
if (ena_bus)
rc <= bus_r;
always @(posedge clk_cog or negedge nres)
if (!nres)
ec <= 1'b0;
else if (ena_bus)
ec <= bus_e;
always @(posedge clk_cog)
if (ena_bus)
wc <= bus_w;
always @(posedge clk_cog)
if (ena_bus)
sc <= bus_s;
always @(posedge clk_cog)
if (ena_bus)
ac <= bus_a;
always @(posedge clk_cog)
if (ena_bus)
dc <= bus_d;
// connect hub memory to signals from cog[n-1]
wire mem_w = ec && ~&sc && wc;
wire [3:0] mem_wb = sc[1] ? 4'b1111 // wrlong
: sc[0] ? ac[1] ? 4'b1100 : 4'b0011 // wrword
: 4'b0001 << ac[1:0]; // wrbyte
wire [31:0] mem_d = sc[1] ? dc // wrlong
: sc[0] ? {2{dc[15:0]}} // wrword
: {4{dc[7:0]}}; // wrbyte
wire [31:0] mem_q;
hub_mem hub_mem_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.w (mem_w),
.wb (mem_wb),
.a (ac[15:2]),
.d (mem_d),
.q (mem_q) );
// latch bus signals from cog[n-1]
reg rd;
reg ed;
reg [1:0] sd;
reg [1:0] ad;
always @(posedge clk_cog)
if (ena_bus)
rd <= !rc && ac[15];
always @(posedge clk_cog or negedge nres)
if (!nres)
ed <= 1'b0;
else if (ena_bus)
ed <= ec;
always @(posedge clk_cog)
if (ena_bus)
sd <= sc;
always @(posedge clk_cog)
if (ena_bus)
ad <= ac[1:0];
// set bus output according to cog[n-2]
wire [31:0] ramq = mem_q;
always @(posedge clk_cog)
bus_q <= sd[1] ? sd[0] ? {29'b0, sys_q} // cogid/coginit/locknew
: ramq // rdlong
: sd[0] ? ramq >> {ad[1], 4'b0} & 32'h0000FFFF // rdword
: ramq >> {ad[1:0], 3'b0} & 32'h000000FF; // rdbyte
assign bus_c = sys_c;
// generate bus acknowledge for cog[n-2]
assign bus_ack = ed ? {bus_sel[1:0], bus_sel[7:2]} : 8'b0;
// sys common logic
//
// ac in dc in num sys_q sys_c
// -----------------------------------------------------------------------------------------
// 000 CLKSET config(8) - - -
// 001 COGID - - [n-1] -
// 010 COGINIT ptr(28),newx,id(3) id(3)/newx id(3)/newx all
// 011 COGSTOP -,id(3) id(3) id(3) -
// 100 LOCKNEW - newx newx all
// 101 LOCKRET -,id(3) id(3) id(3) -
// 110 LOCKSET -,id(3) id(3) id(3) lock_state[id(3)]
// 111 LOCKCLR -,id(3) id(3) id(3) lock_state[id(3)]
wire sys = ec && (&sc);
wire [7:0] enc = ac[2] ? lock_e : cog_e;
wire all = &enc; // no free cogs/locks
wire [2:0] newx = &enc[3:0] ? &enc[5:4] ? enc[6] ? 3'b111 // x1111111 -> 111
: 3'b110 // x0111111 -> 110
: enc[4] ? 3'b101 // xx011111 -> 101
: 3'b100 // xxx01111 -> 100
: &enc[1:0] ? enc[2] ? 3'b011 // xxxx0111 -> 011
: 3'b010 // xxxxx011 -> 010
: enc[0] ? 3'b001 // xxxxxx01 -> 001
: 3'b000; // xxxxxxx0 -> 000
wire [2:0] num = ac[2:0] == 3'b010 && dc[3] || ac[2:0] == 3'b100 ? newx : dc[2:0];
wire [7:0] num_dcd = 1'b1 << num;
// cfg
always @(posedge clk_cog or negedge nres)
if (!nres)
cfg <= 8'b0;
else if (ena_bus && sys && ac[2:0] == 3'b000)
cfg <= dc[7:0];
// cogs
reg [7:0] cog_e;
wire cog_start = sys && ac[2:0] == 3'b010 && !(dc[3] && all);
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_e <= 8'b00000001;
else if (ena_bus && sys && ac[2:1] == 2'b01)
cog_e <= cog_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_ena <= 8'b0;
else if (ena_bus)
cog_ena <= cog_e & ~({8{cog_start}} & num_dcd);
assign ptr_w = {8{cog_start}} & num_dcd;
assign ptr_d = dc[31:4];
// locks
reg [7:0] lock_e;
reg [7:0] lock_state;
always @(posedge clk_cog or negedge nres)
if (!nres)
lock_e <= 8'b0;
else if (ena_bus && sys && ac[2:1] == 2'b10)
lock_e <= lock_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog)
if (ena_bus && sys && ac[2:1] == 2'b11)
lock_state <= lock_state & ~num_dcd | {8{!ac[0]}} & num_dcd;
wire lock_mux = lock_state[dc[2:0]];
// output
reg [2:0] sys_q;
reg sys_c;
always @(posedge clk_cog)
if (ena_bus && sys)
sys_q <= ac[2:0] == 3'b001 ? { bus_sel[7] || bus_sel[6] || bus_sel[5] || bus_sel[0], // cogid
bus_sel[7] || bus_sel[4] || bus_sel[3] || bus_sel[0],
bus_sel[6] || bus_sel[4] || bus_sel[2] || bus_sel[0] }
: num; // others
always @(posedge clk_cog)
if (ena_bus && sys)
sys_c <= ac[2:1] == 2'b11 ? lock_mux // lockset/lockclr
: all; // others
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double PI = acos(-1.0); const int N = 1e5 + 5; int n; map<string, set<string> > m; map<string, set<string> > m2; set<string> host; vector<set<string> > res; int main(void) { ios_base::sync_with_stdio(false); cin >> n; while (n--) { string s; cin >> s; host.insert(s); string s1 = , s2 = ; int count = 0; for (int i = 0; i < (int)s.size(); i++) { if (s[i] == / ) count++; if (count < 3) { s1 += s[i]; } else { s2 += s[i]; } } s1 += ; s2 += ; m[s1].insert(s2); } for (map<string, set<string> >::iterator it = m.begin(); it != m.end(); it++) { string str = ; for (set<string>::iterator itt = (it->second).begin(); itt != (it->second).end(); itt++) { str += (*itt); } m2[str].insert(it->first); } for (map<string, set<string> >::iterator it = m2.begin(); it != m2.end(); it++) { if ((it->second).size() > 1) { res.push_back(it->second); } } cout << res.size() << endl; for (int i = 0; i < (int)res.size(); i++) { for (set<string>::iterator it = res[i].begin(); it != res[i].end(); it++) { cout << (*it) << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[105], b[105], t, i, k; cin >> t; for (i = 1; i < t + 1; i++) { scanf( %d , &a[i]); } for (i = 1; i < t + 1; i++) { k = a[i]; b[k] = i; } for (i = 1; i < t + 1; i++) { printf( %d , b[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[105]; int b[105]; int main() { int n, m, i, j; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d%d , &a[i], &b[i]); int con = 0; for (i = 1; i <= 10000; i++) { int s = 0; for (j = 1; j <= n; j++) s += (i * a[j] / b[j] + 1); if (s == m) con++; } printf( %d n , con); }
|
#include <bits/stdc++.h> using namespace std; long long int n, m, cnt = 0, k, cntt = 0, cnts = 0; long long int v[100001]; bool vis[100001], ans[100001]; long long int cnte[100001]; int main() { cin >> n >> m; memset(vis, false, sizeof(vis)); memset(cnte, 0, sizeof(cnte)); for (int i = 1; i <= m; i++) { cin >> v[i]; cnte[v[i]]++; if (vis[v[i]] == false) { vis[v[i]] = true; cnt++; } if (cnt == n) { ans[i] = 1; for (int j = 1; j <= n; j++) { if (cnte[j] > 1) { cnte[j]--; } else { cnt--; cnte[j]--; vis[j] = false; } } } else { ans[i] = 0; } } for (int i = 1; i <= m; i++) { cout << ans[i]; } }
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Top(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// ports of submodule fbox_core
wire [63 : 0] fbox_core$req_v1,
fbox_core$req_v2,
fbox_core$req_v3,
fbox_core$word_fst;
wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode;
wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd;
wire [2 : 0] fbox_core$req_rm;
wire fbox_core$EN_req,
fbox_core$EN_server_reset_request_put,
fbox_core$EN_server_reset_response_get,
fbox_core$RDY_server_reset_request_put,
fbox_core$RDY_server_reset_response_get,
fbox_core$valid;
// rule scheduling signals
wire CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// action method server_reset_request_put
assign RDY_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign CAN_FIRE_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign CAN_FIRE_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = fbox_core$valid ;
// value method word_fst
assign word_fst = fbox_core$word_fst ;
// value method word_snd
assign word_snd = fbox_core$word_snd ;
// submodule fbox_core
mkFBox_Core fbox_core(.verbosity(verbosity),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(fbox_core$req_f7),
.req_opcode(fbox_core$req_opcode),
.req_rm(fbox_core$req_rm),
.req_rs2(fbox_core$req_rs2),
.req_v1(fbox_core$req_v1),
.req_v2(fbox_core$req_v2),
.req_v3(fbox_core$req_v3),
.EN_server_reset_request_put(fbox_core$EN_server_reset_request_put),
.EN_server_reset_response_get(fbox_core$EN_server_reset_response_get),
.EN_req(fbox_core$EN_req),
.RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get),
.valid(fbox_core$valid),
.word_fst(fbox_core$word_fst),
.word_snd(fbox_core$word_snd));
// submodule fbox_core
assign fbox_core$req_f7 = req_f7 ;
assign fbox_core$req_opcode = req_opcode ;
assign fbox_core$req_rm = req_rm ;
assign fbox_core$req_rs2 = req_rs2 ;
assign fbox_core$req_v1 = req_v1 ;
assign fbox_core$req_v2 = req_v2 ;
assign fbox_core$req_v3 = req_v3 ;
assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ;
assign fbox_core$EN_server_reset_response_get =
EN_server_reset_response_get ;
assign fbox_core$EN_req = EN_req ;
endmodule // mkFBox_Top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_4_V
`define SKY130_FD_SC_MS__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_4_V
|
#include<bits/stdc++.h> #define int long long #define pii pair<int,int> #define F first #define S second #define pi acos(-1.0) #define pb push_back #define sf(x) scanf( %lld ,&x) #define pf(x) printf( %lld ,&x) using namespace std; const int mod=1e9+7; int a1[2000],ar[2000],ff[2000] ; map<int,int>mp,mk ; int bigmod(int a , int b) { if(b==0) return 1 ; int x = bigmod(a,b/2) ; x=((x%mod)*(x%mod))%mod ; if(b%2) x=((x%mod)*(a%mod))%mod ; return x ; } int ncr(int a , int b) { int p=(ff[a-b]*ff[b])%mod ; p=(ff[a]*bigmod(p,mod-2)) ; p%=mod ; return p ; } int32_t main() { ios_base::sync_with_stdio(0) ; cin.tie(0) ; cout.tie(0) ; ff[0]=1 ; ff[1]=1 ; for(int i = 2 ; i <= 1000 ; i++) ff[i]=(ff[i-1]*i)%mod ; int t ; cin>>t ; while(t--) { int n,k,mx=0 ; cin>>n>>k ; mp.clear() ; mk.clear() ; set<int>st ; for(int i = 1 ; i <= n ; i++){cin>>ar[i] ; mp[ar[i]]++ ; a1[i]=ar[i] ; } sort(a1+1,a1+n+1) ; reverse(a1+1,a1+n+1) ; // for(int i = 1 ; i <= n ; i++) cout<<a1[i]<< ; cout<<endl ; for(int i = 1 ; i <= k ; i++) {mx+=a1[i] ; st.insert(a1[i]) ; mk[a1[i]]++ ;} int ans=1 ; for(int x : st) { int p=mp[x],q=mk[x] ; // cout<<x<< <<p<< <<q<<endl ; ans*=ncr(p,q); ans%=mod ; } cout<<ans<<endl ; } }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_8x16_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_8x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_8x16_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,fma ) #pragma GCC optimize( unroll-loops ) using namespace std; int n, k, t, a, b; long long w, z, x[3008], y[3008]; int main() { for (ios::sync_with_stdio(0), cin.tie(0), cin >> n >> k; n--; z = b = 0) { for (cin >> t; t--;) for (cin >> a, z += a, ++b, a = k + 1; a-- > b; y[a] < (w = x[a - b] + z) ? y[a] = w : 0) ; for (a = k + 1; a--; x[a] = y[a]) ; } cout << x[k], exit(0); }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C;
assign CO = C;
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
wire ci;
wire co;
// First in chain
generate if (i == 0) begin
// CI connected to a constant
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
localparam INIT = (_TECHMAP_CONSTVAL_CI_ == 0) ?
16'b0110_0110_0000_1000:
16'b1001_1001_0000_1110;
// LUT4 configured as 1-bit adder with CI=const
adder_lut4 #(
.LUT(INIT),
.IN2_IS_CIN(1'b0)
) lut_ci_adder (
.in({AA[i], BB[i], 1'b1, 1'b1}),
.cin(),
.lut4_out(Y[i]),
.cout(ci)
);
// CI connected to a non-const driver
end else begin
// LUT4 configured as passthrough to drive CI of the next stage
adder_lut4 #(
.LUT(16'b0000_0000_0000_1100),
.IN2_IS_CIN(1'b0)
) lut_ci (
.in({1'b1, CI, 1'b1, 1'b1}),
.cin(),
.lut4_out(),
.cout(ci)
);
end
// Not first in chain
end else begin
assign ci = C[i-1];
end endgenerate
// ....................................................
// Single 1-bit adder, mid-chain adder or non-const CI
// adder
generate if ((i == 0 && _TECHMAP_CONSTMSK_CI_ == 0) || (i > 0)) begin
// LUT4 configured as full 1-bit adder
adder_lut4 #(
.LUT(16'b1001_0110_0110_1000),
.IN2_IS_CIN(1'b1)
) lut_adder (
.in({AA[i], BB[i], 1'b1, 1'b1}),
.cin(ci),
.lut4_out(Y[i]),
.cout(co)
);
end else begin
assign co = ci;
end endgenerate
// ....................................................
// Last in chain
generate if (i == Y_WIDTH-1) begin
// LUT4 configured for passing its CI input to output. This should
// get pruned if the actual CO port is not connected anywhere.
adder_lut4 #(
.LUT(16'b1111_0000_1111_0000),
.IN2_IS_CIN(1'b1)
) lut_co (
.in({1'b1, 1'b1, 1'b1, 1'b1}),
.cin(co),
.lut4_out(C[i]),
.cout()
);
// Not last in chain
end else begin
assign C[i] = co;
end endgenerate
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double weight = 0; long n, m; cin >> n >> m; long long a[n]; long long b[n]; bool flag = 0; for (long i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) { flag = 1; } } for (long i = 0; i < n; i++) { cin >> b[i]; if (b[i] == 1) { flag = 1; } } if (flag == 1) { cout << -1 << endl; exit(0); } weight = m; weight += double(weight) / double(b[0] - 1); for (long i = n - 1; i > 0; i--) { weight += double(weight) / double(a[i] - 1); weight += double(weight) / double(b[i] - 1); } weight += double(weight) / double(a[0] - 1); cout << setprecision(30) << weight - m << endl; }
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long long int lli; const int mod=1e9+7; int main() { ll t; cin>>t; while(t--) { ll n; cin>>n; if(n<=32) { ll m=n-3; m+=5; cout<<m<<endl; for(ll i=3; i<n; i++) { cout<<i<< <<n<<endl; } for(ll i=0; i<5; i++) { cout<<n<< <<2<<endl; } } else { ll m = n-4; m+=9; cout<<m<<endl; for(ll i=3; i<n; i++) { if(i==16) continue; cout<<i<< <<n<<endl; } for(ll i=0; i<5; i++) { cout<<n<< <<16<<endl; } for(ll i=0; i<4; i++) { cout<<16<< <<2<<endl; } //cout<<m<<nn; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_BEHAVIORAL_V
|
// Interrupt request and interrupt service register pair
module rzrp(
input clk_sys,
input imask, // interrupt mask
input irq, // async irq source
input w, // clocked irq source
input rz_c, // irq clock
input rz_r, // irq clear
input rp_c, // interrupt service clock
input prio_in, // interrupt priority chain input
output rz, // irq
output sz, // irq & mask
output rp, // interrupt service register
output prio_out // interrupt priority chain output
);
assign sz = rz & imask;
always @ (posedge clk_sys, posedge irq) begin
if (irq) rz <= 1'b1;
else if (rz_r) rz <= 1'b0;
else if (rz_c) case ({w, rp})
2'b00 : rz <= rz;
2'b01 : rz <= 1'b0;
2'b10 : rz <= 1'b1;
2'b11 : rz <= ~rz;
endcase
end
// NOTE: rp_c should be too long to be a clock enable signal here, but it seems to work just fine
always @ (posedge clk_sys, posedge prio_in) begin
if (prio_in) rp <= 1'b0;
else if (rp_c) rp <= sz;
end
assign prio_out = rp | prio_in;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`default_nettype wire
module sram1024x18 (
clk_a,
cen_a,
wen_a,
addr_a,
wmsk_a,
wdata_a,
rdata_a,
clk_b,
cen_b,
wen_b,
addr_b,
wmsk_b,
wdata_b,
rdata_b
);
(* clkbuf_sink *)
input wire clk_a;
input wire cen_a;
input wire wen_a;
input wire [9:0] addr_a;
input wire [17:0] wmsk_a;
input wire [17:0] wdata_a;
output reg [17:0] rdata_a;
(* clkbuf_sink *)
input wire clk_b;
input wire cen_b;
input wire wen_b;
input wire [9:0] addr_b;
input wire [17:0] wmsk_b;
input wire [17:0] wdata_b;
output reg [17:0] rdata_b;
reg [17:0] ram [1023:0];
reg [9:0] laddr_a;
reg [9:0] laddr_b;
reg lcen_a;
reg lwen_a;
reg [17:0] lwdata_a;
reg lcen_b;
reg lwen_b;
reg [17:0] lwdata_b;
reg [17:0] lwmsk_a;
reg [17:0] lwmsk_b;
always @(posedge clk_a) begin
laddr_a <= addr_a;
lwdata_a <= wdata_a;
lwmsk_a <= wmsk_a;
lcen_a <= cen_a;
lwen_a <= wen_a;
end
always @(posedge clk_b) begin
laddr_b <= addr_b;
lwdata_b <= wdata_b;
lwmsk_b <= wmsk_b;
lcen_b <= cen_b;
lwen_b <= wen_b;
end
always @(*) begin
if ((lwen_b == 0) && (lcen_b == 0)) begin
ram[laddr_b][0] = (lwmsk_b[0] ? ram[laddr_b][0] : lwdata_b[0]);
ram[laddr_b][1] = (lwmsk_b[1] ? ram[laddr_b][1] : lwdata_b[1]);
ram[laddr_b][2] = (lwmsk_b[2] ? ram[laddr_b][2] : lwdata_b[2]);
ram[laddr_b][3] = (lwmsk_b[3] ? ram[laddr_b][3] : lwdata_b[3]);
ram[laddr_b][4] = (lwmsk_b[4] ? ram[laddr_b][4] : lwdata_b[4]);
ram[laddr_b][5] = (lwmsk_b[5] ? ram[laddr_b][5] : lwdata_b[5]);
ram[laddr_b][6] = (lwmsk_b[6] ? ram[laddr_b][6] : lwdata_b[6]);
ram[laddr_b][7] = (lwmsk_b[7] ? ram[laddr_b][7] : lwdata_b[7]);
ram[laddr_b][8] = (lwmsk_b[8] ? ram[laddr_b][8] : lwdata_b[8]);
ram[laddr_b][9] = (lwmsk_b[9] ? ram[laddr_b][9] : lwdata_b[9]);
ram[laddr_b][10] = (lwmsk_b[10] ? ram[laddr_b][10] : lwdata_b[10]);
ram[laddr_b][11] = (lwmsk_b[11] ? ram[laddr_b][11] : lwdata_b[11]);
ram[laddr_b][12] = (lwmsk_b[12] ? ram[laddr_b][12] : lwdata_b[12]);
ram[laddr_b][13] = (lwmsk_b[13] ? ram[laddr_b][13] : lwdata_b[13]);
ram[laddr_b][14] = (lwmsk_b[14] ? ram[laddr_b][14] : lwdata_b[14]);
ram[laddr_b][15] = (lwmsk_b[15] ? ram[laddr_b][15] : lwdata_b[15]);
ram[laddr_b][16] = (lwmsk_b[16] ? ram[laddr_b][16] : lwdata_b[16]);
ram[laddr_b][17] = (lwmsk_b[17] ? ram[laddr_b][17] : lwdata_b[17]);
lwen_b = 1;
end
if (lcen_b == 0) begin
rdata_b = ram[laddr_b];
lcen_b = 1;
end
else
rdata_b = rdata_b;
end
always @(*) begin
if ((lwen_a == 0) && (lcen_a == 0)) begin
ram[laddr_a][0] = (lwmsk_a[0] ? ram[laddr_a][0] : lwdata_a[0]);
ram[laddr_a][1] = (lwmsk_a[1] ? ram[laddr_a][1] : lwdata_a[1]);
ram[laddr_a][2] = (lwmsk_a[2] ? ram[laddr_a][2] : lwdata_a[2]);
ram[laddr_a][3] = (lwmsk_a[3] ? ram[laddr_a][3] : lwdata_a[3]);
ram[laddr_a][4] = (lwmsk_a[4] ? ram[laddr_a][4] : lwdata_a[4]);
ram[laddr_a][5] = (lwmsk_a[5] ? ram[laddr_a][5] : lwdata_a[5]);
ram[laddr_a][6] = (lwmsk_a[6] ? ram[laddr_a][6] : lwdata_a[6]);
ram[laddr_a][7] = (lwmsk_a[7] ? ram[laddr_a][7] : lwdata_a[7]);
ram[laddr_a][8] = (lwmsk_a[8] ? ram[laddr_a][8] : lwdata_a[8]);
ram[laddr_a][9] = (lwmsk_a[9] ? ram[laddr_a][9] : lwdata_a[9]);
ram[laddr_a][10] = (lwmsk_a[10] ? ram[laddr_a][10] : lwdata_a[10]);
ram[laddr_a][11] = (lwmsk_a[11] ? ram[laddr_a][11] : lwdata_a[11]);
ram[laddr_a][12] = (lwmsk_a[12] ? ram[laddr_a][12] : lwdata_a[12]);
ram[laddr_a][13] = (lwmsk_a[13] ? ram[laddr_a][13] : lwdata_a[13]);
ram[laddr_a][14] = (lwmsk_a[14] ? ram[laddr_a][14] : lwdata_a[14]);
ram[laddr_a][15] = (lwmsk_a[15] ? ram[laddr_a][15] : lwdata_a[15]);
ram[laddr_a][16] = (lwmsk_a[16] ? ram[laddr_a][16] : lwdata_a[16]);
ram[laddr_a][17] = (lwmsk_a[17] ? ram[laddr_a][17] : lwdata_a[17]);
lwen_a = 1;
end
if (lcen_a == 0) begin
rdata_a = ram[laddr_a];
lcen_a = 1;
end
else
rdata_a = rdata_a;
end
endmodule
`default_nettype none
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_counters(
input sys_clk,
input first,
input next,
input [6:0] hmesh_last,
input [6:0] vmesh_last,
output [31:0] r0,
output [31:0] r1,
output reg last
);
reg [6:0] r0r;
assign r0 = {25'd0, r0r};
reg [6:0] r1r;
assign r1 = {25'd0, r1r};
always @(posedge sys_clk) begin
if(first) begin
r0r <= 7'd0;
r1r <= 7'd0;
end else if(next) begin
if(r0r == hmesh_last) begin
r0r <= 7'd0;
r1r <= r1r + 7'd1;
end else
r0r <= r0r + 7'd1;
end
end
/* Having some latency in the generation of "last"
* is not a problem, because DMA is never immediately
* triggered after "first" or "next" has been
* asserted.
*/
always @(posedge sys_clk)
last <= (r0r == hmesh_last) & (r1r == vmesh_last);
endmodule
|
#include <bits/stdc++.h> const int N = 200005; const int M = 500005; using namespace std; pair<int, int> a[N]; int p[20][M]; int main() { int n, m; scanf( %d%d , &n, &m); int i, j; for (i = 0; i < n; i++) { scanf( %d%d , &a[i].first, &a[i].second); } sort(a, a + n); memset(p, -1, sizeof(p)); int maxe = -1; j = 0; for (i = 0; i < M; i++) { while (j < n && a[j].first <= i) { if (a[j].second > maxe) maxe = a[j].second; j++; } if (maxe >= i) p[0][i] = maxe; else p[0][i] = -1; } for (j = 0; j < 19; j++) for (i = 0; i < M; i++) if (p[j][i] == -1) p[j + 1][i] = -1; else p[j + 1][i] = p[j][p[j][i]]; int u, v; for (i = 0; i < m; i++) { scanf( %d%d , &u, &v); int ans = 0; for (j = 19; j >= 0; j--) if (p[j][u] < v) { u = p[j][u]; ans += 1 << j; } u = p[0][u]; ans++; if (u >= v) printf( %d n , ans); else printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> char s[101]; char t[10] = ><+-.,[] ; int c[10] = {8, 9, 10, 11, 12, 13, 14, 15}; void func() { int n = strlen(s), i, j, ans = 0; const int mod = 1000003; for (i = 0; i < n; i++) { for (j = 0; j < 8; j++) { if (t[j] == s[i]) { ans = (ans * 16 + c[j]) % mod; break; } } } printf( %d n , ans); } int main(int argc, char **argv) { while (scanf( %s , s) == 1) { func(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; pair<long long, long long> ans1[N], ans2[N]; long long x; long long cal(long long n) { n--; long long tmp = n * (n + 1) * (2 * n + 1) / 6; n++; tmp -= (n * n * n - n * n) / 2; if (2 * (x - tmp) % (n * n + n)) return -1; long long m = 2 * (x - tmp) / (n * n + n); return m; } void solve() { int cnt = 0, tot = 0; for (int i = 1; i < 1500000; i++) { long long m = cal((long long)i); if (m == -1) continue; if (m < i) break; ans1[tot++] = make_pair(i, m); if (m == i) break; ans2[cnt++] = make_pair(m, i); } printf( %d n , tot + cnt); for (int i = 0; i < tot; i++) printf( %I64d %I64d n , ans1[i].first, ans1[i].second); for (int i = cnt - 1; i >= 0; i--) printf( %I64d %I64d n , ans2[i].first, ans2[i].second); } int main() { scanf( %I64d , &x); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int ask(int l) { cout << ? ; for (int i = 0; i < n - 1; i++) cout << 1 << ; cout << l << endl; cout.flush(); int k; cin >> k; if (k == 0) return 1; else return 0; } int ask1(int l, int x) { cout << ? ; for (int i = 0; i < n - 1; i++) { cout << x << ; } cout << l << n ; cout.flush(); int k; cin >> k; return k; } int main() { cin >> n; int t = 0; int k = n; for (int i = 0; i < n - 1; ++i) { if (ask(i + 2)) { break; } k--; } int ans[n]; ans[n - 1] = k; for (int i = 1; i <= n; i++) { if (i != k) { int m = ask1(i, k); ans[m - 1] = i; } } cout << ! ; for (int i = 0; i < n; ++i) cout << ans[i] << ; cout << n ; cout.flush(); }
|
/***********************************************************************
Single Port RAM that maps to a Xilinx/Lattice BRAM
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This is a program memory for the AVR. It maps to a Xilinx/Lattice
BRAM.
This version can be modified by the CPU (i. e. SPM instruction)
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the BSD license
------------------------------------------------------------------------------
Design unit: SinglePortPM(Xilinx) (Entity and architecture)
File name: pm_s_rw.in.v (template used)
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
Target FPGA: Spartan 3 (XC3S1500-4-FG456)
iCE40 (iCE40HX4K)
Language: Verilog
Wishbone: No
Synthesis tools: Xilinx Release 9.2.03i - xst J.39
iCEcube2.2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module lattuino_1_blPM_2
#(
parameter WORD_SIZE=16,// Word Size
parameter FALL_EDGE=0, // Ram clock falling edge
parameter ADDR_W=13 // Address Width
)
(
input clk_i,
input [ADDR_W-1:0] addr_i,
output [WORD_SIZE-1:0] data_o,
input we_i,
input [WORD_SIZE-1:0] data_i
);
localparam ROM_SIZE=2**ADDR_W;
reg [ADDR_W-1:0] addr_r;
reg [WORD_SIZE-1:0] rom[0:ROM_SIZE-1];
initial begin
$readmemh("../../../Work/lattuino_1_bl_2_v.dat",rom,696);
end
generate
if (!FALL_EDGE)
begin : use_rising_edge
always @(posedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_rising_edge
else
begin : use_falling_edge
always @(negedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_falling_edge
endgenerate
assign data_o=rom[addr_r];
endmodule // lattuino_1_blPM_2
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int n) { if (x == 0) return 0; if (n == 0) return 1; if (n == 1) return x; if (n % 2 == 0) { long long int temp = power(x, n / 2); return (temp % 1000000007 * temp % 1000000007) % 1000000007; } else { long long int temp = power(x, n / 2); return (x % 1000000007 * ((temp % 1000000007 * temp % 1000000007) % 1000000007) % 1000000007) % 1000000007; } } long long int findroot(long long int i, long long int Arr[]) { while (Arr[i] != i) { Arr[i] = Arr[Arr[i]]; i = Arr[i]; } return i; } void weightedunion(long long int i, long long int j, long long int arr[], long long int size[]) { long long int x = findroot(i, arr); long long int y = findroot(j, arr); if (size[x] > size[y]) { size[x] += size[y]; arr[y] = arr[x]; } else { size[y] += size[x]; arr[x] = arr[y]; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, k, i, j, temp, ans = 0; cin >> n >> k; long long int arr[n]; set<long long int> s; map<long long int, long long int> mp; for (i = 0; i < n; i++) { cin >> arr[i]; mp[arr[i]]++; } if (k == 1) cout << mp.size() << n ; else { sort(arr, arr + n); for (i = 0; i < n; i++) { if (s.find(arr[i]) != s.end()) continue; else { s.insert(arr[i]); vector<long long int> inc; vector<long long int> ninc; inc.push_back(mp[arr[i]]); ninc.push_back(0); for (temp = k * arr[i]; temp <= (long long int)1e9; temp = temp * k) { s.insert(temp); if (mp.find(temp) == mp.end()) { inc.push_back(max(inc.back(), ninc.back())); ninc.push_back(inc.back()); } else { long long int x = inc.back(), y = ninc.back(); inc.push_back(mp[arr[i]] + ninc.back()); ninc.push_back(max(x, y)); } } ans += max(inc.back(), ninc.back()); } } cout << ans << n ; } return 0; }
|
`include "defines.v"
module id_ex(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//´ÓÒëÂë½×¶Î´«µÝµÄÐÅÏ¢
input wire[`AluOpBus] id_aluop,
input wire[`AluSelBus] id_alusel,
input wire[`RegBus] id_reg1,
input wire[`RegBus] id_reg2,
input wire[`RegAddrBus] id_wd,
input wire id_wreg,
input wire[`RegBus] id_link_address,
input wire id_is_in_delayslot,
input wire next_inst_in_delayslot_i,
input wire[`RegBus] id_inst,
input wire[`RegBus] id_current_inst_address,
input wire[31:0] id_excepttype,
//´«µÝµ½Ö´Ðн׶εÄÐÅÏ¢
output reg[`AluOpBus] ex_aluop,
output reg[`AluSelBus] ex_alusel,
output reg[`RegBus] ex_reg1,
output reg[`RegBus] ex_reg2,
output reg[`RegAddrBus] ex_wd,
output reg ex_wreg,
output reg[`RegBus] ex_link_address,
output reg ex_is_in_delayslot,
output reg is_in_delayslot_o,
output reg[`RegBus] ex_inst,
output reg[31:0] ex_excepttype,
output reg[`RegBus] ex_current_inst_address
);
always @ (posedge clk) begin
if (rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
is_in_delayslot_o <= `NotInDelaySlot;
ex_inst <= `ZeroWord;
ex_excepttype <= `ZeroWord;
ex_current_inst_address <= `ZeroWord;
end else if(flush == 1'b1 ) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_excepttype <= `ZeroWord;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
ex_current_inst_address <= `ZeroWord;
is_in_delayslot_o <= `NotInDelaySlot;
end else if(stall[2] == `Stop && stall[3] == `NoStop) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
ex_inst <= `ZeroWord;
ex_excepttype <= `ZeroWord;
ex_current_inst_address <= `ZeroWord;
end else if(stall[2] == `NoStop) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_link_address <= id_link_address;
ex_is_in_delayslot <= id_is_in_delayslot;
is_in_delayslot_o <= next_inst_in_delayslot_i;
ex_inst <= id_inst;
ex_excepttype <= id_excepttype;
ex_current_inst_address <= id_current_inst_address;
end
end
endmodule
|
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (CLK_100MHZ);
parameter LOOP_LOG2 = 0;
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input CLK_100MHZ;
////
reg [255:0] state = 0;
reg [127:0] data = 0;
reg [31:0] nonce = 32'h0;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLK_IN1(CLK_100MHZ), .CLK_OUT1(hash_clk));
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP), .NUM_ROUNDS(64)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, data}),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP), .NUM_ROUNDS(LOOP == 1 ? 61 : 64)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
`ifndef SIM
wire [35:0] control0, control1, control2;
chipscope_icon ICON_inst ( .CONTROL0(control0), .CONTROL1(control1), .CONTROL2(control2));
chipscope_vio_tochip midstate_vw_blk ( .CONTROL(control0), .CLK(hash_clk), .SYNC_OUT(midstate_vw) );
chipscope_vio_tochip data_vw_blk ( .CONTROL(control1), .CLK(hash_clk), .SYNC_OUT(data2_vw) );
`endif
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
`ifndef SIM
chipscope_vio_fromchip golden_nonce_vw_blk ( .CONTROL(control2), .CLK(hash_clk), .SYNC_IN(golden_nonce) );
`endif
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
assign cnt_next = (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next = feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
if (LOOP == 1)
is_golden_ticket <= (hash2[159:128] + 32'h5be0cd19 == 32'h00000000);
else
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd128;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[50][50]; int main() { int n, m; cin >> n >> m; for (int j = 0; j < m; j++) a[0][j] = # ; for (int j = 0; j < m - 1; j++) a[1][j] = . ; a[1][m - 1] = # ; for (int i = 2; i < n; i++) { for (int j = 0; j < m; j++) { if (i % 2 == 0) a[i][j] = # ; else { if (j == 0 && a[i - 2][0] == . ) a[i][j] = # ; else if (j == m - 1 && a[i - 2][m - 1] == . ) a[i][j] = # ; else a[i][j] = . ; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << a[i][j]; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; const int size = 1e6 + 1; int n; double a[size]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n; double l, r, c1, c2; l = r = c1 = c2 = 0; string s; cin >> s; for (int i = int(0); i < int(n); i++) { if (s[i] == ? ) a[i] = -1; else a[i] = s[i] - 0 ; if ((i) < n / 2) { if (a[i] != -1) l += a[i]; else c1++; } else { if (a[i] != -1) r += a[i]; else c2++; } } bool ans = false; if (l + 9 * ceil(double(c1 / 2.0)) != r + 9 * ceil(double(c2 / 2.0))) ans = true; if (!ans) cout << Bicarp ; else cout << Monocarp ; return 0; }
|
#include <bits/stdc++.h> template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (b < a) { a = b; return 1; } return 0; } using namespace std; const double eps = 1e-10; int sgn(double x) { return (x > eps) - (x < -eps); } int cmp(double x, double y) { return sgn(x - y); } struct P { double x, y, k; P() : x(0), y(0) {} P(double a, double b) : x(a), y(b) {} void in() { scanf( %lf%lf , &x, &y); } P operator+(const P &a) const { return P(x + a.x, y + a.y); } P operator-(const P &a) const { return P(x - a.x, y - a.y); } P operator*(const double &a) const { return P(x * a, y * a); } P operator/(const double &a) const { return P(x / a, y / a); } double norm2() { return x * x + y * y; } } p[1000 + 5]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); p[i] = P((double)a / b, (double)c / d); p[i] = p[i] / p[i].norm2(); } vector<P> pt; for (int i = 1; i <= n; i++) for (int j = 1; j <= i - 1; j++) { P mid = (p[i] + p[j]) / 2, tmp = p[i] - p[j]; mid.k = sgn(tmp.x) == 0 ? 1e100 : tmp.y / tmp.x; pt.push_back(mid); } sort(pt.begin(), pt.end(), [](P a, P b) { if (cmp(a.x, b.x)) return cmp(a.x, b.x) < 0; if (cmp(a.y, b.y)) return cmp(a.y, b.y) < 0; return a.k < b.k; }); int N = pt.size(); long long ans = 0; for (int l = 0, r; l < N; l = r) { for (r = l; r < N && cmp(pt[r].x, pt[l].x) == 0 && cmp(pt[r].y, pt[l].y) == 0; r++) ; int c = 2, ways = 1; for (int i = l + 1; i <= r; i++) { if (i < r && cmp(pt[i].k, pt[i - 1].k) == 0) c++; else ways = 1ll * ways * c % 1000000007, c = 2; } ans = (ans + ways - 1 - (r - l) + 1000000007) % 1000000007; } printf( %lld n , ans); return 0; }
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Butterworth low pass IIR filter
// input: 8bit ADC signal, 1MS/s
// output: 8bit value, Fc=20khz
//
// coef: (using http://www-users.cs.york.ac.uk/~fisher/mkfilter/trad.html)
// Recurrence relation:
// y[n] = ( 1 * x[n- 2])
// + ( 2 * x[n- 1])
// + ( 1 * x[n- 0])
// + ( -0. * y[n- 2])
// + ( 1. * y[n- 1])
//
// therefore:
// a = [1,2,1]
// b = [-0., 1.]
// b is approximated to b = [-0xd6/0x100, 0x1d3 / 0x100] (for optimization)
// gain = 2.761139367e2
//
// See details about its design see
// https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
// clk is 24MHz, the IIR filter is designed for 1MS/s
// hence we need to divide it by 24
// using a shift register takes less area than a counter
reg [23:0] cnt = 1;
assign rdy = cnt[0];
always @(posedge clk)
cnt <= {cnt[22:0], cnt[23]};
reg [7:0] x0 = 0;
reg [7:0] x1 = 0;
reg [16:0] y0 = 0;
reg [16:0] y1 = 0;
always @(posedge clk)
begin
if (rdy)
begin
x0 <= x1;
x1 <= adc_d;
y0 <= y1;
y1 <=
// center the signal:
// input range is [0; 255]
// We want "128" to be at the center of the 17bit register
// (128+z)*gain = 17bit center
// z = (1<<16)/gain - 128 = 109
// We could use 9bit x registers for that, but that would be
// a waste, let's just add the constant during the computation
// (x0+109) + 2*(x1+109) + (x2+109) = x0 + 2*x1 + x2 + 436
x0 + {x1, 1'b0} + adc_d + 436
// we want "- y0 * 0xd6 / 0x100" using only shift and add
// 0xd6 == 0b11010110
// so *0xd6/0x100 is equivalent to
// ((x << 1) + (x << 2) + (x << 4) + (x << 6) + (x << 7)) >> 8
// which is also equivalent to
// (x >> 7) + (x >> 6) + (x >> 4) + (x >> 2) + (x >> 1)
- ((y0 >> 7) + (y0 >> 6) + (y0 >> 4) + (y0 >> 2) + (y0 >> 1)) // - y0 * 0xd6 / 0x100
// we want "+ y1 * 0x1d3 / 0x100"
// 0x1d3 == 0b111010011
// so this is equivalent to
// ((x << 0) + (x << 1) + (x << 4) + (x << 6) + (x << 7) + (x << 8)) >> 8
// which is also equivalent to
// (x >> 8) + (x >> 7) + (x >> 4) + (x >> 2) + (x >> 1) + (x >> 0)
+ ((y1 >> 8) + (y1 >> 7) + (y1 >> 4) + (y1 >> 2) + (y1 >> 1) + y1);
end
end
// output: reduce to 8bit
assign out = y1[16:9];
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
cpu_0_jtag_debug_module_tck the_cpu_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
cpu_0_jtag_debug_module_sysclk the_cpu_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic cpu_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam cpu_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// cpu_0_jtag_debug_module_phy.sld_instance_index = 0,
// cpu_0_jtag_debug_module_phy.sld_ir_width = 2,
// cpu_0_jtag_debug_module_phy.sld_mfg_id = 70,
// cpu_0_jtag_debug_module_phy.sld_sim_action = "",
// cpu_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// cpu_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// cpu_0_jtag_debug_module_phy.sld_type_id = 34,
// cpu_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; long long ma = -1e15, need = 0; for (int i = 0; i < n; i++) { long long a; cin >> a; ma = max(a, ma); need = max(need, ma - a); } long long ans = 0; while ((1ll << ans) - 1 < need) ans++; cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int ok[101010]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> ct(n); int tl = 0; int nn = 0; int odd = 0; for (int i = 0; i < n; i++) { cin >> ct[i]; tl += ct[i]; if (ct[i] % 2 == 1) odd++; if (ct[i] > 0) { nn++; for (int j = 1; j <= ct[i]; j++) { if (ct[i] % j == 0) { ok[j]++; } } } } if (nn < 2) { cout << tl << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < ct[i]; j++) { cout << (char)( a + i); } } cout << endl; } else if (odd > 1) { cout << 0 << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < ct[i]; j++) { cout << (char)( a + i); } } cout << endl; } else { int bv = 1; for (int i = 1; i <= tl; i++) { if (ok[i] == nn) { int x = i; int o = 0; for (int ii = 0; ii < n; ii++) { ct[ii] /= x; if (ct[ii] % 2 == 1) o++; } if (o < 2 || (i % 2 == 0)) { bv = max(bv, i); } for (int ii = 0; ii < n; ii++) { ct[ii] *= x; } } } cout << bv << endl; tl /= bv; string r(tl, ); int of = 0; for (int ii = 0; ii < n; ii++) { ct[ii] /= bv; if (ct[ii] % 2 == 1) of = 1; } if (bv % 2 == 0) { int i2 = 0; for (int i = 0; i < (int)ct.size(); i++) { for (int j = 0; j < ct[i]; j++) { r[i2++] = (char)( a + i); } } } else { int i2 = 0; if (of) { for (int i = 0; i < (int)ct.size(); i++) { if (ct[i] % 2 == 1) { for (int j = 0; j < ct[i]; j += 2) { r[tl / 2 - i2] = (char)( a + i); r[tl / 2 + i2] = (char)( a + i); i2++; } } } for (int i = 0; i < (int)ct.size(); i++) { if (ct[i] % 2 == 0) { for (int j = 0; j < ct[i]; j += 2) { r[tl / 2 - i2] = (char)( a + i); r[tl / 2 + i2] = (char)( a + i); i2++; } } } } else { for (int i = 0; i < (int)ct.size(); i++) { if (ct[i] % 2 == 0) { for (int j = 0; j < ct[i]; j += 2) { r[tl / 2 - i2 - 1] = (char)( a + i); r[tl / 2 + i2] = (char)( a + i); i2++; } } } } } string v = ; for (int i = 0; i < bv; i++) { v = v + r; reverse(r.begin(), r.end()); } cout << v << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<long long> g[200000]; long long c[200000]; long long cnt; void dfs(long long v, long long p = -1) { cnt++; long long cnt1 = cnt; for (long long to : g[v]) { if (to != p) { dfs(to, v); } } c[v] = cnt - cnt1 + 1; } signed main() { long long t; cin >> t; for (long long q = 0; q < t; q++) { long long k; cin >> k; k *= 2; vector<pair<long long, long long>> edge; long long t[k]; for (long long i = 0; i < k - 1; i++) { long long a, b; cin >> a >> b >> t[i]; a--; b--; g[a].push_back(b); g[b].push_back(a); edge.push_back({a, b}); } dfs(0); long long mnsum = 0, mxsum = 0; for (long long i = 0; i < k - 1; i++) { long long c1 = min(c[edge[i].first], c[edge[i].second]); mnsum += c1 % 2 * t[i]; mxsum += min(c1, k - c1) * t[i]; } cout << mnsum << << mxsum << n ; for (long long i = 0; i < k; i++) { g[i].clear(); } } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) void read(int &a) { a = 0; char c = getchar(); while (c < 0 || c > 9 ) { c = getchar(); } while (c >= 0 && c <= 9 ) { a = (a << 1) + (a << 3) + (c ^ 48); c = getchar(); } } const int Maxn = 50000; const int Inf = 0x3f3f3f3f; int n, q; int a[Maxn + 5]; int fa[Maxn + 5]; int head[Maxn + 5], arrive[Maxn + 5], nxt[Maxn + 5], tot; void add_edge(int from, int to) { arrive[++tot] = to; nxt[tot] = head[from]; head[from] = tot; } int dep[Maxn + 5], dis[Maxn + 5]; int dfn[Maxn + 5], right[Maxn + 5], rnk[Maxn + 5], dfn_tot, sz[Maxn + 5]; int sum[Maxn + 5]; long long f[Maxn + 5]; void init_dfs(int u) { dep[u] = dep[fa[u]] + 1; if (a[u] != 1) { dfn[u] = ++dfn_tot; dis[dfn_tot] = dep[u]; rnk[dfn_tot] = u; sz[u] = 1; sum[u] = 0; } else { dfn[u] = dfn_tot + 1; sz[u] = 0; sum[u] = 1; } for (int i = head[u]; i; i = nxt[i]) { int v = arrive[i]; init_dfs(v); sz[u] += sz[v]; sum[u] += sum[v]; f[u] += f[v]; f[u] += sum[v]; } right[u] = dfn[u] + sz[u] - 1; } int del[Maxn + 5]; int main() { read(n), read(q); for (register int i = 1; i <= n; ++i) { read(a[i]); del[i] = -Inf; } for (register int i = 2; i <= n; ++i) { read(fa[i]); add_edge(fa[i], i); } init_dfs(1); for (register int i = 1; i <= q; ++i) { int u; read(u); long long ans_1 = 0; int ans_2 = 0; for (register int j = dfn[u]; j <= right[u]; ++j) { int tmp = (i >= del[j]); ans_1 += dis[j] * tmp; ans_2 += tmp; del[j] = (tmp ? i + a[rnk[j]] : del[j]); } ans_1 -= 1ll * ans_2 * dep[u]; ans_1 += f[u], ans_2 += sum[u]; printf( %lld %d n , ans_1, ans_2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> x; vector<vector<int> > adjList; vector<bool> visited; long long int ans = 0; long long int add(long long int a, long long int b) { return (a + b) % 1000000007; } long long int mul(long long int a, long long int b) { return (a * b) % 1000000007; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } void dfs(int node, unordered_map<long long int, long long int> mp) { long long int gc; unordered_map<long long int, long long int> mp2; for (auto elem : mp) { gc = gcd(elem.first, x[node]); ans = add(ans, mul(gc, elem.second)); mp2[gc] += elem.second; } ans = add(x[node], ans); mp2[x[node]] += 1LL; for (auto elem : adjList[node]) { if (!visited[elem]) { visited[elem] = true; dfs(elem, mp2); } } } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; x.resize(n + 1, 0); visited.resize(n + 1, false); adjList.resize(n + 1); for (register int i = 1; i <= n; i++) cin >> x[i]; int a, b; for (int i = 1; i < n; i++) { cin >> a >> b; adjList[a].push_back(b); adjList[b].push_back(a); } unordered_map<long long int, long long int> mp; visited[1] = true; dfs(1, mp); cout << ans << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const long long inf = 1e9; const int MAXM = 1048800; const int MAXN = 1e7 + 1; bool visit[MAXM]; int a[MAXM]; int k; vector<int> v; int main() { int n, i, j, k; cin >> n; n *= 2; for (int i = 0; i < n; i++) { cin >> a[i]; } int ans = INT_MAX, cnt = 0; sort(a, a + n); for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { v.clear(); cnt = 0; for (int k = 0; k < n; k++) { if (k == i or k == j) continue; v.push_back(a[k]); } int nn = v.size(); for (int k = 0; k < nn; k += 2) { cnt += v[k + 1] - v[k]; } ans = min(ans, cnt); } } cout << ans << endl; return 0; }
|
module sf_camera_clk_gen (
input clk,
input rst,
output locked,
output phy_out_clk
);
//Local parameters
//Registers/Wires
wire clkfbout_buf;
wire clkfb;
wire clkout;
wire phy_bufout;
//Submodules
DCM_SP #(
.CLKDV_DIVIDE (2.500),
.CLKFX_DIVIDE (5),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
//.DESKEW_ASJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm (
//Input Clocks
.CLKIN (clk), //Already went through a global clock buffer
.CLKFB (clkfbout_buf),
//Output Clocks
.CLK0 (clkfb),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkout),
.CLKFX180 (),
.CLKDV (),
//Ports for dynamic phase shifting
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
//Status
.LOCKED (locked),
.STATUS (),
.RST (rst),
.DSSEN (1'b0)
);
BUFG bufg_camera_clk (
.I(clkout),
.O(phy_bufout)
);
BUFG pll_fb (
.I (clkfb),
.O (clkfbout_buf)
);
ODDR2 #(
.DDR_ALIGNMENT ("NONE"), //Sets output alignment to NON
.INIT (1'b0), //Sets the inital state to 0
.SRTYPE ("SYNC") //Specified "SYNC" or "ASYNC" reset
) pad_buf (
.Q (phy_out_clk),
.C0 (phy_bufout),
.C1 (~phy_bufout),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0)
);
//Asynchronous Logic
//Synchronous Logic
endmodule
|
module division_factor(div, mul, shift);
input [7:0] div;
output [15:0] mul;
output [8:0] shift;
reg [15:0] mul;
reg [8:0] shift;
always @(div)
begin
case(div)
8'd1: begin mul = 16'd1; shift = 8'd0; end
8'd2: begin mul = 16'd1; shift = 8'd1; end
8'd3: begin mul = 16'd21845; shift = 8'd16; end
8'd4: begin mul = 16'd1; shift = 8'd2; end
8'd5: begin mul = 16'd13107; shift = 8'd16; end
8'd6: begin mul = 16'd10923; shift = 8'd16; end
8'd7: begin mul = 16'd9362; shift = 8'd16; end
8'd8: begin mul = 16'd1; shift = 8'd3; end
8'd9: begin mul = 16'd7282; shift = 8'd16; end
8'd10:begin mul = 16'd6554; shift = 8'd16; end
8'd11:begin mul = 16'd5958; shift = 8'd16; end
8'd12:begin mul = 16'd5461; shift = 8'd16; end
8'd13:begin mul = 16'd5041; shift = 8'd16; end
8'd14:begin mul = 16'd4681; shift = 8'd16; end
8'd15:begin mul = 16'd4369; shift = 8'd16; end
8'd16:begin mul = 16'd1; shift = 8'd4; end
8'd17:begin mul = 16'd3855; shift = 8'd16; end
8'd18:begin mul = 16'd3641; shift = 8'd16; end
8'd19:begin mul = 16'd3449; shift = 8'd16; end
8'd20:begin mul = 16'd3277; shift = 8'd16; end
8'd21:begin mul = 16'd3121; shift = 8'd16; end
8'd22:begin mul = 16'd2979; shift = 8'd16; end
8'd23:begin mul = 16'd2849; shift = 8'd16; end
8'd24:begin mul = 16'd2731; shift = 8'd16; end
8'd25:begin mul = 16'd2621; shift = 8'd16; end
8'd26:begin mul = 16'd2521; shift = 8'd16; end
8'd27:begin mul = 16'd2427; shift = 8'd16; end
8'd28:begin mul = 16'd2341; shift = 8'd16; end
8'd29:begin mul = 16'd2260; shift = 8'd16; end
8'd30:begin mul = 16'd2185; shift = 8'd16; end
default: begin mul = 16'd1; shift = 8'd0; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void umax(T &a, T b) { if (a < b) a = b; } template <class T> inline void umin(T &a, T b) { if (a > b) a = b; } template <class T> inline T abs(T a) { return a > 0 ? a : -a; } template <class T> inline T gcd(T a, T b) { return __gcd(a, b); } template <class T> inline T lcm(T a, T b) { return a / gcd(a, b) * b; } const int inf = 1e9 + 143; const long long longinf = 1e18 + 143; inline int read() { int x; scanf( %d , &x); return x; } const int N = 1e6 + 100; int p[N], sz[N]; int get(int x) { if (x == p[x]) return x; return p[x] = get(p[x]); } int main() { int n = read(); int m = read(); int mod = read(); for (int i = 1; i <= n; i++) p[i] = i; for (int i = 1; i <= m; i++) { int a = read(); int b = read(); a = get(a); b = get(b); if (a != b) { p[a] = b; } } vector<int> trees; for (int i = 1; i <= n; i++) { sz[get(i)] += 1; } for (int i = 1; i <= n; i++) { if (i == get(i)) { trees.push_back(sz[i]); } } if (trees.size() == 1) { printf( %d n , 1 % mod); return 0; } int res = 1; for (int i = 1; i <= (int)trees.size() - 2; i++) res = (long long)res * n % mod; for (int i = 0; i < trees.size(); i++) res = (long long)res * trees[i] % mod; printf( %d n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; long long int max(long long int a, long long int b) { if (a > b) return a; else return b; } long long int min(long long int a, long long int b) { if (a < b) return a; else return b; } long long int binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } long long binpow(long long a, long long b) { if (b == 0) return 1; long long res = binpow(a, b / 2); if (b % 2) return res * res * a; else return res * res; } vector<vector<pair<int, int>>> adj; vector<int> dp; vector<int> ans; int dfs(int x, int p) { for (auto c : adj[x]) { if (c.first == p) continue; int val = dfs(c.first, x); if (val == 0 && c.second == 2) { dp[x] += val + 1; ans.push_back(c.first); } else { dp[x] += val; } } return dp[x]; } void solve() { int n; cin >> n; adj.resize(n + 1); for (int i = 0; i < n - 1; i++) { int x, y, t; cin >> x >> y >> t; adj[x].push_back({y, t}); adj[y].push_back({x, t}); } dp.resize(n + 1); dfs(1, 0); cout << dp[1] << endl; for (auto c : ans) { cout << c << ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const double EPS = 1e-9; const double PI = acos(-1.); const long long LL_INF = 1e17 + 16; const int INF = 1e9 + 10; const long long MOD = 1e9 + 7; const int MAXN = 20; set<long long> goods; long long f[MAXN]; void gen() { for (int i = (1); i <= (int)(10); i++) { for (int j = (0); j < (int)(1 << i); j++) { long long v = 0; long long st10 = 1; for (int k = (0); k < (int)(i); k++) { if (j & (1 << k)) { v += 7 * st10; } else { v += 4 * st10; } st10 *= 10; } goods.insert(v); } } } int per[MAXN]; int used[MAXN]; void solve() { gen(); long long n, k; cin >> n >> k; f[0] = 1; int m; for (m = 1;; m++) { f[m] = f[m - 1] * m; if (f[m] >= k) { break; } } if (m > n) { printf( -1 n ); return; } int ans = 0; int offset = n - m; for (__typeof((goods).begin()) it = (goods).begin(); it != (goods).end(); it++) { if ((*it) <= offset) { ans++; } } k--; int top = 1; for (int i = m; i >= 1; i--) { int v = k / f[i - 1] + 1; int cnt = 0; for (int j = (1); j <= (int)(m); j++) { if (!used[j]) { cnt++; if (cnt == v) { per[top++] = j; used[j] = 1; break; } } } k %= f[i - 1]; } for (int i = (1); i <= (int)(m); i++) { if (goods.count(i + offset) && goods.count(per[i] + offset)) { ans++; } } cout << ans << endl; } int main() { int t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, w, a[105], cnt1 = 0, cnt = 0, b[105], c[105], e[105], colour[105]; memset(colour, 0, sizeof colour); scanf( %d%d , &n, &w); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); c[i] = a[i]; cnt1 = a[i] / 2; if (a[i] % 2 == 1) cnt1++; b[i] = cnt1; cnt += cnt1; } if (cnt > w) { printf( -1 n ); return 0; } if (w > cnt) { int dif = w - cnt; sort(c + 1, c + n + 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (c[i] == a[j] && colour[j] == 0) { e[i] = j; colour[j] = 1; break; } } } int d = n; while (d > 0) { if (c[d] % 2 == 1) { int k = c[d] / 2 + 1; int diff = c[d] - k; if (dif > diff) { dif -= diff; b[e[d]] += diff; } else b[e[d]] += dif, dif = 0; } else { int k = c[d] / 2; int diff = c[d] - k; if (dif > diff) { dif -= diff; b[e[d]] += diff; } else b[e[d]] += dif, dif = 0; } if (dif == 0) break; d--; } if (dif > 0) { printf( -1 n ); return 0; } for (int i = 1; i <= n; i++) printf( %d , b[i]); } else if (cnt == w) { for (int i = 1; i <= n; i++) printf( %d , b[i]); } }
|
module SigmaDelta2ndOrder_tb ();
parameter WIDTH = 16; ///< Input width
parameter GAIN = 7.0/6.0; ///< Gain parameter
parameter GROWTH = 1; ///< Growth bits on accumulators
parameter CLAMP = 1; ///< Clamp accumulators
parameter FREQ_RATE = ;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] in;
wire sdOut;
wire signed [15:0] dataOut;
integer i;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
in = 'd0;
#2 rst = 1'b0;
#20000 in = 2**(WIDTH-1)-1;
#20000 in = -2**(WIDTH-1)+1;
#20000 in = 'd0;
#20000 in = 'd0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) in = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) in = $random();
end
$stop();
end
always #1 clk = ~clk;
SigmaDelta2ndOrder #(
.WIDTH (WIDTH ), ///< Input width
.GAIN (GAIN ), ///< Gain parameter
.GROWTH(GROWTH), ///< Growth bits on accumulators
.CLAMP (CLAMP ) ///< Clamp accumulators
)
uut (
.clk(clk),
.rst(rst),
.en(en),
.in(in), ///< [WIDTH-1:0]
.sdOut(sdOut)
);
Sinc3Filter #(
.OSR(32) // Output width is 3*ceil(log2(OSR))+1
)
testFilter (
.clk(clk),
.en(en), ///< Enable (use to clock at slower rate)
.in(sdOut),
.out(dataOut) ///< [3*$clog2(OSR):0]
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_SYMBOL_V
`define SKY130_FD_SC_HD__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 100000; vector<int> g[NMAX + 1]; int H[NMAX + 1], D[NMAX + 1], G[NMAX + 1], GS[NMAX + 1]; long long DS[NMAX + 1]; vector<int> data[NMAX + 1]; vector<long long> acc[NMAX + 1], psum[NMAX + 1]; int dfs1(int u, int p, int gp) { G[u] = gp; GS[gp]++; for (int v : g[u]) if (v != p) H[u] = max(dfs1(v, u, gp) + 1, H[u]); return H[u]; } void dfs2(int u, int p, int pLen = 0) { int m1 = -2, mi1 = -1, m2 = -2, mi2 = -1; for (int v : g[u]) if (v != p) { if (m2 < H[v]) m2 = H[v], mi2 = v; if (m1 < m2) swap(m1, m2), swap(mi1, mi2); } D[u] = max(pLen, m1 + 1); for (int v : g[u]) if (v != p) { if (v == mi1) dfs2(v, u, max(pLen + 1, m2 + 2)); else dfs2(v, u, max(pLen + 1, m1 + 2)); } while (data[G[u]].size() <= D[u]) data[G[u]].push_back(0); data[G[u]][D[u]]++; DS[G[u]] += D[u]; } map<pair<int, int>, double> cache; void query(int u, int v) { u = G[u], v = G[v]; if (u == v) { printf( -1 n ); return; } if (data[u].size() > data[v].size()) swap(u, v); pair<int, int> P(u, v); if (cache.count(P)) { printf( %.10f n , cache[P]); return; } long long S = 1LL * GS[u] * GS[v] + 1LL * GS[u] * DS[v] + 1LL * DS[u] * GS[v]; int bound = data[v].size() - 1; for (int i = 0; i < data[u].size(); i++) { int R = bound - i - 1; if (0 <= R) { R = min(R, (int)data[v].size() - 1); long long terms = data[u][i] * acc[v][R]; S -= i * terms + psum[v][R] * data[u][i] + terms; S += bound * terms; } } printf( %.10f n , (double)S / GS[u] / GS[v]); } void process() { int N, M, Q; scanf( %d%d%d , &N, &M, &Q); for (int i = 0; i < M; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } int gps = 0; for (int i = 1; i <= N; i++) if (!G[i]) { gps++; dfs1(i, -1, gps); } for (int i = 1; i <= N; i++) if (data[G[i]].empty()) { dfs2(i, -1); } for (int i = 1; i <= gps; i++) { acc[i] = psum[i] = vector<long long>(data[i].size()); acc[i][0] = data[i][0]; for (int j = 1; j < acc[i].size(); j++) acc[i][j] = acc[i][j - 1] + data[i][j]; for (int j = 1; j < psum[i].size(); j++) psum[i][j] = psum[i][j - 1] + 1LL * data[i][j] * j; } for (int i = 0; i < Q; i++) { int u, v; scanf( %d%d , &u, &v); query(u, v); } } int main() { process(); }
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const int N = 1205; const int INF = 0x3f3f3f3f; template <class T> bool read(T& x) { char c; while (!isdigit(c = getchar()) && c != - && c != EOF) ; if (c == EOF) return false; T flag = 1; if (c == - ) { flag = -1; x = 0; } else x = c - 0 ; while (isdigit(c = getchar())) x = x * 10 + c - 0 ; x *= flag; return true; } template <class T, class... R> bool read(T& a, R&... b) { if (!read(a)) return false; return read(b...); } mt19937 gen(steady_clock::now().time_since_epoch().count()); struct edge { int to, cap, next; } e[N * 4]; int head[N], cnt, depth[N], group[N]; void add(int u, int v, int c) { e[cnt] = {v, c, head[u]}; head[u] = cnt++; } void add_edge(int u, int v, int c) { add(u, v, c); add(v, u, 0); } bool isap_bfs(int s, int t) { memset(depth, -1, sizeof(depth)); memset(group, 0, sizeof(group)); group[depth[t] = 0]++; queue<int> q; q.push(t); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = head[u]; ~i; i = e[i].next) { int v = e[i].to; if (~depth[v]) continue; group[depth[v] = depth[u] + 1]++; q.push(v); } } return ~depth[s]; } int isap_dfs(int u, int t, int c) { if (u == t) return c; int tmp = c; for (int i = head[u]; tmp && ~i; i = e[i].next) { int v = e[i].to; if (depth[v] + 1 == depth[u] && e[i].cap) { int d = isap_dfs(v, t, min(tmp, e[i].cap)); e[i].cap -= d; e[i ^ 1].cap += d; tmp -= d; } } if (tmp) { if (!--group[depth[u]]) depth[t] = -1; group[++depth[u]]++; } return c - tmp; } int isap(int s, int t) { if (!isap_bfs(s, t)) return 0; int max_flow = 0; while (~depth[t]) max_flow += isap_dfs(s, t, INF); return max_flow; } int deg[N], x[N], y[N], xe[N], ye[N]; vector<int> edg[N]; int main() { time_point<steady_clock> start = steady_clock::now(); int T, n, m, k; read(T); while (T--) { read(n, m, k); int s = 0, t = n + m + 1; cnt = 0; for (int i = s; i <= t; i++) { head[i] = -1; deg[i] = 0; edg[i].clear(); } for (int i = 1; i <= m; i++) { read(x[i], y[i]); deg[x[i]]++; deg[y[i]]++; edg[x[i]].push_back(i); edg[y[i]].push_back(i); } for (int i = 1; i <= n; i++) { if (deg[i] > 2 * k) { k = -1; break; } } if (k == -1) { for (int i = 1; i <= m; i++) printf( 0 ); puts( ); continue; } int tot = 0; for (int i = 1; i <= n; i++) { if (deg[i] > k) { tot += deg[i] - k; add_edge(m + i, t, 2 * (deg[i] - k)); } } tot *= 2; for (int i = 1; i <= m; i++) { add_edge(s, i, 1); add_edge(i, m + x[i], 1); xe[i] = cnt - 1; add_edge(i, m + y[i], 1); ye[i] = cnt - 1; } if (isap(s, t) == tot) { for (int i = 1; i <= m; i++) deg[i] = 0; k = 1; for (int i = 1; i <= n; i++) { int c = 0; for (auto j : edg[i]) { if (x[j] == i && e[xe[j]].cap || y[j] == i && e[ye[j]].cap) { if (c == 0) deg[j] = k; else deg[j] = k++; c ^= 1; } } } for (int i = 1; i <= m; i++) if (!deg[i]) deg[i] = k++; for (int i = 1; i <= m; i++) printf( %d , deg[i]); puts( ); } else { for (int i = 1; i <= m; i++) printf( 0 ); puts( ); } } cerr << endl << ------------------------------ << endl << Time: << duration<double, milli>(steady_clock::now() - start).count() << ms. << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool f[300010]; map<pair<int, int>, int> mp; vector<int> g[300010]; long long nm[300010], kk[300010], x, y, p; long long ans, n, i; void go(int now) { f[now] = 1; for (int i = 0; i < g[now].size(); i++) if (!f[g[now][i]]) if (nm[now] + nm[g[now][i]] - mp[make_pair(now, g[now][i])] < p && p <= nm[now] + nm[g[now][i]]) ans -= 2; for (int i = 0; i < g[now].size(); i++) if (!f[g[now][i]]) go(g[now][i]); } int main() { cin >> n >> p; for (i = 1; i <= n; i++) { scanf( %d%d , &x, &y); mp[make_pair(x, y)]++; mp[make_pair(y, x)]++; if (mp[make_pair(x, y)] == 1) { g[x].push_back(y); g[y].push_back(x); } nm[x]++; nm[y]++; } for (i = 1; i <= n; i++) if (2 * nm[i] >= p) ans--; for (i = 1; i <= n; i++) kk[nm[i]]++; for (i = 300000; i >= 0; i--) kk[i] += kk[i + 1]; for (i = 1; i <= n; i++) ans += kk[max(0LL, p - nm[i])]; for (i = 1; i <= n; i++) if (!f[i]) go(i); cout << ans / 2 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_2_V
`define SKY130_FD_SC_MS__AND4_2_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/03/17 18:08:10
// Design Name:
// Module Name: filter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//symmetric filter
module filter
(
input clk,
input resetn,
input [71:0] din,
input [53:0] kernel,
input din_valid,
output [15:0] dout,
output dout_valid
);
parameter latency = 9;// layer 1: 3, layer 2: 3, layer 3~5: 3, 3+3+3 = 9
wire [8:0] din_array [8:0];
wire [5:0] kernel_array [8:0];
wire plus_or_minus [2:0]; // 0 for plus, 1 for minus.
genvar i;
generate
for(i = 0; i < 9; i = i + 1) begin
assign din_array[i] = {1'b0, din[i*8 +: 8]}; // for signed num 0~255
assign kernel_array[i] = kernel[i*6 +: 6]; // -32~31
end
for(i = 0; i < 3; i = i + 1) begin
assign plus_or_minus[i] = (kernel_array[i*3] == kernel_array[i*3+2]) ? 1'b0 : 1'b1;
end
endgenerate
reg [latency-1:0] layer_valid;
wire [14:0] layer_1_2 [2:0];//(a+b)*c
reg [8:0] layer_1_2_buf [3*3-1:0];// din_array 1 4 7 buffer (din1 -> 0->1->2) (din3 -> 3->4->5) (din5 -> 6->7->8) latency of layer 1 is 3
wire [15:0] layer_2_3 [2:0];// a*b+c result, latency of layer 3 is 3
reg [15:0] layer_3_4 [1:0];
reg [15:0] layer_4_5;
reg [15:0] layer_5_end;
assign dout = layer_5_end;
assign dout_valid = layer_valid[latency-1];
generate
for(i = 0; i < 3; i = i + 1)
begin:layer1 // (0 +/- 2)*kernel (3 +/- 5)*kernel (6 +/- 8)*kernel
xbip_dsp48_macro_preadder_l3 pre_adder (// (A+D)*B latency 3
.CLK(clk), // input CLK
.A(din_array[i*3]), // input [8 : 0] A
.B(kernel_array[i*3]), // input [5 : 0] B
.D(plus_or_minus[i] == 1'b0 ? din_array[i*3+2] : -din_array[i*3+2]), // input [8 : 0] D
.P(layer_1_2[i]) // output [14 : 0] P
);
end
for(i = 0; i < 3; i = i + 1)
begin:layer2// (1, 4, 7)*kernel + pre-result
xbip_dsp48_macro_macc_l3 macc_ABC (//A*B+C, latency 3
.CLK(clk), // input CLK
.A(layer_1_2_buf[i*3+2]), // input [8 : 0] A
.B(kernel_array[i*3+1]), // input [5 : 0] B
.C(layer_1_2[i]), // input [14 : 0] C
.P(layer_2_3[i]) // output [15 : 0] P
);
end
endgenerate
integer j;
always@(posedge clk) begin
if( resetn == 1'b0 ) begin
layer_valid <= 0;
for(j = 0; j < 9; j = j + 1)begin
layer_1_2_buf[j] <= 9'b0;
end
for(j = 0; j < 2; j = j + 1)begin
layer_3_4[j] <= 16'b0;
end
layer_4_5 <= 16'b0;
layer_5_end <= 16'b0;
end
else begin
//layer 1 buffer for 1 4 7
for(j = 0; j < 3; j = j + 1) begin
layer_1_2_buf[j*3] <= din_array[j*3+1];
layer_1_2_buf[j*3+1] <= layer_1_2_buf[j*3];
layer_1_2_buf[j*3+2] <= layer_1_2_buf[j*3+1];
end
//adder tree
//layer 3
layer_3_4[0] <= layer_2_3[0] + layer_2_3[1];
layer_3_4[1] <= layer_2_3[2];
//layer 4
layer_4_5 <= layer_3_4[0] + layer_3_4[1];
//layer 5
layer_5_end <= layer_4_5;
//layer_valid <= {layer_valid, din_valid};
layer_valid <= {layer_valid, din_valid};
/*layer_valid[0] <= din_valid;
for(j = 1; j < latency; j = j + 1)begin
layer_valid[j] <= layer_valid[j-1];
end*/
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Info { int h, l, r; vector<int> A; Info(vector<int> _A, int _h, int _l, int _r) : A(_A), h(_h), l(_l), r(_r) {} }; int FindMaxGoodSleep(int idx, int time, vector<vector<int>>& memo, const Info& input) { if (idx >= input.A.size()) { return 0; } if (memo[idx][time] != -1) { return memo[idx][time]; } int new_time = (time + input.A[idx]) % input.h; int a = (new_time >= input.l && new_time <= input.r ? 1 : 0) + FindMaxGoodSleep(idx + 1, new_time, memo, input); new_time = (time + input.A[idx] - 1) % input.h; int b = (new_time >= input.l && new_time <= input.r ? 1 : 0) + FindMaxGoodSleep(idx + 1, new_time, memo, input); memo[idx][time] = max(a, b); return memo[idx][time]; } int main(void) { int n, h, l, r; cin >> n >> h >> l >> r; vector<int> A(n); for (int i = 0; i < n; i++) { cin >> A[i]; } Info info(A, h, l, r); vector<vector<int>> memo(n + 5, vector<int>(2005, -1)); cout << FindMaxGoodSleep(0, 0, memo, info) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__O22AI_PP_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1001001001; const long long INFLL = 1001001001001001001LL; template <typename T> void pv(T a, T b) { for (T i = a; i != b; ++i) cout << *i << ; cout << endl; } template <typename T> void chmin(T& a, T b) { if (a > b) a = b; } template <typename T> void chmax(T& a, T b) { if (a < b) a = b; } int in() { int x; scanf( %d , &x); return x; } double fin() { double x; scanf( %lf , &x); return x; } long long lin() { long long x; scanf( %lld , &x); return x; } int N, K, P, A[500005], S[500005], nxt[500005][101]; vector<int> pos[101]; int dp[101][10001]; int main() { N = in(); K = in(); P = in(); int s = 0; for (int i = 0; i < N; ++i) { A[i] = in() % P; S[i] = ((s += A[i]) %= P); pos[s].push_back(i); } vector<int> nx(P, INF); for (int i = 0; i < P; ++i) { pos[i].push_back(INF); nx[i] = pos[i][0]; } s = 0; for (int i = 0; i < N; ++i) { for (int j = 0; j < P; ++j) { nxt[i][(j - s + P) % P] = nx[j]; } (s += A[i]) %= P; nx[s] = *upper_bound(pos[s].begin(), pos[s].end(), i); } for (int i = 0; i <= 100; ++i) { fill(dp[i], dp[i] + 10001, INF); } dp[0][0] = 0; for (int k = 0; k + 1 < K; ++k) { for (int x = 0; x < K * P; ++x) { if (dp[k][x] >= N) continue; const int f = dp[k][x]; for (int p = 0; p < P; ++p) { if (nxt[f][p] == INF) continue; chmin(dp[k + 1][x + p], nxt[f][p] + 1); } } } int res = INF; for (int x = 0; x < K * P; ++x) { if (dp[K - 1][x] >= N) continue; int v = dp[K - 1][x]; int t = (S[N - 1] - S[v - 1] + P) % P; chmin(res, x + t); } printf( %d n , res); return 0; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.