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#include <bits/stdc++.h> using namespace std; long long n, m; long long arr[200002], time_freq[101]; void solve() { long long total_time = 0; for (long long i = 0; i < n; i++) { long long exam_start_time = total_time + arr[i] - m; int student_removed = 0; if (exam_start_time > 0) { for (int j = 100; j > 0; j--) { long long y = time_freq[j] * j; if (exam_start_time <= y) { student_removed += ((exam_start_time + j - 1) / j); break; } exam_start_time -= (time_freq[j] * j); student_removed += time_freq[j]; } } total_time += arr[i]; time_freq[arr[i]]++; cout << student_removed << ; } cout << endl; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> arr[i]; ; solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > bl; long long fact[200005]; long long ifact[200005]; long long invert_mod(long long a, long long p) { long long n = 1, old = 0, q = p, r, h; bool pos = false; while (a > 0) { r = q % a; q = q / a; h = q * n + old; old = n; n = h; q = a; a = r; pos = !pos; } return pos ? old : (p - old); } void calc_fact() { fact[0] = fact[1] = 1; ifact[0] = ifact[1] = 1; for (long long i = 2; i < 200005; i++) { fact[i] = (i * fact[i - 1]) % 1000000007; ifact[i] = invert_mod(fact[i], 1000000007) % 1000000007; } } int main(void) { ios_base::sync_with_stdio(false); long long h, w, n; cin >> h >> w >> n; calc_fact(); bl.resize(n); for (int i = 0; i < n; i++) { cin >> bl[i].first >> bl[i].second; } bl.push_back(make_pair(h, w)); vector<long long> dp(n + 1, 0); sort(bl.begin(), bl.end()); dp[0] = ((fact[bl[0].first + bl[0].second - 2] * ifact[bl[0].first - 1]) % 1000000007 * ifact[bl[0].second - 1]) % 1000000007; for (int i = 1; i <= n; i++) { dp[i] = ((fact[bl[i].first + bl[i].second - 2] * ifact[bl[i].first - 1]) % 1000000007 * ifact[bl[i].second - 1]) % 1000000007; long long ans = 0; for (int j = 0; j < i; j++) { long long val; if (bl[i].second >= bl[j].second && bl[i].first >= bl[j].first) val = ((fact[(bl[i].first + bl[i].second) - (bl[j].first + bl[j].second)] * ifact[bl[i].first - bl[j].first]) % 1000000007 * ifact[bl[i].second - bl[j].second]) % 1000000007; else val = 0; ans = (ans + (dp[j] * val) % 1000000007) % 1000000007; } dp[i] = (dp[i] + (1000000007 - ans)) % 1000000007; } cout << dp[n]; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int mod = 1e9 + 7; long long qpow(long long a, long long b) { long long res = 1; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } struct graph { int head[maxn], nxt[maxn << 1], to[maxn << 1], w[maxn << 1], sz; void init() { memset(head, -1, sizeof(head)); } graph() { init(); } void push(int a, int b, int c) { nxt[sz] = head[a], to[sz] = b, w[sz] = c, head[a] = sz++; } int& operator[](const int a) { return to[a]; } }; long long dist[maxn][40], fi[maxn][40], mi[maxn][40]; int to[maxn], w[maxn]; int main() { int n; long long k; cin >> n >> k; for (int i = 0; i < n; ++i) scanf( %d , &to[i]); for (int i = 0; i < n; ++i) { scanf( %d , &w[i]); dist[i][0] = w[i]; mi[i][0] = w[i]; fi[i][0] = to[i]; } for (int i = 1; i <= 39; ++i) { for (int j = 0; j < n; ++j) { dist[j][i] = dist[j][i - 1] + dist[fi[j][i - 1]][i - 1]; fi[j][i] = fi[fi[j][i - 1]][i - 1]; mi[j][i] = min(mi[j][i - 1], mi[fi[j][i - 1]][i - 1]); } } for (int i = 0; i < n; ++i) { long long mix = 1e18; long long ans = 0; long long res = k; int now = i; for (int j = 39; j >= 0; --j) { if (res >= (1ll << j)) { ans += dist[now][j]; mix = min(mix, mi[now][j]); now = fi[now][j]; res -= (1ll << j); } } printf( %lld %lld n , ans, mix); } return 0; }
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SPI Slave
*/
module axis_spi_slave #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
/*
* SPI interface
*/
input wire cs,
input wire sck,
input wire mosi,
output wire miso,
/*
* Status
*/
output wire busy
);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_TRANSFER = 2'd1,
STATE_WAIT = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [DATA_WIDTH-1:0] tx_data_reg = 0, tx_data_next;
reg [DATA_WIDTH-1:0] rx_data_reg = 0, rx_data_next;
reg [4:0] bit_cnt_reg = 0, bit_cnt_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 0, output_axis_tlast_next;
reg cs_reg = 1;
reg sck_reg = 0;
reg mosi_reg = 0;
reg miso_reg = 0, miso_next;
reg busy_reg = 0;
assign input_axis_tready = input_axis_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign miso = miso_reg;
assign busy = busy_reg;
reg sck_last_reg = 0;
wire sck_posedge = sck_reg & !sck_last_reg;
wire sck_negedge = !sck_reg & sck_last_reg;
always @* begin
state_next = 0;
tx_data_next = tx_data_reg;
rx_data_next = rx_data_reg;
bit_cnt_next = bit_cnt_reg;
input_axis_tready_next = 0;
output_axis_tdata_next = output_axis_tdata_reg;
output_axis_tvalid_next = output_axis_tvalid_reg & ~output_axis_tready;
output_axis_tlast_next = output_axis_tlast_reg;
miso_next = miso_reg;
case (state_reg)
STATE_IDLE: begin
if (cs_reg) begin
// cs deasserted
miso_next = 0;
state_next = STATE_IDLE;
end else begin
// cs asserted - start of frame
if (input_axis_tvalid) begin
// input data valid, read it in
{miso_next, tx_data_next[DATA_WIDTH-1:1]} = input_axis_tdata;
input_axis_tready_next = 1;
end else begin
// input data not valid, send filler
miso_next = 0;
tx_data_next = 0;
end
rx_data_next = 0;
bit_cnt_next = DATA_WIDTH-1;
state_next = STATE_TRANSFER;
end
end
STATE_TRANSFER: begin
if (sck_posedge) begin
// rising sck edge, read mosi
rx_data_next = {rx_data_reg[DATA_WIDTH-2:0], mosi_reg};
state_next = STATE_TRANSFER;
end else if (sck_negedge) begin
// falling sck edge, write miso
if (bit_cnt_reg > 0) begin
// not last edge, pull from buffer
{miso_next, tx_data_next[DATA_WIDTH-1:1]} = tx_data_reg;
bit_cnt_next = bit_cnt_reg - 1;
state_next = STATE_TRANSFER;
end else begin
// last falling edge, look ahead
if (input_axis_tvalid) begin
// grab next bit from buffer if available
{miso_next, tx_data_next[DATA_WIDTH-1:1]} = input_axis_tdata;
end else begin
// otherwise send filler
miso_next = 0;
tx_data_next = 0;
end
// wait for next event (don't know if end of frame yet)
state_next = STATE_WAIT;
end
end else if (cs_reg) begin
// premature end of frame
output_axis_tdata_next = 0;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_WAIT: begin
if (cs_reg) begin
// end of frame, transfer out
output_axis_tdata_next = rx_data_reg;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 1;
state_next = STATE_IDLE;
end else if (sck_posedge) begin
// continuing frame, transfer out
output_axis_tdata_next = rx_data_reg;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 0;
// read in new byte
if (input_axis_tvalid) begin
{miso_next, tx_data_next[DATA_WIDTH-1:1]} = input_axis_tdata;
input_axis_tready_next = 1;
end else begin
miso_next = 0;
tx_data_next = 0;
end
rx_data_next = mosi_reg;
bit_cnt_next = DATA_WIDTH-1;
state_next = STATE_TRANSFER;
end else begin
state_next = STATE_WAIT;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
tx_data_reg <= 0;
rx_data_reg <= 0;
bit_cnt_reg <= 0;
cs_reg <= 1;
sck_reg <= 0;
mosi_reg <= 0;
sck_last_reg <= 0;
input_axis_tready_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
miso_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
tx_data_reg <= tx_data_next;
rx_data_reg <= rx_data_next;
bit_cnt_reg <= bit_cnt_next;
cs_reg <= cs;
sck_reg <= sck;
mosi_reg <= mosi;
sck_last_reg <= sck_reg;
input_axis_tready_reg <= input_axis_tready_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tlast_reg <= output_axis_tlast_next;
miso_reg <= miso_next;
busy_reg <= state_next != STATE_IDLE;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
interface counter_if;
logic [3:0] value;
logic reset;
modport counter_mp (input reset, output value);
modport core_mp (output reset, input value);
endinterface
// Check can have inst module before top module
module counter_ansi
(
input clkm,
counter_if c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_if c1_data();
counter_if c2_data();
counter_if c3_data();
counter_if c4_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data.counter_mp),
.i_value(4'h1));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c2 (.clkm(clk),
.c_data(c2_data.counter_mp),
.i_value(4'h2));
counter_ansi_m c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif
/**/ c4 (.clkm(clk),
.c_data(c4_data),
.i_value(4'h4));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
c4_data.value = 4'h7;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
c4_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
c4_data.reset <= 0;
end
if (cyc==20) begin
$write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset,
c4_data.value, c4_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
if (c4_data.value != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi
(clkm, c_data, i_value);
input clkm;
counter_if c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module counter_ansi_m
(
input clkm,
counter_if.counter_mp c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi_m
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi_m
(clkm, c_data, i_value);
input clkm;
counter_if.counter_mp c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi_m
`endif
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 100; int n, k; long long C[maxn][maxn]; void Init() { C[0][0] = 1; for (int i = 1; i < maxn; ++i) { for (int j = 0; j <= i; ++j) { if (j == 0 || j == i) { C[i][j] = 1; } else { C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } } } } int main() { ios::sync_with_stdio(false); Init(); while (scanf( %d%d , &n, &k) != EOF) { long long ans = 0; if (k >= 1) { ans += 1; } if (k >= 2) { ans += C[n][2]; } if (k >= 3) { ans += C[n][3] * 2; } if (k >= 4) { ans += C[n][4] * 9; } printf( %I64d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_TB_V
`define SKY130_FD_SC_LS__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_TB_V
|
/*
-- ============================================================================
-- FILE NAME : bus_if.v
-- DESCRIPTION : oXC^tF[X
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "cpu.h"
`include "bus.h"
/********** W
[ **********/
module bus_if (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
M
output reg busy, // rW[M
/********** CPUC^tF[X **********/
input wire [`WordAddrBus] addr, // AhX
input wire as_, // AhXLø
input wire rw, // ÇÝ^«
input wire [`WordDataBus] wr_data, // «Ýf[^
output reg [`WordDataBus] rd_data, // ÇÝoµf[^
/********** SPMC^tF[X **********/
input wire [`WordDataBus] spm_rd_data, // ÇÝoµf[^
output wire [`WordAddrBus] spm_addr, // AhX
output reg spm_as_, // AhXXg[u
output wire spm_rw, // ÇÝ^«
output wire [`WordDataBus] spm_wr_data, // «Ýf[^
/********** oXC^tF[X **********/
input wire [`WordDataBus] bus_rd_data, // ÇÝoµf[^
input wire bus_rdy_, // fB
input wire bus_grnt_, // oXOg
output reg bus_req_, // oXNGXg
output reg [`WordAddrBus] bus_addr, // AhX
output reg bus_as_, // AhXXg[u
output reg bus_rw, // ÇÝ^«
output reg [`WordDataBus] bus_wr_data // «Ýf[^
);
/********** àM **********/
reg [`BusIfStateBus] state; // oXC^tF[XÌóÔ
reg [`WordDataBus] rd_buf; // ÇÝoµobt@
wire [`BusSlaveIndexBus] s_index; // oXX[uCfbNX
/********** oXX[uÌCfbNX **********/
assign s_index = addr[`BusSlaveIndexLoc];
/********** oÍÌATC **********/
assign spm_addr = addr;
assign spm_rw = rw;
assign spm_wr_data = wr_data;
/********** ANZX̧ä **********/
always @(*) begin
/* ftHgl */
rd_data = `WORD_DATA_W'h0;
spm_as_ = `DISABLE_;
busy = `DISABLE;
/* oXC^tF[XÌóÔ */
case (state)
`BUS_IF_STATE_IDLE : begin // ACh
/* ANZX */
if ((flush == `DISABLE) && (as_ == `ENABLE_)) begin
/* ANZXæÌIð */
if (s_index == `BUS_SLAVE_1) begin // SPMÖANZX
if (stall == `DISABLE) begin // Xg[¶Ì`FbN
spm_as_ = `ENABLE_;
if (rw == `READ) begin // ÇÝoµANZX
rd_data = spm_rd_data;
end
end
end else begin // oXÖANZX
busy = `ENABLE;
end
end
end
`BUS_IF_STATE_REQ : begin // oXNGXg
busy = `ENABLE;
end
`BUS_IF_STATE_ACCESS : begin // oXANZX
/* fBÒ¿ */
if (bus_rdy_ == `ENABLE_) begin // fB
if (rw == `READ) begin // ÇÝoµANZX
rd_data = bus_rd_data;
end
end else begin // fB¢
busy = `ENABLE;
end
end
`BUS_IF_STATE_STALL : begin // Xg[
if (rw == `READ) begin // ÇÝoµANZX
rd_data = rd_buf;
end
end
endcase
end
/********** oXC^tF[XÌóÔ§ä **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
state <= #1 `BUS_IF_STATE_IDLE;
bus_req_ <= #1 `DISABLE_;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_as_ <= #1 `DISABLE_;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
rd_buf <= #1 `WORD_DATA_W'h0;
end else begin
/* oXC^tF[XÌóÔ */
case (state)
`BUS_IF_STATE_IDLE : begin // ACh
/* ANZX */
if ((flush == `DISABLE) && (as_ == `ENABLE_)) begin
/* ANZXæÌIð */
if (s_index != `BUS_SLAVE_1) begin // oXÖANZX
state <= #1 `BUS_IF_STATE_REQ;
bus_req_ <= #1 `ENABLE_;
bus_addr <= #1 addr;
bus_rw <= #1 rw;
bus_wr_data <= #1 wr_data;
end
end
end
`BUS_IF_STATE_REQ : begin // oXNGXg
/* oXOgÒ¿ */
if (bus_grnt_ == `ENABLE_) begin // oX l¾
state <= #1 `BUS_IF_STATE_ACCESS;
bus_as_ <= #1 `ENABLE_;
end
end
`BUS_IF_STATE_ACCESS : begin // oXANZX
/* AhXXg[uÌlQ[g */
bus_as_ <= #1 `DISABLE_;
/* fBÒ¿ */
if (bus_rdy_ == `ENABLE_) begin // fB
bus_req_ <= #1 `DISABLE_;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
/* ÇÝoµf[^ÌÛ¶ */
if (bus_rw == `READ) begin // ÇÝoµANZX
rd_buf <= #1 bus_rd_data;
end
/* Xg[¶Ì`FbN */
if (stall == `ENABLE) begin // Xg[¶
state <= #1 `BUS_IF_STATE_STALL;
end else begin // Xg[¢¶
state <= #1 `BUS_IF_STATE_IDLE;
end
end
end
`BUS_IF_STATE_STALL : begin // Xg[
/* Xg[¶Ì`FbN */
if (stall == `DISABLE) begin // Xg[ð
state <= #1 `BUS_IF_STATE_IDLE;
end
end
endcase
end
end
endmodule
|
// ZX-Evo SD Load (c) NedoPC 2008,2009,2010,2011,2012,2013,2014,2015,2016,2019
//
// top-level
/*
This file is part of ZX-Evo SD Load firmware.
ZX-Evo SD Load firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo SD Load firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo SD Load firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module top(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
assign clkz_out = 1'b0;
assign int_n = 1'bZ;
assign nmi_n = 1'bZ;
assign wait_n = 1'bZ;
assign res = 1'bZ;
assign d = 8'bZZZZ_ZZZZ;
assign csrom = 1'bZ;
assign romoe_n = 1'b1;
assign romwe_n = 1'b1;
assign rompg0_n = 1'b1;
assign dos_n = 1'b1;
assign rompg2 = 1'b1;
assign rompg3 = 1'b1;
assign rompg4 = 1'b1;
assign iorq1_n = 1'b1;
assign iorq2_n = 1'b1;
assign rd = 16'hZZZZ;
assign ra = 10'd0;
assign rwe_n = 1'b1;
assign rucas_n = 1'b1;
assign rlcas_n = 1'b1;
assign rras0_n = 1'b1;
assign rras1_n = 1'b1;
assign ay_clk = 1'b0;
assign ay_bdir = 1'b0;
assign ay_bc1 = 1'b0;
assign beep = 1'b0;
assign ide_a = 3'bZZZ;
assign ide_d = 16'hZZZZ;
assign ide_dir = 1'b0;
assign ide_cs0_n = 1'b1;
assign ide_cs1_n = 1'b1;
assign ide_rs_n = 1'b0;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_clk = 1'b0;
assign vg_cs_n = 1'b1;
assign vg_res_n = 1'b0;
assign vg_hdry = 1'b0;
assign vg_rclk = 1'b0;
assign vg_rawr = 1'b0;
assign vg_a a= 2'b00;
assign vg_wrd = 1'b0;
assign vg_side = 1'b0;
assign sdcs_n = 1'b1;
assign sddo = 1'b1;
assign sdclk = 1'b0;
assign spidi = 1'bZ;
assign spiint_n = 1'b1;
endmodule
|
`timescale 1ns / 1ps
module hvsync_generator(
input wire clk,
input wire reset,
output reg vga_h_sync,
output reg vga_v_sync,
output reg [10:0] CounterX,
output reg [10:0] CounterY,
output reg inDisplayArea
);
parameter TotalHorizontalPixels = 11'd800;
parameter HorizontalSyncWidth = 11'd96;
parameter VerticalSyncWidth = 11'd2;
parameter TotalVerticalLines = 11'd525;
parameter HorizontalBackPorchTime = 11'd144 ;
parameter HorizontalFrontPorchTime = 11'd784 ;
parameter VerticalBackPorchTime = 11'd12 ;
parameter VerticalFrontPorchTime = 11'd492;
reg VerticalSyncEnable;
reg [10:0] HorizontalCounter;
reg [10:0] VerticalCounter;
//Counter for the horizontal sync signal
always @(posedge clk or posedge reset)
begin
if(reset == 1)
HorizontalCounter <= 0;
else
begin
if(HorizontalCounter == TotalHorizontalPixels - 1)
begin //the counter has hreached the end of a horizontal line
HorizontalCounter<=0;
VerticalSyncEnable <= 1;
end
else
begin
HorizontalCounter<=HorizontalCounter+1;
VerticalSyncEnable <=0;
end
end
end
//Generate the vga_h_sync pulse
//Horizontal Sync is low when HorizontalCounter is 0-127
always @(*)
begin
if((HorizontalCounter<HorizontalSyncWidth))
vga_h_sync = 1;
else
vga_h_sync = 0;
end
//Counter for the vertical sync
always @(posedge clk or posedge reset)
begin
if(reset == 1)
VerticalCounter<=0;
else
begin
if(VerticalSyncEnable == 1)
begin
if(VerticalCounter==TotalVerticalLines-1)
VerticalCounter<=0;
else
VerticalCounter<=VerticalCounter+1;
end
end
end
//generate the vga_v_sync pulse
always @(*)
begin
if(VerticalCounter < VerticalSyncWidth)
vga_v_sync = 1;
else
vga_v_sync = 0;
end
always @(posedge clk)
begin
if((HorizontalCounter<HorizontalFrontPorchTime) && (HorizontalCounter>HorizontalBackPorchTime) && (VerticalCounter<VerticalFrontPorchTime) && (VerticalCounter>VerticalBackPorchTime))
begin
inDisplayArea <= 1;
CounterX<= HorizontalCounter - HorizontalBackPorchTime;
CounterY<= VerticalCounter - VerticalBackPorchTime;
end
else
begin
inDisplayArea <= 0;
CounterX<=0;
CounterY<=0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, teo = 0, s = 0, a[100001], t[100001]; cin >> n >> k; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) { cin >> t[i]; if (t[i] == 1) { teo = teo + a[i]; a[i] = 0; } a[i] = a[i] + a[i - 1]; } for (i = k; i <= n; i++) s = max(s, a[i] - a[i - k]); cout << teo + s; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 200010, LOG = 20; struct DSU { int par[MAXN]; int rank[MAXN]; stack<pair<int*, int>> stk; DSU() { for (int i = 1; i < MAXN; i++) par[i] = i; } int get(int x) { if (par[x] == x) return x; return get(par[x]); } int join(int x, int y) { x = get(x); y = get(y); if (x == y) return 0; if (rank[x] > rank[y]) swap(x, y); stk.push({&par[x], par[x]}); stk.push({&rank[y], rank[y]}); par[x] = y; rank[y] += (rank[x] == rank[y]); return 1; } void undo(int cnt = 1) { cnt <<= 1; while (cnt--) { auto it = stk.top(); stk.pop(); *it.first = it.second; } } } dsu; int n, m, k, u, v, x, y, a, b, last; int T[MAXN], X[MAXN], Y[MAXN]; map<pair<int, int>, vector<int>> mp; vector<pair<int, int>> seg[MAXN << 2]; set<pair<int, int>> edge; string out; int f(int x) { if (x == n) return 1; return x + 1; } pair<int, int> ff(int x, int y) { if (x > y) swap(x, y); return {x, y}; } void Add(int id, int tl, int tr, int l, int r, pair<int, int> p) { if (r <= tl || tr <= l) return; if (l <= tl && tr <= r) { seg[id].push_back(p); return; } int mid = (tl + tr) >> 1; Add(id << 1, tl, mid, l, r, p); Add(id << 1 | 1, mid, tr, l, r, p); } void handle(int i) { if (T[i] == 2) return; if (last) X[i] = f(X[i]), Y[i] = f(Y[i]); pair<int, int> p = ff(X[i], Y[i]); if (edge.count(p)) edge.erase(p); else edge.insert(p); } void dfs(int id, int tl, int tr) { int cnt = 0; for (pair<int, int> p : seg[id]) if (edge.count(p)) cnt += dsu.join(p.first, p.second); if (tr - tl == 1) { if (T[tl] == 1) ; else { int i = tl; if (last) X[i] = f(X[i]), Y[i] = f(Y[i]); out += 0 + (last = (dsu.get(X[i]) == dsu.get(Y[i]))); } } else { int mid = (tl + tr) >> 1; dfs(id << 1, tl, mid); handle(mid); dfs(id << 1 | 1, mid, tr); } dsu.undo(cnt); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> T[i] >> X[i] >> Y[i]; mp[ff(X[i], Y[i])].push_back(i); mp[ff(f(X[i]), f(Y[i]))].push_back(i); } for (auto it : mp) { it.second.push_back(m + 1); for (int i = 0; i < it.second.size() - 1; i++) Add(1, 1, m + 1, it.second[i], it.second[i + 1], it.first); } handle(1); dfs(1, 1, m + 1); cout << out << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t-- > 0) { char c[100005]; int n; cin >> n; string s0 = ; string sm = ; string s1 = ; bool flag0 = true; int pos1 = -1; int pos0 = -1; for (int i = 1; i <= n; i++) { cin >> c[i]; if (c[i] == 1 ) { if (flag0) flag0 = false; if (pos1 == -1) pos1 = i; s1 = s1 + 1 ; } else { if (flag0) s0 = s0 + 0 ; s1 = ; pos0 = i; } } if (pos1 != -1 && pos0 != -1 && pos0 > pos1) sm = 0 ; string s = s0 + sm + s1; cout << s << endl; } }
|
/*
* 16 to 8 bit instruction prefetch fifo
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to 16 to 8 bit by Charley Picker <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module zet_front_fifo16to8(
input clk_i,
input rst_i,
input flush_i,
input stb_i,
input [15:0] di,
output can_burst_o,
output do8_valid,
output reg [7:0] do8,
input next_i /* should only be asserted when do8_valid = 1 */
);
/*
* FIFO can hold 8 16-bit words
* that is 16 8-bit bytes.
*/
reg [15:0] storage[0:7];
reg [2:0] produce; /* in 16-bit words */
reg [3:0] consume; /* in 8-bit bytes */
/*
* 8-bit bytes stored in the FIFO, 0-15 (16 possible values)
*/
reg [3:0] level;
wire [15:0] do16;
assign do16 = storage[consume[3:1]];
always @(*) begin
case(consume[0])
1'd0: do8 <= do16[15:8];
1'd1: do8 <= do16[7:0];
endcase
end
always @(posedge clk_i) begin
if(rst_i) begin
produce = 3'd0;
consume = 4'd0;
level = 4'd0;
end else begin
if(stb_i) begin
storage[produce] = di;
produce = produce + 3'd1;
level = level + 4'd2;
end
if(next_i) begin /* next should only be asserted when do8_valid = 1 */
consume = consume + 4'd1;
level = level - 4'd1;
end
end
end
assign do8_valid = ~(level == 4'd0);
assign can_burst_o = level >= 4'd14;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; pair<double, double> p[301]; double a, b, c, den, len; double area(int i) { double num = abs(a * p[i].first + b * p[i].second + c); return (num) / (2.0); } double f(int i, int j) { a = (p[j].second - p[i].second); b = (p[i].first - p[j].first); c = 0 - p[i].second * b - p[i].first * a; den = sqrtf(a * a + b * b); len = sqrtf((p[i].first - p[j].first) * (p[i].first - p[j].first) + (p[i].second - p[j].second) * (p[i].second - p[j].second)); double m1 = -1, m2 = -1; for (int k = 0; k < n; ++k) { if (k == i or k == j) continue; long long temp = a * p[k].first + b * p[k].second + c; double flag = area(k); if (temp >= 0) m1 = max(m1, flag); else m2 = max(m2, flag); } if (m1 == -1 or m2 == -1) return 0; return m1 + m2; } int main() { cin >> n; for (int i = 0; i < n; ++i) { double x, y; scanf( %lf%lf , &x, &y); p[i] = {x, y}; } double ans = 0; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { ans = max(ans, f(i, j)); } } printf( %0.10f n , ans); return 0; }
|
`timescale 1ns/10ps
module DE0_NANO_SOC_QSYS_pll_sys(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(3),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("200.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, size = 1e6 + 1; cin >> n; vector<int> prime(1e6 + 1, 1); prime[0] = 0; prime[1] = 0; for (int ri = 2; ri <= sqrt(size); ri++) { if (prime[ri]) { for (int pi = ri * ri; pi <= size; pi += ri) if (prime[pi]) prime[pi] = 0; } } vector<long long int> tprime; for (long long int ri = 0; ri < size; ri++) { if (prime[ri]) { tprime.push_back(ri * ri); } } long long int arr[n]; for (int ri = 0; ri < n; ri++) scanf( %lld , &arr[ri]); for (int ri = 0; ri < n; ri++) { bool val = binary_search(tprime.begin(), tprime.end(), arr[ri]); if (val) cout << YES n ; else cout << NO n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp2 (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int n = 10, dir[4][2] = {{1, 0}, {0, 1}, {1, -1}, {1, 1}}; int main() { char b[n][n]; for (int i = 0; i < 10; i++) for (int j = 0; j < n; j++) scanf( %c , &b[i][j]); bool found = false; for (int i = 0; !found && i < n; i++) for (int j = 0; !found && j < n; j++) for (int k = 0; k < 4; k++) { int p = 0, q = 0; for (int l = 0; l < 5; l++) { int x = i + dir[k][0] * l, y = j + dir[k][1] * l; if (x < 0 || x >= n || y < 0 || y >= n) break; ; char c = b[x][y]; p += (c == X ), q += (c == . ); } if (p == 4 && q == 1) found = true; } if (found) printf( YES n ); else printf( NO n ); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_pgmrom.v when simulating
// the core, upd77c25_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [23 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [23 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, x = (int)(1e7 + 1); cin >> n; vector<bool> p(x, true); p[0] = p[1] = false; int c = 0; for (i = 2; i <= x; i++) { if (p[i]) { c++; cout << i << ; if (c == n) break; for (j = i; (long long)i * j <= x; j++) { p[i * j] = false; } } } cout << endl; return 0; }
|
#include <bits/stdc++.h> inline long long int min(long long int a, long long int b) { return (a < b) ? a : b; } long long int dp[303][303], cost[303][303]; int main() { int n, m, k, o, j, i; scanf( %d %d %d , &n, &m, &o); for (i = 0; i <= n; i++) for (j = 0; j <= n; j++) dp[i][j] = cost[i][j] = 10000000000000LL; for (i = 0; i < m; i++) { int l, r, c; scanf( %d %d %d , &l, &r, &c); cost[l][r] = min(cost[l][r], c); } for (i = 1; i <= n; i++) for (j = 1; j <= i; j++) for (k = i; k <= n; k++) { cost[j][i] = min(cost[j][i], cost[j][k]); cost[i][k] = min(cost[i][k], cost[j][k]); } for (i = 0; i <= n; i++) { dp[i][0] = 0; for (j = 1; j <= i; j++) { dp[i][j] = min(cost[i - j + 1][i], dp[i - 1][j]); for (k = 1; k < j; k++) dp[i][j] = min(dp[i][j], cost[i - k + 1][i] + dp[i - k][j - k]); } } if (dp[n][o] != 10000000000000LL) printf( %I64d n , dp[n][o]); else printf( -1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t) { t--; long long a, b; cin >> a >> b; long long n = a / b + (bool)(a % b); cout << b * n - a << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:05:46 08/01/2008
// Design Name:
// Module Name: test_vdu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test_vdu (
input sys_clk_in,
output tft_lcd_clk,
output [1:0] tft_lcd_r,
output [1:0] tft_lcd_g,
output [1:0] tft_lcd_b,
output tft_lcd_hsync,
output tft_lcd_vsync,
output led
);
// Net declarations
wire lock, rst;
// Module instantiations
clock clk0 (
.CLKIN_IN (sys_clk_in),
.CLKDV_OUT (tft_lcd_clk),
.LOCKED_OUT (lock)
);
vdu vdu0 (
.wb_rst_i (rst),
.wb_clk_i (tft_lcd_clk), // 25MHz VDU clock
.vga_red_o (tft_lcd_r),
.vga_green_o (tft_lcd_g),
.vga_blue_o (tft_lcd_b),
.horiz_sync (tft_lcd_hsync),
.vert_sync (tft_lcd_vsync)
);
// Continuous assignments
assign rst = !lock;
assign led = 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long ka[6] = {0, 0, 0, 0, 2, 4}; int main() { long long n, m; while (cin >> n >> m) { if (n > m) { int tmp = n; n = m; m = tmp; } long long ret; if (n == 1) ret = m / 6 * 6 + ka[m % 6]; else if (n == 2) { if (m == 2) ret = 0; else if (m == 3) ret = 4; else if (m == 7) ret = 12; else ret = n * m; } else { if (n % 2 && m % 2) ret = n * m - 1; else ret = n * m; } cout << ret << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int n; cin >> n; int maxi = 0, mini = 1000000000; vector<long long int> a(n, 0); long long int xor1 = 0; long long int sum1 = 0; for (int i = 0; i < n; i++) { cin >> a[i]; xor1 ^= a[i]; sum1 += a[i]; } sum1 += xor1; cout << 2 << endl << xor1 << << sum1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3010; bool visit[maxn]; int n, m, ans, f[maxn]; vector<int> ve; vector<pair<int, int> > maps[maxn]; void first_dfs(const int u) { visit[u] = 1; for (int i = 0; i < ((int)(maps[u]).size()); ++i) { int v = maps[u][i].first; int w = maps[u][i].second; if (!visit[v]) { first_dfs(v); f[u] += f[v] + w; } } } void second_dfs(const int u) { visit[u] = 1; for (int i = 0; i < ((int)(maps[u]).size()); ++i) { int v = maps[u][i].first; int w = maps[u][i].second; if (!visit[v]) { f[v] = f[u] + (w ? -1 : 1); m = min(m, f[v]); second_dfs(v); } } } void solve(const int u) { first_dfs(u); ans = min(ans, f[u]); if (((int)(maps[u]).size()) >= 2) { ve.clear(); memset(visit, 0, sizeof(visit)); visit[u] = 1; for (int i = 0; i < ((int)(maps[u]).size()); ++i) { int v = maps[u][i].first; int w = maps[u][i].second; m = f[v]; second_dfs(v); ve.push_back(m + (w ? -1 : 1) - f[v]); } sort(ve.begin(), ve.end()); ans = min(ans, f[u] + ve[0] + ve[1]); } } int main() { scanf( %d , &n); int u, v; for (int i = 1; i < n; ++i) { scanf( %d%d , &u, &v); maps[u].push_back(make_pair(v, 0)); maps[v].push_back(make_pair(u, 1)); } ans = maxn; for (int i = 1; i <= n; ++i) { memset(f, 0, sizeof(f)); memset(visit, 0, sizeof(visit)); solve(i); } printf( %d n , ans); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Dedicated Dual Data Rate (DDR) Output Register
// /___/ /\ Filename : ODDRE1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ODDRE1 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D1_INVERTED = 1'b0,
parameter [0:0] IS_D2_INVERTED = 1'b0,
parameter [0:0] SRVAL = 1'b0
)(
output Q,
input C,
input D1,
input D2,
input SR
);
// define constants
localparam MODULE_NAME = "ODDRE1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "ODDRE1_dr.v"
`else
localparam [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
localparam [0:0] IS_D1_INVERTED_REG = IS_D1_INVERTED;
localparam [0:0] IS_D2_INVERTED_REG = IS_D2_INVERTED;
localparam [0:0] SRVAL_REG = SRVAL;
`endif
wire IS_C_INVERTED_BIN;
wire IS_D1_INVERTED_BIN;
wire IS_D2_INVERTED_BIN;
wire SRVAL_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg Q_out,QD2_posedge_int;
reg R_sync1 = 1'b0;
reg R_sync2 = 1'b0;
reg R_sync3 = 1'b0;
wire Q_delay;
wire C_in;
wire D1_in;
wire D2_in;
wire SR_in;
wire C_delay;
wire D1_delay;
wire D2_delay;
wire SR_delay;
assign #(out_delay) Q = Q_delay;
// inputs with no timing checks
assign #(inclk_delay) C_delay = C;
assign #(in_delay) D1_delay = D1;
assign #(in_delay) D2_delay = D2;
assign #(in_delay) SR_delay = SR;
assign Q_delay = Q_out;
assign C_in = C_delay ^ IS_C_INVERTED_BIN;
assign D1_in = D1_delay ^ IS_D1_INVERTED_BIN;
assign D2_in = D2_delay ^ IS_D2_INVERTED_BIN;
assign SR_in = SR_delay;
assign IS_C_INVERTED_BIN = IS_C_INVERTED_REG;
assign IS_D1_INVERTED_BIN = IS_D1_INVERTED_REG;
assign IS_D2_INVERTED_BIN = IS_D2_INVERTED_REG;
assign SRVAL_BIN = SRVAL_REG;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IS_C_INVERTED_REG !== 1'b0) && (IS_C_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-101] IS_C_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_C_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_D1_INVERTED_REG !== 1'b0) && (IS_D1_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] IS_D1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_D1_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_D2_INVERTED_REG !== 1'b0) && (IS_D2_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] IS_D2_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_D2_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SRVAL_REG !== 1'b0) && (SRVAL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-106] SRVAL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, SRVAL_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(posedge C_in) begin
R_sync1 <= SR_in;
R_sync2 <= R_sync1;
R_sync3 <= R_sync2;
end
always @ (glblGSR or SR_in or R_sync1 or R_sync2 or R_sync3) begin
if (glblGSR == 1'b1) begin
assign Q_out = SRVAL_REG;
assign QD2_posedge_int = SRVAL_REG;
end
else if (glblGSR == 1'b0) begin
if (SR_in == 1'b1 || R_sync1 == 1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1 ) begin
assign Q_out = SRVAL_REG;
assign QD2_posedge_int = SRVAL_REG;
end
else if (R_sync3 == 1'b0) begin
deassign Q_out;
deassign QD2_posedge_int;
end
end
end
always @(posedge C_in) begin
if (SR_in == 1'b1 || R_sync1 ==1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1) begin
Q_out <= SRVAL_REG;
QD2_posedge_int <= SRVAL_REG;
end
else if (R_sync3 == 1'b0) begin
Q_out <= D1_in;
QD2_posedge_int <= D2_in;
end
end
always @(negedge C_in) begin
if (SR_in == 1'b1 || R_sync1 == 1'b1 || R_sync2 == 1'b1 || R_sync3 == 1'b1)
Q_out <= SRVAL_REG;
else if (R_sync3 == 1'b0) begin
Q_out <= QD2_posedge_int;
end
end
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_TB_V
`define SKY130_FD_SC_HVL__DECAP_TB_V
/**
* decap: Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__decap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hvl__decap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e7; long long int a[N], ans; int main() { long long int n; cin >> n; long long int l = 0, r = n - 1; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = 0; i < n / 2; i++) { ans += (a[l] + a[r]) * (a[l] + a[r]); r--, l++; } cout << ans; }
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 04/18/2012
// Description: divider core using successive approximation method
//-----------------------------------------------
module divider_28_20 #
(
parameter LATENCY=8,
parameter DIVIDEND_W=28,
parameter DIVISOR_W=20,
parameter QUOTIENT_W=28
)
(
input clk,
input start,
input [DIVIDEND_W-1:0]dividend,
input [DIVISOR_W-1:0]divisor,
output [QUOTIENT_W-1:0]quotient,
output qv
);
//-----------------------------------------------
reg [DIVIDEND_W-1:0] dividend_reg = 0;
reg [DIVISOR_W-1:0] divisor_reg = 0;
reg [QUOTIENT_W-1:0]sar=0;
wire [DIVISOR_W+QUOTIENT_W-1:0]mul_res;
reg [7:0]i;
reg [7:0]lat_cnt;
reg rv_reg=1'b0;
reg [QUOTIENT_W-1:0]result_reg;
//-----------------------------------------------
mult_28_20_lm instance_name
(
.clk(clk),
.a(sar),
.b(divisor_reg),
.p(mul_res)
);
//-----------------------------------------------
parameter IDLE=2'b00;
parameter DIV=2'b01;
parameter NOP=2'b10;
parameter END=2'b11;
reg [1:0]state=IDLE;
//-----------------------------------------------
always @(posedge clk)
begin
rv_reg<=1'b0;
case(state)
IDLE:
begin
i<=QUOTIENT_W-1;
sar<=0;
if(start)
begin
state<=DIV;
dividend_reg <= dividend;
divisor_reg <= divisor;
end
end
DIV:
begin
sar[i]<=1;
lat_cnt<=LATENCY;
state<=NOP;
end
NOP:
begin
lat_cnt<=lat_cnt-1;
if(lat_cnt==0)
begin
if(mul_res>dividend_reg) sar[i]<=0;
i<=i-1;
if(i==0) state<=END;
else state<=DIV;
end
end
END:
begin
rv_reg<=1'b1;
result_reg<=sar;
state<=IDLE;
end
endcase
end
//-----------------------------------------------
assign quotient=result_reg;
assign qv=rv_reg;
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
//-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
module apl2c_connect(autoinoutmodport_type_intf ctl_i,
/*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
// Beginning of automatic in/out/inouts (from modport)
input [4:0] inst,
input isel_t isel,
input replay
// End of automatics
);
/*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
// Beginning of automatic assignments from modport
assign ctl_i.inst = inst;
assign ctl_i.isel = isel;
assign ctl_i.replay = replay;
// End of automatics
endmodule
interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
import uvm_pkg::*;
import ap_defines::*;
logic [4:0] inst;
isel_t isel;
logic replay;
clocking ctl_cb @(posedge clk);
input inst;
input isel;
input replay;
endclocking: ctl_cb
modport ctl_mp(clocking ctl_cb);
endinterface
// Local Variables:
// verilog-typedef-regexp:"_t"
// End:
|
`timescale 1ps/1ps
module test_spi_device_test;
reg running;
reg [7:0] data;
reg [3:0] cnt;
reg [4:0] clk_cnt;
reg clk;
reg reset;
reg end_flag;
reg [7:0] buffer;
wire mosi;
reg sck;
wire miso;
assign mosi = buffer[7];
parameter osc = / 4;
test_spi_device device (reset, sck, mosi, miso);
initial begin
$dumpfile("test_spi_device_test.vcd");
$dumpvars(0, test_spi_device_test);
reset <= 1'b1;
running <= 1'b0;
cnt <= 3'b0;
clk <= 1'b0;
clk_cnt <= 5'b0;
data <= 8'b0;
end_flag <= 1'b0;
#10
reset <= 1'b0;
#10
reset <= 1'b1;
end
always #(osc/2) begin
clk <= ~clk;
end
always @(posedge clk) begin
clk_cnt <= clk_cnt + 4'b1;
if (running) begin
if (clk_cnt == 5'b01111) begin
sck <= 1'b1;
end
if (clk_cnt == 5'b11111) begin
sck <= 1'b0;
buffer[7:0] <= { buffer[6:0] , miso };
cnt <= cnt + 3'b1;
if (cnt == 3'b111) begin
running <= 1'b0;
data[7:0] <= data[7:0] + 8'b1;
if (data[7:0] == 8'b11111111) end_flag <= 1'b1;
end
end
end else begin
if (clk_cnt == 5'b11111) begin
running <= 1'b1;
cnt <= 3'b0;
buffer[7:0] <= data[7:0];
if (end_flag) $finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long g; void ex_gcd(long long a, long long b, long long& x, long long& y) { if (!b) { g = a; x = 1, y = 0; } else { ex_gcd(b, a % b, y, x); y = y - a / b * x; } } int main() { long long a, b, c; scanf( %lld%lld%lld , &a, &b, &c); long long x, y; ex_gcd(a, b, x, y); if (c % g != 0) return 0 * printf( -1 n ); return 0 * printf( %lld %lld n , x * (-c / g), y * (-c / g)); }
|
#include <bits/stdc++.h> using namespace std; int n; string a, b; void perform(int len) { for (int i = 0; i < len / 2; ++i) { if (a[i] == a[len - 1 - i]) { a[i] = 0 + 1 - a[i]; a[len - 1 - i] = 0 + 1 - a[len - 1 - i]; } } if (len & 1) a[len / 2] = 0 + 1 - a[len / 2]; } int main() { int t; cin >> t; while (t--) { cin >> n >> a >> b; int k = 0; vector<int> ops; for (int i = n - 1; i >= 0; --i) { if (a[i] != a[0]) perform(1), ++k, ops.push_back(1); if (a[i] != b[i]) perform(i + 1), ++k, ops.push_back(i + 1); } cout << k << ; for (int x : ops) cout << x << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> const int MAXN = 2e5 + 10; const int mod = 1e9 + 7; void reduce(int& x) { x += x >> 31 & mod; } int mul(int a, int b) { return (long long)a * b % mod; } int pow(int a, int b, int res = 1) { for (; b; b >>= 1, a = mul(a, a)) if (b & 1) res = mul(res, a); return res; } const int MAXS = 1e6 + 1; int pri[MAXS], npri[MAXS], tot; int fac[MAXS], inv[MAXS]; void sieve() { inv[0] = inv[1] = 1; fac[1] = 1; for (int i = 2; i != MAXS; ++i) { inv[i] = mul(inv[mod % i], mod - mod / i); if (!npri[i]) fac[pri[++tot] = i] = i; for (int j = 1, t; j <= tot && (t = i * pri[j]) < MAXS; ++j) { npri[t] = true; fac[t] = pri[j]; if (i % pri[j] == 0) break; } } } int A[MAXN]; int n, m; int pre[MAXN]; int tr[MAXN]; void add(int x, int v) { for (; x; x &= x - 1) tr[x] = mul(tr[x], v); } int lst[MAXS], ansl[MAXN]; int ls[MAXN]; std::vector<int> qs[MAXN]; int qry(int x) { int r = 1; for (; x <= n; x += x & -x) r = mul(r, tr[x]); return r; } int main() { std::ios_base::sync_with_stdio(false), std::cin.tie(0); sieve(); std::cin >> n; pre[0] = 1; for (int i = 1; i <= n; ++i) { std::cin >> A[i]; pre[i] = mul(pre[i - 1], A[i]); tr[i] = 1; } std::cin >> m; for (int i = 1, r; i <= m; ++i) { std::cin >> ls[i] >> r; qs[r].push_back(i); } for (int i = 1; i <= n; ++i) { std::set<int> hl; int x = A[i]; while (x > 1) hl.insert(fac[x]), x /= fac[x]; for (auto t : hl) { add(lst[t], mul(inv[t - 1], t)); add(lst[t] = i, mul(inv[t], t - 1)); } for (auto t : qs[i]) { ansl[t] = pow(pre[ls[t] - 1], mod - 2, pre[i]); ansl[t] = mul(ansl[t], qry(ls[t])); } } for (int i = 1; i <= m; ++i) std::cout << ansl[i] << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O2111A_FUNCTIONAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; string inst; cin >> inst; int total = 0; for (int i = 0; i < N; i++) { for (int j = i + 1; j < N; j++) { int ct_u = 0; int ct_l = 0; for (int k = i; k <= j; k++) { if (inst[k] == U ) { ct_u++; } else if (inst[k] == D ) { ct_u--; } else if (inst[k] == L ) { ct_l--; } else if (inst[k] == R ) { ct_l++; } } if (ct_u == 0 && ct_l == 0) total++; } } cout << total << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[1010000]; int main() { int i, j, k, m, n; scanf( %s , s); n = strlen(s); if (n % 2 == 1) { n = (n + 1) / 2; for (i = 1; i <= n; i++) putchar( 4 ); for (i = 1; i <= n; i++) putchar( 7 ); puts( ); } else { char u = 7 ; int flag = 0; for (i = 0; i < n; i++) { if (i + i == n) u = 4 ; if (s[i] > u) { flag = -1; break; } else if (s[i] < u) { flag = 1; break; } } if (flag == -1) { n = (n + 2) / 2; for (i = 1; i <= n; i++) putchar( 4 ); for (i = 1; i <= n; i++) putchar( 7 ); puts( ); } else { int pos = -1; int c4 = 0, c7 = 0; int f = 0; for (i = 0; i < n; i++) { if (f || s[i] <= 4 ) { if (s[i] < 4 ) f = 1; s[i] = 4 ; pos = i; c4++; } else if (s[i] <= 7 ) { if (s[i] < 7 ) f = 1; s[i] = 7 ; c7++; } else { s[i] = 4 ; s[pos] = 7 ; pos = i; c7++; f = 1; } } if (c7 > c4) { int cnt = 0; for (i = n - 1; i >= 0; i--) { if (s[i] == 7 ) cnt++; if (cnt >= (c7 - c4) / 2 + 1) break; } for (; i >= 0; i--) if (s[i] == 4 ) { c7++; c4--; s[i] = 7 ; break; } for (i = i + 1; i < n; i++) if (s[i] == 7 ) { s[i] = 4 ; c7--; c4++; } } if (c7 < c4) { for (i = n - 1; i >= 0; i--) { if (c4 > c7 && s[i] == 4 ) { s[i] = 7 ; c4--; c7++; } } } puts(s); } } scanf( %*d ); }
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/uart/uart.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* UART controller. Universal Asynchronous Receiver/Transmitter control module for an RS-232
* (serial) port.
***************************************************************************************************/
`include "uart_baud_clk.v"
`include "uart_rx.v"
`include "uart_tx.v"
`include "../fifo/fifo.v"
module uart
#(
parameter SYS_CLK_FREQ = 50000000,
parameter BAUD_RATE = 19200,
parameter DATA_BITS = 8,
parameter STOP_BITS = 1,
parameter PARITY_MODE = 0 // 0 = none, 1 = odd, 2 = even
)
(
input wire clk, // System clk
input wire reset, // Reset signal
input wire rx, // RS-232 rx pin
input wire [DATA_BITS-1:0] tx_data, // Data to be transmitted when wr_en is 1
input wire rd_en, // Pops current read FIFO front off the queue
input wire wr_en, // Write tx_data over serial connection
output wire tx, // RS-232 tx pin
output wire [DATA_BITS-1:0] rx_data, // Data currently at front of read FIFO
output wire rx_empty, // 1 if there is no more read data available
output wire tx_full, // 1 if the transmit FIFO cannot accept more requests
output wire parity_err // 1 if a parity error has been detected
);
localparam BAUD_CLK_OVERSAMPLE_RATE = 16;
wire baud_clk_tick;
wire [DATA_BITS-1:0] rx_fifo_wr_data;
wire rx_done_tick;
wire rx_parity_err;
wire [DATA_BITS-1:0] tx_fifo_rd_data;
wire tx_done_tick;
wire tx_fifo_empty;
// Store parity error in a flip flop as persistent state.
reg q_rx_parity_err;
wire d_rx_parity_err;
always @(posedge clk, posedge reset)
begin
if (reset)
q_rx_parity_err <= 1'b0;
else
q_rx_parity_err <= d_rx_parity_err;
end
assign parity_err = q_rx_parity_err;
assign d_rx_parity_err = q_rx_parity_err || rx_parity_err;
// BAUD clock module
uart_baud_clk #(.SYS_CLK_FREQ(SYS_CLK_FREQ),
.BAUD(BAUD_RATE),
.BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_baud_clk_blk
(
.clk(clk),
.reset(reset),
.baud_clk_tick(baud_clk_tick)
);
// RX (receiver) module
uart_rx #(.DATA_BITS(DATA_BITS),
.STOP_BITS(STOP_BITS),
.PARITY_MODE(PARITY_MODE),
.BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_rx_blk
(
.clk(clk),
.reset(reset),
.baud_clk_tick(baud_clk_tick),
.rx(rx),
.rx_data(rx_fifo_wr_data),
.rx_done_tick(rx_done_tick),
.parity_err(rx_parity_err)
);
// TX (transmitter) module
uart_tx #(.DATA_BITS(DATA_BITS),
.STOP_BITS(STOP_BITS),
.PARITY_MODE(PARITY_MODE),
.BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_tx_blk
(
.clk(clk),
.reset(reset),
.baud_clk_tick(baud_clk_tick),
.tx_start(~tx_fifo_empty),
.tx_data(tx_fifo_rd_data),
.tx_done_tick(tx_done_tick),
.tx(tx)
);
// RX FIFO
fifo #(.DATA_BITS(DATA_BITS),
.ADDR_BITS(3)) uart_rx_fifo
(
.clk(clk),
.reset(reset),
.rd_en(rd_en),
.wr_en(rx_done_tick),
.wr_data(rx_fifo_wr_data),
.rd_data(rx_data),
.empty(rx_empty),
.full()
);
// TX FIFO
fifo #(.DATA_BITS(DATA_BITS),
.ADDR_BITS(3)) uart_tx_fifo
(
.clk(clk),
.reset(reset),
.rd_en(tx_done_tick),
.wr_en(wr_en),
.wr_data(tx_data),
.rd_data(tx_fifo_rd_data),
.empty(tx_fifo_empty),
.full(tx_full)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$P (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; char ss[100002]; int main() { int N, K, k = 0; scanf( %d %d , &N, &K); scanf( %s , ss); string S = ss; for (int i = 0; i < N - 1 && k < K; i++) { if (S[i] == 4 && S[i + 1] == 7 ) { int x = i + 1; if (x % 2) { if (x + 1 < N && S[x + 1] == 7 ) { if ((K - k) % 2) { S[x] = 4 ; } printf( %s , S.c_str()); return 0; } S[x] = 4 ; } else { S[x - 1] = 7 ; i -= 2; } k++; } } printf( %s n , S.c_str()); return 0; }
|
//--------------------------------------------------------------------------------
// stage.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Programmable 32 channel trigger stage. It can operate in serial
// and parallel mode. In serial mode any of the input channels
// can be used as input for the 32bit shift register. Comparison
// is done using the value and mask registers on the input in
// parallel mode and on the shift register in serial mode.
// If armed and 'level' has reached the configured minimum value,
// the stage will start to check for a match.
// The match and run output signal delay can be configured.
// The stage will disarm itself after a match occured or when reset is set.
//
// The stage supports "high speed demux" operation in serial and parallel
// mode. (Lower and upper 16 channels contain a 16bit sample each.)
//
// Matching is done using a pipeline. This should not increase the minimum
// time needed between two dependend trigger stage matches, because the
// dependence is evaluated in the last pipeline step.
// It does however increase the delay for the capturing process, but this
// can easily be software compensated. (By adjusting the before/after ratio.)
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Ian Davis (IED) - Verilog version, changed to use LUT based
// masked comparisons, and other cleanups created - mygizmos.org
//
`timescale 1ns/100ps
module stage(
// system signals
input wire clk,
input wire rst,
// input stream
input wire validIn,
input wire [31:0] dataIn, // Channel data...
//
input wire wrenb, // LUT update write enb
input wire [7:0] din, // LUT update data. All 8 LUT's are updated simultaneously.
input wire wrConfig, // Write the trigger config register
input wire [31:0] config_data, // Data to write into trigger config regs
input wire arm,
input wire demux_mode,
input wire [1:0] level,
output reg run,
output reg match
);
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
//
// Registers...
//
reg [27:0] configRegister;
reg [15:0] counter, next_counter;
reg [31:0] shiftRegister;
reg match32Register;
reg next_run;
reg next_match;
//
// Useful decodes...
//
wire cfgStart = configRegister[27];
wire cfgSerial = configRegister[26];
wire [4:0] cfgChannel = configRegister[24:20];
wire [1:0] cfgLevel = configRegister[17:16];
wire [15:0] cfgDelay = configRegister[15:0];
//
// Handle mask, value & config register write requests
//
always @ (posedge clk)
configRegister <= (wrConfig) ? config_data[27:0] : configRegister;
//
// Use shift register or dataIn depending on configuration...
//
wire [31:0] testValue = (cfgSerial) ? shiftRegister : dataIn;
//
// Do LUT table based comparison...
//
wire [7:0] dout;
wire [7:0] matchLUT;
trigterm_4bit byte0 (testValue[ 3: 0], clk, wrenb, din[0], dout[0], matchLUT[0]);
trigterm_4bit byte1 (testValue[ 7: 4], clk, wrenb, din[1], dout[1], matchLUT[1]);
trigterm_4bit byte2 (testValue[11: 8], clk, wrenb, din[2], dout[2], matchLUT[2]);
trigterm_4bit byte3 (testValue[15:12], clk, wrenb, din[3], dout[3], matchLUT[3]);
trigterm_4bit byte4 (testValue[19:16], clk, wrenb, din[4], dout[4], matchLUT[4]);
trigterm_4bit byte5 (testValue[23:20], clk, wrenb, din[5], dout[5], matchLUT[5]);
trigterm_4bit byte6 (testValue[27:24], clk, wrenb, din[6], dout[6], matchLUT[6]);
trigterm_4bit byte7 (testValue[31:28], clk, wrenb, din[7], dout[7], matchLUT[7]);
wire matchL16 = &matchLUT[3:0];
wire matchH16 = &matchLUT[7:4];
//
// In demux mode only one half must match, in normal mode both words must match...
//
always @(posedge clk)
if (demux_mode) match32Register <= matchH16 | matchL16;
else match32Register <= matchH16 & matchL16;
//
// Select serial channel based on cfgChannel...
//
wire serialChannelL16 = dataIn[{1'b0,cfgChannel[3:0]}];
wire serialChannelH16 = dataIn[{1'b1,cfgChannel[3:0]}];
//
// Shift in bit from selected channel whenever dataIn is ready...
always @(posedge clk)
if (validIn) begin
// in demux mode two bits come in per sample
if (demux_mode) shiftRegister <= {shiftRegister, serialChannelH16, serialChannelL16};
else shiftRegister <= {shiftRegister, (cfgChannel[4]) ? serialChannelH16 : serialChannelL16};
end
//
// Trigger state machine...
//
localparam [1:0]
OFF = 2'h0,
ARMED = 2'h1,
MATCHED = 2'h2;
reg [1:0] state, next_state;
initial state = OFF;
always @(posedge clk, posedge rst)
if (rst) begin
state <= OFF;
counter <= 0;
match <= FALSE;
run <= FALSE;
end else begin
state <= next_state;
counter <= next_counter;
match <= next_match;
run <= next_run;
end
always @*
begin
next_state = state;
next_counter = counter;
next_match = FALSE;
next_run = FALSE;
case (state) // synthesis parallel_case
OFF :
begin
if (arm) next_state = ARMED;
end
ARMED :
begin
next_counter = cfgDelay;
if (match32Register && (level >= cfgLevel))
next_state = MATCHED;
end
MATCHED :
begin
if (validIn)
begin
next_counter = counter-1'b1;
if (~|counter)
begin
next_run = cfgStart;
next_match = ~cfgStart;
next_state = OFF;
end
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, c; double dp[102][102][102]; int main() { scanf( %d%d%d , &a, &b, &c); int n = max(max(a, b), c); dp[1][0][0] = 1; dp[1][1][0] = 1; for (int i = 1; i <= n; i++) dp[i][0][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j <= n; j++) for (int k = 0; k <= n; k++) { if (j && k) { double p = i * j + j * k + k * i; dp[i][j][k] = (dp[i][j - 1][k] * i * j + dp[i][j][k - 1] * j * k + dp[i - 1][j][k] * k * i) / p; } if (j && !k) dp[i][j][k] = 1; if (!j && k) dp[i][j][k] = 0; if (!j && !k) dp[i][j][k] = 1; } printf( %.12f %.12f %.12f , dp[a][b][c], dp[b][c][a], dp[c][a][b]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; int hp[N], dmg[N], p[N]; bool cmp(int a, int b) { return hp[a] - dmg[a] > hp[b] - dmg[b]; } bool vis[N]; int main() { int n, a, b; scanf( %d%d%d , &n, &a, &b); for (int i = 1; i <= n; i++) { scanf( %d%d , &hp[i], &dmg[i]); p[i] = i; } sort(p + 1, p + 1 + n, cmp); long long sum = 0, ans, la = 0, cb = 0; bool flag = false; for (int i = 1; i <= n; i++) { if (i > b || hp[p[i]] <= dmg[p[i]]) { if (!flag) flag = true, la = hp[p[i - 1]] - dmg[p[i - 1]], cb = i - 1; } if (!flag) sum += hp[p[i]], vis[p[i]] = true; else sum += dmg[p[i]]; } ans = sum; if (a && b) { for (int i = 1; i <= n; i++) { long long tmp = hp[i]; for (int j = 1; j <= a; j++) tmp = tmp * 2; tmp += sum; if (vis[i]) { tmp -= hp[i]; } else { tmp -= dmg[i]; if (cb == b) tmp -= la; } ans = max(ans, tmp); } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200000 + 1]; struct info { int sum, prop; } t[3 * 200000 + 3]; void build(int node, int b, int e) { if (b >= e) { if (b == e) t[node].sum = a[b]; return; } int left = node << 1; int right = left | 1; int mid = (b + e) >> 1; build(left, b, mid); build(right, mid + 1, e); t[node].sum = t[left].sum + t[right].sum; } void update(int node, int b, int e, int i, int j) { if (i > e || j < b) return; if (b > e) return; if (b >= i && e <= j) { t[node].sum += ((e - b + 1) * 1); t[node].prop += 1; return; } int left = node << 1; int right = left | 1; int mid = (b + e) >> 1; update(left, b, mid, i, j); update(right, mid + 1, e, i, j); t[node].sum = t[left].sum + t[right].sum + (e - b + 1) * t[node].prop; } int query(int node, int b, int e, int pos, int carry = 0) { if (pos < b || e < pos) return 0; if (b > e) return 0; if (b == pos && pos == e) return t[node].sum + carry * (e - b + 1); int left = node << 1; int right = left | 1; int mid = (b + e) >> 1; int p1 = query(left, b, mid, pos, carry + t[node].prop); int p2 = query(right, mid + 1, e, pos, carry + t[node].prop); return p1 + p2; } int chk[200000 + 1]; int main() { int n, k, q, i, l, r; cin >> n >> k >> q; for (i = 0; i < n; i++) { scanf( %d %d , &l, &r); update(1, 1, 200000, l, r); } for (i = 1; i <= 200000; i++) { if (query(1, 1, 200000, i) >= k) chk[i] = 1; } for (i = 1; i <= 200000; i++) chk[i] += chk[i - 1]; for (i = 0; i < q; i++) { scanf( %d %d , &l, &r); cout << chk[r] - chk[l - 1] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int s, x1, x2, t1, t2, p, d; int main() { cin >> s >> x1 >> x2 >> t1 >> t2 >> p >> d; int t = 0, flag1 = 0, flag2 = 0; while (flag1 == 0 || flag2 == 0) { if (flag1) { if (p == x2) break; } else if (p == x1) flag1 = 1; if (p == 0 || p == s) d = -d; p += d; t++; } cout << min(t * t1, abs(x1 - x2) * t2) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; bool debug = 1; long long MOD = 1e9 + 7; const int N = 2e5 + 10; map<int, vector<int>> mpe, mps; int nonred[N]; int n; set<int> st; int main() { cin >> n; for (int i = 0; i < n; i++) { int l, r; scanf( %d%d , &l, &r); mpe[l].push_back(i + 1); mps[r + 1].push_back(i + 1); st.insert(l); st.insert(r + 1); } set<int> at; for (auto &tempo : st) { for (auto &it : mpe[tempo]) { at.insert(it); } for (auto &it : mps[tempo]) { if (!nonred[it]) { cout << it << endl; return 0; } at.erase(it); } if (at.size() == 1) { nonred[*at.begin()] = 1; } } cout << -1 << endl; return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:03:44 08/31/2014
// Design Name:
// Module Name: lab5dpath
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5dpath(reset, clk, irdy, ordy, din, dout );
input reset, clk, irdy;
input [9:0] din;
output [9:0] dout;
output ordy;
wire [11:0] k1, k2, k3, dmod, mmod, add;
wire [23:0] m;
//fsm control
reg lda, ldb, s_ordy, c_ordy, ordy;
reg [1:0] nstate, pstate, s, sregb;
reg [11:0] k, aq, bq, bd;
//assign k hard encoding
assign k1 = 12'b110000000000;
assign k3 = 12'b110000000000;
assign k2 = 12'b010100000000;
`define STATE_S1 2'b00
`define STATE_S2 2'b01
`define STATE_S3 2'b10
`define STATE_S4 2'b11
// add 2 to lsb of din
assign dmod = {din, 2'b00};
// handle k mux
always @ (posedge clk) begin
k = k1;
case (s)
2'b01:
k = k2;
2'b10:
k = k3;
2'b11:
k = 12'b000000000001;
endcase
end
//multiplier
mult12x12 i1 (.a(k), .b(dmod), .p(m));
// modify mult
assign mmod = m[22:11];
// adder
assign add = bq + aq;
always @* begin
case (sregb)
2'b00:
bd = mmod;
2'b01:
bd = add;
2'b10:
bd = 12'b000000000000;
endcase
end
//regA
always @(posedge clk) begin
if (lda)
aq <= mmod;
end
//regB
always @(posedge clk) begin
if (ldb)
bq <= bd;
end
//handle ordy
always @(posedge clk or posedge reset) begin
if (reset) begin
ordy <= 0;
end
else begin
if (s_ordy) ordy <= 1;
if (c_ordy) ordy <= 0;
end
end
//set state during startup.
always @(posedge clk or posedge reset) begin
if (reset) begin
pstate <= `STATE_S1;
end
else begin
pstate <= nstate;
end
end
//fsm
always @* begin
lda = 0; ldb = 0;
s_ordy = 0; c_ordy = 0;
sregb = 2'b00; s = 2'b00;
nstate = pstate;
case (pstate)
`STATE_S1: begin
lda = 1;
if (irdy == 1)begin
s = 2'b01;
nstate = `STATE_S2;
c_ordy = 1;
end
end
`STATE_S2: begin
s = 2'b10;
ldb = 1;
sregb = 2'b00;
nstate = `STATE_S3;
end
`STATE_S3: begin
lda = 1;
sregb = 2'b01;
ldb = 1;
nstate = `STATE_S4;
end
`STATE_S4: begin
sregb = 2'b01;
ldb = 1;
s_ordy = 1;
nstate = `STATE_S1;
end
endcase
end
//output
assign dout = bq[11:2];
endmodule
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#include <bits/stdc++.h> using namespace std; long long n, m, a[1005], b[1005], c[1005], d[1005], ans, tot; ; char s[1005]; long long calc() { long long cc = 0; for (long long i = 1; i <= n; i++) if (c[i]) { ans += (c[i] - 1) * (m - c[i]) * 4; for (long long j = i + 1; j <= n; j++) if (!c[j] || c[j] < c[j - 1]) break; else cc += (c[i] - 1) * (m - c[j]) * 4; for (long long j = i + 1; j <= n; j++) if (!c[j] || c[j] > c[j - 1]) break; else cc += (c[j] - 1) * (m - c[i]) * 4; } return cc; } int main() { scanf( %I64d%I64d , &n, &m); for (long long i = 1; i <= n; i++) { scanf( %s , s + 1); for (long long j = 1; j <= m; j++) if (s[j] == . ) tot++, a[i]++, b[j]++; else c[i] = j, d[j] = i; } long long o, ct, su; o = ct = su = 0; for (long long i = 1; i <= n; i++) o += su * a[i], ct += a[i], su += ct; ans = o * 2; o = ct = su = 0; for (long long i = 1; i <= m; i++) o += su * b[i], ct += b[i], su += ct; ans += o * 2; ans += calc(); swap(n, m); for (long long i = 1; i <= n; i++) c[i] = d[i]; ans += calc(); printf( %.16lf , ((double)ans) / tot / tot); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k, s, a[5][205]; struct node { int id, x, y; }; vector<node> ans; inline void park() { for (int i = 0; i <= 2 * n - 1; ++i) if (a[1][i] && a[1][i] == a[0][i]) { ans.push_back(node{a[1][i], i / n ? 4 : 1, i % n + 1}); a[1][i] = 0; k--; } } inline bool judge() { park(); for (int i = 0; i <= 2 * n - 1; ++i) if (!a[1][i]) return 1; return 0; } inline void turn() { vector<node> t1, t2; int t = a[1][2 * n - 1]; for (int i = 2 * n - 1; i >= 1; --i) { a[1][i] = a[1][i - 1]; if (a[1][i]) { if (i > s) t1.push_back(node{a[1][i], i / n ? 3 : 2, i % n + 1}); else t2.push_back(node{a[1][i], i / n ? 3 : 2, i % n + 1}); } } a[1][0] = t; if (t) t2.push_back(node{t, 2, 1}); int sz1 = t1.size(), sz2 = t2.size(); for (int i = 0; i <= sz2 - 1; ++i) ans.push_back(t2[i]); for (int i = 0; i <= sz1 - 1; ++i) ans.push_back(t1[i]); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i <= n - 1; ++i) scanf( %d , &a[0][i]); for (int i = 0; i <= n - 1; ++i) scanf( %d , &a[1][i]); for (int i = 2 * n - 1; i >= n; --i) scanf( %d , &a[1][i]); for (int i = 2 * n - 1; i >= n; --i) scanf( %d , &a[0][i]); if (!judge()) return puts( -1 ), 0; for (int i = 0; i <= 2 * n - 1; ++i) if (!a[1][i]) { s = i; break; } while (k) { turn(); park(); s = (s + 1) % (2 * n); } int sz = ans.size(); printf( %d n , sz); for (int i = 0; i < sz; ++i) { if (ans[i].x == 3 || ans[i].x == 4) ans[i].y = n - ans[i].y + 1; printf( %d %d %d n , ans[i].id, ans[i].x, ans[i].y); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; vector<long long> a(k); for (int h = 0; h < a.size(); h++) { cin >> a[h]; }; int gg = max_element(a.begin(), a.end()) - a.begin(); for (int i = k - 1; i > gg; i--) { if (a[i] > a[i - 1]) { cout << no ; return 0; } } for (int i = 0; i < gg; i++) { if (a[i] > a[i + 1]) { cout << no ; return 0; } } cout << YES ; }
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#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const long long Inf = 1e18; const int N = 2e5 + 10; const int mod = 0; long long gi() { long long x = 0, o = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } template <typename T> bool chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; }; template <typename T> bool chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; }; int add(int a, int b) { return a + b >= mod ? a + b - mod : a + b; } int sub(int a, int b) { return a - b < 0 ? a - b + mod : a - b; } void inc(int &a, int b) { a = (a + b >= mod ? a + b - mod : a + b); } void dec(int &a, int b) { a = (a - b < 0 ? a - b + mod : a - b); } int n, x[N], sum[N]; long long a[N], t, b[N]; int main() { cin >> n >> t; for (int i = 1; i <= n; i++) a[i] = gi(); for (int i = 1; i <= n; i++) x[i] = gi(); for (int i = 1; i <= n; i++) { if (x[i] < i) return puts( No ), 0; sum[i]++; sum[x[i]]--; } for (int i = 1; i <= n; i++) { sum[i] += sum[i - 1]; b[i] = a[i] + t; if (sum[i]) b[i] = a[i + 1] + t; chkmax(b[i], b[i - 1] + 1); } for (int i = 1; i <= n; i++) if (x[i] != n && b[x[i]] >= a[x[i] + 1] + t) return puts( No ), 0; puts( Yes ); for (int i = 1; i <= n; i++) printf( %lld , b[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; constexpr int LOGMAX = 31 - __builtin_clz(MAX) + 5; int N; char T[MAX]; int sa[MAX], tsa[MAX], ra[MAX], tra[MAX]; int lcp[MAX], plcp[MAX], phi[MAX], c[MAX], st[LOGMAX][MAX]; long long pref[MAX]; void sort(int k) { memset(c, 0, sizeof c); for (int i = int(0); i < int(N); i++) { c[i + k < N ? ra[i + k] : 0]++; } int sum = 0, maxi = max(300, N); for (int i = int(0); i < int(maxi); i++) { int t = c[i]; c[i] = sum; sum += t; } for (int i = int(0); i < int(N); i++) { int cur = sa[i] + k < N ? ra[sa[i] + k] : 0; tsa[c[cur]++] = sa[i]; } memcpy(sa, tsa, sizeof(int) * N); } void build_sa() { for (int i = int(0); i < int(N); i++) { ra[i] = T[i]; sa[i] = i; } for (int k = 1; k < N; k *= 2) { sort(k); sort(0); int r = tra[sa[0]] = 0; for (int i = int(1); i < int(N); i++) { if (ra[sa[i]] == ra[sa[i - 1]]) { int cur = (sa[i] + k) < N ? ra[sa[i] + k] : 0; int prev = (sa[i - 1] + k) < N ? ra[sa[i - 1] + k] : 0; if (cur == prev) { tra[sa[i]] = r; } else { tra[sa[i]] = ++r; } } else { tra[sa[i]] = ++r; } } if (tra[sa[N - 1]] == N - 1) { break; } memcpy(ra, tra, sizeof(int) * N); } } void build_lcp() { phi[sa[0]] = -1; for (int i = int(1); i < int(N); i++) { phi[sa[i]] = sa[i - 1]; } int l = 0; for (int i = int(0); i < int(N); i++) { if (phi[i] == -1) { plcp[i] = 0; continue; } while (T[i + l] == T[phi[i] + l]) { l++; } plcp[i] = l; l = max(l - 1, 0); } for (int i = int(0); i < int(N); i++) { lcp[i] = plcp[sa[i]]; } } inline long long in_range(int left, int right) { return pref[right] - pref[left - 1]; } inline int min_query(int left, int right) { int sz = right - left + 1; int lg = 31 - __builtin_clz(sz); return min(st[lg][left], st[lg][right - (1 << lg) + 1]); } string roll(int l, int r, int len, long long k) { int left = l + 1, right = r; int edge = l; while (left <= right) { int mid = (left + right) / 2; if (min_query(l + 1, mid) >= len) { edge = mid; left = mid + 1; } else { right = mid - 1; } } long long total = in_range(l, edge) - 1LL * (len - 1) * (edge - l + 1); if (total < k) { return roll(edge + 1, r, len, k - total); } else if (k > (edge - l + 1)) { return roll(l, r, len + 1, k - (edge - l + 1)); } int pos = l + k - 1; string ans = ; for (int i = int(0); i < int(len); i++) { ans += T[sa[pos] + i]; } return ans; } int main() { scanf( %s , T); N = strlen(T); long long k; scanf( %lld , &k); if ((1LL * N * (N + 1)) / 2 < k) { puts( No such line. ); return 0; } T[N++] = $ ; build_sa(); build_lcp(); for (int i = int(1); i < int(N); i++) { pref[i] = pref[i - 1] + N - sa[i] - 1; st[0][i] = lcp[i]; } for (int i = int(1); i < int(LOGMAX); i++) { for (int j = 1; j + (1 << i) - 1 < N; j++) { st[i][j] = min(st[i - 1][j], st[i - 1][j + (1 << (i - 1))]); } } printf( %s n , roll(1, N - 1, 1, k).c_str()); return 0; }
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#include <bits/stdc++.h> using namespace std; int64_t pre[200001]; int64_t dp[200001]; int n; int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> pre[i]; pre[i] += pre[i - 1]; } int64_t mx = -1e15; for (int i = n - 1; i >= 1; --i) { dp[i] = max(pre[n], mx); mx = max(mx, pre[i] - dp[i]); } cout << dp[1] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; void MAIN(); int main() { MAIN(); return 0; } const int N = (int)1e5 + 32; char s[N]; int n; void MAIN() { scanf( %d , &n); scanf( %s , s); vector<int> cnt(26, 0); for (int i = 0; i < int(n); i++) cnt[s[i] - A ]++; int ma = 0, nma = 0; for (int i = 0; i < int(26); i++) { if (cnt[i] > ma) { ma = cnt[i]; nma = 1; } else if (cnt[i] == ma) nma++; } int res = 1; for (int i = 0; i < int(n); i++) res = 1LL * res * nma % MOD; printf( %d n , res); }
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#include <bits/stdc++.h> using namespace std; int main() { long long n = 0, m = 0; cin >> n >> m; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (i % 2 == 0) cout << # ; else if ((j == m - 1 && (i - 1) % 4 == 0) || (j == 0 && (i + 1) % 4 == 0)) cout << # ; else cout << . ; } cout << endl; } return 0; }
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: txfifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module txfifo_packet_composer #(
parameter DATA_WIDTH=64,
parameter LOCAL_FIFO_DEPTH=256
) (
clock,
aclr,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam FIFO_ADDR_WIDTH=log2(LOCAL_FIFO_DEPTH);
input clock;
input aclr;
input [DATA_WIDTH-1:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [DATA_WIDTH-1:0] q;
output [FIFO_ADDR_WIDTH-1:0] usedw;
wire [FIFO_ADDR_WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [DATA_WIDTH-1:0] sub_wire3;
wire sub_wire4;
wire [FIFO_ADDR_WIDTH-1:0] usedw = sub_wire0[FIFO_ADDR_WIDTH-1:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [DATA_WIDTH-1:0] q = sub_wire3[DATA_WIDTH-1:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.aclr (aclr),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = LOCAL_FIFO_DEPTH/2,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = LOCAL_FIFO_DEPTH,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = FIFO_ADDR_WIDTH,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; vector<char> cc; void solve() { int n, m, k, d = 0; cin >> n >> m >> k; vector<string> arr(n), ans(n); for (int i = 0; i < n; i++) { cin >> arr[i]; ans[i].resize(m); for (int j = 0; j < m; j++) d += (arr[i][j] == R ); } vector<int> cnt; for (int i = 0; i < k - d % k; i++) cnt.push_back(d / k); for (int i = 0; i < d % k; i++) cnt.push_back(d / k + 1); vector<int> have(k); int ptr = 0; for (int i = 0; i < n; i++) { if (i % 2 == 0) { for (int j = 0; j < m; j++) { char cur = cc[ptr]; ans[i][j] = cur; have[ptr] += (arr[i][j] == R ); if (have[ptr] == cnt[ptr] && ptr < k - 1) ptr++; } } else { for (int j = m - 1; j >= 0; j--) { char cur = cc[ptr]; ans[i][j] = cur; have[ptr] += (arr[i][j] == R ); if (have[ptr] == cnt[ptr] && ptr < k - 1) ptr++; } } } for (int i = 0; i < n; i++) cout << ans[i] << n ; } int main() { srand(1373737); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); for (char c = 0 ; c <= 9 ; c++) cc.push_back(c); for (char c = a ; c <= z ; c++) cc.push_back(c); for (char c = A ; c <= Z ; c++) cc.push_back(c); int t; cin >> t; while (t--) solve(); return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board ADV7181 video chip.*
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_adv7181 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter INPUT_CONTROL = 16'h0040;
parameter CHROMA_GAIN_1 = 16'h2df4;
parameter CHROMA_GAIN_2 = 16'h2e00;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Video Config Data
10 : data <= {8'h40, 16'h1500};
11 : data <= {8'h40, 16'h1741};
12 : data <= {8'h40, 16'h3a16};
13 : data <= {8'h40, 16'h5004};
14 : data <= {8'h40, 16'hc305};
15 : data <= {8'h40, 16'hc480};
16 : data <= {8'h40, 16'h0e80};
17 : data <= {8'h40, 16'h5004};
18 : data <= {8'h40, 16'h5218};
19 : data <= {8'h40, 16'h58ed};
20 : data <= {8'h40, 16'h77c5};
21 : data <= {8'h40, 16'h7c93};
22 : data <= {8'h40, 16'h7d00};
23 : data <= {8'h40, 16'hd048};
24 : data <= {8'h40, 16'hd5a0};
25 : data <= {8'h40, 16'hd7ea};
26 : data <= {8'h40, 16'he43e};
27 : data <= {8'h40, 16'hea0f};
28 : data <= {8'h40, 16'h3112};
29 : data <= {8'h40, 16'h3281};
30 : data <= {8'h40, 16'h3384};
31 : data <= {8'h40, 16'h37A0};
32 : data <= {8'h40, 16'he580};
33 : data <= {8'h40, 16'he603};
34 : data <= {8'h40, 16'he785};
35 : data <= {8'h40, 16'h5004};
36 : data <= {8'h40, 16'h5100};
37 : data <= {8'h40, INPUT_CONTROL};
38 : data <= {8'h40, 16'h1000};
39 : data <= {8'h40, 16'h0402};
40 : data <= {8'h40, 16'h0860};
41 : data <= {8'h40, 16'h0a18};
42 : data <= {8'h40, 16'h1100};
43 : data <= {8'h40, 16'h2b00};
44 : data <= {8'h40, 16'h2c8c};
45 : data <= {8'h40, CHROMA_GAIN_1};
46 : data <= {8'h40, CHROMA_GAIN_2};
47 : data <= {8'h40, 16'h2ff4};
48 : data <= {8'h40, 16'h30d2};
49 : data <= {8'h40, 16'h0e05};
default : data <= {8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, INF = 1e9; bool check(int n, string s) { for (int i = 1; i <= n; i++) if (s[i] == 0 ) return false; cout << 1 << << n - 1 << << 2 << << n << endl; return true; } void sol(int n, string s) { for (int i = 1; i <= n; i++) if (s[i] == 0 ) { if (i - 1 >= n / 2) cout << 1 << << i << << 1 << << i - 1 << endl; else cout << i << << n << << i + 1 << << n << endl; return; } } int main() { cin.tie(0); ios::sync_with_stdio(false); int t; cin >> t; while (t--) { int n; string s; cin >> n >> s; s = # + s; if (!check(n, s)) sol(n, s); } return 0; }
|
module memorytestbench;
parameter sim_time = 750*2; // Num of Cycles * 2
wire MFC;
wire [31:0] MEMDAT;
reg [31:0] MEMDAT_BUFF;
reg MFA,READ_WRITE,WORD_BYTE, Reset ,Clk;
reg [7:0] MEMADD;
assign MEMDAT = MEMDAT_BUFF;
//module memory (inout reg[31:0] Data, output reg MFC, input MFA, ReadWrite, input [7:0] Address, input wordByte, Reset);
memory mem( MEMDAT, MFC, MFA, READ_WRITE, MEMADD, WORD_BYTE, Reset);
initial fork
Reset =1; Clk = 0; MEMADD=0;MFA=0;MEMADD=0; MEMDAT_BUFF = 32'hzzzz_zzzz;
#1 Reset = 0;
#50 MEMADD = 0 ; #50 READ_WRITE =1 ; #50 WORD_BYTE = 0 ; #50 MFA = 1;
#70 MFA = 0;
#100 MEMADD = 0 ; #100 READ_WRITE =0 ; #100 WORD_BYTE = 0 ; #100 MFA = 1; #100 MEMDAT_BUFF = 32'hAAAA_AAAA;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("memorytestbench.vcd");
$dumpvars(0,memorytestbench);
$display(" Test Results" );
//$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog MEM_256B.v MEM_256B_TEST.v
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3452; vector<int> G[maxn]; pair<int, int> snd[maxn][maxn]; int size[maxn][maxn]; long long f[maxn][maxn]; int n, cur, nxt; void dfs(int p, int fl = -1) { if (fl == cur) { nxt = p; } size[cur][p] = 1; snd[cur][p] = make_pair(nxt, fl); for (auto t : G[p]) { if (t == fl) { continue; } dfs(t, p); size[cur][p] += size[cur][t]; } } long long dp(int x, int y) { if (x == y) { return 0; } pair<int, int> path = snd[x][y]; long long sum = (long long)size[x][y] * size[y][x]; long long &v = f[x][y]; if (v != -1) { return v; } long long l = dp(path.first, y) + sum; long long r = dp(x, path.second) + sum; return v = max(l, r); } int main() { cin >> n; for (int i = 1; i < (n); i++) { int x, y; cin >> x >> y; G[x].push_back(y); G[y].push_back(x); } for (int i = 1; i <= (n); i++) { cur = i; nxt = -1; dfs(i); } memset(f, -1, sizeof(f)); long long ans = 0; for (int i = 1; i <= (n); i++) { for (int j = 1; j < (i); j++) { ans = max(ans, dp(i, j)); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[2][2]; cin >> a[0][0] >> a[0][1] >> a[1][0] >> a[1][1]; int n[2]; if (!a[0][0] && !a[1][0] && !a[0][1] && !a[1][1]) { cout << 0 ; return 0; } for (int i = 0; 1; i++) { int temp = i * (i - 1) / 2; if (temp == a[0][0]) { n[0] = i; break; } if (temp > a[0][0]) { cout << Impossible ; return 0; } } for (int i = 0; 1; i++) { int temp = i * (i - 1) / 2; if (temp == a[1][1]) { n[1] = i; break; } if (temp > a[1][1]) { cout << Impossible ; return 0; } } if (n[0] == 0) if (a[0][1] || a[1][0]) n[0] = 1; if (n[1] == 0) if (a[0][1] || a[1][0]) n[1] = 1; if ((a[0][1] + a[1][0]) != n[0] * n[1]) { cout << Impossible ; return 0; } int base = n[1]; while (1) { if (a[0][1] > base) { cout << 0 ; n[0]--; a[0][1] -= base; } else { for (int i = 0; i < base - a[0][1]; ++i) cout << 1 ; if (n[0] > 0) { cout << 0 ; n[0]--; } for (int i = 0; i < a[0][1]; ++i) cout << 1 ; for (int i = 0; i < n[0]; ++i) cout << 0 ; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long modexp(long long a, long long n) { if (a == 0) return 0; if (n == 0) return 1; long long p = modexp(a, n / 2); p = p * p % MOD; if (n & 1) p = p * a % MOD; return p; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, m, l, r; cin >> n >> m >> l >> r; long long k = r + 1 - l; long long e = n * m % (MOD - 1); long long ans = modexp((k % MOD + MOD) % MOD, e); if (n % 2 == 0 || m % 2 == 0) { long long k0 = 0, k1 = 0; if (l % 2 == 0 && r % 2 == 0) ++k0; if (l % 2 == 1 && r % 2 == 1) ++k1; ans = (ans + modexp((k0 + MOD - k1) % MOD, e)) % MOD; ans = (ans * modexp(2, MOD - 2)) % MOD; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int a[1505]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= i - 1; j++) if (a[j] > a[i]) ans ^= 1; int q; scanf( %d , &q); while (q--) { int a, b; scanf( %d%d , &a, &b); int sz = b - a + 1; sz = sz * (sz - 1) / 2; if (sz % 2 == 1) ans ^= 1; if (ans == 0) printf( even n ); else printf( odd n ); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:50:10 11/03/2014
// Design Name:
// Module Name: Output_2_Disp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Multi_8CH32(input clk,
input rst,
input EN, //Write EN
input[2:0]Test, //ALU&Clock,SW[7:5]
input[63:0]point_in, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öСÊýµã
input[63:0]LES, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öÉÁ˸λ
input[31:0] Data0, //disp_cpudata
input[31:0] data1,
input[31:0] data2,
input[31:0] data3,
input[31:0] data4,
input[31:0] data5,
input[31:0] data6,
input[31:0] data7,
output [7:0] point_out,
output [7:0] LE_out,
output [31:0]Disp_num
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_sincos_s5_double(clock, resetn, enable, dataa, result_a, result_b);
// This is a module intended for Stratix IV family
// Latency = 52.
input clock, resetn, enable;
input [63:0] dataa;
output [63:0] result_a; // sin
output [63:0] result_b; // cos
FPSinCosXDPS5f375 core(
.xIn_v(1'b1),
.xIn_c(8'd0),
.xIn_0(dataa),
.en(enable),
.xOut_v(),
.xOut_c(),
.xOut_0(result_a),
.xOut_1(result_b),
.clk(clock),
.areset(~resetn));
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* CPU data bus to OCP bus wrapper
*/
`include "common.vh"
`include "ocp_const.vh"
/* CPU DBus-to-OCP */
module dbus2ocp(
/* CPU port */
i_DAddr,
i_DCmd,
i_DRnW,
i_DBen,
i_DData,
o_DData,
o_DRdy,
o_DErr,
/* OCP port */
o_MAddr,
o_MCmd,
o_MData,
o_MByteEn,
i_SCmdAccept,
i_SData,
i_SResp
);
/* CPU port */
input wire [`ADDR_WIDTH-1:0] i_DAddr;
input wire i_DCmd;
input wire i_DRnW;
input wire [`BEN_WIDTH-1:0] i_DBen;
input wire [`DATA_WIDTH-1:0] i_DData;
output reg [`DATA_WIDTH-1:0] o_DData;
output reg o_DRdy;
output reg o_DErr;
/* OCP port */
output reg [`ADDR_WIDTH-1:0] o_MAddr;
output reg [2:0] o_MCmd;
output reg [`DATA_WIDTH-1:0] o_MData;
output reg [`BEN_WIDTH-1:0] o_MByteEn;
input wire i_SCmdAccept; /* Not used */
input wire [`DATA_WIDTH-1:0] i_SData;
input wire [1:0] i_SResp;
always @(*)
begin
o_MAddr = i_DAddr;
o_MCmd = (i_DCmd ? (i_DRnW ? `OCP_CMD_READ : `OCP_CMD_WRITE) : `OCP_CMD_IDLE);
o_MByteEn = i_DBen;
o_MData = i_DData;
o_DData = i_SData;
o_DRdy = (i_SResp != `OCP_RESP_NULL ? 1'b1 : 1'b0);
o_DErr = (i_SResp == `OCP_RESP_ERR || i_SResp == `OCP_RESP_FAIL ? 1'b1 : 1'b0);
end
endmodule /* dbus2ocp */
|
`timescale 1us/100ns
module top;
reg pass = 1'b1;
reg [3:0] ia = 4'd1;
wire signed [3:0] iconstp, iconstm, isfunc, iufunc;
wire [7:0] istring;
/* Integer constant value. */
assign #1 iconstp = 2; // 2
assign #1 iconstm = -2; // -2
assign #1 istring = "0"; // "0"
/* Integer System Function. */
assign #1 isfunc = $rtoi(2.0); // 2
/* Integer User Function. */
assign #1 iufunc = int_func(ia); // 2
initial begin
// $monitor($realtime,, iconstp,, iconstm,, istring,, iufunc,, isfunc);
#0.9;
if (iconstp !== 4'bz) begin
pass = 1'b0;
$display("Integer: constant (positive) value not delayed.");
end
if (iconstm !== 4'bz) begin
pass = 1'b0;
$display("Integer: constant (negative) value not delayed.");
end
if (istring !== 8'bz) begin
pass = 1'b0;
$display("Integer: string value not delayed.");
end
if (isfunc !== 4'bz) begin
pass = 1'b0;
$display("Integer: system function value not delayed.");
end
if (iufunc !== 4'bz) begin
pass = 1'b0;
$display("Integer: user function value not delayed.");
end
#0.1;
#0;
if (iconstp !== 2) begin
pass = 1'b0;
$display("Integer: constant (positive) value not delayed correctly.");
end
if (iconstm !== -2) begin
pass = 1'b0;
$display("Integer: constant (negative) value not delayed correctly.");
end
if (istring !== "0") begin
pass = 1'b0;
$display("Integer: string value not delayed correctly.");
end
if (isfunc !== 2) begin
pass = 1'b0;
$display("Integer: system function value not delayed correctly.");
end
if (iufunc !== 2) begin
pass = 1'b0;
$display("Integer: user function value not delayed correctly.");
end
if (pass) $display("PASSED");
end
function [31:0] int_func;
input [31:0] in;
int_func = in * 2;
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); long long n, i, j, k, l, m, arr[100010], arr1[100010], x, y; double a, b, c, d, p, t; cin >> n; for (i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); reverse(arr, arr + n); arr1[0] = arr[0]; for (i = 1; i < n; i++) arr1[i] = arr1[i - 1] + arr[i]; m = 9999999999; for (i = 0; i < n - 1; i++) m = min(abs(abs(arr1[n - 1] - arr1[i]) - arr1[i]) + 1, m); cout << m; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:13:49 05/12/2015
// Design Name:
// Module Name: sbox8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox8(
Bin,
BSout
);
input [6:1] Bin;
output reg [4:1] BSout;
wire [6:1] offset;
assign offset = {Bin[6], Bin[1], Bin[5 : 2]};
always @(offset)
begin
case (offset)
6'b000000: BSout <= 4'd13;
6'b000001: BSout <= 4'd2;
6'b000010: BSout <= 4'd8;
6'b000011: BSout <= 4'd4;
6'b000100: BSout <= 4'd6;
6'b000101: BSout <= 4'd15;
6'b000110: BSout <= 4'd11;
6'b000111: BSout <= 4'd1;
6'b001000: BSout <= 4'd10;
6'b001001: BSout <= 4'd9;
6'b001010: BSout <= 4'd3;
6'b001011: BSout <= 4'd14;
6'b001100: BSout <= 4'd5;
6'b001101: BSout <= 4'd0;
6'b001110: BSout <= 4'd12;
6'b001111: BSout <= 4'd7;
6'b010000: BSout <= 4'd1;
6'b010001: BSout <= 4'd15;
6'b010010: BSout <= 4'd13;
6'b010011: BSout <= 4'd8;
6'b010100: BSout <= 4'd10;
6'b010101: BSout <= 4'd3;
6'b010110: BSout <= 4'd7;
6'b010111: BSout <= 4'd4;
6'b011000: BSout <= 4'd12;
6'b011001: BSout <= 4'd5;
6'b011010: BSout <= 4'd6;
6'b011011: BSout <= 4'd11;
6'b011100: BSout <= 4'd0;
6'b011101: BSout <= 4'd14;
6'b011110: BSout <= 4'd9;
6'b011111: BSout <= 4'd2;
6'b100000: BSout <= 4'd7;
6'b100001: BSout <= 4'd11;
6'b100010: BSout <= 4'd4;
6'b100011: BSout <= 4'd1;
6'b100100: BSout <= 4'd9;
6'b100101: BSout <= 4'd12;
6'b100110: BSout <= 4'd14;
6'b100111: BSout <= 4'd2;
6'b101000: BSout <= 4'd0;
6'b101001: BSout <= 4'd6;
6'b101010: BSout <= 4'd10;
6'b101011: BSout <= 4'd13;
6'b101100: BSout <= 4'd15;
6'b101101: BSout <= 4'd3;
6'b101110: BSout <= 4'd5;
6'b101111: BSout <= 4'd8;
6'b110000: BSout <= 4'd2;
6'b110001: BSout <= 4'd1;
6'b110010: BSout <= 4'd14;
6'b110011: BSout <= 4'd7;
6'b110100: BSout <= 4'd4;
6'b110101: BSout <= 4'd10;
6'b110110: BSout <= 4'd8;
6'b110111: BSout <= 4'd13;
6'b111000: BSout <= 4'd15;
6'b111001: BSout <= 4'd12;
6'b111010: BSout <= 4'd9;
6'b111011: BSout <= 4'd0;
6'b111100: BSout <= 4'd3;
6'b111101: BSout <= 4'd5;
6'b111110: BSout <= 4'd6;
6'b111111: BSout <= 4'd11;
default: BSout <= 4'd0;
endcase
end
endmodule
|
/**
* datapath.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "aludefs.v"
module datapath(
/* regular inputs */
input wire [ 7 : 0] immediate, /* instruction predicate */
input wire [ 7 : 0] mdr_in, /* memory data register input */
/* toplevel signals */
input wire clk, /* clock signal */
input wire res, /* reset signal */
/* control signals */
input wire [ 1 : 0] ac_source, /* accumulator source */
input wire write_ac, /* write accumulator */
input wire mar_source, /* memory address register source */
input wire write_mar, /* write memory address register */
input wire [ 1 : 0] mdr_source, /* memory data register source */
input wire write_mdr, /* write memory data register */
input wire write_flags, /* write flags register */
input wire [ 1 : 0] pc_source, /* program counter source */
input wire write_pc, /* write program counter */
input wire [ 2 : 0] ALU_op_select, /* ALU operand source */
input wire [`ALUCTLW - 1: 0] ALUctl, /* ALU control signal bus */
/* output signals */
output wire [ 7 : 0] mar_out, /* memory address */
output wire [ 7 : 0] mdr_out, /* data */
output wire [ 7 : 0] pc_out, /* program counter */
output wire [`FWIDTH - 1 : 0] flags /* ALU flags */
);
/* internal signals */
wire [ 7 : 0] ALU_feedback, /* ALU output and feedback path */
pc_next, /* next program counter */
ac_out, /* accumulator data output */
ac_in, /* accumulator data input */
alu_operand, /* second ALU operand */
mar_data, /* memory address register data source */
mdr_data; /* memory data register data source */
wire [`FWIDTH - 1 : 0] flags_out; /* flags */
/* program counter jump select
* pc_source:
* 00: regular execution
* 01: direct jump
* 10: indirect jump
* 11: jump with offset
* rationale:
* mechanism allows for implementation of both direct jumps
* and indirect jumps.
*/
mux4 #(.WIDTH(8)) pc_mux (
.in0(pc_out + 8'b1),
.in1(immediate),
.in2(ac_out),
.in3(pc_out + ac_out),
.sel(pc_source),
.mux_out(pc_next)
);
/* program counter register */
ff_d #(.WIDTH(8)) pc (
.D(pc_next),
.en(write_pc),
.clk(clk),
.res(res),
.Q(pc_out)
);
/* flags register
* rationale:
* keep ALU flags for new operations/CPU status
*/
ff_d #(.WIDTH(`FWIDTH)) flags_register (
.D(flags_out),
.en(write_flags),
.clk(clk),
.res(res),
.Q(flags)
);
/* accumulator input select:
* ac_source:
* 00: store value in memory address register
* 01: store value in memory data register
* 10: store result from ALU into accumulator
* 11: store immediate into accumulator
* rationale:
* mechanism allows for accumulator behaviour and for loading
* a numeric constant into accumulator.
*/
mux4 #(.WIDTH(8)) ac_mux (
.in0(mar_out),
.in1(mdr_out),
.in2(ALU_feedback),
.in3(immediate),
.sel(ac_source),
.mux_out(ac_in)
);
/* accumulator register */
ff_d #(.WIDTH(8)) ac (
.D(ac_in),
.en(write_ac),
.clk(clk),
.res(res),
.Q(ac_out)
);
/* memory address register data source select
* mar_source:
* 1: use source from immediate constant
* 0: use source from accumulator register
* rationale:
* allows for both direct and indirect addressing of memory data
*/
assign mar_data = mar_source ? immediate : ac_out;
/* memory address register */
ff_d #(.WIDTH(8)) mar (
.D(mar_data),
.en(write_mar),
.clk(clk),
.res(res),
.Q(mar_out)
);
/* memory data register data source select
* mdr_source:
* 00: the constant 0
* 01: memory bus value
* 10: immediate value
* 11: accumulator register
* rationale:
* allows for both direct and indirect
* addressing of memory data
* allows to easily clear a memory address
*/
mux4 #(.WIDTH(8)) mdr_mux (
.in0(8'b0),
.in1(mdr_in),
.in2(immediate),
.in3(ac_out),
.sel(mdr_source),
.mux_out(mdr_data)
);
/* memory data register */
ff_d #(.WIDTH(8)) mdr (
.D(mdr_data),
.en(write_mdr),
.clk(clk),
.res(res),
.Q(mdr_out)
);
/* ALU operand source select
* ALU_op_select:
* 000: the constant 0
* 001: the constant 1
* 010: the constant 2
* 011: the constant -1
* 100: the constant -2
* 101: accumulator register
* 110: immediate constant
* 111: memory data register
* rationale:
* allows for the ease of implementation of
* arithmetic/logic instructions
*/
mux8 #(.WIDTH(8)) ALU_op_mux (
.in0(8'b0),
.in1(8'b01),
.in2(8'b10),
.in3(8'hff),
.in4(8'hfe),
.in5(ac_out),
.in6(immediate),
.in7(mdr_out),
.sel(ALU_op_select),
.mux_out(alu_operand)
);
/* ALU */
ALU alu0 (
.op1(ac_out),
.op2(alu_operand),
.ctl(ALUctl),
.flags_in(flags),
.result(ALU_feedback),
.flags_out(flags_out)
);
endmodule
`include "aluundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File : des_comp_gen.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_comp_gen
(
input clk,
input rstn,
input [31:0] dx_fx, // 16.16
input [31:0] dy_fx, // 16.16
input [95:0] cmp_i,
output [31:0] curr_i
);
wire [31:0] ix;
wire [31:0] iy;
wire [31:0] ixy;
flt_fx1616_mult u_flt_fx_mult_dx
(
.clk (clk),
.rstn (rstn),
.fx (dx_fx),
.bfl (cmp_i[63:32]),
.fl (ix)
);
flt_fx1616_mult u_flt_fx_mult_dy
(
.clk (clk),
.rstn (rstn),
.fx (dy_fx),
.bfl (cmp_i[31:0]),
.fl (iy)
);
flt_add_sub u_flt_add_subf_xy
(
.clk (clk),
.sub (1'b0),
.afl (ix),
.bfl (iy),
.fl (ixy)
);
flt_add_sub u_flt_add_subf_curr
(
.clk (clk),
.sub (1'b0),
.afl (cmp_i[95:64]),
.bfl (ixy),
.fl (curr_i)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; long long dp[N][5]; long long DP[N]; int head[N], nex[N * 2], to[N * 2], tot = 0; int n, k; long long ans = 0; void add(int u, int v) { to[++tot] = v; nex[tot] = head[u]; head[u] = tot; } void dfs(int u, int fa, int d) { DP[u] = dp[u][d % k] = 1; for (int i = head[u]; i > 0; i = nex[i]) { int v = to[i]; if (v == fa) continue; dfs(v, u, d + 1); for (int j = 0; j < k; j++) { for (int l = 0; l < k; l++) { ans += (k - (j - d + l - d) % k) % k * dp[u][j] * dp[v][l]; } } for (int i = 0; i < k; i++) dp[u][i] += dp[v][i]; ans += ((long long)n - DP[v]) * DP[v]; DP[u] += DP[v]; } } int main() { while (~scanf( %d%d , &n, &k)) { memset(head, 0, sizeof(head)); memset(dp, 0, sizeof(dp)); memset(DP, 0, sizeof(DP)); tot = 0; for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); add(u, v); add(v, u); } ans = 0; dfs(1, 0, 0); printf( %lld n , ans / k); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long n, k; cin >> n >> k; vector<long long> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } long long ans = 0; unordered_map<int, int> m; for (int r = 0, l = 0; r < n; r++) { m[v[r]]++; while (m[v[r]] >= k) { m[v[l++]]--; } ans += l; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int arr[100] = {0}, con = 0, d = 0; ; string x; cin >> x; for (int i = 0; i < x.size(); i++) { if (x[i] == + ) { for (int j = 0; j < con; j++) { arr[d] += (x[i - j - 1] - 48) * pow(10, j); } d++; con = 0; } else con++; } for (int j = 0; j < con; j++) { arr[d] += (x[x.size() - j - 1] - 48) * pow(10, j); } sort(arr, arr + d + 1); for (int j = 0; j <= d; j++) { if (j == d) cout << arr[j]; else cout << arr[j] << + ; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_adder_subtractor_0_0 -prefix
// affine_block_ieee754_fp_adder_subtractor_0_0_ affine_block_ieee754_fp_adder_subtractor_0_1_stub.v
// Design : affine_block_ieee754_fp_adder_subtractor_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_adder_subtractor,Vivado 2016.4" *)
module affine_block_ieee754_fp_adder_subtractor_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5010; int n, arr[N], ans[(N << 1)]; vector<int> a[N], b[N]; const int inv2 = 500000004; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); } for (int i = n - 2; i >= 0; i--) { a[i].resize((int)a[i + 1].size() + 1); for (int j = 1; j < (int)a[i].size(); j++) { a[i][j] = (long long)a[i + 1][j - 1] * arr[i] % 1000000007; } a[i][0] = arr[i]; } b[0] = a[0]; for (int i = 0; i < (int)b[0].size(); i++) ans[i] = b[0][i]; int cur = arr[0]; for (int i = 1; i < n; i++) { swap(b[i], b[i - 1]); b[i][0]--; if (b[i][0] < 0) b[i][0] += 1000000007; for (int j = 0; j < (int)a[i].size(); j++) { b[i][j + 1] -= a[i][j]; if (b[i][j + 1] < 0) b[i][j + 1] += 1000000007; } b[i].push_back(0); for (int j = (int)b[i].size() - 1; j >= 0; j--) { b[i][j] = b[i][j - 1]; } b[i][0] = 1; for (int j = 0; j < (int)a[i].size(); j++) { b[i][j] += a[i][j]; if (b[i][j] >= 1000000007) b[i][j] -= 1000000007; } for (int j = 0; j < (int)b[i].size(); j++) { ans[j] += (long long)b[i][j] * cur % 1000000007; if (ans[j] >= 1000000007) ans[j] -= 1000000007; } cur = (long long)cur * arr[i] % 1000000007; } for (int i = 1; i <= 2 * n - 2; i++) { if (i > 1) putchar( ); printf( %d , (long long)ans[i - 1] * inv2 % 1000000007); } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef long long LL; typedef pair<int, int> PII; typedef pair<LL,LL> PLL; const int INF = 0x3f3f3f3f, N = 1e5 + 10; inline int lc(int u) {return u << 1;} inline int rc(int u) {return u << 1 | 1;} inline int lowbit(int x) {return x & (-x);} int y[27] = {10010,11020,20011,21012,11011,21021,22022,12021,11011,12012,10120,11130,20121,21122,11121,21131,22132,12131,11121,12122,10221,11231,12113,20222,21223,11222}; char x[30000]; inline void solve() { for (int i = 0; i < 26; i ++ ) { if (x[y[i]] == 0) x[y[i]] = i + a ; } int n; cin >> n; for (int i = 1; i <= n; i ++ ) { int res = 0; for (int j = 0; j < 5; j ++ ) { int tmp; cin >> tmp; res = res * 10 + tmp; } cout << x[res]; } } int main() { // ios::sync_with_stdio(false), cin.tie(nullptr); // int t; cin >> t; // while (t -- ) solve(); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:37:07 03/24/2015
// Design Name:
// Module Name: abc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Latency = 5
module abc(
input clk,
input ce,
input [11:0] a,
input [11:0] b,
input [11:0] c,
output [24:0] y
);
wire signed [12:0] sum_ab;
wire signed [11:0] del_c;
// Latency = 2
delay_line #(
.DELAY(2),
.WIDTH(12)
) delay_c (
.clk(clk),
.ce(ce),
.in(c),
.out(del_c),
.rst(0)
);
// Latency = 2
sum summer_ab (
.a(a), // input [11 : 0] a
.b(b), // input [11 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(sum_ab) // output [12 : 0] s
);
//Latency = 3
mul multiplier_ab_c (
.a(del_c), // input [11 : 0] c
.b(sum_ab), // input [12 : 0] a + b
.clk(clk), // input clk
.ce(ce), // input ce
.p(y) // output [24 : 0] p
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; void dout() { cerr << endl; } template <typename Head, typename... Tail> void dout(Head H, Tail... T) { cerr << H << ; dout(T...); } mt19937 rnd(time(0)); struct Node { Node* left = nullptr; Node* right = nullptr; int prior; int size = 1; double val; double sleft; double sright; double sum; double mss; Node(double v) : prior(rnd()), val(v), sleft(max(0.0, v)), sright(max(0.0, v)), sum(v), mss(max(0.0, v)) {} }; int _size(Node* n) { return n ? n->size : 0; } double _sleft(Node* n) { return n ? n->sleft : 0; } double _sright(Node* n) { return n ? n->sright : 0; } double _sum(Node* n) { return n ? n->sum : 0; } double _mss(Node* n) { return n ? n->mss : 0; } void update(Node* n) { n->size = _size(n->left) + _size(n->right) + 1; n->sum = _sum(n->left) + _sum(n->right) + n->val; n->sleft = max(_sleft(n->left), _sum(n->left) + n->val + _sleft(n->right)); n->sright = max(_sright(n->right), _sum(n->right) + n->val + _sright(n->left)); n->mss = max({_mss(n->left), _mss(n->right), _sright(n->left) + n->val + _sleft(n->right)}); } struct Treap { Node* root = nullptr; pair<Node*, Node*> split(Node* n, int index) { if (!n) return make_pair(nullptr, nullptr); int sz = _size(n->left) + 1; if (index < sz) { auto [l, r] = split(n->left, index); n->left = r; update(n); return make_pair(l, n); } else { auto [l, r] = split(n->right, index - sz); n->right = l; update(n); return make_pair(n, r); } } Node* merge(Node* l, Node* r) { if (!l || !r) return l ? l : r; if (l->prior > r->prior) { l->right = merge(l->right, r); update(l); return l; } else { r->left = merge(l, r->left); update(r); return r; } } void push_back(double v) { root = merge(root, new Node(v)); } double max_subarray_sum(int left, int right) { auto [x, r] = split(root, right); auto [l, m] = split(x, left); double ans = _mss(m); root = merge(l, merge(m, r)); return ans; } }; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m, c; cin >> n >> m >> c; vector<double> x(n); for (int i = 0; i < n; i++) { cin >> x[i]; } vector<double> p(n); for (int i = 1; i < n; i++) { cin >> p[i]; p[i] /= 100.0; } Treap treap; treap.push_back(0); for (int i = 1; i < n; i++) { treap.push_back((x[i] - x[i - 1]) * 0.5 - p[i] * c); } double ans = 0.0; for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; ans += treap.max_subarray_sum(l, r); } cout << fixed << setprecision(9) << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int cnt[(100000 + 10)]; int f[(100000 + 10)]; int main() { int n; cin >> n; int ans = 0; int mx = 0; for (int i = 1; i <= n; i++) { int v; cin >> v; cnt[f[v]]--; f[v]++; cnt[f[v]]++; int ok = 0; mx = max(mx, f[v]); if (cnt[1] == i) { ok = 1; } else if (cnt[mx] == i) { ok = 1; } else if (cnt[mx] * mx == i - 1 && cnt[1] == 1) { ok = 1; } else if (cnt[mx - 1] * (mx - 1) == i - mx && cnt[mx] == 1) { ok = 1; } if (ok) { ans = i; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const int mod = 1000000007; using namespace std; long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } int prime[100007]; void SieveOfEratosthenes(int n) { memset(prime, -1, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == -1) { for (int i = p * p; i <= n; i += p) prime[i] = p; } } } int lps(string s) { int len = 0; int n = s.length(); int dp[n]; dp[0] = 0; for (int i = 1; i < n; i++) { if (s[i] == s[len]) { len++; dp[i] = len; continue; } if (len != 0) { len = dp[len - 1]; i--; continue; } dp[i] = 0; } return dp[n - 1]; } long long power(unsigned long long x, unsigned long long y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } vector<pair<long long, long long>> pFactor; void factorize(long long n) { int count = 0; while (!(n % 2)) { n >>= 1; count++; } if (count) pFactor.push_back({2, count}); for (long long i = 3; i <= sqrt(n); i += 2) { count = 0; while (n % i == 0) { count++; n = n / i; } if (count) pFactor.push_back({i, count}); } if (n > 2) pFactor.push_back({n, 1}); } int dp[405][405]; int solve(int a[], int n, int i, int t) { if (i > n) { return 0; } if (t > 2 * n) { return INT_MAX; } if (dp[i][t] != -1) { return dp[i][t]; } int x = solve(a, n, i + 1, t + 1); if (x != INT_MAX) { x += abs(t - a[i]); } x = min(x, solve(a, n, i, t + 1)); dp[i][t] = x; return x; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int a[n + 1]; for (long long i = 1; i < n + 1; i++) cin >> a[i]; sort(a + 1, a + n + 1); memset(dp, -1, sizeof(dp)); int x = solve(a, n, 1, 1); cout << x << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 112; const long long mod = 1e9 + 7; int R; long long p1, p2, p3, p4, s; int lim[N]; long long F[N][N]; long long ksm(long long a, long long b = mod - 2) { long long ret = 1; for (; b; b >>= 1, a = a * a % mod) if (b & 1) ret = ret * a % mod; return ret; } struct node { long long a[N]; node() { memset(a, 0, sizeof a); } } a[N][N]; node operator*(long long x, node a) { node c; for (int i = 0; i <= 2 * R + 1; i++) c.a[i] = a.a[i] * x % mod; return c; } node operator+(node a, node b) { node c; for (int i = 0; i <= 2 * R + 1; i++) c.a[i] = (a.a[i] + b.a[i]) % mod; return c; } node operator-(node a, node b) { node c; for (int i = 0; i <= 2 * R + 1; i++) c.a[i] = (a.a[i] - b.a[i] + mod) % mod; return c; } void solve() { int n = 2 * R; for (int i = 0; i <= n; i++) { int maxx = i; for (int j = i + 1; j <= n; j++) if (abs(F[j][i]) > abs(F[maxx][i])) maxx = j; swap(F[maxx], F[i]); for (int j = 0; j <= n; j++) { if (j != i) { long long x = F[j][i] * ksm(F[i][i]) % mod; for (int k = i; k <= n + 1; k++) F[j][k] = (F[j][k] - F[i][k] * x) % mod; } } } for (int i = 0; i <= n; i++) F[i][n + 1] = F[i][n + 1] * ksm(F[i][i]) % mod; } int main() { scanf( %d%lld%lld%lld%lld , &R, &p1, &p2, &p3, &p4); s = p1 + p2 + p3 + p4; s = ksm(s); p1 = p1 * s % mod; p2 = p2 * s % mod; p3 = p3 * s % mod; p4 = p4 * s % mod; int T = R + 3; p4 = ksm(p4); for (int i = 0; i <= R; i++) for (int j = 0; j * j + i * i <= R * R; j++) lim[i] = j; for (int j = -R; j <= R + 1; j++) for (int i = -R; i <= R; i++) { int lt = lim[abs(i)]; if (j == -lt) a[i + T][-lt + T].a[i + R] = 1; else if (j > -lt && j <= lt + 1) { a[i + T][j + T] = (a[i + T][j - 1 + T] - p1 * a[i - 1 + T][j - 1 + T] - p2 * a[i + T][j - 2 + T] - p3 * a[i + 1 + T][j - 1 + T]); (a[i + T][j + T].a[2 * R + 1])--; (a[i + T][j + T].a[2 * R + 1]) = (a[i + T][j + T].a[2 * R + 1]) % mod; a[i + T][j + T] = p4 * a[i + T][j + T]; } } for (int i = -R; i <= R; i++) { for (int j = 0; j <= 2 * R + 1; j++) F[i + R][j] = a[i + T][lim[abs(i)] + 1 + T].a[j]; F[i + R][2 * R + 1] = -F[i + R][2 * R + 1]; } solve(); long long ans = 0; for (int i = 0; i <= 2 * R; i++) ans = (ans + a[T][T].a[i] * F[i][2 * R + 1]) % mod; ans = (ans + a[T][T].a[2 * R + 1]) % mod; ans = (ans + mod) % mod; cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { int a, b, c; cin >> a >> b >> c; int ans = (int)1e9; int A = -1, B = -1, C = -1; for (int cA = 1; cA <= 2 * a; cA++) { for (int cB = cA; cB <= 2 * b; cB += cA) { for (int i = 0; i < 2; i++) { int cC = cB * (c / cB) + i * cB; int res = abs(cA - a) + abs(cB - b) + abs(cC - c); if (ans > res) { ans = res; A = cA; B = cB; C = cC; } } } } cout << ans << n << A << << B << << C << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int t, n; cin >> t; string s; for (int k = 0; k < t; k++) { cin >> n; cin >> s; if (s.size() == 2) { if (s[0] < s[1]) { cout << YES << n ; cout << 2 << n ; cout << s[0] << << s[1] << endl; } else cout << NO << n ; } else { cout << YES << n ; cout << 2 << n ; cout << s[0] << ; for (int i = 1; i < s.size(); i++) cout << s[i]; cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; bool SR(int &_x) { return scanf( %d , &_x) == 1; } bool SR(long long &_x) { return scanf( %lld , &_x) == 1; } bool SR(double &_x) { return scanf( %lf , &_x) == 1; } bool SR(char *_s) { return scanf( %s , _s) == 1; } bool RI() { return true; } template <typename I, typename... T> bool RI(I &_x, T &..._tail) { return SR(_x) && RI(_tail...); } void SP(const int _x) { printf( %d , _x); } void SP(const long long _x) { printf( %lld , _x); } void SP(const double _x) { printf( %.16lf , _x); } void SP(const char *s) { printf( %s , s); } void PL() { puts( ); } template <typename I, typename... T> void PL(const I _x, const T... _tail) { SP(_x); if (sizeof...(_tail)) putchar( ); PL(_tail...); } const int maxn = 55; struct Solver { int wid, hei; char mp[maxn][maxn]; void rot(int x, int y) { if (mp[x][y] == L ) { for (int i : {x, x + 1}) for (int j : {y, y + 1}) mp[i][j] = UD [i - x]; } else { for (int i : {x, x + 1}) for (int j : {y, y + 1}) mp[i][j] = LR [j - y]; } } vector<pair<int, int> > solve() { assert(wid % 2 == 0); vector<pair<int, int> > ret; for (int i = 0; i < int(hei); i++) for (int j = 0; j < wid; j += 2) { vector<pair<int, int> > cur; int x = i, y = j, f = 0; while (1) { if ((f == 0 && mp[x][y] == L ) || (f == 1 && mp[x][y] == U )) break; cur.push_back({x, y}); if (f == 0) y++; else x++; f ^= 1; } reverse((cur).begin(), (cur).end()); for (auto p : cur) rot(p.first, p.second); ret.insert(ret.end(), (cur).begin(), (cur).end()); } return ret; } } sol0, sol1; int n, m; char f0[maxn][maxn], f1[maxn][maxn]; void read() { RI(n, m); for (int i = 0; i < int(n); i++) RI(f0[i]); for (int i = 0; i < int(n); i++) RI(f1[i]); } bool flip; void build() { if (m % 2) { flip = 1; auto rev = [&](char c) { if (c == L ) return U ; if (c == R ) return D ; if (c == U ) return L ; if (c == D ) return R ; assert(0); }; { sol0.hei = m; sol0.wid = n; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) sol0.mp[j][i] = rev(f0[i][j]); sol1.hei = m; sol1.wid = n; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) sol1.mp[j][i] = rev(f1[i][j]); } } else { sol0.hei = n; sol0.wid = m; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) sol0.mp[i][j] = f0[i][j]; sol1.hei = n; sol1.wid = m; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) sol1.mp[i][j] = f1[i][j]; } } void sol() { auto res0 = sol0.solve(), res1 = sol1.solve(); reverse((res1).begin(), (res1).end()); res0.insert(res0.end(), (res1).begin(), (res1).end()); if (flip) for (auto &p : res0) swap(p.first, p.second); PL(((int)(res0).size())); for (auto p : res0) PL(p.first + 1, p.second + 1); } int main() { read(); build(); sol(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } const int N = 1e2 + 9; char s[N], t[N]; int dp[N][N], sz, n, k, par[N], pw[N]; pair<int, int> way[N][N]; int mod(long long x) { while (x < 0) x += 1000000007; return (x % 1000000007); } int get(int x, int y) { if (x > y) return 0; return mod(par[y] - mod(par[x - 1] * 1LL * pw[y - x + 1])); } int rec(int x, int y) { if (x > sz) { if (t[x - sz] == 1 and y != sz) return 0; if (t[x - sz] == 0 and y == sz) return 0; } if (x > n) return 1; int& ret = dp[x][y]; if (~ret) return ret; ret = 0; for (int i = 0; i < k; i++) { int len = 0; for (int j = min(y + 1, sz); j >= 1; j--) if (mod(get(y - j + 2, y) * 27LL + i + 1) == par[j]) { len = j; break; } if (rec(x + 1, len)) { way[x][y] = make_pair(i, len); return ret = 1; } } return 0; } int main() { memset(dp, -1, sizeof dp); scanf( %d%d , &n, &k); scanf( %s , s + 1); sz = strlen(s + 1); pw[0] = 1; for (int i = 1; i <= sz; i++) { par[i] = mod(par[i - 1] * 27LL + (s[i] - a + 1)); pw[i] = mod(pw[i - 1] * 27LL); } scanf( %s , t + 1); if (!rec(1, 0)) return 0 * puts( No solution ); int now = 0; for (int i = 1; i <= n; i++) { printf( %c , char(way[i][now].first + 97)); now = way[i][now].second; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; for (int i = 0; i < t; i++) { int x, y, a, b; cin >> x >> y >> a >> b; if ((y - x) % (a + b) == 0) { cout << (y - x) / (a + b) << n ; } else { cout << -1 << n ; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, h, m, l, r, x; cin >> n >> h >> m; vector<int> v(n, h); for (int i = 0; i < m; i++) { cin >> l >> r >> x; for (int j = l - 1; j < r; j++) { v[j] = min(v[j], x); } } long long sum = 0; for (int i = 0; i < v.size(); i++) { sum = sum + (v[i] * v[i]); } cout << sum << n ; return 0; }
|
`include "constants.vh"
`default_nettype none
module true_dualport_ram #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
)
(
input wire clka,
input wire [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input wire [DATALEN-1:0] wdataa,
input wire wea,
input wire clkb,
input wire [ADDRLEN-1:0] addrb,
output reg [DATALEN-1:0] rdatab,
input wire [DATALEN-1:0] wdatab,
input wire web
);
reg [DATALEN-1:0] mem [0:DEPTH-1];
always @ (posedge clka) begin
rdataa <= mem[addra];
if (wea) begin
mem[addra] <= wdataa;
end
end
always @ (posedge clkb) begin
rdatab <= mem[addrb];
if (web) begin
mem[addrb] <= wdatab;
end
end
endmodule // true_dualport_ram
module true_dualport_ram_clear #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
)
(
input wire clka,
input wire [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input wire [DATALEN-1:0] wdataa,
input wire wea,
input wire clkb,
input wire [ADDRLEN-1:0] addrb,
output reg [DATALEN-1:0] rdatab,
input wire [DATALEN-1:0] wdatab,
input wire web,
input wire clear
);
reg [DATALEN-1:0] mem [0:DEPTH-1];
integer i;
always @ (*) begin
if (clear) begin
for (i=0; i<DEPTH; i=i+1)
mem[i] = 0;
end
end
always @ (posedge clka) begin
rdataa <= mem[addra];
if (wea) begin
mem[addra] <= wdataa;
end
end
always @ (posedge clkb) begin
rdatab <= mem[addrb];
if (web) begin
mem[addrb] <= wdatab;
end
end
endmodule // true_dualport_ram
`default_nettype wire
|
//sata_link_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module sata_link_layer (
input rst, //reset
input clk,
//Command Interface
output link_layer_ready,
input sync_escape,
output post_align_write,
input hold,
//Phy Layer
input phy_ready,
output write_ready,
input platform_ready,
//XXX: I probably need some feedback to indicate that there is room to write
output [31:0] tx_dout,
output tx_isk,
input [31:0] rx_din,
input [3:0] rx_isk,
input write_start,
output write_strobe,
input [31:0] write_data,
input [31:0] write_size,
input write_hold,
output write_finished,
input write_abort,
output read_start,
output read_strobe,
output [31:0] read_data,
input read_ready,
output read_finished,
output read_crc_ok,
output remote_abort,
output xmit_error,
output wsize_z_error,
input prim_scrambler_en,
input data_scrambler_en,
input is_device,
output [3:0] lax_i_state,
output [3:0] lax_r_state,
output [3:0] lax_w_state,
output [3:0] lax_w_fstate,
//Detection
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_ok,
output detect_r_err,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_align,
output detect_preq_s,
output detect_preq_p,
output detect_xrdy_xrdy,
output send_crc,
output dbg_send_holda,
output [23:0] in_data_addra,
output [12:0] d_count,
output [12:0] write_count,
output [3:0] buffer_pos
);
//Parameters
parameter NOT_READY = 4'h0;
parameter IDLE = 4'h1;
parameter PM_DENY = 4'h2;
//Registers/Wires
reg [3:0] state;
//Primatives
reg send_sync;
reg send_pmack;
reg send_pmnack;
wire sli_idle;
wire [31:0] sli_tx_dout;
wire sli_tx_isk;
reg write_en;
wire write_idle;
wire [31:0] slw_tx_dout;
wire slw_tx_isk;
reg read_en;
wire read_idle;
wire [31:0] slr_tx_dout;
wire slr_tx_isk;
wire [31:0] ll_tx_dout;
wire ll_tx_isk;
wire last_prim;
//Submodules
//XXX: I can probably use only one CRC checker for the entire stack but to make it easier I'm gonna use two for
//the read and write path
//XXX: maybe add a scrambler for PRIM scrambling
cont_controller ccon (
.rst (rst ),
.clk (clk ),
.phy_ready (phy_ready ),
.xmit_cont_en (prim_scrambler_en ),
.last_prim (last_prim ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.ll_tx_din (ll_tx_dout ),
.ll_tx_isk (ll_tx_isk ),
.cont_tx_dout (tx_dout ),
.cont_tx_isk (tx_isk ),
.detect_sync (detect_sync ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_preq_s (detect_preq_s ),
.detect_preq_p (detect_preq_p ),
.detect_align (detect_align ),
.detect_xrdy_xrdy (detect_xrdy_xrdy )
);
sata_link_layer_write slw (
.rst (rst ),
.clk (clk ),
.en (write_en ),
.idle (write_idle ),
.phy_ready (phy_ready ),
.write_ready (write_ready ),
.send_sync_escape (sync_escape ),
.detect_x_rdy (detect_x_rdy ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_sync (detect_sync ),
.detect_align (detect_align ),
.send_holda (dbg_send_holda ),
.write_start (write_start ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.write_size (write_size ),
.write_hold (write_hold ),
.write_finished (write_finished ),
.write_abort (write_abort ),
.last_prim (last_prim ),
.send_crc (send_crc ),
.post_align_write (post_align_write ),
.tx_dout (slw_tx_dout ),
.tx_isk (slw_tx_isk ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.xmit_error (xmit_error ),
.wsize_z_error (wsize_z_error ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.state (lax_w_state ),
.fstate (lax_w_fstate ),
.in_data_addra (in_data_addra ),
.write_count (write_count ),
.d_count (d_count ),
.buffer_pos (buffer_pos )
);
sata_link_layer_read slr (
.rst (rst ),
.clk (clk ),
.en (read_en ),
.idle (read_idle ),
.sync_escape (sync_escape ),
.phy_ready (phy_ready ),
.dbg_hold (hold ),
.detect_align (detect_align ),
.detect_sync (detect_sync ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_holda (detect_holda ),
.detect_hold (detect_hold ),
.detect_xrdy_xrdy (detect_xrdy_xrdy ),
.tx_dout (slr_tx_dout ),
.tx_isk (slr_tx_isk ),
.rx_din (rx_din ),
.rx_isk (rx_isk ),
.read_ready (read_ready ),
.read_strobe (read_strobe ),
.read_data (read_data ),
.read_start (read_start ),
.read_finished (read_finished ),
.remote_abort (remote_abort ),
.crc_ok (read_crc_ok ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.lax_r_state (lax_r_state )
);
//Asynchronous logic
assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
assign ll_tx_isk = (!read_idle) ? slr_tx_isk : (!write_idle) ? slw_tx_isk : sli_tx_isk;
assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
(send_pmack) ? `PRIM_PMACK :
`PRIM_SYNC;
assign sli_tx_isk = 1;
assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
assign lax_i_state = state;
//Main State Machine
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
end
else begin
//Strobes
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
if (!platform_ready) begin
state <= NOT_READY;
end
if (phy_ready) begin
case (state)
NOT_READY: begin
if (platform_ready) begin
state <= IDLE;
end
end
IDLE: begin
write_en <= 1;
read_en <= 1;
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
state <= PM_DENY;
end
end
PM_DENY: begin
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
end
else begin
state <= IDLE;
end
end
default: begin
state <= NOT_READY;
end
endcase
end
end
end
endmodule
|
`timescale 1ns/1ns
module usb_tx_sie
(input c,
input c_48,
input rst,
input [7:0] d,
input dv,
output done,
output oe_n,
inout vp,
inout vm);
wire txf_q, txf_read, txf_empty;
usb_tx_fifo usb_tx_fifo_inst
(.c(c), .c_48(c_48),
.d(d), .dv(dv), // at 125 mhz
.q(txf_q), .read(txf_read),
.empty(txf_empty)); // at 48 mhz
/////////////////////////////////////////////////////////////////////////
// everything below here is in the 48 MHz clock domain
wire stuff_q, stuff_q_empty; // bit-stuffed output data and output data-valid
wire stuff_q_req; // read request from bit-stuffed data stream
usb_tx_stuff usb_tx_stuff_inst
(.c(c_48), .d(txf_q), .d_empty(txf_empty), .d_req(txf_read),
.q(stuff_q), .q_req(stuff_q_req), .q_empty(stuff_q_empty));
localparam ST_IDLE = 4'd0;
localparam ST_OE = 4'd1;
localparam ST_DATA_BIT = 4'd2;
localparam ST_LAST_BIT = 4'd3;
localparam ST_EOP_SE0_0 = 4'd4;
localparam ST_EOP_SE0_1 = 4'd5;
localparam ST_EOP_J = 4'd6;
localparam ST_IPG = 4'd7; // let's do inter-packet gap of 6 bit times
localparam ST_DONE = 4'd8;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(rst), .en(1'b1), .d(next_state), .q(state));
wire [2:0] ones_count;
wire ones_count_rst, ones_count_en;
r #(3) ones_count_r
(.c(c_48), .rst(ones_count_rst), .en(ones_count_en),
.d(ones_count + 1'b1), .q(ones_count));
wire [1:0] bit_timer;
r #(2) bit_timer_r
(.c(c_48), .rst(1'b0), .en(1'b1), .d(bit_timer+1'b1), .q(bit_timer));
wire advance = bit_timer == 2'b00;
//wire t1 = bit_timer == 2'b01;
assign stuff_q_req = ctrl[0];
// inter-packet gap timer
wire ipg_cnt_rst;
wire [4:0] ipg_cnt;
r #(5) ipg_cnt_r
(.c(c_48), .rst(ipg_cnt_rst), .en(1'b1), .d(ipg_cnt+1'b1), .q(ipg_cnt));
always @* begin
case (state)
ST_IDLE:
if (~stuff_q_empty) ctrl = { ST_OE , 5'b11110 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_OE:
if (advance /*& ipg_cnt > 5'd20*/) ctrl = { ST_DATA_BIT , 5'b01110 };
else ctrl = { ST_OE , 5'b01110 };
ST_DATA_BIT:
if (advance & stuff_q_empty) ctrl = { ST_EOP_SE0_0, 5'b00010 };
else if (advance) ctrl = { ST_DATA_BIT , 5'b00011 };
else ctrl = { ST_DATA_BIT , 5'b00010 };
/*
ST_LAST_BIT:
if (advance) ctrl = { ST_EOP_SE0_0, 5'b00010 };
else ctrl = { ST_LAST_BIT , 5'b00010 };
*/
ST_EOP_SE0_0:
if (advance) ctrl = { ST_EOP_SE0_1, 5'b00110 };
else ctrl = { ST_EOP_SE0_0, 5'b00110 };
ST_EOP_SE0_1:
if (advance) ctrl = { ST_EOP_J , 5'b10110 };
else ctrl = { ST_EOP_SE0_1, 5'b00110 };
ST_EOP_J:
if (advance /*& ipg_cnt > 5'd20*/) ctrl = { ST_IPG , 5'b11110 };
else ctrl = { ST_EOP_J , 5'b01110 };
ST_IPG:
if (ipg_cnt == 5'd3) ctrl = { ST_DONE , 5'b00000 };
else ctrl = { ST_IPG , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
wire bit_hardcoded_en = ctrl[2];
wire bit_hardcoded_vp = ctrl[3];
wire bit_hardcoded_vm = 1'b0;
assign ipg_cnt_rst = ctrl[4];
wire oe_n_i = ~(ctrl[1] | rst);
d1 oe_d1_r(.c(c_48), .d(oe_n_i), .q(oe_n));
wire vp_out = rst ? 1'b0 : (bit_hardcoded_en ? bit_hardcoded_vp : stuff_q);
wire vm_out = rst ? 1'b0 : (bit_hardcoded_en ? bit_hardcoded_vm : ~stuff_q);
wire vp_out_d1, vm_out_d1;
d1 vp_out_d1_r(.c(c_48), .d(vp_out), .q(vp_out_d1));
d1 vm_out_d1_r(.c(c_48), .d(vm_out), .q(vm_out_d1));
assign vp = ~oe_n ? vp_out_d1 : 1'bz;
assign vm = ~oe_n ? vm_out_d1 : 1'bz;
wire done_c48 = state == ST_DONE;
sync done_s(.in(done_c48), .clk(c), .out(done));
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 1100; int n; vector<int> g[N]; int ed[N][3]; int ans[10 * N][3]; int ansSz; void addAns(int v, int u, int x) { ans[ansSz][0] = v + 1; ans[ansSz][1] = u + 1; ans[ansSz][2] = x; ansSz++; } int getLeaf(int v, int par, int u) { if (v == u) return -1; if ((int)g[v].size() == 1) return v; int res = -2; for (int w : g[v]) { if (w == par) continue; int z = getLeaf(w, v, u); if (z == -1) return -1; res = z; } return res; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int v, u, w; scanf( %d%d%d , &v, &u, &w); v--; u--; ed[i][0] = v; ed[i][1] = u; ed[i][2] = w; g[v].push_back(u); g[u].push_back(v); } for (int v = 0; v < n; v++) { if ((int)g[v].size() == 2) { printf( NO n ); return 0; } } for (int i = 1; i < n; i++) { int v = ed[i][0], u = ed[i][1], x = ed[i][2] / 2; vector<int> vv, uu; if ((int)g[v].size() == 1) { vv.push_back(v); } else { for (int w : g[v]) { int z = getLeaf(w, v, u); if (z != -1) vv.push_back(z); if ((int)vv.size() == 2) break; } } if ((int)g[u].size() == 1) { uu.push_back(u); } else { for (int w : g[u]) { int z = getLeaf(w, u, v); if (z != -1) uu.push_back(z); if ((int)uu.size() == 2) break; } } if ((int)uu.size() == 1) swap(vv, uu); if ((int)uu.size() == 1) { addAns(vv[0], uu[0], 2 * x); } else if ((int)vv.size() == 1) { addAns(vv[0], uu[0], x); addAns(vv[0], uu[1], x); addAns(uu[0], uu[1], -x); } else { addAns(vv[0], uu[0], x); addAns(vv[1], uu[1], x); addAns(vv[0], vv[1], -x); addAns(uu[0], uu[1], -x); } } printf( YES n ); printf( %d n , ansSz); for (int i = 0; i < ansSz; i++) printf( %d %d %d n , ans[i][0], ans[i][1], ans[i][2]); return 0; }
|
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