text
stringlengths 59
71.4k
|
|---|
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05.10.2017 12:05:16
// Design Name:
// Module Name: memoria_intrucciones
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////
module memoriaintrucciones(direinstru,instru,clk,reset);
input [4:0] direinstru;
input clk;
input reset;
//salida
output wire [31:0] instru;
reg [31:0] registro_rom [31:0];
assign instru = registro_rom[direinstru];
always @ (*)
begin
if (reset == 1)
begin
registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;//carga un 9 en sram1 posicion 4
registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000; // Lee el dato anterior guardado(sram1 pos 4)
registro_rom[2] = 32'b1111_1100_0000_0000__0000_0000_0000_0000; //not
registro_rom[3] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;//salto +3
registro_rom[4] = 32'b1000_1100_0000_0001__0001_1000_0110_0000; //hace una suma
registro_rom[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[6] = 32'b1010_1111_1111_1111__0000_0000_0000_0000;//carga un 9 en sram1 posicion 32
registro_rom[7] = 32'b1000_1111_1111_1110__0000_0000_0000_0000; // Lee el dato anterior guardado(sram1 pos 4)
registro_rom[8] = 32'b1000_1100_0000_0001__0001_1000_0110_0000; //hace una suma
registro_rom[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[20] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
else
begin
// registro_rom[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
// registro_rom[1] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[2] = 32'b0000_0000_0000_0000_0000_0000_0000_0010;
// registro_rom[3] = 32'b0000_0000_0000_0000_0000_0000_0000_0011;
// registro_rom[4] = 32'b0000_0000_0000_0000_0000_0000_0000_0010;
// registro_rom[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[6] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[8] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
// registro_rom[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
// registro_rom[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[20] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
// registro_rom[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
// registro_rom[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
end
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module device_id_reg #(
parameter DEVICE_ID = 0,
parameter REVISION = 0,
parameter DEVICE_STR = "Undefined device"
)
(
// Register interface signals
input reg_req,
output reg reg_ack,
input reg_rd_wr_L,
input [(`CORE_REG_ADDR_WIDTH - 2 - 4) - 1:0] reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
localparam NUM_REGS = 32;
localparam STR_REGS = 25;
localparam DEVICE_STR_LEN = STR_REGS * 4;
localparam WORD_WIDTH = `CPCI_NF2_DATA_WIDTH / 8;
// Extract a part of the device string
//
// Note: This assumes that CPCI_NF2_DATA_WIDTH is 32 bits
// Attempted to make this generic but it generated an XST error to
// do with array accesses (worked fine in ModelSim).
function [`CPCI_NF2_DATA_WIDTH - 1:0] get_device_substr;
input integer word;
reg [DEVICE_STR_LEN * 8 - 1:0] temp_str;
reg [7:0] result_1;
reg [7:0] result_2;
reg [7:0] result_3;
reg [7:0] result_4;
integer length;
integer pos;
integer i;
begin
temp_str = DEVICE_STR;
// Calculate the length
length = 0;
//pos = DEVICE_STR_LEN * 8 - 1;
pos = 0;
while (pos <= DEVICE_STR_LEN * 8 - 1 && temp_str[pos +: 8] != 8'h0) begin
length = length + 1;
pos = pos + 8;
end
// Jump to the location that we are trying to copy data from
pos = (length - word * WORD_WIDTH) * 8 - 1;
// Copy the data
result_1 = (pos < 0) ? 8'b0 : temp_str[pos -: 8];
pos = pos - 8;
result_2 = (pos < 0) ? 8'b0 : temp_str[pos -: 8];
pos = pos - 8;
result_3 = (pos < 0) ? 8'b0 : temp_str[pos -: 8];
pos = pos - 8;
result_4 = (pos < 0) ? 8'b0 : temp_str[pos -: 8];
get_device_substr = {result_1, result_2, result_3, result_4};
end
endfunction // get_device_substr
reg req_acked;
wire [`CPCI_NF2_DATA_WIDTH-1:0] device_id[0:NUM_REGS - 1];
genvar i;
assign device_id[`DEV_ID_MD5_0] = `DEV_ID_MD5_VALUE_0;
assign device_id[`DEV_ID_MD5_1] = `DEV_ID_MD5_VALUE_1;
assign device_id[`DEV_ID_MD5_2] = `DEV_ID_MD5_VALUE_2;
assign device_id[`DEV_ID_MD5_3] = `DEV_ID_MD5_VALUE_3;
assign device_id[`DEV_ID_DEVICE_ID] = DEVICE_ID;
assign device_id[`DEV_ID_REVISION] = REVISION;
assign device_id[`DEV_ID_CPCI_ID] = {`CPCI_REVISION_ID, `CPCI_VERSION_ID};
generate
for (i = 0 ; i < STR_REGS; i = i + 1) begin: device_id_gen
assign device_id[i + (NUM_REGS - STR_REGS)] = get_device_substr(i);
end
endgenerate
// ==============================================
// Main state machine
always @(posedge clk)
begin
if (reset) begin
reg_ack <= 1'b0;
reg_rd_data <= 'h 0;
req_acked <= 1'b0;
end
else begin
if (reg_req) begin
// Only process the request if it's new
if (!req_acked) begin
reg_ack <= 1'b1;
req_acked <= 1'b1;
// Verify that the address actually corresponds to the RAM
if (reg_addr < NUM_REGS) begin
reg_rd_data <= device_id[reg_addr];
end
else begin
reg_rd_data <= 'h dead_beef;
end
end
else begin
reg_ack <= 1'b0;
end
end // if (reg_req)
else begin
reg_ack <= 1'b0;
req_acked <= 1'b0;
end // if (reg_req) else
end
end
endmodule // device_id_reg
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int maxn = 1e6; const int INF = 0x7fffffff; const int mod = 1e9 + 7; const double eps = 1e-7; const double Pi = acos(-1.0); inline int read_int() { char c; int ret = 0, sgn = 1; do { c = getchar(); } while ((c < 0 || c > 9 ) && c != - ); if (c == - ) sgn = -1; else ret = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); return sgn * ret; } inline long long read_ll() { char c; long long ret = 0, sgn = 1; do { c = getchar(); } while ((c < 0 || c > 9 ) && c != - ); if (c == - ) sgn = -1; else ret = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); return sgn * ret; } int n, res = 1; string s; int main() { cin >> n >> s; for (int i = 1; i < n; i++) { res += (s[i] != s[i - 1]); } cout << ((res + 2) < (n) ? (res + 2) : (n)) << endl; return 0; }
|
// -*- Mode: Verilog -*-
// Filename : fw_interface_wb.v
// Description : Firmware Testing Wishbone Bus Interface
// Author : Philip Tracton
// Created On : Wed Dec 21 14:05:32 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 21 14:05:32 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module fw_interface_wb (/*AUTOARG*/
// Outputs
wb_ack_o, wb_rty_o, wb_err_o, wb_dat_o, new_report, new_warning,
new_error, new_compare, report_reg, warning_reg, error_reg,
expected_reg, measured_reg, trigger_reg, write_mem, data, index,
// Inputs
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i,
wb_bte_i, wb_cti_i, wb_cyc_i, wb_stb_i
) ;
//
// Wishbone Interface
//
input wire wb_clk_i;
input wire wb_rst_i;
input wire [31:0] wb_adr_i;
input wire [31:0] wb_dat_i;
input wire [3:0] wb_sel_i;
input wire wb_we_i;
input wire [1:0] wb_bte_i;
input wire [2:0] wb_cti_i;
input wire wb_cyc_i;
input wire wb_stb_i;
output reg wb_ack_o;
output reg wb_rty_o;
output reg wb_err_o;
output reg [31:0] wb_dat_o;
output wire new_report;
output wire new_warning;
output wire new_error;
output wire new_compare;
output reg [31:0] report_reg;
output reg [31:0] warning_reg;
output reg [31:0] error_reg;
output reg [31:0] expected_reg;
output reg [31:0] measured_reg;
output reg [31:0] trigger_reg;
output wire write_mem;
output wire [7:0] data;
output wire [5:0] index;
`define CONTROL_REG_OFFSET 6'h00 // 0x00
`define REPORT_REG_OFFSET 6'h01 // 0x04 >> 2
`define WARNING_REG_OFFSET 6'h02 // 0x08 >> 2
`define ERROR_REG_OFFSET 6'h03 // 0x0C >> 2
`define MEASURED_REG_OFFSET 6'h04 // 0x10 >> 2
`define EXPECTED_REG_OFFSET 6'h05 // 0x14 >> 2
`define TRIGGER_REG_OFFSET 6'h06 // 0x18 >> 2
`define MEMORY_OFFSET 6'h07 // 0x1C >> 2
`define MEMORY_END 6'h17 // 0x5C >> 2
/*AUTOREG*/
/*AUTOWIRE*/
wire [6:0] word_addr = wb_adr_i[8:2];
wire control_reg_enable = (wb_adr_i[8:2] == `CONTROL_REG_OFFSET) & wb_cyc_i & wb_stb_i;
wire [7:0] index_sel_offset;
//
// Control Signals for String Memory in logic block
//
assign write_mem = ((wb_adr_i[8:2] >= `MEMORY_OFFSET) && (wb_adr_i[8:2] < `MEMORY_END)) & wb_cyc_i & wb_stb_i;
assign data = (write_mem) ? wb_dat_i[7:0] : 0;
assign index_sel_offset = (wb_sel_i == 4'h08) ? 8'h00:
(wb_sel_i == 4'h04) ? 8'h01:
(wb_sel_i == 4'h02) ? 8'h02:
(wb_sel_i == 4'h01) ? 8'h03:
0;
wire [5:0] sub = wb_adr_i[7:0] - (`MEMORY_OFFSET <<2);
//
// FIXME: This is very annoying....
//
`ifdef WISHBONE_CPU_LM32
assign index = (write_mem) ? wb_adr_i[7:0] - (`MEMORY_OFFSET <<2) /*+ index_sel_offset*/ : 0;
`else
assign index = (write_mem) ? wb_adr_i[7:0] - (`MEMORY_OFFSET <<2) + index_sel_offset : 0;
`endif
//
// Detect a new message
//
assign new_report = (wb_we_i & control_reg_enable & wb_dat_i[0]);
assign new_warning = (wb_we_i & control_reg_enable & wb_dat_i[1]);
assign new_error = (wb_we_i & control_reg_enable & wb_dat_i[2]);
assign new_compare = (wb_we_i & control_reg_enable & wb_dat_i[3]);
//
// Wishbone Response
//
always @(posedge wb_clk_i)
if (wb_rst_i) begin
wb_ack_o <= 1'b0;
wb_err_o <= 1'b0;
wb_rty_o <= 1'b0;
end else begin
//
// If we address beyond the end of memory, that is an ERROR
//
if ((wb_cyc_i & wb_stb_i) & (wb_adr_i[7:2] > `MEMORY_END)) begin
wb_err_o <= 1;
end else begin
wb_err_o <= 0;
end
//
// We always respond in a single cycle, so ack on
// cycle and strobe
//
if (wb_cyc_i & wb_stb_i) begin
wb_ack_o <= 1;
end else begin
wb_ack_o <= 0;
end
end // else: !if(wb_rst_i)
//
// Register Write Logic
//
always @(posedge wb_clk_i)
if (wb_rst_i) begin
report_reg <= 0;
warning_reg <= 0;
error_reg <= 0;
expected_reg <= 0;
measured_reg <= 0;
trigger_reg <= 0;
end else begin
if (wb_cyc_i & wb_stb_i & wb_we_i) begin
case (wb_adr_i[8:2])
`REPORT_REG_OFFSET:begin
report_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : report_reg[07:00];
report_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : report_reg[15:08];
report_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : report_reg[23:16];
report_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : report_reg[31:24];
end
`WARNING_REG_OFFSET:begin
warning_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : warning_reg[07:00];
warning_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : warning_reg[15:08];
warning_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : warning_reg[23:16];
warning_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : warning_reg[31:24];
end
`ERROR_REG_OFFSET:begin
error_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : error_reg[07:00];
error_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : error_reg[15:08];
error_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : error_reg[23:16];
error_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : error_reg[31:24];
end
`MEASURED_REG_OFFSET:begin
measured_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : measured_reg[07:00];
measured_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : measured_reg[15:08];
measured_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : measured_reg[23:16];
measured_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : measured_reg[31:24];
end
`EXPECTED_REG_OFFSET:begin
expected_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : expected_reg[07:00];
expected_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : expected_reg[15:08];
expected_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : expected_reg[23:16];
expected_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : expected_reg[31:24];
end
`TRIGGER_REG_OFFSET:begin
trigger_reg[07:00] <= wb_sel_i[0] ? wb_dat_i[07:00] : trigger_reg[07:00];
trigger_reg[15:08] <= wb_sel_i[1] ? wb_dat_i[15:08] : trigger_reg[15:08];
trigger_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : trigger_reg[23:16];
trigger_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : trigger_reg[31:24];
end
endcase // case (wb_adr_i[7:2])
end // if (wb_cyc_i & wb_stb_i & wb_we_i)
end // else: !if(wb_rst_i)
//
// Register Read Logic
//
always @(posedge wb_clk_i)
if (wb_rst_i) begin
wb_dat_o <= 0;
end else begin
if (wb_cyc_i & wb_stb_i & ~wb_we_i) begin
case (wb_adr_i[7:2])
`REPORT_REG_OFFSET: wb_dat_o <= report_reg;
`WARNING_REG_OFFSET: wb_dat_o <= warning_reg;
`ERROR_REG_OFFSET: wb_dat_o <= error_reg;
`MEASURED_REG_OFFSET: wb_dat_o <= measured_reg;
`EXPECTED_REG_OFFSET: wb_dat_o <= expected_reg;
`TRIGGER_REG_OFFSET: wb_dat_o <= trigger_reg;
default: wb_dat_o <= 0;
endcase // case (wb_adr_i[7:2])
end begin
wb_dat_o <= 0;
end
end
endmodule // fw_interface_wb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { map<long long, pair<long long, long long> > mpl; vector<long long> ml; long long n, q, xi, amyor = 0; scanf( %lld %lld , &n, &q); deque<long long> dq; for (int i = (0); i < int(n); i++) { scanf( %lld , &xi); amyor = max(amyor, xi); dq.push_back(xi); } long long cnt = 0; while (1) { if (dq.front() == amyor) break; long long A = dq.front(); dq.pop_front(); long long B = dq.front(); dq.pop_front(); if (B > A) { dq.push_front(B); dq.push_back(A); } else { dq.push_front(A); dq.push_back(B); } mpl[cnt] = {A, B}; cnt++; } dq.pop_front(); while (!dq.empty()) { ml.push_back(dq.front()); dq.pop_front(); } while (q--) { long long m; scanf( %lld , &m); if (m <= cnt) { m--; long long x, y; printf( %lld %lld n , mpl[m].first, mpl[m].second); } else { long long N = cnt; long long rango = (m - N); N = ml.size(); long long D = rango % N; if (D == 0) D = N; D--; m = D; printf( %lld %lld n , amyor, ml[m]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n, l, k = 0, maxi; scanf( %d , &n); long long int count = 0; int a[15]; l = n; while (l) { a[k] = l % 10; l = l / 10; k++; } while (k > 0) { maxi = 0; for (i = 0; i < k; i++) if (a[i] > maxi) maxi = a[i]; n = n - maxi; k = 0; l = n; while (l) { a[k] = l % 10; l = l / 10; k++; } count++; } if (n == 0) cout << count << endl; else cout << count + 1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_4_V
`define SKY130_FD_SC_LP__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_4_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double error = 1e-7; double v, r; bool puede(double t, double dist) { dist -= v * t; if (dist <= 0) return true; double tvuelta = r * 2 * M_PI / v; t -= int(t / tvuelta) * tvuelta; double a = t * v / r; return dist <= 2 * r * sin(a / 2.0); } int main() { cout.setf(ios::fixed); cout.precision(10); int n; cin >> n >> r >> v; for (int cas = 0; cas < n; cas++) { int s, f; cin >> s >> f; double inf = 0; double sup = 2000000000; double d = f - s; while (inf + error < sup) { double med = (inf + sup) / 2.0; if (puede(med, d)) sup = med; else inf = med; } cout << inf << endl; } }
|
#include <bits/stdc++.h> using namespace std; map<int, int> frontc; map<int, int> backc; int main() { int n, ans, a, b, x, i, x1; cin >> n; ans = n; for (i = 0; i < n; i++) { cin >> a >> b; if (a != b) backc[b]++; frontc[a]++; } map<int, int>::iterator it; for (it = frontc.begin(); it != frontc.end(); it++) { x = it->first; a = frontc[x]; b = backc[x]; if (a >= (n + 1) / 2) { cout << 0 << endl; return 0; } if (a + b >= (n + 1) / 2) if ((n + 1) / 2 - a < ans) ans = (n + 1) / 2 - a; } if (ans != n) { cout << ans << endl; return 0; } for (it = backc.begin(); it != backc.end(); it++) { x = it->first; b = backc[x]; if (b >= (n + 1) / 2) { cout << (n + 1) / 2 << endl; return 0; } } if (ans == n) { cout << -1 << endl; return 0; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; cout << N << ; for (int i = 1; i < N; i++) cout << i << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1000000 + 5; int f[maxn], inv[maxn], finv[maxn]; void init() { inv[1] = 1; for (int i = 2; i < maxn; i++) inv[i] = (mod - mod / i) * 1ll * inv[mod % i] % mod; f[0] = finv[0] = 1; for (int i = 1; i < maxn; i++) { f[i] = f[i - 1] * 1ll * i % mod; finv[i] = finv[i - 1] * 1ll * inv[i] % mod; } } int C(int n, int m) { if (m < 0 || m > n) return 0; return f[n] * 1ll * finv[n - m] % mod * finv[m] % mod; } long long qpow(long long x, long long n) { long long r = 1; while (n > 0) { if (n & 1) r = r * x % mod; n >>= 1; x = x * x % mod; } return r; } long long T(long long n, long long k) { if (k == n) return 1; return k * qpow(n, n - k - 1) % mod; } int n, m, a, b; int main() { init(); cin >> n >> m >> a >> b; long long ans = 0; for (int i = 1; i < n; i++) { long long tot = 1ll * C(m - 1, i - 1) * C(n - 2, i - 1) % mod * f[i - 1] % mod * qpow(m, n - i - 1) % mod * T(n, i + 1) % mod; ans += tot; if (ans >= mod) ans -= mod; } cout << ans << endl; return 0; }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module mbus_ctrl_wrapper(
input CLK_EXT,
input CLKIN,
output CLKOUT,
input RESETn,
input DIN,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH-1:0] RX_ADDR,
output [`DATA_WIDTH-1:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK,
`ifdef POWER_GATING
// power gated signals from sleep controller
input MBC_RESET,
// power gated signals to layer controller
output LRC_SLEEP,
output LRC_CLKENB,
output LRC_RESET,
output LRC_ISOLATE,
// wake up bus controller
input EXTERNAL_INT,
output CLR_EXT_INT,
output CLR_BUSY,
// wake up processor
output reg SLEEP_REQUEST_TO_SLEEP_CTRL,
`endif
input [`WATCH_DOG_WIDTH-1:0] THRESHOLD
);
parameter ADDRESS = 20'haaaaa;
wire CLK_CTRL_TO_NODE;
wire DOUT_CTRL_TO_NODE;
wire NODE_RX_REQ;
wire NODE_RX_ACK;
`ifdef POWER_GATING
wire SLEEP_REQ;
`endif
reg ctrl_addr_match, ctrl_rx_ack;
`ifdef POWER_GATING
wire RESETn_local = (RESETn & (~MBC_RESET));
`else
wire RESETn_local = RESETn;
`endif
always @ *
begin
if ((RX_BROADCAST) && (RX_ADDR[`FUNC_WIDTH-1:0]==`CHANNEL_CTRL))
ctrl_addr_match = 1;
else
ctrl_addr_match = 0;
end
assign RX_REQ = (ctrl_addr_match)? 1'b0 : NODE_RX_REQ;
always @ (posedge CLK_EXT or negedge RESETn_local)
begin
if (~RESETn_local)
begin
ctrl_rx_ack <= 0;
`ifdef POWER_GATING
SLEEP_REQUEST_TO_SLEEP_CTRL <= 0;
`endif
end
else
begin
if (ctrl_addr_match & NODE_RX_REQ)
begin
ctrl_rx_ack <= 1;
end
if (ctrl_rx_ack & (~NODE_RX_REQ))
ctrl_rx_ack <= 0;
`ifdef POWER_GATING
// delay 1 cycle
SLEEP_REQUEST_TO_SLEEP_CTRL <= SLEEP_REQ;
`endif
end
end
assign NODE_RX_ACK = (RX_ACK | ctrl_rx_ack);
mbus_ctrl ctrl0(
.CLK_EXT(CLK_EXT),
.RESETn(RESETn_local),
.CLKIN(CLKIN),
.CLKOUT(CLK_CTRL_TO_NODE),
.DIN(DIN),
.DOUT(DOUT_CTRL_TO_NODE),
.THRESHOLD(THRESHOLD)
);
mbus_node#(.ADDRESS(ADDRESS), .MASTER_NODE(1'b1), .CPU_LAYER(1'b1)) node0(
.CLKIN(CLK_CTRL_TO_NODE),
.RESETn(RESETn),
.DIN(DOUT_CTRL_TO_NODE),
.CLKOUT(CLKOUT),
.DOUT(DOUT),
.TX_ADDR(TX_ADDR),
.TX_DATA(TX_DATA),
.TX_PEND(TX_PEND),
.TX_REQ(TX_REQ),
.TX_PRIORITY(TX_PRIORITY),
.TX_ACK(TX_ACK),
.RX_ADDR(RX_ADDR),
.RX_DATA(RX_DATA),
.RX_REQ(NODE_RX_REQ),
.RX_ACK(NODE_RX_ACK),
.RX_BROADCAST(RX_BROADCAST),
.RX_FAIL(RX_FAIL),
.RX_PEND(RX_PEND),
.TX_FAIL(TX_FAIL),
.TX_SUCC(TX_SUCC),
.TX_RESP_ACK(TX_RESP_ACK),
`ifdef POWER_GATING
.MBC_RESET(MBC_RESET),
.LRC_SLEEP(LRC_SLEEP),
.LRC_CLKENB(LRC_CLKENB),
.LRC_RESET(LRC_RESET),
.LRC_ISOLATE(LRC_ISOLATE),
.SLEEP_REQUEST_TO_SLEEP_CTRL(SLEEP_REQ),
.EXTERNAL_INT(EXTERNAL_INT),
.CLR_EXT_INT(CLR_EXT_INT),
.CLR_BUSY(CLR_BUSY),
`endif
.ASSIGNED_ADDR_IN(4'h1),
.ASSIGNED_ADDR_OUT(),
.ASSIGNED_ADDR_VALID(1'b1),
.ASSIGNED_ADDR_WRITE(),
.ASSIGNED_ADDR_INVALIDn()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool compare(int a, int b) { return a > b; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (long long int i = 0; i < n + 1; i++) { for (long long int j = 0; j < 2 * (n - i); j++) { cout << ; } for (long long int j = 0; j < i + 1; j++) { if (i) cout << j << ; else cout << j; } for (int j = i - 1; j >= 0; j--) { if (j) cout << j << ; else cout << j; } cout << endl; } for (int i = n - 1; i >= 1; i--) { for (long long int j = 0; j < 2 * (n - i); j++) { cout << ; } for (long long int j = 0; j < i + 1; j++) { cout << j << ; } for (int j = i - 1; j >= 0; j--) { if (j) cout << j << ; else cout << j; } cout << endl; } for (long long int j = 0; j < 2 * (n); j++) { cout << ; } cout << 0 ; return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:167772160 ) int comp(const void* a, const void* b) { return (*(long long*)a) - (*(long long*)b); } int main() { int n; long long mas[300000], ans(0); scanf( %d , &n); for (int i(0); i < n; ++i) scanf( %I64d , &mas[i]); qsort(mas, n, sizeof(long long), comp); for (int i(0); i < n; ++i) ans += mas[i] * (2 + i); ans -= mas[n - 1]; printf( %I64d , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_1_V
`define SKY130_FD_SC_LP__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_1_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; long long POW(long long a, long long b, long long MMM = MOD) { long long ret = 1; for (; b; b >>= 1, a = (a * a) % MMM) if (b & 1) ret = (ret * a) % MMM; return ret; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { if (a == 0 || b == 0) return a + b; return a * (b / gcd(a, b)); } int dx[] = {0, 1, 0, -1, 1, 1, -1, -1}, dy[] = {1, 0, -1, 0, 1, -1, 1, -1}; int ddx[] = {-1, -2, 1, -2, 2, -1, 2, 1}, ddy[] = {-2, -1, -2, 1, -1, 2, 1, 2}; pair<int, int> a[200000]; int c[20], b[200000]; int n; bool ok(int k) { for (int(i) = (0); (i) <= (n - 1); (i) += (1)) a[i] = make_pair(b[i] >= (1 << k) ? 0 : b[i], i); for (int(i) = (k - 1); (i) >= (0); (i) -= (1)) { int t = max_element(a, a + n) - a; swap(a[0], a[t]); if (a[0].first == 0) return 0; if (31 - __builtin_clz(a[0].first) != i) return 0; c[i] = b[a[0].second]; for (int(j) = (n - 1); (j) >= (0); (j) -= (1)) if (a[j].first & (1 << i)) a[j].first ^= a[0].first; } printf( %d n , k); int now = 0; for (int(i) = (1); (i) <= (1 << k); (i) += (1)) { printf( %d , now); now ^= (c[__builtin_ctz(i)]); } return 1; } int main() { scanf( %d , &n); for (int(i) = (0); (i) <= (n - 1); (i) += (1)) { scanf( %d , &b[i]); } for (int(k) = (18); (k) >= (1); (k) -= (1)) { if (ok(k)) return 0; } puts( 0 n0 ); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
//Simple debug:
//wire [1:1] wir_a [3:3] [2:2]; //11
//logic [1:1] log_a [3:3] [2:2]; //12
//wire [3:3] [2:2] [1:1] wir_p; //13
//logic [3:3] [2:2] [1:1] log_p; //14
integer cyc; initial cyc = 0;
`ifdef iverilog
reg [7:0] arr [3:0];
wire [7:0] arr_w [3:0];
`else
reg [3:0] [7:0] arr;
wire [3:0] [7:0] arr_w;
`endif
reg [7:0] sum;
reg [7:0] sum_w;
integer i0;
initial begin
for (i0=0; i0<5; i0=i0+1) begin
arr[i0] = 1 << (i0[1:0]*2);
end
end
assign arr_w = arr;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
sum <= 0;
sum_w <= 0;
end
else if (cyc >= 10 && cyc < 14) begin
sum <= sum + arr[cyc-10];
sum_w <= sum_w + arr_w[cyc-10];
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
if (sum != 8'h55) $stop;
if (sum != sum_w) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// Test ordering of packed dimensions
logic [31:0] data_out;
logic [31:0] data_out2;
logic [0:0] [2:0] [31:0] data_in;
logic [31:0] data_in2 [0:0] [2:0];
assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2];
assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2];
logic [31:0] last_data_out;
always @ (posedge clk) begin
if (cyc <= 2) begin
data_in[0][0] <= 0;
data_in[0][1] <= 0;
data_in[0][2] <= 0;
data_in2[0][0] <= 0;
data_in2[0][1] <= 0;
data_in2[0][2] <= 0;
end
else if (cyc > 2 && cyc < 99) begin
data_in[0][0] <= data_in[0][0] + 1;
data_in[0][1] <= data_in[0][1] + 1;
data_in[0][2] <= data_in[0][2] + 1;
data_in2[0][0] <= data_in2[0][0] + 1;
data_in2[0][1] <= data_in2[0][1] + 1;
data_in2[0][2] <= data_in2[0][2] + 1;
last_data_out <= data_out;
`ifdef TEST_VERBOSE
$write("data_out %0x %0x\n", data_out, last_data_out);
`endif
if (cyc > 4 && data_out != last_data_out + 3) $stop;
if (cyc > 4 && data_out != data_out2) $stop;
end
end
// Test for mixed implicit/explicit dimensions and all implicit packed
bit [3:0][7:0][1:0] vld [1:0][1:0];
bit [3:0][7:0][1:0] vld2;
// There are specific nodes for Or, Xor, Xnor and And
logic vld_or;
logic vld2_or;
assign vld_or = |vld[0][0];
assign vld2_or = |vld2;
logic vld_xor;
logic vld2_xor;
assign vld_xor = ^vld[0][0];
assign vld2_xor = ^vld2;
logic vld_xnor;
logic vld2_xnor;
assign vld_xnor = ~^vld[0][0];
assign vld2_xnor = ~^vld2;
logic vld_and;
logic vld2_and;
assign vld_and = &vld[0][0];
assign vld2_and = &vld2;
// Bit reductions should be cloned, other unary operations should clone the
// entire assign.
bit [3:0][7:0][1:0] not_lhs;
bit [3:0][7:0][1:0] not_rhs;
assign not_lhs = ~not_rhs;
// Test an AstNodeUniop that shouldn't be expanded
bit [3:0][7:0][1:0] vld2_inv;
assign vld2_inv = ~vld2;
initial begin
for (int i=0; i<4; i=i+2) begin
for (int j=0; j<8; j=j+2) begin
vld[0][0][i][j] = 2'b00;
vld[0][0][i+1][j+1] = 2'b00;
vld2[i][j] = 2'b00;
vld2[i+1][j+1] = 2'b00;
not_rhs[i][j] = i[1:0];
not_rhs[i+1][j+1] = i[1:0];
end
end
end
logic [3:0] expect_cyc; initial expect_cyc = 'd15;
always @(posedge clk) begin
expect_cyc <= expect_cyc + 1;
for (int i=0; i<4; i=i+1) begin
for (int j=0; j<8; j=j+1) begin
vld[0][0][i][j] <= vld[0][0][i][j] + 1;
vld2[i][j] <= vld2[i][j] + 1;
if (not_rhs[i][j] != ~not_lhs[i][j]) $stop;
not_rhs[i][j] <= not_rhs[i][j] + 1;
end
end
if (cyc % 8 == 0) begin
vld[0][0][0][0] <= vld[0][0][0][0] - 1;
vld2[0][0] <= vld2[0][0] - 1;
end
if (expect_cyc < 8 && !vld_xor) $stop;
else if (expect_cyc > 7 && vld_xor) $stop;
if (expect_cyc < 8 && vld_xnor) $stop;
else if (expect_cyc > 7 && !vld_xnor) $stop;
if (expect_cyc == 15 && vld_or) $stop;
else if (expect_cyc == 11 && vld_or) $stop;
else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop;
if (expect_cyc == 10 && !vld_and) $stop;
else if (expect_cyc == 14 && !vld_and) $stop;
else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop;
if (vld_xor != vld2_xor) $stop;
if (vld_xnor != vld2_xnor) $stop;
if (vld_or != vld2_or) $stop;
if (vld_and != vld2_and) $stop;
end
endmodule
|
#include <bits/stdc++.h> const int d = 998244353; using namespace std; int main() { int n, m, k; cin >> n >> m >> k; vector<vector<long long int>> t(n + 1); vector<long long int> init(k + 1, 0); for (int i = 0; i <= n; i++) { t[i] = init; } t[1][0] = m; t[1][1] = 0; for (int i = 2; i <= n; i++) { for (int j = 0; j <= min(i - 1, k); j++) { if (j >= 1) { t[i][j] = (t[i - 1][j] + (m - 1) * t[i - 1][j - 1]) % d; } if (j == 0) { t[i][0] = m; } } } cout << t[n][k]; return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charReceived (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_TB_V
`define SKY130_FD_SC_LS__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:13 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top RAT_slice_12_8_0 -prefix
// RAT_slice_12_8_0_ RAT_xlslice_0_0_sim_netlist.v
// Design : RAT_xlslice_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_xlslice_0_0,xlslice,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlslice,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_slice_12_8_0
(Din,
Dout);
input [17:0]Din;
output [4:0]Dout;
wire [17:0]Din;
assign Dout[4:0] = Din[7:3];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9; long double sqr(long double a) { return a * a; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); long long k; cin >> k; map<long long, pair<long long, long long> > sm; for (auto i = 0; i < k; ++i) { long long n, sum = 0; cin >> n; vector<long long> a(n); for (auto &it : a) { cin >> it; sum += it; } for (auto j = 0; j < n; ++j) { if (sm.find(sum - a[j]) != sm.end()) { cout << YES n << sm[sum - a[j]].first << << sm[sum - a[j]].second << n << i + 1 << << j + 1; return 0; } } for (auto j = 0; j < n; ++j) { sm[sum - a[j]] = {i + 1, j + 1}; } } cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_TB_V
`define SKY130_FD_SC_LS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_jesd_align (
// jesd interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg rx_sof = 'd0;
reg rx_ip_sof_d = 'd0;
reg [31:0] rx_data = 'd0;
// dword may contain more than one frame per clock
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
rx_ip_sof_d <= rx_ip_sof;
if (rx_ip_sof != 4'h0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof_d;
if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data <= rx_ip_data;
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data <= {rx_ip_data[ 7:0], rx_ip_data_d[31: 8]};
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]};
end else if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]};
end else begin
rx_data <= 32'd0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 == 0) cout << NO << endl; else { cout << YES << endl; cout << 1 << ; for (int i = 4; i < 2 * n; i += 4) cout << i << << i + 1 << ; for (int i = 2; i < 2 * n; i += 4) cout << i << << i + 1 << ; cout << 2 * n << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int y, b, r; cin >> y >> b >> r; while (1) { if (r - 1 <= b && r - 2 <= y) { break; } --r; } cout << 3 * r - 3; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : rf_2p_be.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Two port register file with write byte enable
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module rf_2p_be (
clka ,
cena_i ,
addra_i ,
dataa_o ,
clkb ,
cenb_i ,
wenb_i ,
addrb_i ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=8;
parameter Byte_Width=(Word_Width>>3);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input [Addr_Width-1:0] addra_i; // address input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input [Byte_Width-1:0] wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_w;
wire [Word_Width-1:0] datab_m;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if (!cena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = dataa_r;
// -- B Port --//
assign datab_m = mem_array[addrb_i];
genvar j;
generate
for (j=0; j<Byte_Width; j=j+1) begin:j_n
always@(*) begin
datab_w[(j+1)*8-1:j*8] = wenb_i[j] ? datab_m[(j+1)*8-1:j*8]:datab_i[(j+1)*8-1:j*8];
end
end
endgenerate
always @(posedge clkb) begin
if(!cenb_i && !(&wenb_i))
mem_array[addrb_i] <= datab_w;
end
endmodule
|
#include<bits/stdc++.h> #define int long long #define f first #define s second #define N 1010 #define M 1010 #define MOD 998244353 #define oo 1e18 using namespace std; typedef pair<int,int> ii; int v[N][N], estado[N]; set<int>freq[N][N]; int n; void eraseLine(int line, queue<int>&unique) { for(int c=0; c<n; c++) { int val = v[line][c]; freq[c][val].erase(line); if(freq[c][val].size() == 1) { int line = *freq[c][val].begin(); unique.push(line); freq[c][val].clear(); } } } int32_t main() { int t; cin >> t; while(t--) { cin >> n; for(int l=0; l<2*n; l++) { estado[l] = 0; for(int i=0; i<=n; i++) { freq[l][i].clear(); } } for(int l=0; l<2*n; l++) { for(int c=0; c<n; c++) { cin >> v[l][c]; freq[c][v[l][c]].insert(l); } } queue<int>unique; for(int c=0; c<n; c++) { for(int i=1; i<=n; i++) { if(freq[c][i].size() == 1) { int line = *freq[c][i].begin(); unique.push(line); freq[c][i].clear(); } } } int quantityAnswers = 1; vector<int>example; while(example.size() != n) { int choosenLine = -1; if(unique.size()) { choosenLine = unique.front(); unique.pop(); if(estado[choosenLine]) continue; } else { quantityAnswers *= 2; quantityAnswers %= MOD; choosenLine = -1; for(int l=0; l<=2*n; l++) { if(estado[l]) continue; choosenLine = l; break; } } estado[choosenLine] = 2; example.push_back(choosenLine); for(int curLine=0; curLine<2*n; curLine++) { if(estado[curLine]) continue; for(int c=0; c<n; c++) { if(v[choosenLine][c] == v[curLine][c]) { estado[curLine] = 1; break; } } if(estado[curLine]) { eraseLine(curLine, unique); } } eraseLine(choosenLine, unique); } sort(example.begin(), example.end()); cout << quantityAnswers << endl; for(int val:example) cout << val + 1 << ; cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_1_V
`define SKY130_FD_SC_HD__NOR4B_1_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer j;
reg [63:0] cam_lookup_hit_vector;
integer hit_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count = 0;
for (j=0; j < 64; j=j+1) begin
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count2;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count2 = 0;
for (j=63; j >= 0; j=j-1) begin
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count3;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count3 = 0;
for (j=63; j > 0; j=j-1) begin
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
end
end
reg [127:0] wide_for_index;
reg [31:0] wide_for_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
wide_for_count = 0;
for (wide_for_index = 128'hff_00000000_00000000;
wide_for_index < 128'hff_00000000_00000100;
wide_for_index = wide_for_index + 2) begin
wide_for_count = wide_for_count+32'h1;
end
end
// While loop
integer w;
initial begin
while (w<10) w=w+1;
if (w!=10) $stop;
while (w<20) begin w=w+2; end
while (w<20) begin w=w+99999; end // NEVER
if (w!=20) $stop;
end
// Do-While loop
integer dw;
initial begin
do dw=dw+1; while (dw<10);
if (dw!=10) $stop;
do dw=dw+2; while (dw<20);
if (dw!=20) $stop;
do dw=dw+5; while (dw<20); // Once
if (dw!=25) $stop;
end
always @ (posedge clk) begin
cam_lookup_hit_vector <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
cam_lookup_hit_vector <= 64'h00010000_00010000;
end
if (cyc==2) begin
if (hit_count != 32'd2) $stop;
if (hit_count2 != 32'd2) $stop;
if (hit_count3 != 32'd2) $stop;
cam_lookup_hit_vector <= 64'h01010010_00010001;
end
if (cyc==3) begin
if (hit_count != 32'd5) $stop;
if (hit_count2 != 32'd5) $stop;
if (hit_count3 != 32'd4) $stop;
if (wide_for_count != 32'h80) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> struct BIT { int n; vector<T> dat; BIT(int n = 0) { initialize(n); } void initialize(int nin) { n = nin; dat.resize(n, 0); } T sum(int i) { T s = 0; while (i >= 0) { s += dat[i]; i = (i & (i + 1)) - 1; } return s; } T sum_between(int i, int j) { return sum(j) - sum(i - 1); } void plus(int i, T x) { while (i < n) { dat[i] += x; i |= i + 1; } } int lower_bound(T x) { if (x < 0) return -1; if (sum(n - 1) < x) return n; int ret = -1; int k = 1; while (2 * k <= n) k <<= 1; for (; k > 0; k >>= 1) { if (ret + k < n && dat[ret + k] < x) { x -= dat[ret + k]; ret += k; } } return ret + 1; } }; void solve() { string S; cin >> S; vector<pair<int, int>> D; for (int i = 0; i < int(S.size()) - 1; i++) if (S[i] == S[i + 1]) { D.emplace_back(S[i] - a , i + 1); } int N = D.size(); vector<int> num(26); BIT<int> bit[26], bit_sum(N); for (int k = 0; k < 26; k++) bit[k].initialize(N); for (int i = 0; i < N; i++) { int al = D[i].first; num[al]++; bit[al].plus(i, 1); bit_sum.plus(i, D[i].second - (i ? D[i - 1].second : 0)); } int sum = N; int total = S.size(); vector<pair<int, int>> ans; while (true) { int mx_al = max_element(num.begin(), num.end()) - num.begin(); if (num[mx_al] == sum) break; int fst = bit[mx_al].lower_bound(1); int r = N, l = -1; for (int k = 0; k < 26; k++) if (k != mx_al) { int pos = bit[k].lower_bound(bit[k].sum(fst) + 1); r = min(r, pos); } if (r == N) { r = fst; for (int k = 0; k < 26; k++) if (k != mx_al) { int pos = bit[k].lower_bound(bit[k].sum(fst)); l = max(l, pos); } } else { l = bit[mx_al].lower_bound(bit[mx_al].sum(r)); } int LL = bit_sum.sum(l); int RR = bit_sum.sum(r); ans.emplace_back(LL, RR); bit_sum.plus(l + 1, LL - RR); total -= RR - LL; sum -= 2; num[D[l].first]--; num[D[r].first]--; bit[D[l].first].plus(l, -1); bit[D[r].first].plus(r, -1); } for (int i = 0; i < N; i++) { int s = bit[D[i].first].sum_between(i, i); if (s > 0) { int rem = bit_sum.sum(i); ans.emplace_back(0, rem); bit_sum.plus(0, -rem); total -= rem; } } ans.emplace_back(0, total); printf( %d n , int(ans.size())); for (auto& p : ans) printf( %d %d n , p.first + 1, p.second); } int main() { int T; cin >> T; while (T--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { return a <= b ? true : false; } template <class T> bool uax(T &a, T b) { return a >= b ? true : false; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); cout << fixed; long long H; int n; cin >> H >> n; vector<long long> a(n); long long sum = 0; long long gap = 0; long long h = H; for (int i = 0; i < n; i++) { cin >> a[i]; sum -= a[i]; h += a[i]; if (h <= 0) { cout << i + 1 << endl; return 0; } gap = max(gap, sum); } if (sum <= 0) { cout << -1 << endl; return 0; } long long whole = (H - gap) / sum; H -= whole * sum; long long result = whole * n; for (int i = 0;; i++) { H += a[i % n]; result++; if (H <= 0) { cout << result << endl; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<vector<int>> p; bool is(int val) { int c = 0; vector<bool> pres(n, 0); bool flag = 0; for (int i = 0; i < m; i++) { c = 0; for (int j = 0; j < n; j++) { if (p[i][j] >= val) { pres[j] = true; c++; } } if (c > 1) flag = 1; } if (!flag) return false; bool ans = 1; for (bool i : pres) if (!i) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { cin >> m >> n; p.assign(m, vector<int>(n)); int minn = INT_MAX, maxx; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) cin >> p[i][j]; for (int i = 0; i < n; i++) { maxx = -1; for (int j = 0; j < m; j++) { maxx = max(maxx, p[j][i]); } minn = min(maxx, minn); } int l = 1, r = minn + 3; while (r - l > 1) { int mid = (l + r) / 2; if (is(mid)) l = mid; else r = mid; } cout << l << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int MOD = 998244353; long long int INF = 1e18; long long int vv; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int i, j, k = 0, l = 0, r = 0, m = 0, n, c, p = 0, cnt = 0, cnt1 = 0, x, y, z = 0, a, b, low, mid, high, ans = 0, maxi = 0, mini = INF, t, x1, y1; string s; cin >> s; n = s.size(); queue<long long int> q; long long int V[n]; bool visited[10]; long long int dist[10]; long long int ds[10][10]; for (i = 0; i < n; i++) { k = s[i]; k = k - 48; V[i] = k; } for (i = 0; i <= 9; i++) { for (j = 0; j <= 9; j++) { for (l = 0; l <= 9; l++) { for (r = 0; r <= 9; r++) { ds[l][r] = -1; } } for (l = 0; l <= 9; l++) { for (r = 0; r <= 9; r++) { visited[r] = false; dist[r] = INF; } q.push(l); dist[l] = 0; if (i == 0 || j == 0) { ds[l][l] = 1; visited[l] = true; } while (!q.empty()) { k = q.front(); q.pop(); r = (k + i) % 10; if (visited[r] == false) { visited[r] = true; dist[r] = (dist[k] + 1); ds[l][r] = dist[r]; q.push(r); } r = (k + j) % 10; if (visited[r] == false) { visited[r] = true; dist[r] = (dist[k] + 1); ds[l][r] = dist[r]; q.push(r); } } } cnt = 0; for (l = 0; l < n - 1; l++) { if (ds[V[l]][V[l + 1]] == -1) { cnt = -1; goto last; } else { cnt += ds[V[l]][V[l + 1]] - 1; } } last: cout << cnt << ; } cout << endl; } }
|
/*
module tail_length (clk, reset_n);
input clk;
input reset_n;
// declarations
always @(l0, l1)
begin
l0
l1
end
*/
module tail_length (ir, len);
input [3:0] ir;
output [3:0] len;
reg [3:0] len;
reg ir32;
/*
..00 ..01 ..10 ..11
00.. 1 0 0 0
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
len[0] = (ir[3] & !ir[1]) | (!ir[1] & !ir[0]);
..00 ..01 ..10 ..11
00.. 0 1 0 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[1] = !ir[3] & !ir[2] & !ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 0 0 1 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[2] = !ir[3] & !ir[2] & ir[1] & !ir[0];
..00 ..01 ..10 ..11
00.. 0 0 0 1
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[3] = !ir[3] & !ir[2] & ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 1 2 4 8
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
*/
always @ (ir)
begin
len = {
(ir == 4'b0011),
(ir == 4'b0010),
(ir == 4'b0001),
((ir | 4'b0101) == 4'b1101) | ((ir | 4'b1100) == 4'b1100)
};
end
// 107.89 / 121.08
// always @ (ir)
// begin
// ir32 = |ir[3:2];
// len = {
// (!ir32 & ir[1] & ir[0]),
// (!ir32 & ir[1] & !ir[0]),
// (!ir32 & !ir[1] & ir[0]),
// ((ir[3] & !ir[1]) | (!ir[1] & !ir[0]))
// };
// end
// always @ (ir)
// casez (ir)
// 4'b??00: len = 1;
// 4'b1?0?: len = 1;
// 4'b0001: len = 2;
// 4'b0010: len = 4;
// 4'b0011: len = 8;
// default len = 0;
// endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[100005]; bitset<100005> vis; int nodes = 0, edges = 0; void dfs(int v) { nodes++; vis[v] = true; for (auto nv : adj[v]) { if (!vis[nv]) dfs(nv); edges++; } } int main() { int n, k; scanf( %d%d , &n, &k); int x[k], y[k]; for (int i = 0; i < k; i++) { scanf( %d%d , &x[i], &y[i]); adj[--x[i]].push_back(--y[i]); adj[y[i]].push_back(x[i]); } int sad = 0; for (int i = 0; i < n; i++) { if (!vis[i]) { nodes = 0; edges = 0; dfs(i); edges >>= 1; sad += edges - nodes + 1; } } printf( %d n , sad); }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file blk_mem_gen_v4_2.v when simulating
// the core, blk_mem_gen_v4_2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module blk_mem_gen_v4_2(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [4 : 0] addra;
input [127 : 0] dina;
output [127 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_2 #(
.C_ADDRA_WIDTH(5),
.C_ADDRB_WIDTH(5),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32),
.C_READ_DEPTH_B(32),
.C_READ_WIDTH_A(128),
.C_READ_WIDTH_B(128),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32),
.C_WRITE_DEPTH_B(32),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(128),
.C_WRITE_WIDTH_B(128),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of blk_mem_gen_v4_2 is "black_box"
endmodule
|
//date:2016/3/16
//engineer: zhaishaomin
//module function :test whether dc_download will behave as what i want it to do ,such as handling coming flit correctly
/*
// test examples
//wbrep 11 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,wbrep_cmd,5'b00000,seled_addr,data_read};
//ATflurep 11 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,ATflurep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],data_read};
//shrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//SHexrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//exrep 9 flits long
msg={temp_rep_head_flit,data_read,32'h00000000};
//wbreq 3 flits long
msg={temp_rep_head_flit,seled_addr,128'h0000};
//flushreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//SCinvreq or invreq 3 flits long
msg={temp_req_head_flit,seled_addr,128'h0000};
//shreq 3 flits long
flits_d_m_areg={seled_addr[12:11],1'b0,local_id,1'b1,shreq_cmd,5'b00000,seled_addr,128'hzzzz};
//exreq 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,exreq_cmd,5'b00000,seled_addr,128'hzzzz};
//C2Hinvrep 3 flits long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//flushrep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,local_id,1'b0,flushrep_cmd,5'b00000,seled_addr,128'h0000};
//flushfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,flushfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//wbfail_rep 3 flits long
flits_d_m_areg={flits_in[140:139],1'b1,flits_in[132:131],1'b0,wbfail_rep_cmd,5'b00000,seled_addr,128'h0000};
//nackrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
//C2Cinvrep 1 flit long
flits_d_m_areg={state_tag_out[3:2],1'b0,local_id,1'b1,C2Hinvrep_cmd,5'b00000,
seled_addr[31:13],delayed_state_tag,seled_addr[8:0],128'hzzzz};
//SCflushrep 1 flit long
msg={temp_rep_head_flit,data_read,32'h00000000};
*/
`timescale 1ns/1ps
module tb_dc_download();
//inputs
reg clk;
reg rst;
reg [15:0] IN_flit_dc;
reg v_IN_flit_dc;
reg [1:0] In_flit_ctrl_dc;
reg dc_done_access;
//output
wire v_dc_download;
wire [1:0] dc_downlaod_state;
wire [143:0]dc_download_flits;
//instantiate the uut
dc_download uut(//input
.clk(clk),
.rst(rst),
.IN_flit_dc(IN_flit_dc),
.v_IN_flit_dc(v_IN_flit_dc),
.In_flit_ctrl_dc(In_flit_ctrl_dc),
.dc_done_access(dc_done_access),
//output
.v_dc_download(v_dc_download),
.dc_download_flits(dc_download_flits),
.dc_download_state(dc_download_state)
);
// store the simulation log into log_file
integer logfile;
// Initialize Inputs
initial begin
clk = 1'b0;
rst = 1'b0;
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b0;
In_flit_ctrl_dc=2'b00;
dc_done_access=1'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// mem_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,a rep msg from IN_local_rep fifo come and dc_download should be ready to receive the flits
// note :here are three kinds of reps and reqs totally,
// including :9 flits long msg : exrep , shrep, sh->exrep
// 3 flits long msg : invreq, wbreq, flushreq, scflushreq,
// 1 flit long msg : C2Cinvrep so far.
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 9 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 4th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 5th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 6th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 8th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
`step
// 9th flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg todata cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 3 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
// second flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) TEST ERROR msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
`step
// 3rd flit comes and is usefull for dc_download
IN_flit_dc=16'h1234;
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
/////////////////////////////////////////////////////////////
/////////////FIRST TEST 1 FLITS LONG MSG
//first flit
IN_flit_dc=16'h1234; // condition: IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd
v_IN_flit_dc=1'b1;
In_flit_ctrl_dc=2'b01;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$fdisplay(logfile,"(%t) msg to data cache is :%h,and is vallid :%b ,and dc_download_state is:%b ",$time,dc_download_flits,v_dc_download,dc_download_state);
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; long long power(long long x, long long y) { long long t = 1; while (y > 0) { if (y % 2) y -= 1, t = t * x % mod; else y /= 2, x = x * x % mod; } return t; } long long val[N]; vector<pair<long long, long long> > G[N]; int vk[N]; set<pair<long long, long long> > S[N]; int ans[N]; int tl = 0; void merge(int &p, int nw, long long cs) { if (S[nw].size() == 0) return; set<pair<long long, long long> >::iterator it = S[nw].end(); vector<pair<long long, long long> > z; while (1) { it--; if ((*it).first > cs) { z.push_back(*it); } else break; if (it == S[nw].begin()) break; } for (int i = 0; i < z.size(); ++i) S[nw].erase(z[i]); if (p == -1) { p = nw; return; } if (S[p].size() < S[nw].size()) swap(p, nw); it = S[nw].begin(); while (it != S[nw].end()) { S[p].insert(*it); it++; } } int dfs1(int v, long long c) { int my = -1; for (int i = 0; i < G[v].size(); ++i) { int x = dfs1(G[v][i].first, G[v][i].second + c); merge(my, x, c); } if (my == -1) my = tl++; ans[v] = S[my].size(); S[my].insert(make_pair(c - val[v], v)); return my; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %lld , &val[i]); for (int i = 0; i < n - 1; ++i) { long long x, y; scanf( %lld%lld , &x, &y); x--; G[x].push_back(make_pair(i + 1, y)); } dfs1(0, 0); for (int i = 0; i < n; ++i) printf( %d , ans[i]); printf( n ); return 0; }
|
#include<bits/stdc++.h> using namespace std; long long a[1000010]; bool cmp(long long a,long long b) { return a>b; } int main() { long long m,n,i,j,x,y,suma=0,sumb=0; cin>>n; while(n--) { cin>>m; for(i=0;i<m;i++) cin>>a[i]; sort(a,a+m,cmp); for(i=0;i<m;) { if(a[i]%2==0) suma+=a[i]; i++; if(a[i]%2!=0) sumb+=a[i]; i++; } if(sumb==suma) cout<< Tie <<endl; if(suma>sumb) cout<< Alice <<endl; if(suma<sumb) cout<< Bob <<endl; suma=0; sumb=0; } return 0; }
|
// $Id: router_wrap.v 1730 2009-12-13 08:39:16Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// wrapper around router component (configures router parameters based on
// selected network topology, etc.)
module router_wrap
(clk, reset, router_address, flit_ctrl_in_ip, flit_data_in_ip,
flow_ctrl_out_ip, flit_ctrl_out_op, flit_data_out_op, flow_ctrl_in_op,
error);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
`include "parameters.v"
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flow control signals
localparam flow_ctrl_width = 1 + vc_idx_width;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// control signals for each incoming flit
input [0:num_ports*flit_ctrl_width-1] flit_ctrl_in_ip;
// flit data for each incoming flit
input [0:num_ports*flit_data_width-1] flit_data_in_ip;
// outgoing flow control signals
output [0:num_ports*flow_ctrl_width-1] flow_ctrl_out_ip;
wire [0:num_ports*flow_ctrl_width-1] flow_ctrl_out_ip;
// control signals for each outgoing flit
output [0:num_ports*flit_ctrl_width-1] flit_ctrl_out_op;
wire [0:num_ports*flit_ctrl_width-1] flit_ctrl_out_op;
// flit data for each outgoing flit
output [0:num_ports*flit_data_width-1] flit_data_out_op;
wire [0:num_ports*flit_data_width-1] flit_data_out_op;
// incoming flow control signals
input [0:num_ports*flow_ctrl_width-1] flow_ctrl_in_op;
// internal error condition detected
output error;
wire error;
generate
case(router_type)
`ROUTER_TYPE_WORMHOLE:
begin
whr_top
#(.num_flit_buffers(num_flit_buffers),
.num_header_buffers(num_header_buffers),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.flit_data_width(flit_data_width),
.perf_ctr_enable(perf_ctr_enable),
.perf_ctr_width(perf_ctr_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.routing_type(routing_type),
.dim_order(dim_order),
.header_fifo_type(header_fifo_type),
.input_stage_can_hold(input_stage_can_hold),
.fbf_regfile_type(fbf_regfile_type),
.arbiter_type(sw_alloc_arbiter_type),
.crossbar_type(data_crossbar_type),
.reset_type(reset_type))
whr
(.clk(clk),
.reset(reset),
.router_address(router_address),
.flit_ctrl_in_ip(flit_ctrl_in_ip),
.flit_data_in_ip(flit_data_in_ip),
.flow_ctrl_out_ip(flow_ctrl_out_ip),
.flit_ctrl_out_op(flit_ctrl_out_op),
.flit_data_out_op(flit_data_out_op),
.flow_ctrl_in_op(flow_ctrl_in_op),
.error(error));
end
`ROUTER_TYPE_VC:
begin
vcr_top
#(.num_flit_buffers(num_flit_buffers),
.num_header_buffers(num_header_buffers),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.flit_data_width(flit_data_width),
.perf_ctr_enable(perf_ctr_enable),
.perf_ctr_width(perf_ctr_width),
.error_capture_mode(error_capture_mode),
.track_vcs_at_output(track_vcs_at_output),
.restrict_turns(restrict_turns),
.routing_type(routing_type),
.dim_order(dim_order),
.int_flow_ctrl_type(int_flow_ctrl_type),
.header_fifo_type(header_fifo_type),
.fbf_regfile_type(fbf_regfile_type),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_requires_credit(vc_alloc_requires_credit),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.ctrl_crossbar_type(ctrl_crossbar_type),
.data_crossbar_type(data_crossbar_type),
.reset_type(reset_type))
vcr
(.clk(clk),
.reset(reset),
.router_address(router_address),
.flit_ctrl_in_ip(flit_ctrl_in_ip),
.flit_data_in_ip(flit_data_in_ip),
.flow_ctrl_out_ip(flow_ctrl_out_ip),
.flit_ctrl_out_op(flit_ctrl_out_op),
.flit_data_out_op(flit_data_out_op),
.flow_ctrl_in_op(flow_ctrl_in_op),
.error(error));
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a = 0, b = 0, c, d, e, f = 0, l, g, m, n, k, i, j, t, p, q; cin >> t; while (t--) { cin >> n; f = 0; v.clear(); for (i = 2; f < 2 && i <= sqrt(n) + 1; i++) { if (n % i == 0) { v.push_back(i); n /= i; f++; } } if (v.size() < 2 || n == 1 || n == v[0] || n == v[1]) { cout << NO n ; } else { cout << YES n << v[0] << << v[1] << << n << n ; } } return 0; }
|
//rd0 - 128/64/32 bits wide (can be unaligned)
//rd1 - 32 bits wide
//rd2 - 32 bits wide
//wr0 - 128/64/32 bits wide (4 bit enable) (can be unaligned)
module reg_1024x32b_3r_1w (/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data, clk
);
//innitial test will only include all 32b ops
//keep 128 bit bus for future
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
//10 bit addr -> 1024 locations
input [9:0] rd0_addr;
input [9:0] rd1_addr;
input [9:0] rd2_addr;
input [9:0] wr0_addr;
input [3:0] wr0_en; //extern 4 bit enable [legacy--4 bits determined vector length]
input [31:0] wr0_data;
input clk;
reg [31:0] rd0_data;
reg [31:0] rd1_data;
reg [31:0] rd2_data;
wire [31:0] rd0_data_bank0;
wire [9:0] rd0_addr_last;
wire [9:0] rd1_addr_last;
wire [9:0] rd2_addr_last;
dff rd_addr_data_path_delay[10+10+10-1:0]
(.q({rd0_addr_last, rd1_addr_last, rd2_addr_last}),
.d({rd0_addr, rd1_addr, rd2_addr}),
.clk(clk),
.rst(1'b0));
// Rd data path
always @(rd0_addr_last or rd0_data_bank0)//or rd0_data_bank1 or rd0_data_bank2 or rd0_data_bank3)
begin
//rd0_data <= {{96{1'b0}},rd0_data_bank0};
// S: change to 32b line
rd0_data <= rd0_data_bank0;
end
wire [31:0] rd1_data_bank0;
always @(rd1_addr_last or rd1_data_bank0)// or rd1_data_bank1 or rd1_data_bank2 or rd1_data_bank3)
begin
rd1_data <= rd1_data_bank0;
end
wire [31:0] rd2_data_bank0;
always @(rd2_addr_last or rd2_data_bank0)// or rd2_data_bank1 or rd2_data_bank2 or rd2_data_bank3)
begin
rd2_data <= rd2_data_bank0;
end
`ifdef FPGA_BUILD
reg_256x32b_3r_1w_fpga
`else
reg_256x32b_3r_1w
`endif
bank0(
.rd0_addr(rd0_addr),
.rd0_data(rd0_data_bank0),
.rd1_addr(rd1_addr),
.rd1_data(rd1_data_bank0),
.rd2_addr(rd2_addr),
.rd2_data(rd2_data_bank0),
.wr0_addr(wr0_addr), //connect write address straight in
.wr0_en(wr0_en[0]|wr0_en[1]|wr0_en[2]|wr0_en[3]), //only focus on 32b, so only enable if bottom bit active high
.wr0_data(wr0_data[31:0]),
.clk(clk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, c, ans = 0; string s; cin >> s; bool sol = 1; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 && s[i + 1] == 4 && s[i + 2] == 4 ) { i += 2; continue; } if (s[i] == 1 || (s[i] == 4 && s[i - 1] == 1 )) continue; else sol = 0; } if (sol) cout << YES ; else cout << NO ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_2_V
`define SKY130_FD_SC_HDLL__NAND3_2_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFBBP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; string multiply(string num1, string num2) { int len1 = num1.size(); int len2 = num2.size(); if (len1 == 0 || len2 == 0) return 0 ; vector<int> result(len1 + len2, 0); int i_n1 = 0; int i_n2 = 0; for (int i = len1 - 1; i >= 0; i--) { int carry = 0; int n1 = num1[i] - 0 ; i_n2 = 0; for (int j = len2 - 1; j >= 0; j--) { int n2 = num2[j] - 0 ; int sum = n1 * n2 + result[i_n1 + i_n2] + carry; carry = sum / 10; result[i_n1 + i_n2] = sum % 10; i_n2++; } if (carry > 0) result[i_n1 + i_n2] += carry; i_n1++; } int i = result.size() - 1; while (i >= 0 && result[i] == 0) i--; if (i == -1) return 0 ; string s = ; while (i >= 0) s += std::to_string(result[i--]); return s; } string divide(string number, int divisor) { string ans; int idx = 0; int temp = number[idx] - 0 ; while (temp < divisor) temp = temp * 10 + (number[++idx] - 0 ); while (number.size() > idx) { ans += (temp / divisor) + 0 ; temp = (temp % divisor) * 10 + number[++idx] - 0 ; } if (ans.length() == 0) return 0 ; return ans; } int main() { int spf[100000]; for (int i = 0; i < 100000; ++i) { spf[i] = i; } for (int i = 4; i < 100000; i += 2) { spf[i] = 2; } for (int i = 3; i * i < 100000; ++i) { if (spf[i] == i) { for (int j = i * i; j < 100000; j += i) { if (spf[j] == j) { spf[j] = i; } } } } vector<int> primes; for (int i = 2; i < 100000; ++i) { if (spf[i] == i) { primes.push_back(i); } } int n; cin >> n; if (n == 2) { cout << -1 << endl; return 0; } string ans = 1 ; for (int i = 0; i < n; ++i) { ans = multiply(ans, to_string(primes[i])); } for (int i = 0; i < n; ++i) { cout << divide(ans, primes[i]) << endl; } return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_rxdata (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_TB_V
`define SKY130_FD_SC_HS__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A_N = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A_N = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A_N = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A_N = 1'bx;
end
sky130_fd_sc_hs__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int M = 4; int now[2], dila[2]; int vis[N][4], n, m, cnt, ans_cnt; char s[4]; long long ans; int main() { int i, j, k, *p; bool lose = false; scanf( %d%d%d%d%s , &n, &m, &now[0], &now[1], s); if (s[0] == U ) dila[0] = -1; else dila[0] = 1; if (s[1] == L ) dila[1] = -1; else dila[1] = 1; if (now[0] == 1) vis[now[1]][0]++, cnt++; if (now[0] == n) vis[now[1]][2]++, cnt++; if (now[1] == 1) vis[now[0]][1]++, cnt++; if (now[1] == m) vis[now[0]][3]++, cnt++; ans_cnt += (m - (((now[1] - now[0] + 1) % 2 - 2) % 2 + 2)) / 2 + 1; ans_cnt += (n - (((now[0] - now[1] + 1) % 2 - 2) % 2 + 2)) / 2 + 1; ans_cnt += (m - (((now[1] + (n - now[0])) % 2 - 2) % 2 + 2)) / 2 + 1; ans_cnt += (n - (((now[0] + (m - now[1])) % 2 - 2) % 2 + 2)) / 2 + 1; ans++; while (cnt < ans_cnt && !lose) { k = 0x7fffffff; if (dila[0] == 1) k = min(k, n - now[0]); else k = min(k, now[0] - 1); if (dila[1] == 1) k = min(k, m - now[1]); else k = min(k, now[1] - 1); ans += k; now[0] += dila[0] * k; now[1] += dila[1] * k; if (now[0] == 1) { p = &vis[now[1]][0]; (*p)++; if (*p == 1) cnt++; if (*p > M) lose = true; if (dila[0] == -1) dila[0] = -dila[0]; } if (now[0] == n) { p = &vis[now[1]][2]; (*p)++; if (*p == 1) cnt++; if (*p > M) lose = true; if (dila[0] == 1) dila[0] = -dila[0]; } if (now[1] == 1) { p = &vis[now[0]][1]; (*p)++; if (*p == 1) cnt++; if (*p > M) lose = true; if (dila[1] == -1) dila[1] = -dila[1]; } if (now[1] == m) { p = &vis[now[0]][3]; (*p)++; if (*p == 1) cnt++; if (*p > M) lose = true; if (dila[1] == 1) dila[1] = -dila[1]; } } if (lose) puts( -1 ); else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s1, s2; cin >> s1 >> s2; int n = s1.size(); int m = s2.size(); pair<pair<int, int>, pair<int, char> > parent[n + 1][m + 1][205]; int dp[n + 5][m + 5][205]; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { for (int bal = 0; bal <= 200; bal++) { dp[i][j][bal] = 600; } } } dp[0][0][0] = 0; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { for (int bal = 0; bal <= 200; bal++) { if (dp[i][j][bal] == 600) continue; int newI = i + (i < n && s1[i] == ( ); int newJ = j + (j < m && s2[j] == ( ); if (bal + 1 < 205 && dp[newI][newJ][bal + 1] > dp[i][j][bal] + 1) { dp[newI][newJ][bal + 1] = dp[i][j][bal] + 1; parent[newI][newJ][bal + 1] = make_pair(make_pair(i, j), make_pair(bal, ( )); } newI = i + (i < n && s1[i] == ) ); newJ = j + (j < m && s2[j] == ) ); if (bal > 0 && dp[newI][newJ][bal - 1] > dp[i][j][bal] + 1) { dp[newI][newJ][bal - 1] = dp[i][j][bal] + 1; parent[newI][newJ][bal - 1] = make_pair(make_pair(i, j), make_pair(bal, ) )); } } } } int cBal = 0; for (int bal = 0; bal <= 200; bal++) { if (dp[n][m][bal] + bal < dp[n][m][cBal] + cBal) { cBal = bal; } } int ci = n, cj = m; string res = string(cBal, ) ); while (ci > 0 || cj > 0 || cBal != 0) { int nci = parent[ci][cj][cBal].first.first; int ncj = parent[ci][cj][cBal].first.second; int ncBal = parent[ci][cj][cBal].second.first; res += parent[ci][cj][cBal].second.second; ci = nci; cj = ncj; cBal = ncBal; } reverse(res.begin(), res.end()); cout << res << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:134217728 ) using namespace std; char buf[2]; vector<int> sign; int n; int main() { sign.push_back(1); scanf( %s , buf); while (1) { scanf( %s , buf); if (buf[0] == = ) break; sign.push_back(buf[0] == + ? 1 : -1); scanf( %s , buf); } scanf( %d , &n); int MIN = 0; int MAX = 0; vector<int> res; for (int i = 0; i < sign.size(); ++i) { if (sign[i] == 1) { MIN++; MAX += n; res.push_back(n); } else { MIN -= n; MAX--; res.push_back(1); } } if (MIN <= n && n <= MAX) { printf( Possible n ); int need = MAX - n; for (int i = 0; i < res.size(); ++i) { if (sign[i] == 1) { int d = min(need, res[i] - 1); res[i] -= d; need -= d; } else { int d = min(need, n - res[i]); res[i] += d; need -= d; } } printf( %d , res[0]); for (int i = 1; i < res.size(); ++i) { if (sign[i] == 1) printf( + ); else printf( - ); printf( %d , res[i]); } printf( = %d n , n); } else printf( Impossible n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long K = 1000000000000000000; map<int, int> M; int q, mn, w[600005], nxt[600005], Q[600005], anc[600005], r; char opt[5], s[600005]; long long ans0, ans, g, ansx, ansy; int mask((1 << 30) - 1); int calc(int x) { return w[Q[lower_bound(Q + 1, Q + r + 1, x) - Q]]; } int main() { mn = 1 << 30; scanf( %d , &q); int j(0); for (int i = 1; i <= q; ++i) { scanf( %s%d , opt, &w[i]); s[i] = (ansy + opt[0] - a ) % 26 + a ; w[i] ^= (ansx & mask); mn = min(mn, w[i]); if (i == 1) { printf( %lld n , ans = w[i]); ansx = ans & mask; ansy = w[i] % 26; while (r && w[Q[r]] >= w[i]) --r; Q[++r] = i; continue; } while (j && s[j + 1] != s[i]) j = nxt[j]; if (s[j + 1] == s[i]) ++j; nxt[i] = j; if (s[i] == s[nxt[i - 1] + 1]) anc[i - 1] = anc[nxt[i - 1]]; else anc[i - 1] = nxt[i - 1]; for (int j = (s[i - 1] == s[1] ? i - 1 : nxt[i - 1]); j;) { if (s[j + 1] == s[i]) j = anc[j]; else { int o(calc(i - j)); g -= o; map<int, int>::iterator it = M.lower_bound(o); assert(it != M.end()); --it->second; if (!it->second) M.erase(it); j = nxt[j]; } } while (r && w[Q[r]] >= w[i]) --r; Q[++r] = i; int cnt(s[i] == s[1]); map<int, int>::iterator it = M.lower_bound(w[i]); while (it != M.end()) { g -= (long long)it->first * it->second; cnt += it->second; M.erase(it); it = M.lower_bound(w[i]); } g += (long long)cnt * w[i]; M.insert(make_pair(w[i], cnt)); ans += g, ans += mn; if (ans >= K) ++ans0, ans -= K; ansx = (ansx + g + mn) & mask; ansy = (ansy + g + mn) % 26; if (!ans0) printf( %lld n , ans); else { cout << ans0 << setw(18) << setfill( 0 ) << ans << endl; } } return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_65x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_65x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [64:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [64:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "65"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "65"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 65 0 INPUT NODEFVAL data[64..0]
// Retrieval info: USED_PORT: q 0 0 65 0 OUTPUT NODEFVAL q[64..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 65 0 data 0 0 65 0
// Retrieval info: CONNECT: q 0 0 65 0 @q 0 0 65 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int N = 5002; constexpr int mod = 1e9 + 7; string x, y; int n, m; int cache[N][N]; int dp(int a, int b) { if (b == m) return 0; int &rv = cache[a][b]; if (~rv) return rv; rv = dp(a, b + 1); if (x[a] == y[b]) rv += 1 + dp(a + 1, b + 1), rv %= mod; return rv; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> x >> y; n = x.size(), m = y.size(); memset(cache, -1, sizeof cache); dp(0, 0); int result = 0; for (int i = 0; i < n; i++) result += dp(i, 0), result %= mod; cout << result << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const int N = 1000000 + 10; const int M = 1000; const string st2 = ABCDEFGHIJKLMNOPQRSTUVWXYZ ; const string s1 = abcdefghijklmnopqrstuvwxyz ; pair<int, int> a[N]; int b[N]; string ans[N], da[N]; int main() { cin >> b[1] >> b[2] >> b[3] >> b[4] >> b[5] >> b[6]; int n; cin >> n; da[1] = S ; da[2] = M ; da[3] = L ; da[4] = XL ; da[5] = XXL ; da[6] = XXXL ; for (int i = 1; i <= n; i++) { string second; cin >> second; if (second == S ) a[i] = make_pair(1, 0); else if (second == M ) a[i] = make_pair(2, 0); else if (second == L ) a[i] = make_pair(3, 0); else if (second == XL ) a[i] = make_pair(4, 0); else if (second == XXL ) a[i] = make_pair(5, 0); else if (second == XXXL ) a[i] = make_pair(6, 0); else if (second[0] == S ) a[i] = make_pair(1, 1); else if (second[0] == M ) a[i] = make_pair(2, 1); else if (second[0] == L ) a[i] = make_pair(3, 1); else if (second[1] == L ) a[i] = make_pair(4, 1); else if (second[2] == L ) a[i] = make_pair(5, 1); else a[i] = make_pair(6, 1); } for (int i = 1; i <= n; i++) if (a[i].second == 0) { if (b[a[i].first] != 0) { ans[i] = da[a[i].first]; b[a[i].first]--; } } for (int i = 1; i <= 6; i++) { for (int j = 1; j <= n; j++) if (ans[j] == && a[j].second == 1) { if (a[j].first + 1 == i && b[i] > 0) { b[i]--; ans[j] = da[i]; } } for (int j = 1; j <= n; j++) if (ans[j] == && a[j].second == 1) { if (a[j].first == i && b[i] > 0) { b[i]--; ans[j] = da[i]; } } } for (int i = 1; i <= n; i++) if (ans[i] == ) { cout << NO << endl; return 0; } cout << YES << endl; for (int i = 1; i <= n; i++) cout << ans[i] << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 5005; int n, T; int pp[MAX]; int t[MAX]; double p[MAX]; double ps[MAX]; double pl[MAX]; double dp[2][MAX]; int main(void) { scanf( %d%d , &n, &T); for (int i = (0); i < (n); ++i) scanf( %d%d , pp + i, t + i); for (int i = (0); i < (n); ++i) { p[i] = 0.01 * pp[i]; double cp = 0.0; double lp = p[i]; for (int j = (0); j < (t[i] - 1); ++j) { cp *= (1.0 - p[i]); cp += p[i]; } for (int j = (0); j < (t[i] - 2); ++j) lp *= (1.0 - p[i]); ps[i] = 1.0 - cp; pl[i] = lp; } for (int i = n - 1; i >= 0; --i) { int I = i % 2; dp[I][0] = 0.0; for (int tt = 1; tt <= T; ++tt) { dp[I][tt] = dp[I][tt - 1]; if (t[i] == 1) { dp[I][tt] = 1.0 + dp[I ^ 1][tt - 1]; } else { if (tt - t[i] - 1 >= 0) dp[I][tt] -= ps[i] * (1 + dp[I ^ 1][tt - t[i] - 1]); if (tt - t[i] >= 0) dp[I][tt] -= pl[i] * (1.0 + dp[I ^ 1][tt - t[i]]); dp[I][tt] *= (1.0 - p[i]); dp[I][tt] += p[i] * (1.0 + dp[I ^ 1][tt - 1]); if (tt - t[i] >= 0) dp[I][tt] += ps[i] * (1.0 + dp[I ^ 1][tt - t[i]]); } } } printf( %.10lf n , dp[0][T]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); long long n; cin >> n; long long s = 0; for (int i = 0; i < n; ++i) { long long x; cin >> x; s += x; } long long add = (s - n * (n - 1) / 2) / n; long long cnt = s - (n * (n - 1) / 2 + add * n); for (int i = 0; i < n; ++i) { cout << i + add + int(i < cnt) << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int k, n, fl = 0; cin >> n >> k; v.resize(n); for (int i = 0; i < n; ++i) { cin >> v[i]; if (v[i] == k) fl = 1; } int ct = 0; if (!fl) { v.push_back(k); ct++; ++n; } sort(v.begin(), v.end()); int p, d = 1e9; for (int i = 0; i < v.size(); ++i) { if (k == v[i] && abs((n + 1) / 2 - (i + 1)) < d) { p = i + 1; d = abs((n + 1) / 2 - (i + 1)); } } while (p < (n + 1) / 2) { ++ct; ++p; ++n; } while (p > (n + 1) / 2) { ++ct; ++n; } cout << ct; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_SYMBOL_V
/**
* udp_dff$PR_pp$sN: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_SYMBOL_V
|
/*!
* <b>Module:</b>action_decoder
* @file action_decoder.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
module action_decoder (
input clk,
input enable,
input [10:0] data,
output reg PXSERR_DIAG_X,
output reg SIRQ_DHR,
output reg SIRQ_DP,
output reg SIRQ_DS,
output reg SIRQ_IF,
output reg SIRQ_INF,
output reg SIRQ_PS,
output reg SIRQ_SDB,
output reg SIRQ_TFE,
output reg SIRQ_UF,
output reg PFSM_STARTED,
output reg PCMD_CR_CLEAR,
output reg PCMD_CR_SET,
output reg PXCI0_CLEAR,
output reg PXSSTS_DET_1,
output reg SSTS_DET_OFFLINE,
output reg SCTL_DET_CLEAR,
output reg HBA_RST_DONE,
output reg SET_UPDATE_SIG,
output reg UPDATE_SIG,
output reg UPDATE_ERR_STS,
output reg UPDATE_PIO,
output reg UPDATE_PRDBC,
output reg CLEAR_BSY_DRQ,
output reg CLEAR_BSY_SET_DRQ,
output reg SET_BSY,
output reg SET_STS_7F,
output reg SET_STS_80,
output reg XFER_CNTR_CLEAR,
output reg DECR_DWCR,
output reg DECR_DWCW,
output reg FIS_FIRST_FLUSH,
output reg CLEAR_CMD_TO_ISSUE,
output reg DMA_ABORT,
output reg DMA_PRD_IRQ_CLEAR,
output reg XMIT_COMRESET,
output reg SEND_SYNC_ESC,
output reg SET_OFFLINE,
output reg R_OK,
output reg R_ERR,
output reg EN_COMINIT,
output reg FETCH_CMD,
output reg ATAPI_XMIT,
output reg CFIS_XMIT,
output reg DX_XMIT,
output reg GET_DATA_FIS,
output reg GET_DSFIS,
output reg GET_IGNORE,
output reg GET_PSFIS,
output reg GET_RFIS,
output reg GET_SDBFIS,
output reg GET_UFIS);
always @(posedge clk) begin
PXSERR_DIAG_X <= enable && data[ 1] && data[ 0];
SIRQ_DHR <= enable && data[ 2] && data[ 0];
SIRQ_DP <= enable && data[ 3] && data[ 0];
SIRQ_DS <= enable && data[ 4] && data[ 0];
SIRQ_IF <= enable && data[ 5] && data[ 0];
SIRQ_INF <= enable && data[ 6] && data[ 0];
SIRQ_PS <= enable && data[ 7] && data[ 0];
SIRQ_SDB <= enable && data[ 8] && data[ 0];
SIRQ_TFE <= enable && data[ 9] && data[ 0];
SIRQ_UF <= enable && data[10] && data[ 0];
PFSM_STARTED <= enable && data[ 2] && data[ 1];
PCMD_CR_CLEAR <= enable && data[ 3] && data[ 1];
PCMD_CR_SET <= enable && data[ 4] && data[ 1];
PXCI0_CLEAR <= enable && data[ 5] && data[ 1];
PXSSTS_DET_1 <= enable && data[ 6] && data[ 1];
SSTS_DET_OFFLINE <= enable && data[ 7] && data[ 1];
SCTL_DET_CLEAR <= enable && data[ 8] && data[ 1];
HBA_RST_DONE <= enable && data[ 9] && data[ 1];
SET_UPDATE_SIG <= enable && data[10] && data[ 1];
UPDATE_SIG <= enable && data[ 3] && data[ 2];
UPDATE_ERR_STS <= enable && data[ 4] && data[ 2];
UPDATE_PIO <= enable && data[ 5] && data[ 2];
UPDATE_PRDBC <= enable && data[ 6] && data[ 2];
CLEAR_BSY_DRQ <= enable && data[ 7] && data[ 2];
CLEAR_BSY_SET_DRQ <= enable && data[ 8] && data[ 2];
SET_BSY <= enable && data[ 9] && data[ 2];
SET_STS_7F <= enable && data[10] && data[ 2];
SET_STS_80 <= enable && data[ 4] && data[ 3];
XFER_CNTR_CLEAR <= enable && data[ 5] && data[ 3];
DECR_DWCR <= enable && data[ 6] && data[ 3];
DECR_DWCW <= enable && data[ 7] && data[ 3];
FIS_FIRST_FLUSH <= enable && data[ 8] && data[ 3];
CLEAR_CMD_TO_ISSUE <= enable && data[ 9] && data[ 3];
DMA_ABORT <= enable && data[10] && data[ 3];
DMA_PRD_IRQ_CLEAR <= enable && data[ 5] && data[ 4];
XMIT_COMRESET <= enable && data[ 6] && data[ 4];
SEND_SYNC_ESC <= enable && data[ 7] && data[ 4];
SET_OFFLINE <= enable && data[ 8] && data[ 4];
R_OK <= enable && data[ 9] && data[ 4];
R_ERR <= enable && data[10] && data[ 4];
EN_COMINIT <= enable && data[ 6] && data[ 5];
FETCH_CMD <= enable && data[ 7] && data[ 5];
ATAPI_XMIT <= enable && data[ 8] && data[ 5];
CFIS_XMIT <= enable && data[ 9] && data[ 5];
DX_XMIT <= enable && data[10] && data[ 5];
GET_DATA_FIS <= enable && data[ 7] && data[ 6];
GET_DSFIS <= enable && data[ 8] && data[ 6];
GET_IGNORE <= enable && data[ 9] && data[ 6];
GET_PSFIS <= enable && data[10] && data[ 6];
GET_RFIS <= enable && data[ 8] && data[ 7];
GET_SDBFIS <= enable && data[ 9] && data[ 7];
GET_UFIS <= enable && data[10] && data[ 7];
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_stub.v
// Design : pikachu_down_pixel
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module pikachu_down_pixel(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 50; const int mod = 1e9 + 7; const int inf = (1 << 30); vector<int> v[maxn][5], tpl; int ted[maxn], com[maxn], tmp = 1; bool visited[maxn]; bool dfs(int u, int d) { visited[u] = 1; bool rz = (ted[com[u]] == 1); if (d == 1) { com[u] = tmp; ted[tmp]++; } for (auto w : v[u][d]) { if (!visited[w]) { rz &= dfs(w, d); } } if (d == 0) tpl.push_back(u); return rz; } bool dfs1(int u) { visited[u] = 1; bool rz = (ted[com[u]] == 1); for (auto w : v[u][0]) if (!visited[w]) rz &= dfs1(w); for (auto w : v[u][1]) if (!visited[w]) rz &= dfs1(w); return rz; } int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int a, b; cin >> a >> b; v[a][0].push_back(b); v[b][1].push_back(a); } for (int i = 1; i <= n; i++) if (!visited[i]) dfs(i, 0); memset(visited, 0, sizeof visited); for (int i = n - 1; i >= 0; i--) { int u = tpl[i]; if (!visited[u]) { dfs(u, 1); tmp++; } } memset(visited, 0, sizeof visited); long long ans = n; for (int i = 1; i <= n; i++) { if (!visited[i]) { bool k = dfs1(i); ans -= k; } } cout << ans << endl; }
|
`timescale 1ns / 1ps
module crc #(
parameter POLYNOMIAL = 5'b00101,
parameter DATA_WIDTH = 8,
parameter CRC_WIDTH = 5,
parameter SEED = 0,
parameter DEBUG = 0,
parameter REVERSE = 1
)(
input [DATA_WIDTH-1:0] data,
input data_enable,
output reg [CRC_WIDTH-1:0] crc_out,
input init,
input clock,
input reset
);
function automatic prev;
input integer level;
input integer index;
input [DATA_WIDTH-1:0] data;
input [CRC_WIDTH-1:0] crc;
begin
if (POLYNOMIAL[index])
begin
if (level)
begin
if (index)
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ crc[%0d] ^ data[%0d]", level, index, (index)?index-1:CRC_WIDTH-1, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = prev(level-1, (index)?index-1:CRC_WIDTH-1, data, crc) ^ prev(level-1, CRC_WIDTH-1, data, crc) ^ data[DATA_WIDTH-1-level];
end
else
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ data[%0d]", level, index, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = prev(level-1, CRC_WIDTH-1, data, crc) ^ data[DATA_WIDTH-1-level];
end
end
else
begin
if (index)
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ crc[%0d] ^ data[%0d] // STOP", level, index, index-1, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = crc[index-1-:1] ^ crc[CRC_WIDTH-1-:1] ^ data[DATA_WIDTH-1-level];
end
else
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ data[%0d] // STOP", level, index, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = crc[CRC_WIDTH-1-:1] ^ data[DATA_WIDTH-1-level];
end
end
end
else
begin
if (level)
begin
if (index)
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d]", level, index, index - 1);
prev = prev(level-1, index-1, data, crc);
end
else
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ data[%0d]", level, index, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = prev(level-1, CRC_WIDTH-1, data, crc) ^ data[DATA_WIDTH-1-level];
end
end
else
begin
if (index)
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] // STOP", level, index, index - 1);
prev = crc[index-1-:1];
end
else
begin
if (DEBUG)
$display("LEVEL %0d | crc[%0d] = crc[%0d] ^ data[%0d] // STOP", level, index, CRC_WIDTH-1, DATA_WIDTH - 1 - level);
prev = crc[CRC_WIDTH-1-:1] ^ data[DATA_WIDTH-1-level];
end
end
end
end
endfunction
wire [DATA_WIDTH-1:0] temp;
genvar j;
generate
if (REVERSE)
begin
for (j = DATA_WIDTH-1; j >= 0; j = j - 1)
begin : reverse_loop
assign temp[DATA_WIDTH-1-j] = data[j];
end
end
else
begin
assign temp = data;
end
endgenerate
genvar i;
generate
for(i = 0; i < CRC_WIDTH; i= i + 1)
begin : loop
always @(posedge clock)
begin
if (reset)
begin
crc_out[i+:1] = SEED[i+:1];
end
else if (init)
begin
crc_out[i+:1] = SEED[i+:1];
end
else if (data_enable)
begin
if (DEBUG)
$display("\n\nCRC OUT[%0d]\n***************************************************************************", i);
crc_out[i+:1] <= prev(DATA_WIDTH-1,i,temp,crc_out);
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int mpow(int base, int exp); void ipgraph(int m); void dfs(int u, int par); const int mod = 1000000007; const int N = 1e6, M = N; const int LN = 1e9; long long dir[4][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } struct cmp { bool operator()(const pair<int, int> &a, const pair<int, int> &b) { int len1 = a.second - a.first + 1; int len2 = b.second - b.first + 1; if (len1 == len2) { return a.first < b.first; } return len1 > len2; } }; long long fac[N], inv[N], b[N]; int mpow(int base, int exp) { base %= mod; int result = 1; while (exp > 0) { if (exp & 1) result = ((long long)result * base) % mod; base = ((long long)base * base) % mod; exp >>= 1; } return result; } void pre() { int i; fac[0] = inv[0] = 1; fac[1] = inv[1] = 1; for (i = 2; 2 < N ? i < N : i > N; 2 < N ? i += 1 : i -= 1) { fac[i] = (i * fac[i - 1]) % mod; inv[i] = (mpow(i, mod - 2) * inv[i - 1]) % mod; } } long long C(int n, int r) { if (r > n) return 0; long long ans = fac[n]; ans *= inv[r]; ans %= mod; ans *= inv[n - r]; ans %= mod; return ans; } long long n; vector<vector<int>> arr(50, vector<int>(50)); vector<int> permutation; int chosen[100] = {0}; long long power(long long a, long long b) { long long ans = 1; while (b--) ans *= a; return ans; } long long k; long long dp[N][2]; vector<int> adj[N]; long long m; void solve() { long long a, b, c, p = 0, q, d, r, s, l, t, x, h, y, z, avg, x1, x2, y1, y2, i, j, ii, jj, count = 0; string s1, s2 = , sa = , sb = , sc = , ans = ; cin >> a >> b >> c; if (a >= c) { cout << -1 << ; } else { cout << 1 << ; } if (c < a * b) { cout << b << endl; } else cout << -1 << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; t = 1; cin >> t; while (t--) { solve(); } }
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// OmniVision Serial Camera Control Bus (SCCB (a.k.a I2C)) controller.
//
// Supports both 3-Phase writes and 2-phase write/reads.
//
//##################################################################################################
`timescale 1ns / 1ps
module SCCBCtrl (clk_i, rst_i, sccb_clk_i, data_pulse_i, addr_i, data_i, data_o, rw_i, start_i, ack_error_o,
done_o, sioc_o, siod_io);
input clk_i; // Main clock.
input rst_i; // Reset.
input sccb_clk_i; // SCCB clock. Typical - 100KHz as per SCCB spec.
input data_pulse_i; // Negative mid sccb_clk_i cycle pulse.
input [7:0] addr_i; // Device ID. Bit 0 is ignored since read/write operation is specified by rw_i.
input [15:0] data_i; // Register address in [15:8] and data to write in [7:0] if rw_i = 1 (write).
// Register address in [15:8] if rw_i = 0 (read).
output reg [7:0] data_o; // Data received if rw_i = 0 (read).
input rw_i; // 0 - read command. 1 - write command.
input start_i; // Start transaction.
output ack_error_o; // Error occurred during the transaction.
output reg done_o; // 0 - transaction is in progress. 1 - transaction has completed.
output sioc_o; // SIOC line.
inout siod_io; // SIOD line. External pull-up resistor required.
reg sccb_stm_clk = 1;
reg [6:0] stm = 0;
reg bit_out = 1;
reg ack_err1 = 1;
reg ack_err2 = 1;
reg ack_err3 = 1;
assign sioc_o = (start_i == 1 &&
(stm >= 5 && stm <= 12 || stm == 14 ||
stm >= 16 && stm <= 23 || stm == 25 ||
stm >= 27 && stm <= 34 || stm == 36 ||
stm >= 44 && stm <= 51 || stm == 53 ||
stm >= 55 && stm <= 62 || stm == 64)) ? sccb_clk_i : sccb_stm_clk;
// Output acks and read data only.
assign siod_io = (stm == 13 || stm == 14 || stm == 24 || stm == 25 || stm == 35 || stm == 36 ||
stm == 52 || stm == 53 || stm >= 54 && stm <= 62) ? 1'bz : bit_out;
assign ack_error_o = ack_err1 | ack_err2 | ack_err3;
always @(posedge clk_i or negedge rst_i) begin
if(rst_i == 0) begin
stm <= 0;
sccb_stm_clk <= 1;
bit_out <= 1;
data_o <= 0;
done_o <= 0;
ack_err1 <= 1;
ack_err2 <= 1;
ack_err3 <= 1;
end else if (data_pulse_i) begin
if (start_i == 0 || done_o == 1) begin
stm <= 0;
end else if (rw_i == 0 && stm == 25) begin
stm <= 37;
end else if (rw_i == 1 && stm == 36) begin
stm <= 65;
end else if (stm < 68) begin
stm <= stm + 1;
end
if (start_i == 1) begin
(* parallel_case *) case(stm)
// Initialize
7'd0 : bit_out <= 1;
7'd1 : bit_out <= 1;
// Start write transaction.
7'd2 : bit_out <= 0;
7'd3 : sccb_stm_clk <= 0;
// Write device`s ID address.
7'd4 : bit_out <= addr_i[7];
7'd5 : bit_out <= addr_i[6];
7'd6 : bit_out <= addr_i[5];
7'd7 : bit_out <= addr_i[4];
7'd8 : bit_out <= addr_i[3];
7'd9 : bit_out <= addr_i[2];
7'd10: bit_out <= addr_i[1];
7'd11: bit_out <= 0;
7'd12: bit_out <= 0;
7'd13: ack_err1 <= siod_io;
7'd14: bit_out <= 0;
// Write register address.
7'd15: bit_out <= data_i[15];
7'd16: bit_out <= data_i[14];
7'd17: bit_out <= data_i[13];
7'd18: bit_out <= data_i[12];
7'd19: bit_out <= data_i[11];
7'd20: bit_out <= data_i[10];
7'd21: bit_out <= data_i[9];
7'd22: bit_out <= data_i[8];
7'd23: bit_out <= 0;
7'd24: ack_err2 <= siod_io;
7'd25: bit_out <= 0;
// Write data. This concludes 3-phase write transaction.
7'd26: bit_out <= data_i[7];
7'd27: bit_out <= data_i[6];
7'd28: bit_out <= data_i[5];
7'd29: bit_out <= data_i[4];
7'd30: bit_out <= data_i[3];
7'd31: bit_out <= data_i[2];
7'd32: bit_out <= data_i[1];
7'd33: bit_out <= data_i[0];
7'd34: bit_out <= 0;
7'd35: ack_err3 <= siod_io;
7'd36: bit_out <= 0;
// Stop transaction.
7'd37: sccb_stm_clk <= 0;
7'd38: sccb_stm_clk <= 1;
7'd39: bit_out <= 1;
// Start read tranasction. At this point register address has been set in prev write transaction.
7'd40: sccb_stm_clk <= 1;
7'd41: bit_out <= 0;
7'd42: sccb_stm_clk <= 0;
// Write device`s ID address.
7'd43: bit_out <= addr_i[7];
7'd44: bit_out <= addr_i[6];
7'd45: bit_out <= addr_i[5];
7'd46: bit_out <= addr_i[4];
7'd47: bit_out <= addr_i[3];
7'd48: bit_out <= addr_i[2];
7'd49: bit_out <= addr_i[1];
7'd50: bit_out <= 1;
7'd51: bit_out <= 0;
7'd52: ack_err3 <= siod_io;
7'd53: bit_out <= 0;
// Read register value. This concludes 2-phase read transaction.
7'd54: bit_out <= 0;
7'd55: data_o[7] <= siod_io;
7'd56: data_o[6] <= siod_io;
7'd57: data_o[5] <= siod_io;
7'd58: data_o[4] <= siod_io;
7'd59: data_o[3] <= siod_io;
7'd60: data_o[2] <= siod_io;
7'd61: data_o[1] <= siod_io;
7'd62: data_o[0] <= siod_io;
7'd63: bit_out <= 1;
7'd64: bit_out <= 0;
// Stop transaction.
7'd65: sccb_stm_clk <= 0;
7'd66: sccb_stm_clk <= 1;
7'd67: begin
bit_out <= 1;
done_o <= 1;
end
default: sccb_stm_clk <= 1;
endcase
end else begin
sccb_stm_clk <= 1;
bit_out <= 1;
data_o <= data_o;
done_o <= 0;
ack_err1 <= 1;
ack_err2 <= 1;
ack_err3 <= 1;
end
end
end
endmodule
|
#pragma GCC optimize( Ofast ) #include <iostream> #include <fstream> #include <algorithm> #include <functional> #include <array> #include <chrono> #include <random> #include <vector> #include <string> #include <sstream> #include <cmath> #include <cstring> #include <bitset> #include <list> #include <stack> #include <queue> #include <set> #include <map> #include <cassert> #define sq(x) ((x) * (x)) #define err(x) cerr << [ #x ] << (x) << n ; #define errp(x) cerr << [ #x ] { << ((x).first) << , << ((x).second) << } n ; #define errv(x) {cerr << [ #x ] [ ;for(const auto& ___ : (x)) cerr << ___ << , ; cerr << ] n ;} #define errvn(x, n) {cerr << [ #x ] [ ;for(auto ___ = 0; ___ < (n); ++___) cerr << (x)[___] << , ; cerr << ] n ;} #define errf() cerr << n n ; using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); ll getrnd(ll l, ll r) { return uniform_int_distribution<ll>(l, r)(rng); } template <typename T1, typename T2> inline bool relax(T1& a, const T2& b) { return a > b ? a = b, true : false; } template <typename T1, typename T2> inline bool strain(T1& a, const T2& b) { return a < b ? a = b, true : false; } // ::::::::::::::::::::::::::::::: void solve() { int n; cin >> n; int x = 0; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; x ^= a[i]; } int cur = 0; for (int i = 0; i < n; ++i) { cur ^= a[i]; if (cur == (x ^ cur)) { cout << YES n ; return; } } cur = 0; for (int i = 0; i < n; ++i) { cur ^= a[i]; int sec = 0; for (int j = i + 1; j < n - 1; ++j) { sec ^= a[j]; if (cur == sec && sec == (cur ^ sec ^ x)) { cout << YES n ; return; } } } cout << NO n ; } int main() { ios::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); int t = 1; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[90]; void error() { cout << -1 << endl; exit(0); } int main() { int n, m, l = 1, r; scanf( %d%d n , &n, &m); r = n; while (m--) { int v; scanf( To the %s of %d n , s, &v); if (!strcmp(s, left )) { if (l >= v) error(); if (r >= v) r = v - 1; } else { if (r <= v) error(); if (l <= v) l = v + 1; } } cout << r - l + 1 << endl; return 0; }
|
//
// Copyright (c) 2001 Stephan Gehring
//
// (Modified by Stephan Williams to include PASS/FAIL messages.)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [7:0] x;
initial begin
x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz
if (x !== 8'hxx) begin
$display("FAILED -- x = %b", x);
$finish;
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/06/2015 11:20:11 PM
// Design Name:
// Module Name: bin_to_bcd_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bin_to_bcd_tb;
reg [10:0] bin;
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire [3:0] thousands;
bin_to_bcd U0(
.bin(bin),
.ones(ones),
.tens(tens),
.hundreds(hundreds),
.thousands(thousands)
);
integer i;
reg success_flag;
initial begin
#10
bin = 0;
#10
bin = 321;
#10
bin = 2020;
#10
bin = 1234;
#10
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED** TEST!");
end
else begin
$display("**PASSED** TEST!");
end
#10 $stop;
#5 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1002][102]; int main() { int n, m, k, x; cin >> n >> m >> k; cout << m * (m - 1) / 2 << endl; for (int i = 0; i < m; i++) { for (int j = i + 1; j < m; j++) { if (!k) cout << i + 1 << << j + 1 << endl; else cout << j + 1 << << i + 1 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int x1, yy1, r1, R1; int x2, y2, r2, R2; int dis; inline bool inside(int r, int R) { double dist = sqrt((double)dis); if (dist <= double(R - r)) return true; return false; } inline bool outside(int r, int R) { double dist = sqrt((double)dis); if (dist >= double(R + r)) return true; return false; } int main() { scanf( %d%d%d%d , &x1, &yy1, &r1, &R1); scanf( %d%d%d%d , &x2, &y2, &r2, &R2); dis = (x1 - x2) * (x1 - x2) + (yy1 - y2) * (yy1 - y2); if (R1 > R2) { swap(x1, x2); swap(yy1, y2); swap(r1, r2); swap(R1, R2); } int ans = 0; if (inside(r1, r2) || outside(r1, R2)) ans++; if (inside(R1, r2) || outside(R1, R2)) ans++; if (inside(R1, r2) || inside(r2, r1) || outside(r2, R1)) ans++; if (inside(R1, R2) || outside(R1, R2)) ans++; printf( %d , ans); return 0; }
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* $Id: sqrt-virtex.v,v 1.5 2007/03/22 16:08:18 steve Exp $"
*/
/*
* This module is a synthesizable square-root function. It is also a
* detailed example of how to target Xilinx Virtex parts using
* Icarus Verilog. In fact, for no particular reason other than to
* be excessively specific, I will step through the process of
* generating a design for a Spartan-II XC2S15-VQ100, and also how to
* generate a generic library part for larger Virtex designs.
*
* In addition to Icarus Verilog, you will need implementation
* software from Xilinx. As of this writing, this example was tested
* with Foundation 4.2i, but it should work the same with ISE and
* WebPACK software.
*
* This example source contains all the Verilog needed to do
* everything described below. We use conditional compilation to
* select the bits of Verilog that are needed to perform each specific
* task.
*
* SIMULATE THE DESIGN
*
* This source file includes a simulation test bench. To compile the
* program to include this test bench, use the command line:
*
* iverilog -DSIMULATE=1 -oa.out sqrt-virtex.v
*
* This generates the file "a.out" that can then be executed with the
* command:
*
* vvp a.out
*
* This causes the simulation to run a long set of example sqrt
* calculations. Each result is checked by the test bench to assure
* that the result is valid. When it is done, the program prints
* "PASSED" and finishes the simulation.
*
* When you take a close look at the "main" module below, you will see
* that it uses Verilog constructs that are not synthesizable. This
* is fine, as we will never try to synthesize it.
*
* LIBRARY PARTS
*
* One can use the sqrt32 module to generate an EDIF file suitable for
* use as a library part. This part can be imported to the Xilinx
* schematic editor, then placed like any other pre-existing
* macro. One can also pass the generated EDIF as a precompiled macro
* that other designers may use as they see fit.
*
* To make an EDIF file from the sqrt32 module, execute the command:
*
* iverilog -osqrt32.edf -tfpga -parch=virtex sqrt-virtex.v
*
* The -parch=virtex tells the code generator to generate code for the
* virtex architecture family (we don't yet care what specific part)
* and the -osqrt32.edf places the output into the file
* sqrt32.edf.
*
* Without any preprocessor directives, the only module is the sqrt32
* module, so sqrt32 is compiled as the root. The ports of the module
* are automatically made into ports of the sqrt32.edf netlist, and
* the contents of the sqrt32 module are connected appropriately.
*
* COMPLETE CHIP DESIGNS
*
* To make a complete chip design, there are other bits that need to
* be accounted for. Signals must be assigned to pins, and some
* special devices may need to be created. We also want to write into
* the EDIF file complete part information so that the implementation
* tools know how to route the complete design. The command to compile
* for our target part is:
*
* iverilog -ochip.edf -tfpga \
* -parch=virtex -ppart=XC2S15-VQ100 \
* -DMAKE_CHIP=1 sqrt-virtex.v
*
* This command uses the "chip" module as the root. This module in
* turn has ports that are destined to be the pins of the completed
* part. The -ppart= option gives complete part information, that is
* in turn written into the EDIF file. This saves us the drudgery of
* repeating that part number for later commands.
*
* The next steps involve Xilinx software, and to talk to Xilinx
* software, the netlist must be in the form of an "ngd" file, a
* binary netlist format. The command:
*
* ngdbuild chip.edf chip.ngd
*
* does the trick. The input to ngdbuild is the chip.edf file created
* by Icarus Verilog, and the output is the chip.ngd file that the
* implementation tools may read. From this point, it is best to refer
* to Xilinx documentation for the software you are using, but the
* quick summary is:
*
* map -o map.ncd chip.ngd
* par -w map.ncd chip.ncd
*
* The result of this sequence of commands is the chip.ncd file that
* is ready to be viewed by FPGA Edit, or converted to a bit stream,
* or whatever.
*
* POST MAP SIMULATION
*
* Warm fuzzies are good, and retesting your design after the part
* is mapped by the Xilinx backend tools is a cheap source of fuzzies.
* The command to make a Verilog file out of the mapped design is:
*
* ngd2ver chip.ngd chip_root.v
*
* This command creates from the chip.ngd the file "chip_root.v" that
* contains Verilog code that simulates the mapped design. This output
* Verilog has the single root module "chip_root", which came from the
* name of the root module when we were making the EDIF file in the
* first place. The module has ports named just line the ports of the
* chip_root module below.
*
* The generated Verilog uses the library in the directory
* $(XILINX)/verilog/src/simprims. This directory comes with the ISE
* WebPACK installation that you are using. Icarus Verilog is able to
* simulate using that library.
*
* To compile a post-map simulation of the chip_root.v, use the
* command:
*
* iverilog -DSIMULATE -DPOST_MAP -ob.out \
* -y $(XILINX)/verilog/src/simprims \
* sqrt-virtex.v chip_root.v \
* $(XILINX)/verilog/src/glbl.v
*
* This command line generates b.out from the source files
* sqrt-virtex.v and chip_root.v (the latter from ngd2ver)
* and the "-y <path>" flag specifies the library directory that will
* be needed. The glbl.v source file is also included to provide the
* GSR and related signals.
*
* The POST_MAP compiler directive causes the GSR manipulations
* included in the test bench to be compiled in, to simulate the chip
* startup. Other than that, the test bench runs the post-map design
* the same way the pre-synthesis design works.
*
* Run this design with the command:
*
* vvp b.out
*
* And there you go.
*/
`ifndef POST_MAP
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* too big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
* x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32 bit numbers, this will never run more than 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] acc;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [31:0] acc2;
// Keep track of which bit I'm working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [31:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
(* ivl_synthesis_on *)
always @(posedge clk or posedge reset)
if (reset) begin
acc = 0;
acc2 = 0;
bitl = 15;
end else begin
if (guess2 <= x) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 5'd1;
end
endmodule // sqrt32
`endif // `ifndef POST_MAP
`ifdef SIMULATE
/*
* This module is a test bench for the sqrt32 module. It runs some
* test input values through the sqrt32 module, and checks that the
* output is valid. If an invalid output is generated, print and
* error message and stop immediately. If all the tested values pass,
* then print PASSED after the test is complete.
*/
module main;
reg [31:0] x;
reg clk, reset;
wire [15:0] y;
wire rdy;
`ifdef POST_MAP
chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
`else
sqrt32 dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
`endif
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut;
begin
reset = 1;
@(posedge clk) ;
#1 reset = 0;
@(negedge clk) ;
end
endtask // reset_dut
task crank_dut;
begin
while (rdy == 0) begin
@(posedge clk) /* wait */;
end
end
endtask // crank_dut
`ifdef POST_MAP
reg GSR;
assign glbl.GSR = GSR;
`endif
integer idx;
(* ivl_synthesis_off *)
initial begin
reset = 0;
clk = 0;
/* If doing a post-map simulation, when we need to wiggle
The GSR bit to simulate chip power-up. */
`ifdef POST_MAP
GSR = 1;
#100 GSR = 0;
`endif
#100 x = 1;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 3;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 4;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
for (idx = 0 ; idx < 200 ; idx = idx + 1) begin
x = $random;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
if (x < (y * y)) begin
$display("ERROR: y is too big");
$finish;
end
if (x > ((y + 1)*(y + 1))) begin
$display("ERROR: y is too small");
$finish;
end
end
$display("PASSED");
$finish;
end
endmodule // main
`endif
`ifdef MAKE_CHIP
/*
* This module represents the chip packaging that we intend to
* generate. We bind pins here, and route the clock to the global
* clock buffer.
*/
module chip_root(clk, rdy, reset, x, y);
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] y;
wire clk_int;
(* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk);
sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
/* Assign the clk to GCLK0, which is on pin P39. */
$attribute(clk, "PAD", "P39");
// We don't care where the remaining pins go, so set the pin number
// to 0. This tells the implementation tools that we want a PAD,
// but we don't care which. Also note the use of a comma (,)
// separated list to assign pins to the bits of a vector.
$attribute(rdy, "PAD", "0");
$attribute(reset, "PAD", "0");
$attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
$attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
endmodule // chip_root
`endif
|
#include <bits/stdc++.h> using namespace std; int n; long long int aib[15][100005]; inline void update(long long int aib[], int pos, long long int val) { for (; pos <= n; pos += ((pos) & (-(pos)))) aib[pos] += val; } inline long long int query(long long int aib[], int pos) { long long int ans = 0; for (; pos; pos -= ((pos) & (-(pos)))) ans += aib[pos]; return ans; } long long int dp[15][100005]; int main() { ios_base ::sync_with_stdio(false); int k; cin >> n >> k; ++k; long long int ans = 0; int val; for (int i = 1; i <= n; ++i) { cin >> val; dp[1][i] = val; update(aib[1], val, 1); for (int j = 2; j <= k; ++j) { dp[j][i] = query(aib[j - 1], val - 1); update(aib[j], val, dp[j][i]); } ans += dp[k][i]; } cout << ans << n ; return 0; }
|
//oob_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module oob_controller (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output reg platform_error, //Underlyaing physal platform received an error, this should probably be a reset
output reg linkup, //link is finished
output reg tx_comm_reset, //send a init OOB signal
output reg tx_comm_wake, //send a wake OOB signal
input tx_oob_complete, //Phy has said we are finished with this OOB transaction
input comm_init_detect, //detected an init
input comm_wake_detect, //detected a wake on the rx lines
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input rx_byte_is_aligned,
input phy_error,
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output [3:0] lax_state
);
//platform signals
//Parameters
//States
parameter IDLE = 4'h0;
parameter SEND_RESET = 4'h1;
parameter WAIT_FOR_INIT = 4'h2;
parameter WAIT_FOR_NO_INIT = 4'h3;
parameter WAIT_FOR_CONFIGURE_END = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter WAIT_FOR_WAKE = 4'h6;
parameter WAIT_FOR_NO_WAKE = 4'h7;
parameter WAIT_FOR_IDLE = 4'h8;
parameter WAIT_FOR_ALIGN = 4'h9;
parameter SEND_ALIGN = 4'hA;
parameter DETECT_SYNC = 4'hB;
parameter READY = 4'hC;
//Registers/Wires
reg [3:0] state;
reg [31:0] timer;
reg [1:0] no_align_count;
reg [3:0] retries;
//timer used to send 'INITs', WAKEs' and read them
wire timeout;
wire align_detected;
wire sync_detected;
//Submodules
//Asynchronous Logic
assign timeout = (timer == 0);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
assign sync_detected = ((rx_is_k > 0) && (rx_din == `PRIM_SYNC));
assign lax_state = state;
//Synchronous Logic
initial begin
tx_set_elec_idle <= 1;
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
linkup <= 0;
timer <= 0;
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
no_align_count <= 0;
platform_error <= 0;
retries <= 0;
end
else begin
//to support strobes, continuously reset the following signals
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_is_k <= 0;
//timer (when reache 0 timeout has occured)
if (timer > 0) begin
timer <= timer - 1;
end
//main state machine, if this reaches ready an initialization sequence has completed
case (state)
IDLE: begin
platform_error <= 0;
linkup <= 0;
tx_set_elec_idle <= 1;
if (platform_ready) begin
$display ("oob_controller: send RESET");
//the platform is ready
// PLL has locked onto a clock
// DCM has generated the correct clocks
timer <= 32'h000000A2;
state <= SEND_RESET;
tx_comm_reset <= 1;
end
end
SEND_RESET: begin
//XXX: In the groundhog COMM RESET was continuously issued for a long period of time
//send the INIT sequence, this will initiate a communication with the
//SATA hard drive, or reset it so that it can be initiated to state
//strobe the comm init so that the platform will send an INIT OOB signal
if (timeout || tx_oob_complete) begin
timer <= `INITIALIZE_TIMEOUT;
state <= WAIT_FOR_INIT;
$display ("oob_controller: wait for INIT");
end
end
WAIT_FOR_INIT: begin
//wait for a response from the SATA harddrive, if the timeout occurs
//go back to the SEND_RESET state
if (comm_init_detect) begin
//HD said 'sup' go to a wake
//timer <= 0;
timer <= 32'h00001000;
state <= WAIT_FOR_NO_INIT;
$display ("oob_controller: wait for INIT to go low");
end
if (timeout) begin
$display ("oob_controller: timed out while waiting for INIT");
state <= IDLE;
end
end
WAIT_FOR_NO_INIT: begin
//wait for the init signal to go low from the device
if (!comm_init_detect && (timeout || tx_oob_complete)) begin
$display ("oob_controller: INIT deasserted");
$display ("oob_controller: start configuration");
state <= WAIT_FOR_CONFIGURE_END;
end
end
WAIT_FOR_CONFIGURE_END: begin
$display ("oob_controller: System is configured");
state <= SEND_WAKE;
timer <= 32'h0000009B;
tx_comm_wake <= 1;
//end
end
SEND_WAKE: begin
//XXX: In the groundhog COMM WAKE was continuously send for a long period of time
//Send the WAKE sequence to the hard drive to initiate a wakeup sequence
//XXX: Is this timeout correct?
//880uS
if (timeout || tx_oob_complete) begin
//timer <= 32'd`INITIALIZE_TIMEOUT;
timer <= 32'h000203AD;
state <= WAIT_FOR_WAKE;
end
end
WAIT_FOR_WAKE: begin
//Wait for the device to send a COMM Wake
if (comm_wake_detect) begin
//Found a comm wake, now wait for the device to stop sending WAKE
timer <= 0;
state <= WAIT_FOR_NO_WAKE;
$display ("oob_controller: WAKE detected");
end
if (timeout) begin
//Timeout occured before reading WAKE
state <= IDLE;
$display ("oob_controller: timed out while waiting for WAKE to be asserted");
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
//The device stopped sending comm wake
//XXX: Is this timeout correct?
//880uS
$display ("oob_controller: detected WAKE deasserted");
$display ("oob_controller: Send Dialtone, wait for ALIGN");
//Going to add more timeout
//timer <= 32'h0203AD;
timer <= 32'h0203AD;
state <= WAIT_FOR_ALIGN;
//state <= WAIT_FOR_IDLE;
retries <= 4;
end
end
/*
WAIT_FOR_IDLE: begin
if (!rx_is_elec_idle) begin
state <= WAIT_FOR_ALIGN;
timer <= 32'h0101D0;
end
else if (timeout) begin
if (retries > 0) begin
timer <= 32'h0203AD;
retries <= retries - 1;
end
if (retries == 0) begin
state <= IDLE;
end
end
end
*/
WAIT_FOR_ALIGN: begin
//transmit the 'dialtone' continuously
//since we need to start sending actual data (not OOB signals, get out
// of tx idle)
tx_set_elec_idle <= 0;
//a sequence of 0's and 1's
tx_dout <= `DIALTONE;
tx_is_k <= 0;
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
//we got something from the device!
timer <= 0;
//now send an align from my side
state <= SEND_ALIGN;
no_align_count <= 0;
$display ("oob_controller: ALIGN detected");
$display ("oob_controller: Send out my ALIGNs");
end
if (timeout) begin
//didn't read an align in time :( reset
$display ("oob_controller: timed out while waiting for AIGN");
state <= IDLE;
end
end
SEND_ALIGN: begin
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
if (!align_detected) begin
$display ("oob_controller: detected ALIGN deasserted");
//XXX: Groundhog detects the SYNC primitve before declaring linkup
if (no_align_count == 3) begin
$display ("oob_controller: ready");
state <= READY;
end
else begin
no_align_count <= no_align_count + 2'b01;
end
end
end
DETECT_SYNC: begin
if (sync_detected) begin
state <= READY;
end
end
READY: begin
linkup <= 1;
/*
if (phy_error) begin
platform_error <= 1;
end
*/
if (comm_init_detect) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
//==================================================================================================
// Filename : ceespu_regfile.v
// Created On : 2018-07-21 21:13:53
// Last Modified : 2018-08-04 21:44:12
// Revision :
// Author : Cees Wolfs
//
// Description : The register file for the ceespu
//
//
//==================================================================================================
`timescale 1ns / 1ps
module ceespu_regfile(
input I_clk, // clock
input I_rst, // reset
input [4:0] I_selA,
input [4:0] I_selB,
input I_we,
input [4:0] I_selD,
input [31:0] I_dataD,
output [31:0] O_dataA,
output [31:0] O_dataB
);
reg [31:0] regfile [31:0];
assign O_dataA = regfile[I_selA];
assign O_dataB = regfile[I_selB];
/* Sequential Logic */
always @(posedge I_clk) begin
if (I_we) begin
$display("%d = %d, out is now %d at %d", I_selD, I_dataD, O_dataB, $time);
regfile[I_selD] <= I_dataD;
end
end
reg [5:0] k;
initial begin
for (k = 0; k <= 31; k = k + 1) begin
regfile[k] = 0;
end
// initialize stack pointer
regfile[18] = 32'h0000DFFF;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 150005; int n, m; int a, b; vector<int> g[N]; bool pos[N]; vector<int> dsu; bool rez; bool proveri() { for (int u = 0; u < dsu.size(); u++) if (g[dsu[u]].size() != dsu.size() - 1) return false; return true; } void dfs(int cvor) { pos[cvor] = true; dsu.push_back(cvor); for (int v = 0; v < g[cvor].size(); v++) if (!pos[g[cvor][v]]) dfs(g[cvor][v]); } void DFS() { for (int u = 1; u <= n && !rez; u++) { if (!pos[u]) { dsu.clear(); dfs(u); if (!proveri()) rez = true; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } DFS(); if (rez == true) cout << NO << endl; else cout << YES << endl; return 0; }
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: WB_SPI_Flash.v
// Description: Wishbone SPI Master core.
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module WB_SPI_Flash(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
output reg sclk, // Serial pad signal
input miso,
output reg mosi,
output reg sels, // Flash Select
output reg mcus // MCU select
);
wire op; // Operator
wire start; // Start indication
wire send; // End indication
reg st;
reg [7:0] tr;
reg [7:0] sft;
reg [1:0] clk_div;
assign op = wb_stb_i & wb_cyc_i;
assign start = !st & op;
assign send = start & wb_we_i & wb_sel_i[0];
always @(posedge wb_clk_i) clk_div <= clk_div - 2'd1;
always @(posedge wb_clk_i) sclk <= wb_rst_i ? 1'b1 : (clk_div[0] ? sclk : !(op & clk_div[1]));
always @(posedge wb_clk_i) wb_ack_o <= wb_rst_i ? 1'b0 : (wb_ack_o ? 1'b0 : (sft[0] && clk_div == 2'b00));
always @(negedge wb_clk_i) sels <= wb_rst_i ? 1'b1 : ((op & wb_we_i & wb_sel_i[1]) ? wb_dat_i[8] : sels);
always @(negedge wb_clk_i) mcus <= wb_rst_i ? 1'b1 : ((op & wb_we_i & wb_sel_i[1]) ? wb_dat_i[9] : mcus);
always @(posedge wb_clk_i) mosi <= wb_rst_i ? 1'b1 : (clk_div == 2'b10 ? (send ? wb_dat_i[7] : tr[7]) : mosi);
always @(posedge wb_clk_i) tr <= wb_rst_i ? 8'hff : (clk_div == 2'b10 ? { (send ? wb_dat_i[6:0] : tr[6:0]), 1'b1 } : tr);
always @(posedge wb_clk_i) wb_dat_o <= wb_rst_i ? 8'h0 : ((op && clk_div == 2'b0) ? { wb_dat_o[6:0], miso } : wb_dat_o);
always @(posedge wb_clk_i) st <= wb_rst_i ? 1'b0 : (st ? !sft[0] : op && clk_div == 2'b10);
always @(posedge wb_clk_i) sft <= wb_rst_i ? 8'h0 : (clk_div == 2'b10 ? { start, sft[7:1] } : sft);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$PKG$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void printvec(vector<T>& x, int a, int b) { for (int i = (a); i <= (b); i++) cout << x[i] << ; cout << n ; } const double PI = acos((double)-1); const double EPSILON = 1e-7; const int N = 1e6 + 1; const int NN = 1e3 + 1; const long long MOD = 998244353; const long long oo = LLONG_MAX; const int BASE = 10000; void query() { int n, x; cin >> n >> x; vector<vector<int>> g(n + 1); for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } if ((int)(g[x]).size() <= 1) { cout << Ayush << n ; return; } if (n % 2) { cout << Ashish << n ; } else { cout << Ayush << n ; } } void solve() { int q; cin >> q; while (q--) { query(); } } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); cout << fixed << setprecision(10); solve(); cerr << Time elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_6_2,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_6_2,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=32,DIN_FROM=30,DIN_TO=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_2 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
module decoder(input [1:0] op,input [5:0] funct,input [3:0]rd,
output reg [1:0] flagw,output wire pcs,output wire regw,
output wire memw,output wire memtoreg,output wire alusrc,
output wire [1:0] immsrc,output wire [1:0] regsrc,output reg[1:0] alucontrol ,output wire nowrite
);
reg [9:0] control;
wire aluop;
wire branch;
always @*
case(op)
2'b00: if(funct[5]) control=10'b0001001001; //data processing with immediate
else control=10'b0000001001; //data processing with register
2'b01: if(funct[0]) control=10'b0101011000; //LDR indtruction
else control=10'b0011010100; //STR instruction
2'b10: control=10'b1001100010; //branching
default:control=10'bxxxxxxxxxx;
endcase
assign {branch,memtoreg,memw,alusrc,immsrc,regw,regsrc,aluop} = control; // concatination for changing output of module
always @*
if(aluop)begin
case(funct[4:1])
4'd4 : alucontrol=0; //add
4'd2 : alucontrol=1; //sub
4'd0 : alucontrol=2; //and
4'd12: alucontrol=3; //or
4'd10: alucontrol=1; //subtract for CMP instruction
default:alucontrol=2'bxx;
endcase
flagw[1]=funct[0]; //s=1 update all flags
flagw[0] = funct[0] & (alucontrol == 0 | alucontrol == 1); //update c&v only while sub and add
end
else begin //no alu operation
flagw=0;
alucontrol=0;
end
assign pcs =((rd == 15) & regw) | branch ; //if write to pc register or branching instruction
assign nowrite = (funct[4:1]==10);
endmodule
module conditional_logic(input clk,input reset,input [3:0] cond,input [3:0]aluflags,input [1:0] flagw ,input pcs,
input wire regsw,input memw,input nowrite,output reg condex,
output wire PCSrc,output wire RegWrite ,output wire MemWrite);
wire [3:0] flags; //current flags
wire n,z,c,v;
wire [1:0]flagwrite;
assign flagwrite= flagw & {2{condex}};
flip_flop f1 (clk,reset,flagwrite[0],aluflags[1:0],flags[1:0]);
flip_flop f2 (clk,reset,flagwrite[1],aluflags[3:2],flags[3:2]);
assign {n,z,c,v} = flags;
always@(*)
case(cond)
4'b0000: condex=z; //EQ equal
4'b0001: condex=~z; //NE not equal
4'b0010: condex=c; //CS/HS a>b or the same
4'b0011: condex=~c; //CC/LO a<c the same unsigned
4'b0100: condex=n; //MI negative
4'b0101: condex=~n; //PL positive or zero
4'b0110: condex=v; //VS overflow
4'b0111: condex=~v; //VC no overflow
4'b1000: condex= ~z & c; //HI a>b
4'b1001: condex= ~c | z; //ls a<b or same
4'b1010: condex=~(n^v); //GE a>b signed or equal
4'b1011: condex=n^v; //LT a<b signed
4'b1100: condex=~z & ~(n ^ v); //GT a>b signed or equal
4'b1101: condex=~z & ~(n ^ v); //a>b signed
4'b1110: condex=1'b1; //non conditional
default: condex=1'bx;
endcase
assign PCSrc = pcs & condex;
assign RegWrite = regsw & condex & (~ nowrite);
assign MemWrite = memw & condex;
endmodule
module flip_flop(input clk,input reset,input en,input [1:0] d,output reg [1:0] q);
always @(posedge clk) begin
if(reset) q<=0;
else begin
if(en) q <= d;
end
end
endmodule
module control_unit(input Clk,input reset,input [3:0] Cond,input [1:0] Op,input [5:0] Funct,input [3:0] Rd,input [3:0]ALUFlags,
output wire PCSrc,output wire MemtoReg,output wire MemWrite,output wire [1:0]ALUControl,
output wire ALUSrc,output wire [1:0]ImmSrc,output wire RegWrite,output wire [1:0]RegSrc);
wire [1:0]Flagw;
wire PCS,RegW,MemW;
wire nowrite;
wire condex;
decoder d1(Op,Funct,Rd,Flagw,PCS,RegW,MemW,MemtoReg,ALUSrc,ImmSrc,RegSrc,ALUControl,nowrite);
conditional_logic c1(Clk,reset,Cond,ALUFlags,Flagw,PCS,RegW,MemW,nowrite,condex,PCSrc,RegWrite,MemWrite);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q ;
wire not0_out_qn;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, j, k, m, t, x, y, sum; cin >> t; while (t > 0) { t = t - 1; cin >> n >> k; long long a[n], c[k]; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < k; i++) { cin >> c[i]; } sort(a, a + n); sort(c, c + k); sum = 0; m = -1; j = n - 1; for (i = 0; i < k; i++) { if (c[i] == 1) { sum = sum + 2 * a[j]; m = i; } else sum = sum + a[j]; c[i] = c[i] - 1; j = j - 1; } j = m + 1; i = n - k - 1; for (i = i; i >= 0; i = i - 1) { while (c[j] > 1) { c[j] = c[j] - 1; i = i - 1; } sum = sum + a[i]; j = j + 1; } cout << sum << n ; } return 0; }
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = ~(a & b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
nand104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A21BO_BEHAVIORAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> AL[100005]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d , &u); scanf( %d , &v); AL[u].push_back(v); AL[v].push_back(u); } long long int l = 0; int fl = 0; for (int i = 1; i <= n; i++) { if (AL[i].size() == 2) { fl = 1; } } if (fl == 0) { printf( YES n ); } else { printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int _sieve_size; bitset<10000010> bs; vector<int> primes; void sieve(long long int upperbound) { _sieve_size = upperbound + 1; bs.set(); bs[0] = bs[1] = 0; for (long long int i = 2; i <= _sieve_size; i++) if (bs[i]) { for (long long int j = i * i; j <= _sieve_size; j += i) bs[j] = 0; primes.push_back((int)i); } } bool isPrime(long long int N) { if (N <= _sieve_size) return bs[N]; for (int i = 0; i < (int)primes.size(); i++) if (N % primes[i] == 0) return false; return true; } int main() { int h1, m1, h2, m2, oh, om; char tmp; cin >> h1 >> tmp >> m1; cin >> h2 >> tmp >> m2; om = m1 - m2; if (om < 0) { om += 60; h1 -= 1; } oh = h1 - h2; if (oh < 0) { oh += 24; } if (oh < 10) { cout << 0 << oh; } else cout << oh; cout << tmp; if (om < 10) { cout << 0 << om; } else cout << om; return 0; }
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module rom32(address, data_out);
input [31:0] address;
output [31:0] data_out;
reg [31:0] data_out;
parameter BASE_ADDRESS = 25'd0; // address that applies to this memory
wire [5:0] mem_offset;
wire address_select;
assign mem_offset = address[7:2]; // drop 2 LSBs to get word offset
assign address_select = (address[31:8] == BASE_ADDRESS); // address decoding
always @(address_select or mem_offset)
begin
if ((address % 4) != 0) $display($time, " rom32 error: unaligned address %d", address);
if (address_select == 1)
begin
case (mem_offset)
5'd0 : data_out = { 6'd35, 5'd0, 5'd2, 16'd4 };//lw $2, 4($0) r2=1
5'd1 : data_out = { 6'd0, 5'd2, 5'd2, 5'd3, 5'd0, 6'd32 }; //add $3, $2, $2
5'd2 : data_out = { 6'd2, 26'd0 }; //J 0
// add more cases here as desired
default data_out = 32'hxxxx;
endcase
$display($time, " reading data: rom32[%h] => %h", address, data_out);
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:55 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 5, MOD = 998244353; int m, n, k; long long res; int free_Row, free_Col, line_vert, line_hori; int Num_Row[N], Num_Row2[N][2], Num_Col[N], Num_Col2[N][2]; int c[2][2]; map<pair<int, int>, int> M; long long power(long long x, int k) { long long ans = 1; while (k) { if (k & 1) ans = ans * x % MOD; x = x * x % MOD; k >>= 1; } return ans; } void Calculate() { res = 0; if (line_vert && line_hori) return; if (!line_vert) (res += power(2, free_Row)) %= MOD; if (!line_hori) (res += power(2, free_Col)) %= MOD; if (!line_vert && !line_vert) { if (c[0][0] == 0 && c[1][1] == 0) (res += MOD - 1) %= MOD; if (c[0][1] == 0 && c[1][0] == 0) (res += MOD - 1) %= MOD; } } void Delete(int x, int y) { if (!M.count({x, y})) return; int z = M[{x, y}]; M.erase({x, y}); --c[z][(x + y) & 1]; if (--Num_Row[x] == 0) ++free_Row; if (--Num_Row2[x][z ^ (y & 1)] == 0 && Num_Row[x]) --line_vert; if (--Num_Col[y] == 0) ++free_Col; if (--Num_Col2[y][z ^ (x & 1)] == 0 && Num_Col[y]) --line_hori; } void Add(int x, int y, int z) { M[{x, y}] = z; ++c[z][(x + y) & 1]; if (Num_Row[x]++ == 0) --free_Row; if (Num_Row2[x][z ^ (y & 1)]++ == 0 && Num_Row[x] > 1) ++line_vert; if (Num_Col[y]++ == 0) --free_Col; if (Num_Col2[y][z ^ (x & 1)]++ == 0 && Num_Col[y] > 1) ++line_hori; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> m >> n >> k; free_Row = m; free_Col = n; line_hori = 0; line_vert = 0; int x, y, z; while (k--) { cin >> x >> y >> z; Delete(x, y); if (z >= 0) Add(x, y, z); Calculate(); cout << res << n ; } }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.