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#include <bits/stdc++.h> using namespace std; const int MAXN = 20; int a[MAXN]; int main() { int k; scanf( %d , &k); for (int i = 1; i <= 12; i++) { scanf( %d , &a[i]); } sort(a + 1, a + 13); int tot = 0, ans = 0; for (int i = 12; i >= 1; i--) { if (tot >= k) { break; } tot += a[i]; ans++; } if (tot < k) { printf( -1 n ); } else { printf( %d n , ans); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module decodes video input streams on the DE boards. *
* *
******************************************************************************/
module video_sys_Video_In_Decoder (
// Inputs
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
stream_out_ready,
// Bidirectional
// Outputs
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input stream_out_ready;
// Bidirectional
// Outputs
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire video_clk;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
// Internal Registers
reg reached_start_of_frame;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge video_clk)
begin
if (reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
// Internal Registers
always @(posedge video_clk)
begin
if (reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
// Internal Assignments
assign video_clk = TD_CLK27;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// NTSC Video In Decoding
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
// Inputs
.clk (video_clk),
.reset (reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
// Bidirectionals
// Outputs
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
// Inputs
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
// .data ({1'b0, decoded_startofpacket, decoded_pixel}),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
// Bidirectionals
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: seven_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module seven_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/seven_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/seven_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL seven_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int tux; cin >> tux; int foo = 0, bar = 0, baz = 0, quz = 1; for (int i = 1; i <= tux; i++) { int pur; cin >> pur; foo += pur; bar = bar + 1; if (foo * quz > baz * bar) { baz = foo; quz = bar; } } double a = baz, b = quz; cout << fixed << setprecision(6) << a / b << endl; }
|
///////////////////
// File Name: VGA Tutorial
// Author : Da Cheng
// Course : EE201
///////////////////
// timing diagram for the horizontal synch signal (HS)
// 0 655 752 800 (pixels)
// -------------------------|______|-----------------
// timing diagram for the vertical synch signal (VS)
// 0 490 491 525 (lines)
// -----------------------------------|______|-------
module hvsync_generator(clk, reset,vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
input reset;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [9:0] CounterY;
//////////////////////////////////////////////////
reg [9:0] CounterX;
reg [9:0] CounterY;
reg vga_HS, vga_VS;
reg inDisplayArea;
//increment column counter
always @(posedge clk)
begin
if(reset)
CounterX <= 0;
else if(CounterX==10'h320) //800
CounterX <= 0;
else
CounterX <= CounterX + 1'b1;
end
//increment row counter
always @(posedge clk)
begin
if(reset)
CounterY<=0;
else if(CounterY==10'h209) //521
CounterY<=0;
else if(CounterX==10'h320) //800
CounterY <= CounterY + 1'b1;
end
//generate synchronization signal for both vertical and horizontal
always @(posedge clk)
begin
vga_HS <= (CounterX > 655 && CounterX < 752); // change these values to move the display horizontally
vga_VS <= (CounterY == 490 || CounterY == 491); // change these values to move the display vertically
end
always @(posedge clk)
if(reset)
inDisplayArea<=0;
else
inDisplayArea <= (CounterX<640) && (CounterY<480);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return a ? gcd(b % a, a) : b; } template <typename T> T lcm(T a, T b) { return (a / gcd(a, b)) * b; } string int_to_str_easy(long long n) { return n ? : int_to_str_easy(n / 10) + (char)( 0 + n % 10); } template <typename T> T sum(vector<T> v) { T ans = 0; for (T i : v) ans += i; return ans; } bool is_down(char x) { return ( a <= x && x <= z ); } bool is_upper(char x) { return ( A <= x && x <= Z ); } bool is_digit(char x) { return ( 0 <= x && x <= 9 ); } string follow(string s) { for (int i = 0; i < s.length(); i++) if (is_upper(s[i])) s[i] += a - A ; return s; } const long double pi = 3.141592653589793238462643383279; const long double log23 = 1.58496250072115618145373894394781; const long double eps = 1e-8; const long double zero = 0; const long long INF = 1e18; const int COUT = 30; const int prost = 239; const long long prost64 = 239; const int two = 2; const long long MOD = 1000000007; const int BIG = 1e9; const int alf = 26; const int MAX_M = 2001; const int MAX_N = 2 * 1e5 + 1; const int km = (1 << 18) - 1; const int dxo[8] = {-1, -1, -1, 0, 1, 1, 1, 0}; const int dyo[8] = {-1, 0, 1, 1, 1, 0, -1, -1}; const int dx[4] = {-1, 0, 1, 0}; const int dy[4] = {0, 1, 0, -1}; const int bit_max = 32; void solve() { return; } int n; string s; int main() { cin.sync_with_stdio(0); cin >> n >> s; string e = ; int ans = 0; for (int i = 0; i < n; i++) { if (i % 2 == 0) e += r ; else e += b ; } int now = 0; string w = s; int no1 = 0; int no2 = 0; for (int i = 0; i < n; i++) { if (w[i] != e[i] && (i + 1) % 2 == 0) no1++; else if (w[i] != e[i]) no2++; } now = min(no1, no2) + abs(no1 - no2); ans = now; now = 0; e = ; for (int i = 0; i < n; i++) { if (i % 2 == 0) e += b ; else e += r ; } w = s; no1 = 0; no2 = 0; for (int i = 0; i < n; i++) { if (w[i] != e[i] && (i + 1) % 2 == 0) no1++; else if (w[i] != e[i]) no2++; } now = min(no1, no2) + abs(no1 - no2); ans = min(ans, now); cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A211OI_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_BLACKBOX_V
|
#include <bits/stdc++.h> void sc(int &x) { scanf( %d , &x); } void sc(int &x, int &y) { scanf( %d%d , &x, &y); } void sc(int &x, int &y, int &z) { scanf( %d%d%d , &x, &y, &z); } void sc(long long &x) { scanf( %lld , &x); } void sc(long long &x, long long &y) { scanf( %lld%lld , &x, &y); } void sc(long long &x, long long &y, long long &z) { scanf( %lld%lld%lld , &x, &y, &z); } void sc(char *x) { scanf( %s , x); } void sc(char *x, char *y) { scanf( %s%s , x, y); } void sc(char *x, char *y, char *z) { scanf( %s%s%s , x, y, z); } void out(int x) { printf( %d n , x); } void out(long long x) { printf( %lld n , x); } void out(int x, int y) { printf( %d %d n , x, y); } void out(long long x, long long y) { printf( %lld %lld n , x, y); } void out(int x, int y, int z) { printf( %d %d %d n , x, y, z); } void out(long long x, long long y, long long z) { printf( %lld %lld %lld n , x, y, z); } void ast(long long x, long long l, long long r) { assert(x >= l && x <= r); } using namespace std; const int N = 666, mod = 998244353; int k, a, h, rk[N], srk[N], g[N]; vector<pair<int, int>> l1, l2, r1, r2; void sol(int l, int r, vector<pair<int, int>> &s1, vector<pair<int, int>> &s2) { int len = r - l + 1; int tot = 0; while (len) { len /= 2; tot += len; } int up = 1 << tot; for (int i = 0; i < up; i++) { int cur = k + 1; vector<int> vc; for (int j = l; j <= r; j++) vc.push_back(j); int s = 0; int mul = 0; while (vc.size() > 1) { vector<int> gc; for (int j = 0; j < vc.size(); j += 2) { if (i >> s & 1) mul = (mul + 1ll * vc[j] * g[cur]) % mod, gc.push_back(vc[j + 1]); else mul = (mul + 1ll * vc[j + 1] * g[cur]) % mod, gc.push_back(vc[j]); s++; } vc = gc; cur--; } assert(s == tot); assert(cur == 2); assert(vc.size() == 1); s1.push_back({(mul + 1ll * vc[0] * g[1]) % mod, i}); s2.push_back({(mul + 1ll * vc[0] * g[2]) % mod, i}); } } int ans[N]; int cal(int i, int l, int r) { vector<int> vc; for (int j = l; j <= r; j++) vc.push_back(j); int s = 0, cur = k + 1; while (vc.size() > 1) { vector<int> gc; for (int j = 0; j < vc.size(); j += 2) { if (i >> s & 1) ans[vc[j]] = rk[cur], gc.push_back(vc[j + 1]); else ans[vc[j + 1]] = rk[cur], gc.push_back(vc[j]); s++; } vc = gc; cur--; } return vc[0]; } void get(vector<pair<int, int>> &l, vector<pair<int, int>> &r, int rkl, int rkr) { sort(r.begin(), r.end()); for (pair<int, int> x : l) { int pos = lower_bound(r.begin(), r.end(), make_pair((h + mod - x.first) % mod, 0)) - r.begin(); if (pos >= 0 && pos < r.size() && r[pos].first == (h + mod - x.first) % mod) { int a = cal(x.second, 1, 1 << (k - 1)), b = cal(r[pos].second, (1 << (k - 1)) + 1, 1 << k); ans[a] = rkl; ans[b] = rkr; for (int i = 1; i <= (1 << k); i++) printf(i == (1 << k) ? %d n : %d , ans[i]); exit(0); } } } void sol(int cas) { sc(k, a, h); for (int i = 1; i <= k + 1; i++) rk[i] = i - 2 >= 0 ? (1 << (i - 2)) + 1 : 1; for (int i = 1; i <= k + 1; i++) { g[i] = 1; for (int j = 1; j <= rk[i]; j++) g[i] = 1ll * g[i] * a % mod; } sol(1, 1 << (k - 1), l1, l2); sol((1 << (k - 1)) + 1, 1 << k, r1, r2); get(l1, r2, 1, 2); get(l2, r1, 2, 1); out(-1); } int main() { srand(time(0)); int t = 1, cas = 0; while (t--) { sol(++cas); } return 0; }
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#include <bits/stdc++.h> const int inf = 0x7f7f7f7f; inline void gettime() { ; } inline int read() { static char c; static int x; int flag = 1; while (c = getchar(), !isdigit(c)) if (c == - ) flag = -1; x = c - 0 ; while (c = getchar(), isdigit(c)) x = (x << 1) + (x << 3) + c - 0 ; return x * flag; } inline char achar() { static char c; while (c = getchar(), !isdigit(c)) ; return c; } int n, ones; char s[200200]; std::queue<int> ns[200200]; std::queue<int> ps[2]; int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i <= n; ++i) ones += s[i] == 1 ; int k = (n - ones) - ones; if (k <= 0) return puts( -1 ), 0; for (int i = 1; i <= k; ++i) ps[0].push(i); for (int i = 1; i <= n; ++i) { int cur = s[i] == 1 ; if (ps[cur].empty()) return puts( -1 ), 0; ns[ps[cur].front()].push(i); ps[cur ^ 1].push(ps[cur].front()); ps[cur].pop(); } if (!ps[0].empty()) return puts( -1 ), 0; printf( %d n , k); for (int i = 1; i <= k; ++i) { printf( %d , ns[i].size()); for (; !ns[i].empty(); ns[i].pop()) printf( %d , ns[i].front()); printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; const int NR = 4e6 + 5; int n; long long P = 51123987; char s[NR]; int d[NR]; long long f[NR], g[NR]; int main() { scanf( %d , &n); scanf( %s , s + 1); for (int i = n; i >= 1; i--) { s[i * 2] = s[i]; s[i * 2 - 1] = # ; } s[n * 2 + 1] = # ; n = n * 2 + 1; int p = 0, maxr = 0; for (int i = 1; i <= n; i++) { if (i <= maxr) d[i] = min(d[p + maxr - i], maxr - i + 1); while (i - d[i] >= 1 && i + d[i] <= n && s[i - d[i]] == s[i + d[i]]) d[i]++; if (i + d[i] - 1 > maxr) { p = i - d[i] + 1; maxr = i + d[i] - 1; } if (s[i] == # && d[i] == 1) continue; f[(i - d[i] + 2) / 2]++; f[i / 2 + 1]--; if (s[i] == # ) g[i / 2 + 1]++; else g[i / 2]++; g[(i + d[i] - 1) / 2 + 1]--; } n = (n - 1) / 2; for (int i = 1; i <= n; i++) { f[i] += f[i - 1]; f[i] %= P; g[i] += g[i - 1]; g[i] %= P; } long long sum1 = 0, sum2 = 0, ans = 0; for (int i = 1; i <= n; i++) { sum1 += f[i]; sum1 %= P; ans += f[i] * sum2; ans %= P; sum2 += g[i]; sum2 %= P; } sum1 = sum1 * (sum1 - 1) / 2 % P; printf( %lld n , (sum1 - ans + P) % P); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int bignumlen = 2200; const int Blen = 8; const long long base = 100000000; struct bignum { int len; long long data[bignumlen]; long long &operator[](int x) { return (data[x]); } const long long &operator[](int x) const { return (data[x]); } bignum() { memset(data, 0, sizeof(data)); len = 0; } void clear() { for (int i = len; i >= 1; --i) data[i] = 0; len = 0; } int check(const bignum &a, const bignum &b) { if (a.len > b.len) return (0); if (b.len > a.len) return (1); for (int i = a.len; i >= 1; --i) { if (a.data[i] < b.data[i]) return (1); if (b.data[i] < a.data[i]) return (0); } return 2; } bool operator<(const bignum &b) { return (check(*this, b) == 1); } bool operator>(const bignum &b) { return (check(*this, b) == 0); } bool operator<=(const bignum &b) { return (check(*this, b) >= 1); } bool operator>=(const bignum &b) { return (check(*this, b) % 2 == 0); } bool operator!=(const bignum &b) { return (check(*this, b) != 2); } bool operator==(const bignum &b) { return (check(*this, b) == 2); } bignum operator=(const bignum &x) { for (int i = x.len + 1; i <= len; ++i) data[i] = 0; for (int i = 1; i <= x.len; ++i) data[i] = x.data[i]; len = x.len; return *this; } bignum operator=(long long x) { for (int i = len; i >= 0; --i) data[i] = 0; len = 0; while (x) { data[++len] = x % base; x /= base; } return *this; } bignum(long long x) { memset(data, 0, sizeof(data)); len = 0; (*this) = x; } bignum operator*(const bignum &b) { int i, j; bignum tmp; for (i = 1; i <= len; ++i) if (data[i] != 0) for (j = 1; j <= b.len; ++j) if (b.data[j] != 0) { tmp.data[i + j - 1] += data[i] * b.data[j]; tmp.data[i + j] += tmp.data[i + j - 1] / base; tmp.data[i + j - 1] %= base; } tmp.len = len + b.len - 1; while (tmp.data[tmp.len + 1]) tmp.len++; return tmp; } bignum operator*(long long x) { int i; bignum tmp; for (i = 1; i <= len; ++i) tmp[i] = data[i] * x; tmp.len = len; for (i = 1; i <= len; ++i) { tmp[i + 1] += tmp[i] / base, tmp[i] %= base; if (tmp[i + 1] && i + 1 > tmp.len) tmp.len++; } return tmp; } bignum operator/(long long x) { int i; bignum tmp; long long y = 0; for (i = len; i >= 1; --i) { y = y * base + data[i]; tmp[i] = y / x; y %= x; } tmp.len = len; while (tmp[tmp.len] == 0 && tmp.len > 1) tmp.len--; return tmp; } bignum operator/(const bignum &b) { if (b.len <= 1 && b[1] == 0) { printf( error! ?0?! ); for (;;) ; } int i, l1 = (len - 1) * Blen, l2 = (b.len - 1) * Blen; long long x = data[len], y = b[b.len]; while (x) x /= 10, l1++; while (y) y /= 10, l2++; bignum tmp, chu, B; chu = *this; B = b; for (i = 1; i * Blen <= l1 - l2; ++i) B *= base; for (i = 1; i <= (l1 - l2) % Blen; ++i) B *= 10; for (i = l1 - l2; i >= 0; --i) { x = 0; while (chu >= B) chu -= B, x++; tmp[i / Blen + 1] = tmp[i / Blen + 1] * 10 + x; B /= 10; } tmp.len = (l1 - l2) / Blen + 1; while (tmp.len >= 1 && !tmp[tmp.len]) tmp.len--; return tmp; } bignum operator+(const bignum &b) { bignum tmp; int i, l = max(len, b.len); for (i = 1; i <= l; ++i) tmp[i] = data[i] + b[i]; for (i = 1; i <= l; ++i) tmp[i + 1] += tmp[i] / base, tmp[i] %= base; tmp.len = l; if (tmp[tmp.len + 1]) tmp.len++; return tmp; } bignum operator+(long long x) { bignum tmp; tmp = *this; tmp[1] += x; for (int i = 1; i <= len && tmp[i] >= base; ++i) tmp[i + 1] += tmp[i] / base, tmp[i] %= base; while (tmp[tmp.len + 1]) tmp.len++; return tmp; } bignum operator-(const bignum &b) { int i; bignum tmp; for (i = 1; i <= len; ++i) tmp.data[i] = data[i] - b.data[i]; for (i = 1; i <= len; ++i) { if (tmp[i] < 0) tmp.data[i] += base, tmp.data[i + 1]--; } tmp.len = len; while (tmp[tmp.len] == 0 && tmp.len > 1) tmp.len--; return tmp; } bignum operator-(long long x) { bignum tmp; tmp = *this; tmp[1] -= x; for (int i = 1; i <= len && tmp[i] < 0; ++i) { tmp[i + 1] += (tmp[i] + 1) / base - 1; tmp[i] = (tmp[i] + 1) % base + base - 1; } while (!tmp[tmp.len] && tmp.len > 1) tmp.len--; return tmp; } long long operator%(long long x) { int i; long long y = 0; for (i = len; i >= 1; --i) y = (y * base + data[i]) % x; return y; } bignum operator%(const bignum &b) { if (b.len <= 1 && b[1] == 0) { printf( error! ?0 mod! ); for (;;) ; } int i, l1 = (len - 1) * Blen, l2 = (b.len - 1) * Blen; long long x = data[len], y = b[b.len]; while (x) x /= 10, l1++; while (y) y /= 10, l2++; bignum chu, B; chu = *this; B = b; for (i = 1; i * Blen <= l1 - l2; ++i) B *= base; for (i = 1; i <= (l1 - l2) % Blen; ++i) B *= 10; for (i = l1 - l2; i >= 0; --i) { while (chu >= B) chu -= B; B /= 10; } return chu; } bignum operator+=(const bignum &b) { return *this = (*this + b); } bignum operator*=(const bignum &b) { return *this = (*this * b); } bignum operator-=(const bignum &b) { return *this = (*this - b); } bignum operator/=(const bignum &b) { return *this = (*this / b); } bignum operator%=(const bignum &b) { return *this = (*this % b); } bignum operator*=(long long x) { return (*this = (*this * x)); } bignum operator+=(long long x) { return (*this = (*this + x)); } bignum operator-=(long long x) { return (*this = (*this - x)); } bignum operator/=(long long x) { return (*this = (*this / x)); } void read() { char c[bignumlen * Blen + 10]; scanf( %s , c + 1); int l = strlen(c + 1); (*this).clear(); long long x; for (int i = 1; i <= (l - 1) / Blen + 1; ++i) { x = 0; for (int j = l - Blen * i + 1; j <= l - Blen * i + Blen; ++j) if (j >= 1) x = x * 10 + c[j] - 48; data[++len] = x; } } void write() { printf( %lld , data[len]); for (int i = len - 1; i >= 1; --i) printf( %0*I64d , Blen, data[i]); } } p, q, pp, qq; bignum gcd(const bignum &A, const bignum &B) { bignum a = A, b = B, res = 1; while (!(a[1] & 1) && !(b[1] & 1)) a /= 2, b /= 2, res *= 2; for (;;) { if (a.len == 1 && a[1] == 0) return b * res; if (b.len == 1 && b[1] == 0) return a * res; while (!(a[1] & 1)) a /= 2; while (!(b[1] & 1)) b /= 2; if (a > b) a -= b; else b -= a; } } void YF(bignum &A, bignum &B) { bignum tmp = gcd(A, B); A /= tmp; B /= tmp; } int n, i, x, num; int main() { scanf( %d , &n); while (n % 2 == 0) { n /= 2; num++; } if (n == 1) { printf( %d/%d n , num, 1); return 0; } p = 0; q = 1; pp = 1; qq = 1; for (i = n + 1;;) { if (i > n) { if (q % (i - n) == 0) q /= i - n; else p *= i - n; if (qq % (i - n) == 0) qq /= i - n; else pp *= i - n; if (p % i == 0) p /= i; else q *= i; if (pp % i == 0) pp /= i; else qq *= i; } else p += q; if (i == 1) break; if (i % 2 == 0) i /= 2; else i += n; } YF(p, q); p = p * qq; q = q * (qq - pp); p += q * num; bignum tmp = gcd(p, q); (p / tmp).write(); printf( / ); (q / tmp).write(); }
|
#include <bits/stdc++.h> using namespace std; int N; string A; string B; int main() { ios_base::sync_with_stdio(NULL); cout.tie(NULL); cin.tie(NULL); cin >> N; cin >> A >> B; int answer = 0; for (int i = 0; i < N - 1; ++i) { if (A[i] == B[i]) continue; if (A[i + 1] == B[i] && A[i] == B[i + 1]) swap(A[i], A[i + 1]); else A[i] = B[i]; ++answer; } if (A[N - 1] != B[N - 1]) { ++answer; A[N - 1] = B[N - 1]; } cerr << A << endl; cout << answer << endl; return 0; }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:36 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_gcd_0_1_stub.v
// Design : gcd_block_design_gcd_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:35 12/16/2015
// Design Name: uart2_tx
// Module Name: H:/Firmware/font5_base_new/font5_base/font5-firmware/uart2_tb.v
// Project Name: font5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart2_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart2_tb;
// Inputs
reg reset;
reg clk;
reg ld_tx_data;
reg [7:0] tx_data;
reg tx_enable;
// Outputs
wire tx_out;
wire tx_empty;
// Instantiate the Unit Under Test (UUT)
uart2_tx uut (
.reset(reset),
.clk(clk),
.ld_tx_data(ld_tx_data),
.tx_data(tx_data),
.tx_enable(tx_enable),
.tx_out(tx_out),
.tx_empty(tx_empty)
);
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
ld_tx_data = 0;
tx_data = 0;
tx_enable = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* Module: arbiter
*
* Description:
* A look ahead, round-robing parametrized arbiter.
*
* <> request
* each bit is controlled by an actor and each actor can 'request' ownership
* of the shared resource by bring high its request bit.
*
* <> grant
* when an actor has been given ownership of shared resource its 'grant' bit
* is driven high
*
* <> select
* binary representation of the grant signal (optional use)
*
* <> active
* is brought high by the arbiter when (any) actor has been given ownership
* of shared resource.
*
*
* Created: Sat Jun 1 20:26:44 EDT 2013
*
* Author: Berin Martini //
*/
`ifndef _arbiter_ `define _arbiter_
module arbiter
#(parameter
NUM_PORTS = 6)
(input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg [$clog2(NUM_PORTS)-1:0] select,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2*NUM_PORTS;
// Find First 1 - Start from MSB and count downwards, returns 0 when no
// bit set
function [$clog2(NUM_PORTS)-1:0] ff1;
input [NUM_PORTS-1:0] in;
integer i;
begin
ff1 = 0;
for (i = NUM_PORTS-1; i >= 0; i=i-1) begin
if (in[i])
ff1 = i;
end
end
endfunction
`ifdef VERBOSE
initial $display("Bus arbiter with %d units", NUM_PORTS);
`endif
/**
* Internal signals
*/
integer yy;
wire next;
wire [NUM_PORTS-1:0] order;
reg [NUM_PORTS-1:0] token;
wire [NUM_PORTS-1:0] token_lookahead [NUM_PORTS-1:0];
wire [WRAP_LENGTH-1:0] token_wrap;
/**
* Implementation
*/
assign token_wrap = {token, token};
assign next = ~|(token & request);
always @(posedge clk)
grant <= token & request;
always @(posedge clk)
select <= ff1(token & request);
always @(posedge clk)
active <= |(token & request);
always @(posedge clk)
if (rst) token <= 'b1;
else if (next) begin
for (yy = 0; yy < NUM_PORTS; yy = yy + 1) begin : TOKEN_
if (order[yy]) begin
token <= token_lookahead[yy];
end
end
end
genvar xx;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
assign token_lookahead[xx] = token_wrap[xx +: NUM_PORTS];
assign order[xx] = |(token_lookahead[xx] & request);
end
endgenerate
endmodule
`endif // `ifndef _arbiter_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_0_V
`define SKY130_FD_SC_LP__O221AI_0_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_2_V
`define SKY130_FD_SC_LS__FA_2_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int sasha_chiz, masha_chiz, coconut_price, sasha_buy_co, masha_buy_co, sum_buy_co, given_chiz = 0; cin >> sasha_chiz >> masha_chiz >> coconut_price; sasha_buy_co = sasha_chiz / coconut_price; masha_buy_co = masha_chiz / coconut_price; if (sasha_chiz % coconut_price != 0 && masha_chiz % coconut_price != 0) { sasha_chiz = sasha_chiz % coconut_price; masha_chiz = masha_chiz % coconut_price; if (sasha_chiz + masha_chiz >= coconut_price) { if (sasha_chiz >= masha_chiz) { given_chiz = coconut_price - sasha_chiz; sasha_buy_co = sasha_buy_co + 1; } else { given_chiz = coconut_price - masha_chiz; masha_buy_co = masha_buy_co + 1; } } } sum_buy_co = sasha_buy_co + masha_buy_co; cout << sum_buy_co << << given_chiz; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool reach(int from[3], int to[3], vector<vector<string>> &works) { if (works[from[0]][from[1]][from[2]] == 0 ) return false; if (from[0] == to[0] && from[1] == to[1] && from[2] == to[2]) return true; for (int d = 0; d < 3; ++d) if (from[d] < to[d]) { ++from[d]; bool res = reach(from, to, works); --from[d]; if (res) return true; } return false; } int main() { int lim[3]; for (int i = 0; i < 3; ++i) scanf( %d , &lim[i]); vector<vector<string>> works(lim[0], vector<string>(lim[1], string(lim[2], ))); for (int i = 0; i < lim[0]; ++i) for (int j = 0; j < lim[1]; ++j) scanf( %s , &works[i][j][0]); int result = 0; for (int i = 0; i < lim[0]; ++i) for (int j = 0; j < lim[1]; ++j) for (int k = 0; k < lim[2]; ++k) if (works[i][j][k] == 1 ) { int at[3] = {i, j, k}; bool critical = false; for (int fromd = 0; fromd < 3; ++fromd) if (at[fromd] >= 1) { int from[3] = {i, j, k}; --from[fromd]; for (int tod = 0; tod < 3; ++tod) if (at[tod] + 1 < lim[tod]) { int to[3] = {i, j, k}; ++to[tod]; bool before = reach(from, to, works); works[i][j][k] = 0 ; bool after = reach(from, to, works); works[i][j][k] = 1 ; if (before && !after) critical = true; } } if (critical) ++result; } printf( %d n , result); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool v[6]; int a[100009][6], maxx = -1, t; long long m = 1e9 + 7; struct pi { long long ah[60][60]; }; pi multi(pi x, pi y) { pi z; for (int i = 1; i <= t; i++) { for (int j = 1; j <= t; j++) { z.ah[i][j] = 0; for (int k = 1; k <= t; k++) z.ah[i][j] = (z.ah[i][j] % m + x.ah[i][k] % m * y.ah[k][j] % m) % m; z.ah[i][j] %= m; } } return z; } pi quimul(pi x, long long int n) { pi an; for (int i = 1; i <= t; i++) an.ah[i][i] = 1; for (; n; n >>= 1) { if (n & 1) an = multi(an, x); x = multi(x, x); } return an; } int main() { long long n; int x, v, p[600], zh[90][90]; char c = a , u; for (int i = 1; i <= 52; i++) for (int j = 1; j <= 52; j++) zh[i][j] = 1; for (int i = 1; i <= 26; i++) p[(int)c + i - 1] = i; c = A ; for (int i = 27; i <= 52; i++) p[(int)c + i - 27] = i; cin >> n >> t >> v; for (int i = 0; i < v; i++) { scanf( %c %c , &c, &u); zh[p[(int)c]][p[(int)u]] = 0; } pi ans; for (int i = 1; i <= t; i++) for (int j = 1; j <= t; j++) ans.ah[i][j] = zh[i][j]; ans = quimul(ans, n - 1); long long int pp = 0; for (int i = 1; i <= t; i++) for (int j = 1; j <= t; j++) pp = (pp + ans.ah[i][j]) % m; cout << (pp + m) % m << endl; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > numbersWithGrundy(1); int a[200001], grundyValues[200001]; bool isPrime[200001], isMoveValid[200001]; vector<string> players{ Alice , Bob }; void PreProcess(int n, int m) { vector<int> primes; for (int i = 2; i <= n; ++i) { isPrime[i] = 1; } for (int i = 2; i <= n; ++i) { if (!isPrime[i]) { continue; } for (int j = i + i; j <= n; j += i) { isPrime[j] = 0; } primes.push_back(i); for (int prime : primes) { if (i * prime > n) { break; } isMoveValid[i * prime] = 1; } isMoveValid[i] = 1; } isMoveValid[m] = 0; numbersWithGrundy[0].push_back(0); for (int i = 1; i <= n; ++i) { int &k = grundyValues[i]; for (; k < numbersWithGrundy.size(); ++k) { bool valid = 1; for (int l = 0, r = numbersWithGrundy[k].size() - 1; l <= r && valid; ++l, --r) { valid = !(isMoveValid[i - numbersWithGrundy[k][l]] || isMoveValid[i - numbersWithGrundy[k][r]]); } if (valid) { break; } } if (k >= numbersWithGrundy.size()) { numbersWithGrundy.resize(k + 1); } numbersWithGrundy[k].push_back(i); } } int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1, j = 0; i <= n; ++i) { int b, w, r; scanf( %d%d%d , &b, &w, &r); a[++j] = w - b - 1; a[++j] = r - w - 1; } n = 2 * n; int m = 0; for (int i = 1; i <= n; ++i) { m = max(m, a[i]); } PreProcess(m, k); int ans = 0; for (int i = 1; i <= n; ++i) { ans ^= grundyValues[a[i]]; } ans = (ans == 0) ? 1 : 0; for (int i = 0; i < players.size(); ++i) { cout << players[i ^ ans] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using lint = long long int; lint liters(int l, vector<int> &arr) { lint sum = 0; for (int k : arr) sum += (lint)(k - l); return sum; } int main() { int n, m = 1000000010; lint s; vector<int> arr; cin >> n >> s; arr.resize(n); for (int i = 0; i < n; i++) { cin >> arr[i]; m = min(m, arr[i]); } if (s > liters(0, arr)) cout << -1 << endl; else { int start = 0, end = m; while (start < end) { int mid = (start + end) / 2 + 1; if (s <= liters(mid, arr)) start = mid; else end = mid - 1; } cout << start << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int mxN = 500, M = 1e9 + 7; int n, a[mxN]; long long dp[mxN][mxN]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) cin >> a[i], --a[i]; dp[0][0] = 1; for (int i = 1; i < n; ++i) dp[i][i] = dp[i - 1][i] = 1; for (int i = n - 1; ~i; --i) { for (int j = i + 2; j < n; ++j) { dp[i][j] = dp[i + 1][j]; for (int k = i + 1; k < j; ++k) if (a[k + 1] > a[i + 1]) dp[i][j] = (dp[i][j] + dp[i + 1][k] * dp[k][j]) % M; } } cout << dp[0][n - 1]; return 0; }
|
//////////////////////////////////////////////////////////////////////
// File: CRC32.v
// Date: Thu Nov 27 13:56:49 2003
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: (Jan Zegers)
// http://www.easics.com
//
// Modified by Nathan Yawn for the Advanced Debug Module
// Changes (C) 2008 - 2010 Nathan Yawn
///////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_crc32.v,v $
// Revision 1.2 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.1 2008/07/22 20:28:29 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:53 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/20 19:22:10 Nathan
// Reversed the direction of the CRC computation shift, for a more
// hardware-efficient implementation.
//
//
//
//
module adbg_crc32 (clk, data, enable, shift, clr, rst, crc_out, serial_out);
input clk;
input data;
input enable;
input shift;
input clr;
input rst;
output [31:0] crc_out;
output serial_out;
reg [31:0] crc;
wire [31:0] new_crc;
// You may notice that the 'poly' in this implementation is backwards.
// This is because the shift is also 'backwards', so that the data can
// be shifted out in the same direction, which saves on logic + routing.
assign new_crc[0] = crc[1];
assign new_crc[1] = crc[2];
assign new_crc[2] = crc[3];
assign new_crc[3] = crc[4];
assign new_crc[4] = crc[5];
assign new_crc[5] = crc[6] ^ data ^ crc[0];
assign new_crc[6] = crc[7];
assign new_crc[7] = crc[8];
assign new_crc[8] = crc[9] ^ data ^ crc[0];
assign new_crc[9] = crc[10] ^ data ^ crc[0];
assign new_crc[10] = crc[11];
assign new_crc[11] = crc[12];
assign new_crc[12] = crc[13];
assign new_crc[13] = crc[14];
assign new_crc[14] = crc[15];
assign new_crc[15] = crc[16] ^ data ^ crc[0];
assign new_crc[16] = crc[17];
assign new_crc[17] = crc[18];
assign new_crc[18] = crc[19];
assign new_crc[19] = crc[20] ^ data ^ crc[0];
assign new_crc[20] = crc[21] ^ data ^ crc[0];
assign new_crc[21] = crc[22] ^ data ^ crc[0];
assign new_crc[22] = crc[23];
assign new_crc[23] = crc[24] ^ data ^ crc[0];
assign new_crc[24] = crc[25] ^ data ^ crc[0];
assign new_crc[25] = crc[26];
assign new_crc[26] = crc[27] ^ data ^ crc[0];
assign new_crc[27] = crc[28] ^ data ^ crc[0];
assign new_crc[28] = crc[29];
assign new_crc[29] = crc[30] ^ data ^ crc[0];
assign new_crc[30] = crc[31] ^ data ^ crc[0];
assign new_crc[31] = data ^ crc[0];
always @ (posedge clk or posedge rst)
begin
if(rst)
crc[31:0] <= #1 32'hffffffff;
else if(clr)
crc[31:0] <= #1 32'hffffffff;
else if(enable)
crc[31:0] <= #1 new_crc;
else if (shift)
crc[31:0] <= #1 {1'b0, crc[31:1]};
end
//assign crc_match = (crc == 32'h0);
assign crc_out = crc; //[31];
assign serial_out = crc[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string n; int k = 0; cin >> n; if (n[0] <= Z ) { for (int i = 0; i < n.size(); i++) { if (n[i] <= Z ) k++; } if (k == n.size()) { transform(n.begin(), n.end(), n.begin(), (int (*)(int))tolower); cout << n; } else cout << n; } else { for (int i = 0; i < n.size(); i++) { if (n[i] <= Z ) k++; } if (k == n.size() - 1) { transform(n.begin(), n.end(), n.begin(), (int (*)(int))tolower); n.at(0) = toupper(n.at(0)); cout << n; } else cout << n; } }
|
// file: clk_dll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______267.325____251.827
// CLK_OUT2____25.000______0.000______50.0______308.718____251.827
// CLK_OUT3_____3.200______0.000______50.0______464.696____251.827
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_dll,clk_wiz_v3_6,{component_name=clk_dll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_dll
(// Clock in ports
input clk50in,
// Clock out ports
output clk50,
output clk25,
output clk3p2,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (clk50in));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (16),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (125),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Status and control signals
.LOCKED (LOCKED),
.RST (RESET),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (clk50),
.I (clkout0));
BUFG clkout2_buf
(.O (clk25),
.I (clkout1));
BUFG clkout3_buf
(.O (clk3p2),
.I (clkout2));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { cin.tie(0), cout.tie(0); ios::sync_with_stdio(false); int t; cin >> t; while (t--) { int n, l, r, now = 1; cin >> n; for (int i = 0; i < n; i++) { cin >> l >> r; if (now < l) { now = l; } if (now <= r) { cout << now << ; now++; } else { cout << 0 << ; } } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n; long long k, time, maks, tot, ar[10005], ans, temp, m; bool cek; scanf( %d %I64d %I64d , &n, &m, &k); for (i = 0; i < n; ++i) scanf( %I64d , &ar[i]); if ((n % 2) == 0) printf( 0 n ); else { ans = 0; time = (n + 1) / 2; if (time > m) printf( 0 n ); else { temp = m / time; maks = temp * k; ans = ar[0]; for (i = 2; i < n; i += 2) ans = min(ans, ar[i]); ans = min(ans, maks); printf( %I64d n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a[1000000], b = 0, c = 0, d = 0; long long int n, i; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; d += a[i]; } d = d / n; for (i = 1; i <= n; i++) { b += a[i] - d; c += abs(b); } cout << c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[100001]; bool seen[100001]; int n, q; vector<int> v, c; long long cal() { long long a, b; cin >> a >> b; for (int i = 0; i < 100001; i++) seen[i] = false; int c1, c2; c1 = c2 = -1; for (int i = 0; i < n; i++) { long long maxV = b * v[i]; if (seen[c[i]]) { maxV = (((dp[c[i]] + a * v[i]) > (maxV)) ? (dp[c[i]] + a * v[i]) : (maxV)); } if (c1 >= 0 && c1 != c[i]) { maxV = (((dp[c1] + b * v[i]) > (maxV)) ? (dp[c1] + b * v[i]) : (maxV)); } if (c2 >= 0 && c2 != c[i]) { maxV = (((dp[c2] + b * v[i]) > (maxV)) ? (dp[c2] + b * v[i]) : (maxV)); } if (!seen[c[i]]) dp[c[i]] = maxV; seen[c[i]] = true; dp[c[i]] = (((maxV) > (dp[c[i]])) ? (maxV) : (dp[c[i]])); if (c1 < 0 || maxV > dp[c1]) { c2 = c1; c1 = c[i]; } else if (c2 < 0 || maxV > dp[c2] && c[i] != c1) { c2 = c[i]; } } if (c1 >= 0) return (((dp[c1]) > (0LL)) ? (dp[c1]) : (0LL)); return 0LL; } int main() { cin >> n >> q; for (int i = 0; i < n; i++) { int tmp; cin >> tmp; v.push_back(tmp); } for (int i = 0; i < n; i++) { int tmp; cin >> tmp; c.push_back(tmp); } for (int i = 0; i < q; i++) cout << cal() << endl; return 0; }
|
/*
* There are a number of problem that this example uncovers.
*
* It appears that the inverter connected to the ctl input of the
* tranif gate is not getting the signal passed to it. It looks
* like once the ctl signal is pulled into the island it can not
* propagate the signal back out. The fix may be in the compiler
* where we should only use the island port signal for the tranif
* control instead of any signal that connects to the ctl net.
*
* When the ctl signal removes the connection between the two
* nets they should self resolve. Is appears that when the ctl
* signal is removed the nets stay at their current value.
*/
module top;
reg pass;
reg ctl, ctl2, in, in2;
wire y1, y2, ctlb, y2b;
assign y1 = in;
pullup (weak1) (y2);
tranif0 q1(y1, y2, ctl);
assign y2 = ctl2 ? in2 : 1'bz;
not q2(ctlb, ctl);
not q3(y2b, y2);
initial begin
pass = 1'b1;
// The tran gate is closed and both sides should track 'in'.
ctl = 1'b0;
ctl2 = 1'b0;
in = 1'b1;
#1;
if (ctlb !== 1'b1) begin
$display("Failed ctlb with ctl = 0, expected 1'b1, got %b", ctlb);
pass = 1'b0;
end
if (y2 !== 1'b1) begin
$display("Failed tran with ctl = 0, in = 1, expected 1'b1, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b0) begin
$display("Failed y2b with ctl = 0, in = 1, expected 1'b0, got %b", y2b);
pass = 1'b0;
end
in = 1'b0;
#1;
if (y2 !== 1'b0) begin
$display("Failed tran with ctl = 0, in = 0, expected 1'b0, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b1) begin
$display("Failed y2b with ctl = 0, in = 0, expected 1'b1, got %b", y2b);
pass = 1'b0;
end
// The tran gate is open so y2 should go high (pullup).
ctl = 1'b1;
#1;
if (ctlb !== 1'b0) begin
$display("Failed ctlb with ctl = 1, expected 1'b0, got %b", ctlb);
pass = 1'b0;
end
if (y2 !== 1'b1) begin
$display("Failed tran with ctl = 1, expected 1'b1, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b0) begin
$display("Failed y2b with ctl = 1, expected 1'b0, got %b", y2b);
pass = 1'b0;
end
// Now try driving y2 from in2.
ctl2 = 1'b1;
in2 = 1'b1;
#1;
if (y2 !== 1'b1) begin
$display("Failed tran with ctl2 = 1, in2 = 1, expected 1'b1, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b0) begin
$display("Failed y2b with ctl2 = 1, in2 = 1, expected 1'b0, got %b", y2b);
pass = 1'b0;
end
in2 = 1'b0;
#1;
if (y2 !== 1'b0) begin
$display("Failed tran with ctl2 = 1, in2 = 0, expected 1'b0, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b1) begin
$display("Failed y2b with ctl2 = 1, in2 = 0, expected 1'b1, got %b", y2b);
pass = 1'b0;
end
// Now back to just a pullup on y2.
ctl2 = 1'b0;
#1;
if (y2 !== 1'b1) begin
$display("Failed tran with ctl2 = 0, expected 1'b1, got %b", y2);
pass = 1'b0;
end
if (y2b !== 1'b0) begin
$display("Failed y2b with ctl2 = 0, expected 1'b0, got %b", y2b);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << Black << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg [40:0] quad; initial quad = 41'ha_bbbb_cccc;
reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678;
reg [31:0] str; initial str = "\000\277\021\n";
reg [47:0] str2; initial str2 = "\000what!";
reg [79:0] str3; initial str3 = "\000hmmm!1234";
reg [8:0] nine; initial nine = 12;
string svs = "sv-str";
sub sub ();
sub2 sub2 ();
initial begin
$write("[%0t] In %m: Hi\n", $time);
sub.write_m;
sub2.write_m;
// Escapes
$display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line.
// Display formatting
$display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
nine, nine, quad, quad);
$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
nine, nine, quad, quad);
$display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time,
nine, nine, quad, quad, wide, wide);
//
// verilator lint_off WIDTH
$display("[%0t] %%C=%C %%0C=%0C", $time,
"a"+nine, "a"+nine);
$display("[%0t] %%c=%c %%0c=%0c", $time,
"a"+nine, "a"+nine);
// verilator lint_on WIDTH
$display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%P=%P", $time,
svs);
$display("[%0t] %%u=%u %%0u=%0u", $time,
{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
$display("[%0t] %%U=%U %%0U=%0U", $time,
{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
// %z is tested in t_sys_sformat.v
$display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time,
nine, nine, nine, nine, nine);
$display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time,
$time, $time, $time);
$display;
// Not testing %0s, it does different things in different simulators
$display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
str2[7:0], str2, str3);
$display("[%0t] %s%s%s", $time,
"hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
$display("hel", "lo, fr", "om a concatenated string.");
$write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time);
$display("extra argument: ", $time);
$write("[%0t] Embedded \r return\n", $time);
$display("[%0t] Embedded\
multiline", $time);
// Str check
`ifndef NC // NC-Verilog 5.3 chokes on this test
if (str !== 32'h00_bf_11_0a) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub;
task write_m;
begin
$write("[%0t] In %m (%l)\n", $time);
begin : subblock
$write("[%0t] In %M (%L)\n", $time); // Uppercase %M test
end
end
endtask
endmodule
module sub2;
// verilator no_inline_module
task write_m;
begin
$write("[%0t] In %m (%l)\n", $time);
begin : subblock2
$write("[%0t] In %m (%L)\n", $time);
end
end
endtask
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "qlf_k6n10f/cells_sim.v"
module tb();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#2 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Filter control
reg [2:0] fcnt;
reg [3:0] dcnt;
initial begin
fcnt <= 0;
dcnt <= 0;
end
// MAC cycle counter
always @(posedge clk)
if (rst) fcnt <= 0;
else begin
if (fcnt == 4)
fcnt <= 0;
else
fcnt <= fcnt + 1;
end
wire stb = (fcnt == 4);
// Data address counter
always @(posedge clk)
if (rst) dcnt <= 0;
else if (stb) dcnt <= dcnt + 1;
// Filter coeffs (S0.19)
reg signed [19:0] coeff;
always @(*) case (fcnt)
2'd0: coeff <= 20'h0000B;
2'd1: coeff <= 20'h0000E;
2'd2: coeff <= 20'h0000E;
2'd3: coeff <= 20'h0000F;
default: coeff <= 20'h00000;
endcase
// Input data (S0.17)
reg signed [17:0] data;
always @(*) case (dcnt)
'd0: data <= 18'h00400;
'd1: data <= 18'h00000;
'd2: data <= 18'h00000;
'd3: data <= 18'h00000;
'd4: data <= 18'h00000;
'd5: data <= 18'h00000;
'd6: data <= 18'h00000;
'd7: data <= 18'h00000;
'd8: data <= 18'h00800;
default data <= 18'h00000;
endcase
// UUT
wire signed [3:0] acc_fir_i = 4'h0;
wire signed [19:0] A = coeff;
wire signed [17:0] B = data;
wire signed [37:0] Z;
dsp_t1_sim # (
) uut (
.clock_i (clk),
.reset_n_i (~rst),
.a_i ((!stb) ? A : 20'h0),
.b_i ((!stb) ? B : 18'h0),
.acc_fir_i ((!stb) ? acc_fir_i : 4'h0),
.unsigned_a_i (1'b0),
.unsigned_b_i (1'b0),
.feedback_i (stb),
.load_acc_i (1'b1),
.shift_right_i (6'd10),
.register_inputs_i (1'b0),
.output_select_i (3'h1),
.round_i (1'b1),
.saturate_enable_i (1'b1),
.subtract_i (1'b0),
.z_o (Z)
);
// Output counter
integer ocnt;
initial ocnt <= 0;
always @(posedge clk)
if (stb) ocnt <= ocnt + 1;
// Expected output data
reg signed [31:0] odata;
always @(*) case (ocnt)
'd0: odata <= 32'h000036;
'd1: odata <= 32'h000000;
'd2: odata <= 32'h000000;
'd3: odata <= 32'h000000;
'd4: odata <= 32'h000000;
'd5: odata <= 32'h000000;
'd6: odata <= 32'h000000;
'd7: odata <= 32'h000000;
'd8: odata <= 32'h00006C;
default: odata <= 32'h000000;
endcase
// Error detection
wire error = stb && (odata !== Z[31:0]);
// Error counting
integer error_count;
initial error_count <= 0;
always @(posedge clk) begin
if (error) error_count <= error_count + 1;
end
// Simulation control / data dump
initial begin
$dumpfile(`VCD_FILE);
$dumpvars(0, tb);
#150 $finish_and_return( (error_count == 0) ? 0 : -1 );
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int casos; cin >> casos; while (casos > 0) { int a, b; cin >> a >> b; if (a > b) { int dif = a - b; b -= dif; a -= dif * 2; } else if (b > a) { int dif = b - a; a -= dif; b -= dif * 2; } if (a % 3 == 0 && a == b && a >= 0) { printf( YES n ); } else { printf( NO n ); } casos--; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_2_V
`define SKY130_FD_SC_HD__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_2_V
|
#include <bits/stdc++.h> using namespace std; namespace mine { long long qread() { long long ans = 0, f = 1; char c = getchar(); while (c < 0 or c > 9 ) { if (c == - ) f = -1; c = getchar(); } while ( 0 <= c and c <= 9 ) ans = ans * 10 + c - 0 , c = getchar(); return ans * f; } void write(long long num) { if (num < 0) putchar( - ), num = -num; if (num >= 10) write(num / 10); putchar( 0 + num % 10); } void write1(long long num) { write(num); putchar( ); } void write2(long long num) { write(num); putchar( n ); } template <typename T> void chmax(T &x, const T y) { x = (x > y ? x : y); } template <typename T> void chmin(T &x, const T y) { x = (x < y ? x : y); } long long gcd(long long x, long long y) { return y ? gcd(y, x % y) : x; } const int INF = 0x3f3f3f3f; const int MOD = 998244353; inline int mm(const int x) { return x >= MOD ? x - MOD : x; } template <typename T> inline void add(T &x, const T y) { x = mm(x + y); } inline long long qpower(long long x, long long e, int mod = MOD) { long long ans = 1; if (e < 0) { puts( error ); exit(666); } while (e) { if (e & 1) ans = ans * x % mod; x = x * x % mod; e >>= 1; } return ans; } long long invm(long long x) { return qpower(x, MOD - 2); } const int N = 2e5 + 10; int n; namespace SGT { int mxc[N * 4]; void change_cnt(int x, int l, int r, int pos, int num) { if (l == r) { mxc[x] = num; return; } if (pos <= (l + r) / 2) change_cnt(x << 1, l, (l + r) / 2, pos, num); else change_cnt(x << 1 | 1, (l + r) / 2 + 1, r, pos, num); mxc[x] = max(mxc[x << 1], mxc[x << 1 | 1]); } int ask_cnt(int x, int l, int r, int fl, int fr) { if (fl > fr) return 0; if (l == fl and r == fr) return mxc[x]; if (fr <= (l + r) / 2) return ask_cnt(x << 1, l, (l + r) / 2, fl, fr); if (fl > (l + r) / 2) return ask_cnt(x << 1 | 1, (l + r) / 2 + 1, r, fl, fr); return max(ask_cnt(x << 1, l, (l + r) / 2, fl, (l + r) / 2), ask_cnt(x << 1 | 1, (l + r) / 2 + 1, r, (l + r) / 2 + 1, fr)); } int mif[N * 4], tag[N * 4], mifl[N * 4], mifr[N * 4], sum[N * 4]; void init(int x, int l, int r) { mifl[x] = l; mifr[x] = r; if (l < r) init(x << 1, l, (l + r) / 2), init(x << 1 | 1, (l + r) / 2 + 1, r); } void pushdown(int x) { if (tag[x] != 0) mif[x << 1] += tag[x], mif[x << 1 | 1] += tag[x], tag[x << 1] += tag[x], tag[x << 1 | 1] += tag[x], tag[x] = 0; } void pushup(int x, int l, int r) { if (l == r) { sum[x] = ask_cnt(x, l, r, l, l); return; } pushdown(x); if (mif[x << 1] == mif[x << 1 | 1]) { mif[x] = mif[x << 1]; mifl[x] = mifl[x << 1]; mifr[x] = mifr[x << 1 | 1]; sum[x] = sum[x << 1] + sum[x << 1 | 1] - ask_cnt(x, l, r, mifr[x << 1] + 1, (l + r) / 2) - ask_cnt(x, l, r, (l + r) / 2 + 1, mifl[x << 1 | 1]) + ask_cnt(x, l, r, mifr[x << 1] + 1, mifl[x << 1 | 1]); } else if (mif[x << 1] < mif[x << 1 | 1]) { mif[x] = mif[x << 1]; mifl[x] = mifl[x << 1]; mifr[x] = mifr[x << 1]; sum[x] = sum[x << 1] - ask_cnt(x, l, r, mifr[x << 1] + 1, (l + r) / 2) + ask_cnt(x, l, r, mifr[x << 1] + 1, r); } else { mif[x] = mif[x << 1 | 1]; mifl[x] = mifl[x << 1 | 1]; mifr[x] = mifr[x << 1 | 1]; sum[x] = sum[x << 1 | 1] - ask_cnt(x, l, r, (l + r) / 2 + 1, mifl[x << 1 | 1]) + ask_cnt(x, l, r, l, mifl[x << 1 | 1]); } } void add_f(int x, int l, int r, int fl, int fr, int val) { if (l == fl and r == fr) { mif[x] += val; tag[x] += val; pushup(x, l, r); return; } pushdown(x); if (fr <= (l + r) / 2) add_f(x << 1, l, (l + r) / 2, fl, fr, val); else if (fl > (l + r) / 2) add_f(x << 1 | 1, (l + r) / 2 + 1, r, fl, fr, val); else add_f(x << 1, l, (l + r) / 2, fl, (l + r) / 2, val), add_f(x << 1 | 1, (l + r) / 2 + 1, r, (l + r) / 2 + 1, fr, val); pushup(x, l, r); } void add_f(int l, int r, int val) { if (l <= r) add_f(1, 1, n, l, r, val); } void change_cnt(int pos, int num) { change_cnt(1, 1, n, pos, num); add_f(pos, pos, 0); } }; // namespace SGT int a[N]; set<int> pos[N]; void main() { n = qread(); int q = qread(); SGT::init(1, 1, n); for (int i = (1), I = (n); i <= I; i++) a[i] = qread(), pos[a[i]].insert(i); for (int num = (1), I = (N - 1); num <= I; num++) if (((int)(pos[num]).size())) SGT::change_cnt(*pos[num].begin(), ((int)(pos[num]).size())), SGT::add_f(*pos[num].begin(), *(--pos[num].end()) - 1, 1); write2(n - SGT::sum[1]); while (q--) { int x = qread(), val = qread(); set<int>::iterator now = pos[a[x]].find(x); SGT::change_cnt(*pos[a[x]].begin(), 0); if (((int)(pos[a[x]]).size()) > 1) { if (now == pos[a[x]].begin()) SGT::add_f(x, *(++now) - 1, -1); else if (now == --pos[a[x]].end()) SGT::add_f(*(--now), x - 1, -1); } pos[a[x]].erase(x); if (((int)(pos[a[x]]).size())) SGT::change_cnt(*pos[a[x]].begin(), ((int)(pos[a[x]]).size())); a[x] = val; pos[a[x]].insert(x); SGT::change_cnt(*pos[a[x]].begin(), ((int)(pos[a[x]]).size())); now = pos[a[x]].find(x); if (((int)(pos[a[x]]).size()) > 1) { if (now == pos[a[x]].begin()) { now++; SGT::add_f(x, *now - 1, 1); SGT::change_cnt(*now, 0); } else if (now == --pos[a[x]].end()) SGT::add_f(*(--now), x - 1, 1); } write2(n - SGT::sum[1]); } } }; // namespace mine signed main() { srand(time(0)); mine::main(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_FUNCTIONAL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_alu_control (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 2: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 2: 0] data_out;
wire [ 2: 0] out_port;
wire [ 2: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {3 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[2 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_cmdram_wrap.v
// Version : v1.0
// Description: command ram wrapper module: To manage the read/write
// addresses to cmdram module.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_cmdram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_RAMINIT_CMDRAM0_F = "NONE",
parameter C_RAMINIT_CMDRAM1_F = "NONE",
parameter C_RAMINIT_CMDRAM2_F = "NONE",
parameter C_RAMINIT_CMDRAM3_F = "NONE"
) (
input Clk ,
input rst_l ,
input [15:0 ] cmdram_we ,
input [15:0 ] aw_agen_addr ,
input reg0_m_enable_ff ,
input [9:0 ] reg0_mw_ptr_update , //maw_ptr_new
input [9:0 ] reg0_mr_ptr_update , //mar_ptr_new
input [9:0 ] mar_ptr_new_ff ,
input [15:0 ] ar_agen0_addr ,
input [63:0 ] slvram_wr_data ,
input arfifo_valid ,
input [71:0 ] arfifo_out ,
input [23:0 ] param_cmdr_submitcnt_ff ,
input [23:0 ] param_cmdw_submitcnt_ff ,
input [9:0 ] maw_ptr_new_ff ,
output [127:0] cmd_out_mr_i ,
output cmdram_mr_regslice_id_stable,
output [127:0] cmd_out_mw_regslice ,
output [127:0] cmd_out_mr_regslice ,
output [127:0] cmd_out_mw_regslice_ff ,
output [127:0] cmd_out_mr_regslice_ff ,
output cmdram_mw_regslice_id_stable
);
wire [9:0] maw_ptr_new = reg0_mw_ptr_update;
wire [9:0] mar_ptr_new = reg0_mr_ptr_update;
wire [127:0] cmd_out_mw_i;
wire [15:0] cmdram_addra = (reg0_m_enable_ff) ?
{ 4'b0001, maw_ptr_new[7:0], 4'b0000 } :
{ 3'b000, aw_agen_addr[12:4], 4'b0000 };
wire [15:0] cmdram_addrb = (reg0_m_enable_ff) ?
{ 4'b0000, mar_ptr_new[7:0], 4'b0000 } :
{ 3'b000, ar_agen0_addr[12:4], 4'b0000 };
wire [127:0] cmd_out_mw_raw;
wire [127:0] cmd_out_mr_raw;
generate if (C_ATG_BASIC_AXI4 == 0 ) begin : CMDRAM_FULLAXI
assign cmd_out_mw_i = cmd_out_mw_raw;
assign cmd_out_mr_i = cmd_out_mr_raw;
end
endgenerate
//
//Fixed controls for a basic axi4 support.
//
wire [2:0] size;
generate if(C_M_AXI_DATA_WIDTH == 32 ) begin : CMDWRAP_SISE32
assign size = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64 ) begin : CMDWRAP_SISE64
assign size = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128 ) begin : CMDWRAP_SISE128
assign size = 3'b100;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256 ) begin : CMDWRAP_SISE256
assign size = 3'b101;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512 ) begin : CMDWRAP_SISE512
assign size = 3'b110;
end
endgenerate
wire fixed_lock = 1'b0;
wire [1:0] fixed_burst = 2'b01;
wire [2:0] fixed_prot = 3'b010;
wire [3:0] fixed_cache = 4'h0;
wire [7:0] fixed_user = 7'h0;
wire [2:0] fixed_size = size;
wire [3:0] fixed_qos = 4'h0;
generate if (C_ATG_BASIC_AXI4 == 1 ) begin : CMDRAM_BASICAXI
assign cmd_out_mw_i = {
cmd_out_mw_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mw_raw[99:96],
cmd_out_mw_raw[95:64],
cmd_out_mw_raw[63:56],fixed_prot,cmd_out_mw_raw[52:47],fixed_size,fixed_burst,cmd_out_mw_raw[41],fixed_lock,cmd_out_mw_raw[39:32],
cmd_out_mw_raw[31:0]
};
assign cmd_out_mr_i = {
cmd_out_mr_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mr_raw[99:96],
cmd_out_mr_raw[95:64],
cmd_out_mr_raw[63:56],fixed_prot,cmd_out_mr_raw[52:47],fixed_size,fixed_burst,cmd_out_mr_raw[41],fixed_lock,cmd_out_mr_raw[39:32],
cmd_out_mr_raw[31:0]
};
end
endgenerate
axi_traffic_gen_v2_0_7_cmdram #(
.C_FAMILY (C_FAMILY ),
.C_INITRAM_0(C_RAMINIT_CMDRAM0_F),
.C_INITRAM_1(C_RAMINIT_CMDRAM1_F),
.C_INITRAM_2(C_RAMINIT_CMDRAM2_F),
.C_INITRAM_3(C_RAMINIT_CMDRAM3_F)
) Cmdram (
.reset (~rst_l ),
.clk_a (Clk ),
.we_a (cmdram_we[15:0] ),
.active (reg0_m_enable_ff ),
.addr_a_idle ({ 3'b000, aw_agen_addr[12:4], 4'b0000 } ),
.addr_a_active ( { 4'b0001, maw_ptr_new_ff[7:0], 4'b0000 }),
.wr_data_a ({ 2 { slvram_wr_data[63:0] } } ),
.rd_data_a (cmd_out_mw_raw[127:0] ),
.clk_b (Clk ),
.addr_b_idle_latch(arfifo_valid ),
.addr_b_idle ({ 3'b000, arfifo_out[12:4], 4'b0000 } ),
.addr_b_active ({ 4'b0000, mar_ptr_new_ff[7:0], 4'b0000 } ),
.rd_data_b (cmd_out_mr_raw[127:0] )
);
// id is a mix of submitcnt,mar_ptr -- so can ID new cmds even if just a repeat
wire [9:0] cmdram_mr_regslice_idin = {param_cmdr_submitcnt_ff[0],1'b0, mar_ptr_new_ff[7:0]};
wire [9:0] cmdram_mw_regslice_idin = {param_cmdw_submitcnt_ff[0],reg0_m_enable_ff, maw_ptr_new_ff[7:0]};
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MR_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MR_ID )
)
cmdram_regslice_r
(
.din (cmd_out_mr_i ),
.dout (cmd_out_mr_regslice_ff ),
.dout_early (cmd_out_mr_regslice ),
.idin (cmdram_mr_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mr_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MW_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MW_ID )
)
cmdram_regslice_w
(
.din (cmd_out_mw_i ),
.dout (cmd_out_mw_regslice_ff ),
.dout_early (cmd_out_mw_regslice ),
.idin (cmdram_mw_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mw_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__EBUFN_PP_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_PP_BLACKBOX_V
|
// Verilog test fixture created from schematic B:\NICNAC16\dunc16.sch - Wed Sep 17 00:13:28 2014
`timescale 1ns / 1ps
module dunc16_dunc16_sch_tb();
// Inputs
reg CLK;
reg RESET;
// Output
wire I_STA;
wire I_LDA;
wire I_JMP;
wire I_ADD;
wire I_BL;
wire I_RET;
wire I_BAN;
wire EN_MD;
wire EN_MA;
wire EN_AC;
wire EN_PC;
wire EN_IR;
wire DO_BL;
wire DO_JUMP;
wire DO_RET;
wire DO_ADD;
wire DO_LDA;
wire INCR_PC;
wire [15:0] PC_OUT;
wire [15:0] AC_OUT;
wire [15:0] AC_IN;
wire [15:0] MD_OUT;
wire [15:0] PC_IN;
wire [3:0] IR_OUT;
wire [15:0] LINK_OUT;
wire [15:0] MA_OUT;
wire [15:0] MA_IN;
wire [15:0] MD_IN;
wire [15:0] MEMORY_READ;
wire [15:0] MMO;
wire AZ;
wire AN;
reg ININ;
// Bidirs
// Instantiate the UUT
dunc16 UUT (
.I_STA(I_STA),
.I_LDA(I_LDA),
.I_JMP(I_JMP),
.I_BAN(I_BAN),
.I_ADD(I_ADD),
.I_BL(I_BL),
.I_RET(I_RET),
.AN(AN),
.AZ(AZ),
.DO_BL(DO_BL),
.DO_RET(DO_RET),
.DO_JUMP(DO_JUMP),
.DO_ADD(DO_ADD),
.DO_LDA(DO_LDA),
.INCR_PC(INCR_PC),
.T0(T0),
.T1(T1),
.T2(T2),
.T3(T3),
.EN_MD(EN_MD),
.EN_MA(EN_MA),
.EN_AC(EN_AC),
.EN_PC(EN_PC),
.EN_IR(EN_IR),
.MEMORY_READ(MEMORY_READ),
.AC_OUT(AC_OUT),
.AC_IN(AC_IN),
.MD_OUT(MD_OUT),
.IR_OUT(IR_OUT),
.LINK_OUT(LINK_OUT),
.PC_OUT(PC_OUT),
.PC_IN(PC_IN),
.MA_IN (MA_IN),
.MD_IN (MD_IN),
.MMO(MMO),
.MA_OUT(MA_OUT),
.ININ(ININ),
.CLK(CLK),
.RESET(RESET)
);
initial begin
$monitor("%b%b%b%b PC=%h, f%be%b, s%bl%b. %h %h",UUT.T0,UUT.T1,UUT.T2,UUT.T3,UUT.PC.Q,UUT.FETCH, UUT.EXECUTE, I_STA, UUT.I_LDA, UUT.MD.Q, UUT.AC.Q);
end
initial begin
ININ = 0;
CLK = 0;
//start reset
RESET = 1'b1;
repeat(4)
#1
CLK = ~CLK;
RESET = 1'b0;
// end reset
forever
#1
CLK = ~CLK; // generate a clock
end
initial begin
@(negedge RESET); // wait for reset
repeat (960)
@(posedge CLK);
$finish;
end
endmodule
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: double hash miner
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module miner253 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
parameter NONCE2_OFFS = 32'd0;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, hash2, nonce2;
reg [31:0] nonce;
wire [255:0] hash;
wire [31:0] hash2_w;
reg reset_b1, reset_b2, reset_b3, is_golden_nonce;
sha256_pipe130 p1 (
.clk(clk),
.state(midstate),
.state2(midstate),
.data({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash(hash)
);
sha256_pipe123 p2 (
.clk(clk),
.data({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash(hash2_w)
);
always @ (posedge clk)
begin
if ( reset_b1 )
begin
nonce <= 32'd254 + NONCE_OFFS;
end else begin
nonce <= nonce + NONCE_INCR;
end
if ( reset_b2 )
begin
nonce2 <= NONCE_OFFS + NONCE2_OFFS;
end else begin
nonce2 <= nonce2 + NONCE_INCR;
end
if ( reset_b3 )
begin
golden_nonce1 <= 32'd0;
golden_nonce2 <= 32'd0;
end
else if ( is_golden_nonce )
begin
golden_nonce1 <= nonce2;
golgen_nonce2 <= golden_nonce1;
end
reset_b1 <= reset;
reset_b2 <= reset;
reset_b3 <= reset;
hash2 <= hash2_w;
is_golden_nonce <= hash2_w == 32'ha41f32e7;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_SYMBOL_V
`define SKY130_FD_SC_HD__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file side.v when simulating
// the core, side. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module side(
clka,
addra,
douta
);
input clka;
input [16 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("side.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(76800),
.C_READ_DEPTH_B(76800),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(76800),
.C_WRITE_DEPTH_B(76800),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v; vector<string> veg; bool comp(pair<int, int> p1, pair<int, int> p2) { return (p1.first < p2.first or ((p1.first == p2.first) and (p1.second < p2.second))); } int main() { int n, m, k, t, x, y; veg.push_back( Grapes ); veg.push_back( Carrots ); veg.push_back( Kiwis ); cin >> n >> m >> k >> t; while (k--) { cin >> x >> y; v.push_back(make_pair(x, y)); } sort(v.begin(), v.end(), comp); while (t--) { int f = 0, s = 0; int left = 0, right = v.size() - 1; cin >> f >> s; int mid = (left + right) / 2, flag = 0; while (left < right) { mid = left + (right - left) / 2 + 1; if (v[mid].first == f and v[mid].second == s) { flag = 1; cout << Waste << endl; break; } if (f < v[mid].first or (f == v[mid].first and s < v[mid].second)) right = mid - 1; else left = mid; } if (!flag) { if (v[left].first == f and v[left].second == s) cout << Waste << endl; else { if (v[left].first > f or v[left].first == f and v[left].second > s) left--; cout << veg[((f - 1) * m + s - left - 1) % 3] << endl; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_SYMBOL_V
`define SKY130_FD_SC_HD__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, p; set<int> ss; int idx[500500]; char str[500500], op[500500]; int main() { cin >> n >> m >> p; scanf( %s%s , str + 1, op + 1); stack<int> s; ss.insert(0); for (int i = 1; i <= n; i++) { ss.insert(i); if (str[i] == ( ) s.push(i); else idx[s.top()] = i, idx[i] = s.top(), s.pop(); } for (int i = 1; i <= m; i++) { if (op[i] == R ) p = *ss.upper_bound(p); else if (op[i] == L ) p = *prev(ss.lower_bound(p)); else { auto it = ss.lower_bound(p); int from = *it; int to = idx[from]; int val; do { val = *it; auto nxt = it; if (from < to) nxt++; else nxt--; ss.erase(it); it = nxt; } while (val != to); if (from > to) it++; if (it == ss.end()) it--; p = *it; } } for (auto it : ss) if (it) printf( %c , str[it]); puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-11-01 17:10:58
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module DW_mult
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
reg [2*SW-1:0] Result;
always @* begin
Result = Data_A_i *Data_B_i ;
end
RegisterAdd #(.W(2*SW)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result),
.Q(sgf_result_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; long long n, m, i, j, k = 200000; n = a.size(); m = b.size(); for (i = 1; i <= k; i++) { if (n - i >= 0 && m - i >= 0) { if (a[n - i] != b[m - i]) break; } else break; } cout << (n - i) + 1 + (m - i) + 1; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_2_V
`define SKY130_FD_SC_LS__FILL_DIODE_2_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_2_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; long long a[200011]; string s; int main() { long long n, k, i, x, res = 0, j; cin >> n >> k; for (i = 0; i < n; i++) cin >> a[i]; cin >> s; char C = A ; for (i = 0; i < n; i++) { x = k; if (s[i] == C) v.push_back(a[i]); if (s[i] != C || i == n - 1) { if (i == n - 1 && s[i] != C) res += a[i]; C = s[i]; sort(v.begin(), v.end()); if (v.size()) { for (j = v.size() - 1; j >= 0; j--) { if (x > 0) { res += v[j]; x--; } } v.erase(v.begin(), v.end()); } v.push_back(a[i]); } } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = int64_t; using ull = uint64_t; inline void solve() {} int main() { ios::sync_with_stdio(0); cin.tie(0); string s; cin >> s; int lucky = 0; for (auto const &c : s) lucky += c == 4 || c == 7 ; bool is_lucky = lucky > 0; while (lucky) { int x = lucky % 10; if (!(x == 4 || x == 7)) is_lucky = false; lucky /= 10; } cout << (is_lucky ? YES : NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tc; cin >> tc; while (tc--) { int n; cin >> n; priority_queue<pair<int, int> > pq; for (int i = 0; i < n; i++) { int ai; cin >> ai; pq.push(pair<int, int>(ai, i)); } int turn = 0; while (not pq.empty()) { auto pp = pq.top(); pq.pop(); turn = 1 - turn; if (pq.empty()) break; auto qq = pq.top(); pq.pop(); turn = 1 - turn; pp.first -= 1; qq.first -= 1; if (pp.first != 0) pq.push(pp); if (qq.first != 0) pq.push(qq); } if (turn == 0) cout << HL n ; else cout << T n ; } return (0); }
|
#include <bits/stdc++.h> const long double pie = 3.1415926535; using namespace std; bool br1, br2, br; long long n, k, x, y, z, mini, maxi, l, ind, ini, sum, t, len, r, q, imini, w, m; string s, s1, s2; struct Point { long long X, Y; static long long getDir(Point a, Point b, Point c) { return ((b.X - a.X) * (c.Y - a.Y) - (b.Y - a.Y) * (c.X - a.X)); } }; void solve() { Point A, B, C; cin >> A.X >> A.Y >> B.X >> B.Y >> C.X >> C.Y; m = A.getDir(A, B, C); if (m == 0) cout << TOWARDS << endl; else if (m > 0) cout << LEFT << endl; else cout << RIGHT << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; static const int INF = 500000000; template <class T> void debug(T a, T b) { for (; a != b; ++a) cerr << *a << ; cerr << endl; } string s[2005]; int n, K; int lcp[2005]; int prof[2005][2005]; struct uf { int par[2005]; vector<int> dp[2005]; void init(int n) { for (int i = 0; i < n; ++i) { dp[i].resize(2); } memset(par, -1, sizeof(par)); } int root(int a) { if (par[a] == -1) return a; return par[a] = root(par[a]); } void unite(int a, int b, int lb) { a = root(a); b = root(b); vector<int> tmp(dp[a].size() + dp[b].size() - 1); for (int i = 0; i < dp[a].size(); ++i) for (int j = 0; j < dp[b].size(); ++j) tmp[i + j] = max(tmp[i + j], dp[a][i] + dp[b][j] + lb * i * j); par[a] = b; dp[b] = tmp; dp[a].clear(); } }; uf u; int used[2005]; int main() { scanf( %d%d , &n, &K); for (int i = 0; i < n; ++i) cin >> s[i]; sort(s, s + n); u.init(n); for (int i = 0; i < n - 1; ++i) { int& t = lcp[i]; for (t = 0; t < s[i].size() && t < s[i + 1].size() && s[i][t] == s[i + 1][t]; ++t) ; } for (int i = 0; i < n - 1; ++i) { int tallest = -1, ind; for (int j = 0; j < n - 1; ++j) if (used[j] == 0 && tallest < lcp[j]) { tallest = lcp[j]; ind = j; } used[ind] = 1; u.unite(ind, ind + 1, tallest); } printf( %d n , u.dp[u.root(0)][K]); return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_65_256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_65_256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [64:0] data;
input rdreq;
input wrreq;
output empty;
output [64:0] q;
wire sub_wire0;
wire [64:0] sub_wire1;
wire empty = sub_wire0;
wire [64:0] q = sub_wire1[64:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 65,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "65"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "65"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "65"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 65 0 INPUT NODEFVAL "data[64..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 65 0 OUTPUT NODEFVAL "q[64..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 65 0 data 0 0 65 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 65 0 @q 0 0 65 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_65_256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// Modifications Copryright (c) 2017 Simon Southwell. All rights reserved.
module USB_JTAG (// HOST
iTxD_DATA, oTxD_Done, iTxD_Start,
oRxD_DATA, oRxD_Ready, iRST_n,iCLK,
// JTAG
TDO, TDI, TCS, TCK);
input [7:0] iTxD_DATA;
input iTxD_Start, iRST_n, iCLK;
output reg [7:0] oRxD_DATA;
output reg oTxD_Done, oRxD_Ready;
input TDI, TCS, TCK;
output TDO;
wire [7:0] mRxD_DATA;
wire mTxD_Done, mRxD_Ready;
reg Pre_TxD_Done, Pre_RxD_Ready;
reg mTCK;
// JTAG Receive
JTAG_REC u0 (mRxD_DATA, mRxD_Ready, TDI, TCS, mTCK);
// JTAG Transmitter
JTAG_TRANS u1 (iTxD_DATA, iTxD_Start, mTxD_Done, TDO, TCK, TCS);
// JTAG CLK Sync
always @(posedge iCLK)
begin
mTCK <= TCK;
end
// JTAG Receiver Sync.
always @(posedge iCLK or negedge iRST_n)
begin
if(!iRST_n)
begin
oRxD_Ready <= 1'b0;
Pre_RxD_Ready <= 1'b0;
end
else
begin
Pre_RxD_Ready <= mRxD_Ready;
if ({Pre_RxD_Ready, mRxD_Ready} == 2'b01 && ~iTxD_Start)
begin
oRxD_Ready <= 1'b1;
oRxD_DATA <= mRxD_DATA;
end
else
begin
oRxD_Ready <= 1'b0;
end
end
end
// JTAG Transmitter Sync.
always @(posedge iCLK or negedge iRST_n)
begin
if(!iRST_n)
begin
oTxD_Done <= 1'b0;
Pre_TxD_Done <= 1'b0;
end
else
begin
Pre_TxD_Done <= mTxD_Done;
if ({Pre_TxD_Done,mTxD_Done} == 2'b01)
begin
oTxD_Done <= 1'b1;
end
else
begin
oTxD_Done <= 1'b0;
end
end
end
endmodule
module JTAG_REC (// HOST
oRxD_DATA, oRxD_Ready,
// JTAG
TDI, TCS, TCK);
input TDI, TCS, TCK;
output reg [7:0] oRxD_DATA;
output reg oRxD_Ready;
reg [7:0] rDATA;
reg [2:0] rCont;
always@(posedge TCK or posedge TCS)
begin
if(TCS)
begin
oRxD_Ready <= 1'b0;
rCont <= 3'b000;
end
else
begin
rCont <= rCont + 3'b001;
rDATA <= {TDI, rDATA[7:1]};
if (rCont == 3'b000)
begin
oRxD_DATA <= {TDI, rDATA[7:1]};
oRxD_Ready <= 1'b1;
end
else
begin
oRxD_Ready <= 1'b0;
end
end
end
endmodule
module JTAG_TRANS (// HOST
iTxD_DATA, iTxD_Start, oTxD_Done,
// JTAG
TDO, TCK, TCS);
input [7:0] iTxD_DATA;
input iTxD_Start;
output reg oTxD_Done;
input TCK, TCS;
output reg TDO;
reg [2:0] rCont;
always@(posedge TCK or posedge TCS)
begin
if (TCS)
begin
oTxD_Done <= 1'b0;
rCont <= 3'b000;
TDO <= 1'b0;
end
else
begin
if (iTxD_Start)
begin
rCont <= rCont + 3'b001;
TDO <= iTxD_DATA[rCont];
end
else
begin
rCont <= 3'b000;
TDO <= 1'b0;
end
if (rCont == 3'b111)
begin
oTxD_Done <= 1'b1;
end
else
begin
oTxD_Done <= 1'b0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; --n; int right, left, down, up; right = left = down = up = n / 4; n = n - up * 4; if (n != 0) { ++right; --n; } if (n != 0) { ++down; --n; } if (n != 0) { ++left; --n; } if (n != 0) { ++up; --n; } int centerx = 0, centery = 0; cout << centerx << << centery << endl; for (int i = 0; i < right; ++i) { cout << centerx + i + 1 << << centery << endl; } for (int i = 0; i < left; ++i) { cout << centerx - i - 1 << << centery << endl; } for (int i = 0; i < up; ++i) { cout << centerx << << centery + i + 1 << endl; } for (int i = 0; i < down; ++i) { cout << centerx << << centery - i - 1 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
/**
* top_xres4v2: XRES (Input buffer with Glitch filter).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_xres4v2 (
//# {{data|Data Signals}}
input FILT_IN_H ,
input INP_SEL_H ,
inout PAD ,
inout PAD_A_ESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input DISABLE_PULLUP_H,
input ENABLE_H ,
input ENABLE_VDDIO ,
input EN_VDDIO_SIG_H ,
output XRES_H_N ,
//# {{power|Power}}
inout PULLUP_H ,
input VSWITCH ,
input VCCD ,
input VCCHIB ,
input VDDA ,
input VDDIO ,
input VDDIO_Q ,
output TIE_HI_ESD ,
inout TIE_WEAK_HI_H ,
input VSSA ,
input VSSD ,
input VSSIO ,
input VSSIO_Q ,
output TIE_LO_ESD
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); std::ios::sync_with_stdio(false); string a; cin >> a; for (int i = 0; i < a.size(); i++) { if (((int)(a[i]) >= 48 && (int)(a[i]) <= 57) || ((int)(a[i]) >= 97 && (int)(a[i]) <= 122) || (int)(a[i]) == 95 || (int)(a[i]) == 64 || (int)(a[i]) == 46 || (int)(a[i]) == 47 || ((int)(a[i]) >= 65 && (int)(a[i]) <= 90)) { continue; } else { cout << NO ; return 0; } } string d = ; int ans1 = -1; for (int i = 0; i < a.size(); i++) { if (a[i] == @ ) { ans1 = i; break; } d += a[i]; } if (ans1 == 0 || ans1 == -1) { cout << NO ; return 0; } for (int i = 0; i < d.size(); i++) { if (d[i] == . || d[i] == / ) { cout << NO ; return 0; } } string e = ; int ans2 = -1; for (int i = ans1 + 1; i < a.size(); i++) { if (a[i] == / ) { ans2 = i; break; } e += a[i]; } if (e.size() == 0) { cout << NO ; return 0; } if (ans2 - ans1 == 1) { cout << NO ; return 0; } int ans3 = 0; for (int i = 0; i < e.size(); i++) { if (e[i] == @ ) { cout << NO ; return 0; } if (e[i] == . ) { ans3++; } } if (e[e.size() - 1] == . || e[0] == . ) { cout << NO ; return 0; } for (int i = 0; i < e.size() - 1; i++) { if (e[i] == . && e[i + 1] == . ) { cout << NO ; return 0; } } if (ans2 == -1) { cout << YES ; return 0; } string r = ; for (int i = ans2 + 1; i < a.size(); i++) { if (a[i] == / || a[i] == . || a[i] == @ ) { cout << NO ; return 0; } } if (ans2 == a.size() - 1) { cout << NO ; return 0; } cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int fact(int n) { long long ans = n; for (int i = n - 1; i > 0; --i) { ans = (ans * i) % MOD; } return ans; } int pow2(int n) { long long ans = 1, b = 2; while (n > 0) { if (n % 2) { ans = (ans * b) % MOD; } b = (b * b) % MOD; n /= 2; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; cout << (fact(n) - pow2(n - 1) + MOD) % MOD; }
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 2e5 + 10; const int MOD = 1e9 + 7; const int INF = 1e9; int main() { int L, n, p, t; cin >> L >> n >> p >> t; if (n == 0) { cout << 0 << n ; exit(0); } vector<pair<int, int> > seg(n); for (int i = 0; i < n; ++i) { cin >> seg[i].first >> seg[i].second; } sort(seg.begin(), seg.end()); set<pair<int, int> > st; map<int, int> f; for (int i = 0; i < n; ++i) { st.insert(make_pair(seg[i].first, i)); } int ans = 0; while (!st.empty()) { int x = st.begin()->first, where = st.begin()->second; ans = max(ans, f[x]); st.erase(st.begin()); int ex = seg[where].second; if (where + 1 < (int)seg.size()) { f[seg[where + 1].first] = max(f[seg[where + 1].first], f[x]); } int can = (ex - x) / p; int val = f[x] + can; ans = max(ans, f[x] + can); if (where + 1 < n && f[seg[where + 1].first] >= val) { continue; } x += (ex - x) / p * p + t; if (where + 1 < n && seg[where + 1].first >= x) { f[seg[where + 1].first] = max(f[seg[where + 1].first], val); continue; } int pos = lower_bound(seg.begin(), seg.end(), make_pair(x, INF)) - seg.begin() - 1; if (pos < n && seg[pos].first <= x && x <= seg[pos].second) { st.insert(make_pair(x, pos)); f[x] = max(f[x], val); } else if (pos + 1 != n) { f[seg[pos + 1].first] = max(f[seg[pos + 1].first], val); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng_32(chrono::steady_clock::now().time_since_epoch().count()); const long long maxn = 3e5 + 10; struct E { long long to, nxt; } e[maxn * 2]; long long tot, head[maxn]; long long Add[maxn << 2], lz[maxn << 2]; void adde(long long u, long long v) { tot++; e[tot] = {v, head[u]}; head[u] = tot; } vector<pair<long long, long long> > v[maxn]; long long n; long long ans[maxn]; void dfs(int u, int fa, int dep) { int len = v[u].size(); for (int i = 0; i < len; i++) { int d = min(n + 1, dep + v[u][i].first + 1); Add[dep] += v[u][i].second; Add[d] -= v[u][i].second; } Add[dep] += Add[dep - 1]; ans[u] = Add[dep]; for (int i = head[u]; i; i = e[i].nxt) { int to = e[i].to; if (to == fa) continue; dfs(to, u, dep + 1); } for (int i = 0; i < len; i++) { int d = min(n + 1, dep + v[u][i].first + 1); Add[dep] -= v[u][i].second; Add[d] += v[u][i].second; } Add[dep] -= Add[dep - 1]; } int main() { cin >> n; long long t1, t2; for (long long i = 1; i < n; i++) { scanf( %lld%lld , &t1, &t2); adde(t1, t2); adde(t2, t1); } long long m, t3; cin >> m; for (long long i = 1; i <= m; i++) { scanf( %lld%lld%lld , &t1, &t2, &t3); v[t1].push_back(make_pair(t2, t3)); } dfs(1, 1, 1); for (int i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_TB_V
`define SKY130_FD_SC_HD__A41O_TB_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_TB_V
|
/*
-- ============================================================================
-- FILE NAME : uart.v
-- DESCRIPTION : Universal Asynchronous Receiver and Transmitter
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ???????
-- ============================================================================
*/
/********** ?????a???????? **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ???e??a???????? **********/
`include "uart.h"
/********** ????`?? **********/
module uart (
/********** ????a? & ???a? **********/
input wire clk, // ????a?
input wire reset, // ???????a?
/********** ?V?????????`?? **********/
input wire cs_, // ???a??????
input wire as_, // ??????????`??
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // ?????
input wire [`WordDataBus] wr_data, // ?????z???`??
output wire [`WordDataBus] rd_data, // ?i???????`??
output wire rdy_, // ????
/********** ????z?? **********/
output wire irq_rx, // ???????????z??
output wire irq_tx, // ???????????z??
/********** UART????????? **********/
input wire rx, // UART???????
output wire tx // UART???????
);
/********** ??????? **********/
// ????????
wire rx_busy; // ?????V??
wire rx_end; // ???????????
wire [`ByteDataBus] rx_data; // ?????`??
// ????????
wire tx_busy; // ?????V??
wire tx_end; // ???????????
wire tx_start; // ?????_????
wire [`ByteDataBus] tx_data; // ?????`??
/********** UART????????`?? **********/
uart_ctrl uart_ctrl (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** Host Interface **********/
.cs_ (cs_), // ???a??????
.as_ (as_), // ??????????`??
.rw (rw), // Read / Write
.addr (addr), // ?????
.wr_data (wr_data), // ?????z???`??
.rd_data (rd_data), // ?i???????`??
.rdy_ (rdy_), // ????
/********** Interrupt **********/
.irq_rx (irq_rx), // ???????????z??
.irq_tx (irq_tx), // ???????????z??
/********** ??????? **********/
// ????????
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
// ????????
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
.tx_start (tx_start), // ?????_????
.tx_data (tx_data) // ?????`??
);
/********** UART???????`?? **********/
uart_tx uart_tx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.tx_start (tx_start), // ?????_????
.tx_data (tx_data), // ?????`??
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
/********** Transmit Signal **********/
.tx (tx) // UART???????
);
/********** UART???????`?? **********/
uart_rx uart_rx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
/********** Receive Signal **********/
.rx (rx) // UART???????
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> G(n); for (int i = 0; i < n; i++) { cin >> G[i]; } vector<vector<pair<int, int>>> arr(27, vector<pair<int, int>>()); bool ret_flag = false; bool empty_flag = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (G[i][j] == . ) continue; empty_flag = false; auto temp = G[i][j] - a ; if (arr[temp].size() == 1 && !(arr[temp][0].first == i || arr[temp][0].second == j)) { ret_flag = true; break; } else if (arr[temp].size() > 1 && !((arr[temp][0].first == i && arr[temp][arr[temp].size() - 1].first == i) || (arr[temp][0].second == j && arr[temp][arr[temp].size() - 1].second == j))) { ret_flag = true; break; } arr[temp].push_back(make_pair(i, j)); } if (ret_flag) break; } if (empty_flag) { cout << YES << endl; cout << 0 << endl; continue; } if (ret_flag) { cout << NO << endl; continue; } int max_snake = 0; for (int i = 25; i >= 0; i--) { if (arr[i].size() == 0) continue; max_snake = max(max_snake, i); if (arr[i][0].first == arr[i][arr[i].size() - 1].first) { int r = arr[i][0].first; for (int j = arr[i][0].second; j <= arr[i][arr[i].size() - 1].second; j++) { if (G[r][j] - a >= i) continue; ret_flag = true; break; } if (ret_flag) break; } else if (arr[i][0].second == arr[i][arr[i].size() - 1].second) { int c = arr[i][0].second; for (int j = arr[i][0].first; j <= arr[i][arr[i].size() - 1].first; j++) { if (G[j][c] >= a + i) continue; ret_flag = true; break; } if (ret_flag) break; } if (ret_flag) break; } if (ret_flag) { cout << NO << endl; continue; } cout << YES << endl; cout << max_snake + 1 << endl; for (int i = 0; i <= 25; i++) { int j = i; if (arr[i].empty()) { while (i < 26 && arr[i].empty()) i++; } if (i == 26) break; cout << arr[i][0].first + 1 << << arr[i][0].second + 1 << << arr[i].back().first + 1 << << arr[i].back().second + 1 << endl; i = j; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const double pi = acos(-1); const double EPS = 1e-9; long long binpowmod(long long a, long long b) { a %= MOD; long long ret = 1; while (b) { if (b & 1) ret = ret * a % MOD; a = a * a % MOD; b >>= 1; } return ret % MOD; } long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } const int N = 1 << 18; const int E = N * 2; bool good(long long n) { long long t = n; int sumofdigits = 0; while (n) { sumofdigits += n % 10; n /= 10; } return (gcd(t, sumofdigits) > 1); } int n, m, ans; vector<vector<int> > a; bool good(int i, int j) { for (int k = 0; k < m; ++k) { if (a[i][k] != a[j][k]) return false; } return true; } void solveit(int l = 0, int r = n - 1, int c = 1) { int len = r - l + 1; if (len % 2) return; int i = l, j = r; while (i < j) { if (!good(i, j)) return; i++; j--; } ans = min(ans, n / (1 << c)); int mid = (l + r) / 2; solveit(l, mid, c + 1); solveit(mid + 1, r, c + 1); } void solve() { cin >> n >> m; ans = n; a.assign(n, vector<int>(m)); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> a[i][j]; solveit(); cout << ans << n ; } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 1; while (tc--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; inline void prnt(bool ok) { cout << (ok ? YES : NO ); } const int ppr = 257; const long long INF = 2e18; const int inf = 2e9; const int mod = 1e9 + 7; const int N = 3e6 + 123; const long double pi = 3.141592653589793238462643; const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, 1, 0, -1}; long long n, m, a[N], b[N], q, cur; vector<long long> g[N]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; while (m--) { long long x, y; cin >> x >> y; if (x < y) swap(x, y); g[y].push_back(x); a[x]++; b[y]++; } for (long long i = 1; i <= n; i++) cur += a[i] * b[i]; cin >> q; cout << cur << n ; while (q--) { long long x; cin >> x; cur -= a[x] * b[x]; a[x] += g[x].size(); b[x] = 0; for (auto to : g[x]) { cur -= a[to] * b[to]; b[to]++; a[to]--; cur += a[to] * b[to]; g[to].push_back(x); } g[x].clear(); cout << cur << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, Q; int cnt_bad = 0; bool bad[2][100100]; int main() { scanf( %d%d , &n, &Q); memset(bad, 0, sizeof(bad)); for (int i = 0; i < Q; i++) { int x, y; scanf( %d%d , &x, &y); x--, y--; if (bad[x][y]) { bad[x][y] = 0; if (y - 1 >= 0) cnt_bad -= bad[x ^ 1][y - 1]; cnt_bad -= bad[x ^ 1][y]; if (y + 1 < n) cnt_bad -= bad[x ^ 1][y + 1]; } else { bad[x][y] = 1; if (y - 1 >= 0) cnt_bad += bad[x ^ 1][y - 1]; cnt_bad += bad[x ^ 1][y]; if (y + 1 < n) cnt_bad += bad[x ^ 1][y + 1]; } if (cnt_bad == 0) printf( Yes n ); else printf( No n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
|
// DESCRIPTION::Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t;
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
typedef enum logic [1:0]
{ ZERO = 2'd0,
ONE = 2'd1,
TWO = 2'd2,
THREE = 2'd3,
XXX = 2'dx
} num_t;
function automatic logic is_odd;
input en;
input num_t number;
case (en)
1'b1: begin
unique if (number inside {ONE, THREE})
is_odd = 1'b1;
else if (number inside {ZERO, TWO})
is_odd = 1'b0;
else
is_odd = 1'bx;
end
1'b0: is_odd = 1'bx;
default: is_odd = 1'bx;
endcase
endfunction
initial begin
`checkh ((4'd4 inside {4'd1,4'd5}), 1'b0);
`checkh ((4'd4 inside {4'd1,4'd4}), 1'b1);
//
`checkh ((4'b1011 inside {4'b1001}), 1'b0);
`checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1??1}), 1'b1);
`ifndef VERILATOR
`checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx);
`endif
// Range
`checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches
`checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
//
// Unsupported $ bound
//
// Unsupported if unpacked array, elements tranversed
//int unpackedarray [$] = '{8,9};
//( expr inside {2, 3, unpackedarray}) // { 2,3,8,9}
//
`checkh (is_odd(1'b1, ZERO), 1'd0);
`checkh (is_odd(1'b1, ONE), 1'd1);
`checkh (is_odd(1'b1, TWO), 1'd0);
`checkh (is_odd(1'b1, THREE),1'd1);
`ifndef VERILATOR
`checkh (is_odd(1'b1, XXX), 1'dx);
`endif
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double vp, vd, t, f, c; int main() { cin >> vp >> vd >> t >> f >> c; if (vp >= vd) { cout << 0 ; return 0; } int numberOfBojous = 0; double timeToHaveTheDragonBack = 0, overtakePosition = 0; double princessPosition = vp * t; while (princessPosition < c) { overtakePosition = vd * princessPosition / (vd - vp); if (overtakePosition < c) numberOfBojous++; timeToHaveTheDragonBack = (overtakePosition / vd) + f; princessPosition = (vp * timeToHaveTheDragonBack) + overtakePosition; } cout << numberOfBojous; return 0; }
|
#include <bits/stdc++.h> using namespace std; void FastIO() { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); } int main() { FastIO(); int N; int A[200][200]; cin >> N; int Count = 0; int Cars[1000] = {0}; for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { cin >> A[i][j]; if (A[i][j] == 0) { if (Cars[i + 1] == 0) Cars[i + 1] = 100; if (Cars[j + 1] == 0) Cars[j + 1] = 100; } else if (A[i][j] == 1) { Cars[i + 1] = -100; } else if (A[i][j] == 2) Cars[j + 1] = -100; else if (A[i][j] == 3) { Cars[i + 1] = -100; Cars[j + 1] = -100; } } } for (int i = 1; i <= N; i++) { if (Cars[i] != -100) { Count++; } } cout << Count << endl; for (int i = 1; i <= N; i++) { if (Cars[i] != -100) cout << i << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 20; int n, x, i, f[N]; int main() { scanf( %d , &n); while (n--) scanf( %d , &x), f[x]++; for (i = N - 1; i >= 0; i--) if (f[i] & 1) return 0 * printf( Conan ); printf( Agasa ); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using vi = vector<int>; using ii = pair<int, int>; using vii = vector<pair<int, int>>; void solve() { int n; cin >> n; int r = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { int x; cin >> x; if (i == j) r += x; } } r %= 2; string res; int q; cin >> q; while (q--) { int t; cin >> t; if (t == 3) res += to_string(r); else if (t == 1 || t == 2) { int waste; cin >> waste; r ^= 1; } } cout << res << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int tc = 1; while (tc--) solve(); }
|
module multipumped_memory(clk, wr, addr, d, q);
parameter PORTS = 8;
parameter WIDTH = 64;
parameter DEPTH = 512;
parameter LOG2_DEPTH = log2(DEPTH - 1);
parameter LOG2_PORTS = log2(PORTS - 1);
input clk;
input [0:PORTS - 1] wr;
input [PORTS * LOG2_DEPTH - 1:0] addr;
input [PORTS * WIDTH - 1:0] d;
output reg [PORTS * WIDTH - 1:0] q;
reg [LOG2_PORTS - 2:0] counter;
initial counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
integer i, j;
reg [LOG2_DEPTH - 1:0] addr_2d [0:PORTS - 1];
reg [WIDTH - 1:0] d_2d [0:PORTS - 1];
always @* for(i = 0; i < PORTS; i = i + 1) begin
addr_2d[i] = addr[(i + 1) * LOG2_DEPTH - 1 -:LOG2_DEPTH];
d_2d[i] = d[(i + 1) * WIDTH - 1 -: WIDTH];
end
wire [WIDTH - 1:0] ram_q_a, ram_q_b;
dual_port_block_ram ram(clk, wr[{1'H0, counter}], addr_2d[{1'H0, counter}], d_2d[{1'H0, counter}], ram_q_a, wr[{1'H1, counter}], addr_2d[{1'H1, counter}], d_2d[{1'H1, counter}], ram_q_b);
always @(posedge clk) begin
for(i = 1; i < PORTS / 2; i = i + 1) begin
if((i + 1) % (PORTS / 2) == counter) begin
q[(i + 1) * WIDTH - 1 -: WIDTH] <= ram_q_a;
q[(i + PORTS / 2 + 1) * WIDTH - 1 -: WIDTH] <= ram_q_b;
end
end
end
`include "common.vh"
endmodule
|
`timescale 1ns / 1ps
module M_uxa_mgia(
input CLK_I_50MHZ,
input RST_I,
output CLK_O_25MHZ,
output HSYNC_O,
output VSYNC_O,
output [2:0] RED_O,
output [2:0] GRN_O,
output [2:1] BLU_O,
output [13:1] MGIA_ADR_O,
input [15:0] MGIA_DAT_I,
output MGIA_CYC_O,
output MGIA_STB_O,
input MGIA_ACK_I
);
wire pen;
wire clk25mhz;
wire vga_refresh;
wire vga_fetch;
wire odd_line;
wire [ 5:0] sh_adr;
wire [15:0] sh_dat;
wire [ 5:0] vfb_ctr;
wire [15:0] vfb_dat;
wire vfb_we;
assign unused = 12'h000; // drive unused outputs on Nexys2 board
assign RED_O = {3{pen}};
assign GRN_O = {3{pen}};
assign BLU_O = {2{pen}};
assign CLK_O_25MHZ = clk25mhz;
TIMEBASE tb(
.RST_I(RST_I),
.CLK_I_50MHZ(CLK_I_50MHZ),
.CLK_O_25MHZ(clk25mhz),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.VFEN_O(vga_fetch),
.VREN_O(vga_refresh),
.ODD_O(odd_line)
);
LINE_BUFFERS lb(
.CLK_I(clk25mhz),
.ODD_I(odd_line),
.F_ADR_I(sh_adr),
.F_DAT_O(sh_dat),
.S_ADR_I(vfb_ctr),
.S_DAT_I(vfb_dat),
.S_WE_I(vfb_we)
);
SHIFTER sh(
.CLK_I_25MHZ(clk25mhz),
.VREN_I(vga_refresh & !odd_line),
.F_ADR_O(sh_adr),
.F_DAT_I(sh_dat),
.PEN_O(pen)
);
VIDEO_FETCHER vf(
.RST_I(RST_I),
.CLK_I_25MHZ(clk25mhz),
.VSYNC_I(VSYNC_O),
.VFEN_I(vga_fetch & odd_line),
.RAM_ADR_O(MGIA_ADR_O),
.RAM_CYC_O(MGIA_CYC_O),
.RAM_STB_O(MGIA_STB_O),
.RAM_ACK_I(MGIA_ACK_I),
.RAM_DAT_I(MGIA_DAT_I),
.LB_ADR_O(vfb_ctr),
.LB_DAT_O(vfb_dat),
.LB_WE_O(vfb_we)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int const MAX_N = 600100; int const INT_INF = 1000000000; int my_rank[MAX_N], my_parent[MAX_N], diam_ancestor[MAX_N]; int d[MAX_N], och[MAX_N], nnew[MAX_N]; void make_set(int v) { my_parent[v] = v; diam_ancestor[v] = 0; my_rank[v] = 0; } int find_set(int v) { if (v != my_parent[v]) my_parent[v] = find_set(my_parent[v]); return my_parent[v]; } void my_Link(int x, int y, int flag) { if (my_rank[x] > my_rank[y]) my_parent[y] = x; else my_parent[x] = y; my_rank[y] += my_rank[x] == my_rank[y]; if (flag) { int D1 = diam_ancestor[x]; int D2 = diam_ancestor[y]; int new_VVV = find_set(x); int val = (D1 + 1) / 2 + (D2 + 1) / 2 + 1; diam_ancestor[new_VVV] = max(D1, max(D2, val)); } } void my_Union(int x, int y, int flag) { int V1 = find_set(x); int V2 = find_set(y); if (V1 == V2) return; my_Link(V1, V2, flag); } vector<int> e[MAX_N]; int main() { int n, m, q; scanf( %d%d%d , &n, &m, &q); for (int i = 0; i < n; i++) make_set(i); for (int i = 0; i < m; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; my_Union(a, b, 0); e[a].push_back(b); e[b].push_back(a); } for (int i = 0; i < n; i++) d[i] = INT_INF; for (int i = 0; i < n; i++) if (!nnew[i]) { int p_read = 0, p_write = 1; och[p_read] = i; nnew[i] = 1; d[i] = 0; while (p_read < p_write) { int v = och[p_read]; p_read++; for (int j = 0; j < (int)e[v].size(); j++) { int new_v = e[v][j]; if (d[new_v] > d[v] + 1) { d[new_v] = d[v] + 1; och[p_write] = new_v; p_write++; nnew[new_v] = 1; } } } int mx_dist = -1, ans_vertex = -1; for (int j = 0; j < p_write; j++) if (d[och[j]] > mx_dist) { mx_dist = d[och[j]]; ans_vertex = och[j]; } for (int j = 0; j < p_write; j++) d[och[j]] = INT_INF; p_read = 0, p_write = 1; och[p_read] = ans_vertex; d[ans_vertex] = 0; while (p_read < p_write) { int v = och[p_read]; p_read++; for (int j = 0; j < (int)e[v].size(); j++) { int new_v = e[v][j]; if (d[new_v] > d[v] + 1) { d[new_v] = d[v] + 1; och[p_write] = new_v; p_write++; } } } mx_dist = -1; for (int j = 0; j < p_write; j++) mx_dist = max(mx_dist, d[och[j]]); diam_ancestor[find_set(i)] = mx_dist; } for (int i = 0; i < q; i++) { int tp; scanf( %d , &tp); if (tp == 2) { int a, b; scanf( %d%d , &a, &b); a--; b--; my_Union(a, b, 1); } else if (tp == 1) { int v; scanf( %d , &v); v--; int VVV = find_set(v); printf( %d n , diam_ancestor[VVV]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int e[maxn], ne[maxn], h[maxn], idx = 0; int sz[maxn]; int ans = 0; void add(int a, int b) { e[idx] = b, ne[idx] = h[a]; h[a] = idx++; } void dfs(int now, int fa) { sz[now] = 1; for (int i = h[now]; i != -1; i = ne[i]) { int j = e[i]; if (j == fa) continue; dfs(j, now); sz[now]++; } } int dfs2(int now, int fa) { int d1 = 0, d2 = 0; for (int i = h[now]; i != -1; i = ne[i]) { int j = e[i]; if (j == fa) continue; int d = dfs2(j, now); if (d > d1) d2 = d1, d1 = d; else if (d > d2) d2 = d; } if (d1 >= 1 && d2 >= 1) { if (now != 1) ans = max(ans, d1 + d2 + sz[now] - 1); else ans = max(ans, d1 + d2 + sz[now] - 2); } else if (d2 == 0 && d1 >= 1) { if (now != 1) ans = max(ans, d1 + sz[now]); else ans = max(ans, d1 + sz[now] - 1); } return (d1 == 0 ? 1 : d1 + sz[now] - 1); } int main() { int t; scanf( %d , &t); memset(h, -1, sizeof h); while (t--) { int n; scanf( %d , &n); idx = 0; ans = 0; for (int i = 1; i <= n - 1; i++) { int a, b; scanf( %d%d , &a, &b); add(a, b); add(b, a); } dfs(1, -1); dfs2(1, -1); cout << ans << endl; for (int i = 1; i <= n; i++) h[i] = -1, sz[i] = 0; } return 0; }
|
`timescale 1ns/1ps
//THIS MODULE IS INSTANTIATED PER TX QUAD
module tx_reset_sm
(
input refclkdiv2,
input rst_n,
input tx_pll_lol_qd_s,
output reg tx_pcs_rst_ch_c, //TX Lane Reset (modified to have one bit)
output reg rst_qd_c // QUAD Reset
);
parameter count_index = 17;
// States of LSM
localparam QUAD_RESET = 0,
WAIT_FOR_TIMER1 = 1,
CHECK_PLOL = 2,
WAIT_FOR_TIMER2 = 3,
NORMAL = 4;
localparam STATEWIDTH =3;
// Flop variables
reg [STATEWIDTH-1:0] cs /*synthesis syn_encoding="safe, gray"*/; // current state of lsm
// Combinational logic variables
reg [STATEWIDTH-1:0] ns; // next state of lsm
reg tx_pll_lol_qd_s_int;
reg tx_pll_lol_qd_s_int1;
reg [3:0] tx_pcs_rst_ch_c_int; //TX Lane Reset
reg rst_qd_c_int; // QUAD Reset
//SEQUENTIAL
always @(posedge refclkdiv2 or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
cs <= QUAD_RESET;
tx_pll_lol_qd_s_int <= 1;
tx_pll_lol_qd_s_int1 <= 1;
tx_pcs_rst_ch_c <= 1'b1;
rst_qd_c <= 1;
end
else
begin
cs <= ns;
tx_pll_lol_qd_s_int1 <= tx_pll_lol_qd_s;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s_int1;
tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int[0];
rst_qd_c <= rst_qd_c_int;
end
end
//
reg reset_timer1, reset_timer2;
//TIMER1 = 20ns;
//Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
// A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
localparam TIMER1WIDTH=3;
reg [TIMER1WIDTH-1:0] counter1;
reg TIMER1;
always @(posedge refclkdiv2 or posedge reset_timer1)
begin
if (reset_timer1)
begin
counter1 <= 0;
TIMER1 <= 0;
end
else
begin
if (counter1[2] == 1)
TIMER1 <=1;
else
begin
TIMER1 <=0;
counter1 <= counter1 + 1 ;
end
end
end
//TIMER2 = 1,400,000 UI;
//WORST CASE CYCLES is with smallest multipier factor.
// This would be with X8 clock multiplier in DIV2 mode
// IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
// SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
// An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
//localparam TIMER2WIDTH=19;
//1,400,000 * 400 ps / 20 ns = 28000
// so a 16 bit counter is enough
localparam TIMER2WIDTH=18;
reg [TIMER2WIDTH-1:0] counter2;
reg TIMER2;
always @(posedge refclkdiv2 or posedge reset_timer2)
begin
if (reset_timer2)
begin
counter2 <= 0;
TIMER2 <= 0;
end
else
begin
// `ifdef SIM //IF SIM parameter is set, define lower value
// //TO SAVE SIMULATION TIME
// if (counter2[4] == 1)
// `else
// if (counter2[18] == 1)
// `endif
if (counter2[count_index] == 1)
TIMER2 <=1;
else
begin
TIMER2 <=0;
counter2 <= counter2 + 1 ;
end
end
end
always @(*)
begin : NEXT_STATE
reset_timer1 = 0;
reset_timer2 = 0;
case (cs)
QUAD_RESET: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
reset_timer1 = 1;
ns = WAIT_FOR_TIMER1;
end
WAIT_FOR_TIMER1: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
if (TIMER1)
ns = CHECK_PLOL;
else
ns = WAIT_FOR_TIMER1;
end
CHECK_PLOL: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
reset_timer2 = 1;
ns = WAIT_FOR_TIMER2;
end
WAIT_FOR_TIMER2: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
if (TIMER2)
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
else
ns = WAIT_FOR_TIMER2;
end
NORMAL: begin
tx_pcs_rst_ch_c_int = 4'h0;
rst_qd_c_int = 0;
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
end
// prevent lockup in undefined state
default: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
ns = QUAD_RESET;
end
endcase // case
end //NEXT_STATE
endmodule
|
#include <bits/stdc++.h> using namespace std; int memo[2700][2700]; string S; int N; int doit(int lo, int hi) { if (lo == hi) { return 1; } if (lo > hi) { return 0; } int &ret = memo[lo][hi]; if (ret != -1) return ret; ret = 0; if (S[lo] == S[hi]) { ret = max(ret, doit(lo + 1, hi - 1) + 2); } ret = max(ret, doit(lo + 1, hi)); ret = max(ret, doit(lo, hi - 1)); return ret; } string prefixStr, suffixStr, middleStr; void doitG(int lo, int hi) { if (lo == hi) { middleStr += S[lo]; return; } if (lo > hi) return; if (S[lo] == S[hi]) { prefixStr += S[lo]; suffixStr += S[lo]; doitG(lo + 1, hi - 1); } else { if (doit(lo + 1, hi) > doit(lo, hi - 1)) { doitG(lo + 1, hi); } else { doitG(lo, hi - 1); } } } int main() { cin >> S; N = S.size(); if (N > 2600) { for (char c = a ; c <= z ; c++) { int cnt = 0; for (int i = 0; i < S.size(); i++) { if (S[i] == c) { cnt++; } } if (cnt >= 100) { for (int i = 0; i < 100; i++) cout << c; cout << endl; return 0; } } assert(0); } else { memset(memo, -1, sizeof(memo)); int ret = doit(0, N - 1); prefixStr = suffixStr = middleStr = ; doitG(0, N - 1); reverse(suffixStr.begin(), suffixStr.end()); string res = ; for (int i = 0; i < prefixStr.size(); i++) res += prefixStr[i]; for (int i = 0; i < middleStr.size(); i++) res += middleStr[i]; for (int i = 0; i < suffixStr.size(); i++) res += suffixStr[i]; if (res.size() < 100) { int n = res.size(); cout << res << endl; } else { if (res.size() == 100) { cout << res << endl; } else { int n = res.size(); for (int i = 0; i < 50; i++) cout << res[i]; for (int j = n - 50; j < n; j++) cout << res[j]; cout << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; if (k % (n - 1) == 0) { cout << (k / (n - 1) * n) - 1 << endl; } else { cout << k / (n - 1) * n + k % (n - 1) << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int LG = 20; int n, a[N], u, v; long long dp[LG][N][2]; long long sdp[LG][N][2]; long long ans, ans2; vector<int> G[N]; bool mark[N]; int h[N]; void input(); void find_ans(); void dfs(int, int); int main() { input(); for (int i = 0; i < LG; i++) { dfs(0, i); fill(mark, mark + n, false); } find_ans(); cout << ans + (ans2 / 2) << endl; } void input() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { cin >> u >> v; u--, v--; G[u].push_back(v); G[v].push_back(u); } } void dfs(int x, int z) { mark[x] = true; for (int i = 0; i < G[x].size(); i++) { int y = G[x][i]; if (!mark[y]) { h[y] = h[x] + 1; dfs(y, z); dp[z][x][0] += dp[z][y][(a[x] >> z) & 1]; dp[z][x][1] += dp[z][y][1 - ((a[x] >> z) & 1)]; sdp[z][x][0] += dp[z][y][0]; sdp[z][x][1] += dp[z][y][1]; } } dp[z][x][(a[x] >> z) & 1]++; } void find_ans() { for (int i = 0; i < LG; i++) for (int j = 0; j < n; j++) ans += (dp[i][j][1] * (1 << i)); for (int i = 0; i < LG; i++) for (int j = 0; j < n; j++) for (int k = 0; k < G[j].size(); k++) { int x = G[j][k]; if (h[x] > h[j]) { ans2 += (dp[i][x][1]) * (sdp[i][j][(a[j] >> i) & 1] - dp[i][x][(a[j] >> i) & 1]) * (1 << i); ans2 += (dp[i][x][0]) * (sdp[i][j][1 - ((a[j] >> i) & 1)] - dp[i][x][1 - ((a[j] >> i) & 1)]) * (1 << i); } } }
|
// $Id: c_rotator.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// rotate bit vector by given amount
module c_rotator
(amount, data_in, data_out);
`include "c_functions.v"
`include "c_constants.v"
// width of input data
parameter width = 8;
// direction in which to rotate
parameter rotate_dir = `ROTATE_DIR_LEFT;
// width of rotation amount
localparam amount_width = clogb(width);
// input data
input [0:width-1] data_in;
// result
input [0:amount_width-1] amount;
// amount by which to rotate
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:(2*width-1)-1] data_dup;
wire [0:(2*width-1)-1] data_rot;
generate
case (rotate_dir)
`ROTATE_DIR_LEFT:
begin
assign data_dup = {data_in, data_in[0:(width-1)-1]};
assign data_rot = data_dup << amount;
assign data_out = data_rot[0:width-1];
end
`ROTATE_DIR_RIGHT:
begin
assign data_dup = {data_in[1:width-1], data_in};
assign data_rot = data_dup >> amount;
assign data_out = data_rot[width-1:(2*width-1)-1];
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; string s1 = ; if (n % 2 == 0) { for (int i = 0; i < n; i++) { cout << s[i] << s[i + 1]; i++; if (i < n - 2) { cout << - ; } } } else { if (n == 3) cout << s << endl; else { for (int i = 0; i < n; i++) { if (i == 0) { cout << s[i] << s[i + 1] << s[i + 2] << - ; i += 2; continue; } else { cout << s[i] << s[i + 1]; } if (i < n - 2) { cout << - ; } i++; } } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846264338327950288419716939937510582097494459230; struct debugger { static void call(const char *arg) {} template <typename T, typename... aT> static void call(const char *it, T a, aT... rest) { string b; for (; *it && (*it) != , ; it++) { b += *it; } cerr << b << = << a << ; call(++it, rest...); } }; int main() { int n, b, m; cin >> n >> b; int ar[n]; m = b; for (int i = 0; i < (n); i++) { cin >> ar[i]; } for (int i = 0; i < (n); i++) { int c = b / ar[i], r = b % ar[i]; for (int j = (i + 1); j < (n); j++) { int w = ar[j] * c; w = w + r; m = max(w, m); } } cout << m; }
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_soc_interface;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg output_axis_tready = 1'b0;
reg port0_cmd_empty = 1'b0;
reg port0_cmd_full = 1'b0;
reg port0_wr_empty = 1'b0;
reg port0_wr_full = 1'b0;
reg port0_wr_underrun = 1'b0;
reg [6:0] port0_wr_count = 7'b0;
reg port0_wr_error = 1'b0;
reg [31:0] port0_rd_data = 32'b0;
reg port0_rd_empty = 1'b0;
reg port0_rd_full = 1'b0;
reg port0_rd_overflow = 1'b0;
reg [6:0] port0_rd_count = 7'b0;
reg port0_rd_error = 1'b0;
reg port1_cmd_empty = 1'b0;
reg port1_cmd_full = 1'b0;
reg port1_wr_empty = 1'b0;
reg port1_wr_full = 1'b0;
reg port1_wr_underrun = 1'b0;
reg [6:0] port1_wr_count = 7'b0;
reg port1_wr_error = 1'b0;
reg [31:0] port1_rd_data = 32'b0;
reg port1_rd_empty = 1'b0;
reg port1_rd_full = 1'b0;
reg port1_rd_overflow = 1'b0;
reg [6:0] port1_rd_count = 7'b0;
reg port1_rd_error = 1'b0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire port0_cmd_clk;
wire port0_cmd_en;
wire [2:0] port0_cmd_instr;
wire [5:0] port0_cmd_bl;
wire [31:0] port0_cmd_byte_addr;
wire port0_wr_clk;
wire port0_wr_en;
wire [3:0] port0_wr_mask;
wire [31:0] port0_wr_data;
wire port0_rd_clk;
wire port0_rd_en;
wire port1_cmd_clk;
wire port1_cmd_en;
wire [2:0] port1_cmd_instr;
wire [5:0] port1_cmd_bl;
wire [31:0] port1_cmd_byte_addr;
wire port1_wr_clk;
wire port1_wr_en;
wire [3:0] port1_wr_mask;
wire [31:0] port1_wr_data;
wire port1_rd_clk;
wire port1_rd_en;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
output_axis_tready,
port0_cmd_empty,
port0_cmd_full,
port0_wr_empty,
port0_wr_full,
port0_wr_underrun,
port0_wr_count,
port0_wr_error,
port0_rd_data,
port0_rd_empty,
port0_rd_full,
port0_rd_overflow,
port0_rd_count,
port0_rd_error,
port1_cmd_empty,
port1_cmd_full,
port1_wr_empty,
port1_wr_full,
port1_wr_underrun,
port1_wr_count,
port1_wr_error,
port1_rd_data,
port1_rd_empty,
port1_rd_full,
port1_rd_overflow,
port1_rd_count,
port1_rd_error);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
port0_cmd_clk,
port0_cmd_en,
port0_cmd_instr,
port0_cmd_bl,
port0_cmd_byte_addr,
port0_wr_clk,
port0_wr_en,
port0_wr_mask,
port0_wr_data,
port0_rd_clk,
port0_rd_en,
port1_cmd_clk,
port1_cmd_en,
port1_cmd_instr,
port1_cmd_bl,
port1_cmd_byte_addr,
port1_wr_clk,
port1_wr_en,
port1_wr_mask,
port1_wr_data,
port1_rd_clk,
port1_rd_en,
busy);
// dump file
$dumpfile("test_soc_interface.lxt");
$dumpvars(0, test_soc_interface);
end
soc_interface
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// mcb interface port 0
.port0_cmd_clk(port0_cmd_clk),
.port0_cmd_en(port0_cmd_en),
.port0_cmd_instr(port0_cmd_instr),
.port0_cmd_bl(port0_cmd_bl),
.port0_cmd_byte_addr(port0_cmd_byte_addr),
.port0_cmd_empty(port0_cmd_empty),
.port0_cmd_full(port0_cmd_full),
.port0_wr_clk(port0_wr_clk),
.port0_wr_en(port0_wr_en),
.port0_wr_mask(port0_wr_mask),
.port0_wr_data(port0_wr_data),
.port0_wr_empty(port0_wr_empty),
.port0_wr_full(port0_wr_full),
.port0_wr_underrun(port0_wr_underrun),
.port0_wr_count(port0_wr_count),
.port0_wr_error(port0_wr_error),
.port0_rd_clk(port0_rd_clk),
.port0_rd_en(port0_rd_en),
.port0_rd_data(port0_rd_data),
.port0_rd_empty(port0_rd_empty),
.port0_rd_full(port0_rd_full),
.port0_rd_overflow(port0_rd_overflow),
.port0_rd_count(port0_rd_count),
.port0_rd_error(port0_rd_error),
// mcb interface port 1
.port1_cmd_clk(port1_cmd_clk),
.port1_cmd_en(port1_cmd_en),
.port1_cmd_instr(port1_cmd_instr),
.port1_cmd_bl(port1_cmd_bl),
.port1_cmd_byte_addr(port1_cmd_byte_addr),
.port1_cmd_empty(port1_cmd_empty),
.port1_cmd_full(port1_cmd_full),
.port1_wr_clk(port1_wr_clk),
.port1_wr_en(port1_wr_en),
.port1_wr_mask(port1_wr_mask),
.port1_wr_data(port1_wr_data),
.port1_wr_empty(port1_wr_empty),
.port1_wr_full(port1_wr_full),
.port1_wr_underrun(port1_wr_underrun),
.port1_wr_count(port1_wr_count),
.port1_wr_error(port1_wr_error),
.port1_rd_clk(port1_rd_clk),
.port1_rd_en(port1_rd_en),
.port1_rd_data(port1_rd_data),
.port1_rd_empty(port1_rd_empty),
.port1_rd_full(port1_rd_full),
.port1_rd_overflow(port1_rd_overflow),
.port1_rd_count(port1_rd_count),
.port1_rd_error(port1_rd_error),
// status
.busy(busy)
);
endmodule
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#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long a[1000005], b[1000005]; long long nine[100], t[100]; int main() { int n, k; t[0] = 1LL; for (int i = (1); i <= (10); i++) t[i] = (t[i - 1] * 10LL) % mod; nine[1] = 9LL; for (int i = (2); i <= (10); i++) nine[i] = (nine[i - 1] * 10 + 9) % mod; long long ans = 1; scanf( %d , &(n)); scanf( %d , &(k)); for (int i = (1); i <= (n / k); i++) scanf( %lld , &(a[i])); for (int i = (1); i <= (n / k); i++) scanf( %lld , &(b[i])); t[0] = 0; nine[0] = 9; for (int i = (1); i <= (n / k); i++) { long long f = ((t[k] - 1) / a[i]) + 1; f %= mod; long long ss = b[i]; long long temp = 0; long long st = ss * t[k - 1]; long long e = st + nine[k - 1]; if (k == 1) st = b[i]; if (k == 1) e = st; temp = ((e / a[i]) - ((st - 1) / a[i])); if (st == 0) temp = e / a[i] + 1; f -= temp; if (f < mod) f += mod; ans = (ans * f) % mod; } cout << ans % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using vi = vector<int>; using vll = vector<ll, ll>; using pii = pair<int, int>; using pll = pair<ll, ll>; ll modpow(ll a, ll b, ll mod = (ll)(1e9 + 7)) { if (!b) return 1; a %= mod; return modpow(a * a % mod, b / 2, mod) * (b & 1 ? a : 1) % mod; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int DEBUG = 1; const int mxk = 13, mxm = 4, dsz = (1 << mxm) * mxk, mod = 1e9 + 7; int n, m, k; void add(ll &a, ll b) { a += b; if (a >= mod) a -= mod; } struct Matrix { ll a[dsz][dsz]; Matrix() { for (int i = 0; i < dsz; i++) for (int j = 0; j < dsz; j++) a[i][j] = 0; } } id; void init() { for (int i = 0; i < dsz; i++) id.a[i][i] = 1; } Matrix operator*(Matrix a, Matrix b) { Matrix ret; for (int i = 0; i < dsz; i++) for (int j = 0; j < dsz; j++) for (int kk = 0; kk < dsz; kk++) add(ret.a[i][kk], a.a[i][j] * b.a[j][kk] % mod); return ret; } int cnv(int mask, int kk) { return (kk << mxm) + mask; } int rot(int mask) { return (mask << 1) % (1 << m); } Matrix modpow(Matrix a, ll b) { Matrix ans = id; while (b) { if (b & 1) ans = ans * a; a = a * a; b /= 2; } return ans; } void solve() { init(); Matrix op; for (int mask = 0; mask < 1 << m; mask++) for (int kk = 0; kk <= k; kk++) { add(op.a[cnv(rot(mask), kk)][cnv(mask, kk)], 1); if (kk < k) add(op.a[cnv(rot(mask) + 1, kk + 1)][cnv(mask, kk)], 1 + __builtin_popcount(mask)); } Matrix b; b.a[0][0] = 1; Matrix res = modpow(op, n) * b; ll ans = 0; for (int mask = 0; mask < 1 << m; mask++) add(ans, res.a[cnv(mask, k)][0]); cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); while (cin >> n >> k >> m) solve(); return 0; }
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