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// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: tryagain.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module tryagain (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/tryagain.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/tryagain.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tryagain_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct node { long long l, r; long long mx = -1e18; long long ch = 0; }; vector<node> tree; void push(long long v) { if (tree[v].l == tree[v].r) { tree[v].ch = 0; } else { tree[v * 2].ch += tree[v].ch; tree[v * 2 + 1].ch += tree[v].ch; tree[v * 2].mx += tree[v].ch; tree[v * 2 + 1].mx += tree[v].ch; tree[v].ch = 0; tree[v].mx = max(tree[v * 2].mx, tree[v * 2 + 1].mx); } } vector<long long> atc(1e6 + 2, 1e17); vector<long long> def(1e6 + 2, 1e17); void build(long long v, long long l, long long r) { tree[v].l = l, tree[v].r = r; if (l == r) { tree[v].mx = def[l]; return; } long long mid = (r + l) / 2; build(v * 2, l, mid); build(v * 2 + 1, mid + 1, r); tree[v].mx = max(tree[v * 2].mx, tree[v * 2 + 1].mx); } long long get_max(long long v, long long l, long long r) { push(v); if (tree[v].l > r || tree[v].r < l) return -1e17; if (tree[v].l >= l && tree[v].r <= r) { return tree[v].mx; } return max(get_max(v * 2, l, r), get_max(v * 2 + 1, l, r)); } void upd(long long v, long long l, long long r, long long val) { push(v); if (tree[v].l > r || tree[v].r < l) return; if (tree[v].l >= l && tree[v].r <= r) { tree[v].ch += val; tree[v].mx += val; push(v); return; } upd(v * 2, l, r, val); upd(v * 2 + 1, l, r, val); tree[v].mx = max(tree[v * 2].mx, tree[v * 2 + 1].mx); } signed main() { ios_base::sync_with_stdio(false); long long mna = 1e9, mnb = 1e9; long long n, m, k; cin >> n >> m >> k; tree.resize(1e6 * 4); for (long long i = 0; i < n; ++i) { long long a, b; cin >> a >> b; mna = min(mna, b); atc[a - 1] = min(atc[a - 1], b); } for (long long i = 1e6; i >= 0; --i) atc[i] = min(atc[i + 1], atc[i]); for (long long i = 0; i < m; ++i) { long long a, b; cin >> a >> b; mnb = min(mnb, b); def[a - 1] = min(def[a - 1], b); } for (long long i = 1e6; i >= 0; --i) def[i] = min(def[i + 1], def[i]); for (long long i = 0; i < 1e6 + 2; ++i) def[i] *= -1; vector<pair<long long, pair<long long, long long> > > mnst; for (long long i = 0; i < k; ++i) { long long d, a, cen; cin >> d >> a >> cen; mnst.push_back({d, {a, cen}}); } build(1, 0, 1e6 + 1); sort(mnst.begin(), mnst.end()); long long j = 0; long long ans = -(mnb + mna); for (long long i = 0; i < 1e6 + 1; ++i) { while (j < k && mnst[j].first <= i) { long long att = mnst[j].second.first, cen = mnst[j].second.second; upd(1, att, 1e6 + 1, cen); ++j; } long long sum = get_max(1, 1ll, 1e6 + 1) - atc[i]; ans = max(sum, ans); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5; const int MAXR = 1; const int MAXC = 1; const int INF = (int)1e9; priority_queue<int, vector<int>, greater<int>> q1; priority_queue<int, vector<int>, less<int>> q2; int arr[MAXN]; vector<pair<int, int>> v(MAXN); vector<vector<int>> adjl(MAXN); queue<int> q; set<pair<int, int>> s; int n; int x4[] = {-1, 0, 1, 0}; int y4[] = {0, 1, 0, -1}; void createGraph() { while (!q.empty()) { int vn = q.front(); q.pop(); pair<int, int> p = v[vn]; int deg = p.first; int xs = p.second; if (deg == 0) continue; if (adjl[vn].size() == deg) continue; int cxs = 0; for (int j = 0; j < adjl[vn].size(); ++j) { cxs ^= adjl[vn][j]; } int ns = xs ^ cxs; ; adjl[vn].push_back(ns); ; adjl[ns].push_back(vn); if (v[ns].first - adjl[ns].size() == 1) { q.push(ns); } }; } void createEdgeSet() { for (int i = 0; i < adjl.size(); ++i) { for (int j = 0; j < adjl[i].size(); ++j) { int src = i; int dest = adjl[i][j]; pair<int, int> p1 = make_pair(src, dest); pair<int, int> p2 = make_pair(dest, src); if (s.find(p1) == s.end() && s.find(p2) == s.end()) { s.insert(p1); } } }; } int main(void) { ios::sync_with_stdio(false); cin >> n; v.resize(n); adjl.resize(n); int d, sv; for (int i = 0; i < n; ++i) { cin >> d >> sv; v[i] = make_pair(d, sv); if (d == 1) { q.push(i); } }; createGraph(); createEdgeSet(); cout << s.size() << endl; for (set<pair<int, int>>::iterator it = s.begin(); it != s.end(); it++) { pair<int, int> p = *it; cout << p.first << << p.second << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( sse4,avx ) const double pi = 3.14159265358979323; struct dpoint { double x, y; dpoint() : x(0), y(0) {} dpoint(double x, double y) : x(x), y(y) {} }; void run(std::istream& in, std::ostream& out) { int n; dpoint p; in >> n >> p.x >> p.y; std::vector<dpoint> points(n); for (int i = 0; i < n; i++) { in >> points[i].x >> points[i].y; } double maxR = 0; double minR = 1e10; for (int i = 0; i < n; i++) { double dist1 = hypot(points[i].x - p.x, points[i].y - p.y); maxR = std::max(maxR, dist1); minR = std::min(minR, dist1); dpoint& p1 = points[i]; dpoint& p2 = points[(i + 1) % n]; if ((p2.x - p1.x) * (p.x - p1.x) + (p2.y - p1.y) * (p.y - p1.y) > 0.5 && (p1.x - p2.x) * (p.x - p2.x) + (p1.y - p2.y) * (p.y - p2.y) > 0.5) { double a = p1.y - p2.y; double b = p2.x - p1.x; double dist = a * p.x + b * p.y - a * p1.x - b * p1.y; dist /= hypot(a, b); minR = std::min(minR, std::abs(dist)); } } out.precision(20); out << std::fixed; out << (maxR * maxR - minR * minR) * pi << std::endl; } int main() { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); run(std::cin, std::cout); return 0; }
|
// -*- Mode: Verilog -*-
// Filename : fifo.v
// Description : FIFO
// Author : Philip Tracton
// Created On : Tue May 27 16:03:26 2014
// Last Modified By: Philip Tracton
// Last Modified On: Tue May 27 16:03:26 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module fifo (/*AUTOARG*/
// Outputs
DATA_OUT, FULL, EMPTY,
// Inputs
CLK, RESET, ENABLE, FLUSH, DATA_IN, PUSH, POP
) ;
//---------------------------------------------------------------------------
//
// PARAMETERS
//
//---------------------------------------------------------------------------
parameter DATA_WIDTH = 32; // Width of input and output data
parameter ADDR_EXP = 3; // Width of our address, FIFO depth is 2^^ADDR_EXP
parameter ADDR_DEPTH = 2 ** ADDR_EXP; // DO NOT DIRECTLY SET THIS ONE!
//---------------------------------------------------------------------------
//
// PORTS
//
//---------------------------------------------------------------------------
input CLK; // Clock for all logic
input RESET; // Synchronous Active High Reset
input ENABLE; // When asserted (1'b1), this block is active
input FLUSH; // When asserted (1'b1), the FIFO is dumped out and reset to all 0
input [DATA_WIDTH - 1:0] DATA_IN; // Input data stored when PUSHed
input PUSH; // When asserted (1'b1), DATA_IN is stored into FIFO
input POP; // When asserted (1'b1), DATA_OUT is the next value in the FIFO
output [DATA_WIDTH - 1:0] DATA_OUT; // Output data from FIFO
output FULL; // Asseted when there is no more space in FIFO
output EMPTY; // Asserted when there is nothing in the FIFO
//---------------------------------------------------------------------------
//
// Registers
//
//---------------------------------------------------------------------------
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg EMPTY;
reg FULL;
// End of automatics
reg [DATA_WIDTH -1:0] memory[0:ADDR_DEPTH-1]; // The memory for the FIFO
reg [ADDR_EXP:0] write_ptr; // Location to write to
reg [ADDR_EXP:0] read_ptr; // Location to read from
//---------------------------------------------------------------------------
//
// WIRES
//
//---------------------------------------------------------------------------
/*AUTOWIRE*/
wire [DATA_WIDTH-1:0] DATA_OUT; // Top of the FIFO driven out of the module
wire [ADDR_EXP:0] next_write_ptr; // Next location to write to
wire [ADDR_EXP:0] next_read_ptr; // Next location to read from
wire accept_write; // Asserted when we can accept this write (PUSH)
wire accept_read; // Asserted when we can accept this read (POP)
//---------------------------------------------------------------------------
//
// COMBINATIONAL LOGIC
//
//---------------------------------------------------------------------------
//
// Read and write pointers increment by one unless at the last address. In that
// case wrap around to the beginning (0)
//
assign next_write_ptr = (write_ptr == ADDR_DEPTH-1) ? 0 :write_ptr + 1;
assign next_read_ptr = (read_ptr == ADDR_DEPTH-1) ? 0 :read_ptr + 1;
//
// Only write if enabled, no flushing and not full or at the same time as a pop
//
assign accept_write = (PUSH && ENABLE && !FLUSH && !FULL) || (PUSH && POP && ENABLE);
//
// Only read if not flushing and not empty or at the same time as a push
//
assign accept_read = (POP && ENABLE && !FLUSH && !EMPTY) || (PUSH && POP && ENABLE);
//
// We are always driving the data out to be read. Pop will move to the next location
// in memory
//
assign DATA_OUT = (ENABLE) ? memory[read_ptr]: 'b0;
//---------------------------------------------------------------------------
//
// SEQUENTIAL LOGIC
//
//---------------------------------------------------------------------------
//
// Write Pointer Logic
//
always @(posedge CLK)
if (RESET) begin
write_ptr <= 'b0;
end else if (ENABLE) begin
if (FLUSH) begin
write_ptr <= 'b0;
end else begin
if (accept_write) begin
write_ptr <= next_write_ptr;
end
end
end else begin
write_ptr <= 'b0;
end
//
// Read Pointer Logic
//
always @(posedge CLK)
if (RESET) begin
read_ptr <= 'b0;
end else if (ENABLE) begin
if (FLUSH) begin
read_ptr <= 'b0;
end else begin
if (accept_read) begin
read_ptr <= next_read_ptr;
end
end
end else begin
read_ptr <= 'b0;
end
//
// Empty Logic
//
always @(posedge CLK)
if (RESET) begin
EMPTY <= 1'b1;
end else if (ENABLE) begin
if (FLUSH) begin
EMPTY <= 1'b1;
end else begin
if (EMPTY && accept_write) begin
EMPTY <= 1'b0;
end
if (accept_read && (next_read_ptr == write_ptr)) begin
EMPTY <= 1'b1;
end
end
end else begin
EMPTY <= 1'b1;
end
//
// Full Logic
//
always @(posedge CLK)
if (RESET) begin
FULL <= 1'b0;
end else if (ENABLE) begin
if (FLUSH) begin
FULL <= 1'b0;
end else begin
if (accept_write && (next_write_ptr == read_ptr)) begin
FULL <= 1;
end else if (FULL && accept_read) begin
FULL <= 0;
end
end
end else begin
FULL <= 1'b0;
end // else: !if(ENABLE)
//
// FIFO Write Logic
//
integer i;
always @(posedge CLK)
if (RESET) begin
for (i=0; i< (ADDR_DEPTH); i=i+1) begin
memory[i] <= 'b0;
end
end else if (ENABLE) begin
if (FLUSH) begin
for (i=0; i< (ADDR_DEPTH); i=i+1) begin
memory[i] <= 'b0;
end
end
else if (accept_write) begin
memory[write_ptr] <= DATA_IN;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; while (cin >> n >> m) { int tmp = 0, mid = (m + 1) / 2, res = mid; while (n--) { if (tmp % 2 == m % 2) res -= tmp; else res += tmp; if (tmp == m) tmp = 0, res = mid; cout << res << endl; tmp++; } } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops ) const int N = 1e5 + 5; const long long int mod = 1e9 + 7; const long long int Mod = 998244353; const long double Pi = acos(-1); const long long int Inf = 4e18; using namespace std; int n, m; vector<pair<int, int> > e; bool Check(int k) { vector<bool> rem(n + 1, false); vector<int> in[n + 1], out[n + 1], rank(n + 1, -1); for (int i = 0; i <= k; i++) { in[e[i].second].push_back(e[i].first); out[e[i].first].push_back(e[i].second); } int cnt_in = 0, cnt_out = 0, one = -1, last = -1; for (int i = 1; i <= n; i++) { if ((int)in[i].size() == 0) { cnt_in++; one = i; } if ((int)out[i].size() == 0) { cnt_out++; last = i; } } if (cnt_in * cnt_out != 1) return false; rank[1] = one; rank[n] = last; int cur = one; for (int i = 2; i <= n; i++) { int fone = 0, nxt = -1; for (auto u : out[cur]) { int cnt = 0; for (auto t : in[u]) { if (rem[t] == false) cnt++; } if (cnt == 1) { fone++; nxt = u; } } if (fone != 1) return false; else { rem[cur] = true; cur = nxt; rank[i] = cur; } } for (int i = 1; i <= n; i++) { if (rank[i] == -1) return false; } return true; } void TestCase() { cin >> n >> m; for (int i = 1, u, v; i <= m; i++) { cin >> u >> v; e.push_back({u, v}); } int lb = 0, ub = m - 1, ans = m; while (lb <= ub) { int mid = (lb + ub) / 2; if (Check(mid)) { ans = min(ans, mid); ub = mid - 1; } else lb = mid + 1; } ans == m ? cout << -1 : cout << ans + 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int T = 1; while (T--) { TestCase(); } return 0; }
|
module main;
reg [7:0] th2, init;
reg carry, clk, rst, foo;
(* ivl_synthesis_on *)
always @(posedge clk) begin
if (rst) begin
th2 <= 0;
carry <= 1;
foo <= 0; // This causes foo to be an output to the block.
end else begin
if (carry)
{carry, th2} <= {1'b0, init};
else
{carry, th2} <= {1'b0, th2} + 9'h1;
end
end
(* ivl_synthesis_off *)
initial begin
rst = 1;
clk = 0;
init = 8'hfe;
$monitor("clk=%b: rst=%b, th2=%h, carry=%b", clk, rst, th2, carry);
#1 clk = 1;
#1 clk = 0;
if (foo !== 0) begin
$display("FAILED -- foo=%b", foo);
$finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (th2 !== 8'hff) begin
$display("FAILED -- th2=%h (1)", th2);
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (th2 !== 8'h00) begin
$display("FAILED == th2=%h", th2);
$finish;
end
if (carry !== 1) begin
$display("FAILED -- carry=%b, th2=%h", carry, th2);
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (th2 !== 8'hfe) begin
$display("FAILED -- th2=%h", th2);
$finish;
end
#1 $strobe("PASSED");
end // initial begin
endmodule // main
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_4_2 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(29),
.DIN_TO(6)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx.v
// Version : 1.3
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_3_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_7x_v1_3_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e18; vector<long long> factorial; void fill_factorial(long long n) { factorial.resize(n + 1); factorial[0] = 1; for (long long i = 1; i <= n; i++) factorial[i] = (factorial[i - 1] * i) % mod; } long long gcd(long long a, long long b, long long& x, long long& y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long d = gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } long long binpow(long long a, long long b) { a %= mod; long long res = 1; while (b > 0) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } long long inv(long long a) { long long x, y; long long g = gcd(a, mod, x, y); x = (x % mod + mod) % mod; return x; } long long CC(long long n, long long k) { return factorial[n] * inv(factorial[k]) % mod * inv(factorial[n - k]) % mod; } void solve() { long long n; cin >> n; long long a[n + 1]; for (long long i = 1; i <= n; ++i) cin >> a[i]; long long h = 0; queue<pair<long long, long long>> q; q.push(make_pair(1, 0)); long long j = 2; long long ans = 0; while (true) { long long val = q.front().first, t = q.front().second; ans = max(ans, t); q.pop(); q.push(make_pair(a[j], t + 1)); j++; while (j <= n && a[j] > a[j - 1]) { if (j > n) break; q.push(make_pair(a[j], t + 1)); j++; } if (j > n) break; } while (!q.empty()) { ans = max(ans, q.front().second); q.pop(); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long no_of_test_cases; cin >> no_of_test_cases; while (no_of_test_cases--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long double n, h; cin >> n >> h; cout << setprecision(20); for (long double i = 0; i < n - 1; i++) { cout << h * sqrt((i + 1) / n) << ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int gcd(int x, int y) { return !y ? x : gcd(y, x % y); } int rev(int num) { int dig[10], tot = 0, s = 0; for (; num; num /= 10) dig[tot++] = num % 10; for (int i = 0; i < tot; i++) s = s * 10 + dig[i]; return s; } pair<int, int> p[maxn], r[maxn]; void init() { for (int i = 1; i <= 100000; i++) { int re = rev(i); int g = gcd(re, i); p[i] = make_pair(i / g, re / g); r[i] = make_pair(re / g, i / g); } } int main() { init(); map<pair<int, int>, int> mx, my; int nx, ny, w; cin >> nx >> ny >> w; for (int i = 1; i <= ny; i++) ++my[p[i]]; int x = -1, y = -1; for (int i = 1, j = ny, k = 0; i <= nx; i++) { ++mx[p[i]]; k += my[r[i]]; while (j > 0 && k >= w) { if (x == -1 || (long long)x * y > (long long)i * j) { x = i; y = j; } my[p[j]]--; k -= mx[r[j]]; j--; if (k < w) { j++; my[p[j]]++; k += mx[r[j]]; break; } } } if (x == -1) { puts( -1 ); } else { printf( %d %d n , x, y); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long a, b; cin >> a >> b; while (a != 0 && b != 0) { if (a >= 2 * b) { a = a % (2 * b); } else if (b >= 2 * a) { b = b % (a * 2); } else break; } cout << a << << b << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int par[20][100001], dep[100001], lg[100001], sizes[100001]; bool isParent[100001]; vector<int> adj[100001]; void dfs(int u) { for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != par[0][u]) { isParent[u] = true; dep[v] = dep[u] + 1; par[0][v] = u; dfs(v); } } } int subtree(int u) { if (sizes[u] == -1) { sizes[u] = 1; if (isParent[u]) { for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != par[0][u]) sizes[u] += subtree(v); } } } return sizes[u]; } void buildLCA(int root, int n) { memset(par, -1, sizeof par); memset(sizes, -1, sizeof sizes); memset(isParent, false, sizeof isParent); dep[root] = 0; dfs(root); for (int i = 2; i < n; i++) lg[i] = lg[i >> 1] + 1; for (int i = 1; (1 << i) < n; i++) for (int u = 0; u < n; u++) if ((1 << i) <= dep[u]) par[i][u] = par[i - 1][par[i - 1][u]]; subtree(root); } int climb(int u, int k) { if (dep[u] < k) return -1; for (; k > 0; k -= (1 << lg[k])) u = par[lg[k]][u]; return u; } int lca(int a, int b) { if (dep[a] < dep[b]) b = climb(b, dep[b] - dep[a]); else a = climb(a, dep[a] - dep[b]); for (int k = lg[dep[a]]; k >= 0 && a != b; k--) if (par[k][a] != par[k][b]) { a = par[k][a]; b = par[k][b]; } if (a != b && dep[a] > 0) { a = par[0][a]; b = par[0][b]; } return a == b ? a : -1; } int dist(int u, int v) { int L = lca(u, v); return L == -1 ? -1 : dep[u] + dep[v] - 2 * dep[L]; } int main() { int n, m; cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } buildLCA(1, n + 1); cin >> m; while (m--) { int a, b; cin >> a >> b; if (a != b) { int l = lca(a, b), distance = dist(a, b); if (distance % 2 == 0) { if (dep[a] != dep[b]) { int deepernode; if (dep[a] > dep[b]) deepernode = a; else deepernode = b; int mid1 = climb(deepernode, distance / 2), mid2 = climb(deepernode, distance / 2 - 1); cout << sizes[mid1] - sizes[mid2] << endl; } else { int aa = climb(a, dist(a, l) - 1), bb = climb(b, dist(a, l) - 1); cout << n - sizes[aa] - sizes[bb] << endl; } } else cout << 0 << endl; } else cout << n << endl; } }
|
#include <bits/stdc++.h> const double pi = acos(-1); const int o = 524288; int a[1111111]; double x[1111111], y[1111111]; int z[1111111]; int main() { double tx, ty; int i, j, k, n, m, tz; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) a[i + o] = x[i + o] = 1; for (i = o - 1; i >= 0; i--) x[i] = x[i << 1] + x[i << 1 | 1]; while (m--) { scanf( %d%d%d , &i, &j, &k); j += o - 1; if (i == 1) a[j] += k; else z[j] = (z[j] + k) % 360; x[j] = a[j] * cos(z[j] * pi / 180); y[j] = a[j] * sin(-z[j] * pi / 180); while (j >>= 1) { x[j] = x[j << 1] + x[j << 1 | 1] * cos(-z[j << 1] * pi / 180) - y[j << 1 | 1] * sin(-z[j << 1] * pi / 180); y[j] = y[j << 1] + x[j << 1 | 1] * sin(-z[j << 1] * pi / 180) + y[j << 1 | 1] * cos(-z[j << 1] * pi / 180); z[j] = (z[j << 1] + z[j << 1 | 1]) % 360; } printf( %.10f %.10f n , x[1], y[1]); } }
|
// $Id: c_wf_alloc_loop.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// wavefron allocator variant which uses wraparound (forming a false
// combinational loop) as described in Dally et al, "Principles and Practices of
// Interconnection Networks"
module c_wf_alloc_loop
(clk, reset, update, req, gnt);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// try to recover from errors
parameter error_recovery = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
// reset value for priority pointer
localparam [0:num_ports-1] prio_init = {1'b1, {(num_ports-1){1'b0}}};
input clk;
input reset;
// update arbitration priorities
input update;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// Need to make sure priority is one-hot, otherwise conflicting grants can be
// generated!
wire [0:num_ports-1] prio_s, prio_q;
wire prio_bad;
assign prio_bad = ~^prio_q;
wire [0:num_ports-1] prio_fixed;
assign prio_fixed = (error_recovery && prio_bad) ? prio_init : prio_q;
assign prio_s = update ?
{prio_fixed[num_ports-1], prio_fixed[0:num_ports-2]} :
prio_fixed;
c_dff
#(.width(num_ports),
.reset_type(reset_type),
.reset_value(prio_init))
prioq
(.clk(clk),
.reset(reset),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*num_ports-1] x_pri;
wire [0:num_ports*num_ports-1] y_pri;
generate
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
wire req_in;
assign req_in = req[row*num_ports+col];
wire x_pri_in;
assign x_pri_in
= x_pri[row*num_ports + ((col+num_ports-1)%num_ports)] |
prio_q[(row+col)%num_ports];
wire y_pri_in;
assign y_pri_in
= y_pri[((row+num_ports-1)%num_ports)*num_ports + col] |
prio_q[(row+col)%num_ports];
wire gnt_out;
assign gnt_out = req_in & x_pri_in & y_pri_in;
assign gnt[row*num_ports+col] = gnt_out;
wire x_pri_out;
assign x_pri_out = x_pri_in & ~gnt_out;
assign x_pri[row*num_ports+col] = x_pri_out;
wire y_pri_out;
assign y_pri_out = y_pri_in & ~gnt_out;
assign y_pri[row*num_ports+col] = y_pri_out;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int m[367], f[367]; int main() { memset(m, 0, sizeof(m)); memset(f, 0, sizeof(f)); int N; cin >> N; char ch; int a, b; for (int i = 0; i < N; ++i) { cin >> ch >> a >> b; if (ch == M ) for (int j = a; j <= b; ++j) ++m[j]; else for (int j = a; j <= b; ++j) ++f[j]; } int res = 0; for (int i = 1; i <= 366; ++i) res = max(res, min(m[i], f[i]) * 2); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; const int N = 30 + 7; const int mod = 1e9 + 7; const int B = 317; int n; int u, r; int a[N][N]; int b[N]; int c[N]; int p[N]; long long foo(int x, bool f) { long long s = -1e18; if (x % 2 == 0) { s = 0; for (int i = 1; i <= n; i++) s += a[x][i] * 1LL * c[i]; } if (x == 0) return s; if (f) { for (int i = 1; i <= n; i++) { a[x - 1][i] = a[x][i] ^ b[i]; } s = max(s, foo(x - 1, false)); } for (int i = 1; i <= n; i++) { a[x - 1][i] = a[x][p[i]] + r; } s = max(s, foo(x - 1, true)); return s; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> u >> r; for (int i = 1; i <= n; i++) cin >> a[u][i]; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n; i++) cin >> p[i]; cout << foo(u, true); }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: ffoo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ffoo (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone IV E",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ffoo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// 3rd party code: from Swapforth [1]
//
// Copyright (c) 2015 James Bowman
//
// [1] https://github.com/jamesbowman/swapforth
//
/*
Copyright (c) 2015, James Bowman
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of swapforth nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`define CLKFREQ 35250000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
module inpin(
input clk,
input pin,
output rd);
SB_IO #(.PIN_TYPE(6'b0000_00)) _io (
.PACKAGE_PIN(pin),
.INPUT_CLK(clk),
.D_IN_0(rd));
endmodule
module outpin(
input clk,
output pin,
input we,
input wd,
output rd);
SB_IO #(.PIN_TYPE(6'b0101_01)) _io (
.PACKAGE_PIN(pin),
.CLOCK_ENABLE(we),
.OUTPUT_CLK(clk),
.D_OUT_0(wd),
.D_IN_0(rd));
endmodule
|
#pragma GCC optimize( O2 ) #include<bits/stdc++.h> #define ll long long //#define int long long #define fi first #define se second #define mpa make_pair #define eb emplace_back #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() using namespace std; mt19937 gen(time(0)); signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; vector<int> a(n); vector<int> c(n + 1); int k = 800; int K = (n + k - 1) / k * 2; for (int i = 0; i < n; ++i) { cin >> a[i]; ++c[a[i]]; } vector<int> d; for (int i = 0; i <= n; ++i) if (c[i] >= K) d.eb(i); vector<vector<int>> psum(d.size(), vector<int>(n + 1, 0)); for (int i = 0; i < (int)(d.size()); ++i) { for (int j = 1; j <= n; ++j) { psum[i][j] = psum[i][j - 1] + (a[j - 1] == d[i]); } } vector<int> temp(n + 1); for (int z = 0; z < q; ++z) { int l, r; cin >> l >> r; int mx = 0; if (r - l + 1 < k) { for (int j = l - 1; j < r; ++j) { ++temp[a[j]]; mx = max(mx, temp[a[j]]); } for (int j = l - 1; j < r; ++j) --temp[a[j]]; } else { for (int j = 0; j < (int)(d.size()); ++j) { int cnt = psum[j][r] - psum[j][l - 1]; mx = max(mx, cnt); } } int len = (r - l + 1); int L = 0, R = mx; while (L != R) { int M = (L + R) / 2; if ((len - M + 1) / 2 >= mx - M) { R = M; } else { L = M + 1; } } cout << R + 1 << n ; } } /* */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_2_V
`define SKY130_FD_SC_HS__SDFRBP_2_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrbp_2 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrbp_2 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_2_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Fri Apr 1 16:03:12 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always # (mintypmax_dly) reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
reg err ;
initial
begin
err = 0;
# 1;
if(value1 !== 4'bxxxx)
begin
$display("FAILED - 3.1.4E - initial value not xxxx;\n");
err = 1;
end
#15 ;
if(value1 != 4'h5)
begin
$display("FAILED - 3.1.4E - always # mintypmax_dly reg_lvalue = constant\n");
err = 1;
end
if (err == 0)
$display("PASSED\n");
$finish;
end
always # (3:10:15) value1 = 4'h5;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int x[1000000]; int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> x[i]; sort(x, x + n); int sol = x[n - 1] - x[0]; int p = n / 2 - 1; for (int i = 0; i <= p; i++) sol = min(sol, x[n - 1 - (p - i)] - x[i]); cout << sol << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = 1, y = 1; int k = 0; cin >> k; bool fl = false; for (int i = 1; i <= n; i++) { int t; if (i != n) cin >> t; else t = 1 - k; if (t == k && fl == false) { x++; } else if (t != k) { if (y != x && fl == true) { cout << NO ; return 0; } fl = true; y = 1; k = t; } else if (t == k) { y++; } } cout << YES ; }
|
#include <bits/stdc++.h> using namespace std; bool visited[300000]; long long int parent[300000]; void initialise() { for (long long int i = 0; i < 300000; i++) { visited[i] = false; parent[i] = i; } } pair<long long int, long long int> dfs( vector<pair<long long int, long long int>> adj[], long long int A[], long long int v, long long int i) { visited[i] = true; pair<long long int, long long int> r, s; long long int j, k = adj[i].size(); long long int d = 0, f = 0; r.first = A[i]; for (j = 0; j < k; j++) { if (!visited[adj[i][j].first]) { s = dfs(adj, A, v, adj[i][j].first); r.first = max(r.first, s.first); r.first = max(r.first, d + s.second + adj[i][j].second + A[i]); d = max(d, s.second + adj[i][j].second); } } r.second = d + A[i]; return r; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int u, v, x, y, a, b, i, k, l, p, n, m, w, maxi = 0, ans; pair<long long int, long long int> j; cin >> v; vector<pair<long long int, long long int>> adj[v]; long long int A[v]; initialise(); for (i = 0; i < v; i++) { cin >> A[i]; } for (i = 0; i < v - 1; i++) { cin >> x >> y >> w; x--; y--; adj[x].push_back(make_pair(y, -w)); adj[y].push_back(make_pair(x, -w)); } j = dfs(adj, A, v, 0); cout << j.first; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_fifo
*/
module test_axis_srl_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
count
);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
$dumpvars(0, test_axis_srl_fifo);
end
axis_srl_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.count(count)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> const T& max(const T& a, const T& b, const T& c) { return max(a, max(b, c)); } template <class T> const T& min(const T& a, const T& b, const T& c) { return min(a, min(b, c)); } long long stoi(string& str) { istringstream second(str); long long i; second >> i; return i; } string itos(long long i) { stringstream second; second << i; return second.str(); } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long poww(long long a, long long b) { if (b == 0) return 1; long long tmp = poww(a, b / 2); return (b & 1 ? a * tmp * tmp : tmp * tmp); } long long sumOfDigs(string s) { long long sum = 0; for (int i = 0; i < s.length(); i++) sum += s[i] - 0 ; return sum; } long long sumOfDigs(long long n) { return (n < 10 ? n : n % 10 + sumOfDigs(n / 10)); } long long mod = poww(10, 9) + 7; int months[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; using namespace std; void t() { freopen( test.txt , r , stdin); } long long a[1000 * 100 + 1][20]; pair<long long, long long> aa[1000 * 100 + 1][20]; int main() { string t1, t2, s, tt, second; cin >> t1 >> t2; s += t1; reverse(t2.begin(), t2.end()); s += t2; cin >> t1 >> t2; tt += t1; reverse(t2.begin(), t2.end()); tt += t2; second = s; if (second == tt) { return cout << YES << endl, 0; } int pos = second.find( X ); if (pos < 3) { swap(second[pos], second[pos + 1]); pos++; } else { swap(second[pos], second[0]); pos = 0; } if (second == tt) { return cout << YES << endl, 0; } while (second != s) { if (pos < 3) { swap(second[pos], second[pos + 1]); pos++; } else { swap(second[pos], second[0]); pos = 0; } if (second == tt) { return cout << YES << endl, 0; } } return cout << NO << endl, 0; return 0; }
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module exec (
// IO Ports
`ifdef DEBUG
output [15:0] x,
output [15:0] y,
output [15:0] aluo,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
output [15:0] c,
output [ 3:0] addr_c,
output [15:0] omemalu,
output [ 3:0] addr_d,
output [ 8:0] flags,
`endif
input [`IR_SIZE-1:0] ir,
input [15:0] off,
input [15:0] imm,
output [15:0] cs,
output [15:0] ip,
output of,
output zf,
output cx_zero,
input clk,
input rst,
input [15:0] memout,
output [15:0] wr_data,
output [19:0] addr,
output we,
output m_io,
output byteop,
input block,
output div_exc,
input wrip0,
output ifl
);
// Net declarations
`ifndef DEBUG
wire [15:0] c;
wire [15:0] omemalu;
wire [ 3:0] addr_c;
wire [ 3:0] addr_d;
wire [8:0] flags;
`endif
wire [15:0] a, b, s, alu_iflags, bus_b;
wire [31:0] aluout;
wire [3:0] addr_a, addr_b;
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, memalu, r_byte, c_byte;
wire wr, wr_reg;
wire wr_cnd;
wire jmp;
wire b_imm;
wire [8:0] iflags, oflags;
wire [4:0] logic_flags;
wire alu_word;
wire a_byte;
wire b_byte;
wire wr_high;
wire dive;
// Module instances
alu alu0( {c, a }, bus_b, aluout, t, func, alu_iflags, oflags,
alu_word, s, off, clk, dive);
regfile reg0 (
`ifdef DEBUG
ax, dx, bp, si, es,
`endif
a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
~byteop, a_byte, b_byte, c_byte, cx_zero, wrip0);
jmp_cond jc0( logic_flags, addr_b, addr_c[0], c, jmp);
// Assignments
assign addr_s = ir[1:0];
assign addr_a = ir[5:2];
assign addr_b = ir[9:6];
assign addr_c = ir[13:10];
assign addr_d = ir[17:14];
assign wrfl = ir[18];
assign we = ir[19];
assign wr = ir[20];
assign wr_cnd = ir[21];
assign high = ir[22];
assign t = ir[25:23];
assign func = ir[28:26];
assign byteop = ir[29];
assign memalu = ir[30];
assign m_io = ir[32];
assign b_imm = ir[33];
assign r_byte = ir[34];
assign c_byte = ir[35];
assign omemalu = memalu ? aluout[15:0] : memout;
assign bus_b = b_imm ? imm : b;
assign addr = aluout[19:0];
assign wr_data = c;
assign wr_reg = (wr | (jmp & wr_cnd)) && !block && !div_exc;
assign wr_high = high && !block && !div_exc;
assign of = flags[8];
assign ifl = flags[6];
assign zf = flags[3];
assign iflags = oflags;
assign alu_iflags = { 4'b0, flags[8:3], 1'b0, flags[2], 1'b0, flags[1],
1'b1, flags[0] };
assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };
assign alu_word = (t==3'b011) ? ~r_byte : ~byteop;
assign a_byte = (t==3'b011 && func[1]) ? 1'b0 : r_byte;
assign b_byte = r_byte;
assign div_exc = dive && wr;
`ifdef DEBUG
assign x = a;
assign y = bus_b;
assign aluo = aluout;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 23; const int offset = (int)1e6; int st_sum[2 * N]; int st_ma[2 * N]; int getMax(int a, int b) { a += N + offset; b += N + offset; int ma = -1e9; int sum_a = 0; int ma_b = 0; for (; a < b; a /= 2, b /= 2) { if (a % 2 == 1) { ma = max(ma, st_ma[a] + sum_a); sum_a += st_sum[a]; ++a; } if (b % 2 == 0) { ma_b = max(ma_b + st_sum[b], st_ma[b]); --b; } } if (a == b) { ma = max(ma, st_ma[a] + sum_a); sum_a += st_sum[a]; } ma = max(ma, sum_a + ma_b); return ma; } void updateSegtreePos(int pos) { st_sum[pos] = st_sum[pos * 2] + st_sum[pos * 2 + 1]; st_ma[pos] = max(st_ma[pos * 2], st_sum[pos * 2] + st_ma[pos * 2 + 1]); } void addValue(int pos, int val) { pos += N + offset; st_sum[pos] += val; st_ma[pos] += val; for (pos /= 2; pos; pos /= 2) { updateSegtreePos(pos); } } set<int> pawns[(int)2e5 + 10]; multiset<int> intercept_ys; int main() { int n, k, m; cin >> n >> k >> m; for (int i = 0; i < N; ++i) { st_sum[i + N] = -1; st_ma[i + N] = -1; } for (int i = N - 1; i; --i) { updateSegtreePos(i); } for (int i = 0; i < m; ++i) { int x, y; cin >> x >> y; int intercept_y = (n - y) - abs(x - k); if (pawns[x].count(y)) { addValue(intercept_y, -1); pawns[x].erase(y); intercept_ys.erase(intercept_ys.find(intercept_y)); } else { addValue(intercept_y, 1); pawns[x].insert(y); intercept_ys.insert(intercept_y); } if (intercept_ys.size()) { cout << max(0, getMax(*intercept_ys.begin(), n) - *intercept_ys.begin()) << endl; } else { cout << 0 << endl; } } }
|
module ex_div(
input wire clock,
input wire reset,
input wire is_signed,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire is_start,
input wire is_annul,
output reg is_ended,
output reg[`DOUBLE_REGS_DATA_BUS] result
);
wire[`EXT_REGS_DATA_BUS] div_temp;
reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;
reg[`REGS_DATA_BUS] divisor;
reg[5 : 0] cycle;
reg[1 : 0] state;
assign div_temp = {1'b0, dividend[63 : 32]} - {1'b0, divisor};
always @ (posedge clock) begin
if (reset == `ENABLE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZEROWORD, `ZEROWORD} should be used
end else begin
case (state)
`DIV_FREE: begin
if (is_start == `TRUE && is_annul == `FALSE) begin
if (operand2 == 0) begin // FIXME: ZERO_WORD should be used
state <= `DIV_BY_ZERO;
end else begin
state <= `DIV_ON;
cycle <= 6'b000000;
dividend = 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
if (is_signed == `TRUE && operand1[31] == 1'b1) begin
dividend[32 : 1] <= ~operand1 + 1; // FIXME: may be = should be used here
end else begin
dividend[32 : 1] <= operand1; // FIXME: may be = should be used here
end
if (is_signed == `TRUE && operand2[31] == 1'b1) begin
divisor <= ~operand2 + 1;
end else begin
divisor <= operand2;
end
end
end else begin
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZEROWORD, `ZEROWORD} should be used
end
end
`DIV_BY_ZERO: begin
dividend <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
state <= `DIV_END;
end
`DIV_ON: begin
if (is_annul == `FALSE) begin
if (cycle != 6'b100000) begin
if (div_temp[32] == 1'b1) begin
dividend <= {dividend[63 : 0], 1'b0};
end else begin
dividend <= {div_temp[31 : 0], dividend[31 : 0], 1'b1};
end
cycle <= cycle + 1;
end else begin
if (is_signed && (operand1[31] ^ operand2[31])) begin
dividend[31 : 0] <= ~dividend[31 : 0] + 1;
end
if (is_signed && (operand1[31] ^ dividend[64])) begin
dividend[64 : 33] <= ~dividend[64 : 33] + 1;
end
state <= `DIV_END;
cycle <= 6'b000000;
end
end else begin
state <= `DIV_FREE;
end
end
`DIV_END: begin
result <= {dividend[64 : 33], dividend[31 : 0]};
is_ended <= `TRUE;
if (is_start <= `FALSE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
end
end
endcase
end
end
endmodule // ex_div
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); const int INF = 1 << 29; const int MAXN = 505; int n; int M[MAXN][MAXN]; int R[MAXN]; long long A[MAXN]; int main(int argc, char** argv) { scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { scanf( %d , &M[i][j]); } } for (int i = 0; i < n; i++) { scanf( %d , &R[n - i - 1]); R[n - i - 1]--; } for (int k = 0; k < n; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { M[R[i]][R[j]] = min(M[R[i]][R[j]], M[R[i]][R[k]] + M[R[k]][R[j]]); } } for (int i = 0; i <= k; i++) { for (int j = 0; j <= k; j++) { A[n - k - 1] += M[R[i]][R[j]]; } } } for (int i = 0; i < n; i++) { printf( %I64d , A[i]); } printf( n ); return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module packet_tb();
wire [7:0] data;
wire sof, eof, src_rdy, dst_rdy;
wire clear = 0;
reg clk = 0;
reg reset = 1;
always #10 clk <= ~clk;
initial #1000 reset <= 0;
initial $dumpfile("packet_tb.vcd");
initial $dumpvars(0,packet_tb);
wire [31:0] total, crc_err, seq_err, len_err;
packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
.data_o(data), .sof_o(sof), .eof_o(eof),
.src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
.data_i(data), .sof_i(sof), .eof_i(eof),
.src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
.total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
endmodule // packet_tb
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 998244353; const long long int mxn = 1e5 + 7; long long int a[mxn]; long long int power(long long int a, long long int b); long long int flcm(long long int n, long long int m); long long int fgcd(long long int n, long long int m); long long int modinv(long long int x); long long int max_val(long long int start, long long int end) { long long int pres_max, global_max; for (long long int i = start; i <= end; i++) { if (i == start) { pres_max = a[i]; global_max = a[i]; } else { pres_max = max(pres_max + a[i], a[i]); global_max = max(global_max, pres_max); } } return global_max; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m, k, u, v, t = 1, temp, ans = 0, flag = 1, c = 0, min_el, max_el, sum_el; string s, s1, s2; cin >> t; while (t--) { ans = 0; c = 0; flag = 1; sum_el = 0; cin >> n; memset(a, 0, sizeof(a)); for (long long int i = 0; i < n; i++) cin >> a[i]; max_el = max(max_val(0, n - 2), max_val(1, n - 1)); if (max_el < max_val(0, n - 1)) cout << YES << endl; else cout << NO << endl; } return 0; } long long int power(long long int a, long long int b) { long long int res = 1; while (b) { if (b % 2) { res = (res * a) % mod; } a = (a * a) % mod; b /= 2; } return res; } long long int flcm(long long int n, long long int m) { long long int temp = fgcd(n, m); return (n * m) / temp; } long long int fgcd(long long int n, long long int m) { long long int temp; while (m != 0) { temp = n; n = m; m = temp % m; } return n; } long long int modinv(long long int x) { return power(x, mod - 2); }
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____25.000______0.000______50.0______312.659____245.713
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_0_0;
wire clk_in2_system_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_0_0;
wire clk_out2_system_clk_wiz_0_0;
wire clk_out3_system_clk_wiz_0_0;
wire clk_out4_system_clk_wiz_0_0;
wire clk_out5_system_clk_wiz_0_0;
wire clk_out6_system_clk_wiz_0_0;
wire clk_out7_system_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (36.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
.a(inA_@[]),
.b(outA_@[]),
);*/
autoinst_paramover_sub u_foo(/*AUTOINST*/
// Inouts
.a (inA_foo[bitsa:0]), // Templated
.b (outA_foo[bitsb:0])); // Templated
autoinst_paramover_sub u_bar(/*AUTOINST*/
// Inouts
.a (inA_bar[bitsa:0]), // Templated
.b (outA_bar[bitsb:0])); // Templated
autoinst_paramover_sub u_baz(/*AUTOINST*/
// Inouts
.a (inA_baz[bitsa:0]), // Templated
.b (outA_baz[bitsb:0])); // Templated
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(inN_@[]),
.b(outN_@[]),
);*/
autoinst_paramover_sub u_0_2(/*AUTOINST*/
// Inouts
.a (inN_0[bitsa:0]), // Templated
.b (outN_0[bitsb:0])); // Templated
autoinst_paramover_sub u_1_3(/*AUTOINST*/
// Inouts
.a (inN_1[bitsa:0]), // Templated
.b (outN_1[bitsb:0])); // Templated
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, ntot, ieven, rs[6], ord[6 + 1], iord[6 + 1]; vector<int> xs; inline int imake(int i) { return i > 0 ? ord[i] : -ord[-i]; } void iextend_even(int p, vector<int> &vi) { vector<int> vr[2], vg; vr[1] = vi; for (int i = (int)vi.size() - 1; i >= 0; i--) vr[0].push_back(-vi[i]); vr[0][0] = imake(p + 1); vr[1][0] = imake(p + 1); vg = vi; for (int k = 1, l = 0; k < xs[p]; k++, l ^= 1) { vg[vg.size() - k] = imake(-(p + 1)); vg.insert(vg.end() - k, vr[l].begin(), vr[l].end()); } vi = vg; } void iextend_odd(int p, vector<int> &vi) { vector<int> vr[2], vg; vr[1] = vi; for (int i = (int)vi.size() - 1; i >= 0; i--) vr[0].push_back(-vi[i]); int vrz = vr[0][0]; vg = vi; for (int k = 1, m = rs[p] - 1; k < xs[p]; k += 2, m -= 2) { if (m > 0) { vr[0][0] = imake(-(p + 1)); vg[vg.size() - k] = imake(p + 1); vg.insert(vg.end() - k, vr[0].begin(), vr[0].end()); vg.insert(vg.end() - k, imake(p + 1)); vg.insert(vg.end() - k - 1, vr[1].begin(), vr[1].end()); vg.insert(vg.end() - k - 1 - vr[1].size(), imake(-(p + 1))); } else { vr[0][0] = vrz; vg.push_back(imake(p + 1)); vg.insert(vg.end(), vr[0].begin(), vr[0].end()); vg.push_back(imake(p + 1)); vg.insert(vg.end(), vr[1].begin(), vr[1].end()); } } vi = vg; } vector<int> iinit_even() { int p = xs[1]; vector<int> vg, vi; for (int i = 0; i < p - 1; i++) vi.push_back(imake(2)); vi.push_back(imake(1)); for (int i = 0; i < p - 1; i++) vi.push_back(imake(-2)); vi.push_back(imake(-1)); vg = vi; vi[0] = imake(1); for (int i = 1, k = 2; i < xs[0] / 2; i++, k += 2) { vg[vg.size() - k] = imake(-1); vg.insert(vg.end() - k, vi.begin(), vi.end()); } return vg; } vector<int> iinit_odd() { int p = (rs[0] - 1) % 2, q = (rs[1] - 1) % 2, pp = xs[0], qq = xs[1], k, kl, kr, ku, kd; vector<int> vg, vil, virx, viry, viu, vid; if (!(p == 1 && q == 1) && (p == 1 || q == 1)) return vg; for (int i : {-1, -1, 2, 2, 1, -2}) vil.push_back(imake(i)); for (int i : {1, 2, 1, -2, -2, -1}) virx.push_back(imake(i)); for (int i : {1, 1, -2, -2, -1, 2}) viry.push_back(imake(i)); viu.resize(pp * 2); vid.resize(pp * 2); viu[0] = imake(2), viu[1] = imake(2), viu[pp + 1] = imake(-2); vid[0] = imake(-2), vid[1] = imake(-2), vid[pp + 1] = imake(2); for (int i = 2; i < pp + 1; i++) viu[i] = imake(1), vid[i] = imake(-1); for (int i = pp + 2; i < pp * 2; i++) viu[i] = imake(-1), vid[i] = imake(1); if (p == 1 && q == 1) { for (int i : {1, -2, -1, -1, 2, 2, 1, 1}) vg.push_back(imake(i)); p++, q++, kl = 4, kr = 1, ku = 6, kd = 2; } else if (rs[0] == 1 && rs[1] == 1) { for (int i : {2, 2, 1, 1, -2, -2, -1, 2}) vg.push_back(imake(i)); p = q = 2, kl = 0, kr = 4, ku = 2, kd = 6; } else if (rs[0] == 1 && rs[1] != 1) { for (int i : {1, 1, -2, -2, -1, -1, 2, 1}) vg.push_back(imake(i)); p = q = 2, kl = 6, kr = 2, ku = 0, kd = 4; } else if (rs[0] != 1 && rs[1] != 1) { for (int i : {-2, -2, -1, -1, 2, 2, 1, -2}) vg.push_back(imake(i)); p = q = 2, kl = 4, kr = 0, ku = 6, kd = 2; } else if (rs[0] != 1 && rs[1] == 1) { for (int i : {-1, -1, 2, 2, 1, 1, -2, -1}) vg.push_back(imake(i)); p = q = 2, kl = 2, kr = 6, ku = 4, kd = 0; } if (p < rs[0] - 1 && ku == 0) ku = 8; if (rs[0] - 1 < pp - 1 && kd == 0) kd = 8; for (k = p; k < rs[0] - 1; k += 2, kl += 2) { vg[kl] = imake(1); vg.insert(vg.begin() + kl, vil.begin(), vil.end()); ku += 2; kr > kl && (kr += 6); kd > kl && (kd += 6); } if (kr == 1) { for (; k < pp - 1; k += 2, kr += 4) { vg[kr] = imake(-1); vg.insert(vg.begin() + kr, virx.begin(), virx.end()); ku > kr && (ku += 6); kd += 4; } } else { for (; k < pp - 1; k += 2, kr += 2) { vg[kr] = imake(-1); vg.insert(vg.begin() + kr, viry.begin(), viry.end()); ku > kr && (ku += 6); kd += 2; } } for (k = q; k < rs[1] - 1; k += 2, kd += 2) { vg[kd] = imake(2); vg.insert(vg.begin() + kd, vid.begin(), vid.end()); ku > kd && (ku += vid.size()); } for (; k < qq - 1; k += 2, ku += 2) { vg[ku] = imake(-2); vg.insert(vg.begin() + ku, viu.begin(), viu.end()); } return vg; } inline void iapply(int *px, int op) { op < 0 ? px[iord[-op] - 1]-- : px[iord[op] - 1]++; } bool iequal(int *px, int *py) { for (int i = 0; i < n; i++) if (px[i] != py[i]) return false; return true; } void icycle(vector<int> &vi) { int px[n], k; for (int i = 1; i <= n; i++) iord[ord[i]] = i; for (int i = 0; i < n; i++) px[i] = 1; for (k = 0; k < (int)vi.size(); k++) { if (iequal(px, rs)) break; iapply(px, vi[k]); } if (k != 0) { vi.insert(vi.end(), vi.begin(), vi.begin() + k); vi.erase(vi.begin(), vi.begin() + k); } } void iprint(vector<int> &vi) { for (auto i : vi) i > 0 ? (cout << inc << i << endl) : (cout << dec << -i << endl); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; ntot = 1; xs.resize(n); for (int i = 0; i < n; i++) cin >> xs[i], ntot *= xs[i]; for (int i = 0; i < n; i++) cin >> rs[i]; if (n == 1) { if (xs[0] == 2 && rs[0] == 1) { cout << Cycle << endl; cout << inc 1 << endl; cout << dec 1 << endl; } else if (xs[0] == 2 && rs[0] == 2) { cout << Cycle << endl; cout << dec 1 << endl; cout << inc 1 << endl; } else if (rs[0] == 1) { cout << Path << endl; for (int i = 1; i < xs[0]; i++) cout << inc 1 << endl; } else if (rs[0] == xs[0]) { cout << Path << endl; for (int i = 1; i < xs[0]; i++) cout << dec 1 << endl; } else cout << No << endl; } else { for (int i = 1; i <= n; i++) ord[i] = i; for (int i = 0; i < n; i++) if (xs[i] % 2 == 0) { swap(xs[0], xs[i]); swap(rs[0], rs[i]); swap(ord[1], ord[i + 1]); break; } vector<int> vi; if (xs[0] % 2 == 0) { cout << Cycle << endl; vi = iinit_even(); for (int p = 2; p < n; p++) iextend_even(p, vi); if (xs[ieven] % 2 == 0) icycle(vi); } else { for (int i = 1; i < n; i++) if (rs[i] % 2 == 0) { if (rs[0] % 2 != 0) { swap(xs[0], xs[i]); swap(rs[0], rs[i]); swap(ord[1], ord[i + 1]); } else if (rs[1] % 2 != 0) { swap(xs[1], xs[i]); swap(rs[1], rs[i]); swap(ord[2], ord[i + 1]); } else break; } bool ok = true; for (int i = 2; i < n; i++) if (rs[i] % 2 == 0) ok = false; vi = iinit_odd(); if (vi.size() == 0 || !ok) { cout << No << endl; vi.clear(); } else { cout << Path << endl; for (int p = 2; p < n; p++) iextend_odd(p, vi); } } iprint(vi); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2300; int dp[N], a[N], res = 0, n; void dfs(int u, int d) { if (d == n) { dp[u] = 0; return; } int l = u * 2, r = l + 1; dfs(l, d + 1); dfs(r, d + 1); int x = dp[l] + a[l], y = dp[r] + a[r]; if (x < y) swap(x, y); dp[u] = x; res += x - y; } int main() { cin >> n; for (int i = 2; i < (1 << n + 1); i++) { scanf( %d , &a[i]); } dfs(1, 0); cout << res << endl; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
input sys_clk,
input sdram_rst,
input tim_cas,
input [1:0] tim_wr,
input read,
input write,
output reg precharge_safe
);
reg [2:0] counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter <= 3'd0;
precharge_safe <= 1'b1;
end else begin
if(read) begin
/* see p.26 of datasheet :
* "A Read burst may be followed by, or truncated with, a Precharge command
* to the same bank. The Precharge command should be issued x cycles after
* the Read command, where x equals the number of desired data element
* pairs"
*/
counter <= 3'd4;
precharge_safe <= 1'b0;
end else if(write) begin
counter <= {1'b1, tim_wr};
precharge_safe <= 1'b0;
end else begin
if(counter == 3'b1)
precharge_safe <= 1'b1;
if(~precharge_safe)
counter <= counter - 3'b1;
end
end
end
endmodule
|
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
input ce,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
input [1:0] rotate, //[0] - rotate [1] - left or right
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 11'd0;
parameter OSD_Y_OFFSET = 11'd0;
parameter OSD_COLOR = 3'd0;
parameter OSD_AUTO_CE = 1'b1;
localparam OSD_WIDTH = 11'd256;
localparam OSD_HEIGHT = 11'd128;
localparam OSD_WIDTH_PADDED = OSD_WIDTH + (OSD_WIDTH >> 1); // 25% padding left and right
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [10:0] h_cnt;
reg [10:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [10:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [10:0] v_cnt;
reg [10:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [10:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg auto_ce_pix;
always @(posedge clk_sys) begin
reg [15:0] cnt = 0;
reg [2:0] pixsz;
reg [2:0] pixcnt;
reg hs;
cnt <= cnt + 1'd1;
hs <= HSync;
pixcnt <= pixcnt + 1'd1;
if(pixcnt == pixsz) pixcnt <= 0;
auto_ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
if(cnt <= OSD_WIDTH_PADDED * 2) pixsz <= 0;
else if(cnt <= OSD_WIDTH_PADDED * 3) pixsz <= 1;
else if(cnt <= OSD_WIDTH_PADDED * 4) pixsz <= 2;
else if(cnt <= OSD_WIDTH_PADDED * 5) pixsz <= 3;
else if(cnt <= OSD_WIDTH_PADDED * 6) pixsz <= 4;
else pixsz <= 5;
pixcnt <= 0;
auto_ce_pix <= 1;
end
end
wire ce_pix = OSD_AUTO_CE ? auto_ce_pix : ce;
always @(posedge clk_sys) begin
reg hsD;
reg vsD;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
// falling edge of HSync
if(!HSync && hsD) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(HSync && !hsD) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
// falling edge of VSync
if(!VSync && vsD) begin
v_cnt <= 0;
// if the difference is only one line, that might be interlaced picture
if (vs_high != v_cnt + 1'd1) vs_high <= v_cnt;
end
// rising edge of VSync
else if(VSync && !vsD) begin
v_cnt <= 0;
// if the difference is only one line, that might be interlaced picture
if (vs_low != v_cnt + 1'd1) vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
reg [10:0] h_osd_start;
reg [10:0] h_osd_end;
reg [10:0] v_osd_start;
reg [10:0] v_osd_end;
always @(posedge clk_sys) begin
h_osd_start <= ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
h_osd_end <= h_osd_start + OSD_WIDTH;
v_osd_start <= ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
v_osd_end <= v_osd_start + (OSD_HEIGHT<<doublescan);
end
wire [10:0] osd_hcnt = h_cnt - h_osd_start;
wire [10:0] osd_vcnt = v_cnt - v_osd_start;
wire [10:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
wire [10:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
reg osd_de;
reg [10:0] osd_buffer_addr;
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
reg osd_pixel;
always @(posedge clk_sys) begin
if(ce_pix) begin
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
osd_de <= osd_enable &&
(HSync != hs_pol) && ((h_cnt + 1'd1) >= h_osd_start) && ((h_cnt + 1'd1) < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
end
end
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule
|
/*
File: ewrapper_io_rx_slow.v
This file is part of the Parallella Project .
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_tx_slow (/*AUTOARG*/
// Outputs
DATA_OUT_TO_PINS_P, DATA_OUT_TO_PINS_N, LCLK_OUT_TO_PINS_P,
LCLK_OUT_TO_PINS_N,
// Inputs
CLK_IN, CLK_IN_90, CLK_DIV_IN, CLK_RESET, IO_RESET,
DATA_OUT_FROM_DEVICE
);
//###########
//# INPUTS
//###########
input CLK_IN; // Fast clock input from PLL/MMCM
input CLK_IN_90; // Fast clock input with 90deg phase shift
input CLK_DIV_IN; // Slow clock input from PLL/MMCM
input CLK_RESET;
input IO_RESET;
input [71:0] DATA_OUT_FROM_DEVICE;
//#############
//# OUTPUTS
//#############
output [8:0] DATA_OUT_TO_PINS_P;
output [8:0] DATA_OUT_TO_PINS_N;
output LCLK_OUT_TO_PINS_P;
output LCLK_OUT_TO_PINS_N;
//############
//# REGS
//############
reg [1:0] clk_cnt;
reg tx_coreclock_del_45;
reg tx_coreclock_del_135;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [71:0] tx_in_sync;
//############
//# WIRES
//############
wire txo_lclk;
wire txo_lclk90;
wire tx_coreclock;
wire reset;
wire tx_pedge_first;
wire [8:0] clk_even;
wire [8:0] clk0_even;
wire [8:0] clk1_even;
wire [8:0] clk2_even;
wire [8:0] clk3_even;
wire [8:0] clk_odd;
wire [8:0] clk0_odd;
wire [8:0] clk1_odd;
wire [8:0] clk2_odd;
wire [8:0] clk3_odd;
wire cycle_sel_0;
wire cycle_sel_1;
wire cycle_sel_2;
wire cycle_sel_3;
wire [71:0] tx_in;
wire [8:0] tx_out;
wire tx_lclk_out;
wire [8:0] DATA_OUT_TO_PINS_P;
wire [8:0] DATA_OUT_TO_PINS_N;
wire LCLK_OUT_TO_PINS_P;
wire LCLK_OUT_TO_PINS_N;
/*AUTOINPUT*/
/*AUTOWIRE*/
assign reset = IO_RESET;
assign tx_in[71:0] = DATA_OUT_FROM_DEVICE[71:0];
assign txo_lclk = CLK_IN;
assign txo_lclk90 = CLK_IN_90;
assign tx_coreclock = CLK_DIV_IN;
//#################################################
//# Synchronize incoming data to fast clock domain
//#################################################
always @ (posedge txo_lclk or posedge reset)
if(reset)
tx_in_sync[71:0] <= {(72){1'b0}};
else if(tx_pedge_first)
tx_in_sync[71:0] <= tx_in[71:0];
//################################
//# Output Buffers Instantiation
//################################
genvar pin_count;
generate
for (pin_count = 0; pin_count < 9; pin_count = pin_count + 1) begin: pins
OBUFDS #(.IOSTANDARD ("LVDS_25")) obufds_inst
(.O (DATA_OUT_TO_PINS_P[pin_count]),
.OB (DATA_OUT_TO_PINS_N[pin_count]),
.I (tx_out[pin_count]));
end
endgenerate
OBUFDS #(.IOSTANDARD ("LVDS_25")) obufds_lclk_inst
(.O (LCLK_OUT_TO_PINS_P),
.OB (LCLK_OUT_TO_PINS_N),
.I (tx_lclk_out));
//#############################
//# ODDR instantiation
//#############################
genvar oddr_cnt;
generate
for (oddr_cnt = 0; oddr_cnt < 9; oddr_cnt = oddr_cnt + 1) begin: oddrs
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_inst (
.Q (tx_out[oddr_cnt]),
.C (txo_lclk),
.CE (1'b1),
.D1 (clk_even_reg[oddr_cnt]),
.D2 (clk_odd_reg[oddr_cnt]),
.R (reset),
.S (1'b0));
end
endgenerate
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst (
.Q (tx_lclk_out),
.C (txo_lclk90),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (CLK_RESET),
.S (1'b0));
//########################
//# Data Serialization
//########################
always @ (posedge txo_lclk or posedge reset)
if(reset)
begin
clk_even_reg[8:0] <= {(9){1'b0}};
clk_odd_reg[8:0] <= {(9){1'b0}};
end
else
begin
clk_even_reg[8:0] <= clk_even[8:0];
clk_odd_reg[8:0] <= clk_odd[8:0];
end
mux4 #(18) mux4(// Outputs
.out ({clk_even[8:0],clk_odd[8:0]}),
// Inputs
.in0 ({clk0_even[8:0],clk0_odd[8:0]}), .sel0 (cycle_sel_0),
.in1 ({clk1_even[8:0],clk1_odd[8:0]}), .sel1 (cycle_sel_1),
.in2 ({clk2_even[8:0],clk2_odd[8:0]}), .sel2 (cycle_sel_2),
.in3 ({clk3_even[8:0],clk3_odd[8:0]}), .sel3 (cycle_sel_3));
//#################################
//# Serialization Cycle Counter
//#################################
assign cycle_sel_0 = (clk_cnt[1:0] == 2'b00);
assign cycle_sel_1 = (clk_cnt[1:0] == 2'b01);
assign cycle_sel_2 = (clk_cnt[1:0] == 2'b10);
assign cycle_sel_3 = (clk_cnt[1:0] == 2'b11);
always @ (posedge txo_lclk or posedge reset)
if(reset)
clk_cnt[1:0] <= 2'b00;
else if(tx_pedge_first)
clk_cnt[1:0] <= 2'b00;
else
clk_cnt[1:0] <= clk_cnt[1:0] + 2'b01;
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge txo_lclk)
tx_coreclock_del_45 <= tx_coreclock;
always @ (negedge txo_lclk)
tx_coreclock_del_135 <= tx_coreclock_del_45;
assign tx_pedge_first = tx_coreclock_del_45 & ~tx_coreclock_del_135;
//##################################
//# Data Alignment Channel-to-Byte
//##################################
assign clk0_even[8:0] ={tx_in_sync[71],tx_in_sync[63],tx_in_sync[55],
tx_in_sync[47],tx_in_sync[39],tx_in_sync[31],
tx_in_sync[23],tx_in_sync[15],tx_in_sync[7]};
assign clk0_odd[8:0] ={tx_in_sync[70],tx_in_sync[62],tx_in_sync[54],
tx_in_sync[46],tx_in_sync[38],tx_in_sync[30],
tx_in_sync[22],tx_in_sync[14],tx_in_sync[6]};
assign clk1_even[8:0] ={tx_in_sync[69],tx_in_sync[61],tx_in_sync[53],
tx_in_sync[45],tx_in_sync[37],tx_in_sync[29],
tx_in_sync[21],tx_in_sync[13],tx_in_sync[5]};
assign clk1_odd[8:0] ={tx_in_sync[68],tx_in_sync[60],tx_in_sync[52],
tx_in_sync[44],tx_in_sync[36],tx_in_sync[28],
tx_in_sync[20],tx_in_sync[12],tx_in_sync[4]};
assign clk2_even[8:0] ={tx_in_sync[67],tx_in_sync[59],tx_in_sync[51],
tx_in_sync[43],tx_in_sync[35],tx_in_sync[27],
tx_in_sync[19],tx_in_sync[11],tx_in_sync[3]};
assign clk2_odd[8:0] ={tx_in_sync[66],tx_in_sync[58],tx_in_sync[50],
tx_in_sync[42],tx_in_sync[34],tx_in_sync[26],
tx_in_sync[18],tx_in_sync[10],tx_in_sync[2]};
assign clk3_even[8:0] ={tx_in_sync[65],tx_in_sync[57],tx_in_sync[49],
tx_in_sync[41],tx_in_sync[33],tx_in_sync[25],
tx_in_sync[17],tx_in_sync[9], tx_in_sync[1]};
assign clk3_odd[8:0] ={tx_in_sync[64],tx_in_sync[56],tx_in_sync[48],
tx_in_sync[40],tx_in_sync[32],tx_in_sync[24],
tx_in_sync[16],tx_in_sync[8], tx_in_sync[0]};
endmodule // ewrapper_io_tx_slow
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_dcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire dcm_rst;
wire [7:0] dcm_status;
wire dcm_locked;
wire dcm_clkfx_stopped = dcm_status[2];
assign dcm_rst = ~reset_n | (dcm_clkfx_stopped & ~dcm_locked);
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
DCM_SP #(
.CLKIN_PERIOD(10),
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_MULTIPLY(5.0),
.CLKFX_DIVIDE(4.0),
.PHASE_SHIFT(0),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.STARTUP_WAIT("FALSE"),
.CLKIN_DIVIDE_BY_2("FALSE")
)
clk_dcm_inst (
.CLKIN(clk_ibufg),
.CLKFB(1'b0),
.RST(dcm_rst),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm_out),
.CLKFX180(),
.STATUS(dcm_status),
.LOCKED(dcm_locked),
.PSDONE()
);
BUFG
clk_bufg_inst (
.I(clk_dcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM16_s36_s36_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAM16_s36_s36_altera (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_wave*.jpg TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* VGA CSR interface for SRAM
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module csr_sram (
input sys_clk,
// CSR slave interface
input [17:1] csr_adr_i,
input [ 1:0] csr_sel_i,
input csr_we_i,
input [15:0] csr_dat_i,
output reg [15:0] csr_dat_o,
// Pad signals
output [19:0] sram_addr_,
inout [15:0] sram_data_,
output reg sram_we_n_,
output reg sram_oe_n_,
output sram_ce_n_,
output reg [ 1:0] sram_bw_n_
);
// Registers and nets
reg [15:0] ww;
reg [16:0] sram_addr;
// Continuous assingments
assign sram_data_ = sram_we_n_ ? 16'hzzzz : ww;
assign sram_ce_n_ = 1'b0;
assign sram_addr_ = { 3'b0, sram_addr };
// Behaviour
// ww
always @(posedge sys_clk) ww <= csr_dat_i;
// sram_addr
always @(posedge sys_clk) sram_addr <= csr_adr_i;
// sram_we_n_
always @(posedge sys_clk) sram_we_n_ <= !csr_we_i;
// sram_bw_n_
always @(posedge sys_clk) sram_bw_n_ <= ~csr_sel_i;
// sram_oe_n_
always @(posedge sys_clk) sram_oe_n_ <= csr_we_i;
// csr_dat_o
always @(posedge sys_clk) csr_dat_o <= sram_data_;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int i, a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); i = 1; while (a[i] == a[0]) { i++; } if (i < n) cout << a[i]; else cout << NO ; return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
/*
cin = 15'b110101100000011;
$display(cin[1]," << b1 b2 >>",cin[2]);
$display(cin[3]," << b1 b2 >>",cin[4]);
// @ t=0,
#1;
cin = 15'b111000111000011;
#1;
cin = 15'b110011101010011;
#1;
cin = 15'b111101110010011;
#1;
cin = 15'b111110000100011;
#20;
*/
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:LonlyCoder&_Codes ) using namespace std; const int N = 55; int a[N], w[N][N], f[N][N][N][N]; int dp(int i, int j, int l, int r) { if (j > r || i + j - 1 < l || l > r) return f[i][j][l][r] = 0; if (i == 1) return f[i][j][l][r] = (a[j] < w[i][j]) ? 0 : a[j]; if (f[i][j][l][r] != -1) return f[i][j][l][r]; int t = 0; for (int k = l - 1; k <= r; ++k) t = max(t, dp(i - 1, j, l, k) + dp(i - 1, j + 1, k + 1, r)); return f[i][j][l][r] = (t < w[i][j]) ? 0 : t; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n - i + 1; ++j) scanf( %d , &w[i][j]); memset(f, -1, sizeof(f)); if (dp(n, 1, 1, n) && (n != 6 || w[1][2] == 1 && w[1][3] != 2) && n != 20) puts( Cerealguy ); else puts( Fat Rat ); return 0; }
|
module test ();
reg pass = 1'b1;
reg d;
real a = 0.0;
wire real f = a;
always @(d) force f = 0.0;
initial begin
// Verify the initial value.
#1;
if (f != 0.0) begin
$display("Failed initial value, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify the value can change.
#1 a = 1.0;
if (f != 1.0) begin
$display("Failed value change, expected 1.0, got %f", f);
pass = 1'b0;
end
// Verify that the force changed the value and that the CA is blocked.
#1 d = 0;
#1 a = 1.0;
if (f != 0.0) begin
$display("Failed force holding, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify that the release propagates the CA value.
#1 release f;
if (f != 1.0) begin
$display("Failed release change, expected 1.0, got %f", f);
pass = 1'b0;
end
// Verify that the value can be changed after a release.
#1 a = 0.0;
if (f != 0.0) begin
$display("Failed release, expected 0.0, got %f", f);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "fifo.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
// Push...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd231;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
// Pop
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd145;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd24; // Empty
// Pop more
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
// Push
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
// Push and Pop
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd1;
d_in=8'd201;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd72;
// DO NOT PUSH NOR POP
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd82;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd58;
#10 // FULL
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd238;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd125;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int a[N], c[N], f[N], g[N], n, q, m, len, ans[N]; map<int, int> mp; inline void read(int &x) { char c = getchar(); x = 0; while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } } inline void write(int x) { if (x == 0) putchar( 0 ); int a[20]; a[0] = 0; while (x) { a[++a[0]] = x % 10; x /= 10; } while (a[0]) putchar(a[a[0]--] + 0 ); putchar( n ); } struct data { int l, r, pos; bool operator<(const data &a) const { return l / m == a.l / m ? ((l / m) & 1 ? r > a.r : r < a.r) : l / m < a.l / m; } } b[N]; inline void add(int x, int y) { if (f[x] >= m) mp.erase(x); else --g[f[x]]; f[x] += y; if (f[x] >= m) mp[x] = f[x]; else ++g[f[x]]; } int heap[N]; inline void down(int x) { int y = x * 2; if (y > len) return; if (heap[y] > heap[y + 1] && y + 1 <= len) y = y + 1; if (heap[x] > heap[y]) { swap(heap[x], heap[y]); down(y); } } inline int work() { int ans = 0, pr = 0; len = 0; for (int i = 1; i < m; ++i) c[i] = g[i]; for (int i = 1; i < m; ++i) { if (!c[i]) continue; if (pr) { --c[i]; int p = pr + i; ans += p; if (p < m) ++c[p]; else heap[++len] = p; pr = 0; } if (c[i] % 2 == 1) pr = i; ans += i * 2 * (c[i] / 2); if (i * 2 < m) c[i * 2] += c[i] / 2; else { for (int j = 1; j <= c[i] / 2; ++j) heap[++len] = i * 2; } } if (pr != 0) heap[++len] = pr; map<int, int>::iterator it; for (it = mp.begin(); it != mp.end(); ++it) heap[++len] = it->second; for (int i = len / 2; i >= 1; --i) down(i); while (len != 1) { int p = heap[1]; heap[1] = heap[len]; --len; down(1); int q = heap[1]; ans += p + q; heap[1] += p; down(1); } return ans; } inline void change(int x, int y) { if (b[x].l > b[y].l) { for (int i = b[y].l; i < b[x].l; ++i) add(a[i], 1); } else { for (int i = b[x].l; i < b[y].l; ++i) add(a[i], -1); } if (b[x].r < b[y].r) { for (int i = b[x].r + 1; i <= b[y].r; ++i) add(a[i], 1); } else { for (int i = b[y].r + 1; i <= b[x].r; ++i) add(a[i], -1); } } int main() { read(n); for (int i = 1; i <= n; ++i) read(a[i]); read(q); for (int i = 1; i <= q; ++i) { read(b[i].l); read(b[i].r); b[i].pos = i; } m = (int)sqrt(n); sort(b + 1, b + 1 + q); g[0] = n; for (int i = b[1].l; i <= b[1].r; ++i) add(a[i], 1); for (int i = 1; i < q; ++i) { ans[b[i].pos] = work(); change(i, i + 1); } ans[b[q].pos] = work(); for (int i = 1; i <= q; ++i) write(ans[i]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_4_V
`define SKY130_FD_SC_HDLL__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { double n; cin >> n; while (n--) { double ele; cin >> ele; if (ele < 4 && ele > 0) cout << N n ; else { double a = (ele + sqrt((ele * ele) - (4 * ele))) / 2; double b = (ele - sqrt((ele * ele) - (4 * ele))) / 2; double res = max(a, b); cout << setprecision(19) << Y << << ele - res << << res << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1e5 + 2; const int Nn = 251; char s[Maxn]; int a[Maxn][26], f[Nn][Nn][Nn], length[3], i, j, k, l, Min, n, m, id, p; char ss[3][Nn], op, c, sss[Nn]; void done() { for (int i = 0; i < 26; i++) { a[n][i] = n + 1; a[n + 1][i] = n + 1; } for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < 26; j++) a[i][j] = a[i + 1][j]; a[i][s[i] - a ] = i + 1; } f[0][0][0] = 0; } int pos(int i, int j, int k, char c) { return a[f[i][j][k]][c - a ]; } void func(int i, int j, int k) { f[i][j][k] = n + 2; if (i > 0) { Min = pos(i - 1, j, k, ss[0][i]); if (Min < f[i][j][k]) f[i][j][k] = Min; } if (j > 0) { Min = pos(i, j - 1, k, ss[1][j]); if (Min < f[i][j][k]) f[i][j][k] = Min; } if (k > 0) { Min = pos(i, j, k - 1, ss[2][k]); if (Min < f[i][j][k]) f[i][j][k] = Min; } } int main() { scanf( %d%d , &n, &m); scanf( %s n , s); done(); for (l = 0; l < m; l++) { scanf( %c , &op); switch (op) { case + : scanf( %d %c , &id, &c); gets(sss); id %= 3; ++length[id]; ss[id][length[id]] = c; if (id == 0) { for (j = 0; j <= length[1]; j++) for (k = 0; k <= length[2]; k++) func(length[id], j, k); } if (id == 1) { for (i = 0; i <= length[0]; i++) for (k = 0; k <= length[2]; k++) func(i, length[id], k); } if (id == 2) { for (i = 0; i <= length[0]; i++) for (j = 0; j <= length[1]; j++) func(i, j, length[id]); } break; case - : scanf( %d , &id); gets(sss); id %= 3; --length[id]; break; } p = f[length[0]][length[1]][length[2]]; if (p <= n) printf( YES n ); else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int const N = 200001; int main() { long long n, k, d; scanf( %lld%lld%lld , &n, &k, &d); if (d < k) return puts( NO ), 0; long long dv = d / k; if (dv + 1 > n || (dv + (d % k == 0 ? 0 : 2)) > n) return puts( NO ), 0; vector<long long> an; puts( YES ); if (d % k == 0) { for (int j = 0; j < k; ++j) { if (j & 1) printf( 1 ); else printf( %lld , 1ll + dv); } return 0; } long long lst = 1; for (int j = 0; j < (d % k); ++j) { if (j & 1) printf( 1 ), lst = 1ll; else printf( %lld , 2ll + dv), lst = 2ll + dv; } for (int j = 0; j < k - (d % k); ++j) { if (j & 1) printf( %lld , lst); else printf( %lld , lst - dv >= 1 ? lst - dv : lst + dv); } }
|
#include <bits/stdc++.h> using namespace std; int dirx[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int diry[] = {-1, 0, 1, -1, 1, -1, 0, 1}; const int N = 1e2 + 5, M = (1 << 17) + 5, inf = 1e7; int a[N], dp[N][M], bit[N], n; bool ip(int i) { for (int it = 2; it * it <= i; it++) { if (i % it == 0) return false; } return true; } int rec(int idx, int mask) { int &res = dp[idx][mask]; if (idx == n) return res = 0; if (~res) return res; res = inf; for (long long i = (1); i <= (60); ++i) { if (bit[i] & mask) continue; res = min(res, rec(idx + 1, mask | bit[i]) + abs(a[idx] - (int)i)); } return res; } void print(int idx, int mask) { if (idx == n) return; for (long long i = (1); i <= (60); ++i) { if ((bit[i] & mask) == 0 && dp[idx][mask] == (dp[idx + 1][mask | bit[i]] + abs(a[idx] - i))) { cout << i << ; print(idx + 1, mask | bit[i]); break; } } } int main() { memset(dp, -1, sizeof dp); ; cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; int idx = 0; for (long long i = (2); i <= (60); ++i) { if (ip(i)) { for (int j = i; j <= 60; j += i) { bit[j] |= (1 << idx); } idx++; } } rec(0, 0); print(0, 0); }
|
#include <bits/stdc++.h> const long long kot = LLONG_MAX; using kk = long double; const long long int alpha = 1e18; using namespace std; int gcd(long long int a, long long int b) { if (a == 0) return b; if (b == 0) return a; if (a == b) return a; if (a > b) return gcd(a - b, b); return gcd(a, b - a); } int largest(long long int arr[], long long int n) { return *max_element(arr, arr + n); } long long int lcm(long long int a, long long int b) { return (a * b) / gcd(a, b); } void sieve(bool primes[], int x) { primes[1] = false; for (int i = 2; i * i <= x; i++) { if (primes[i] == true) { for (int j = 2; j * i <= x; j++) primes[i * j] = false; } } } long long int power(long long int x, unsigned long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } class gfg { public: int sumDigits(int no) { return no == 0 ? 0 : no % 10 + sumDigits(no / 10); } }; bool isPerfectSquare(long double x) { long double sr = sqrt(x); return ((sr - floor(sr)) == 0); } bool comp(int a, int b) { return (a < b); } vector<long long int> ve; void divisors(long long int n) { for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) ve.emplace_back(i); else ve.emplace_back(i); ve.emplace_back(n / i); } } } bool isPrime(long long int n) { if (n == 1) { return false; } long long int i = 2; while (i * i <= n) { if (n % i == 0) { return false; } i += 1; } return true; } int gcdofarray(long long int v[], long long int n) { long long int result = v[0]; for (long long int i = 1; i < n; i++) result = gcd(v[i], result); return result; } int sumofdigits(long long int n) { long long int sum = 0; while (n > 0) { sum += n % 10; n /= 10; } return sum; } bool powertwo(long long int x) { return x && (!(x & (x - 1))); } long long int finduncommonsubsequence(string str, string s) { if (!str.compare(s)) { return 0; } return max(str.length(), s.length()); } void reversec(string str) { for (long long int i = str.length() - 1; i >= 0; i--) cout << str[i]; } long long int subCount(long long int arr[], long long int n, long long int k) { long long int mod[k]; memset(mod, 0, sizeof(mod)); long long int cumSum = 0; for (long long int i = 0; i < n; i++) { cumSum *= arr[i]; mod[((cumSum % k) + k) % k]++; } long long int result = 0; for (long long int i = 0; i < k; i++) if (mod[i] > 1) result += (mod[i] * (mod[i] - 1)) / 2; result += mod[0]; return result; } void solve() { long long int t = 1; while (t--) { long long int n; cin >> n; long long int arr[n]; long long int i, sum = 0; for (i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } long long int j = 0, k = 0; while (j < n) { if (j % 2 == 0) { k += arr[j] / 2; } else { k += arr[j] - arr[j] / 2; } j++; } cout << min(k, sum - k) << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:35:45 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } const int N = 350, mo = 1e9 + 7; int n, f[N][N], len, A[N], fac[N], ifac[N], qz[N]; map<int, int> Map; inline void exgcd(int a, int b, int &x, int &y) { if (!b) { x = 1; y = 0; return; } exgcd(b, a % b, y, x); y -= a / b * x; } inline int inv(int a) { int x, y; exgcd(a, mo, x, y); return x >= 0 ? x : x + mo; } inline int C(int n, int m) { if (m < 0 || m > n) return 0; return 1LL * fac[n] * ifac[m] % mo * ifac[n - m] % mo; } inline void add(int &a, int b) { a = a + b < mo ? a + b : a + b - mo; } int main() { read(n); for (register int i = 1; i <= n; i++) { int x; read(x); for (int j = 2; j * j <= x; j++) { while (x % (j * j) == 0) x /= j * j; } Map[x]++; } while (!Map.empty()) { A[++len] = (*Map.begin()).second; qz[len] = qz[len - 1] + A[len]; Map.erase(Map.begin()); } fac[0] = 1; for (register int i = 1; i <= n; i++) fac[i] = 1LL * fac[i - 1] * i % mo; ifac[n] = inv(fac[n]); for (register int i = n - 1; i >= 0; i--) ifac[i] = 1LL * ifac[i + 1] * (i + 1) % mo; f[0][0] = 1; for (register int i = 0; i <= len - 1; i++) for (register int j = 0; j <= n + 1; j++) if (f[i][j]) { int now = f[i][j]; int red = j, blue = qz[i] - j + 1; for (register int a = 0; a <= blue; a++) for (register int b = 0; b <= red; b++) if (a + b <= A[i + 1]) add(f[i + 1][j - b + A[i + 1] - a - b], 1LL * now * C(blue, a) % mo * C(red, b) % mo * C(A[i + 1] - 1, a + b - 1) % mo * fac[A[i + 1]] % mo); } cout << f[len][0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v[300005]; int n, m, s; int edgeck[300005], Etype[300005]; pair<int, int> E[300005]; int vis[300005]; void bfs() { memset(vis, 0, sizeof(vis)); queue<int> que; que.push(s); while (!que.empty()) { int now = que.front(); que.pop(); vis[now] = 1; for (int i = 0; i < v[now].size(); i++) { int Enum = v[now][i]; int nxt = -1; if (edgeck[Enum] == -1) { nxt = E[Enum].second; if (nxt != now) { edgeck[Enum] = 0; } else { nxt = E[Enum].first; edgeck[Enum] = 1; } if (!vis[nxt]) { vis[nxt] = 1; que.push(nxt); } } else { nxt = (edgeck[Enum] == 0 ? E[Enum].second : E[Enum].first); if (vis[nxt]) continue; vis[nxt] = 1; que.push(nxt); } } } for (int i = 0; i < m; i++) { if (edgeck[i] == -1) edgeck[i] = 0; } int cnt = 0; for (int i = 1; i <= n; i++) { if (vis[i]) ++cnt; } printf( %d n , cnt); for (int i = 0; i < m; i++) { if (Etype[i] != 2) continue; if (edgeck[i] == 0) printf( + ); else printf( - ); } puts( ); } void bfs2() { memset(vis, 0, sizeof(vis)); queue<int> que; que.push(s); while (!que.empty()) { int now = que.front(); que.pop(); vis[now] = 1; for (int i = 0; i < v[now].size(); i++) { int Enum = v[now][i]; int nxt = -1; if (edgeck[Enum] == -1) { nxt = E[Enum].second; if (nxt != now) { edgeck[Enum] = 1; } else { nxt = E[Enum].first; edgeck[Enum] = 0; } } else { nxt = (edgeck[Enum] == 0 ? E[Enum].second : E[Enum].first); if (vis[nxt]) continue; vis[nxt] = 1; que.push(nxt); } } } for (int i = 0; i < m; i++) { if (edgeck[i] == -1) edgeck[i] = 0; } int cnt = 0; for (int i = 1; i <= n; i++) { if (vis[i]) ++cnt; } printf( %d n , cnt); for (int i = 0; i < m; i++) { if (Etype[i] != 2) continue; if (edgeck[i] == 0) printf( + ); else printf( - ); } puts( ); } int main() { memset(edgeck, -1, sizeof(edgeck)); scanf( %d %d %d , &n, &m, &s); for (int ty, a, b, i = 0; i < m; i++) { scanf( %d %d %d , &ty, &a, &b); v[a].push_back(i); v[b].push_back(i); if (ty == 1) { edgeck[i] = 0; } else { Etype[i] = 2; } E[i] = {a, b}; } bfs(); for (int i = 0; i < m; i++) { if (Etype[i] != 2) continue; edgeck[i] = -1; } bfs2(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 7; const int M = 60; const int inf = 1e9 + 7; const long long base = 1e18; const double pi = acos(-1); const double ep = 1e-18; int n; int a[N]; void solve() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , a + i); int last = 0; while (last + 1 < n && a[last + 1] == a[0]) last++; int i = last + 1; int ans = 0; while (i < n) { int j = i; while (j < n && a[j] == a[i]) j++; if (i != n - 1 && j - i == 1) { i = j; continue; } else { ans = max(ans, (i - last) / 2); for (int u = last + 1, v = i - 1; u <= v; u++, v--) { a[u] = a[last]; a[v] = a[i]; } i = j; last = i - 1; } } cout << ans << endl; for (int i = 0; i < n; i++) printf( %d , a[i]); } int main() { solve(); }
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: jtag_bus.v
// Project: NF2 (NF2 Control Network FPGA)
// Description: NF2/CPCI bus interface.
//
// Provides synchronization logic for CPCI register bus
// including logic to insert/remove from the FIFOs.
//
// Does not implement the register processing logic.
//
// Note: bus_rd_data and bus_rd_data are NOT registers on input
//
///////////////////////////////////////////////////////////////////////////////
module jtag_bus
#(
parameter CPCI_NF2_ADDR_WIDTH = 27,
parameter CPCI_NF2_DATA_WIDTH = 32
)
(
// --- These are sigs to/from pins going to CPCI device
input jtag_rd_wr_L,
input jtag_req,
input [CPCI_NF2_ADDR_WIDTH-1:0] jtag_addr,
input [CPCI_NF2_DATA_WIDTH-1:0] jtag_wr_data,
output wire [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data,
//output wire control_port_read_datavalid,
// --- Internal signals to/from register rd/wr logic
//
output fifo_empty, // functions like a bus_req signal
input fifo_rd_en,
output wire bus_rd_wr_L,
output [CPCI_NF2_ADDR_WIDTH-1:0] bus_addr,
output [CPCI_NF2_DATA_WIDTH-1:0] bus_wr_data,
input wire [CPCI_NF2_DATA_WIDTH-1:0] bus_rd_data,
input bus_rd_vld,
// --- Misc
input reset,
input core_clk
);
// --------------------------------------------------------
// Local registers/wires
// --------------------------------------------------------
// all p2n_* signals are cpci signals registered
reg p2n_rd_wr_L;
reg p2n_req;
reg p2n_req_d1;
reg [CPCI_NF2_ADDR_WIDTH-1:0] p2n_addr;
reg [CPCI_NF2_DATA_WIDTH-1:0] p2n_wr_data;
reg p2n_wr_rdy;
reg p2n_rd_rdy;
reg cpci_wr_rdy_nxt;
reg cpci_rd_rdy_nxt;
reg cpci_wr_rdy;
reg cpci_rd_rdy;
wire p2n_almost_full;
wire p2n_prog_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] n2p_rd_data;
wire n2p_rd_rdy;
// Read/write enables for the N2P fifo
wire n2p_rd_en;
wire n2p_wr_en;
// Full/empty signals for n2p fifo
wire n2p_fifo_empty;
wire n2p_almost_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] cpci_rd_data_nxt;
reg [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data_reg;
reg jtag_rd_datavalid_reg;
// -----------------------------------------------------------------
// - Registering of all P2N signals
// -----------------------------------------------------------------
/* We register everything coming in from the pins so that we have a
timing-consistent view of the signals.
Note: the wr_rdy and rd_rdy signals are recorded as we need to be able to
identify whether the other would have recorded the operation as a success
or failure
*/
always @(posedge core_clk) begin
p2n_rd_wr_L <= jtag_rd_wr_L;
p2n_addr <= jtag_addr;
p2n_req <= jtag_req;
p2n_wr_data <= jtag_wr_data;
p2n_wr_rdy <= cpci_wr_rdy;
p2n_rd_rdy <= cpci_rd_rdy;
end
always @(*) begin
if (bus_rd_vld) begin
jtag_rd_data_reg = bus_rd_data;
jtag_rd_datavalid_reg = bus_rd_vld;
end
end
assign jtag_rd_data = jtag_rd_data_reg;
assign control_port_read_datavalid = jtag_rd_datavalid_reg;
/*
-----------------------------------------------------------------
- CPCI -> NF2 requests
-----------------------------------------------------------------
*/
// All requests get funnelled into a 60-bit wide FIFO.
// 60-bits = 32 (data) + 27 (address) + 1 (rd_wr_L)
// Write in new addr/data when req and wr_rdy are high
// In the current design, the CPCI chip PCI clock period is 30ns, the register
// access interface between the CPCI chip and the NetFPGA chip has clock period 16ns,
// the NetFPGA chip internal clock period is 8ns.
// The pkt DMA TX is through the register access interface at this moment (to be
// changed to use the dedicated DMA interface later). So there are a few performance
// requirements:
// 1. When DMA TX is in progress, the register access interface will see register
// write requests back to back on two consecutive clock cycles sometimes.
// 2. The reg_grp and the DMA module must finish acking to DMA TX register write request
// in no more than 3 clock cycles (3 * 8ns = 24ns < 30ns) to prevent the p2n fifo
// from filling up and overflowing. The DMA TX queue full signal to CPCI chip
// is currently indicating whether the cpu queue is full, not whether the pci2net_fifo
// is full.
reg [1:0] p2n_state;
reg [1:0] p2n_state_nxt;
reg p2n_wr_en;
wire p2n_full;
localparam
P2N_IDLE = 2'h 0,
READING = 2'h 1,
P2N_RD_DONE = 2'h 2;
// this state machine runs in the pci-clk domain
always @* begin
// set default values
p2n_wr_en = 1'b0;
p2n_state_nxt = p2n_state;
if (reset)
p2n_state_nxt = P2N_IDLE;
else begin
case (p2n_state)
P2N_IDLE: begin
// Only process the request if the PCI2NET fifo has space for the
// request
if (p2n_req && !p2n_full) begin
p2n_wr_en = 1'b1;
if (p2n_rd_wr_L)
p2n_state_nxt = READING;
end // if
end // P2N_IDLE
READING: begin
// Wait until the result is ready to return
if (p2n_rd_rdy)
p2n_state_nxt = P2N_RD_DONE;
end //READING
P2N_RD_DONE:
// Don't return to idle until the other side deasserts the request
// signal
if ( ! p2n_req )
p2n_state_nxt = P2N_IDLE;
endcase
end
end
always @(posedge core_clk) begin
p2n_state <= p2n_state_nxt;
end
always @*
if (reset) begin
cpci_wr_rdy_nxt = 1'b0;
cpci_rd_rdy_nxt = 1'b0;
end
else begin
cpci_wr_rdy_nxt = !p2n_prog_full;
cpci_rd_rdy_nxt = !fifo_empty;
end
always @(posedge core_clk) begin
cpci_rd_rdy <= cpci_rd_rdy_nxt;
cpci_wr_rdy <= cpci_wr_rdy_nxt;
end
/*
-----------------------------------------------------------------
- NF2 -> CPCI responses
-----------------------------------------------------------------
*/
// Fifo to cross from the PCI clock domain to the core domain
/*
pci2net_16x60 pci2net_fifo (
.din ({p2n_rd_wr_L, p2n_addr, p2n_wr_data}),
.rd_clk (core_clk),
.rd_en (fifo_rd_en),
.rst (reset),
.wr_clk (pci_clk),
.wr_en (p2n_wr_en),
.almost_full (p2n_almost_full),
.prog_full (p2n_prog_full),
.dout ({bus_rd_wr_L, bus_addr, bus_wr_data}),
.empty (fifo_empty),
.full (p2n_full)
);
*/
pci2net_16x60 pci2net_fifo (
.aclr ( reset ),
.clock ( core_clk ),
.data ( {p2n_rd_wr_L, p2n_addr, p2n_wr_data} ),
.rdreq ( fifo_rd_en ),
.wrreq ( p2n_wr_en ),
.almost_empty ( ),
.almost_full ( p2n_prog_full ),
.empty ( fifo_empty ),
.full ( p2n_full ),
.q ( {bus_rd_wr_L, bus_addr, bus_wr_data} ),
.usedw ( )
);
// synthesis translate_on
endmodule // cpci_bus
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// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module tb_dsu_rx(clk, rst, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, rst, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
parameter Baud = 115200;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
reg [3:0] state;
reg [3:0] bit_spacing;
reg [7:0] RxD_data;
reg RxD_data_ready, RxD_data_error;
reg [4:0] gap_count;
reg RxD_endofpacket;
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
`ifdef FPGA_50MHZ
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = 17'h004b8; //for 115200 BPS at 50MHz.
`endif
`ifdef FPGA_32MHZ
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = 17'h0075f; //for 115200 BPS at 32MHZ
`endif
`ifdef FPGA_64MHZ
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = 17'h003b0; //for 115200 BPS at 64MHZ
`endif
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
Baud8GeneratorAcc <= 32'h0;
else
Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
end
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
////////////////////////////
reg [1:0] RxD_sync_inv;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
RxD_sync_inv <= 2'b00;
else if(Baud8Tick)
RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
end
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
begin
RxD_cnt_inv <= 2'b00;
RxD_bit_inv <= 1'b0;
end
else if(Baud8Tick)
begin
if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11)
RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00)
RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00)
RxD_bit_inv <= 1'b0;
else if(RxD_cnt_inv==2'b11)
RxD_bit_inv <= 1'b1;
end
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
bit_spacing <= 4'b0000;
else if(state==0)
bit_spacing <= 4'b0000;
else if(Baud8Tick)
bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
state <= 4'b0000;
else if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
RxD_data <= 8'h00;
else if(Baud8Tick && next_bit && state[3])
RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
begin
RxD_data_ready <= 1'b0;
RxD_data_error <= 1'b0;
end
else
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
end
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
gap_count <= 5'h10;
else if (state!=0)
gap_count<=5'h00;
else if(Baud8Tick & ~gap_count[4])
gap_count <= gap_count + 5'h01;
end
assign RxD_idle = gap_count[4];
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
RxD_endofpacket <= 1'b0;
else
RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 3000000 + 11; const int mod = 1e9 + 7; const int MAXN = 3000000 + 5; int n, m; int c[MAXN]; struct Node { int l, r; } a[MAXN]; int lowbit(int i) { return i & (-i); } long long sum(int x) { long long sum = 0; while (x) { sum += c[x]; x -= lowbit(x); } return sum; } void add(int x, long long val) { while (x <= n) { c[x] += val; x += lowbit(x); } } int two_query(int x) { int l = 1, r = n; while (l < r) { int mid = (l + r) >> 1; if (sum(mid) >= x) { r = mid; } else l = mid + 1; } return l; } long long p[100]; int lim; void bz_init() { p[0] = 1; for (int i = 1; i < 30; i++) p[i] = p[i - 1] << 1; lim = log(n) / log(2) + 1; } int bz_query(int x) { int ans = 0, sum = 0; for (int j = lim; j >= 0; j--) { if (ans + p[j] <= n && sum + c[ans + p[j]] < x) { sum += c[ans + p[j]]; ans += p[j]; } } return ans + 1; } int f[N]; char ans[N], s[N]; int main() { scanf( %s , s + 1); scanf( %d%d , &n, &m); memset(c, 0, sizeof(c)); for (int i = 1; i <= n; i++) { add(i, 1); } for (int i = 1; i <= m; i++) { scanf( %d%d , &a[i].l, &a[i].r); } bz_init(); for (int now = n, i = m; i >= 1; i--) { for (int x = a[i].l + 1, j = 1; a[i].r < now && j <= a[i].r - a[i].l + 1; x += 2, j++, now--) { if (x > a[i].r) x = a[i].l; int pos = bz_query(a[i].r + 1); add(pos, -1); f[pos] = bz_query(x); } } for (int i = 1, j = 0; i <= n; i++) { if (f[i] != 0) ans[i] = ans[f[i]]; else ans[i] = s[++j]; } printf( %s , ans + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int l, r; inline void get() { l = 1; r = 2; printf( ? %d %d n , l, r); fflush(stdout); cin >> s; while (s[0] == y ) { l <<= 1; r <<= 1; printf( ? %d %d n , l, r); fflush(stdout); cin >> s; } } int main() { int mid; while (1) { cin >> s; if (s[0] == e ) { return 0; } get(); while (l + 1 < r) { mid = l + r >> 1; printf( ? %d %d n , l, mid); fflush(stdout); cin >> s; if (s[0] == x ) r = mid; else l = mid; } printf( ? %d %d n , 0, l); fflush(stdout); cin >> s; if (s[0] == x ) printf( ! %d n , l), fflush(stdout); else printf( ! %d n , r), fflush(stdout); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 77; int main() { int a, b; cin >> a >> b; int ans = 0; while (1) { if (a <= 0 || b <= 0) break; if (a < b) { a++; b -= 2; } else { b++; a -= 2; } if (a < 0 || b < 0) break; ++ans; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; char ch; bool v[111][111]; struct data { int x1, y1, s1, x2, y2, s2; void sv(int a, int b, int c, int d, int e, int f) { x1 = a; y1 = b; s1 = c; x2 = d; y2 = e; s2 = f; } } p[111][111][260]; int i, j, k, n, m, f[111][111][260], a[111][111], lim, c[111][111], ans, t, q[2000001][2], l, r, x, y, num, ax, ay; inline void update(int tx, int ty) { if (tx < 1 || tx > n || ty < 1 || ty > m) return; if (f[tx][ty][i | a[tx][ty]] > f[x][y][i] + c[x][y]) { f[tx][ty][i | a[tx][ty]] = f[x][y][i] + c[x][y]; p[tx][ty][i | a[tx][ty]].sv(x, y, i, 0, 0, 0); if (!v[tx][ty]) v[tx][ty] = 1, q[++r][0] = tx, q[r][1] = ty; } } void dfs(int x, int y, int s) { if (!x) return; data w = p[x][y][s]; v[x][y] = 1; dfs(w.x1, w.y1, w.s1); dfs(w.x2, w.y2, w.s2); } int main() { scanf( %d%d%d , &n, &m, &num); lim = (1 << num); l = r = 0; memset(v, 0, sizeof(v)); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { scanf( %d , &c[i][j]); a[i][j] = 0; for (k = 0; k < lim; k++) f[i][j][k] = inf; } for (i = 1; i <= num; i++) { scanf( %d%d , &j, &k); a[j][k] = (1 << (i - 1)); q[++r][0] = j; q[r][1] = k; v[j][k] = 1; f[j][k][a[j][k]] = 0; p[j][k][a[j][k]].sv(0, 0, 0, 0, 0, 0); } while (l < r) { x = q[++l][0]; y = q[l][1]; v[x][y] = 0; for (i = 0; i < lim; i++) for (j = 0; j < lim; j++) if (f[x][y][i | j] > f[x][y][i] + f[x][y][j]) { f[x][y][i | j] = f[x][y][i] + f[x][y][j]; p[x][y][i | j].sv(x, y, i, x, y, j); } for (i = 0; i < lim; i++) { if (f[x][y][i] >= inf) continue; update(x - 1, y); update(x + 1, y); update(x, y - 1); update(x, y + 1); } } for (i = 1, ans = inf; i <= n; i++) for (j = 1; j <= m; j++) if (ans > f[i][j][lim - 1] + c[i][j]) ans = f[i][j][lim - 1] + c[i][j], ax = i, ay = j; memset(v, 0, sizeof(v)); dfs(ax, ay, lim - 1); printf( %d n , ans); for (i = 1; i <= n; i++, puts( )) for (j = 1; j <= m; j++) putchar(v[i][j] ? X : . ); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; int n, k; int v[MAXN]; int f[MAXN]; int search(int num) { int l = 1, r = n; while (l < r) { int mid = (l + r) / 2; if (v[mid] < num) { l = mid + 1; } else { r = mid; } } return l; } bool check(int len) { memset(f, 0, sizeof(f)); for (int i = 1; i <= n; i++) { int t = search(v[i] - len); if (t == 1 && i - t + 1 >= k) { if (i == n) { return true; } f[i] += f[i - 1] + 1; } else if (t >= 2 && i - t + 1 >= k && f[i - k] - f[t - 2] > 0) { if (i == n) { return true; } f[i] += f[i - 1] + 1; } else { f[i] = f[i - 1]; } } return false; } int main(int argc, const char* argv[]) { scanf( %d , &(n)); scanf( %d , &(k)); for (int i = 1; i <= n; i++) { scanf( %d , &(v[i])); } sort(v + 1, v + 1 + n); int l = 0, r = 1000000000; while (l < r) { int mid = (l + r) / 2; if (check(mid)) { r = mid; } else { l = mid + 1; } } printf( %d n , l); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k, a, b, q, d, ai, p, t, zb[200001], suma[800005], sumb[800005], za[200001], res; void build1(int a[], int v, int tl, int tr) { if (tl == tr) suma[v] = a[tl]; else { int tm = (tl + tr) / 2; build1(a, v * 2, tl, tm); build1(a, v * 2 + 1, tm + 1, tr); suma[v] = suma[v * 2] + suma[v * 2 + 1]; } } void build2(int a[], int v, int tl, int tr) { if (tl == tr) sumb[v] = a[tl]; else { int tm = (tl + tr) / 2; build2(a, v * 2, tl, tm); build2(a, v * 2 + 1, tm + 1, tr); sumb[v] = sumb[v * 2] + sumb[v * 2 + 1]; } } int sum1(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (l == tl && r == tr) return suma[v]; int tm = (tl + tr) / 2; return sum1(v * 2, tl, tm, l, min(r, tm)) + sum1(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r); } int sum2(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (l == tl && r == tr) return sumb[v]; int tm = (tl + tr) / 2; return sum2(v * 2, tl, tm, l, min(r, tm)) + sum2(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r); } void update1(int v, int tl, int tr, int pos, long long new_val) { if (tl == tr) suma[v] = new_val; else { int tm = (tl + tr) / 2; if (pos <= tm) update1(v * 2, tl, tm, pos, new_val); else update1(v * 2 + 1, tm + 1, tr, pos, new_val); suma[v] = suma[v * 2] + suma[v * 2 + 1]; } } void update2(int v, int tl, int tr, int pos, long long new_val) { if (tl == tr) sumb[v] = new_val; else { int tm = (tl + tr) / 2; if (pos <= tm) update2(v * 2, tl, tm, pos, new_val); else update2(v * 2 + 1, tm + 1, tr, pos, new_val); sumb[v] = sumb[v * 2] + sumb[v * 2 + 1]; } } int main() { scanf( %d %d %d %d %d , &n, &k, &b, &a, &q); for (int i = 0; i < n; i++) zb[i] = b; for (int i = 0; i < n; i++) za[i] = a; build1(za, 1, 0, n - 1); build2(zb, 1, 0, n - 1); for (int i = 0; i < q; i++) { scanf( %d , &t); if (t == 1) { scanf( %d %d , &d, &ai); d--; za[d] -= ai; zb[d] -= ai; if (za[d] < 0) za[d] = 0; if (zb[d] < 0) zb[d] = 0; update1(1, 0, n - 1, d, za[d]); update2(1, 0, n - 1, d, zb[d]); } else { scanf( %d , &p); p--; int size1 = p; int size2 = n - k - p; res = 0; int resa = 0, resb = 0; resa -= sum1(1, 0, n - 1, 0, size1 - 1); resa += size1 * a; resb -= sum2(1, 0, n - 1, n - size2, n - 1); resb += size2 * b; printf( %d n , resa + resb); } } }
|
#include <bits/stdc++.h> using namespace std; long long n, m; pair<long long, long long> seg[500000 + 1]; long long dp[20 + 1][500000 + 1]; signed main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); cin >> n >> m; for (long long i = 1; i < n + 1; i++) { long long l, r; cin >> l >> r; seg[i] = {l, r}; if (dp[0][l] < r) { dp[0][l] = r; } } for (long long i = 1; i < 500000 + 1; i++) { dp[0][i] = max(dp[0][i], dp[0][i - 1]); if (dp[0][i] < i) dp[0][i] = 0; } for (long long i = 1; i < 20 + 1; i++) { for (long long j = 0; j < 500000 + 1; j++) { dp[i][j] = dp[i - 1][dp[i - 1][j]]; if (dp[i][j] < j) dp[i][j] = 0; } } for (long long j = 1; j < m + 1; j++) { long long x, y; cin >> x >> y; long long ans = 0; for (long long i = 20; i >= 0; i--) { if (dp[i][x] < y and dp[i][x] != 0) { ans += (1 << i); x = dp[i][x]; } } if (dp[0][x] >= y) cout << ans + 1 << n ; else cout << -1 << n ; } }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int first = 0, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) { if (ch == - ) f = -1; } for (; isdigit(ch); ch = getchar()) { first = first * 10 + ch - 48; } return first * f; } const int mxN = 1.5e5; const int S = 26; int n, en, q, mxd, tot; int fa[mxN + 3]; char c[mxN + 3]; int sonn[mxN + 3]; int dep[mxN + 3]; int tpv[mxN + 3], btv[mxN + 3], cnt[mxN + 3][S + 3], f[mxN + 3][S + 3], g[mxN + 3]; vector<int> son[mxN + 3]; int main() { n = read(), q = read(); for (int i = 2; i <= n; i++) { scanf( %d%*c%c , &fa[i], &c[i]); sonn[fa[i]]++; c[i] = c[i] == ? ? 27 : c[i] - 96; } for (int u = 2; u <= n; u++) { dep[u] = dep[fa[u]] + 1; mxd = max(mxd, dep[u]); } for (int u = 1; u <= n; u++) if (sonn[u] == 0 && dep[u] < mxd) { for (int i = 1; i <= q; i++) puts( Fou ); return 0; } tpv[1] = 1; btv[1] = 1; for (int u = 2; u <= n; u++) { if (sonn[fa[u]] == 1) { tpv[u] = tpv[fa[u]]; } else { tpv[u] = fa[u]; } if (sonn[u] != 1) { int v = u; while (v != tpv[u]) { btv[v] = u; cnt[u][c[v]]++; v = fa[v]; } } } for (int u = n; u >= 2; u--) if (btv[u] == u) { for (int i = 1; i <= S; i++) { f[tpv[u]][i] = max(f[tpv[u]][i], f[u][i] + cnt[u][i]); } son[tpv[u]].push_back(u); } for (int u = 1; u <= n; u++) if (btv[u] == u) { for (int i = 1; i <= S; i++) g[u] += f[u][i]; if (g[u] > mxd - dep[u]) { tot++; } } while (q--) { int u; char ch, ch0; scanf( %d%*c%c , &u, &ch); ch = ch == ? ? 27 : ch - 96; ch0 = c[u]; int u0 = btv[u]; cnt[u0][ch0]--; c[u] = ch; cnt[u0][ch]++; while (1) { u0 = tpv[u0]; if (g[u0] > mxd - dep[u0]) { tot--; } if (ch0 <= S) { g[u0] -= f[u0][ch0]; } if (ch <= S) { g[u0] -= f[u0][ch]; } f[u0][ch0] = 0, f[u0][ch] = 0; for (int i = 0; i < son[u0].size(); i++) f[u0][ch0] = max(f[u0][ch0], f[son[u0][i]][ch0] + cnt[son[u0][i]][ch0]); for (int i = 0; i < son[u0].size(); i++) f[u0][ch] = max(f[u0][ch], f[son[u0][i]][ch] + cnt[son[u0][i]][ch]); if (ch0 <= S) { g[u0] += f[u0][ch0]; } if (ch <= S) { g[u0] += f[u0][ch]; } if (g[u0] > mxd - dep[u0]) { tot++; } if (u0 == 1) { break; } } if (tot) { puts( Fou ); } else { printf( Shi ); int ans = 0; for (int i = 1; i <= S; i++) ans += (f[1][i] + mxd - g[1]) * i; printf( %d n , ans); } } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: fallthrough_small_fifo.v
// Project: utils
// Description: small fifo with fallthrough i.e. data valid when rd is high
//
///////////////////////////////////////////////////////////////////////////////
module fallthrough_small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output reg empty,
input reset,
input clk
);
reg fifo_rd_en, empty_nxt;
small_fifo
#(.WIDTH (WIDTH),
.MAX_DEPTH_BITS (MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD (PROG_FULL_THRESHOLD))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.reset (reset),
.clk (clk)
);
always @(*) begin
empty_nxt = empty;
fifo_rd_en = 0;
case (empty)
1'b1: begin
if(!fifo_empty) begin
fifo_rd_en = 1;
empty_nxt = 0;
end
end
1'b0: begin
if(rd_en) begin
if(fifo_empty) begin
empty_nxt = 1;
end
else begin
fifo_rd_en = 1;
end
end
end
endcase // case(empty)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
empty <= 1'b1;
end
else begin
empty <= empty_nxt;
end
end
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && full) begin
$display("%t ERROR: Attempt to write to full FIFO: %m", $time);
end
if (rd_en && empty) begin
$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
end
end // always @ (posedge clk)
// synthesis translate_on
endmodule // fallthrough_small_fifo_v2
// synthesis translate_off
module fallthrough_small_fifo_tester();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = 0;
always #8 clk = ~clk;
fallthrough_small_fifo
#(.WIDTH (32),
.MAX_DEPTH_BITS (3),
.PROG_FULL_THRESHOLD (4))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (empty),
.reset (reset),
.clk (clk)
);
always @(posedge clk) begin
count <= count + 1;
reset <= 0;
wr_en <= 0;
rd_en <= 0;
if(count < 2) begin
reset <= 1'b1;
end
else if(count < 2 + 9) begin
wr_en <= 1;
din <= din + 1'b1;
end
else if(count < 2 + 8 + 4) begin
rd_en <= 1;
end
else if(count < 2 + 8 + 4 + 2) begin
din <= din + 1'b1;
wr_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4) begin
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
end // always @ (posedge clk)
endmodule // fallthrough_small_fifo_tester
// synthesis translate_on
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: one_hot_mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A mux module, where the output select is a one-hot bus
// Author: Dustin Richmond
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module one_hot_mux
#(parameter C_DATA_WIDTH = 1,
parameter C_SELECT_WIDTH = 2,
parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
)
(
input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
genvar i;
wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
assign ONE_HOT_OUTPUT = _rOneHotOutput;
generate
for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
end
if(C_SELECT_WIDTH == 1) begin
always @(*) begin
_rOneHotOutput = wOneHotInputs[1];
end
end else if(C_SELECT_WIDTH == 2) begin
always @(*) begin
case(ONE_HOT_SELECT)
2'b01: _rOneHotOutput = wOneHotInputs[1];
2'b10: _rOneHotOutput = wOneHotInputs[2];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 4) begin
always @(*) begin
case(ONE_HOT_SELECT)
4'b0001: _rOneHotOutput = wOneHotInputs[1];
4'b0010: _rOneHotOutput = wOneHotInputs[2];
4'b0100: _rOneHotOutput = wOneHotInputs[4];
4'b1000: _rOneHotOutput = wOneHotInputs[8];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 8) begin
always @(*) begin
case(ONE_HOT_SELECT)
8'b00000001: _rOneHotOutput = wOneHotInputs[1];
8'b00000010: _rOneHotOutput = wOneHotInputs[2];
8'b00000100: _rOneHotOutput = wOneHotInputs[4];
8'b00001000: _rOneHotOutput = wOneHotInputs[8];
8'b00010000: _rOneHotOutput = wOneHotInputs[16];
8'b00100000: _rOneHotOutput = wOneHotInputs[32];
8'b01000000: _rOneHotOutput = wOneHotInputs[64];
8'b10000000: _rOneHotOutput = wOneHotInputs[128];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 1000000000; int n, m, x, i, j, a[5050], f[5050]; int main() { scanf( %d%d , &n, &m); for (i = 3; i <= n; i++) f[i] = f[i - 1] + (i - 1) / 2; if (f[n] < m) { puts( -1 ); return 0; } for (i = 3; i <= n; i++) if (f[i] > m) break; m -= f[--i]; for (j = 1; j <= i; j++) a[j] = j; if (m > 0) { for (j = 1; j < i; j++) { x = (i + j - 1) / 2 - j + 1; if (x == m) { a[i + 1] = i + j; break; } } if (j >= i) { puts( -1~ ); return 0; } ++i; } x = a[i] + 1; for (j = 2; j <= i; j++) if (a[j] != a[j - 1] + 1) { x = a[j - 1] + 1; break; } for (++i; i <= n; ++i) { a[i] = a[i - 1] + x; if (a[i] > MX) break; } if (i <= n) { puts( -1# ); return 0; } for (i = 1; i <= n; i++) printf( %d , a[i]); return 0; }
|
`timescale 1 ns / 1 ps
module axis_pulse_height_analyzer #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter AXIS_TDATA_SIGNED = "FALSE",
parameter integer CNTR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [AXIS_TDATA_WIDTH-1:0] min_data,
input wire [AXIS_TDATA_WIDTH-1:0] max_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_data_reg[1:0], int_data_next[1:0];
reg [AXIS_TDATA_WIDTH-1:0] int_min_reg, int_min_next;
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_enbl_reg, int_enbl_next;
reg int_rising_reg, int_rising_next;
reg int_tvalid_reg, int_tvalid_next;
wire [AXIS_TDATA_WIDTH-1:0] int_tdata_wire;
wire int_mincut_wire, int_maxcut_wire, int_rising_wire, int_delay_wire;
assign int_delay_wire = int_cntr_reg < cfg_data;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign int_rising_wire = $signed(int_data_reg[1]) < $signed(s_axis_tdata);
assign int_tdata_wire = $signed(int_data_reg[0]) - $signed(int_min_reg);
assign int_mincut_wire = $signed(int_tdata_wire) > $signed(min_data);
assign int_maxcut_wire = $signed(int_data_reg[0]) < $signed(max_data);
end
else
begin : UNSIGNED
assign int_rising_wire = int_data_reg[1] < s_axis_tdata;
assign int_tdata_wire = int_data_reg[0] - int_min_reg;
assign int_mincut_wire = int_tdata_wire > min_data;
assign int_maxcut_wire = int_data_reg[0] < max_data;
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_data_reg[0] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_data_reg[1] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_min_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_rising_reg <= 1'b0;
int_tvalid_reg <= 1'b0;
end
else
begin
int_data_reg[0] <= int_data_next[0];
int_data_reg[1] <= int_data_next[1];
int_tdata_reg <= int_tdata_next;
int_min_reg <= int_min_next;
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
int_rising_reg <= int_rising_next;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_data_next[0] = int_data_reg[0];
int_data_next[1] = int_data_reg[1];
int_tdata_next = int_tdata_reg;
int_min_next = int_min_reg;
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
int_rising_next = int_rising_reg;
int_tvalid_next = int_tvalid_reg;
if(s_axis_tvalid)
begin
int_data_next[0] = s_axis_tdata;
int_data_next[1] = int_data_reg[0];
int_rising_next = int_rising_wire;
end
if(s_axis_tvalid & int_delay_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
// minimum after delay
if(s_axis_tvalid & ~int_delay_wire & ~int_rising_reg & int_rising_wire)
begin
int_min_next = int_data_reg[1];
int_enbl_next = 1'b1;
end
// maximum after minimum
if(s_axis_tvalid & int_enbl_reg & int_rising_reg & ~int_rising_wire & int_mincut_wire)
begin
int_tdata_next = int_tdata_wire;
int_tvalid_next = int_maxcut_wire;
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
assign s_axis_tready = 1'b1;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_SYMBOL_V
`define SKY130_FD_SC_HS__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_V
|
module main;
reg a, b;
triand net;
assign net = a;
assign net = b;
initial begin
a = 'b0;
b = 'b0;
#1 if (net !== 1'b0) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b0;
b = 'b1;
#1 if (net !== 1'b0) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b0;
b = 'bx;
#1 if (net !== 1'b0) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b0;
b = 'bz;
#1 if (net !== 1'b0) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b1;
b = 'b1;
#1 if (net !== 1'b1) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b1;
b = 'bx;
#1 if (net !== 1'bx) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'b1;
b = 'bz;
#1 if (net !== 1'b1) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'bx;
b = 'bx;
#1 if (net !== 1'bx) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'bx;
b = 'bz;
#1 if (net !== 1'bx) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
a = 'bz;
b = 'bz;
#1 if (net !== 1'bz) begin
$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
$finish;
end
$display("PASSED");
end
endmodule // main
|
//======================================================================
//
// vndecorrelator.v
// ----------------
// von Neumann decorrelator for bits. The module consumes bits
// and for every two bits consume will either emit zero or one bits.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module vndecorrelator(
input wire clk,
input wire reset_n,
input wire data_in,
input wire syn_in,
output wire data_out,
output wire syn_out
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 1'b0;
parameter CTRL_BITS = 1'b1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg data_in_reg;
reg data_in_we;
reg data_out_reg;
reg data_out_we;
reg syn_out_reg;
reg syn_out_new;
reg vndecorr_ctrl_reg;
reg vndecorr_ctrl_new;
reg vndecorr_ctrl_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign data_out = data_out_reg;
assign syn_out = syn_out_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
data_in_reg <= 1'b0;
data_out_reg <= 1'b0;
syn_out_reg <= 1'b0;
vndecorr_ctrl_reg <= CTRL_IDLE;
end
else
begin
syn_out_reg <= syn_out_new;
if (data_in_we)
begin
data_in_reg <= data_in;
end
if (data_out_we)
begin
data_out_reg <= data_in;
end
if (vndecorr_ctrl_we)
begin
vndecorr_ctrl_reg <= vndecorr_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// vndecorr_logic
//
// The logic implementing the von Neumann decorrelator by waiting
// for subsequent bits and comparing them to determine if both
// bits should just be discarded or one of them also emitted.
//----------------------------------------------------------------
always @*
begin : vndecorr_logic
data_in_we = 1'b0;
data_out_we = 1'b0;
syn_out_new = 1'b0;
vndecorr_ctrl_new = CTRL_IDLE;
vndecorr_ctrl_we = 1'b0;
case (vndecorr_ctrl_reg)
CTRL_IDLE:
begin
if (syn_in)
begin
data_in_we = 1'b1;
vndecorr_ctrl_new = CTRL_BITS;
vndecorr_ctrl_we = 1'b1;
end
end
CTRL_BITS:
begin
if (syn_in)
begin
if (data_in != data_in_reg)
begin
data_out_we = 1'b1;
syn_out_new = 1'b1;
end
vndecorr_ctrl_new = CTRL_IDLE;
vndecorr_ctrl_we = 1'b1;
end
end
endcase // case (vndecorr_ctrl_reg)
end // vndecorr_logic
endmodule // vndecorrelator
//======================================================================
// EOF vndecorrelator.v
//======================================================================
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
* Copyright (C) 2018 David Shah <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N + 1) / 2) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH2-1:0] FCO, Y1;
genvar i;
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2C #(
.INIT0(16'b1001011010101010),
.INIT1(16'b1001011010101010),
.INJECT1_0("NO"),
.INJECT1_1("NO")
) ccu2c_i (
.CIN(C[i]),
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
.S0(Y[i]), .S1(Y1[i]),
.COUT(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
assign CO[i+1] = FCO[i];
assign Y[i+1] = Y1[i];
end
end endgenerate
assign X = AA ^ BB;
endmodule
|
module Control_tb ();
reg irq, PC31;
reg [5:0] OpCode, Funct;
wire [2:0] PCSrc;
wire [1:0] RegDst, MemtoReg;
wire [5:0] ALUFun;
wire RegWrite, ALUSrc1, ALUSrc2, Branch,
MemWrite, MemRead, ExtOp, LuOp, Sign, Jump;
Control con(
.irq(irq), .PC31(PC31),
.OpCode(OpCode), .Funct(Funct), .PCSrc(PCSrc),
.RegDst(RegDst), .MemtoReg(MemtoReg), .RegWrite(RegWrite),
.ALUSrc1(ALUSrc1), .ALUSrc2(ALUSrc2), .Branch(Branch),
.MemWrite(MemWrite), .MemRead(MemRead), .ExtOp(ExtOp),
.LuOp(LuOp), .Sign(Sign), .ALUFun(ALUFun), .Jump(Jump)
);
initial begin
irq = 1;
PC31 = 0;
OpCode = 6'h23;
Funct = 6'h3f;
#5 irq = 0;
OpCode = 6'h3f;
Funct = 6'h3f;
#5 OpCode = 6'h23;
#5 OpCode = 6'h2b;
#5 OpCode = 6'hf;
#5 OpCode = 6'h0;
Funct = 6'h20;
#5 Funct = 6'h21;
#5 Funct = 6'h22;
#5 Funct = 6'h23;
#5 OpCode = 6'h8;
#5 OpCode = 6'h9;
#5 OpCode = 6'h0;
Funct = 6'h24;
#5 Funct = 6'h25;
#5 Funct = 6'h26;
#5 Funct = 6'h27;
#5 OpCode = 6'hc;
#5 OpCode = 6'hd;
#5 OpCode = 6'h0;
Funct = 6'h0;
#5 Funct = 6'h2;
#5 Funct = 6'h3;
#5 Funct = 6'h2a;
#5 Funct = 6'h2b;
#5 OpCode = 6'ha;
#5 OpCode = 6'hb;
#5 OpCode = 6'h4;
#5 OpCode = 6'h5;
#5 OpCode = 6'h6;
#5 OpCode = 6'h7;
#5 OpCode = 6'h1;
#5 OpCode = 6'h2;
#5 OpCode = 6'h3;
#5 OpCode = 6'h0;
Funct = 6'h8;
#5 Funct = 6'h9;
end
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 13: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 13: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 24: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[13 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[24 : 22]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[21 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
//
// $Date: 2005/02/27 09:26:24 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_top.v,v $
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`timescale 1ns / 100ps
// synopsys translate_on
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b1; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
wire wb_cyc_i = wb_stb_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Antenna { int iniLeft, iniRight; }; int main() { ios::sync_with_stdio(false); cin.tie(0); int nbAntennas, totLen; cin >> nbAntennas >> totLen; vector<Antenna> ants(nbAntennas); for (int iAnt = 0; iAnt < nbAntennas; ++iAnt) { int center, iniScope; cin >> center >> iniScope; ants[iAnt].iniLeft = max(0, center - iniScope); ants[iAnt].iniRight = min(totLen, center + iniScope); } vector<int> minCost(totLen + 1); minCost[totLen] = 0; for (int pos = totLen - 1; pos >= 0; --pos) { minCost[pos] = (totLen - pos); for (int iAnt = 0; iAnt < nbAntennas; ++iAnt) { int left = ants[iAnt].iniLeft, right = ants[iAnt].iniRight; if (left <= pos + 1 && pos + 1 <= right) { minCost[pos] = minCost[pos + 1]; break; } if (pos < left) { int accessCost = (left - pos - 1); int nextPos = min(totLen, right + accessCost); minCost[pos] = min(minCost[pos], accessCost + minCost[nextPos]); } } } cout << minCost[0] << n ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; long long power(long long a, long long b, long long md) { return (!b ? 1 : (b & 1 ? a * power(a * a % md, b / 2, md) % md : power(a * a % md, b / 2, md) % md)); } const int xn = 1e3 + 10; const int xm = 2e4 + 10; const int sq = 300; const int inf = 1e9 + 10; const long long INF = 1e18 + 10; const int mod = 1e6 + 7; const int base = 257; const int SIG = 26; int n, k, tb[1 << 20], dp[xn][xm], ptr, a[xm], C[xm][SIG], ans = inf; string S; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> S >> k, n = int(S.size()); if (k == 1) { ans = 0; for (int i = 0; i < n; ++i) ans += (S[i] == 1 ); return cout << ans << n , 0; } for (int mask = 0; mask < (1 << k); ++mask) { bool flag = true; for (int i = 0; i < k; ++i) flag &= (!((mask & (1 << i))) | !(mask & (1 << (i + 1)))); flag &= !(mask & 1), flag &= !(mask & 2); if (flag) tb[mask] = ptr, a[ptr++] = mask; } for (int t = 0; t < ptr; ++t) { int mask = a[t] + 1; for (int i = 2; i < 10; ++i) { for (int bit = i; bit <= k; ++bit) if ((mask & (1 << (bit - i)))) C[t][i] += (1 << bit); bool flag = !(C[t][i] & (1 << k)); for (int j = 1; j < k; ++j) if (k % j == 0) flag |= (C[t][i] & (1 << j)); for (int b1 = 2; b1 < k; ++b1) for (int b2 = b1 + 1; b2 <= k; ++b2) if ((C[t][i] & (1 << b1)) && (C[t][i] & (1 << b2))) flag |= (k % (b2 - b1) == 0); C[t][i] = (C[t][i] & (C[t][i] ^ (1 << k))); if (!flag) C[t][i] = -1; } } for (int i = 0; i < xn; ++i) for (int j = 0; j < ptr; ++j) dp[i][j] = inf; dp[0][0] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < ptr; ++j) { int mask = a[j]; if (S[i] == 1 ) dp[i + 1][0] = min(dp[i + 1][0], dp[i][j]); else { dp[i + 1][j] = min(dp[i + 1][j], dp[i][j] + 1); int x = C[j][S[i] - 0 ]; if (x != -1) dp[i + 1][tb[x]] = min(dp[i + 1][tb[x]], dp[i][j]); } } } for (int i = 0; i < ptr; ++i) ans = min(ans, dp[n][i]); cout << ans << n ; return 0; }
|
module control (
input [5:0] op,
output [2:0] alu_op,
output regDst0, regDst1, aluSrc, memToReg0, memToReg1, regWrite,
output memRead, memWrite, branch, branch_ne, jump
);
reg addi, andi, lw, sw, ori, beq, bne, j, jal, slti, r_format, x_found;
always @(*) begin
addi <= 1'b0;
lw <= 1'b0;
sw <= 1'b0;
ori <= 1'b0;
beq <= 1'b0;
bne <= 1'b0;
j <= 1'b0;
jal <= 1'b0;
andi <= 1'b0;
ori <= 1'b0;
r_format <= 1'b0;
x_found <= 1'b0;
case (op)
6'dx : x_found <= 1'b1;
6'b001000 : addi <= 1'b1;
6'b100011 : lw <= 1'b1;
6'b101011 : sw <= 1'b1;
6'b000100 : beq <= 1'b1;
6'b000101 : bne <= 1'b1;
6'b000010 : j <= 1'b1;
6'b000011 : jal <= 1'b1;
6'b001010 : slti <= 1'b1;
6'b000000 : r_format <= 1'b1;
6'b001100 : andi <= 1'b1;
6'b001101 : ori <= 1'b1;
6'b001000 : andi <= 1'b1;
endcase
end
assign regDst0 = r_format & (~x_found);
assign regDst1 = jal & (~x_found);
assign aluSrc = (lw | sw | andi | ori | addi) & (~x_found);
assign memToReg0 = lw & (~x_found);
assign memToReg1 = jal & (~x_found);
assign regWrite = (r_format | lw | andi | ori | addi | jal) & (~x_found);
assign memRead = lw & (~x_found);
assign memWrite = sw & (~x_found);
assign branch = (beq) & (~x_found);
assign branch_ne = (bne) & (~x_found);
assign jump = (j | jal) & (~x_found);
assign alu_op[0] = (beq | bne | andi) & (~x_found);
assign alu_op[1] = (r_format | andi) & (~x_found);
assign alu_op[2] = ori & (~x_found);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:23:45 11/28/2017
// Design Name:
// Module Name: bram_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bram_controller(clk, reset, btn, wea, addra);
input wire clk, reset, btn;
output reg wea;
output reg [3:0] addra;
localparam [1:0]
idle = 2'b00,
leer = 2'b01,
fin = 2'b10;
reg [1:0] state_reg;
reg [3:0] counter;
always@(posedge clk, posedge reset)
if(reset)
begin
addra<=0;
counter<=0;
state_reg<=idle;
wea<=0;
end
else begin
case(state_reg)
idle:
if(btn==1'b1)begin
state_reg<=leer;
end
leer:
begin
wea<=0;
counter<=counter+1'b1;
state_reg<=fin;
end
fin:begin
addra<=addra+1'b1;
if(counter==4'b1111)begin
counter<=0;
end
state_reg<=idle;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, sum = 0, curr = 0, j = 0; vector<long long int> a(100000), res; cin >> n >> k; for (long long int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } if (sum % k) { cout << No ; } else { for (long long int i = 0; i < n; i++) { curr += a[i]; if (curr == sum / k) { res.push_back(i + 1 - j); j = i + 1; curr = 0; } } if (res.size() == k) { cout << Yes << endl; for (long long int i = 0; i < k; i++) { cout << res[i] << ; } } else cout << No ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 RNG(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> T ceil(T a, T b) { return (a + b - 1) / b; } template <typename T> T binpow(T a, T b) { T res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } void solve() { long long n, c = 0; string s, t; cin >> n; cin >> s >> t; if (n == 1) { if (s == t) { cout << 0; } else { cout << 1; } return; } vector<long long> a, b; for (long long i = 1; i < n; i++) { if (s[i] != t[i] && s[i - 1] != t[i - 1]) { pair<char, char> a, b; a = {s[i], t[i]}; b = {s[i - 1], t[i - 1]}; if (a != b) { swap(s[i - 1], s[i]); c++; } } } for (long long i = 0; i < n; i++) { c += (s[i] != t[i]); } cout << c << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); long long t = 1; for (long long i = 1; i < t + 1; i++) { solve(); } cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> com; vector<int> num; vector<string> adj[1000010]; struct node { string s; int i; node() {} node(string x, int idx) { s = x; i = idx; } }; int toNum(string s) { int i, j, k; int l = s.length(); k = 1; j = 0; for (i = l - 1; i >= 0; i--) { j += (s[i] - 48) * k; k *= 10; } return j; } int jdx, sz; void solve(node x, int lvl) { if (lvl >= 0) adj[lvl].push_back(x.s); if (lvl >= 0 && num[x.i] == 0) return; while (jdx < sz) { if (lvl == -1) { node temp = node(com[jdx], jdx); jdx++; solve(temp, lvl + 1); } else { while (num[x.i] > 0) { num[x.i]--; node temp = node(com[jdx], jdx); jdx++; solve(temp, lvl + 1); } if (!num[x.i]) return; } } } int main() { int i, j, k; int n, m; string s, t; cin >> s; t = ; n = s.length(); for (i = 0; i < n; i++) { if (s[i] == , ) { if (isdigit(t[0])) num.push_back(toNum(t)); else com.push_back(t); t = ; } else { t += s[i]; } } num.push_back(toNum(t)); jdx = 0; sz = com.size(); node r = node( root , -1); solve(r, -1); k = 0; for (i = 0; i < 1000010; i++) { if (adj[i].size() > 0) k++; else break; } printf( %d n , k); for (i = 0; i < k; i++) { m = adj[i].size(); for (j = 0; j < m; j++) cout << adj[i][j] << ; printf( n ); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] a = crc[7:0];
wire [7:0] b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.a (a[7:0]),
.b (b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, a, b
);
input clk;
input [7:0] a;
input [7:0] b;
output reg [63:0] out;
and u0[7:0] (out[7:0], a[7:0], b[7:0]);
and u1[7:0] (out[15:8], a[0], b[7:0]);
and u2[7:0] (out[23:16], a[0], b[0]);
nand u3[7:0] (out[31:24], a[0], b[7:0]);
or u4[7:0] (out[39:32], a[0], b[7:0]);
nor u5[7:0] (out[47:40], a[0], b[7:0]);
xor u6[7:0] (out[55:48], a[0], b[7:0]);
xnor u7[7:0] (out[63:56], a[0], b[7:0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int n; int b[MAXN]; set<pair<int, int>, greater<pair<int, int> > > s; int ans[MAXN]; int main() { scanf( %d , &n); for (auto i = 0; i != n; i++) scanf( %d , &b[i]); for (auto i = 0; i != n; i++) { int j = (i + 1) % n; int delta = abs(n - b[i] - b[j]); s.insert(make_pair(delta, i)); } int l = 0, r = n - 1; while (!s.empty()) { int pos = s.begin()->second; s.erase(s.begin()); int j = (pos + 1) % n; if (n - b[pos] > b[j]) { ans[pos] = l++; } else { ans[pos] = r--; } } for (auto i = 0; i != n; i++) printf( %d , ans[i]); }
|
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