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// FSM of Power Gating Process
`include "globalVariable.v"
module fsmPG (clk, reset, portType, portLoad, pgEnable, inPG, inWU, portStatus, outPG, outWU);
input clk, reset, portType, pgEnable, inPG, inWU;
input [`PG_PORT_LOAD_SIZE-1:0] portLoad;
output reg [`PORT_STAT_SIZE-1:0] portStatus;
output reg outPG;
output reg outWU;
wire [5:0] control;
reg [4:0] delay;
assign control [0] = (portType == `PERMANENT) ? 1 : 0; // Warning V318 can be ignored.
assign control [1] = (portLoad < `PG_THRESHOLD_PORT) ? 1 : 0; // Warning V318 can be ignored.
assign control [2] = inPG;
assign control [3] = (delay == 0) ? 1 : 0; // Warning V318 can be ignored.
assign control [4] = inWU;
assign control [5] = pgEnable;
always @ (portStatus or delay) begin
case (portStatus)
`ACTIVE:
; // no operation
`WAIT_PG_HIGH:
outPG = 1'b1;
`INACTIVE:
delay = `WAKE_UP_DELAY;
`WAKE_UP_TX: begin
outWU = 1'b1;
delay = delay - 1;
end
`WAKE_UP_RX:
delay = delay - 1;
`WAIT_PG_LOW: begin
outPG = 1'b0;
outWU = 1'b0;
end
`WAIT_WU_LOW:
outPG = 1'b0;
default: begin
outPG = 1'b0;
outWU = 1'b0;
end
endcase
end
always @ (posedge clk or negedge reset) begin
if (~reset)
portStatus = `ACTIVE;
else begin
case (portStatus)
`ACTIVE:
if (control[0]==0 && control[1]==1 && control[5]==1) portStatus = `WAIT_PG_HIGH;
`WAIT_PG_HIGH:
if (control[2]==1) portStatus = `INACTIVE;
`INACTIVE: begin
if ((control[0]==1 && control[5]==1) | (control[1]==0 && control[5]==1)) portStatus = `WAKE_UP_TX;
else if (control[4] == 1) portStatus = `WAKE_UP_RX;
end
`WAKE_UP_TX:
if (control[3]==1) portStatus = `WAIT_PG_LOW;
`WAKE_UP_RX:
if (control[3]==1) portStatus = `WAIT_WU_LOW;
`WAIT_PG_LOW:
if (control[2]==0) portStatus = `ACTIVE;
`WAIT_WU_LOW:
if (control[4]==0) portStatus = `ACTIVE;
default:
portStatus = `ACTIVE;
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int s, v1, v2, t1, t2, i1, i2; cin >> s >> v1 >> v2 >> t1 >> t2; i1 = s * v1 + 2 * t1; i2 = s * v2 + 2 * t2; if (i1 < i2) cout << First ; else if (i1 > i2) cout << Second ; else cout << Friendship ; }
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#include <bits/stdc++.h> using namespace std; int main() { int m, n, i, j, k, a, b; scanf( %d , &a); if (a == 1) printf( 1 n ); else { printf( %d n , (a - 1) * a / 2 * 12 + 1); } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; const long long INF64 = 1000000000000000007; int n; int p[17]{2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59}; int a[105]; int number[60]; int dp[105][1 << 17]; int pred[105][1 << 17]; void find_pred(int x, int p) { if (x == n) return; cout << pred[x][p] << ; find_pred(x + 1, p | number[pred[x][p]]); } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 2; i < 60; i++) { for (int j = 0; j < 17; j++) { if (i % p[j] == 0) { number[i] |= (1 << j); } } } for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < (1 << 17); j++) { dp[i][j] = INF; for (int k = 1; k < 60; k++) { if (!(j & number[k])) { int w = dp[i + 1][j | number[k]] + abs(k - a[i]); if (dp[i][j] > w) { dp[i][j] = w; pred[i][j] = k; } } } } } find_pred(0, 0); return 0; }
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#include <bits/stdc++.h> using namespace std; int Szukaj(vector<int>& moje, vector<bool>& jest, int x) { int nr = -1; for (int i = 0; i < moje.size(); ++i) { if (moje[i] >= x && jest[i]) { if (nr == -1) nr = i; else { if (moje[i] < moje[nr]) nr = i; } } } return nr; } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; vector<int> atk, def; for (int i = 0; i < n; ++i) { string op; int s; cin >> op >> s; if (op == ATK ) atk.push_back(s); else def.push_back(s); } vector<int> moje(m); for (int i = 0; i < m; ++i) cin >> moje[i]; int odp = 0; sort(atk.begin(), atk.end()); sort(moje.begin(), moje.end()); reverse(moje.begin(), moje.end()); for (int i = 1; i <= min(atk.size(), moje.size()); ++i) { vector<int> a, b; for (int j = 0; j < i; ++j) a.push_back(moje[j]); for (int j = i - 1; j >= 0; --j) b.push_back(atk[j]); int s = 0; bool ok = true; for (int j = 0; j < i; ++j) { if (a[j] >= b[j]) s += a[j] - b[j]; else ok = false; } if (ok) odp = max(odp, s); } bool ok = true; int s = 0; vector<bool> jest(moje.size(), true); sort(def.begin(), def.end()); for (int i = 0; i < def.size(); ++i) { int nr = Szukaj(moje, jest, def[i] + 1); if (nr != -1) jest[nr] = false; else ok = false; } for (int i = 0; i < atk.size(); ++i) { int nr = Szukaj(moje, jest, atk[i]); if (nr != -1) { jest[nr] = false; s += moje[nr] - atk[i]; } else ok = false; } for (int i = 0; i < moje.size(); ++i) if (jest[i]) s += moje[i]; if (ok) odp = max(odp, s); cout << odp; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:07:34 02/15/2017
// Design Name:
// Module Name: car_detector
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module car_detector(
input wire clk, res,
input wire sensorA,
input wire sensorB,
output wire [3:0] car_count
);
localparam abUnblocked=2'b00, aBlocked=2'b01, abBlocked=2'b10, bBlocked=2'b11;
reg [1:0] current_state;
reg increase, decrease;
reg [3:0] count = 0;
//initialize all necessary values
initial begin
increase = 0;
decrease = 0;
current_state = 0;
end
// State register logic
always@(posedge clk, posedge res) begin
if (res)
current_state <= abUnblocked;
else
begin
increase <= 0;
decrease <= 0;
case(current_state)
abUnblocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked; //stay
end
aBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked; //stay
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
decrease <= 1; //finished exiting
end
abBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked; //stay
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
bBlocked: if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
increase <= 1;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked; //stay
end
default: current_state <= abUnblocked;
endcase
if(increase)
count <= count + 1'b1; //increment the total counter
else if(decrease)
count <= count - 1'b1; //decrement the total counter
end //end else
end //end always
assign car_count = count;
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_static_cmdgen.v
// Version : v1.0
// Description: Rd/wr command generator
// various features/status of the core.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_static_cmdgen
# (
parameter C_ATG_STATIC_ADDRESS = 32'h12A0_0000,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_MIF_ADDR_BITS = 4 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_STATIC_LENGTH = 3,
parameter C_ATG_SYSTEM_INIT = 0,
parameter C_ATG_SYSTEM_TEST = 0
) (
input Clk ,
input rst_l ,
input static_ctl_en ,
input [7:0] static_len ,
input [9:0] rom_addr_ptr_ff,
input [31:0] rom_addr ,
input [31:0] rom_data ,
output [127:0] cmd_out_mw ,
output [C_M_AXI_DATA_WIDTH-1:0] cmd_data ,
output [127:0] cmd_out_mr
);
wire [2:0] size;
generate if(C_M_AXI_DATA_WIDTH == 32 ) begin : M_SISE32
assign size = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64 ) begin : M_SISE64
assign size = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128 ) begin : M_SISE128
assign size = 3'b100;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256 ) begin : M_SISE256
assign size = 3'b101;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512 ) begin : M_SISE512
assign size = 3'b110;
end
endgenerate
wire [5:0] id = 6'h0;
wire [1:0] burst = 2'b01;
reg [7:0] len = 8'h0;
always @(posedge Clk) begin
len[7:0] <= (rst_l) ? static_len[7:0] : C_ATG_STATIC_LENGTH;
end
//
//Static-mode
//
generate if(C_ATG_SYSTEM_INIT == 0 &&
C_ATG_SYSTEM_TEST == 0 ) begin : STATIC_MODE_ON
assign cmd_out_mw = {
32'h0,
32'h0,
static_ctl_en,7'h0,3'b010,id,size,burst,2'b00,len,
C_ATG_STATIC_ADDRESS
};
assign cmd_out_mr = {
32'h0,
32'h0,
static_ctl_en,7'h0,3'b010,id,size,burst,2'b00,len,
C_ATG_STATIC_ADDRESS
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = {
64'hCAFE5AFE_C001CAFE,
64'hCAFE1AFE_C001DAFE,
64'hCAFE2AFE_C001EAFE,
64'hCAFE3AFE_C001FAFE
};
end
endgenerate
wire system_init_en;
wire system_init_cnt_en;
wire system_init_cmd_en;
// disable when no.of commands count reached Maximum limit(16)
assign system_init_cnt_en = (rom_addr_ptr_ff[C_ATG_MIF_ADDR_BITS] != 1'b1);
// disable when command has cmd-valid bit set to 0
assign system_init_cmd_en = ~(&rom_addr); // All 1's is NOP OPCODE.
assign system_init_en = system_init_cnt_en && system_init_cmd_en;
generate if(C_ATG_SYSTEM_INIT == 1 || C_ATG_SYSTEM_TEST == 1 ) begin : SYSTEM_INIT_TEST_MODE_ON
assign cmd_out_mw = {
32'h0,
32'h0,
system_init_en,7'h0,3'b010,id,size,burst,2'b00,8'h0,
rom_addr[31:0]
};
assign cmd_data[C_M_AXI_DATA_WIDTH-1:0] = rom_data[31:0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void check_max(T& a, T b) { if (a < b) a = b; } template <class T> void check_min(T& a, T b) { if (a > b) a = b; } const int MAXN = 10100; int n, k; double per; double a[MAXN]; int main() { cin >> n >> k; per = (double)k / 100; for (int _t = n, i = 0; i < _t; i++) cin >> a[i]; sort(a, a + n); double l = 0, r = 1000; while (r - l > 1e-8) { double m = (r + l) / 2; double more = 0, less = 0; for (int _t = n, i = 0; i < _t; i++) if (a[i] > m) more += a[i] - m; else less += m - a[i]; if (more * (1 - per) >= less) l = m; else r = m; } double ans = (l + r) / 2; printf( %.7lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, nn = 0, pp = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); if (x < 0) nn++; else if (x > 0) pp++; } if (nn >= n / 2 + n % 2) printf( -1 ); else if (pp >= n / 2 + n % 2) printf( 1 ); else printf( 0 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2E5 + 77; void putint(int x) { static bool first = true; if (first) { printf( %d , x); first = false; } else printf( %d , x); } struct QUERY { int t, r; } Q[maxn]; int cnt = 0; int N, M, A[maxn], B[maxn], pb = 0; int main() { scanf( %d%d , &N, &M); for (int i = 0; i < N; ++i) scanf( %d , A + i); for (int i = 0; i < M; ++i) { int t, r; scanf( %d%d , &t, &r); while (cnt && r >= Q[cnt - 1].r) --cnt; if (!cnt || t != Q[cnt - 1].t) Q[cnt++] = (QUERY){t, r}; } Q[cnt] = (QUERY){0, 0}; sort(A, A + Q[0].r); int ptr[2] = {0, Q[0].r - 1}, d = Q[0].t == 1; for (int i = 0; i < cnt; ++i) { for (int j = Q[i].r; j > Q[i + 1].r; --j) { B[pb++] = A[ptr[d]]; ptr[d] += d ? -1 : 1; } d ^= 1; } for (int i = Q[0].r - 1; i >= 0; --i) putint(B[i]); for (int i = Q[0].r; i < N; ++i) putint(A[i]); printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, l, m, n; int a[1001]; char s[1000], c; while (scanf( %d%d , &n, &m) != EOF) { memset(a, 0, sizeof(a)); while (m--) { scanf( %s , s); scanf( %s , s); scanf( %s , s); c = s[0]; scanf( %s , s); scanf( %d , &k); if (c == r ) { for (i = 1; i <= k; i++) a[i] = 1; } else { for (i = k; i <= n; i++) a[i] = 1; } } k = 0; for (i = 1; i <= n; i++) if (a[i] == 0) k++; if (k == 0) printf( -1 n ); else printf( %d n , k); } }
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#include<bits/stdc++.h> using namespace std; #define FIO ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0) mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); #define endl n #define mp make_pair #define pb push_back #define ins insert #define lb lower_bound #define ub upper_bound #define ff first #define ss second #define sz(x) (ll)(x).size() #define vi vector<int> #define mt make_tuple #define mii map<int,int> #define um unordered_map<int,int> #define pii pair<int,int> #define maxpq priority_queue<int> #define minpq priority_queue<int,vi,greater<int>> #define setbits(x) __builtin_popcountll(x) #define ps(x,y) fixed<<setprecision(y)<<x #define all(x) x.begin(), x.end() #define allr(x) rbegin(x), rend(x) #define w(x) int x; cin>>x; while(x--) #define goog(tno) cout << Case # << tno << : #define trace(x) cerr<<#x<< : <<x<< <<endl; typedef long double ld; #define ll long long int #define ull unsigned ll const int MOD = 1000000007; const ll INF = 1e18; const ld pi =3.14159265359; // const int mod = 1000003; template <class T> ll maxpower(T a , T b){ll ans = 0;while(a > 0 && a % b == 0){ans++;a /= b;}return ans;} template <class T> T mceil(T a, T b){if(a % b == 0) return a/b; else return a/b + 1;} //--------------------------------------------------------------------------- // cin>> vector<T> template <class T> istream &operator>>(istream &in, vector<T> &a){for (auto &i : a)cin >> i;return in;} // cout << vector<T> template <class T> ostream &operator<<(ostream &ostream, const vector<T> &c){for (auto &it : c) cout << it << ;return ostream;} //--------------------------------------------------------------------------- void __print(int x) {cerr << x;} void __print(long x) {cerr << x;} void __print(long long x) {cerr << x;} void __print(unsigned x) {cerr << x;} void __print(unsigned long x) {cerr << x;} void __print(unsigned long long x) {cerr << x;} void __print(float x) {cerr << x;} void __print(double x) {cerr << x;} void __print(long double x) {cerr << x;} void __print(char x) {cerr << << x << ;} void __print(const char *x) {cerr << << x << ;} void __print(const string &x) {cerr << << x << ;} void __print(bool x) {cerr << (x ? true : false );} template<typename T, typename V> void __print(const pair<T, V> &x) {cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ;} template<typename T> void __print(const T &x) {int f = 0; cerr << { ; for (auto &i: x) cerr << (f++ ? , : ), __print(i); cerr << } ;} void _print() {cerr << ] n ;} template <typename T, typename... V> void _print(T t, V... v) {__print(t); if (sizeof...(v)) cerr << , ; _print(v...);} #ifndef ONLINE_JUDGE #define debug(x...) cerr << [ << #x << ] = [ ; _print(x) #else #define debug(x...) #endif int main(){ FIO; w(t){ ll n; cin>>n; ll sum = 0; for(ll i=0;i<n;i++){ ll x; cin>>x; sum += x; } cout<<sum%n*(n-sum%n)<<endl; } }
|
// -*- Verilog -*-
//====================================================================
// DESCRIPTION: Manual test case showing use of AUTOASCII
//
// Copyright 2001-2010 by Wilson Snyder. This program is free software;
// you can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
//====================================================================
`include "vregs_spec_defs.v"
module vregs_enums (/*AUTOARG*/);
`include "vregs_spec_param.v"
reg [3:0] // synopsys enum En_ExEnum
m_exenum_r;
/*AUTOASCIIENUM("m_exenum_r", "m_exenum_r_ascii", "EP_ExEnum_")*/
// Beginning of automatic ASCII enum decoding
reg [63:0] m_exenum_r_ascii; // Decode of m_exenum_r
always @(m_exenum_r) begin
case ({m_exenum_r})
EP_ExEnum_ONE: m_exenum_r_ascii = "one ";
EP_ExEnum_TWO: m_exenum_r_ascii = "two ";
EP_ExEnum_FIVE: m_exenum_r_ascii = "five ";
EP_ExEnum_FOURTEEN: m_exenum_r_ascii = "fourteen";
default: m_exenum_r_ascii = "%Error ";
endcase
end
// End of automatics
// ****************************************************************
// surefire lint_off STMINI
initial begin
m_exenum_r = EP_ExEnum_FIVE;
$write("State = %x = %s\n", m_exenum_r, m_exenum_r_ascii);
end
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant: t
// verilog-library-directories:("." "../test_dir")
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// compile-command: "vlint --brief +incdir+../test_dir vregs_enums.v"
// End:
|
#include <bits/stdc++.h> using namespace std; bool vis[100006]; int main() { int n, k; while (cin >> n >> k) { memset(vis, false, sizeof(vis)); int st = 1, ed = 1 + k; int cnt = 0; while (cnt < k && st <= ed) { if (st != ed) vis[st] = vis[ed] = true, cout << st << << ed << ; else vis[st] = true, cout << st << ; st++, ed--; cnt++; } for (int i = 1; i <= n; i++) { if (!vis[i]) cout << i << ; } puts( ); } return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcomms6_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if ((spi_count == 6'd16) && (spi_csn[2] == 1'b1)) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "../vtr/full-adder/adder.sim.v"
module MULTIPLE_INSTANCE (a, b, c, d, cin, cout, sum);
localparam DATA_WIDTH = 4;
input wire [DATA_WIDTH-1:0] a;
input wire [DATA_WIDTH-1:0] b;
input wire [DATA_WIDTH-1:0] c;
input wire [DATA_WIDTH-1:0] d;
output wire [DATA_WIDTH*2-1:0] sum;
input wire [DATA_WIDTH-1:0] cin;
output wire [DATA_WIDTH-1:0] cout;
wire [DATA_WIDTH-1:0] a2b;
genvar i;
/* n = 0..DATA_WIDTH
*
* cin[n]
* ↓
* a[n] + b[n] → sum[n]
* ↓
* c[n] + d[n] → sum[4+n]
* ↓
* cout[n]
*/
for(i=0; i<DATA_WIDTH; i=i+1) begin
ADDER comb_apb (.a(a[i]), .b(b[i]), .cin(cin[i]), .cout(a2b[i]), .sum(sum[i]));
ADDER comb_cpd (.a(c[i]), .b(d[i]), .cin(a2b[i]), .cout(cout[i]), .sum(sum[DATA_WIDTH+i]));
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int a[maxn]; int n, x, k; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> x >> k; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0; for (int i = 0; i < n; i++) { long long l = (a[i] - 1) / x; long long r = l + k; ans += (long long)(lower_bound(a, a + n, (r + 1) * x) - lower_bound(a, a + n, max(r * x, (long long)a[i]))); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; const long long INF = 1e18; inline int abs(int x) { return x > 0 ? x : -x; } inline long long sqr(long long x) { return x * x; } bool cmp(pair<int, int>& x, pair<int, int>& y) { return x.first < y.first; } int n; pair<int, int> p[N]; long long minY[N + 1][2], maxY[N + 1][2]; bool check(long long d) { long long dY, sqrX, sqrY; int l = 0, r = 0; while (r < n) { while (r < n && sqr((long long)p[r].first - p[l].first) <= d) { sqrX = max(sqr((long long)p[r].first), sqr((long long)p[l].first)); sqrY = max(max(sqr(maxY[l][0]), sqr(maxY[n - r - 1][1])), max(sqr(minY[l][0]), sqr(minY[n - r - 1][1]))); dY = sqr(max(maxY[l][0], maxY[n - r - 1][1]) - min(minY[n - r - 1][1], minY[l][0])); if (max(dY, sqrX + sqrY) <= d) { if (d < 400) { } return true; } ++r; } while (r < n && l <= r && sqr((long long)p[r].first - p[l].first) > d) ++l; } return false; } long long solve() { sort(p, p + n, cmp); maxY[0][0] = maxY[0][1] = -INF; minY[0][0] = minY[0][1] = INF; for (int i = 1; i <= n; ++i) { maxY[i][0] = max(maxY[i - 1][0], (long long)p[i - 1].second); maxY[i][1] = max(maxY[i - 1][1], (long long)p[n - i].second); minY[i][0] = min(minY[i - 1][0], (long long)p[i - 1].second); minY[i][1] = min(minY[i - 1][1], (long long)p[n - i].second); } long long l = 0, r = INF, m; while (l < r) { m = (l + r) / 2; if (check(m)) r = m; else l = m + 1; } return min(l, sqr((long long)p[n - 1].first - p[0].first)); } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d%d , &p[i].first, &p[i].second); long long ans = solve(); for (int i = 0; i < n; ++i) swap(p[i].first, p[i].second); ans = min(ans, solve()); printf( %I64d , ans); }
|
#include <bits/stdc++.h> using namespace std; int cnt[26]; bool work() { char ch; while (isalpha(ch = getchar())) ++cnt[ch - a ]; int c = 0; for (int x = 0; x < 26; ++x) if (cnt[x] & 1) ++c; return c == 0 || (c & 1); } int main() { puts(work() ? First : Second ); }
|
#include <bits/stdc++.h> using namespace std; int main() { int b, h, a; long long int count = 0; cin >> b >> h; for (int i = h - 1; i >= 0; i = i - 2) { for (int j = b - 1; j >= 0; j = j - 2) { a = j * i; count += a; } } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; if (k < n / 2) { cout << -1; return 0; } if (n == 1) { if (k) cout << -1; else cout << 1; return 0; } int x = k - (n - 2) / 2; cout << x << << 2 * x << ; for (int i = 2, j = 2 * x + 1; i < n; i++, j++) cout << j << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 1000010; int n, cnt[N], ans, val[N]; long long a[N]; template <typename T> void gi(T &x) { x = 0; register char c = getchar(), pre = 0; for (; c < 0 || c > 9 ; pre = c, c = getchar()) ; for (; c >= 0 && c <= 9 ; c = getchar()) x = x * 10ll + (c ^ 48); if (pre == - ) x = -x; } int main() { gi(n); for (int i = (1); i <= (n); i++) { gi(a[i]); long long t = a[i]; int w = 0; for (; t % 2 == 0; t /= 2, ++w) ; ++cnt[w], val[i] = w; } for (int i = (1); i <= (70); i++) if (cnt[i] > cnt[ans]) ans = i; printf( %d n , n - cnt[ans]); for (int i = (1); i <= (n); i++) if (val[i] != ans) printf( %lld , a[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int x, y, a, b, c; cin >> x >> y >> a >> b >> c; long long int t = a * 2; long long int r = c * 3; cout << max(t + b - x, 0ll) + max(r + b - y, 0ll); return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp, x[1000005]; int main() { int t1; cin >> t1; while (t1--) { string s, t; cin >> s >> t; mp.clear(); for (int i = 0; i < s.size(); i++) mp[s[i]]++; bool q = true; for (int i = 0; i < t.size(); i++) { if (mp[t[i]] == 0) { q = false; break; } } if (q == false) { cout << -1 << endl; continue; } for (int j = 100005; j >= 1; j--) x[j].clear(); for (int i = s.size() - 1; i >= 0; i--) { for (int j = 1; j <= 26; j++) x[i + 1][j] = x[i + 2][j]; x[i + 1][s[i] - a + 1] = i + 1; } int in = 0, ans = 0; while (in < t.size()) { ans++; int ind = 0; while (true) { if (x[ind + 1][t[in] - a + 1] == 0) break; ind = x[ind + 1][t[in] - a + 1]; in++; if (in >= t.size()) break; } if (in >= t.size()) break; } cout << ans << endl; } }
|
#include <bits/stdc++.h> const int N = 400 + 10, MOD = 1000000007; inline void add(int &lhs, long long rhs) { lhs = (lhs + rhs) % MOD; } int n, f[N][N]; int main() { scanf( %d , &n); f[1][0] = f[1][1] = 1; for (int i = 2; i <= n; ++i) { for (int x = 0; x <= n; ++x) { for (int y = 0; x + y <= n; ++y) { int cur = (long long)f[i - 1][x] * f[i - 1][y] % MOD; if (!cur) continue; add(f[i][x + y], cur); add(f[i][x + y + 1], cur); if (x) add(f[i][x + y], 2LL * x * cur); if (y) add(f[i][x + y], 2LL * y * cur); if (x || y) add(f[i][x + y - 1], (x + y) * (x + y - 1LL) * cur); } } } printf( %d n , f[n][1]); return 0; }
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.reals.IVT.
Import CRing_Homomorphisms.coercions.
(**
* Roots of polynomials of odd degree *)
Section CPoly_Big.
(**
** Monic polynomials are positive near infinity
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma Cbigger : forall x y : R, {z : R | x [<=] z | y [<=] z}.
Proof.
intros.
elim (less_cotransitive_unfolded _ x (x[+][1]) (less_plusOne _ _) y); intro.
exists (y[+][1]); apply less_leEq.
apply less_leEq_trans with y. auto. apply less_leEq; apply less_plusOne.
apply less_plusOne.
exists (x[+][1]); apply less_leEq.
apply less_plusOne.
auto.
Qed.
Lemma Ccpoly_big : forall (p : RX) n, 0 < n ->
monic n p -> forall Y, {X : R | forall x, X [<=] x -> Y [<=] p ! x}.
Proof.
intro. elim p.
unfold monic in |- *. simpl in |- *. intros. elim H0. intros H1 H2.
cut ([0][~=] ([1]:R)). intro. elim (H3 H1).
apply ap_imp_neq. apply ap_symmetric_unfolded. apply ring_non_triv.
intros c q. intros H n H0 H1 Y.
elim (O_or_S n); intro y. elim y. intro m. intro y0.
rewrite <- y0 in H1.
elim (zerop m); intro y1. simpl in |- *.
exists (Y[-]c). intros.
rewrite y1 in H1.
apply shift_leEq_plus'.
cut (q ! x [=] [1]). intro.
astepr (x[*][1]). astepr x. auto.
apply monic_one with c. auto.
cut (monic m q). intro H2.
elim (Cbigger [0] (Y[-]c)). intro Y'. intros H3 H4.
elim (H m y1 H2 Y'). intro X'. intro H5.
simpl in |- *.
elim (Cbigger [1] X'). intro X. intros H6 H7.
exists X. intros.
apply shift_leEq_plus'.
apply leEq_transitive with ([1][*]Y').
astepr Y'. auto.
apply mult_resp_leEq_both; auto.
apply less_leEq. apply pos_one.
apply leEq_transitive with X; auto.
change (Y' [<=] q ! x) in |- *.
apply H5.
apply leEq_transitive with X; auto.
apply monic_cpoly_linear with c; auto.
rewrite <- y in H0.
elim (lt_irrefl _ H0).
Qed.
Lemma cpoly_pos : forall (p : RX) n, 0 < n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intros x H1.
exists (x[+][1]).
apply H1. apply less_leEq. apply less_plusOne.
Qed.
Lemma Ccpoly_pos' : forall (p : RX) a n, 0 < n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intro x'. intro H1.
elim (Cbigger (a[+][1]) x'). intro x. intros.
exists x; auto.
apply less_leEq_trans with (a[+][1]).
apply less_plusOne. auto.
Qed.
End CPoly_Big.
Section Flip_Poly.
(**
** Flipping a polynomial
%\begin{convention}% Let [R] be a ring.
%\end{convention}%
*)
Variable R : CRing.
Add Ring R: (CRing_Ring R).
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Fixpoint flip (p : RX) : RX :=
match p with
| cpoly_zero _ => cpoly_zero _
| cpoly_linear _ c q => cpoly_inv _ (cpoly_linear _ c (flip q))
end.
Lemma flip_poly : forall (p : RX) x, (flip p) ! x [=] [--]p ! ( [--]x).
Proof.
intro p. elim p.
intros. simpl in |- *. algebra.
intros c q. intros.
change ( [--]c[+]x[*] (cpoly_inv _ (flip q)) ! x [=] [--] (c[+][--]x[*]q ! ( [--]x))) in |- *.
astepl ( [--]c[+]x[*][--] (flip q) ! x).
astepl ( [--]c[+]x[*][--][--]q ! ( [--]x)).
ring.
Qed.
Lemma flip_coefficient : forall (p : RX) i,
nth_coeff i (flip p) [=] [--] ( [--][1][^]i) [*]nth_coeff i p.
Proof.
intro p. elim p.
simpl in |- *. algebra.
intros c q. intros.
elim i. simpl in |- *. ring.
intros. simpl in |- *.
astepl ( [--] (nth_coeff n (flip q))).
astepl ( [--] ( [--] ( [--][1][^]n) [*]nth_coeff n q)).
simpl in |- *. ring.
Qed.
Hint Resolve flip_coefficient: algebra.
Lemma flip_odd : forall (p : RX) n, odd n -> monic n p -> monic n (flip p).
Proof.
unfold monic in |- *. unfold degree_le in |- *.
intros.
elim H0. clear H0. intros.
split.
astepl ( [--] ( [--][1][^]n) [*]nth_coeff n p).
astepl ( [--][--] ([1][^]n) [*]nth_coeff n p).
astepl ([1][^]n[*]nth_coeff n p).
astepl ([1][*]nth_coeff n p).
Step_final ([1][*] ([1]:R)).
intros.
astepl ( [--] ( [--][1][^]m) [*]nth_coeff m p).
Step_final ( [--] ( [--][1][^]m) [*] ([0]:R)).
Qed.
End Flip_Poly.
Hint Resolve flip_poly: algebra.
Section OddPoly_Signs.
(**
** Sign of a polynomial of odd degree
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma oddpoly_pos : forall (p : RX) n, odd n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
apply cpoly_pos with n; auto.
elim H. intros. auto with arith.
Qed.
Lemma oddpoly_pos' : forall (p : RX) a n,
odd n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_pos' _ p a n). intros x H1 H2.
exists x; assumption.
elim H; auto with arith.
assumption.
Qed.
Lemma oddpoly_neg : forall (p : RX) n, odd n -> monic n p -> {x : R | p ! x [<=] [0]}.
Proof.
intros.
elim (oddpoly_pos _ _ H (flip_odd _ _ _ H H0)). intro x. intros.
exists ( [--]x).
astepl ( [--][--]p ! ( [--]x)). astepr ( [--] ([0]:R)).
apply inv_resp_leEq.
astepr (flip _ p) ! x. auto.
Qed.
End OddPoly_Signs.
Section Poly_Norm.
(**
** The norm of a polynomial
%\begin{convention}% Let [R] be a field, and [RX] the polynomials over
this field.
%\end{convention}%
*)
Variable R : CField.
(* begin hide *)
Let RX := cpoly_cring R.
(* end hide *)
Lemma poly_norm_aux : forall (p : RX) n, degree n p -> nth_coeff n p [#] [0].
Proof.
unfold degree in |- *. intros p n H.
elim H. auto.
Qed.
Definition poly_norm p n H := _C_ ([1][/] _[//]poly_norm_aux p n H) [*]p.
Lemma poly_norm_monic : forall p n H, monic n (poly_norm p n H).
Proof.
unfold poly_norm in |- *. unfold monic in |- *. unfold degree in |- *. unfold degree_le in |- *. intros.
elim H. intros H0 H1.
split.
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff n p).
intros.
astepl (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff m p).
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*][0]).
Qed.
Lemma poly_norm_apply : forall p n H x, (poly_norm p n H) ! x [=] [0] -> p ! x [=] [0].
Proof.
unfold poly_norm in |- *. intros.
apply mult_cancel_lft with ([1][/] nth_coeff n p[//]poly_norm_aux p n H).
apply div_resp_ap_zero_rev. apply ring_non_triv.
astepl ((_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H)) ! x[*]p ! x).
astepl (_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*]p) ! x.
Step_final ([0]:R).
Qed.
End Poly_Norm.
Section OddPoly_Root.
(**
** Roots of polynomials of odd degree
Polynomials of odd degree over the reals always have a root. *)
Lemma oddpoly_root' : forall f n, odd n -> monic n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros.
elim (oddpoly_neg _ f n); auto. intro a. intro H1.
elim (oddpoly_pos' _ f a n); auto. intro b. intros H2 H3.
cut {x : IR | a [<=] x /\ x [<=] b /\ f ! x [=] [0]}.
intro H4.
elim H4. clear H4. intros x H4.
elim H4. clear H4. intros H4 H5.
elim H5. clear H5. intros.
exists x. auto.
apply Civt_poly; auto.
apply monic_apzero with n; auto.
Qed.
Lemma oddpoly_root : forall f n, odd n -> degree n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros f n H H0.
elim (oddpoly_root' (poly_norm _ f n H0) n); auto.
intros. exists x.
apply poly_norm_apply with n H0; auto.
apply poly_norm_monic; auto.
Qed.
Lemma realpolyn_oddhaszero : forall f, odd_cpoly _ f -> {x : IR | f ! x [=] [0]}.
Proof.
unfold odd_cpoly in |- *.
intros f H.
elim H. clear H. intro n. intros H H0.
cut (odd n).
intro.
elim (oddpoly_root f n H1 H0). intros. exists x. auto.
apply Codd_to.
assumption.
Qed.
End OddPoly_Root.
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read1() { T t = 0; char k = getchar(); bool flag = 0; while ( 0 > k || k > 9 ) { if (k == - ) flag = 1; k = getchar(); } while ( 0 <= k && k <= 9 ) t = (t << 3) + (t << 1) + (k ^ 48), k = getchar(); return flag ? -t : t; } int s, x[5], dp[2][16][16][16]; char str[5][1005]; int main() { s = read1<long long>(); for (int i = 1; i < 5; ++i) x[i] = read1<long long>(); for (int i = 1; i <= 4; ++i) scanf( %s , str[i] + 1); memset(dp[0], 0x7f, sizeof(dp[0])); dp[0][15][15][15] = 0; for (int i = 1; i <= s; ++i) { memset(dp[i & 1], 0x7f, sizeof(dp[i & 1])); int t = 0; for (int j = 1; j < 5; ++j) t = t << 1 | (str[j][i] == . ); for (int j = 0; j < 16; ++j) for (int k = 0; k < 16; ++k) for (int l = 0; l < 16; ++l) dp[i & 1][15][15][15] = min(dp[i & 1][15][15][15], dp[~i & 1][j][k][l] + x[4]); for (int k = 0; k < 16; ++k) for (int l = 0; l < 16; ++l) dp[i & 1][k][l][t] = min(dp[i & 1][k][l][t], dp[~i & 1][15][k][l]); for (int j = 0; j < 16; ++j) for (int k = 0; k < 16; ++k) for (int r = 0; r < 16; ++r) for (int l = 1; l < 4; ++l) for (int w = 0; w < 5 - l; ++w) { int op[3] = {j, k, r}; for (int f = 2; f > 2 - l; --f) op[f] |= (1 << l) - 1 << w; dp[i & 1][op[0]][op[1]][op[2]] = min( dp[i & 1][op[0]][op[1]][op[2]], dp[i & 1][j][k][r] + x[l]); } } cout << dp[s & 1][15][15][15]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; string s; int main() { cin >> n; cin >> s; for (int i = 0; i < n; ++i) { int c1 = 0, c2 = 0; for (int j = i - 1; j >= 0; --j) { if (s[j] == L ) { break; } if (s[j] == R ) { ++c1; } } for (int j = i; j < n - 1; ++j) { if (s[j] == R ) { break; } if (s[j] == L ) { ++c2; } } cout << max(c1, c2) + 1 << ; } cout << endl; return 0; }
|
/*
* Titor - System - PS/2 controller wrapper
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_PS2_WRAPPER
`else
`define INC_PS2_WRAPPER
`timescale 1 ns / 100 ps
module PS2(
ps2_clock,
ps2_data,
rx_data,
rx_done,
reset,
clk
);
`include "definition/Definition.v"
inout ps2_clock;
inout ps2_data;
output reg [BYTE-1:0] rx_data;
output reg rx_done;
input reset;
input clk;
localparam BITTHROUGH = 10; // the number of bits to accept including Parity and Stop
localparam STATE_IDLE = 32'd1,
STATE_RX_BIT = 32'd2;
wire devclk;
wire devclkneg;
wire [WORD-1:0] bitcount;
wire bitarc;
reg [WORD-1:0] state;
reg [BITTHROUGH-1:0] shift_in;
reg postbitarc;
reg [BYTE-1:0] clkbuf;
// Clock line conditioning
Debounce #(1*MICROS) stable (
.linein(ps2_clock),
.lineout(devclk),
.reset(reset),
.clk(clk)
);
Negedge tick (
.linein(devclk),
.lineout(devclkneg),
.reset(reset),
.clk(clk)
);
// Bit counting
Radix_Counter #(BITTHROUGH) countoff (
.carry_in((state==STATE_RX_BIT) && devclkneg),
.carry_out(bitarc),
.count(bitcount),
.reset(reset),
.clk(clk)
);
// Finite State Machine
always @(posedge clk) begin
if(reset) state <= STATE_IDLE;
else if((state==STATE_IDLE) && devclkneg) state <= STATE_RX_BIT;
else if((state==STATE_RX_BIT) && bitarc) state <= STATE_IDLE;
else state <= state;
end
// Data capture
always @(posedge clk) begin
if(reset) shift_in <= 0;
else if(devclkneg) shift_in <= {ps2_data, shift_in[BITTHROUGH-1:1]};
else shift_in <= shift_in;
if(reset) postbitarc <= 0;
else postbitarc <= bitarc;
if(reset) rx_data <= 0;
else if(postbitarc) rx_data <= shift_in;
else rx_data <= rx_data;
end
always @(posedge clk) begin
if(reset) rx_done <= 0;
else if(postbitarc) rx_done <= 1;
else rx_done <= 0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; int n; cin >> s; n = s.size(); s = s + b ; for (int i = 0; i < n; i++) { cout << (s[i] != s[i + 1] ? 1 : 0) << ; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: fifo_8x32.v
// Project: CPCI (PCI Control FPGA)
// Description: Small 8 x 32-bit FIFO
//
// Change history:
//
///////////////////////////////////////////////////////////////////////////////
module fifo_8x32(
// PCI Signals
input [31:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [31:0] dout, // Data out
output full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH_BITS = 3;
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [31:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS - 1 + 1 : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <= depth + 'h1;
if (~wr_en & rd_en) depth <= depth - 'h1;
end
end
assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // fifo_8x32
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int T; int main() { cin >> T; while (T--) { int a, b, c; cin >> c >> b >> a; string s; if (a > 0) { s += 1 ; for (int i = 0; i < a; i++) s += 1 ; if (b > 0 && b % 2 == 1) { for (int i = 0; i < b; i++) { if (i % 2 == 0) s += 0 ; else s += 1 ; } if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } } else if (b > 0 && b % 2 == 0) { for (int i = 0; i < b - 1; i++) { if (i % 2 == 0) s += 0 ; else s += 1 ; } if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } cout << 0 ; cout << s << endl; continue; } else if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } } else if (b > 0) { s += 1 ; if (b > 0 && b % 2 == 1) { for (int i = 0; i < b; i++) { if (i % 2 == 0) s += 0 ; else s += 1 ; } if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } } else if (b > 0 && b % 2 == 0) { for (int i = 0; i < b - 1; i++) { if (i % 2 == 0) s += 0 ; else s += 1 ; } if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } cout << 0 ; cout << s << endl; continue; } else if (c > 0) { if (s[s.length() - 1] != 0 ) s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } } else if (c > 0) { s += 0 ; for (int i = 0; i < c; i++) s += 0 ; } cout << s << endl; } }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_qpram32 #(
parameter depth = 11 /* < log2 of the capacity in 32-bit words */
) (
input sys_clk,
/* 32-bit read port 1 */
input [depth-1:0] a1,
output [31:0] d1,
/* 32-bit read port 2 */
input [depth-1:0] a2,
output [31:0] d2,
/* 32-bit read port 3 */
input [depth-1:0] a3,
output [31:0] d3,
/* 32-bit read port 4 */
input [depth-1:0] a4,
output [31:0] d4,
/* 64-bit write port - we=1 disables read ports */
input we,
input [depth-1-1:0] aw,
input [63:0] dw
);
tmu2_dpram #(
.depth(depth),
.width(32)
) ram1 (
.sys_clk(sys_clk),
.a(we ? {aw, 1'b0} : a1),
.we(we),
.di(dw[63:32]),
.do(d1),
.a2(we ? {aw, 1'b1} : a2),
.we2(we),
.di2(dw[31:0]),
.do2(d2)
);
tmu2_dpram #(
.depth(depth),
.width(32)
) ram2 (
.sys_clk(sys_clk),
.a(we ? {aw, 1'b0} : a3),
.we(we),
.di(dw[63:32]),
.do(d3),
.a2(we ? {aw, 1'b1} : a4),
.we2(we),
.di2(dw[31:0]),
.do2(d4)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 10; int ans[maxn]; bool build(int l, int r, int base, int top, int sum) { if (l > r) return true; int len = r - l + 1; int tmp = len * base; if (tmp > sum) return false; if (tmp == sum) { for (int i = l; i <= r; ++i) ans[i] = base; return true; } if (base == top) return false; if (tmp + len >= sum) { for (int i = l; i <= r; ++i) { sum -= base; ans[i] = base; } for (int i = l; i <= r; ++i) { if (!sum) break; sum--; ans[i]++; } return true; } return false; } int main() { int n, k, l, r, sall, sk; scanf( %d%d%d%d%d%d , &n, &k, &l, &r, &sall, &sk); int lim; for (int i = r; i >= l; --i) { if (build(1, k, i, r, sk)) { lim = i; break; } } for (int i = lim; i >= l; --i) { if (build(k + 1, n, i, lim, sall - sk)) { break; } } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int loc[200000 + 10]; int n; int ans[4]; int fnext(int y) { int l = 1, r = n + 1, mid = (l + r) / 2; while (l < r) { if (loc[mid] <= y) l = mid + 1; else r = mid; mid = (l + r) / 2; } return mid; } int ok(int x) { int i, j; int z = 1; for (i = 1; i <= 3; i++) { z = fnext(loc[z] + x); ans[i] = z; if (z >= n + 1) return 1; } return 0; } int main() { while (scanf( %d , &n) != EOF) { int i, j, k; for (i = 1; i <= n; i++) { scanf( %d , &loc[i]); } sort(loc + 1, loc + n + 1); int r = (loc[n] - loc[1]); int l = 0, mid; while (l < r) { mid = (r + l) / 2; if (ok(mid)) r = mid; else l = mid + 1; } ok(l); double radius = l * 1.0 / 2.0; double radar1 = (loc[ans[1] - 1] + loc[1]) * 1.0 / 2.0; double radar2 = (loc[ans[2] - 1] + loc[ans[1]]) / 2.0; double radar3 = (loc[ans[3] - 1] + loc[ans[2]]) / 2.0; printf( %.6f n , radius); printf( %.6f , radar1); printf( %.6f , radar2); printf( %.6f n , radar3); } return 0; }
|
// Lab 4
// Created by David Tran
// Last Modified 02-05-2014
// extras
`timescale 1 ms /1 us
`include "full_adder.v"
// Testbench Module
module full_adder_tb (A, B, D);
output A, B, D;
reg A, B, D;
wire S, C;
reg t_A [5000:0];
reg t_B [5000:0];
reg t_D [5000:0];
reg t_clock;
reg [31:0] vectornum; //Values from 0 -> 2^31
integer fp;
full_adder I1 (A, B, D, S, C);
//initial #1000 $finish;
initial
begin
t_clock=0;
forever #5 t_clock=~t_clock;
end
initial
begin
$readmemb("./bit_str_a_0.txt",t_A);
$readmemb("./bit_str_a_1.txt",t_B);
$readmemb("./bit_str_a_2.txt",t_D);
vectornum=0; // Set test vector 0
end
always @(negedge t_clock)
begin
A<=t_A[vectornum];
B<=t_B[vectornum];
D<=t_D[vectornum];
vectornum<=vectornum+1;
end
initial
begin
fp=$fopen("full_adder_tb.out");
//$fmonitor(fp, "time=%0d", $time,, "A=%b B=%b D=%b S=%b C=%b", A, B, D, S, C);
$monitor("time=%0d", $time,, "A=%b B=%b D=%b S=%b C=%b", A, B, D, S, C);
#1000
$fclose(fp);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, ad, a[444444], u[444444]; char str[11]; int getnum(char str[]) { int ret = 0, neg = -1, i = 1; if (str[0] != - ) { neg = 1; i = 0; } for (; str[i]; i++) { ret = ret * 10 + str[i] - 0 ; } ret *= neg; return ret; } int main() { int i, j, fg = 0, nd, pd, ll, lt, rt, ds, mid, ld; scanf( %d%d , &n, &k); ad = k; for (i = 1; i <= n; i++) { scanf( %s , str); if (str[0] == ? ) a[i + ad] = 1; else u[i + ad] = getnum(str); } for (i = 1; i <= ad; i++) { u[i] = -1010000000 + i; u[ad + n + i] = 1010000000 + i; } for (i = 1; i <= k; i++) { if (fg) break; nd = pd = -1; ll = u[i]; for (j = i + k; j <= n + 2 * ad; j += k) { if (a[j]) continue; if (u[j] <= ll) { fg = 1; break; } ll = u[j]; } if (fg) break; for (j = i; j <= n + 2 * ad; j += k) { if (pd == -1 && !a[j] && u[j] >= 0) { pd = j; break; } } for (j = pd; j >= 1; j -= k) { if (nd == -1 && !a[j] && u[j] < 0) { nd = j; break; } } for (j = pd + k; j <= n + 2 * ad; j += k) { ld = j - k; if (!a[j]) { if (u[ld] >= u[j]) fg = 1; continue; } if (fg) break; a[j] = 0; u[j] = u[ld] + 1; } if (fg) break; for (j = nd - k; j >= 1; j -= k) { ld = j + k; if (!a[j]) { if (u[j] >= u[ld]) fg = 1; continue; } if (fg) break; a[j] = 0; u[j] = u[ld] - 1; } mid = (pd - nd) / k - 1; if (mid > u[pd] - u[nd]) { fg = 1; break; } lt = -((mid - 1) / 2); rt = mid / 2; if (u[pd] <= rt) { ds = rt - u[pd] + 1; rt -= ds; lt -= ds; } if (u[nd] >= lt) { ds = u[nd] - lt + 1; rt += ds; lt += ds; } for (j = nd + k; j < pd; j += k) { u[j] = lt; lt++; } } if (fg) puts( Incorrect sequence ); else { for (i = k + 1; i <= k + n; i++) printf( %d , u[i]); puts( ); } return 0; }
|
module RAMDP(clock,reset,we,addr0,addr1,data_i,data_o0,data_o1);
parameter AddrSize = 8;
parameter DataSize = 8;
input wire clock;
input wire reset;
input wire we;
input wire [AddrSize-1:0] addr0;
input wire [AddrSize-1:0] addr1;
input wire [DataSize-1:0] data_i;
`ifdef SIM
output reg [DataSize-1:0] data_o0;
output reg [DataSize-1:0] data_o1;
reg [DataSize-1:0] s_Data[2**AddrSize-1:0];
reg [AddrSize:0] k;
initial begin
for (k = 0; k < 2**AddrSize; k = k + 1) begin
s_Data[k] = 0;
end
end
always @ (posedge clock) begin
if (reset) begin
data_o0 <= 0;
data_o1 <= 0;
end
else begin
if (we) begin
s_Data[addr0] <= data_i;
end
data_o0 <= s_Data[addr0];
data_o1 <= s_Data[addr1];
end
end // always @ (posedge clock)
`endif // `ifdef SIM
`ifdef FPGA
output wire [DataSize-1:0] data_o0;
output wire [DataSize-1:0] data_o1;
RAMB16_S1_S1
ramse (.CLKA(clock),
.CLKB(clock),
.SSRA(reset),
.SSRB(reset),
.ENA(~reset),
.WEA(we),
.ADDRA(addr0),
.DIA(data_i),
.DOA(data_o0),
.ENB(~reset),
.WEB(0),
.ADDRB(addr1),
.DIB(1'b0),
.DOB(data_o1));
`endif
endmodule // RAMDP
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:not_1bit:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_not_1bit_0_0 (
inp,
outp
);
input wire inp;
output wire outp;
not_1bit inst (
.inp(inp),
.outp(outp)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long rdtsc() { long long tmp; asm( rdtsc : =A (tmp)); return tmp; } inline int myrand() { return abs((rand() << 15) ^ rand()); } inline int rnd(int x) { return myrand() % x; } const int maxn = (int)1e5; char s[maxn + 1]; long long hs[maxn + 1]; const long long Q = 239017; long long qs[maxn + 1]; const int maxc = 26; int colors[maxc][maxn + 1]; void precalc(int n) { hs[0] = 0; for (int i = 0; i < n; ++i) { hs[i + 1] = hs[i]; hs[i + 1] *= Q; hs[i + 1] += (int)s[i]; } qs[0] = 1; for (int i = 1; i <= n; ++i) qs[i] = qs[i - 1], qs[i] *= Q; for (int color = 0; color < maxc; ++color) { colors[color][0] = 0; for (int i = 0; i < n; ++i) colors[color][i + 1] = colors[color][i] + (s[i] == color + a ); } } inline long long getHash(int pos, int len) { long long tmp = hs[pos]; tmp *= qs[len]; long long res = hs[pos + len]; res -= tmp; return res; } const int maxl = 17; inline int commonLen(int left, int right, int n) { assert(left < right); int ans = 0; for (int it = maxl - 1; it >= 0; --it) { if (right + ans + (1 << it) <= n && getHash(left, ans + (1 << it)) == getHash(right, ans + (1 << it))) ans += (1 << it); } return ans; } int gray[maxl][maxn]; int grayLen[maxl]; long long wholeTaken[maxn + 1]; long long getInitial(int n) { for (int i = 0; i <= n; ++i) wholeTaken[i] = 0; long long res = 0; for (int len = 0; len < maxl; ++len) { grayLen[len] = (1 << (len + 1)) - 1; int n0 = n - grayLen[len] + 1; for (int i = 0; i < n0; ++i) { int ¤t = gray[len][i]; current = 0; if (!len) { current = 1; continue; } int half = i + grayLen[len - 1]; int *countMidColor = colors[s[half] - a ]; if (gray[len - 1][i] && countMidColor[i + grayLen[len]] - countMidColor[i] == 1 && getHash(i, grayLen[len - 1]) == getHash(half + 1, grayLen[len - 1])) current = 1; } long long sqrLen = (long long)grayLen[len] * grayLen[len]; for (int i = 0; i < n0; ++i) { if (!gray[len][i]) continue; wholeTaken[i] += sqrLen; wholeTaken[i + grayLen[len]] -= sqrLen; res += sqrLen; } } for (int i = 1; i <= n; ++i) wholeTaken[i] += wholeTaken[i - 1]; return res; } long long changes[maxc][maxn]; void findChanges(int n) { for (int i = 0; i < maxc; ++i) for (int j = 0; j < n; ++j) changes[i][j] = 0; for (int len = 0; len < maxl; ++len) { int n0 = n - grayLen[len] + 1; for (int i = 0; i < n0; ++i) { if (!len) { for (int c = 0; c < maxc; ++c) if (c + a != s[i]) changes[c][i] += 1; continue; } int half = i + grayLen[len - 1]; if (!gray[len - 1][i] && !gray[len - 1][half + 1]) continue; long long sqrLen = (long long)grayLen[len] * grayLen[len]; if (gray[len - 1][i] && getHash(i, grayLen[len - 1]) == getHash(half + 1, grayLen[len - 1])) { for (int c = 0; c < maxc; ++c) { int *countMidColor = colors[c]; if (countMidColor[i + grayLen[len]] - countMidColor[i] == 0) { changes[c][half] += sqrLen; } } } int *countMidColor = colors[s[half] - a ]; int firstLen = commonLen(i, half + 1, n); if (firstLen >= grayLen[len - 1]) continue; int left = i + firstLen, right = left + grayLen[len - 1] + 1; int secondLen = commonLen(left + 1, right + 1, n); if (firstLen + 1 + secondLen < grayLen[len - 1]) continue; if (gray[len - 1][half + 1] && countMidColor[half + 1 + grayLen[len - 1]] - countMidColor[half + 1] == 0) changes[s[right] - a ][left] += sqrLen; if (gray[len - 1][i] && countMidColor[half] - countMidColor[i] == 0) changes[s[left] - a ][right] += sqrLen; } } } bool solve() { if (scanf( %s , s) < 1) return 0; int n = strlen(s); precalc(n); long long ans = getInitial(n); findChanges(n); long long maxAdd = 0; for (int i = 0; i < maxc; ++i) for (int j = 0; j < n; ++j) maxAdd = max(maxAdd, -wholeTaken[j] + changes[i][j]); printf( %lld n , ans + maxAdd); return 1; } int main() { srand(rdtsc()); while (1) { if (!solve()) break; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 7; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; const int mod = 1000000007; const double eps = 1e-6; const double PI = acos(-1); int n, k, miu[N], Pown[N], sum[N]; int Power(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = 1LL * ans * a % mod; a = 1LL * a * a % mod; b >>= 1; } return ans; } int main() { miu[1] = 1; for (int i = 1; i < N; i++) for (int j = i + i; j < N; j += i) miu[j] -= miu[i]; scanf( %d%d , &n, &k); for (int i = 1; i <= k; i++) Pown[i] = Power(i, n); int ans = 0, tmp = 0; for (int i = 1; i <= k; i++) { for (int j = i; j <= k; j += i) { sum[j] = ((sum[j] + 1LL * miu[i] * (Pown[j / i] - Pown[j / i - 1])) % mod + mod) % mod; } tmp = (tmp + sum[i]) % mod; ans = (ans + (tmp ^ i)) % mod; } printf( %d n , ans); return 0; }
|
module time_signal ( //Этот модуль описывает генератор сигнала времени, период времени пол-секунды.
//This module make a signal with a half-second period of time.
input wire clk,
input wire reset,
output wire time_out
);
reg [24:0] clk_number; //Счетчик тактов, на Waveshare CoreEP4CE10 установлен источник 50МГц сигнала.
//Clock counter, Waveshare CoreEP4CE10 have 50MHz global clk. Need just half.
reg [0:0] sec_kp; //Для хранения значения выходного сигнала между отсчетами.
//A signal keeper.
assign time_out = sec_kp; //Соединение выходного провода time_out модуля с регистром sec_kp.
//Операция assign не может быть выполнена в поведенческом always блоке.
//Поведенческий always блок. Только в нем возможно использованием ветвлений и циклов.
always @(posedge clk) //Источник тактового сигнала установлен на плате, частота 50МГц.
begin
if (!reset) //Кнопка сброса также уже смонтирована на CoreEP4CE10, инверсная логика.
begin //A zero level is active.
clk_number <= 25'd0;
sec_kp <= 1'd0; //Сброс регистров в начальное (нулевое) состояние.
//Неблокирующее присваивание "<=". Присвоение регистров произойдет одновременно, параллельно.
//Формат 1'd0: число до апострофа указывает на то сколько бит необходимо для хранения константы,
//буква после апострофа говорит о записи идущего следом числа (b - двоичная, d - десятичная и т.д.)
end
else //Если нога сброса подтянута к Vcc (не нажата кнопка), находится в z состоянии
//или даже в неопределенном (x). В общем там не ноль, то...
begin
if (clk_number <= 25'd25000000) //Проверка значения счетчика тактов, если не отсчитано 25 миллионов,
clk_number <= clk_number + 25'd1; //то продолжить отсчет
else //A half-second is gone.
clk_number <= 25'd0; //иначе счетчик заполнен, сбросить его в ноль.
if (clk_number > 25'd12500000) //Период сигнала здесь пол-секунды.
sec_kp <= 1'd1; //Четверть секунды удерживается единица.
//A quarter-second to do high output.
else
sec_kp <= 1'd0; //Вторую четверть - ноль.
//Next quarter to do low output.
end
end
endmodule
|
//#############################################################################
//# Function: Synchronous FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_sync #(parameter DW = 104, //FIFO width
parameter DEPTH = 32, //FIFO depth
parameter PROG_FULL = (DEPTH/2),//prog_full threshold
parameter AW = $clog2(DEPTH) //rd_count width
)
(
input clk, // clock
input nreset, // active high async reset
input [DW-1:0] din, // data to write
input wr_en, // write fifo
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo full
output prog_full, // fifo is almost full
output empty, // fifo is empty
output reg [AW-1:0] rd_count // valid entries in fifo
);
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
wire fifo_read;
wire fifo_write;
assign empty = (rd_count[AW-1:0] == 0);
assign prog_full = (rd_count[AW-1:0] >= PROG_FULL);
assign full = (rd_count[AW-1:0] == (DEPTH-1));
assign fifo_read = rd_en & ~empty;
assign fifo_write = wr_en & ~full;
always @ ( posedge clk or negedge nreset)
if(!nreset)
begin
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
rd_count[AW-1:0] <= 'b0;
end
else if(fifo_write & fifo_read)
begin
wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
end
else if(fifo_write)
begin
wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
end
else if(fifo_read)
begin
rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
end
// GENERIC DUAL PORTED MEMORY
oh_memory_dp
#(.DW(DW),
.DEPTH(DEPTH))
mem (// read port
.rd_dout (dout[DW-1:0]),
.rd_clk (clk),
.rd_en (fifo_read),
.rd_addr (rd_addr[AW-1:0]),
// write port
.wr_clk (clk),
.wr_en (fifo_write),
.wr_wem ({(DW){1'b1}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (din[DW-1:0]));
endmodule // oh_fifo_sync
|
//
// Landing Gear Controller Behavioral Model
// Jenner Hanni <>
//
// 7-state Moore FSM with 5 inputs and 5 outputs.
//
module LandingGearController(Clock, Clear,
GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever,
RedLED, GrnLED, Valve, Pump, Timer);
input Clock, Clear, GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever;
output RedLED, GrnLED, Valve, Pump, Timer;
reg RedLED, GrnLED, Valve, Pump, Timer;
parameter YES = 1'b1;
parameter ON = 1'b1;
parameter DOWN = 1'b1;
parameter RESET = 1'b1;
parameter NO = 1'b0;
parameter OFF = 1'b0;
parameter UP = 1'b0;
parameter COUNT = 1'b0;
parameter
TAXI = 7'b0000001,
TUP = 7'b0000010,
TDN = 7'b0000100,
GOUP = 7'b0001000,
GODN = 7'b0010000,
FLYUP = 7'b0100000,
FLYDN = 7'b1000000;
reg [6:0] State, NextState;
//
// Updates state or reset on every positive clock edge
//
always @(posedge Clock)
begin
if (Clear)
State <= TAXI;
else
State <= NextState;
end
//
// State Descriptions
//
// TAXI Plane is on the ground -- this is the only state to reset the timer
// TUP Plane has taken off and requested the gear up but less than two seconds
// TDN Plane has taken off but not requested the gear up with less than two seconds
// GOUP Plane is in flight; gear is in motion being retracted
// GODN Plane is in flight; gear is in motion being extended
// FLYUP Plane is in flight with the gear retracted
// FLYDN Plane is in flight with the gear extended
//
always @(State)
begin
case (State)
TAXI: begin
RedLED = OFF;
GrnLED = ON;
Valve = DOWN;
Pump = OFF;
Timer = RESET;
end
TUP: begin
RedLED = OFF;
GrnLED = ON;
Valve = UP;
Pump = OFF;
Timer = COUNT;
end
TDN: begin
RedLED = OFF;
GrnLED = ON;
Valve = DOWN;
Pump = OFF;
Timer = COUNT;
end
GOUP: begin
RedLED = ON;
GrnLED = OFF;
Valve = UP;
Pump = ON;
Timer = COUNT;
end
GODN: begin
RedLED = ON;
GrnLED = OFF;
Valve = DOWN;
Pump = ON;
Timer = COUNT;
end
FLYUP: begin
RedLED = OFF;
GrnLED = OFF;
Valve = UP;
Pump = OFF;
Timer = COUNT;
end
FLYDN: begin
RedLED = OFF;
GrnLED = ON;
Valve = DOWN;
Pump = OFF;
Timer = COUNT;
end
endcase
end
//
// Next state generation logic
//
always @(State or GearIsDown or GearIsUp or PlaneOnGround or TimeUp or Lever)
begin
case (State)
TAXI: begin
if (PlaneOnGround == NO && Lever == UP)
NextState = TUP;
else if (PlaneOnGround == NO && Lever == DOWN)
NextState = TDN;
else
NextState = TAXI;
end
TUP: begin
if (PlaneOnGround)
NextState = TAXI;
else if (GearIsDown == NO)
NextState = GOUP;
else if (TimeUp == YES)
NextState = FLYDN;
else if (TimeUp == NO && Lever == DOWN)
NextState = TDN;
else
NextState = TUP;
end
TDN: begin
if (PlaneOnGround)
NextState = TAXI;
else if (GearIsDown == NO)
NextState = GOUP;
else if (TimeUp == YES)
NextState = FLYDN;
else if (TimeUp == NO && Lever == UP)
NextState = TUP;
else
NextState = TDN;
end
GOUP: begin
if (GearIsUp == YES)
NextState = FLYUP;
else
NextState = GOUP;
end
GODN: begin
if (PlaneOnGround == YES && GearIsDown == YES)
NextState = TAXI;
else if (GearIsDown == YES)
NextState = FLYDN;
else
NextState = GODN;
end
FLYUP: begin
if (Lever == DOWN)
NextState = GODN;
else
NextState = FLYUP;
end
FLYDN: begin
if (PlaneOnGround == YES)
NextState = TAXI;
else if (Lever == UP)
NextState = GOUP;
else
NextState = FLYDN;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:13:00 04/24/2015
// Design Name: ALU_16
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_alu.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ALU_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu;
reg clock;
// Inputs
reg [15:0] ALU_data_in1;
reg [15:0] ALU_data_in2;
reg [7:0] ALU_control;
// Outputs
wire [15:0] ALU_data_out;
wire N;
wire Z;
wire C;
wire V;
// Instantiate the Unit Under Test (UUT)
ALU_16 uut (
.clock(clock),
.ALU_data_in1(ALU_data_in1),
.ALU_data_in2(ALU_data_in2),
.ALU_control(ALU_control),
.ALU_data_out(ALU_data_out),
.N(N),
.Z(Z),
.C(C),
.V(V)
);
initial begin
// Initialize Inputs
clock = 0;
ALU_data_in1 = 0;
ALU_data_in2 = 0;
ALU_control = 0;
// Wait 100 ns for global reset to finish
//#100;
check_alu(16'h8007, 16'hc005, 8'h00, 16'h8005, 0, 0, 0, 0);
check_alu(16'h000a, 16'h000c, 8'he6, 16'h8005, 1, 0, 0, 0);
end
task check_alu;
input [15:0] i_a;
input [15:0] i_b;
input [7:0] i_c;
input [15:0] exp_o;
input exp_n;
input exp_z;
input exp_c;
input exp_v;
begin
ALU_data_in1 = i_a;
ALU_data_in2 = i_b;
ALU_control = i_c;
#1;
if ((ALU_data_out !== exp_o) || (N !== exp_n) || (Z !== exp_z) || (C !== exp_c) || (V !== exp_v)) begin
$display("Error @%dns O=%b, eO=%b | N=%b, eN=%b | Z=%b, eZ=%b | C=%b, eC=%b | V=%b, eV=%b", $time, ALU_data_out, exp_o, N, exp_n, Z, exp_z, C, exp_c, V, exp_v);
end
$display ("======================");
end
endtask
always #1 clock = !clock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CONB_PP_SYMBOL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_256_139.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [138:0] sub_wire0;
wire [7:0] sub_wire1;
wire [138:0] q = sub_wire0[138:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 139,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL "data[138..0]"
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL "q[138..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_wave*.jpg FALSE
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#include <bits/stdc++.h> using namespace std; void ga(int N, int *A) { for (int i(0); i < N; i++) scanf( %d , A + i); } char s[64][64]; int N, M, x = int(1e9 + 1), X, y = int(1e9 + 1), Y; int main(void) { scanf( %d%d , &N, &M); for (int i(0); i < N; i++) scanf( %s , s[i]); for (int i(0); i < N; i++) for (int j(0); j < M; j++) if (s[i][j] == 42) x = min(x, i), X = max(X, i), y = min(y, j), Y = max(Y, j); for (int k(x); k < X + 1; k++) { for (int l(y); l < Y + 1; l++) putchar(s[k][l]); puts( ); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> inline void amin(T &first, const T &second) { if (second < first) first = second; } template <class T> inline void amax(T &first, const T &second) { if (first < second) first = second; } void solve() { int n; cin >> n; vector<pair<int, int> > a(n); map<int, int> home; for (int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; home[a[i].first]++; } vector<int> ret(n); for (int i = 0; i < n; ++i) { ret[i] = n - 1; ret[i] += home[a[i].second]; } for (int i = 0; i < n; ++i) { cout << ret[i] << << 2 * (n - 1) - ret[i] << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long int> adj[101]; set<pair<long long int, long long int>> color[101]; long long int visited[101]; long long int x; void bfs(long long int a, long long int b, long long int c) { queue<long long int> q; q.push(a); while (!q.empty()) { long long int p = q.front(); q.pop(); if (p == b) { x = 1; visited[p] = 1; } if (visited[p]) continue; visited[p] = 1; for (long long int i = 0; i < adj[p].size(); i++) { if (color[c].find({p, adj[p][i]}) != color[c].end()) { q.push(adj[p][i]); } } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int i, j, k, l, m, n, p, t, a, b, c, q; cin >> n >> m; set<pair<long long int, long long int>> s; for (i = 0; i < m; i++) { cin >> a >> b >> c; if (s.find({a, b}) == s.end()) { s.insert({a, b}); adj[a].push_back(b); adj[b].push_back(a); } color[c].insert({a, b}); color[c].insert({b, a}); } cin >> q; for (i = 0; i < q; i++) { cin >> a >> b; p = 0; for (j = 1; j <= m; j++) { x = 0; bfs(a, b, j); p += x; memset(visited, 0, sizeof(visited)); } cout << p << n ; } }
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`timescale 1 ns / 1 ps
module encoder_axi_m_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
output wire [31:0] incoming_data,
output wire incoming_data_valid,
output wire rburst_active,
output wire wburst_active,
output wire wnext,
input wire dram_rreq,
input wire dram_wreq,
input wire [C_M00_AXI_ADDR_WIDTH-1:0] dram_raddr,
input wire [C_M00_AXI_ADDR_WIDTH-1:0] dram_waddr,
input wire [31:0] outgoing_data,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
encoder_axi_m_v1_0_M00_AXI # (
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) encoder_axi_m_v1_0_M00_AXI_inst (
.dram_rreq ( dram_rreq ), // input
.dram_wreq ( dram_wreq ), // input
.dram_raddr ( dram_raddr ), // input
.dram_waddr ( dram_waddr ), // input
.outgoing_data ( outgoing_data ), // input
.wnext ( wnext ), // output
.rburst_active ( rburst_active ), // output
.wburst_active ( wburst_active ), // output
.error_reg(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
assign incoming_data = m00_axi_rdata;
// The data is valid when rvalid AND rready.
// This is needed if slave is allowed to deassert rvalid signal
// during a burst, or if the master asserts rready irrespective
// of expectation of data (NOT our case).
assign incoming_data_valid = m00_axi_rvalid && m00_axi_rready;
// User logic ends
endmodule
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#include <bits/stdc++.h> using namespace std; const long long int M = 1e18 + 7; const long long int mod = 1e9 + 7; const long long int infi = LLONG_MAX; long long int i, j, ans, k, n, x, y, m, mymax = LLONG_MIN, mymin = LLONG_MAX, b, c, z, sum; int main() { long long int x1, x2, s, p, t1, t2, d; scanf( %lld %lld %lld , &s, &x1, &x2); scanf( %lld %lld , &t1, &t2); scanf( %lld %lld , &p, &d); if (x2 < x1) { ans = (x1 - x2) * t2; if (d == 1) { if (p <= x2) { ans = min(ans, (2 * s - x2 - p) * t1); } else if (p > x2 && p <= x1) { ans = min(ans, (2 * s - x2 - p) * t1); } else { ans = min(ans, (2 * s - p - x2) * t1); } } else { if (p < x2) { ans = min(ans, (2 * s - x2 + p) * t1); } else if (p >= x2 && p < x1) { ans = min(ans, (2 * s - x2 + p) * t1); } else { ans = min(ans, (p - x2) * t1); } } printf( %lld n , ans); return 0; } ans = (x2 - x1) * t2; if (d == 1) { if (p <= x1) { ans = min(ans, (x2 - p) * t1); } else if (p > x1 && p <= x2) { ans = min(ans, (2 * s + x2 - p) * t1); } else { ans = min(ans, (2 * s - p + x2) * t1); } } else { if (p < min(x1, x2)) { ans = min(ans, (x2 + p) * t1); } else if (p >= x1 && p <= x2) { ans = min(ans, (p + x2) * t1); } else { ans = min(ans, (p + x2) * t1); } } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> static const int MAXN = 5004; static const int ALPHA = 26; static const int MODULUS = 1e9 + 7; int n; char s[MAXN]; int binom[MAXN][MAXN]; int f[MAXN][ALPHA] = {{0}}, f_rowsum[MAXN] = {0}; void preprocess_binomials() { binom[0][0] = 1; for (int i = 1; i < MAXN; ++i) { binom[i][0] = 1; for (int j = 1; j <= i; ++j) binom[i][j] = (binom[i - 1][j - 1] + binom[i - 1][j]) % MODULUS; } } int main() { preprocess_binomials(); scanf( %d , &n); getchar(); for (int i = 0; i < n; ++i) s[i] = getchar() - a ; f_rowsum[0] = 1; for (int i = 0; i < n; ++i) { for (int len = i + 1; len >= 1; --len) { int increment = ((f_rowsum[len - 1] - f[len - 1][s[i]] - f[len][s[i]]) % MODULUS + MODULUS) % MODULUS; (f[len][s[i]] += increment) %= MODULUS; (f_rowsum[len] += increment) %= MODULUS; } } int ans = 0; for (int i = 1; i <= n; ++i) for (int j = 0; j < ALPHA; ++j) ans = ((long long)ans + (long long)f[i][j] * binom[n - 1][i - 1]) % MODULUS; printf( %d n , ans); return 0; }
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module nmac_crc_check(
clk,
wr_clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
port_error,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input wr_clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output port_error;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg port_error;
reg [2:0]current_state;
parameter idle=3'b0,
transmit=3'b001,
wait_crcbad=3'b010,
discard=3'b011;
always@(posedge clk or negedge reset)
if(!reset)
begin
crc_data_valid<=1'b0;
crc_empty<=4'b0;
start_of_pkt<=1'b0;
end_of_pkt<=1'b0;
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b101)//header;
begin
in_pkt_rdreq<=1'b1;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
start_of_pkt<=1'b1;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
else if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
end_of_pkt<=1'b1;
crc_empty<=4'b1111-in_pkt_q[135:132];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=wait_crcbad;
end
else//middle;
begin
in_pkt_rdreq<=1'b1;
start_of_pkt<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
wait_crcbad:
begin
end_of_pkt<=1'b0;
crc_empty<=4'b0;
crc_data_valid<=1'b0;
out_pkt_wrreq<=1'b0;
if(crc_bad_valid==1'b1)
begin
if(crc_bad==1'b1)//error;
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b0;
port_error <= 1'b1;
end
else
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
end
current_state<=idle;
end
else
begin
current_state<=wait_crcbad;
end
end//end wait_crcbad;
discard:
begin
in_valid_rdreq<=1'b0;
in_pkt_rdreq<=1'b1;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in_pkt_q[138:136]==3'b111)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
current_state<=idle;
end
endcase
end
reg [127:0]crc_data;
reg crc_data_valid;
reg [3:0]crc_empty;
reg start_of_pkt;
reg end_of_pkt;
wire crc_bad_valid;
wire crc_bad;
check_ip check_ip0(
.clk(clk),
.data(crc_data),
.datavalid(crc_data_valid),
.empty(crc_empty),
.endofpacket(end_of_pkt),
.reset_n(reset),
.startofpacket(start_of_pkt),
.crcbad(crc_bad),
.crcvalid(crc_bad_valid)
);
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
asy_256_139 asy_256_139(
.aclr(!reset),
.data(in_pkt),
.rdclk(clk),
.rdreq(in_pkt_rdreq),
.wrclk(wr_clk),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.wrusedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
asy_64_1 asy_64_1(
.aclr(!reset),
.data(in_valid),
.rdclk(clk),
.rdreq(in_valid_rdreq),
.wrclk(wr_clk),
.wrreq(in_valid_wrreq),
.q(in_valid_q),
.rdempty(in_valid_empty)
);
endmodule
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#include <bits/stdc++.h> using namespace std; long long int rowblk[200005]; long long int colblk[200005]; long long int col[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int l, n, i, j, k, m; cin >> n >> m; for (i = 1; i <= m; i++) { cin >> k >> l; rowblk[k] = 1; colblk[l] = 1; } long long int cnt = 0; for (i = 2; i < n; i++) { if (colblk[i] == 0) { cnt++; col[i] = 1; } } for (i = 2; i < n; i++) { if (rowblk[i] == 0) { if (n % 2 != 0 && i == n / 2 + 1) { if (col[i] == 0) cnt++; } else { cnt++; } } } cout << cnt << endl; return 0; }
|
#include <bits/stdc++.h> const int mod = 998244353; using namespace std; inline int read() { int f = 1, x = 0; char s = getchar(); while (!isdigit(s)) { if (s == - ) f = -1; s = getchar(); } while (isdigit(s)) { x = (x << 1) + (x << 3) + (s ^ 48), s = getchar(); } return x * f; } int n, a[500100], is[500100], prime[500100], tot, ans1[500100], ans2[500100]; inline void init(void) { for (int i = 2; i <= 4000; i++) { if (!is[i]) prime[++tot] = i; for (int j = 1; j <= tot && i * prime[j] <= 4000; j++) { is[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } } inline int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } signed main(void) { n = read(); init(); for (int i = 1; i <= n; i++) { ans1[i] = ans2[i] = -1; a[i] = read(); int t = a[i]; for (int j = 1; j <= tot; j++) { int mul = 1; while (t % prime[j] == 0) t /= prime[j], mul *= prime[j]; if (mul != 1 && a[i] / mul != 1) ans1[i] = mul, ans2[i] = a[i] / mul; } if (t != 1 && a[i] / t != 1) ans1[i] = t, ans2[i] = a[i] / t; } for (int i = 1; i <= n; i++) printf( %d , ans1[i]); puts( ); for (int i = 1; i <= n; i++) printf( %d , ans2[i]); return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_data_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module contains the data generation logic for the synthesizable
// testbench.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_data_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input wr_data_en,
input rd_data_valid,
output app_wdf_wren,
output reg [APPDATA_WIDTH-1:0] app_wdf_data,
output reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
localparam WR_IDLE_FIRST_DATA = 2'b00;
localparam WR_SECOND_DATA = 2'b01;
localparam WR_THIRD_DATA = 2'b10;
localparam WR_FOURTH_DATA = 2'b11;
localparam RD_IDLE_FIRST_DATA = 2'b00;
localparam RD_SECOND_DATA = 2'b01;
localparam RD_THIRD_DATA = 2'b10;
localparam RD_FOURTH_DATA = 2'b11;
reg [APPDATA_WIDTH-1:0] app_wdf_data_r;
reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data_r;
wire app_wdf_wren_r;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_fall;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_rise;
wire rd_data_valid_r;
reg [1:0] rd_state;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
wire [APPDATA_WIDTH-1:0] wr_data;
reg wr_data_en_r;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_fall
/* synthesis syn_maxfan = 2 */;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_rise
/* synthesis syn_maxfan = 2 */;
wire [(APPDATA_WIDTH/8)-1:0] wr_mask_data;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_fall;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_rise;
reg [1:0] wr_state;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
always @(posedge clk) begin
app_wdf_data_r <= wr_data;
app_wdf_mask_data_r <= wr_mask_data;
app_wdf_data <= app_wdf_data_r;
app_wdf_mask_data <= app_wdf_mask_data_r;
end
// inst ff for timing
FDRSE ff_wdf_wren
(
.Q (app_wdf_wren_r),
.C (clk),
.CE (1'b1),
.D (wr_data_en_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_wren_r
(
.Q (app_wdf_wren),
.C (clk),
.CE (1'b1),
.D (app_wdf_wren_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
//***************************************************************************
// DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE
//***************************************************************************
assign wr_data = {wr_data_fall, wr_data_rise};
assign wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};
//*****************************************************************
// For now, don't vary data masks
//*****************************************************************
assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};
assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};
//*****************************************************************
// Write data logic
//*****************************************************************
// write data generation
//synthesis attribute max_fanout of wr_data_fall is 2
//synthesis attribute max_fanout of wr_data_rise is 2
always @(posedge clk) begin
if (rst_r1) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'bx}};
wr_data_fall <= {(APPDATA_WIDTH/2){1'bx}};
wr_state <= WR_IDLE_FIRST_DATA;
end else begin
case (wr_state)
WR_IDLE_FIRST_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
wr_data_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
wr_state <= WR_SECOND_DATA;
end
WR_SECOND_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_data_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_state <= WR_THIRD_DATA;
end
WR_THIRD_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_data_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_state <= WR_FOURTH_DATA;
end
WR_FOURTH_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
wr_data_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
wr_state <= WR_IDLE_FIRST_DATA;
end
endcase
end
end
always @(posedge clk)
if (rst_r1)
wr_data_en_r <= 1'b0;
else
wr_data_en_r <= wr_data_en;
//*****************************************************************
// Read data logic
//*****************************************************************
// read comparison data generation
always @(posedge clk)
if (rst_r1) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'bx}};
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'bx}};
rd_state <= RD_IDLE_FIRST_DATA;
end else begin
case (rd_state)
RD_IDLE_FIRST_DATA:
if (rd_data_valid_r)
begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
rd_state <= RD_SECOND_DATA;
end
RD_SECOND_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_state <= RD_THIRD_DATA;
end
RD_THIRD_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_state <= RD_FOURTH_DATA;
end
RD_FOURTH_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
rd_data_pat_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
rd_state <= RD_IDLE_FIRST_DATA;
end
endcase
end
//data to the compare circuit during read
assign app_cmp_data = {rd_data_pat_fall, rd_data_pat_rise};
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (x == 0) return y; else return gcd(y % x, x); } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } bool sortbysize(string &s1, string &s2) { return s1.size() < s2.size(); } bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n, k, a, b, i, x, cnt = 0; cin >> n >> k; vector<pair<int, int>> v; map<int, int> mp; while (n--) { cin >> a >> b; v.push_back(make_pair(a, b)); mp[a]++; } sort(v.begin(), v.end(), sortinrev); for (i = 0; i < v.size();) { if (mp[v[i].first] > 1) { sort(v.begin() + i, v.begin() + i + mp[v[i].first], sortbysec); } i += mp[v[i].first]; } for (i = 0; i < v.size(); i++) { if (v[i].second == v[k - 1].second && v[i].first == v[k - 1].first) cnt++; } cout << cnt << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> pr; bool isp[1001]; void p() { memset(isp, true, sizeof isp); isp[0] = isp[1] = false; for (int i = 2; i < 1001; ++i) { if (!isp[i]) continue; pr.push_back(i); for (int j = 2 * i; j < 1001; j += i) isp[j] = false; } } int main() { p(); string s; cin >> s; int n = s.length(); bool ans = 0; set<int> st; for (int i = 0; i < pr.size(); ++i) { if (pr[i] > n / 2) break; for (int j = 1; pr[i] * j <= n; ++j) st.insert(pr[i] * j); } int cnt[26], mx = 0, ch = -1; memset(cnt, 0, sizeof cnt); for (int i = 0; i < n; ++i) { cnt[s[i] - a ]++; if (mx < cnt[s[i] - a ]) { mx = cnt[s[i] - a ]; ch = s[i]; } } if (mx >= st.size()) { cout << YES << endl; string ans = s; for (int i = 0; i < n; ++i) ans[i] = ; for (set<int>::iterator it = st.begin(); it != st.end(); ++it) ans[*it - 1] = ch; cnt[ch - a ] -= st.size(); int idx = 0; for (int i = 0; i < 26; ++i) for (int j = 0; j < cnt[i]; ++j) { while (ans[idx] != ) ++idx; ans[idx] = i + a ; } cout << ans << endl; } else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = (int)1e9 + 9; bool cmp(const pair<int, int> &a, const pair<int, int> &b) { return a.first < b.first; } int main() { int n, m; cin >> n >> m; vector<pair<int, int> > k(n); for (int(i) = (0); (i) < (n); ++(i)) { cin >> k[i].first >> k[i].second; } sort(((k).begin()), ((k).end()), cmp); double ans = oo; for (int(i) = (0); (i) < (n); ++(i)) { ans = min(ans, (double)k[i].first / (double)k[i].second); } ans *= (double)m; cout << fixed << setprecision(8) << ans << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColokbM_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColokbM (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColokbM_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColokbM_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module mytb
#(
parameter integer register_size = 32,
parameter integer register_count = 32,
parameter integer input_vector_size = 32,
parameter integer output_vector_size = 32,
parameter integer fifo_depth = 512,
parameter integer saddr_w = 24
)
();
// testbench controlled signals
reg logic_reset;
reg clk;
// hack: stuff all configuration registers into an array
reg [register_size-1:0] config_regs [0:register_count-1];
reg [input_vector_size-1:0] input_vector;
wire [output_vector_size-1:0] output_vector;
// load configuration
integer configfile, inputfile, outputfile;
integer configline = 0;
string configfname, inputfname, outputfname;
initial begin
if (!$value$plusargs("configfile=%s", configfname)) begin
$display("FATAL: specify configuration file name with +configfile=<FILE>");
$finish();
end
configfile=$fopen(configfname, "r");
if (!configfile) begin
$display("FATAL: could not open configuration file");
$finish();
end
while (!$feof(configfile)) begin
if (configline < register_count) begin
$fscanf(configfile, "%h\n", config_regs[configline]);
configline = configline + 1;
end
else begin
$display("WARNING: too many values in configuration file");
end
end
$display("INFO: loaded configuration");
end
initial begin
$dumpfile("mytb.vcd");
$dumpvars(0, mytb);
input_vector <= 0;
logic_reset <= 1;
clk <= 0;
#10 logic_reset <= 0;
#10000 $finish();
end
// generate clock
always begin
#1 clk <= !clk;
end
// read input vector
initial begin
#10; //wait for reset to clear
if (!$value$plusargs("inputfile=%s", inputfname)) begin
$display("FATAL: specify input file name with +inputfile=<FILE>");
$finish();
end
inputfile=$fopen(inputfname, "r");
if (!inputfile) begin
$display("FATAL: could not open input file");
$finish();
end
while(!$feof(inputfile)) begin
$fscanf(inputfile, "%h\n", input_vector);
#2; // wait for next clock cycle
end
// finish simulation if we get here, as there is no more input
$display("INFO: no more input available, terminating");
$finish();
end
// write output vector
initial begin
if (!$value$plusargs("outputfile=%s", outputfname)) begin
$display("WARN: using default output.txt as output file");
outputfname = "output.txt";
end
outputfile=$fopen(outputfname, "w");
if (!outputfile) begin
$display("FATAL: could not open output file for writing");
$finish();
end
while (1) begin
$fwrite(outputfile, "%h\n", output_vector);
#2; // wait for next clock cycle
end
end
// instantiate here
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e6 + 7; const int INF = 0x7fffffff; int n, m; struct DATA { int strid; int index; }; vector<DATA> vec; string str[maxn]; char ans[maxn]; bool cmp(DATA a, DATA b) { return a.index < b.index; } int main() { while (cin >> n) { memset(ans, 0, sizeof(ans)); vec.clear(); for (int i = 0; i < n; i++) { int num; cin >> str[i]; scanf( %d , &num); for (int j = 0; j < num; j++) { int k; scanf( %d , &k); k--; DATA t; t.strid = i; t.index = k; vec.push_back(t); } } int last = -1; sort(vec.begin(), vec.end(), cmp); for (int i = 0; i < vec.size(); i++) { for (int j = max(last + 1, vec[i].index); j < vec[i].index + str[vec[i].strid].size(); j++) { ans[j] = str[vec[i].strid][j - vec[i].index]; last = max(last, j); } } for (int i = 0; i <= last; i++) { if (ans[i] != 0) printf( %c , ans[i]); else { printf( a ); } } puts( ); } return 0; }
|
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
`timescale 1 ns / 10 ps
module mult_unit_test ();
reg clk, rstb;
reg [2:0] command;
reg [1:0] tcmd;
wire idle;
wire [26:0] tdata_0, tdata_1, tdata_2;
initial begin
clk = 0;
rstb = 0;
command = 0;
tcmd = 0;
#5 rstb = 1;
#8 command = 3'b100;
#8 command = '0;
#640 tcmd = 2'b01;
command = 3'b010;
#8 tcmd = '0;
command = '0;
#504 command = 3'b011;
#8 command = '0;
#504 command = 3'b011;
#8 command = '0;
#504 command = 3'b011;
#8 command = '0;
#504 command = 3'b101;
#8 command = '0;
end
initial begin
#686 for(int i=0; i<40; i++) begin
$display("%x ", imu.multins.result_reg[i]);
end
$display("\n");
end
always @(clk) clk <= #4 ~clk;
table_control t ( .clk (clk)
, .ctrl_reset_n (rstb)
, .tdatai ('0)
, .twraddr ('0)
, .twren ('0)
, .tdata_0 (tdata_0)
, .tdata_1 (tdata_1)
, .tdata_2 (tdata_2)
, .command (tcmd)
, .idle (t_idle)
);
mult_unit #( .mult_addr (0)
, .e_words (4)
, .c_size (1024)
) imu
( .clk (clk)
, .ctrl_reset_n (rstb)
, .unit_select ('0)
, .g_addr ('0)
, .g_data ('0)
, .g_rden ('0)
, .g_wren ('0)
, .g_q ()
, .e_wraddr ('0)
, .e_data ('0)
, .e_wren ('0)
, .command (command)
, .idle (idle)
, .tdata_0 (tdata_0)
, .tdata_1 (tdata_1)
, .tdata_2 (tdata_2)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_bb.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No user `defines in this module
module ent_bb
//
// Generated Module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } template <class T> T min(T a, T b, T c, T d) { return min(a, min(b, min(c, d))); } template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } template <class T> T max(T a, T b, T c, T d) { return max(a, max(b, max(c, d))); } bool cmp(int a, int b) { return a > b; } long long GCD(long long a, long long b) { return (a % b) ? GCD(b, a % b) : b; } const string namePro = tmp ; int main() { int n; scanf( %d , &n); int cnt = 0; int ans = 0; stack<int> stk; for (int i = (1); i <= (2 * n); ++i) { string s; cin >> s; if (s == add ) { int x; scanf( %d , &x); stk.push(x); } else { ++cnt; if (stk.size() && stk.top() == cnt) stk.pop(); else if (stk.empty()) continue; else { while (stk.size()) stk.pop(); ++ans; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; long long k, n; int index_1[(int)(1e6 + 5)], num = 0; void solve() { cin >> k >> s; n = s.size(); if (k == 0) { long long last = 0, ans = 0; for (int i = 0; i < n; i++) { if (s[i] == 0 ) last++; else { ans += last * (last + 1) / 2; last = 0; } } ans += last * (last + 1) / 2; cout << ans; return; } for (int i = 0; i < n; i++) { if (s[i] == 1 ) index_1[num++] = i; } long long ans = 0; for (int i = k - 1; i < num; i++) { long long t1 = n - 1 - index_1[i] + 1; if (i < num - 1) t1 = index_1[i + 1] - index_1[i]; long long t2 = index_1[i - (k - 1)] - 0 + 1; if (i - (k - 1) > 0) t2 = index_1[i - (k - 1)] - index_1[i - (k - 1) - 1]; ans += t1 * t2; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (b) { a %= b; swap(a, b); } return a; } int main() { int t; cin >> t; while (t--) { long long x, y; cin >> x >> y; if (gcd(x, y) == 1) { cout << FINITE << endl; } else { cout << INFINITE << endl; } } }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) const int inf = 0x3f3f3f3f, Inf = 0x7fffffff; const long long INF = 0x7fffffffffffffff; const double eps = 1e-8; unsigned int seed = 19260817; const unsigned int _RAND_MAX_ = 4294967295u; __inline__ __attribute__((always_inline)) unsigned int Rand() { return seed = seed * 998244353u + 1000000007u; } template <typename _Tp> _Tp gcd(const _Tp &a, const _Tp &b) { return (!b) ? a : gcd(b, a % b); } template <typename _Tp> __inline__ __attribute__((always_inline)) _Tp abs(const _Tp &a) { return a > 0 ? a : -a; } template <typename _Tp> __inline__ __attribute__((always_inline)) _Tp max(const _Tp &a, const _Tp &b) { return a < b ? b : a; } template <typename _Tp> __inline__ __attribute__((always_inline)) _Tp min(const _Tp &a, const _Tp &b) { return a < b ? a : b; } template <typename _Tp> __inline__ __attribute__((always_inline)) void chmax(_Tp &a, const _Tp &b) { (a < b) && (a = b); } template <typename _Tp> __inline__ __attribute__((always_inline)) void chmin(_Tp &a, const _Tp &b) { (a > b) && (a = b); } template <typename _Tp> __inline__ __attribute__((always_inline)) bool _cmp(const _Tp &a, const _Tp &b) { return abs(a - b) <= eps; } template <typename _Tp> __inline__ __attribute__((always_inline)) void read(_Tp &x) { register char ch(getchar()); bool f(false); while (ch < 48 || ch > 57) f |= ch == 45, ch = getchar(); x = ch & 15, ch = getchar(); while (ch >= 48 && ch <= 57) x = (((x << 2) + x) << 1) + (ch & 15), ch = getchar(); if (f) x = -x; } template <typename _Tp, typename... Args> __inline__ __attribute__((always_inline)) void read(_Tp &t, Args &...args) { read(t); read(args...); } __inline__ __attribute__((always_inline)) int read_str(char *s) { register char ch(getchar()); while (ch == || ch == r || ch == n ) ch = getchar(); register char *tar = s; *tar = ch, ch = getchar(); while (ch != && ch != r && ch != n && ch != EOF) *(++tar) = ch, ch = getchar(); return tar - s + 1; } const int N = 1200005; struct node { bool l, r; int ans; __inline__ __attribute__((always_inline)) node operator+( const node &o) const { return (node){l, o.r, ans + o.ans - (r == o.l)}; } }; int L[N], R[N]; int t[N]; int a[N]; struct seg_tr { struct Node { int ls, rs; node val1, val2; bool tag; } f[N << 1]; int node_cnt; __inline__ __attribute__((always_inline)) void PushUp(int x) { f[x].val1 = f[f[x].ls].val1 + f[f[x].rs].val1; f[x].val2 = f[f[x].ls].val2 + f[f[x].rs].val2; } int build(int l, int r) { int cur = ++node_cnt; f[cur].tag = 0; if (l == r) { f[cur].ls = f[cur].rs = 0; f[cur].val1 = (node){a[l] == 0, a[l] == 0, 1}; f[cur].val2 = (node){a[l] == 1, a[l] == 1, 1}; return cur; } int mid = (l + r) >> 1; f[cur].ls = build(l, mid); f[cur].rs = build(mid + 1, r); PushUp(cur); return cur; } __inline__ __attribute__((always_inline)) void upd(int cur) { f[cur].tag ^= 1; std::swap(f[cur].val1, f[cur].val2); } __inline__ __attribute__((always_inline)) void PushDown(int cur) { if (f[cur].tag) { upd(f[cur].ls); upd(f[cur].rs); f[cur].tag = 0; } } void Update(int L, int R, int l, int r, int cur) { if (L <= l && r <= R) { upd(cur); return; } PushDown(cur); int mid = (l + r) >> 1; if (L <= mid) Update(L, R, l, mid, f[cur].ls); if (R > mid) Update(L, R, mid + 1, r, f[cur].rs); PushUp(cur); } __inline__ __attribute__((always_inline)) int Query() { return f[1].val1.ans; } } tr; void MAIN() { tr.node_cnt = 0; int n; read(n); int len = 0; for (int i = 1; i <= n; ++i) { read(L[i], R[i]); t[++len] = L[i]; t[++len] = R[i]; } std::sort(t + 1, t + len + 1); len = std::unique(t + 1, t + len + 1) - t - 1; memset(a, 0, 8 * (len + 2)); for (int i = 1; i <= n; ++i) { L[i] = std::lower_bound(t + 1, t + len + 1, L[i]) - t; R[i] = std::lower_bound(t + 1, t + len + 1, R[i]) - t; L[i] <<= 1; R[i] <<= 1; ++a[L[i]]; --a[R[i] + 1]; } len <<= 1; for (int i = 1; i <= len; ++i) a[i] += a[i - 1]; int root = tr.build(1, len); int ans = 0; for (int i = 1; i <= n; ++i) { tr.Update(L[i], R[i], 1, len, root); chmax(ans, tr.Query() >> 1); tr.Update(L[i], R[i], 1, len, root); } printf( %d n , ans); } int main() { int _; read(_); while (_--) MAIN(); return 0; }
|
/*
* In this example, the set and clr are both synchronous. This checks
* that this complex case is handled correctly.
*/
module main;
reg Q, clk, rst, set, clr;
(* ivl_synthesis_on *)
always@(posedge clk or posedge rst)
begin
if (rst)
Q <= 1'b0;
else if (clr)
Q <= 1'b0;
else if (set)
Q <= 1'b1;
else
Q <= Q;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 0;
set = 0;
clr = 0;
#1 rst = 1;
#1 rst = 0;
if (Q !== 0) begin
$display("FAILED -- rst");
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED -- 1 clk");
$finish;
end
#1 set = 1;
#1 ;
if (Q !== 0) begin
$display("FAILED -- 1 set (no clk)");
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 1) begin
$display("FAILED -- 1 set");
$finish;
end
#1 clr = 1;
#1 ;
if (Q !== 1) begin
$display("FAILED -- 1 clr+set (no clk)");
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED -- 1 clr+set");
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED -- 2 clr+set");
$finish;
end
#1 set = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED -- 1 set+clr");
$finish;
end
#1 clr = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 1) begin
$display("FAILED -- 1 set-clr");
$finish;
end
$display("PASSED");
$finish;
end
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:54:18 03/09/2016
// Design Name: mojo_top
// Module Name: C:/Users/matt/Documents/projects/mojo/i2c-eeprom/testbench_mojo_top.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mojo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_mojo_top;
// Inputs
reg clk;
reg rst_n;
reg cclk;
reg spi_ss;
reg spi_mosi;
reg spi_sck;
reg avr_tx;
reg avr_rx_busy;
// Outputs
wire [7:0] led;
wire spi_miso;
wire [3:0] spi_channel;
wire avr_rx;
wire i2c_scl;
wire i2c_clk_in;
// Bidirs
wire i2c_sda;
// Instantiate the Unit Under Test (UUT)
mojo_top uut (
.clk(clk),
.rst_n(rst_n),
.cclk(cclk),
.led(led),
.spi_miso(spi_miso),
.spi_ss(spi_ss),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_channel(spi_channel),
.avr_tx(avr_tx),
.avr_rx(avr_rx),
.avr_rx_busy(avr_rx_busy),
.i2c_scl(i2c_scl),
.i2c_sda(i2c_sda),
.i2c_clk_in(i2c_clk_in)
);
wire A0 = 0;
wire A1 = 0;
wire A2 = 0;
wire WP = 0;
wire reset = ~rst_n;
M24FC512 eeprom (
.A0(A0),
.A1(A1),
.A2(A2),
.WP(WP),
.SDA(i2c_sda),
.SCL(i2c_scl),
.RESET(reset)
);
initial begin
// Initialize Inputs
clk = 0;
forever begin
clk = #1 ~clk;
end
end
initial begin
// Initialize Inputs
rst_n = 0;
cclk = 0;
spi_ss = 0;
spi_mosi = 0;
spi_sck = 0;
avr_tx = 0;
avr_rx_busy = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
cclk = 1;
rst_n = 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_4_V
`define SKY130_FD_SC_HS__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_4 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_4_V
|
// MBT 5/1/2017 Fast simulation mastercalibration module
//
// FPGA calibration module (example, only implements Phase 1 and dummy Phase 0,2,3)
//
// See BSG Source Synchronous I/O for specification of this.
//
// everything beginning with "out" is the output channel clock
// everything beginning with "in" is the input channel clock
//
// respect the clock domains!
//
// tests_lp defines the number of real tests; but we have one more "fake"
// test at the end, which causes activation or deactivation of the channel
//
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master #(parameter `BSG_INV_PARAM( width_p )
, parameter lg_token_width_p = 6
, parameter lg_out_prepare_hold_cycles_p = 6
// bit vector
, parameter bypass_test_p = 5'b0
, parameter tests_lp = 5
, parameter verbose_lp = 1
)
(// output channel
input out_clk_i
, input out_reset_i // note this is just a synchronized version of core_reset
// we can do calibration in parallel, or channel-by-channel
, input [$clog2(tests_lp+1)-1:0] out_calibration_state_i
, input out_calib_prepare_i // essentially the reset signal
// ignore, we assume all channels are blessed
, input out_channel_blessed_i
// this is used to force data on to the output channel
// (calibration modes 0 and 1)
, output out_override_en_o
, output [width_p+1-1:0] out_override_valid_data_o
// ignore
, input out_override_is_posedge_i
// whether the test passed
, output [tests_lp+1-1:0] out_test_pass_r_o
// ignore
, input in_clk_i
, input in_reset_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_neg_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_pos_i
// hardwired to zero
, output out_infinite_credits_o
);
assign out_infinite_credits_o = 1'b0;
// memory mapped registers
logic [width_p+1-1:0] valid_data_r; // 0
logic override_r; // 1
logic [tests_lp+1-1:0] out_test_pass_r; // 2
logic [$clog2(tests_lp+1):0] match_reg_r; // 3
assign out_override_valid_data_o = valid_data_r;
assign out_override_en_o = override_r;
assign out_test_pass_r_o = out_test_pass_r;
//
// opcode4 <addr2>, <data14>
//
wire v_lo, v_li;
wire [15:0] data_lo, data_li;
wire yumi_li;
localparam match_size_lp = $clog2(tests_lp+1)+1;
// handle opcode4 -> send
// we convert this into a memory mapped write
always_ff @(posedge out_clk_i)
if (out_reset_i)
begin
valid_data_r <= 0;
override_r <= 0;
out_test_pass_r <= 0;
match_reg_r <= 0;
end
else
begin
if (v_lo)
begin
if (data_lo[15:14] == 0)
valid_data_r <= data_lo[0+:width_p+1];
else
if (data_lo[15:14] == 1)
override_r <= data_lo[0];
else
if (data_lo[15:14] == 2)
out_test_pass_r <= data_lo[0+:tests_lp+1];
else
if (data_lo[15:14] == 3)
match_reg_r <= data_lo[0+:$clog2(tests_lp+1)+1];
end
end // else: !if(out_reset_i)
assign yumi_li = v_lo;
// handle opcode -> receive
assign data_li = 16'b0;
assign v_li = (match_reg_r == {out_calib_prepare_i, out_calibration_state_i});
localparam rom_addr_width_lp = 6;
wire [rom_addr_width_lp-1:0] rom_addr_li;
wire [4+16-1:0] rom_data_lo;
bsg_fsb_node_trace_replay
#(.ring_width_p(16)
,.rom_addr_width_p(rom_addr_width_lp)
) tr
(.clk_i(out_clk_i)
,.reset_i(out_reset_i)
,.en_i(1'b1)
,.v_i (v_li)
,.data_i (data_li)
,.ready_o() // ignored
,.v_o (v_lo)
,.data_o (data_lo)
,.yumi_i (yumi_li)
,.rom_addr_o(rom_addr_li)
,.rom_data_i(rom_data_lo)
,.done_o() // cheeky mapping to done signal
,.error_o()
);
// generated with bsg_fsb_master_rom
bsg_comm_link_master_calib_skip_rom
#(.width_p(4+16)
,.addr_width_p(rom_addr_width_lp)
) comm_link_master_rom
(.addr_i(rom_addr_li)
,.data_o(rom_data_lo)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master)
|
// mbt 2-12-16
//
// this goes in silicon
//
//
`include "bsg_defines.v"
module bsg_chip_rocket #(
parameter num_channels_p = 4
, parameter channel_width_p = 8
, parameter enabled_at_start_vec_p = 0
, parameter master_p = 0
, parameter master_to_slave_speedup_p = 100
, parameter master_bypass_test_p = 5'b00000
, parameter nodes_lp = 2
, parameter uniqueness_p = 0
)
(
input core_clk_i
, input async_reset_i
, input io_master_clk_i
// input from i/o
, input [num_channels_p-1:0] io_clk_tline_i // clk
, input [num_channels_p-1:0] io_valid_tline_i
, input [channel_width_p-1:0] io_data_tline_i [num_channels_p-1:0]
, output [num_channels_p-1:0] io_token_clk_tline_o // clk
// out to i/o
, output [num_channels_p-1:0] im_clk_tline_o // clk
, output [num_channels_p-1:0] im_valid_tline_o
, output [channel_width_p-1:0] im_data_tline_o [num_channels_p-1:0]
, input [num_channels_p-1:0] token_clk_tline_i // clk
// this signal is the post-calibration reset signal
// synchronous to the core clock
, output core_reset_o
);
// size of RingPacketType, in bytes
localparam ring_bytes_lp = 10;
localparam ring_width_lp = ring_bytes_lp*channel_width_p;
// into nodes (fsb interface)
wire [nodes_lp-1:0] core_node_v_A;
wire [ring_width_lp-1:0] core_node_data_A [nodes_lp-1:0];
wire [nodes_lp-1:0] core_node_ready_A;
// into nodes (control)
wire [nodes_lp-1:0] core_node_en_r_lo;
wire [nodes_lp-1:0] core_node_reset_r_lo;
// out of nodes (fsb interface)
wire [nodes_lp-1:0] core_node_v_B;
wire [ring_width_lp-1:0] core_node_data_B [nodes_lp-1:0];
wire [nodes_lp-1:0] core_node_yumi_B;
wire [nodes_lp-1:0] core_node_reset_lo;
bsg_rocket_core_fsb #(.nasti_destid_p(1)
.htif_destid_p(0)
) core
(.clk_i (core_clk_i )
// the rocket core uses two ports on the FSB
// we say, it is in reset if either port is in
// reset; and that it is in enable only if both ports
// are in enable.
,.reset_i (|core_node_en_r_lo )
,.enable_i(&core_node_reset_r_lo )
,.v_i (core_node_v_A )
,.data_i (core_node_data_A )
,.ready_o(core_node_ready_A)
,.v_o (core_node_v_B )
..data_o (core_node_data_B )
,.yumi_i (core_node_yumi_B )
);
bsg_comm_link #(.channel_width_p (channel_width_p)
, .core_channels_p (ring_bytes_lp )
, .link_channels_p (num_channels_p )
, .nodes_p (nodes_lp)
, .master_p (0)
) comm_link
(.core_clk_i (core_clk_i )
, .async_reset_i (async_reset_i )
, .io_master_clk_i (io_master_clk_i )
// into nodes (control)
, .core_node_reset_r_o(core_node_reset_lo)
, .core_node_en_r_o (core_node_en_r_lo )
// into nodes (fsb interface)
, .core_node_v_o (core_node_v_A )
, .core_node_data_o (core_node_data_A )
, .core_node_ready_i (core_node_ready_A)
// out of nodes (fsb interface)
, .core_node_v_i (core_node_v_B )
, .core_node_data_i(core_node_data_B)
, .core_node_yumi_o(core_node_yumi_B)
// in from i/o
, .io_valid_tline_i (io_valid_tline_i )
, .io_data_tline_i (io_data_tline_i )
, .io_clk_tline_i (io_clk_tline_i ) // clk
, .io_token_clk_tline_o(io_token_clk_tline_o) // clk
// out to i/o
, .im_valid_tline_o(im_valid_tline_o)
, .im_data_tline_o ( im_data_tline_o)
, .im_clk_tline_o ( im_clk_tline_o) // clk
, .im_slave_reset_tline_r_o () // unused by slave comm link
, .token_clk_tline_i (token_clk_tline_i ) // clk
,.core_calib_reset_r_o(core_reset_o)
// don't use
, .core_async_reset_danger_o()
);
endmodule
|
module fifo(
input w_clk,
input r_clk,
input we,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [15 :0] mask,
output [DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
parameter DATA_WIDTH = 1;
parameter ASYNC = 0;
wire [15:0] _d, _q;
genvar i;
generate
if (DATA_WIDTH <= 16 & DATA_WIDTH > 8)
begin
assign _d = { {(16 - DATA_WIDTH){1'b0}}, {d} };
assign q = { {(16 - DATA_WIDTH){1'b0}}, {_q} };
fifo_#(
.MODE(0),
.ADDR_WIDTH(8),
.ASYNC(ASYNC)
) fifo_256x16_(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(mask) // only masked option
);
end // if (16 >= DATA_WIDTH > 8)
else if ( DATA_WIDTH <= 8 & DATA_WIDTH > 4)
begin
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = i < DATA_WIDTH ? d[i] : 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 2];
end
end
fifo_#(
.MODE(1),
.ADDR_WIDTH(9),
.ASYNC(ASYNC)
) fifo_512x8(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 8 >= DATA_WIDTH > 4)
else if ( DATA_WIDTH <= 4 & DATA_WIDTH > 2)
begin
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 4 + 1];
end
end
fifo_#(
.MODE(2),
.ADDR_WIDTH(10),
.ASYNC(ASYNC)
) fifo_1024x4(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 4 >= DATA_WIDTH > 2)
else if ( DATA_WIDTH <= 2 & DATA_WIDTH > 0)
begin
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 8 + 3];
end
end
fifo_#(
.MODE(3),
.ADDR_WIDTH(11),
.ASYNC(ASYNC)
) fifo_2048x2(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 2 >= DATA_WIDTH > 0)
endgenerate
endmodule // fifo
module fifo_(
input w_clk,
input r_clk,
input we,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
output [RAM_DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
function [ADDR_WIDTH :0] bin_to_gray;
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction // bin_to_gray
parameter MODE = 0;
parameter ADDR_WIDTH = 0;
parameter ASYNC = 0;
localparam RAM_ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
reg [ADDR_WIDTH - 1 : 0] raddr = 0, waddr = 0;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(_raddr),
.RCLK(r_clk),
.RCLKE(1'b1),
.RE(re),
.WADDR(_waddr),
.WCLK(w_clk),
.WCLKE(1'b1),
.WDATA(d),
.WE(we),
.MASK(mask)
);
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
always @ (posedge w_clk)
begin
if (we & ~full)
begin
waddr <= waddr + 1;
end
end
always @ (posedge r_clk)
begin
if (re & ~empty)
begin
raddr <= raddr + 1;
end
end
generate
if (ASYNC)
begin : async_ctrs
reg _full = 0, _empty = 1;
reg [ADDR_WIDTH : 0] wptr = 0, rptr = 0;
reg [ADDR_WIDTH : 0] rq1_wptr = 0, rq2_wptr = 0;
reg [ADDR_WIDTH : 0] wq1_rptr = 0, wq2_rptr = 0;
wire [ADDR_WIDTH : 0] _wptr, _rptr;
assign _wptr = bin_to_gray(waddr + (we & ~full));
assign _rptr = bin_to_gray(raddr + (re & ~empty));
assign full = _full;
assign empty = _empty;
always @ (posedge w_clk)
begin
wptr <= _wptr;
_full <= (_wptr ==
{~wq2_rptr[ADDR_WIDTH:ADDR_WIDTH-1], wq2_rptr[ADDR_WIDTH-2:0]});
end
always @ (posedge r_clk)
begin
_empty <= (_rptr == rq2_wptr);
rptr <= _rptr;
end
always @ (posedge w_clk)
begin
wq1_rptr <= rptr;
wq2_rptr <= wq1_rptr;
end
always @ (posedge r_clk)
begin
rq1_wptr <= wptr;
rq2_wptr <= rq1_wptr;
end
end // if (ASYNC)
else
begin : sync_ctrs
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
assign full = &ctr;
assign empty = ~&ctr;
always @ (posedge w_clk)
begin
if (we & ~re & ~full)
begin
ctr <= ctr + 1;
end
else if(re & ~we & ~empty)
begin
ctr <= ctr - 1;
end
end // always @ (posedge w_clk)
end // else: !if(ASYNC)
endgenerate
endmodule // fifo_
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////
`define ADDR_CONTROL_REG 'h0
`define ADDR_STATUS_REG 'h1
`define ADDR_DATA_REG 'h2
module axi_interface(
//CLK
input FCLK_CLK0,
//RST
input RST_N,
//Signals towards register interface:
output reg [31:0] o_data_to_registers,
output reg o_wr_controll_reg, // Offset: 0x00
output reg o_wr_data_reg, // Offset: 0x08
input wire [31:0] i_controll_reg,
input wire [31:0] i_status_reg,
input wire [31:0] i_data_reg,
//AXI INTERFACE
input [31:0] AXI_araddr, // read address address (data)
input [2:0] AXI_arprot, // ???
output [0:0] AXI_arready, // read address ready
input [0:0] AXI_arvalid, // read address valid
input [31:0] AXI_awaddr, // write address address (channel data)
input [2:0] AXI_awprot, // write address ??
output [0:0] AXI_awready, // write address ready
input [0:0] AXI_awvalid, // write address valid
input [0:0] AXI_bready, // (write) response ready
output [1:0] AXI_bresp, // write response
output [0:0] AXI_bvalid, // write response valid
output reg [31:0] AXI_rdata, // read data
input [0:0] AXI_rready, // read ready
output [1:0] AXI_rresp, // read response
output reg [0:0] AXI_rvalid, // read valid
input [31:0] AXI_wdata, // write data
output [0:0] AXI_wready, // write ready
input [3:0] AXI_wstrb, // ??
input [0:0] AXI_wvalid // write valid
);
wire clk;
//wire reset;
assign reset = ~RST_N;
assign clk = FCLK_CLK0;
always @(*) begin
o_data_to_registers = AXI_wdata[31:0];
end
/// AXI interface
// WRITE -- this block control the enable of registers to write them from AXI
// Note that the second assignment will be valid in verilog.
always @(*) begin
o_wr_data_reg <= '0;
o_wr_controll_reg <= '0;
if (AXI_awvalid[0] & AXI_wvalid[0]) begin
if(AXI_awaddr[15:2] == `ADDR_CONTROL_REG) // BASE + 0x00
o_wr_controll_reg <= '1;
if(AXI_awaddr[15:2] == `ADDR_DATA_REG) // BASE + 0x08
o_wr_data_reg <= '1;
end
end
assign AXI_awready[0] = AXI_awvalid[0] & AXI_wvalid[0]; // AXI_awvalid;
assign AXI_wready[0] = AXI_awvalid[0] & AXI_wvalid[0]; // AXI_awvalid;
assign AXI_bvalid[0] = AXI_awvalid[0] & AXI_wvalid[0]; // 1'b1;
assign AXI_bresp = 2'h0;
// READ -- this block drive the AXI when the AXI bus-master reads a data.
always @(posedge clk) begin
AXI_rdata <= '0;
if (AXI_arvalid[0])
if(AXI_araddr[15:2] == `ADDR_CONTROL_REG) // BASE + 0x00
AXI_rdata <= i_controll_reg;
if(AXI_araddr[15:2] == `ADDR_STATUS_REG) // BASE + 0x04
AXI_rdata <= i_status_reg;
if(AXI_araddr[15:2] == `ADDR_DATA_REG) // BASE + 0x08
AXI_rdata <= i_data_reg;
end
always @(posedge clk) begin
if(reset)
AXI_rvalid[0] <= 1'b0;
else if(AXI_arvalid)
AXI_rvalid[0] <= 1'b1;
else if(AXI_rready)
AXI_rvalid[0] <= 1'b0;
end
assign AXI_arready[0] = AXI_arvalid[0];
assign AXI_rresp = 2'h0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_BLACKBOX_V
`define SKY130_FD_SC_LP__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// read_rs3 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// read_rs3_rs3 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
read_rs3_rs3,
read_rs3,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// value method read_rs3
input [4 : 0] read_rs3_rs3;
output [63 : 0] read_rs3;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_j
reg [4 : 0] rg_j;
wire [4 : 0] rg_j$D_IN;
wire rg_j$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3,
regfile$D_OUT_4;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// inputs to muxes for submodule ports
wire [4 : 0] MUX_rg_j$write_1__VAL_1;
wire MUX_rg_state$write_1__SEL_2;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = regfile$D_OUT_4 ;
// value method read_rs1_port2
assign read_rs1_port2 = regfile$D_OUT_3 ;
// value method read_rs2
assign read_rs2 = regfile$D_OUT_2 ;
// value method read_rs3
assign read_rs3 = regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(regfile$D_OUT_4),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop =
CAN_FIRE_RL_rl_reset_loop && !EN_write_rd ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_2 =
WILL_FIRE_RL_rl_reset_loop && rg_j == 5'd31 ;
assign MUX_rg_j$write_1__VAL_1 = rg_j + 5'd1 ;
// register rg_j
assign rg_j$D_IN =
WILL_FIRE_RL_rl_reset_loop ? MUX_rg_j$write_1__VAL_1 : 5'd1 ;
assign rg_j$EN = WILL_FIRE_RL_rl_reset_loop || WILL_FIRE_RL_rl_reset_start ;
// register rg_state
always@(EN_server_reset_request_put or
MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset_loop && rg_j == 5'd31 ||
EN_server_reset_request_put ||
WILL_FIRE_RL_rl_reset_start ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs3_rs3 ;
assign regfile$ADDR_2 = read_rs2_rs2 ;
assign regfile$ADDR_3 = read_rs1_port2_rs1 ;
assign regfile$ADDR_4 = read_rs1_rs1 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = EN_write_rd ? write_rd_rd : rg_j ;
assign regfile$D_IN = EN_write_rd ? write_rd_rd_val : 64'd0 ;
assign regfile$WE = EN_write_rd || WILL_FIRE_RL_rl_reset_loop ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_j$EN) rg_j <= `BSV_ASSIGNMENT_DELAY rg_j$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_j = 5'h0A;
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFPR_RegFile
|
#include <bits/stdc++.h> using namespace std; long long m; long long f(long long a) { long long res = 0; for (long long k = 2;; k++) { long long k3 = k * k * k; if (k3 > a) break; if (res > m - a / k3) return -1; res += a / k3; } return res; } int main() { cin >> m; long long l = 1, r = 9000000000000000000LL; while (l < r) { long long mid = (l + r) >> 1; long long rr = f(mid); if (rr >= m || rr == -1) r = mid; else l = mid + 1; } while (f(l - 1) == m) l--; cout << (f(l) == m ? l : -1) << endl; return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone IV (E) devices Input Buffer Primitive */
module cycloneive_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (E) devices Output Buffer Primitive */
module cycloneive_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
module cycloneive_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cycloneive_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // cycloneive_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* Cyclone IV E altpll clearbox model */
(* blackbox *)
module cycloneive_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneive_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:31:02 05/20/2014
// Design Name: mips32
// Module Name: F:/mips32/mips32test.v
// Project Name: mips32
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mips32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mips32test;
// Inputs
reg rst;
reg clk;
reg [4:0] interrupts;
// Outputs
wire [31:0] port_PC;
wire [31:0] port_inst;
wire [31:0] port_alu;
// Instantiate the Unit Under Test (UUT)
mips32 uut (
.port_PC(port_PC),
.port_inst(port_inst),
.port_alu(port_alu),
.rst(rst),
.clk(clk),
.interrupts(interrupts)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
interrupts = 0;
// Wait 100 ns for global reset to finish
#100 rst = 1;
#20 rst = 0;
// Add stimulus here
end
initial begin
forever #20 clk = ~clk;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; struct node { long long int u, v, w; } edge[N]; bool cmp(node a, node b) { return a.w < b.w; } long long int n, m, k, v, ans = 0; bool special[N]; long long int root[N]; long long int find_root(long long int x) { if (root[x] == x) return x; return root[x] = find_root(root[x]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (long long int i = 0; i <= k - 1; ++i) { cin >> v; special[v] = true; } for (long long int i = 0; i <= m - 1; ++i) { cin >> edge[i].u >> edge[i].v >> edge[i].w; } sort(edge, edge + m, cmp); for (long long int i = 1; i <= n; ++i) root[i] = i; for (long long int i = 0; i <= m - 1; ++i) { long long int root_u = find_root(edge[i].u); long long int root_v = find_root(edge[i].v); if (root_u != root_v) { if (special[root_u] && special[root_v]) { ans = max(ans, edge[i].w); } if (special[root_u]) root[root_v] = root_u; else root[root_u] = root_v; } } for (long long int j = 1; j <= n; ++j) { if (special[j]) cout << ans << ; } return 0; }
|
`timescale 1ns / 1ps
module Arkanoid(
input iCLK_50,
input btn_W, btn_E, btn_N, btn_S,
input [3:0] iSW,
input iROT_A, iROT_B,
output oVGA_R, oVGA_G, oVGA_B, oHS, oVS,
output [7:0] oLED
);
localparam BALL_NUM = 2;
localparam SHOT_NUM = 2;
reg clk_25;
wire middle, b_dis;
wire [4:0] p_speed;
wire [9:0] p_x, p_y, g_x, g_y;
wire reset, start, btn_r, btn_l;
wire rotary_event, rotary_right;
wire [5:0] b_radius, p_radius;
wire [1:0] b_active;
wire [2:0] g_kind;
wire g_active;
wire [BALL_NUM*10-1:0] b_x, b_y;
wire [10:0] vcounter; // 0~479
wire [11:0] hcounter; // 0~639
wire [3:0] out_back, out_paddle, out_block, out_ball, out_bmem, bm_block, out_gift;
wire [4:0] out_row, out_col, bm_row, bm_col;
wire [1:0] bm_stage, bm_func;
wire bm_ready, bm_enable;
wire st_init, st_dead;
// generate a 25Mhz clock
always @(posedge iCLK_50)
clk_25 = ~clk_25;
// Buttons
syn_edge_detect sed1(iCLK_50, reset, btn_E, btn_r);
syn_edge_detect sed2(iCLK_50, reset, btn_W, btn_l);
syn_edge_detect sed3(iCLK_50, reset, btn_S, start);
// Rotation detection
Rotation_direction r_dir(.CLK(iCLK_50), .ROT_A(iROT_A), .ROT_B(iROT_B),
.rotary_event(rotary_event), .rotary_right(rotary_right));
// Game control
// Paddle control
paddle_control pd_control(.clock(iCLK_50), .reset(reset), .enable(1'b1), .rotary_event(rotary_event),
.rotary_right(rotary_right), .speed(p_speed), .radius(p_radius), .middle(middle), .paddle_x(p_x), .paddle_y(p_y));
state_control s_control(.clock(iCLK_50), .reset(reset), .start(start), .btn_l(btn_l), .btn_r(btn_r), .iSW(iSW),
.bm_ready(bm_ready), .bm_block(bm_block),
.p_x(p_x), .p_y(p_y), .p_radius(p_radius),
.b_active(b_active), .b_radius(b_radius), .o_bx(b_x), .o_by(b_y),
.bm_enable(bm_enable), .bm_row(bm_row), .bm_col(bm_col), .bm_func(bm_func), .bm_stage(bm_stage),
.g_x(g_x), .g_y(g_y), .g_kind(g_kind), .g_active(g_active),
.middle(middle), .p_speed(p_speed), .b_dis(b_dis),
.hp(oLED[7:2]), .dead(st_dead), .init(st_init), .win(st_win));
block_memory b_mem(.clock(iCLK_50), .reset(reset), .enable(bm_enable),
.row1(bm_row), .row2(out_row), .col1(bm_col), .col2(out_col),
.func(bm_func), .stage(bm_stage), .block1(bm_block), .block2(out_bmem), .ready(bm_ready));
// Game display
draw_game d_game(.clock(clk_25), .reset(reset), .visible(visible),
.dead(st_dead), .init(st_init), .win(st_win),
.in_ball(out_ball), .in_gift(out_gift), .in_block(out_block), .in_paddle(out_paddle), .in_back(out_back), .oRGB({oVGA_R, oVGA_G, oVGA_B}));
draw_back d_back(.out(out_back), .vcounter(vcounter), .hcounter(hcounter),
.dead(st_dead), .init(st_init), .win(st_win));
draw_block d_block(.clock(clk_25), .vcounter(vcounter), .hcounter(hcounter), .block(out_bmem),
.sel_row(out_row), .sel_col(out_col), .out(out_block));
draw_ball d_ball(.out(out_ball), .vcounter(vcounter), .hcounter(hcounter), .visible(b_dis),
.xs(b_x), .ys(b_y), .active(b_active), .radius(b_radius));
draw_ball d_shot(.out(out_shot), .vcounter(vcounter), .hcounter(hcounter),
.xs(s_x), .ys(s_y), .active(s_active), .radius(4));
draw_paddle d_paddle(.vcounter(vcounter), .hcounter(hcounter),
.x(p_x), .y(p_y), .radius(p_radius), .out(out_paddle));
draw_gift d_gift(.vcounter(vcounter), .hcounter(hcounter),
.x(g_x), .y(g_y), .kind(g_kind), .active(g_active), .out(out_gift));
VGA_control vga_c(.CLK(clk_25), .reset(reset), .vcounter(vcounter), .hcounter(hcounter),
.visible(visible), .oHS(oHS), .oVS(oVS));
assign reset = btn_N;
assign oLED[1:0] = st_win ? 2'b11 : (st_dead ? 2'b01 : 2'b00);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long unsigned int countDivisors(long long unsigned int n) { long long unsigned int cnt = 0; for (long long unsigned int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) ++cnt; else cnt += 2; } } return cnt; } int Search(string pat, string txt) { int n = txt.size(); int m = pat.size(); for (int i = 0; i <= n - m; i++) { int j; for (j = 0; j < m; j++) { if (txt[i + j] != pat[j]) { break; } } if (j == m) { return i; } } return -1; } int findFirst(const std::vector<long long int> &array, int key, int low, int high) { int ans = -1; while (low <= high) { int mid = low + (high - low) / 2; if (key == array[mid]) { ans = mid; high = mid - 1; } else if (key > array[mid]) low = mid + 1; else high = mid - 1; } return ans; } int findLast(const std::vector<long long int> &array, int key, int low, int high) { int ans = -1; while (low <= high) { int mid = low + (high - low) / 2; if (key == array[mid]) { ans = mid; low = mid + 1; } else if (key > array[mid]) low = mid + 1; else high = mid - 1; } return ans; } int d, x, y; void extendedEuclid(int a, int b) { if (b == 0) { d = 1; x = 1; y = 0; } else { extendedEuclid(b, a % b); int temp = x; x = y; y = temp - (a / b) * y; } } int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; t = 1; for (int tc = 0; tc < t; tc++) { int n; cin >> n; vector<int> arr(n), brr(n, 0), v; for (int i1 = 0; i1 < n; i1++) cin >> arr[i1]; int pos = 0; for (int i = 0; i < n; i++) { int indx = n - arr[i]; brr[indx] = 1; while (brr[pos] == 1 && pos < n) { cout << (n - pos) << ; pos++; } cout << endl; } } return 0; }
|
/* ltcminer_icarus.v copyright kramble 2013
* Based on https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Xilinx_cluster_cgminer
* Hub code for a cluster of miners using async links
* by teknohog
*/
`include "../../source/sha-256-functions.v"
`include "../../source/sha256_transform.v"
`include "../../source/salsa.v"
`include "../../ICARUS-LX150/xilinx_ram.v"
`include "../../ICARUS-LX150/xilinx_pll.v"
`include "../../ICARUS-LX150/uart_receiver.v"
`include "../../ICARUS-LX150/uart_transmitter.v"
`include "../../ICARUS-LX150/serial.v"
`include "../../ICARUS-LX150/serial_hub.v"
`include "../../ICARUS-LX150/hub_core.v"
`include "../../ICARUS-LX150/pwm_fade.v"
module ltcminer_icarus (osc_clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
// NB SPEED_MHZ resolution is 5MHz steps to keep pll divide ratio sensible. Change the divider in xilinx_pll.v if you
// want other steps (1MHz is not sensible as it requires divide 100 which is not in the allowed range 1..32 for DCM_SP)
// TODO dynamic speed adjustment (possibly use top byte of target to set multiplier, this keeps serial interface compatible)
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef SERIAL_CLK
parameter comm_clk_frequency = `SERIAL_CLK;
`else
parameter comm_clk_frequency = 12_500_000; // 100MHz divide 8
`endif
`ifdef BAUD_RATE
parameter BAUD_RATE = `BAUD_RATE;
`else
parameter BAUD_RATE = 115_200;
`endif
// kramble - since using separare clocks for uart and hasher, need clock crossing logic
input osc_clk;
wire hash_clk, uart_clk;
`ifndef SIM
main_pll # (.SPEED_MHZ(SPEED_MHZ)) pll_blk (.CLKIN_IN(osc_clk), .CLKFX_OUT(hash_clk), .CLKDV_OUT(uart_clk));
`else
assign hash_clk = osc_clk;
assign uart_clk = osc_clk;
`endif
// kramble - nonce distribution is crude using top 4 bits of nonce so max LOCAL_MINERS = 8
// teknohog's was more sophisticated, but requires modification of hashcore.v
// Miners on the same FPGA with this hub
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1; // Only ONE core of LX150_FOUR will fit
`endif
// kramble - nonce distribution only works for a single external port
`ifdef EXT_PORTS
parameter EXT_PORTS = `EXT_PORTS;
`else
parameter EXT_PORTS = 1;
`endif
localparam SLAVES = LOCAL_MINERS + EXT_PORTS;
input TMP_SCL, TMP_SDA, TMP_ALERT; // Unused but set to PULLUP so as to avoid turning on the HOT LED
// TODO implement I2C protocol to talk to temperature sensor chip (TMP101?)
// and drive FAN speed control output.
input [3:0]dip;
wire reset, nonce_chip;
assign reset = dip[0]; // Not used
assign nonce_chip = dip[1]; // Distinguishes between the two Icarus FPGA's
// Work distribution is simply copying to all miners, so no logic
// needed there, simply copy the RxD.
input RxD;
output TxD;
// Results from the input buffers (in serial_hub.v) of each slave
wire [SLAVES*32-1:0] slave_nonces;
wire [SLAVES-1:0] new_nonces;
// Using the same transmission code as individual miners from serial.v
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) sertx (.clk(uart_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
hub_core #(.SLAVES(SLAVES)) hc (.uart_clk(uart_clk), .new_nonces(new_nonces), .golden_nonce(golden_nonce), .serial_send(serial_send), .serial_busy(serial_busy), .slave_nonces(slave_nonces));
// Common workdata input for local miners
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
// reg [31:0] targetreg = 32'hffffffff; // TEST - matches ANYTHING
reg [31:0] targetreg = 32'h000007ff; // Start at sane value (overwritten by serial_receive)
wire rx_done; // Signals hashcore to reset the nonce
// NB in my implementation, it loads the nonce from data3 which should be fine as
// this should be zero, but also supports testing using non-zero nonces.
// Synchronise across clock domains from uart_clk to hash_clk
// This probably looks amateurish (mea maxima culpa, novice verilogger at work), but should be OK
reg rx_done_toggle = 1'b0; // uart_clk domain
always @ (posedge uart_clk)
rx_done_toggle <= rx_done_toggle ^ rx_done;
reg rx_done_toggle_d1 = 1'b0; // hash_clk domain
reg rx_done_toggle_d2 = 1'b0;
reg rx_done_toggle_d3 = 1'b0;
wire loadnonce;
assign loadnonce = rx_done_toggle_d3 ^ rx_done_toggle_d2;
always @ (posedge hash_clk)
begin
rx_done_toggle_d1 <= rx_done_toggle;
rx_done_toggle_d2 <= rx_done_toggle_d1;
rx_done_toggle_d3 <= rx_done_toggle_d2;
if (loadnonce)
targetreg <= target;
end
// End of clock domain sync
serial_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) serrx (.clk(uart_clk), .RxD(RxD), .data1(data1),
.data2(data2), .data3(data3), .target(target), .rx_done(rx_done));
// Local miners now directly connected
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out; // Not used
wire [2:0] nonce_core = i;
wire gn_match;
wire salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
// Currently one pbkdfengine per salsaengine - TODO share the pbkdfengine for several salsaengines
pbkdfengine P (.hash_clk(hash_clk), .data1(data1), .data2(data2), .data3(data3), .target(targetreg),
.nonce_msb({nonce_chip, nonce_core}), .nonce_out(nonce_out), .golden_nonce_out(slave_nonces[i*32+31:i*32]),
.golden_nonce_match(gn_match), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine S (.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout), .shift(salsa_shift),
.start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
// Synchronise across clock domains from hash_clk to uart_clk for: assign new_nonces[i] = gn_match;
reg gn_match_toggle = 1'b0; // hash_clk domain
always @ (posedge hash_clk)
gn_match_toggle <= gn_match_toggle ^ gn_match;
reg gn_match_toggle_d1 = 1'b0; // uart_clk domain
reg gn_match_toggle_d2 = 1'b0;
reg gn_match_toggle_d3 = 1'b0;
assign new_nonces[i] = gn_match_toggle_d3 ^ gn_match_toggle_d2;
always @ (posedge uart_clk)
begin
gn_match_toggle_d1 <= gn_match_toggle;
gn_match_toggle_d2 <= gn_match_toggle_d1;
gn_match_toggle_d3 <= gn_match_toggle_d2;
end
// End of clock domain sync
end // for
endgenerate
// External miner ports, results appended to the same
// slave_nonces/new_nonces as local ones
output [EXT_PORTS-1:0] extminer_txd;
input [EXT_PORTS-1:0] extminer_rxd;
assign extminer_txd = {EXT_PORTS{RxD}};
generate
genvar j;
for (j = LOCAL_MINERS; j < SLAVES; j = j + 1)
begin: for_ports
slave_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) slrx (.clk(uart_clk), .RxD(extminer_rxd[j-LOCAL_MINERS]), .nonce(slave_nonces[j*32+31:j*32]), .new_nonce(new_nonces[j]));
end
endgenerate
output [3:0] led;
assign led[1] = ~RxD;
assign led[2] = ~TxD;
assign led[3] = ~ (TMP_SCL | TMP_SDA | TMP_ALERT); // IDLE LED - held low (the TMP pins are PULLUP, this is a fudge to
// avoid warning about unused inputs)
// Light up only from locally found nonces, not ext_port results
pwm_fade pf (.clk(uart_clk), .trigger(|new_nonces[LOCAL_MINERS-1:0]), .drive(led[0]));
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XGMII control/data deinterleave
*/
module xgmii_deinterleave
(
input wire [72:0] input_xgmii_dc,
output wire [63:0] output_xgmii_d,
output wire [7:0] output_xgmii_c
);
assign output_xgmii_d[7:0] = input_xgmii_dc[7:0];
assign output_xgmii_c[0] = input_xgmii_dc[8];
assign output_xgmii_d[15:8] = input_xgmii_dc[16:9];
assign output_xgmii_c[1] = input_xgmii_dc[17];
assign output_xgmii_d[23:16] = input_xgmii_dc[25:18];
assign output_xgmii_c[2] = input_xgmii_dc[26];
assign output_xgmii_d[31:24] = input_xgmii_dc[34:27];
assign output_xgmii_c[3] = input_xgmii_dc[35];
assign output_xgmii_d[39:32] = input_xgmii_dc[43:36];
assign output_xgmii_c[4] = input_xgmii_dc[44];
assign output_xgmii_d[47:40] = input_xgmii_dc[52:45];
assign output_xgmii_c[5] = input_xgmii_dc[53];
assign output_xgmii_d[55:48] = input_xgmii_dc[61:54];
assign output_xgmii_c[6] = input_xgmii_dc[62];
assign output_xgmii_d[63:56] = input_xgmii_dc[70:63];
assign output_xgmii_c[7] = input_xgmii_dc[71];
endmodule
`resetall
|
module ascii (
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
// @todo: shift, alt etc
reg [7:0] r_ascii;
assign ascii = r_ascii;
reg keyup = 0;
always @(posedge scan_ready) begin
if (scan_code == 8'hf0) begin
keyup <= 1;
end else begin
if (keyup) begin
keyup <= 0;
r_ascii <= 8'd0;
end else
case (scan_code)
8'h29: r_ascii <= 8'd32; // [space]
8'h45: r_ascii <= 8'd48; // 0
8'h16: r_ascii <= 8'd49; // 1
8'h1e: r_ascii <= 8'd50; // 2
8'h26: r_ascii <= 8'd51; // 3
8'h25: r_ascii <= 8'd52; // 4
8'h2e: r_ascii <= 8'd53; // 5
8'h36: r_ascii <= 8'd54; // 6
8'h3d: r_ascii <= 8'd55; // 7
8'h3e: r_ascii <= 8'd56; // 8
8'h46: r_ascii <= 8'd57; // 9
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
default: r_ascii <= 8'd0; // nothing
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<int> a(n, 0); for (int i = 0; i < n; i++) cin >> a[i]; vector<int> prev(n, 0); prev[0] = 0; int m = -1; int s = 0; int l = 0; int r = 0; for (int i = 1; i < n - 1; i++) { if (a[i] > a[i + 1] && a[i - 1] < a[i]) { s++; } prev[i] = s; } for (int i = n - 1; i >= k - 1; i--) { if (prev[i - 1] - prev[i - k + 1] >= m) { m = prev[i - 1] - prev[i - k + 1]; l = i - k + 1; } } cout << m + 1 << << l + 1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; bool cmp(pair<ll, ll> a, pair<ll, ll> b) { return a.second > b.second; } bool cmp2(vector<ll> a, vector<ll> b) { return a.size() > b.size(); } int main() { ll n, m; cin >> n >> m; vector<pair<ll, ll>> vp(n); for (ll i = 0; i < n; i++) { ll s, r; cin >> s >> r; s--; vp[i] = make_pair(s, r); } sort(vp.begin(), vp.end(), cmp); vector<vector<ll>> g(m, vector<ll>(1)); ll mxsz = 0; for (ll i = 0; i < n; i++) { g[vp[i].first].push_back(vp[i].second + g[vp[i].first].back()); mxsz = max(mxsz, (ll)g[vp[i].first].size()); } sort(g.begin(), g.end(), cmp2); ll ans = 0; for (ll i = 0; i < mxsz; i++) { ll now = 0; vector<ll> hoge; for (ll j = 0; j < m; j++) { if (i < g[j].size()) { if (g[j][i] > 0) now += g[j][i]; } if (g[j].size() < i) break; } ans = max(ans, now); } cout << max(0LL, ans) << endl; }
|
module state_control
#(
parameter BALL_NUM = 2,
parameter SHOT_NUM = 2
)
(
input clock, reset, start, btn_l, btn_r,
input [3:0] iSW,
input bm_ready,
input [3:0] bm_block,
input [9:0] p_x, p_y,
output reg [5:0] p_radius, b_radius,
output [BALL_NUM*10-1:0] o_bx, o_by,
output reg [BALL_NUM-1:0] b_active,
output reg [SHOT_NUM*2-1:0] o_sx, o_sy,
output [SHOT_NUM-1:0] s_active,
output reg bm_enable,
output [4:0] bm_row, bm_col,
output reg [1:0] bm_func,
output [1:0] bm_stage,
output reg [4:0] p_speed,
output [9:0] g_x, g_y,
output [3:0] g_kind,
output g_active,
output reg b_dis,
output middle,
output reg [5:0] hp,
output dead, init,
output reg win
);
`include "def.v"
localparam ST_INIT = 2'b00;
localparam ST_WAIT = 2'b01;
localparam ST_PLAY = 2'b10;
localparam ST_DEAD = 2'b11;
wire bm_empty;
wire load_stage;
reg b_sw;
wire [5:0] bl_radius;
reg [1:0] state, next_state;
wire [9:0] b_x[BALL_NUM-1:0], b_y[BALL_NUM-1:0];
wire [9:0] bl_x, bl_y;
wire [BALL_NUM-1:0] b_bd_p, b_bd_bl;
wire [1:0] b_bd_di_p[BALL_NUM-1:0], b_bd_di_bl[BALL_NUM-1:0], b_bd_di[BALL_NUM-1:0];
reg [1:0] stage, next_stage;
wire bl_enable, bl_rstc, bl_rstr;
assign bl_x = LEFT + 16 + bm_col*32;
assign bl_y = TOP + 8 + bm_row*16;
assign bm_stage = next_stage;
assign load_stage = (state == ST_INIT || (state == ST_PLAY && bm_empty)) && next_state == ST_WAIT;
assign middle = stage == 2'b11;
wire paddle_size, paddle_speed, give_ball, ball_speed, ball_size, ball_display, get_shot, drop_block;
reg [9:0] g_inx, g_iny;
wire [UBIT-1+8:0] swcnt;
counter #(UBIT+8) cntsw(clock, reset, b_sw, swcnt);
gift_control g_control(clock, reset | (!b_active), |b_bd_bl, g_hit, bl_x, bl_y, g_kind, g_x, g_y, g_active,
paddle_size, paddle_speed, give_ball, ball_speed, ball_size, ball_display, get_shot, drop_block);
bounce_detect g_bounce(g_active, g_x, g_y, 8, p_x, p_y, p_radius, PD_H, g_hit,);
always @(posedge clock)
begin
if (reset) begin
p_radius <= 16;
b_radius <= 8;
p_speed <= 1;
end else begin
if (paddle_size) begin
if (p_radius == 16)
p_radius <= 32;
else if (p_radius == 32)
p_radius <= 8;
else
p_radius <= 16;
end
if (paddle_speed) begin
if (p_speed == 1)
p_speed <= 3;
else if (p_speed == 3)
p_speed <= 5;
else
p_speed <= 1;
end
if (ball_size) begin
if (b_radius == 8)
b_radius <= 16;
else
b_radius <= 8;
end
end
end
assign init = state == ST_INIT;
assign dead = (state == ST_DEAD) && ~win;
always @(posedge clock)
begin
if (reset)
b_dis <= 1'b1;
else if (b_sw)
if (swcnt == 0) b_dis <= ~b_dis;
else
b_dis <= 1'b1;
end
always @(posedge clock)
begin
if (reset)
b_sw <= 1'b0;
else if (ball_display)
b_sw <= ~b_sw;
end
always @(posedge clock)
begin
if (reset)
hp <= 6'b111111;
else if (state == ST_PLAY && !b_active)
hp <= hp >> 1;
end
always @(posedge clock)
begin
if (reset)
win <= 1'b0;
else if (stage == 2'b11 && bm_empty)
win <= 1'b1;
end
assign floor = iSW[1];
wire [BALL_NUM-1:0] b_dead;
always @(posedge clock)
begin : b_block
integer i;
if (reset)
b_active <= 0;
else if (next_state == ST_WAIT)
b_active[0] <= 1'b1;
for (i=0; i<BALL_NUM; i=i+1) begin
if (b_dead[i] || b_bd_bl[i] && bm_block == 3'b001) b_active[i] <= 1'b0;
if (give_ball) b_active[i] <= 1'b1;
end
end
always @(*)
begin
bm_enable = 1'b0;
bm_func = 2'bxx;
if ((state == ST_INIT && start ) || (state == ST_PLAY && bm_empty && next_state == ST_WAIT)) begin
bm_enable = 1'b1;
bm_func = F_LOAD;
end else if (state == ST_PLAY && b_bd_bl && bm_block != 3'b111 && bm_block != 3'b001) begin
bm_enable = 1'b1;
bm_func = F_CLEAR;
end else if (drop_block) begin
bm_enable = 1'b1;
bm_func = 2'b11;
end else if (btn_l) begin
bm_enable = 1'b1;
bm_func = 2'b10;
end else if (btn_r) begin
bm_enable = 1'b1;
bm_func = 2'b11;
end
end
wire [3:0] b_sx[BALL_NUM-1:0], b_sy[BALL_NUM-1:0];
generate
genvar i;
for (i=0; i<BALL_NUM; i=i+1) begin : b_genblock
ball_control ball(clock, reset, next_state == ST_WAIT || ~b_active[i], b_active[i], floor, b_radius, p_x, p_y-PD_H-b_radius, b_sx[i], b_sy[i], i,b_bd_p[i], b_bd_bl[i], b_bd_di[i], b_x[i], b_y[i], b_dead[i]);
bounce_detect p_bounce(1'b1, b_x[i], b_y[i], b_radius, p_x, p_y, p_radius, PD_H, b_bd_p[i], b_bd_di_p[i]);
bounce_detect bl_bounce(bm_block != 0 && bm_ready && b_active[i], b_x[i], b_y[i], b_radius, bl_x, bl_y, bl_radius, 8, b_bd_bl[i], b_bd_di_bl[i]);
ball_speed b_speed(clock, b_x[i], b_y[i], p_x, p_radius, b_bd_p[i], b_sx[i], b_sy[i]);
assign o_bx[i*10+9:i*10] = b_x[i];
assign o_by[i*10+9:i*10] = b_y[i];
assign b_bd_di[i] = b_bd_bl[i] ? b_bd_di_bl[i] : b_bd_di_p[i];
end
endgenerate
always @(posedge clock)
begin
if (reset)
state <= ST_INIT;
else
state <= next_state;
end
always @(*)
begin
case (state)
ST_INIT: begin
if (start && bm_ready)
next_state = ST_WAIT;
else
next_state = ST_INIT;
end
ST_WAIT: begin
if (start && bm_ready)
next_state = ST_PLAY;
else
next_state = ST_WAIT;
end
ST_PLAY: begin
if (!(b_active || hp) || (stage == 2'b11 && bm_empty))
next_state = ST_DEAD;
else if (!b_active)
next_state = ST_WAIT;
else if (bm_empty)
next_state = ST_WAIT;
else
next_state = ST_PLAY;
end
ST_DEAD: next_state = ST_DEAD;
default:
next_state = 2'bxx;
endcase
end
always @(posedge clock)
begin
if (reset)
stage <= 2'b00;
else if (load_stage)
stage <= next_stage;
end
always @(*)
begin
if (iSW[1:0] == 2'b11)
next_stage = iSW[3:2];
else if (state == ST_INIT)
next_stage = 2'b00;
else
next_stage = (stage + 1)%4;
end
// block counter
assign bl_enable = bm_col >= 4'd9;
assign bl_rstc = reset || bl_enable;
assign bl_rstr = reset || (bm_row >= 5'd29 && bl_enable);
counter #(5) cntblc(clock, bl_rstc, 1'b1, bm_col);
counter #(5) cntblr(clock, bl_rstr, bl_enable, bm_row);
reg scan_empty;
always @(posedge clock)
begin
if (reset || ~bm_ready || bm_enable || (bm_block && bm_block != 3'b111 && bm_block != 3'b001))
scan_empty <= 1'b0;
else if (bm_row == 0 && bm_col == 0)
scan_empty <= 1'b1;
end
assign bm_empty = (reset || ~bm_ready || bm_block) ? 1'b0 : bm_row == 5'd29 && bm_col && scan_empty;
assign bl_radius = bm_block[2] ? 16 : 8;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/13/08 - CR 458290 -- Added else condition to handle x case.
// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM.
// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR.
// 11/03/10 - CR 576577 -- changed default value of IOSTANDARD from LVDS_25 to DEFAULT.
// 09/30/11 - CR 626400 -- Added PATHPULSE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT (O, OB, I, IB);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O, OB;
input I, IB;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
buf B0 (O, o_out);
not B1 (OB, o_out);
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_odd_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ODD_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_odd_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_odd_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_odd_parity_psl_logic.v"
`else
`endmodule // ovl_odd_parity
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; string s, p, r; s = 1 ; cin >> p; s = s + p; for (long long int i = 2; i < n - 1; i++) { if (n % i == 0) { p = s.substr(1, i); s = s.substr(i + 1, n); reverse(p.begin(), p.end()); s = 1 + p + s; } } s = s.substr(1, n); reverse(s.begin(), s.end()); cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 77, Mod = 1e9 + 7; int n, d1[N], d2[N], P1, P2, Mx, deg[N], p1[N], p2[N]; long long A; vector<pair<int, pair<int, int> > > R; vector<int> a[N]; void dfs(int v, int prev, bool t) { for (int u : a[v]) { if (u == prev) { continue; } if (t) { d1[u] = d1[v] + 1; p1[u] = v; } else { d2[u] = d2[v] + 1; p2[u] = v; } dfs(u, v, t); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int v, u; scanf( %d %d , &v, &u); deg[v]++; deg[u]++; a[v].push_back(u); a[u].push_back(v); } dfs(1, 1, 1); for (int i = 1; i <= n; i++) { if (d1[i] > Mx) { Mx = d1[i]; P1 = i; } } d1[P1] = 0; dfs(P1, P1, 1); Mx = 0; for (int i = 1; i <= n; i++) { if (d1[i] > Mx) { Mx = d1[i]; P2 = i; } } dfs(P2, P2, 0); vector<int> Leaves; for (int i = 1; i <= n; i++) { if (i == P1 || i == P2 || deg[i] > 1) continue; Leaves.push_back(i); } while (Leaves.size()) { int v = Leaves.back(); Leaves.pop_back(); if (d1[v] >= d2[v]) { A += d1[v]; R.push_back(make_pair(v, make_pair(P1, v))); } else { A += d2[v]; R.push_back(make_pair(v, make_pair(P2, v))); } deg[v]--; for (int u : a[v]) { deg[u]--; if (deg[u] == 1) Leaves.push_back(u); } } while (p2[P1]) { R.push_back(make_pair(P1, make_pair(P2, P1))); A += d2[P1]; P1 = p2[P1]; } printf( %I64d n , A); for (auto x : R) printf( %d %d %d n , x.first, x.second.first, x.second.second); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
|
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