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#include <bits/stdc++.h> int main() { int n; std::scanf( %d , &n); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { std::printf( %d , j * n + (j % 2 == 0 ? i : n - i - 1) + 1); } std::printf( n ); } return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Test.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Test (
address,
clock,
q);
input [0:0] address;
input clock;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "test.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=test",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 1,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "test"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=test"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int kMod = 1e9 + 7; const int kNmax = 2e5 + 10; int n, v[kNmax], sub[kNmax], up[kNmax][2], down[kNmax][2], res, res_even; vector<int> g[kNmax]; void dfs(int node, int father = 0) { sub[node] = 1; down[node][0] = 1; int ways = (1LL * n * n) % kMod; for (int vec : g[node]) { if (vec == father) continue; dfs(vec, node); ways = (ways - 1LL * sub[vec] * sub[vec]) % kMod; if (ways < 0) ways += kMod; sub[node] += sub[vec]; down[node][0] += down[vec][1]; down[node][1] += down[vec][0]; } ways = (ways - 1LL * (n - sub[node]) * (n - sub[node])) % kMod; if (ways < 0) ways += kMod; res = (res + 1LL * ways * v[node]) % kMod; if (res < 0) res += kMod; } void dfs_bad(int node, int father = 0) { int s0 = 0, s1 = 0; int ways = (1LL * down[node][1] * (n - sub[node])) % kMod; ways = (ways + 1LL * up[node][1] * sub[node]) % kMod; for (int vec : g[node]) { if (vec == father) continue; ways = (ways + 1LL * down[vec][0] * (sub[node] - sub[vec])) % kMod; s0 += down[vec][0]; s1 += down[vec][1]; } res_even = (res_even + 1LL * ways * v[node]) % kMod; if (res_even < 0) res_even += kMod; for (int vec : g[node]) { if (vec == father) continue; up[vec][0] = up[node][1] + s0 - down[vec][0]; up[vec][1] = n - sub[vec] - up[vec][0]; dfs_bad(vec, node); } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1, a, b; i < n; i++) { cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } dfs(1); up[1][0] = 1; dfs_bad(1); res = (res - 2LL * res_even) % kMod; if (res < 0) res += kMod; cout << res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A2BB2OI_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2005, maxm = 200005; vector<int> g[maxn]; int tmp, vis[maxn], dis[maxn], mp[maxn][maxn]; int n, m, ans, cnt, tot, res, ecnt, info[maxn], nx[maxm], v[maxm]; int id, en, dfn[maxn], low[maxn], ori[maxn], sta[maxn], outd[maxn]; void add(int u1, int v1) { nx[++ecnt] = info[u1]; info[u1] = ecnt; v[ecnt] = v1; } void targin(int x, int fa) { dfn[x] = low[x] = ++id; sta[++en] = x; for (int i = info[x]; i; i = nx[i]) { if (v[i] == fa) continue; if (!dfn[v[i]]) targin(v[i], x), low[x] = min(low[x], low[v[i]]); else low[x] = min(low[x], dfn[v[i]]); } if (low[x] == dfn[x]) { int v; cnt++; do v = sta[en--], ori[v] = cnt; while (v != x); } } void dfs(int x, int fa) { vis[x] = 1; dis[x] = dis[fa] + 1; if (dis[tmp] < dis[x]) tmp = x; for (int i = 0, lim = g[x].size(); i < lim; i++) if (g[x][i] != fa) dfs(g[x][i], x); } int main() { scanf( %d%d , &n, &m); for (int i = 1, u1, v1; i <= m; i++) scanf( %d%d , &u1, &v1), add(u1, v1), add(v1, u1); for (int i = 1; i <= n; i++) if (!dfn[i]) targin(i, 0); if (cnt == 1) { printf( %d n , n - 1); return 0; } for (int x = 1; x <= n; x++) for (int i = info[x]; i; i = nx[i]) if (!mp[ori[x]][ori[v[i]]] && ori[x] != ori[v[i]]) { mp[ori[x]][ori[v[i]]] = 1; g[ori[x]].push_back(ori[v[i]]); outd[ori[x]]++; } for (int i = 1; i <= cnt; i++) if (outd[i] == 1) res++; for (int i = 1, p1, p2; i <= cnt; i++) if (!vis[i]) { tot++; tmp = 0; dfs(i, 0); p1 = tmp; tmp = 0; dfs(p1, 0); p2 = tmp; if (dis[p2] < 2) res++; else res += dis[p2] - 2; } printf( %d n , n - res + tot - 1); } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000000 + 7; const int N = 100000 + 50; vector<int> a; int val[N]; int p[N]; int rp[N]; int avl[N]; pair<int, int> dp[N]; int curn; pair<int, int> bit[N]; vector<vector<int> > fa; void clear_bit(int n) { for (int i = 0; i < n + 2; i++) { bit[i] = {0, -1}; } } void upd(int i, int x, int y) { while (i < curn) { if (x > bit[i].first) { bit[i] = {x, y}; } i += i & (-i); } } pair<int, int> get(int i) { pair<int, int> ans = {0, 0}; while (i > 0) { if (bit[i].first > ans.first) { ans = bit[i]; } i -= i & (-i); } return ans; } void build() { int n = a.size(); if (n == 0) return; clear_bit(n + 3); curn = n + 2; pair<int, int> vl = {0, 0}; for (int i = 1; i <= n; i++) { avl[i] = 1; auto an = get(a[i - 1]); dp[i] = {an.first + 1, an.second}; if (dp[i].first > vl.first) { vl = {dp[i].first, i}; } upd(a[i - 1], dp[i].first, i); } if (val[n - vl.first] < val[n]) { vector<int> ans; int cur = vl.second; while (cur > 0) { avl[a[cur - 1]] = 0; ans.push_back(p[a[cur - 1]]); cur = dp[cur].second; } reverse(ans.begin(), ans.end()); fa.push_back(ans); int c = 0; for (int i = 1; i <= n; i++) { c += avl[i]; if (avl[i] == 1) { p[c] = p[i]; rp[i] = c; } } vector<int> temp; for (int i = 1; i <= n; i++) { if (avl[a[i - 1]]) { temp.push_back(rp[a[i - 1]]); } } a = temp; build(); return; } else { vector<int> v[n + 5]; for (int i = 1; i <= n; i++) { v[dp[i].first].push_back(p[a[i - 1]]); } for (int i = 0; i <= n; i++) { if (v[i].size()) fa.push_back(v[i]); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int cur = 2; for (int i = 1; i < N; i++) { for (int j = 0; j < cur && i + j < N; j++) { val[i + j] = cur - 1; } i += cur - 1; cur++; } int t; cin >> t; while (t--) { int n; cin >> n; a.clear(); for (int i = 1; i <= n; i++) { p[i] = i; int x; cin >> x; a.push_back(x); } fa.clear(); build(); cout << fa.size() << endl; for (auto& it : fa) { cout << it.size() << ; for (auto it1 : it) cout << it1 << ; cout << endl; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, f[6]; cin >> a >> b >> c; f[0] = a + b + c; f[1] = a + b * c; f[2] = a * b + c; f[3] = a * b * c; f[4] = (a + b) * c; f[5] = a * (b + c); sort(f, f + 6); cout << f[5]; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; long long x, k; long long qow(long long a, long long b) { long long ans = 1; a = a % mod; while (b) { if (b % 2 == 1) { ans = (ans * a) % mod; } a = (a * a) % mod; b /= 2; } return ans; } int main() { while (~scanf( %lld %lld , &x, &k)) { if (x == 0) { printf( 0 n ); continue; } x = x % mod; cout << (((2 * x - 1) * qow(2, k) + mod) % mod + 1 + mod) % mod << endl; } return 0; } |
#include <bits/stdc++.h> bool fine(int v) { int z = 0, s = 0; while ((v & 1) == 0) { z++; v >>= 1; } while ((v & 1) == 1) { s++; v >>= 1; } return v == 0 && z == s - 1; } int main() { int n; scanf( %d , &n); for (int i = n; i >= 1; i--) { if (n % i == 0 && fine(i)) { printf( %d , i); return 0; } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_2_V
`define SKY130_FD_SC_HDLL__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_1_V
`define SKY130_FD_SC_HD__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_1_V
|
#include <bits/stdc++.h> using namespace std; int anc[200007]; int sz[200007]; int x[200005], y[200005]; vector<int> g[200005]; int get_set(int v) { if (v == anc[v]) { return v; } return anc[v] = get_set(anc[v]); } void unite_sets(int u, int v) { u = get_set(u); v = get_set(v); if (u == v) { return; } if (sz[u] < sz[v]) { swap(u, v); } sz[u] = sz[u] + sz[v]; anc[v] = u; } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> x[i] >> y[i]; g[x[i]].push_back(y[i]); g[y[i]].push_back(x[i]); } for (int i = 0; i <= n; i++) { sz[i] = 1; anc[i] = i; } int mx = 0; int z = 1; for (int i = 1; i <= n; i++) { if (g[i].size() > mx) { mx = g[i].size(); z = i; } } for (int i = 0; i < g[z].size(); i++) { if (get_set(z) != get_set(g[z][i])) { unite_sets(z, g[z][i]); cout << z << << g[z][i] << endl; } } for (int i = 0; i < m; i++) { if (get_set(x[i]) != get_set(y[i])) { unite_sets(x[i], y[i]); cout << x[i] << << y[i] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 3) + (x << 1) + (c ^ 48); c = getchar(); } return f == -1 ? ~x + 1 : x; } long long n; vector<long long> ve[11]; long long sum[11]; const long long N = 1e6, mod1 = 998244353, mod2 = 1e9 + 7; long long cnt, tmp, ans; long long m1(long long x) { return (x % mod1 + mod1) % mod1; } void dfs1(long long x, long long v) { if (v > n) return; if (x > 6) return; ++cnt; ve[x].push_back(m1(cnt - v)); sum[x] += m1(cnt - v); for (long long i = 0; i < 10; ++i) dfs1(x + 1, v * 10 + i); } void dfs2(long long x, long long v) { if (v > n) return; if (x >= 1) { if (v * N * 10 > n && v * N + N - 1 <= n) { for (long long i = 0, t = 1; i <= 6; ++i, t *= 10) { long long val = m1(cnt - v * t); long long pos = lower_bound(ve[i].begin(), ve[i].end(), mod1 - val) - ve[i].begin(); (ans += val * ve[i].size() + sum[i] - mod1 * (ve[i].size() - pos)) %= mod2; } cnt += tmp; return; } ++cnt; (ans += m1(cnt - v)) %= mod2; } for (long long i = (x == 0 ? 1 : 0); i <= 9; ++i) dfs2(x + 1, v * 10 + i); } signed main() { n = read(); dfs1(0, 0); tmp = cnt; cnt = 0; for (long long i = 0; i <= 6; ++i) sort(ve[i].begin(), ve[i].end()); dfs2(0, 0); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; struct Node { int l, r; Node(int l, int r) : l(l), r(r) {} bool operator<(const Node &o) const { return r - l == o.r - o.l ? r > o.r : r - l > o.r - o.l; } }; vector<int> event; int arr[200000]; map<int, int> matching; map<int, int> cloak_pos; set<Node> heap; int query[100000 + 10][3]; int query_pos[100000 + 10]; void modify(int pos, int delta) { while (pos < event.size()) { arr[pos] += delta; pos += pos & -pos; } } int sum(int pos) { int ret = 0; while (pos > 0) { ret += arr[pos]; pos -= pos & -pos; } return ret; } int main() { int n, q; scanf( %d%d , &n, &q); for (int i = 0; i < q; ++i) { scanf( %d , &query[i][0]); if (query[i][0] == 0) { scanf( %d%d , &query[i][1], &query[i][2]); } } matching[1] = n; matching[n] = 1; heap.insert(Node(1, n)); event.push_back(0); for (int i = 0; i < q; ++i) { if (query[i][0] > 0) { int x = query[i][0]; if (cloak_pos.count(x)) { int y = cloak_pos[x]; int l1, r1, l2, r2; if (matching.count(y - 1)) { l1 = matching[y - 1]; r1 = y - 1; matching.erase(y - 1); heap.erase(Node(l1, r1)); } else { l1 = r1 = y; } if (matching.count(y + 1)) { l2 = y + 1; r2 = matching[y + 1]; matching.erase(y + 1); heap.erase(Node(l2, r2)); } else { l2 = r2 = y; } matching[l1] = r2; matching[r2] = l1; heap.insert(Node(l1, r2)); query_pos[i] = -y; cloak_pos.erase(x); } else { Node cur = *heap.begin(); heap.erase(heap.begin()); int y = (cur.l + cur.r) / 2; if ((cur.r - cur.l + 1) % 2 == 0) { ++y; } matching.erase(cur.r); if (cur.r != cur.l) { matching.erase(cur.l); } event.push_back(y); query_pos[i] = y; if (y + 1 <= cur.r) { matching[y + 1] = cur.r; matching[cur.r] = y + 1; heap.insert(Node(y + 1, cur.r)); } if (cur.l <= y - 1) { matching[y - 1] = cur.l; matching[cur.l] = y - 1; heap.insert(Node(cur.l, y - 1)); } cloak_pos[x] = y; } } } sort(event.begin(), event.end()); event.erase(unique(event.begin(), event.end()), event.end()); for (int i = 0; i < q; ++i) { if (query[i][0] > 0) { if (query_pos[i] < 0) { int y = -query_pos[i]; int t = lower_bound(event.begin(), event.end(), y) - event.begin(); modify(t, -1); } else { int y = query_pos[i]; int t = lower_bound(event.begin(), event.end(), y) - event.begin(); modify(t, +1); } } else { int x = lower_bound(event.begin(), event.end(), query[i][1]) - event.begin(); int y = upper_bound(event.begin(), event.end(), query[i][2]) - event.begin() - 1; int ans = 0; if (x <= y) { ans = sum(y) - sum(x - 1); } printf( %d n , ans); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long Mo = 1e9 + 7; int cnt[1 << 6], sz; void add(long long &x, long long y) { x += y; x %= Mo; } void gao(int n, int C, int R, vector<vector<long long>> &Ma) { int loop = 1 << R; for (int i = 0; i < sz; i++) { int c = i / loop, r = i % loop; int a1 = r >> 1, a2 = r >> 1 | (1 << (R - 1)); if ((r & 1) && c != 0) { Ma[c * loop + a1 - loop][i] += cnt[a1] + 1; Ma[c * loop + a2 - loop][i] += cnt[a2] + 1; } else if (!(r & 1)) { Ma[c * loop + a1][i] += 1; Ma[c * loop + a2][i] += 1; } } } void mul(vector<vector<long long>> &a, vector<vector<long long>> b) { vector<vector<long long>> ret(sz, vector<long long>(sz)); for (int i = 0; i < sz; i++) { for (int j = 0; j < sz; j++) { for (int k = 0; k < sz; k++) { add(ret[i][j], a[i][k] * b[k][j]); } } } a = ret; } void matpw(vector<vector<long long>> &a, long long b) { vector<vector<long long>> ret(sz, vector<long long>(sz)); for (int i = 0; i < sz; i++) ret[i][i] = 1; while (b) { if (b & 1) mul(ret, a); mul(a, a); b >>= 1; } a = ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); for (int i = 0; i < (1 << 6); i++) { for (int j = 0; j < 6; j++) { if (i & (1 << j)) cnt[i]++; } } int n, K, m; cin >> n >> K >> m; sz = (K + 1) * (1 << m); vector<vector<long long>> Ma(sz, vector<long long>(sz)); gao(sz, K + 1, m, Ma); matpw(Ma, n); vector<vector<long long>> base(sz, vector<long long>(sz)); for (int i = 0; i < sz; ++i) base[i][0] = 1; mul(base, Ma); long long ans = 0; for (int i = 0; i < (1 << m); ++i) add(ans, base[0][sz - i - 1]); cout << ans << endl; return 0; } |
#define _CRT_SECURE_NO_WARNINGS #include <vector> #include <string> #include <map> #include <queue> #include <unordered_map> #include <unordered_set> #include <cassert> #include <complex> #include <cstdio> #include <iostream> #include <iomanip> #include <cmath> #include <functional> #include <algorithm> #include <stack> #include <numeric> #include <set> #include <chrono> #include <random> #define all(X) (X).begin(), (X).end() #define int long long #define m_p make_pair #define endl n using namespace std; mt19937_64 rnd(std::chrono::system_clock::now().time_since_epoch().count()); const int MAXN = 1e6 + 100, mod = 1e9 + 7; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } void extgcd(int a, int b, int &x, int &y) { if (b == 0) { x = 1; y = 0; return; } else { extgcd(b, a % b, x, y); int temp = y; y = x - (a / b) * y; x = temp; } } int inv(int a, int mod) { int x, y; extgcd(a, mod, x, y); x = (x % mod + mod) % mod; return x; } int f[MAXN]; int c(int n, int k) { if (n < 0 || n < 0 || n - k < 0) return 0; return (f[n] * inv(f[n - k] * f[k], mod)) % mod; } signed main() { ios::sync_with_stdio(0); cin.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); #endif int n; cin >> n; f[0] = 1; for (int i = 1; i <= n; i++) f[i] = (f[i - 1] * i) % mod; int ans = 0; for (int k = 0; k <= n; k++) { if ((n - k) % 2) continue; ans += (f[n - k] * ((2 * c(n - k - 1, k) + 4 * c(n - k - 1, k - 1)) % mod)) % mod; ans %= mod; } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire D nor0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_V |
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
wasca_nios2_gen2_0_cpu_debug_slave_tck the_wasca_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
wasca_nios2_gen2_0_cpu_debug_slave_sysclk the_wasca_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic wasca_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_tb();
cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );
reg reset;
reg clk;
reg enable;
reg [15:0] xi, yi, zi;
initial reset = 1'b1;
initial #1000 reset = 1'b0;
initial clk = 1'b0;
always #50 clk <= ~clk;
initial enable = 1'b1;
initial zi = 16'b0;
always @(posedge clk)
zi <= #1 zi + 16'd0;
wire [15:0] xo,yo,zo;
initial $dumpfile("cordic.vcd");
initial $dumpvars(0,cordic_tb);
initial
begin
`include "sine.txt"
end
wire [15:0] xiu = {~xi[15],xi[14:0]};
wire [15:0] yiu = {~yi[15],yi[14:0]};
wire [15:0] xou = {~xo[15],xo[14:0]};
wire [15:0] you = {~yo[15],yo[14:0]};
initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);
endmodule // cordic_tb
|
`timescale 1ns / 1ns
`define MOD_OSRAM
module tb_fmrv32im_artya7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_artya7.RST_N = 1'b0;
/*
`ifdef MOD_OSRAM
force u_fmrv32im_artya7.u_fmrv32im_core.u_fmrv32im_cache.i_base = 32'h2000_0000;
force u_fmrv32im_artya7.u_fmrv32im_core.u_fmrv32im_cache.d_base = 32'h2000_0000;
`endif
*/
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_artya7.RST_N = 1'b1;
/*
`ifdef MOD_OSRAM
release u_fmrv32im_artya7.u_fmrv32im_core.u_fmrv32im_cache.i_base;
release u_fmrv32im_artya7.u_fmrv32im_core.u_fmrv32im_cache.d_base;
`endif
*/
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_artya7.u_fmrv32im_core.dbus_wdata;
end
end
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
fmrv32im_artya7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_artya7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_fmrv32im_artya7.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule // tb_fmrv32im_core
`timescale 1ns / 1ps
module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(/115200/2) clk <= ~clk;
end
always begin
#(/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
// Receive
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
// $display("%s", rdata[7:0]);
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); int dx[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dy[] = {0, 0, 1, -1, -1, -1, 1, 1}; void file() {} int main() { cout << setprecision(20) << fixed; ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int k; cin >> k; int x = 0; for (int i = 2; i <= 2000; i++) { long long s = k + i; if (ceil(s / (double(i - 1))) <= 1e6) { x = i; break; } } if (!x) return cout << -1 << n , 0; cout << x << n ; cout << -1 ; long long s = k + x; long long rem = s % (x - 1); long long num = s / (x - 1); for (int i = 0; i < x - 1; i++) if (rem) cout << num + 1 << , rem--; else cout << num << ; cout << n ; } |
`define WIDTH_P 3
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
The number of possible inputs for each WIDTH_P is very large and moreover,
the implementation of the DUT itself is independent of the value of input.
So thermometer codes are used as test inputs, thus limiting the
number of test inputs to WIDTH_P+1. This module also tests enable and reset
after completing tests with thermometer codes.
2. PARAMETERIZATION
DUT synthesizes a similar logic irrespective of the width. Hence an arbitrary
set of tests including edge might be sufficient. So a minimum set of tests
might be WIDTH_P = 1,2,3,4.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_lo_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("==============================================================\n");
$display( "testing with ...\n"
, "WIDTH_P: %d\n", width_p
);
end
logic [width_p-1:0] test_input_data, test_input_data_r, test_output;
logic [width_p+1:0] count; // counter of width_p+2 -- to prevent overflow
logic test_input_en, test_input_reset, finish_r;
bsg_cycle_counter #( .width_p(width_p+2)
) bcc
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
always_ff @(posedge clk)
begin
if(reset)
begin
test_input_data <= width_p'(1'b0);
test_input_reset <= 1'b1;
test_input_en <= 1'b1;
end
else
begin
test_input_data <= (test_input_data << 1) + 1;
if(test_input_reset == 1'b1)
test_input_reset <= 1'b0;
if(test_input_en == 1'b0)
test_input_en <= 1'b1;
assert(test_input_data_r == test_output)
else $error("mismatch on input %x; expected output: %x; output: %x"
, test_input_data, test_input_data_r, test_output);
end
/*$display("test_input_data_r: %b, test_output: %b\n"
, test_input_data_r, test_output);*///
if(test_input_reset)
test_input_data_r <= width_p'(0);
else if(test_input_en)
test_input_data_r <= test_input_data;
case(count)
width_p : test_input_reset <= 1'b1;
width_p+1: test_input_en <= 1'b0;
width_p+4:
begin
$display("===========================================================\n");
$finish;
end
endcase
end
bsg_dff_reset_en #( .width_p(width_p)
) DUT
( .clk_i(clk)
, .data_i (test_input_data)
, .en_i (test_input_en)
, .reset_i(test_input_reset)
, .data_o (test_output)
);
endmodule |
/* indicators.v */
module indicators (
// system
input wire clk, // clock
input wire rst, // reset
// inputs
input wire [ 8-1:0] track, // floppy track number
input wire f_wr, // floppy fifo write
input wire f_rd, // floppy fifo read
input wire h_wr, // harddisk fifo write
input wire h_rd, // harddisk fifo read
input wire [ 4-1:0] status, // control block slave status
input wire [ 4-1:0] ctrl_status, // control block reg-driven status
input wire [ 4-1:0] sys_status, // status from system
input wire fifo_full,
// outputs
output wire [ 7-1:0] hex_0, // seven segment display 0
output wire [ 7-1:0] hex_1, // seven segment display 1
output wire [ 7-1:0] hex_2, // seven segment display 2
output wire [ 7-1:0] hex_3, // seven segment display 3
output wire [ 8-1:0] led_g, // green leds
output wire [ 10-1:0] led_r // red leds
);
// 7-segment display
sseg_decode #(
.REG (1),
.INV (1)
) sseg_HEX0 (
.clk (clk),
.rst (rst),
.num (track[3:0]),
.sseg (hex_0)
);
sseg_decode #(
.REG (1),
.INV (1)
) sseg_HEX1 (
.clk (clk),
.rst (rst),
.num (track[7:4]),
.sseg (hex_1)
);
assign hex_2 = 7'h7f; // off
assign hex_3 = ~7'h71; // f
// LEDs
reg [1:0] r0, r1, g0, g1;
always @ (posedge clk or posedge rst) begin
if (rst) begin
r0 <= #1 2'b00;
r1 <= #1 2'b00;
g0 <= #1 2'b00;
g1 <= #1 2'b00;
end else begin
r0 <= #1 {r0[0], f_wr};
r1 <= #1 {r1[0], h_wr};
g0 <= #1 {g0[0], f_rd};
g1 <= #1 {g1[0], h_rd};
end
end
wire r0_out, g0_out, r1_out, g1_out;
assign r0_out = |r0;
assign r1_out = |r1;
assign g0_out = |g0;
assign g1_out = |g1;
reg [ 4-1:0] ctrl_leds;
always @ (posedge clk, posedge rst) begin
if (rst)
ctrl_leds <= #1 4'b0;
else
ctrl_leds <= #1 ctrl_status;
end
assign led_g = {ctrl_leds, 1'b0,fifo_full, g1_out, g0_out};
assign led_r = {status, sys_status, r1_out, r0_out};
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m; vector<pair<int, int> > e[N]; vector<int> ans[2]; bool fla[2], flag; int E[N], d[N]; vector<int> cnt[2]; void DFS(int first, int o, int res) { if (flag) return; d[first] = o; cnt[o].push_back(first); for (auto& i : e[first]) { if (flag) return; int second = (i.second + o) % 2; if (d[i.first] == -1) DFS(i.first, second != res, res); else if (d[i.first] != (second != res)) flag = true; } } void SOLVE(int res) { memset(d, -1, sizeof(d)); flag = false; for (int i(1); i <= n; i++) if (d[i] == -1) { cnt[0].clear(); cnt[1].clear(); DFS(i, 0, res); if (flag) { fla[res] = true; return; } for (bool ___ = 1; ___; ___ = 0) { int mx = (cnt[1].size() < cnt[0].size()); for (auto& i : cnt[mx]) ans[res].push_back(i); } } } int main() { n = ({ long long first = 0; int n = 0, c = getchar(); for (; !isdigit(c); c = getchar()) n = c == - ; for (; isdigit(c); c = getchar()) first = first * 10 + c - 0 ; n ? -first : first; }), m = ({ long long first = 0; int n = 0, c = getchar(); for (; !isdigit(c); c = getchar()) n = c == - ; for (; isdigit(c); c = getchar()) first = first * 10 + c - 0 ; n ? -first : first; }); for (int i(1); i <= m; i++) { int first = ({ long long first = 0; int n = 0, c = getchar(); for (; !isdigit(c); c = getchar()) n = c == - ; for (; isdigit(c); c = getchar()) first = first * 10 + c - 0 ; n ? -first : first; }), second = ({ long long first = 0; int n = 0, c = getchar(); for (; !isdigit(c); c = getchar()) n = c == - ; for (; isdigit(c); c = getchar()) first = first * 10 + c - 0 ; n ? -first : first; }); int c = ({ char c = getchar(); while (c == || c == n ) c = getchar(); c; }) == R ; e[first].push_back({second, c}); e[second].push_back({first, c}); } SOLVE(0); SOLVE(1); for (bool ___ = 1; ___; ___ = 0) { int res; if (fla[0] && fla[1]) return cout << -1 << n , 0; else if (fla[0]) res = 1; else if (fla[1]) res = 0; else if (ans[0].size() < ans[1].size()) res = 0; else res = 1; cout << ans[res].size() << n ; for (auto& i : ans[res]) cout << i << ; } } |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="adders,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a75tlftg256-2l,HLS_INPUT_CLOCK=3.250000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.365667,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=236,HLS_SYN_LUT=87}" *)
module adders (
ap_clk,
ap_rst,
in1,
in2,
in3,
ap_return
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input [31:0] in1;
input [31:0] in2;
input [31:0] in3;
output [31:0] ap_return;
wire [31:0] tmp1_fu_42_p2;
reg [31:0] tmp1_reg_53;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire ap_CS_fsm_state2;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
tmp1_reg_53 <= tmp1_fu_42_p2;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_return = (tmp1_reg_53 + in2);
assign tmp1_fu_42_p2 = (in1 + in3);
endmodule //adders
|
// #include<bits/stdc++.h> #include<iostream> #include<algorithm> #include<cmath> /* #include<vector> #include<set> #include<map> #include<unordered_map> #define umap unordered_map #include<unordered_set> #define uset unordered_set */ #define pii pair<int,int> #define F first #define S second #define fr(i,n) for(int i=0;i<n;++i) #define pr cout<< #define en << n #define sp << using namespace std; typedef long long ll; int ar[200001]; int main() { // ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t=1,n,a ; cin>>t; while(t--) { cin>>n; int no=0, cnt=0,ans=0; fr(i,n){ cin>>a; if(a==no) cnt++; else{ ans=max(ans,cnt); cnt=1; no =a; } } ans=max(ans,cnt); pr ans en; } } |
#include <bits/stdc++.h> using namespace std; char s[105]; int main() { int n; cin >> n; cin >> s; int flag = 0; for (int i = 1; i < n; i++) { if (s[i] != ? && s[i] == s[i - 1]) { flag = 1; break; } } if (flag) cout << No << endl; else { if (s[0] == ? || s[n - 1] == ? ) flag = 1; else { for (int i = 1; i < n - 1; i++) { if (s[i] == ? && s[i - 1] == ? || s[i] == ? && s[i + 1] == s[i - 1]) flag = 1; } } if (flag) cout << Yes << endl; else cout << No << endl; } return 0; } |
`include "defines.vh"
module primogen_tb;
reg clk = 0;
wire rst;
reg go = 0;
wire gen_ready;
wire gen_error;
wire [15:0] gen_res;
localparam N = 50;
reg [15:0] primes [N - 1:0];
integer i;
por pos_inst(
.clk(clk),
.rst(rst));
primogen gen(
.clk(clk),
.go(go),
.rst(rst),
.ready(gen_ready),
.error(gen_error),
.res(gen_res));
always #5 clk = !clk;
initial begin
// Need to test many cause of optimizations for first N primes
primes[0] = 1;
primes[1] = 2;
primes[2] = 3;
primes[3] = 5;
primes[4] = 7;
primes[5] = 11;
primes[6] = 13;
primes[7] = 17;
primes[8] = 19;
primes[9] = 23;
primes[10] = 29;
primes[11] = 31;
primes[12] = 37;
primes[13] = 41;
primes[14] = 43;
primes[15] = 47;
primes[16] = 53;
primes[17] = 59;
primes[18] = 61;
primes[19] = 67;
primes[20] = 71;
primes[21] = 73;
primes[22] = 79;
primes[23] = 83;
primes[24] = 89;
primes[25] = 97;
primes[26] = 101;
primes[27] = 103;
primes[28] = 107;
primes[29] = 109;
primes[30] = 113;
primes[31] = 127;
primes[32] = 131;
primes[33] = 137;
primes[34] = 139;
primes[35] = 149;
primes[36] = 151;
primes[37] = 157;
primes[38] = 163;
primes[39] = 167;
primes[40] = 173;
primes[41] = 179;
primes[42] = 181;
primes[43] = 191;
primes[44] = 193;
primes[45] = 197;
primes[46] = 199;
primes[47] = 211;
primes[48] = 223;
primes[49] = 227;
wait (!rst);
for (i = 0; i < N; ++i) begin
if (!gen_ready) begin
$fatal(1, "FAILED -- I=%d, READY=0", i);
end else if (gen_error) begin
$fatal(1, "FAILED -- I=%d, ERROR=1", i);
end else if (`isunknown(gen_res)) begin
$fatal(1, "FAILED -- I=%d, UNDEF (%d)", i, gen_res);
end else if (gen_res != primes[i]) begin
$fatal(1, "FAILED -- I=%d, PRIME=%d (should be %d)", i, gen_res, primes[i]);
end
// Ask for next prime
@(negedge clk);
go = 1;
@(posedge clk);
@(negedge clk) go = 0;
@(posedge gen_ready);
end
$display("primogen_tb ENDED");
$finish;
end
// initial
// $monitor("%t: go = %b, ready = %b, error = %b, res = %h", $time, go, gen_ready, gen_error, gen_res);
endmodule
|
module L1_Cache
(
input clk,
input rst,
input [31:0] addr,
input cs,
input we,
input [31:0] data_i,
output reg [31:0] data_o,
output reg stall
);
//wire [31:0] mem_addr_bus = addr_i;
wire [21:0] mem_tag = addr[31:10];
wire [4:0] mem_index = addr[9:5];
wire [4:0] mem_offset = addr[4:0];
wire [255:0] cache_data_i;
wire [255:0] cache_data_o;
wire [23:0] cache_tag_bus_i;
wire [23:0] cache_tag_bus_o;
wire cache_valid = cache_tag_bus_o[23];
wire cache_dirty = cache_tag_bus_o[22];
wire [21:0] cache_tag = cache_tag_bus_o[21:0];
wire [4:0] cache_index = mem_index;
wire [2:0] block_offset = mem_offset[4:2];
wire cache_hit;
wire [31:0] ext_addr = CPU.ext_mem_addr;
wire [255:0] ext_data_i = CPU.ext_mem_data_i;
reg [255:0] ext_data_o;
assign CPU.ext_mem_data_o = ext_data_o;
// cache initialized.
initial begin
data_o = 32'bz;
end
// indicates whether cache hit or not?
assign cache_hit = ((mem_tag == cache_tag) && cache_valid) ? 1'b1 : 1'b0;
// use multiplexer to decide which block to read
// TODO: fuck this part, need to change it to generate statement
Multiplexer8Way read_data (
.data_1 (cache_data_o[255:224]),
.data_2 (cache_data_o[223:192]),
.data_3 (cache_data_o[191:160]),
.data_4 (cache_data_o[159:128]),
.data_5 (cache_data_o[127:96]),
.data_6 (cache_data_o[95:64]),
.data_7 (cache_data_o[63:32]),
.data_8 (cache_data_o[31:0]),
.sel (block_offset),
.data_o (data_o)
);
wire [1:0] mux_sel_0 = (we && block_offset == 3'd0) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_1 = (we && block_offset == 3'd1) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_2 = (we && block_offset == 3'd2) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_3 = (we && block_offset == 3'd3) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_4 = (we && block_offset == 3'd4) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_5 = (we && block_offset == 3'd5) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_6 = (we && block_offset == 3'd6) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
wire [1:0] mux_sel_7 = (we && block_offset == 3'd7) ? 2'b00 : (cache_hit) ? 2'b10 : 2'b01;
// write data to specified cache block
Multiplexer4Way write_data_b1 (
.data_1 (data_i),
.data_2 (ext_data_i[255:224]),
.data_3 (cache_data_o[255:224]),
.data_4 (32'bz),
.sel (mux_sel_0),
.data_o (cache_data_i[255:224])
);
Multiplexer4Way write_data_b2 (
.data_1 (data_i),
.data_2 (ext_data_i[223:192]),
.data_3 (cache_data_o[223:192]),
.data_4 (32'bz),
.sel (mux_sel_1),
.data_o (cache_data_i[223:192])
);
Multiplexer4Way write_data_b3 (
.data_1 (data_i),
.data_2 (ext_data_i[191:160]),
.data_3 (cache_data_o[191:160]),
.data_4 (32'bz),
.sel (mux_sel_2),
.data_o (cache_data_i[191:160])
);
Multiplexer4Way write_data_b4 (
.data_1 (data_i),
.data_2 (ext_data_i[159:128]),
.data_3 (cache_data_o[159:128]),
.data_4 (32'bz),
.sel (mux_sel_3),
.data_o (cache_data_i[159:128])
);
Multiplexer4Way write_data_b5 (
.data_1 (data_i),
.data_2 (ext_data_i[127:96]),
.data_3 (cache_data_o[127:96]),
.data_4 (32'bz),
.sel (mux_sel_4),
.data_o (cache_data_i[127:96])
);
Multiplexer4Way write_data_b6 (
.data_1 (data_i),
.data_2 (ext_data_i[95:64]),
.data_3 (cache_data_o[95:64]),
.data_4 (32'bz),
.sel (mux_sel_5),
.data_o (cache_data_i[95:64])
);
Multiplexer4Way write_data_b7 (
.data_1 (data_i),
.data_2 (ext_data_i[63:32]),
.data_3 (cache_data_o[63:32]),
.data_4 (32'bz),
.sel (mux_sel_6),
.data_o (cache_data_i[63:32])
);
Multiplexer4Way write_data_b8 (
.data_1 (data_i),
.data_2 (ext_data_i[31:0]),
.data_3 (cache_data_o[31:0]),
.data_4 (32'bz),
.sel (mux_sel_7),
.data_o (cache_data_i[31:0])
);
// write tag
always @ (controller.sram_we) begin
assign cache_tag_bus_i = {1'b1, we, mem_tag};
assign ext_data_o = cache_data_i;
end
// module instantiations.
L1_Cache_Controller controller
(
.clk (clk),
.rst (rst),
.cache_cs (cs),
.cache_we (we),
.cache_hit (cache_hit),
.cache_dirty (cache_dirty),
.sram_cs (),
.sram_we (),
.stall (stall),
.mem_cs (CPU.ext_mem_cs),
.mem_we (CPU.ext_mem_we),
.mem_wb ()
);
SRAM #(.addr_width(5), .data_width(24), .mem_size(32)) tag_mem
(
.clk (clk),
.addr_i (cache_index),
.cs (controller.sram_cs),
.we (controller.sram_we),
.data_i (cache_tag_bus_i),
.data_o (cache_tag_bus_o)
);
SRAM #(.addr_width(5), .data_width(256), .mem_size(32)) data_mem
(
.clk (clk),
.addr_i (cache_index),
.cs (controller.sram_cs),
.we (controller.sram_we),
.data_i (cache_data_i),
.data_o (cache_data_o)
);
endmodule
|
module REGISTERTEST;
reg clock, write, reset;
reg [2:0] address1, address2, writeAddress;
reg [15:0] writeData;
wire [15:0] data1, data2;
parameter STEP = 2;
Register r (clock, write, reset, address1, address2, writeAddress, writeData, data1, data2);
always begin
clock = 0; #(STEP / 2);
clock = 1; #(STEP / 2);
end
initial begin
$dumpfile("registerTest.vcd");
$dumpvars(0, REGISTERTEST);
$monitor ("%t: clock = %b, write = %b, reset = %b, address1 = %b, writeAddress = %b, writeData = %b, data1 = %b", $time, clock, write, reset, address1, writeAddress, writeData, data1);
$display(" --- write ---");
write = 1'b1; writeAddress = 3'b000; writeData = 16'b0000_0000_0000_0001;
#STEP writeAddress = 3'b001; writeData = 16'b0000_0000_0000_0010;
#STEP writeAddress = 3'b010; writeData = 16'b0000_0000_0000_0100;
#STEP writeAddress = 3'b011; writeData = 16'b0000_0000_0000_1000;
#STEP writeAddress = 3'b100; writeData = 16'b0000_0000_0001_0000;
#STEP writeAddress = 3'b101; writeData = 16'b0000_0000_0010_0000;
#STEP writeAddress = 3'b110; writeData = 16'b0000_0000_0100_0000;
#STEP writeAddress = 3'b111; writeData = 16'b0000_0000_1000_0000;
#STEP writeAddress = 3'b000;
$display(" --- load ---");
write = 1'b0; address1 = 3'b000;
#STEP address1 = 3'b001;
#STEP address1 = 3'b010;
#STEP address1 = 3'b011;
#STEP address1 = 3'b100;
#STEP address1 = 3'b101;
#STEP address1 = 3'b110;
#STEP address1 = 3'b111;
#STEP address1 = 3'b000;
$display(" --- reset ---");
reset = 1'b1;
#STEP address1 = 3'b001;
#STEP address1 = 3'b010;
#STEP address1 = 3'b011;
#STEP address1 = 3'b100;
#STEP address1 = 3'b101;
#STEP address1 = 3'b110;
#STEP address1 = 3'b111;
#STEP address1 = 3'b000;
#STEP $finish;
end
endmodule // ALUTEST
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_PP_V |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_fifo(
input clock,
input reset,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
input [3:0] io_ctrl_fmt_len,
input [1:0] io_ctrl_cs_mode,
input [3:0] io_ctrl_wm_tx,
input [3:0] io_ctrl_wm_rx,
input io_link_tx_ready,
output io_link_tx_valid,
output [7:0] io_link_tx_bits,
input io_link_rx_valid,
input [7:0] io_link_rx_bits,
output [7:0] io_link_cnt,
output [1:0] io_link_fmt_proto,
output io_link_fmt_endian,
output io_link_fmt_iodir,
output io_link_cs_set,
output io_link_cs_clear,
output io_link_cs_hold,
input io_link_active,
output io_link_lock,
output io_tx_ready,
input io_tx_valid,
input [7:0] io_tx_bits,
input io_rx_ready,
output io_rx_valid,
output [7:0] io_rx_bits,
output io_ip_txwm,
output io_ip_rxwm
);
wire txq_clock;
wire txq_reset;
wire txq_io_enq_ready;
wire txq_io_enq_valid;
wire [7:0] txq_io_enq_bits;
wire txq_io_deq_ready;
wire txq_io_deq_valid;
wire [7:0] txq_io_deq_bits;
wire [3:0] txq_io_count;
wire rxq_clock;
wire rxq_reset;
wire rxq_io_enq_ready;
wire rxq_io_enq_valid;
wire [7:0] rxq_io_enq_bits;
wire rxq_io_deq_ready;
wire rxq_io_deq_valid;
wire [7:0] rxq_io_deq_bits;
wire [3:0] rxq_io_count;
wire fire_tx;
reg rxen;
reg [31:0] GEN_5;
wire T_94;
wire GEN_0;
wire T_96;
wire GEN_1;
wire T_97;
wire T_98;
wire T_99;
wire [2:0] T_101;
wire [1:0] T_102;
wire [3:0] T_104;
wire [2:0] T_106;
wire [1:0] T_108;
wire [3:0] GEN_2;
wire [3:0] T_110;
wire [3:0] GEN_3;
wire [3:0] T_111;
wire [3:0] cnt_quot;
wire T_112;
wire [1:0] T_115;
wire T_117;
wire [2:0] T_118;
wire T_120;
wire T_123;
wire T_126;
wire T_129;
wire T_131;
wire T_132;
wire cnt_rmdr;
wire [3:0] GEN_4;
wire [4:0] T_133;
wire [3:0] T_134;
reg [1:0] cs_mode;
reg [31:0] GEN_6;
wire cs_mode_hold;
wire cs_mode_off;
wire cs_update;
wire T_135;
wire cs_clear;
wire T_138;
wire T_139;
wire T_140;
wire T_142;
wire T_143;
wire T_144;
sirv_queue_1 txq (
.clock(txq_clock),
.reset(txq_reset),
.io_enq_ready(txq_io_enq_ready),
.io_enq_valid(txq_io_enq_valid),
.io_enq_bits(txq_io_enq_bits),
.io_deq_ready(txq_io_deq_ready),
.io_deq_valid(txq_io_deq_valid),
.io_deq_bits(txq_io_deq_bits),
.io_count(txq_io_count)
);
sirv_queue_1 rxq (
.clock(rxq_clock),
.reset(rxq_reset),
.io_enq_ready(rxq_io_enq_ready),
.io_enq_valid(rxq_io_enq_valid),
.io_enq_bits(rxq_io_enq_bits),
.io_deq_ready(rxq_io_deq_ready),
.io_deq_valid(rxq_io_deq_valid),
.io_deq_bits(rxq_io_deq_bits),
.io_count(rxq_io_count)
);
assign io_link_tx_valid = txq_io_deq_valid;
assign io_link_tx_bits = txq_io_deq_bits;
assign io_link_cnt = {{4'd0}, T_134};
assign io_link_fmt_proto = io_ctrl_fmt_proto;
assign io_link_fmt_endian = io_ctrl_fmt_endian;
assign io_link_fmt_iodir = io_ctrl_fmt_iodir;
assign io_link_cs_set = T_138;
assign io_link_cs_clear = T_140;
assign io_link_cs_hold = 1'h0;
assign io_link_lock = T_142;
assign io_tx_ready = txq_io_enq_ready;
assign io_rx_valid = rxq_io_deq_valid;
assign io_rx_bits = rxq_io_deq_bits;
assign io_ip_txwm = T_143;
assign io_ip_rxwm = T_144;
assign txq_clock = clock;
assign txq_reset = reset;
assign txq_io_enq_valid = io_tx_valid;
assign txq_io_enq_bits = io_tx_bits;
assign txq_io_deq_ready = io_link_tx_ready;
assign rxq_clock = clock;
assign rxq_reset = reset;
assign rxq_io_enq_valid = T_94;
assign rxq_io_enq_bits = io_link_rx_bits;
assign rxq_io_deq_ready = io_rx_ready;
assign fire_tx = io_link_tx_ready & io_link_tx_valid;
assign T_94 = io_link_rx_valid & rxen;
assign GEN_0 = io_link_rx_valid ? 1'h0 : rxen;
assign T_96 = io_link_fmt_iodir == 1'h0;
assign GEN_1 = fire_tx ? T_96 : GEN_0;
assign T_97 = 2'h0 == io_link_fmt_proto;
assign T_98 = 2'h1 == io_link_fmt_proto;
assign T_99 = 2'h2 == io_link_fmt_proto;
assign T_101 = io_ctrl_fmt_len[3:1];
assign T_102 = io_ctrl_fmt_len[3:2];
assign T_104 = T_97 ? io_ctrl_fmt_len : 4'h0;
assign T_106 = T_98 ? T_101 : 3'h0;
assign T_108 = T_99 ? T_102 : 2'h0;
assign GEN_2 = {{1'd0}, T_106};
assign T_110 = T_104 | GEN_2;
assign GEN_3 = {{2'd0}, T_108};
assign T_111 = T_110 | GEN_3;
assign cnt_quot = T_111;
assign T_112 = io_ctrl_fmt_len[0];
assign T_115 = io_ctrl_fmt_len[1:0];
assign T_117 = T_115 != 2'h0;
assign T_118 = io_ctrl_fmt_len[2:0];
assign T_120 = T_118 != 3'h0;
assign T_123 = T_97 ? T_112 : 1'h0;
assign T_126 = T_98 ? T_117 : 1'h0;
assign T_129 = T_99 ? T_120 : 1'h0;
assign T_131 = T_123 | T_126;
assign T_132 = T_131 | T_129;
assign cnt_rmdr = T_132;
assign GEN_4 = {{3'd0}, cnt_rmdr};
assign T_133 = cnt_quot + GEN_4;
assign T_134 = T_133[3:0];
assign cs_mode_hold = cs_mode == 2'h2;
assign cs_mode_off = cs_mode == 2'h3;
assign cs_update = cs_mode != io_ctrl_cs_mode;
assign T_135 = cs_mode_hold | cs_mode_off;
assign cs_clear = T_135 == 1'h0;
assign T_138 = cs_mode_off == 1'h0;
assign T_139 = fire_tx & cs_clear;
assign T_140 = cs_update | T_139;
assign T_142 = io_link_tx_valid | rxen;
assign T_143 = txq_io_count < io_ctrl_wm_tx;
assign T_144 = rxq_io_count > io_ctrl_wm_rx;
always @(posedge clock or posedge reset)
if (reset) begin
rxen <= 1'h0;
end else begin
if (fire_tx) begin
rxen <= T_96;
end else begin
if (io_link_rx_valid) begin
rxen <= 1'h0;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_mode <= 2'h0;
end else begin
cs_mode <= io_ctrl_cs_mode;
end
endmodule
|
//
// Copyright 2014 Ettus Research LLC
//
// Not necessarily that useful in general, but a good test block
//
// rfnoc-neuralnet: Pulled into fpga-src and exposed the pkt_size as an input parameter
// (I'm not really too sure what it's doing, but at least it makes sure tlast is aligned properly)
// Also, changed the count from 4 to 1. Lets count samples in this version, not bytes.
module packet_resizer_variable
(input clk, input reset,
input [15:0] next_dst_sid,
input [15:0] pkt_size,
input [31:0] i_tdata, input [127:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
output [31:0] o_tdata, output [127:0] o_tuser, output o_tlast, output o_tvalid, input o_tready);
reg [15:0] count;
reg first_packet_in_burst = 1'b1;
// Parse i_tuser
wire [1:0] TYPE_in = i_tuser[127:126];
wire TSI_in = i_tuser[125];
wire EOB_in = i_tuser[124];
wire [11:0] SEQ_in = i_tuser[123:112];
wire [15:0] LEN_in = i_tuser[111:96];
wire [15:0] SRC_in = i_tuser[95:80];
wire [15:0] DST_in = i_tuser[79:64];
wire [63:0] TIME_in = i_tuser[63:0];
// Generate o_tuser
wire [1:0] TYPE_out = TYPE_in;
wire TSI_out = TSI_in & first_packet_in_burst;
wire EOB_out = EOB_in & i_tlast;
wire [11:0] SEQ_out = SEQ_in; // Doesn't actually matter, it gets overwritten by chdr_framer
wire [15:0] LEN_out = LEN_in; // Only the bottom 2 bits actually matter, rest gets overwritten
wire [15:0] SRC_out = DST_in;
wire [15:0] DST_out = next_dst_sid;
wire [63:0] TIME_out = TIME_in;
// Pass nearly everything through unchanged
assign o_tdata = i_tdata;
assign o_tlast = (count == pkt_size) | EOB_out;
assign o_tuser = { TYPE_out, TSI_out, EOB_out, SEQ_out, LEN_out, SRC_out, DST_out, TIME_out };
assign o_tvalid = i_tvalid;
assign i_tready = o_tready;
always @(posedge clk)
if(reset)
count <= 16'd1;
else
if(o_tvalid & o_tready)
if(o_tlast)
count <= 16'd1;
else
count <= count + 16'd1;
always @(posedge clk)
if(reset)
first_packet_in_burst <= 1'b1;
else
if(o_tvalid & o_tready & o_tlast)
first_packet_in_burst <= EOB_out;
endmodule // packet_resizer
|
#include <bits/stdc++.h> using namespace std; bool iguales(vector<string>& x, vector<string>& y) { for (int i = (int)0; i < (int)x.size(); i++) { if (x[i] == T || y[i] == T ) continue; if (!(x[i] == y[i])) return false; } return true; } int main() { map<string, vector<vector<string> > > mapa; map<string, string> peso; int n, m, k; scanf( %d n , &n); string linea, nom, alfa, beta; while (n--) { getline(cin, linea); for (int i = (int)0; i < (int)linea.size(); i++) if (linea[i] == ( || linea[i] == ) || linea[i] == , ) linea[i] = ; vector<string> x; stringstream flujo(linea); while (flujo >> linea) x.push_back(linea); nom = x[1]; x.erase(x.begin()); x.erase(x.begin()); mapa[nom].push_back(x); } cin >> m; while (m--) { cin >> alfa >> beta; peso[beta] = alfa; } scanf( %d n , &k); while (k--) { getline(cin, linea); for (int i = (int)0; i < (int)linea.size(); i++) if (linea[i] == ( || linea[i] == ) || linea[i] == , ) linea[i] = ; vector<string> x; stringstream flujo(linea); int cc = 0; while (flujo >> linea) { if (cc == 0) { nom = linea; cc = 1; } else x.push_back(peso[linea]); } map<string, vector<vector<string> > >::iterator iter; iter = mapa.find(nom); if (iter != mapa.end()) { vector<vector<string> > r = iter->second; int tot = 0; for (int i = (int)0; i < (int)r.size(); i++) { vector<string> second = r[i]; if (x.size() == second.size()) { if (iguales(x, second)) tot++; } } cout << tot << endl; } else cout << 0 << endl; } } |
module x;
always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
octet_flag[0] = |arb_select_f[ 7: 0];
octet_flag[1] = |arb_select_f[15: 8];
octet_flag[2] = |arb_select_f[23:16];
octet_flag[3] = |arb_select_f[31:24];
octet_flag[4] = |arb_select_f[39:32];
octet_flag[5] = |arb_select_f[47:40];
octet_flag[6] = |arb_select_f[55:48];
octet_flag[7] = |arb_select_f[63:56];
octet_available = |octet_flag;
shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
end // always @ (arb_select_f)
endmodule
function [7:0] barrel_shifter;
input [7:0] source;
input [2:0] shift_amt;
begin
case (shift_amt) //synopsys parallel_case full_case
3'b0: barrel_shifter = source;
3'b1: barrel_shifter = {source[0], source[7:1]};
3'b2: barrel_shifter = {source[1:0], source[7:2]};
3'b3: barrel_shifter = {source[2:0], source[7:3]};
3'b4: barrel_shifter = {source[3:0], source[7:4]};
3'b5: barrel_shifter = {source[4:0], source[7:5]};
3'b6: barrel_shifter = {source[5:0], source[7:6]};
3'b7: barrel_shifter = {source[6:0], source[7]};
endcase // case(shift_amt)
end
endfunction // barrel_shifter
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 123; int n, t, label[N], times = 0; vector<int> e[N]; vector<pair<int, int> > res; void newLabel(int u) { res.push_back(make_pair(u, times)); label[u] = times; } void dfs(int u, int backLabel = -1, int p = 0) { newLabel(u); int numchild = (int)e[u].size() - (u > 1); for (int v : e[u]) { if (v == p) continue; if (label[u] >= t) { times = backLabel - numchild; newLabel(u); } times = label[u] + 1; dfs(v, label[u], u); if (label[v] > label[u]) { times = label[u]; newLabel(v); } ++times; newLabel(u); --numchild; } if (u > 1 && label[u] > backLabel) { times = backLabel; newLabel(u); } } int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); cin >> n; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; e[u].push_back(v); e[v].push_back(u); } t = -1; for (int i = 1; i <= n; ++i) t = max(t, (int)e[i].size()); dfs(1); cout << res.size() << n ; for (pair<int, int> x : res) { cout << x.first << << x.second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int mini[10], maxi[10], dist[10]; int main() { int n, i, total; scanf( %d , &n); total = 0; for (i = 0; i < 3; ++i) { scanf( %d %d , &mini[i], &maxi[i]); total += mini[i]; dist[i] = mini[i]; } i = 0; while (n - total > 0) { int available, pot; available = maxi[i] - mini[i]; pot = n - total; dist[i] += min(available, pot); total += min(available, pot); i++; } for (i = 0; i < 2; ++i) { printf( %d , dist[i]); } printf( %d n , dist[2]); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; const int MAXN = 5 + 300000; const int MAXB = 21; int n, arr[MAXN], nxt[MAXN][MAXB], memo[MAXN][MAXB]; int dp(int i, int k) { if (i == n) return n; int& ans = memo[i][k]; if (ans == -1) { if (nxt[i][k] == i) { ans = i; } else { ans = n; assert((arr[i] & (1 << k)) == 0); for (int j = 0; j < MAXB; ++j) { if (arr[i] & (1 << j)) { ans = min(ans, dp(nxt[1 + i][j], k)); } } } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int q; cin >> n >> q; memset(nxt, -1, sizeof nxt); for (int i = (int)0; i < (int)n; ++i) { int x; cin >> x; arr[i] = x; for (int k = 0; k < MAXB; ++k) { if (x & (1 << k)) { nxt[i][k] = i; } } } memset(memo, -1, sizeof memo); for (int j = 0; j < MAXB; ++j) { nxt[n][j] = n; } for (int i = n - 1; i >= 0; --i) { for (int j = 0; j < MAXB; ++j) { if (nxt[i][j] == -1) { nxt[i][j] = nxt[1 + i][j]; } } } while (q--) { int x, y; cin >> x >> y; --x; --y; bool ans = false; for (int j = 0; j < MAXB; ++j) { if ((arr[y] & (1 << j)) && dp(x, j) <= y) { ans = true; break; } } cout << (ans ? Shi : Fou ) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 200; int num[MAX], vis[MAX]; int main() { int n, m, a; while (scanf( %d %d , &n, &m) == 2) { memset(vis, 0, sizeof(vis)); for (int i = 0; i < m; i++) { scanf( %d , &a); for (int i = a; i <= n; i++) if (!vis[i]) { num[i] = a; vis[i] = 1; } } for (int i = 1; i <= n; i++) { if (i == 1) printf( %d , num[i]); else printf( %d , num[i]); } printf( n ); } return 0; } |
module bus_arb (
clk,
reset_,
mcs_addr,
mcs_ready,
mcs_wr_data,
mcs_wr_enable,
mcs_rd_data,
mcs_rd_enable,
mcs_byte_enable,
addr,
rnw,
req,
wr_data,
gpio_cs,
gpio_rd_data,
gpio_rdy,
disp_cs,
disp_rd_data,
disp_rdy,
uart_cs,
uart_rd_data,
uart_rdy);
input clk;
input reset_;
// Bus controller to distribute MicroBlaze IO bus to our own hardware modules.
// This circuit decodes the address bus and generates module-independent
// bus control signals to each hardware module (like display, uart, gpio)
// and provides a ready timeout function to prevent the CPU from waiting
// indefinitely for a response (as would be the case if software tried to
// access an unmapped memory location).
// MicroBlaze IO Bus
input [31:0] mcs_addr; // Address from MicroBlaze
output mcs_ready; // Request complete indicator to MicroBlaze
input [31:0] mcs_wr_data; // Write data from MicroBlaze
input mcs_wr_enable; // Write enable from MicroBlaze
output [31:0] mcs_rd_data; // Read data from hardware
input mcs_rd_enable; // Read enable from MicroBlaze
input [3:0] mcs_byte_enable; // Which byte(s) in 32-bit longword are being accessed
// Local IO Bus
output [7:0] addr; // Address to lsuc module
output rnw; // Read, not write, indicator
output req; // Bus request
output [7:0] wr_data; // Write data to lsuc module
output gpio_cs; // GPIO module chip select
input [7:0] gpio_rd_data; // Read data from GPIO module
input gpio_rdy; // Ready indicator from GPIO module
output disp_cs; // Display module chip select
input [7:0] disp_rd_data; // Read data from display module
input disp_rdy; // Ready indicator from display module
output uart_cs; // UART module chip select
input [7:0] uart_rd_data; // Read data from UART module
input uart_rdy; // Ready indicator from UART module
reg [31:0] mcs_rd_data;
reg mcs_ready;
reg [9:0] req_timeout_ctr;
assign addr = mcs_addr[7:0];
assign rnw = ~mcs_wr_enable;
assign req = mcs_rd_enable || mcs_wr_enable;
assign wr_data = mcs_wr_data[7:0];
// Top-level memory mapping
assign gpio_cs = mcs_addr[31:28] == 4'hc; // GPIO module mapped to 0x4000_00xx addresses
assign disp_cs = mcs_addr[31:28] == 4'hd; // Display module mapped to 0x4000_00xx addresses
assign uart_cs = mcs_addr[31:28] == 4'he; // UART module mapped to 0x4000_00xx addresses
// Readback generation
always@ (posedge clk or negedge reset_)
if (!reset_)
mcs_rd_data <= 32'h0000_0000;
else if (rnw && gpio_cs && gpio_rdy)
mcs_rd_data <= {4{gpio_rd_data}};
else if (rnw && disp_cs && disp_rdy)
mcs_rd_data <= {4{disp_rd_data}};
else if (rnw && uart_cs && uart_rdy)
mcs_rd_data <= {4{uart_rd_data}};
// Request ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
mcs_ready <= 1'b0;
else if (gpio_cs)
mcs_ready <= gpio_rdy;
else if (disp_cs)
mcs_ready <= disp_rdy;
else if (uart_cs)
mcs_ready <= uart_rdy;
else
mcs_ready <= &req_timeout_ctr;
// Request timeout generation (prevents CPU from locking if no harware responds to request)
always@ (posedge clk or negedge reset_)
if (!reset_)
req_timeout_ctr <= 10'd0;
else if (mcs_ready)
req_timeout_ctr <= 10'd0;
else if (req)
req_timeout_ctr <= 10'd1;
else if (req_timeout_ctr != 10'd0)
req_timeout_ctr <= req_timeout_ctr + 10'd1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cout.precision(30); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<pair<long long, long long>> ps(n); for (int i = 0; i < n; i++) { cin >> ps[i].first >> ps[i].second; } sort(ps.begin(), ps.end(), [&](pair<long long, long long> a, pair<long long, long long> b) { return make_pair(a.second, a.first) < make_pair(b.second, b.first); }); vector<long long> hadv(n, 0), hadh(n, 0); vector<pair<long long, long long>> v, h; vector<pair<pair<long long, long long>, pair<long long, long long>>> verts; long long cury = ps[0].second; for (int i = 1; i < n; i++) { if (cury != ps[i].second) { cury = ps[i].second; } else { hadv[i - 1] = 1; hadv[i] = 1; verts.push_back({ps[i - 1], ps[i]}); } } for (int i = 0; i < n; i++) { if (!hadv[i]) v.push_back(ps[i]), v.push_back(ps[i]); } sort(ps.begin(), ps.end()); vector<pair<pair<long long, long long>, pair<long long, long long>>> hors; long long curx = ps[0].first; for (int i = 1; i < n; i++) { if (curx != ps[i].first) { curx = ps[i].first; } else { hadh[i - 1] = 1; hadh[i] = 1; hors.push_back({ps[i - 1], ps[i]}); } } for (int i = 0; i < n; i++) { if (!hadh[i]) h.push_back(ps[i]), h.push_back(ps[i]); } swap(hors, verts); swap(h, v); auto inter = [&](pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c, pair<long long, long long> d) { if (c.first < a.first && a.first < d.first) { if (a.second < c.second && c.second < b.second) return true; } return false; }; vector<vector<long long>> g(verts.size()); for (int i = 0; i < verts.size(); i++) { for (int j = 0; j < hors.size(); j++) { if (inter(verts[i].first, verts[i].second, hors[j].first, hors[j].second)) g[i].push_back(j); } } vector<long long> to(hors.size(), -1); vector<long long> used(verts.size(), 0); vector<long long> from(verts.size(), -1); function<bool(int)> dfs = [&](int v) { if (used[v]) return false; used[v] = 1; for (int u : g[v]) { if (to[u] == -1 || dfs(to[u])) { to[u] = v; from[v] = u; return true; } } return false; }; for (int i = 0; i < verts.size(); i++) { used.assign(verts.size(), 0); dfs(i); } used.assign(verts.size(), 0); vector<long long> used1(hors.size(), 0); function<void(int)> dfs1 = [&](int v) { if (used[v]) return; used[v] = 1; for (int u : g[v]) { if (!used1[u]) { used1[u] = 1; dfs1(to[u]); } } }; vector<long long> free(verts.size(), 1); for (int i : to) if (i != -1) free[i] = 0; for (int i = 0; i < verts.size(); i++) if (free[i]) dfs1(i); for (int i = 0; i < verts.size(); i++) { auto a = verts[i].first, b = verts[i].second; if (i == 0 || verts[i - 1].second != verts[i].first) { if (i > 0) v.push_back(verts[i - 1].second); v.push_back(a); } if (!used[i]) v.push_back(a), v.push_back(b); } if (!verts.empty()) v.push_back(verts.back().second); for (int i = 0; i < hors.size(); i++) { auto a = hors[i].first, b = hors[i].second; if (i == 0 || hors[i - 1].second != hors[i].first) { if (i > 0) h.push_back(hors[i - 1].second); h.push_back(a); } if (used1[i]) h.push_back(a), h.push_back(b); } if (!hors.empty()) h.push_back(hors.back().second); cout << h.size() / 2 << endl; for (int i = 0; i < h.size(); i++) cout << h[i].first << << h[i].second << ((i % 2) ? n : ); cout << v.size() / 2 << endl; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << ((i % 2) ? n : ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int b[maxn]; int c[maxn]; bool visit[maxn]; int n, k; int main() { int i, p; while (scanf( %d%d , &n, &k) != EOF) { for (i = 1; i <= n; i++) scanf( %d , &b[i]); memset(c, 0, sizeof(c)); memset(visit, false, sizeof(visit)); for (p = 1; p <= n; p++) { for (i = 1; i <= n; i++) if (c[i] == b[i] && visit[i] == false) break; printf( %d , i); int u = i; visit[u] = true; for (i = 1; i <= n; i++) if (u >= i + k) c[i]++; else break; } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k; void nhap() { cin >> n >> m >> k; } long long tinh(long long x) { if (x > k) return -1e19 + 10; long long r = n / (x + 1); long long h = k - x; long long d = m / (h + 1); return r * d; } void xuli() { if (n - 1 + m - 1 < k) { cout << -1; return; } long long kq = -1e19 + 10; for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { kq = max(kq, tinh(1ll * i - 1)); kq = max(kq, tinh(n / i - 1)); } } swap(n, m); for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { kq = max(kq, tinh(1ll * i - 1)); kq = max(kq, tinh(n / i - 1)); } } cout << kq; } int main() { nhap(); xuli(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_LP_V
`define SKY130_FD_SC_LP__DLRTP_LP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_LP_V
|
/**
* bsg_cache_to_axi.v
*
* @author tommy
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_to_axi
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(num_cache_p)
// tag fifo size can be greater than number of cache dma interfaces
// Set to maximum possible outstanding requests to avoid stalling
,parameter tag_fifo_els_p=num_cache_p
,parameter `BSG_INV_PARAM(axi_id_width_p) // 6
,parameter `BSG_INV_PARAM(axi_addr_width_p)
,parameter `BSG_INV_PARAM(axi_data_width_p)
,parameter `BSG_INV_PARAM(axi_burst_len_p)
,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
,parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
,parameter axi_strb_width_lp=(axi_data_width_p>>3)
)
(
input clk_i
,input reset_i
// cache side
,input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i
,input [num_cache_p-1:0] dma_pkt_v_i
,output logic [num_cache_p-1:0] dma_pkt_yumi_o
,output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
,output logic [num_cache_p-1:0] dma_data_v_o
,input [num_cache_p-1:0] dma_data_ready_i
,input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
,input [num_cache_p-1:0] dma_data_v_i
,output logic [num_cache_p-1:0] dma_data_yumi_o
// axi write address channel
,output logic [axi_id_width_p-1:0] axi_awid_o
,output logic [axi_addr_width_p-1:0] axi_awaddr_o
,output logic [7:0] axi_awlen_o
,output logic [2:0] axi_awsize_o
,output logic [1:0] axi_awburst_o
,output logic [3:0] axi_awcache_o
,output logic [2:0] axi_awprot_o
,output logic axi_awlock_o
,output logic axi_awvalid_o
,input axi_awready_i
// axi write data channel
,output logic [axi_data_width_p-1:0] axi_wdata_o
,output logic [axi_strb_width_lp-1:0] axi_wstrb_o
,output logic axi_wlast_o
,output logic axi_wvalid_o
,input axi_wready_i
// axi write response channel
,input [axi_id_width_p-1:0] axi_bid_i
,input [1:0] axi_bresp_i
,input axi_bvalid_i
,output logic axi_bready_o
// axi read address channel
,output logic [axi_id_width_p-1:0] axi_arid_o
,output logic [axi_addr_width_p-1:0] axi_araddr_o
,output logic [7:0] axi_arlen_o
,output logic [2:0] axi_arsize_o
,output logic [1:0] axi_arburst_o
,output logic [3:0] axi_arcache_o
,output logic [2:0] axi_arprot_o
,output logic axi_arlock_o
,output logic axi_arvalid_o
,input axi_arready_i
// axi read data channel
,input [axi_id_width_p-1:0] axi_rid_i
,input [axi_data_width_p-1:0] axi_rdata_i
,input [1:0] axi_rresp_i
,input axi_rlast_i
,input axi_rvalid_i
,output logic axi_rready_o
);
// dma packets from caches
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s [num_cache_p-1:0] dma_pkt;
assign dma_pkt = dma_pkt_i;
// reader round-robin
//
logic [num_cache_p-1:0] read_rr_v_li;
logic [num_cache_p-1:0] read_rr_yumi_lo;
logic read_rr_v_lo;
bsg_cache_dma_pkt_s read_rr_dma_pkt;
logic [lg_num_cache_lp-1:0] read_rr_tag_lo;
logic read_rr_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
assign read_rr_v_li[i] = dma_pkt_v_i[i] & ~dma_pkt[i].write_not_read;
end
bsg_round_robin_n_to_1 #(
.width_p(dma_pkt_width_lp)
,.num_in_p(num_cache_p)
,.strict_p(0)
) read_rr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_pkt)
,.v_i(read_rr_v_li)
,.yumi_o(read_rr_yumi_lo)
,.v_o(read_rr_v_lo)
,.data_o(read_rr_dma_pkt)
,.tag_o(read_rr_tag_lo)
,.yumi_i(read_rr_yumi_li)
);
// writer round-robin
//
logic [num_cache_p-1:0] write_rr_v_li;
logic [num_cache_p-1:0] write_rr_yumi_lo;
logic write_rr_v_lo;
bsg_cache_dma_pkt_s write_rr_dma_pkt;
logic [lg_num_cache_lp-1:0] write_rr_tag_lo;
logic write_rr_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
assign write_rr_v_li[i] = dma_pkt_v_i[i] & dma_pkt[i].write_not_read;
end
bsg_round_robin_n_to_1 #(
.width_p(dma_pkt_width_lp)
,.num_in_p(num_cache_p)
,.strict_p(0)
) write_rr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_pkt)
,.v_i(write_rr_v_li)
,.yumi_o(write_rr_yumi_lo)
,.v_o(write_rr_v_lo)
,.data_o(write_rr_dma_pkt)
,.tag_o(write_rr_tag_lo)
,.yumi_i(write_rr_yumi_li)
);
// address translation
//
logic [axi_addr_width_p-1:0] rx_axi_addr;
logic [axi_addr_width_p-1:0] tx_axi_addr;
assign rx_axi_addr = {
{(axi_addr_width_p-lg_num_cache_lp-addr_width_p){1'b0}}
,read_rr_tag_lo
,read_rr_dma_pkt.addr
};
assign tx_axi_addr = {
{(axi_addr_width_p-lg_num_cache_lp-addr_width_p){1'b0}}
,write_rr_tag_lo
,write_rr_dma_pkt.addr
};
// dma_pkt handshake
//
for (genvar i = 0; i < num_cache_p; i++) begin
assign dma_pkt_yumi_o[i] = dma_pkt[i].write_not_read
? write_rr_yumi_lo[i]
: read_rr_yumi_lo[i];
end
// rx
//
bsg_cache_to_axi_rx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.tag_fifo_els_p(tag_fifo_els_p)
,.axi_id_width_p(axi_id_width_p)
,.axi_addr_width_p(axi_addr_width_p)
,.axi_data_width_p(axi_data_width_p)
,.axi_burst_len_p(axi_burst_len_p)
) axi_rx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(read_rr_v_lo)
,.yumi_o(read_rr_yumi_li)
,.tag_i(read_rr_tag_lo)
,.axi_addr_i(rx_axi_addr)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_ready_i(dma_data_ready_i)
,.axi_arid_o(axi_arid_o)
,.axi_araddr_o(axi_araddr_o)
,.axi_arlen_o(axi_arlen_o)
,.axi_arsize_o(axi_arsize_o)
,.axi_arburst_o(axi_arburst_o)
,.axi_arcache_o(axi_arcache_o)
,.axi_arvalid_o(axi_arvalid_o)
,.axi_arlock_o(axi_arlock_o)
,.axi_arprot_o(axi_arprot_o)
,.axi_arready_i(axi_arready_i)
,.axi_rid_i(axi_rid_i)
,.axi_rdata_i(axi_rdata_i)
,.axi_rresp_i(axi_rresp_i)
,.axi_rlast_i(axi_rlast_i)
,.axi_rvalid_i(axi_rvalid_i)
,.axi_rready_o(axi_rready_o)
);
// tx
//
bsg_cache_to_axi_tx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.tag_fifo_els_p(tag_fifo_els_p)
,.axi_id_width_p(axi_id_width_p)
,.axi_addr_width_p(axi_addr_width_p)
,.axi_data_width_p(axi_data_width_p)
,.axi_burst_len_p(axi_burst_len_p)
) axi_tx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(write_rr_v_lo)
,.yumi_o(write_rr_yumi_li)
,.tag_i(write_rr_tag_lo)
,.axi_addr_i(tx_axi_addr)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_yumi_o(dma_data_yumi_o)
,.axi_awid_o(axi_awid_o)
,.axi_awaddr_o(axi_awaddr_o)
,.axi_awlen_o(axi_awlen_o)
,.axi_awsize_o(axi_awsize_o)
,.axi_awburst_o(axi_awburst_o)
,.axi_awcache_o(axi_awcache_o)
,.axi_awprot_o(axi_awprot_o)
,.axi_awlock_o(axi_awlock_o)
,.axi_awvalid_o(axi_awvalid_o)
,.axi_awready_i(axi_awready_i)
,.axi_wdata_o(axi_wdata_o)
,.axi_wstrb_o(axi_wstrb_o)
,.axi_wlast_o(axi_wlast_o)
,.axi_wvalid_o(axi_wvalid_o)
,.axi_wready_i(axi_wready_i)
,.axi_bid_i(axi_bid_i)
,.axi_bresp_i(axi_bresp_i)
,.axi_bvalid_i(axi_bvalid_i)
,.axi_bready_o(axi_bready_o)
);
// assertions
//
// synopsys translate_off
initial begin
assert(data_width_p*block_size_in_words_p == axi_data_width_p*axi_burst_len_p)
else $error("cache block size and axi transfer size do not match.");
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_axi)
|
module Alu(input[31:0] op1,
input[31:0] op2,
input[3:0] f,
output reg[31:0] result,
output zero);
always @(op1, op2, f)
case (f)
0: result = op1 + op2;
1: result = op1 - op2;
2: result = op1 & op2;
3: result = op1 | op2;
4: result = op1 ~| op2;
5: result = op1 ^ op2;
6: result = op1 << op2;
7: result = op1 >> op2;
8: result = op1 >>> op2;
9: result = ($signed(op1) < $signed(op2)) ? 1 : 0; //SLT
10: result = (op1 < op2) ? 1 : 0; //SLTU
/* 11:
12:
13:
14:
15:*/
endcase
assign zero = result == 0;
endmodule
module Mult_Div_Alu(input[31:0] op1,
input[31:0] op2,
input[3:0] f,
input en,
output reg[31:0] result_hi,
output reg[31:0] result_lo);
always @(op1, op2, f)
if(en) begin
case (f)
0: begin
result_lo = $signed(op1) / $signed(op2);
result_hi = $signed(op1) % $signed(op2);
end
1: begin
result_lo = op1 / op2;
result_hi = op1 % op2;
end
2: begin
{result_hi, result_lo} = $signed(op1) * $signed(op2);
end
3: begin
{result_hi, result_lo} = op1 * op2;
end
/* 4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15: */
endcase
$display("\tR[lo] = %x (hex)", result_lo);
$display("\tR[hi] = %x (hex)", result_hi);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int t, sp[N]; map<int, int> n, m, s; vector<pair<int, int> > _n, _m, _s; long long n_val, m_val, s_val; void sieve(void) { for (int i = 2; i * i < N; ++i) { if (sp[i]) continue; sp[i] = i; for (int j = i * i; j < N; j += i) { if (sp[j]) continue; sp[j] = i; } } for (int i = 2; i < N; ++i) { if (sp[i]) continue; sp[i] = i; } } int size; long long Less; void backtrack(int at, long long val) { if (at == size) { if (val <= n_val) ++Less; return; } for (int i = 0; i <= _s[at].second; ++i) { backtrack(at + 1, val); val *= 1LL * _s[at].first; } return; } int main() { sieve(); scanf( %d , &t); while (t--) { n.clear(), m.clear(), s.clear(); _n.clear(), _m.clear(), _s.clear(); for (int i = 0; i < 3; ++i) { int x; scanf( %d , &x); while (x > 1) { int p = sp[x]; while (x % p == 0) { ++n[p], x /= p; } } } for (int i = 0; i < 3; ++i) { int x; scanf( %d , &x); while (x > 1) { int p = sp[x]; while (x % p == 0) { ++m[p], x /= p; } } } for (int i = 0; i < 3; ++i) { int x; scanf( %d , &x); while (x > 1) { int p = sp[x]; while (x % p == 0) { ++s[p], x /= p; } } } ++s[2]; n_val = m_val = s_val = 1LL; for (auto it : n) { _n.emplace_back(it.first, it.second); for (int i = 0; i < it.second; ++i) { n_val *= 1LL * it.first; } } for (auto it : m) { _m.emplace_back(it.first, it.second); for (int i = 0; i < it.second; ++i) { m_val *= 1LL * it.first; } } for (auto it : s) { _s.emplace_back(it.first, it.second); for (int i = 0; i < it.second; ++i) { s_val *= 1LL * it.first; } } int sz = _n.size(); long long tot = m_val; for (int mask = 1; mask < 1 << sz; ++mask) { int nope = 0, on = 0; long long num = 1LL; for (int i = 0; i < sz; ++i) { if (!(mask & 1 << i)) continue; ++on; int p = _n[i].first, e = _n[i].second; if (s[p] + 1 > e) { nope = 1; break; } for (int j = 0; j <= s[p]; ++j) { num *= 1LL * p; } } if (nope) continue; long long cur = m_val / num; if (on & 1) cur = -cur; tot += cur; } Less = 0; size = _s.size(); backtrack(0, 1LL); tot += Less; printf( %lld n , tot); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; char cur = s[0]; int count = 1; for (int i = 1; i < s.length(); i++) { if (cur == s[i]) { count++; if (count == 7) { cout << YES << endl; return 0; } } else { count = 1; cur = s[i]; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> inline int lb(int a) { return a & (-a); } long long a[100100], bit[7][15][100100]; int n, m, t; inline void adj(int z, int zm, int pos, long long val) { for (int i = pos; i <= n; i += lb(i)) bit[z][zm][i] += val; } inline long long qry(int z, int zm, int pos) { if (pos <= 0) return 0; long long rt = 0; for (int i = pos; i > 0; i -= lb(i)) rt += bit[z][zm][i]; return rt; } inline long long sum(int z, int zm, int l, int r) { int z2 = z * 2 - 2; int lb = l + zm - 1, rb = r; if (lb > r) return 0; while (rb % z2 != lb % z2) rb--; lb -= z2; if (rb < l) return 0; return qry(z, rb % z2, rb) - qry(z, lb % z2, lb); } inline int s(int z, int i) { int mod = i % (2 * z - 2); if (mod == 0) return 2; else if (mod <= z) return mod; else return 2 * z - mod; } inline void update(int p, int v) { for (int z = 2; z <= 6; z++) { int z2 = z * 2 - 2; adj(z, p % z2, p, v - a[p]); } a[p] = v; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int in; scanf( %d , &in); update(i, in); } scanf( %d , &m); while (m-- > 0) { scanf( %d , &t); if (t == 1) { int p, v; scanf( %d%d , &p, &v); update(p, v); } else { int l, r, z; scanf( %d%d%d , &l, &r, &z); long long ans = 0; int z2 = z * 2 - 2; for (int i = 1; i <= z2; i++) { ans += s(z, i) * sum(z, i, l, r); } printf( %I64d n , ans); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, t; char G[500005]; int solve(int k) { int last = n, i; int hs, ss; hs = ss = 0; for (i = 1; i <= n; i++) { if (G[i] == H ) hs++; if (G[i] == S ) ss++; if (G[i] == H ) last = i; if (hs - ss >= k && G[i] != . ) last = i; } if (hs - ss > k) { return 0; } if (t < last) return 0; int remT = t - 1; int pos, val = k, twice, st; for (pos = 1; pos <= last; pos++) { if (remT < 0) return 0; if (G[pos] == H ) { if (val > 0) val--; else { twice = (last - pos) << 1; if (twice <= remT) { return 1; } else { st = pos; ss = hs = 0; for (; pos <= last; pos++) { if (G[pos] == H ) hs++; else if (G[pos] == S ) ss++; if (hs <= ss) break; } if (pos > last) { return 0; } twice = (pos - st) * 3; remT -= twice; if (remT < 0) return 0; } } } else if (G[pos] == S ) val++; remT--; } return 1; } int main() { scanf( %d%d , &n, &t); scanf( %s , G + 1); int high = n + 1; int low = 0; int mid; while (low < high) { mid = (low + high) / 2; if (solve(mid)) { high = mid; } else { low = mid + 1; } } if (high <= n) printf( %d , high); else printf( -1 ); return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cyclone10lp_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int MSB1(long long x) { int d = 0; while ((1LL << d) <= x) d++; return d; } int main() { int n, m; cin >> n >> m; struct Elm { int l, r, x; }; vector<vector<Elm>> vals(n); while (m--) { int op; cin >> op; if (op == 1) { int t, l, r, x; cin >> t >> l >> r >> x, t--; vals[t].emplace_back(Elm{l, r, x}); continue; } int t, v; cin >> t >> v, t--; set<int> se; for (int l = v, r = v; t < n; t++, l += MSB1(l - 1), r += MSB1(r)) { for (auto &e : vals[t]) if (e.l <= r && l <= e.r) se.emplace(e.x); } cout << se.size() << endl; } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:36:55 06/27/2013
// Design Name: qmult
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Test_mult.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qmult
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_mult;
// Inputs
reg [31:0] i_multiplicand;
reg [31:0] i_multiplier;
// Outputs
wire [31:0] o_result;
wire ovr;
// Instantiate the Unit Under Test (UUT)
qmult #(19,32) uut (
.i_multiplicand(i_multiplicand),
.i_multiplier(i_multiplier),
.o_result(o_result),
.ovr(ovr)
);
initial begin
$monitor ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result, ovr); // Monitor the stuff we care about
// Initialize Inputs
i_multiplicand = 32'b00000000000110010010000111111011; //pi = 3.141592
i_multiplicand[31] = 0; // i_multiplicand sign
i_multiplier[31] = 0; // i_multiplier sign
i_multiplier[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
#100 i_multiplier[0] = 1; // 1.91E-6
end
// Add stimulus here
always begin
#10 i_multiplier[30:0] = (i_multiplier[30:0] << 1) + 1; // Why not??
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_BLACKBOX_V
`define SKY130_FD_SC_HS__AND4_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_BLACKBOX_V
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "config.vh"
`include "bch_defs.vh"
/*
* Tradition chien search, for each cycle, check if the
* value of all the sumuations is zero, if so, this location
* is a bit error.
*/
module bch_error_tmec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0,
parameter ACCUM = PIPELINE_STAGES > 1 ? `CONFIG_LUT_SZ : 1
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
/*
* We have to sum all the chien outputs. Split up the outputs and sum
* them into accumulators. For instance, if REGS == 13, and ACCUM == 3
* then we group together the chien outputs into 5 regs, 4 regs, and
* 4 regs. We then sum together those accumulators.
*/
localparam REGS = `BCH_T(P) + 1;
localparam W_A = (REGS + ACCUM - 1) / ACCUM;
localparam W_B = REGS / ACCUM;
localparam ACCUM_A = REGS - W_B * ACCUM;
localparam ACCUM_B = ACCUM - ACCUM_A;
wire [BITS*`BCH_CHIEN_SZ(P)-1:0] chien;
wire [ACCUM*BITS*M-1:0] accum;
wire [ACCUM*BITS*M-1:0] accum_pipelined;
wire [BITS*M-1:0] sum;
wire [BITS*M-1:0] sum_pipelined;
wire [BITS-1:0] err_raw;
wire first_raw;
genvar i, j;
if (`BCH_T(P) == 1)
tmec_does_not_support_sec u_tdnss();
if (PIPELINE_STAGES > 3)
tmec_only_supports_3_pipeline_stages u_tos2ps();
if (ACCUM > REGS)
tmec_accum_must_be_less_than_or_equal_to_regs u_tambltoretr();
if (ACCUM > 1 && PIPELINE_STAGES < 2)
tmec_accum_requires_2_or_more_pipeline_stages u_tar2omps();
bch_chien #(P, BITS, REG_RATIO) u_chien(
.clk(clk),
.start(start),
.sigma(sigma),
.chien(chien),
.first(first_raw)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline (
.clk(clk),
.i(first_raw),
.o(first)
);
for (i = 0; i < BITS; i = i + 1) begin : BITS_BLOCK
for (j = 0; j < ACCUM_A; j = j + 1) begin : ACCUM_A_BLOCK
finite_parallel_adder #(M, W_A) u_adder(
.in(chien[i*`BCH_CHIEN_SZ(P)+j*W_A*M+:W_A*M]),
.out(accum[(i*ACCUM+j)*M+:M])
);
end
for (j = 0; j < ACCUM_B; j = j + 1) begin : ACCUM_B_BLOCK
finite_parallel_adder #(M, W_B) u_adder(
.in(chien[i*`BCH_CHIEN_SZ(P)+(ACCUM_A*W_A+j*W_B)*M+:W_B*M]),
.out(accum[(i*ACCUM+ACCUM_A+j)*M+:M])
);
end
end
pipeline #(PIPELINE_STAGES > 1) u_accum_pipeline [ACCUM*BITS*M-1:0] (clk, accum, accum_pipelined);
finite_parallel_adder #(M, ACCUM) u_adder [BITS-1:0] (accum_pipelined, sum);
pipeline #(PIPELINE_STAGES > 2) u_sum_pipeline [BITS*M-1:0] (clk, sum, sum_pipelined);
zero_cla #(M, PIPELINE_STAGES > 2 ? 1 : ACCUM) u_zero [BITS-1:0] (sum_pipelined, err_raw);
pipeline #(PIPELINE_STAGES > 0) u_err_pipeline1 [BITS-1:0] (
.clk(clk),
.i(err_raw[BITS-1:0]),
.o(err[BITS-1:0])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); ; int n, m; cin >> n >> m; int dem = 0; if (m % n != 0) { cout << -1; return 0; } int sum = m / n; while (sum % 2 == 0) { sum /= 2; dem++; } while (sum % 3 == 0) { sum /= 3; dem++; } if (sum == 1) cout << dem; else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; string s; vector<int> v; int main(int argc, char const *argv[]) { cin >> s; int n = s.size(); sort(s.begin(), s.end()); for (int i = 0; i < n; i++) { if (s[i] > 0 ) { swap(s[0], s[i]); break; } } string q; cin >> q; for (int i = 0; i < n; i++) { if (q.size() != s.size() or q[i] != s[i]) { cout << WRONG_ANSWER << endl; return 0; } } cout << OK << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 10; const long long INF = (long long)1e9; struct Point { long long x, y; Point() : x(), y() {} void scan() { scanf( %lld%lld , &x, &y); } bool operator<(const Point &a) const { return y < a.y || (y == a.y && x < a.x); } }; long long sqr(long long a) { return a * a; } Point p[N]; long long prefMinX[N], prefMaxX[N]; long long suffMinX[N], suffMaxX[N]; int n; void precalc() { for (int i = 0; i < n; i++) { prefMinX[i] = (i == 0 ? p[i].x : min(prefMinX[i - 1], p[i].x)); prefMaxX[i] = (i == 0 ? p[i].x : max(prefMaxX[i - 1], p[i].x)); } for (int i = n - 1; i >= 0; i--) { suffMinX[i] = (i == n - 1 ? p[i].x : min(suffMinX[i + 1], p[i].x)); suffMaxX[i] = (i == n - 1 ? p[i].x : max(suffMaxX[i + 1], p[i].x)); } } long long getMaxD(long long y1, long long y2, long long x1, long long x2) { long long d = max(sqr(y1 - y2), sqr(x1 - x2)); d = max(d, max(sqr(y1), sqr(y2)) + max(sqr(x1), sqr(x2))); return d; } bool check(long long d) { long long xD = sqr(prefMinX[n - 1] - prefMaxX[n - 1]); if (xD <= d) return true; int it = 0; int kek = n; 42; for (int i = 0; i < n; i++) 42; 42; for (int i = 0; i < n; i++) { if (i != 0 && p[i].y == p[i - 1].y) continue; while (it < n && (it <= i || (sqr(p[it].y - p[i].y) <= d))) it++; while (kek > 0 && llabs(p[kek - 1].y) > llabs(p[i].y)) kek--; int cur = min(kek, it); 42; if (cur < i) break; long long y1 = p[i].y; long long y2 = p[cur - 1].y; if (i == 0 && cur == n) return true; long long x1, x2; if (i == 0) { x1 = suffMinX[cur]; x2 = suffMaxX[cur]; } else if (cur == n) { x1 = prefMinX[i - 1]; x2 = prefMaxX[i - 1]; } else { x1 = min(suffMinX[cur], prefMinX[i - 1]); x2 = max(suffMaxX[cur], prefMaxX[i - 1]); } long long curD = getMaxD(y1, y2, x1, x2); if (curD <= d) return true; } it = n - 1; kek = -1; 42; for (int i = n - 1; i >= 0; i--) { if (i != n - 1 && p[i].y == p[i + 1].y) continue; while (it >= 0 && (it >= i || (sqr(p[it].y - p[i].y) <= d))) it--; while (kek<n - 1 & llabs(p[kek + 1].y)> llabs(p[i].y)) kek++; int cur = max(kek, it); 42; if (cur > i) break; long long y1 = p[i].y; long long y2 = p[cur + 1].y; if (i == n - 1 && cur == -1) return true; long long x1, x2; if (i == n - 1) { x1 = prefMinX[cur]; x2 = prefMaxX[cur]; } else if (cur == -1) { x1 = suffMinX[i + 1]; x2 = suffMaxX[i + 1]; } else { x1 = min(prefMinX[cur], suffMinX[i + 1]); x2 = max(prefMaxX[cur], suffMaxX[i + 1]); } long long curD = getMaxD(y1, y2, x1, x2); if (curD <= d) return true; } return false; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { p[i].scan(); } sort(p, p + n); precalc(); long long l = -1, r = (long long)1e18; while (r - l > 1) { long long mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } printf( %lld n , r); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; char buf[1 << 15], *fs, *ft; inline char getc() { return (ft == fs && (ft = (fs = buf) + fread(buf, 1, 1 << 15, stdin), ft == fs)) ? 0 : *fs++; } template <typename T> inline void read(T &x) { x = 0; T f = 1, ch = getchar(); while (!isdigit(ch) && ch ^ - ) ch = getchar(); if (ch == - ) f = -1, ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x *= f; } template <typename T> inline void write(T &x) { if (!x) { putchar( 0 ), putchar( n ); return; } if (x < 0) putchar( - ), x = -x; T num = 0, ch[16]; while (x) ch[++num] = x % 10 + 48, x /= 10; while (num) putchar(ch[num--]); putchar( n ); } int q[maxn], now; long long f[2][maxn], a[maxn], d[maxn], sum[maxn]; inline long long getUp(int j, int k) { return (f[now ^ 1][j] + sum[j]) - (f[now ^ 1][k] + sum[k]); } inline long long getDw(int j, int k) { return j - k; } int main() { int n, m, p; read(n); read(m); read(p); for (int i = 2; i <= n; ++i) read(d[i]), d[i] += d[i - 1]; for (int i = 1; i <= m; ++i) { int h; long long t; read(h); read(t); a[i] = t - d[h]; } sort(a + 1, a + m + 1); for (int i = 1; i <= m; ++i) sum[i] = sum[i - 1] + a[i], f[0][i] = 1e18; long long ans = 1e18; now = 1; for (int t = 1; t <= p; ++t) { int l = 1, r = 1; q[1] = 0; for (int i = 1; i <= m; ++i) { while (l < r && getUp(q[l + 1], q[l]) <= a[i] * getDw(q[l + 1], q[l])) ++l; f[now][i] = f[now ^ 1][q[l]] + (long long)a[i] * (i - q[l]) - (sum[i] - sum[q[l]]); while (l < r && getUp(i, q[r]) * getDw(q[r], q[r - 1]) <= getUp(q[r], q[r - 1]) * getDw(i, q[r])) --r; q[++r] = i; } ans = min(ans, f[now][m]); now ^= 1; } write(ans); return 0; } |
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_PIPELINE=5 LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=25 LPM_WIDTHN=64 aclr clken clock denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgp3p
(
aclr,
clken,
clock,
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [24:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [24:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [24:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_pipeline = 5,
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 25,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgp3p
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; vector<int> fibonacci; void createFibbo(int num); int main() { int num; cin >> num; if (num == 0) cout << 0 0 0 n ; else if (num == 1) cout << 0 0 1 n ; else if (num == 2) cout << 0 1 1 n ; else if (num == 3) cout << 1 1 1 n ; else createFibbo(num); return 0; } void createFibbo(int num) { int nvo = 0; int pos = 2; fibonacci.push_back(0); fibonacci.push_back(1); while (nvo != num) { nvo = fibonacci[pos - 1] + fibonacci[pos - 2]; fibonacci.push_back(nvo); pos++; } pos--; cout << fibonacci[pos - 4] << << fibonacci[pos - 3] << << fibonacci[pos - 1] << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 512345, lgN = 20, rootN = 1123; const double eps = 1e-11; vector<int> cities; int root = -1; int dp[N]; bool visited[N], rem[N]; vector<int> adj[N]; void dfsTree(int v) { int sum = 0; auto it = lower_bound(cities.begin(), cities.end(), v); if (it < cities.end() && *it == v) ++sum; for (int i = 0; i < adj[v].size(); ++i) { int u = adj[v][i]; if (visited[u]) continue; visited[u] = true; dfsTree(u); sum += dp[u]; } if (sum == 0) rem[v] = true; else if (sum == cities.size() && root == -1) root = v; else if (sum == cities.size()) rem[v] = true; dp[v] = sum; } pair<int, int> bfsDistance(int src) { memset(visited, false, sizeof visited); queue<pair<int, int> > q; q.push(make_pair(src, 0)); visited[src] = true; pair<int, int> ret = make_pair(src, 0); while (!q.empty()) { int v = q.front().first, dist = q.front().second; q.pop(); if (dist > ret.second || (dist == ret.second && v < ret.first)) ret = make_pair(v, dist); for (int i = 0; i < adj[v].size(); ++i) { int u = adj[v][i]; if (visited[u] || rem[u]) continue; visited[u] = true; q.push(make_pair(u, dist + 1)); } } return ret; } int main() { int n, c; scanf( %d %d , &n, &c); int u, v; for (int i = 1; i < n; ++i) { scanf( %d %d , &u, &v); adj[u].push_back(v), adj[v].push_back(u); } cities.resize(c); for (int i = 0; i < cities.size(); ++i) scanf( %d , &cities[i]); sort(cities.begin(), cities.end()); visited[1] = true; dfsTree(1); pair<int, int> x = bfsDistance(root); pair<int, int> y = bfsDistance(x.first); printf( %d n , min(x.first, y.first)); int ct = 0; for (int i = 1; i <= n; ++i) if (!rem[i]) ++ct; int ans = 2 * (ct - 1) - y.second; printf( %d n , ans); return 0; } |
// trick: сперва писать в тестбенче, а потом выделить модуль
//
// vlog *.v; vsim -t ns work.test_math; do waves.do
//
`timescale 10ns/1ps
//`default_nettype none
//=================== int ariphm 2001 ==============
// fixme: px to unsigned for calc? How?
// Verilog:
// http://www.uccs.edu/~gtumbush/published_papers/Tumbush%20DVCon%2005.pdf
// !!! http://amakersblog.blogspot.ru/2008/07/fixed-point-arithmetic-with-verilog.html
// fixme: похоже кодят в ручню, не надясь на Verilog
// Math:
// http://courses.cs.washington.edu/courses/cse467/08au/pdfs/lectures/11-FixedPointArithmetic.pdf
// http://www.superkits.net/whitepapers/Fixed%20Point%20Representation%20&%20Fractional%20Math.pdf
// https://groups.google.com/forum/#!topic/comp.lang.verilog/rRMKVkc8SjQ
// Other:
// http://stackoverflow.com/questions/28942318/16bit-fixed-point-arithmetic-multiplication
module fixed_convertof(
input [5:-7] in,
output signed [7:-7] out );
assign out = {2'b0, in} ;
endmodule
module add_signed_2001 (
input signed [2:0] A,
input signed [2:0] B,
output signed [3:0] Sum // size !!
);
assign Sum = A + B;
endmodule
module add_carry_signed_final(
input signed [2:0] A,
input signed [2:0] B,
input carry_in,
output signed [3:0] Sum // size !!
);
assign Sum = A + B + $signed({1'b0, carry_in});
endmodule
module mult_signed_2001 (
input signed [2:0] a,
input signed [2:0] b,
output signed [5:0] prod // size(a) + size(b) + 1
);
assign prod = a*b;
endmodule
// "However, recall the rule that if any operand of an operation
// is unsigned the entire operation is unsigned. "
module mult_signed_unsigned_2001 (
input signed [2:0] a,
input [2:0] b,
output signed [5:0] prod
);
assign prod = a*$signed({1'b0, b});
endmodule
// expr - "What is an expression? "
//Signed Shifting
//Signed Saturation
module math_tb;
// Tasks:
// fixme: average - comb -> pipelining -> real mem access
reg clk;
always #1 clk=~clk;
initial begin
clk = 0;
end
// Test bench only
real r1, r2;
real z_r;
`define F1 16
`define F2 14
reg [5:-`F1] x, y;
reg [8:-`F2] z;
// sum same size
reg [7:0] a, b, s, d; // for good sum not enouth
reg ovf; // !!!
reg unf; // !!!
// mult
reg [2:0] x1; // 3 bit
reg [2:0] y1;
reg [4 + 1/*3*/:0] p; // ovf / 6 bit
reg ovf_mul;
reg signed [ 7:0] x2;
reg signed [15:0] y2;
// sum
reg signed [11:0] v1, v2;
reg signed [12:0] sum;
reg signed [7:0] x3, y3, z3;
reg s_ovf;
// vec
reg signed [7:0] vec [7:0];
// Fixed-point
// http://my.ece.msstate.edu/faculty/reese/EE4743/lectures/fixed_point/fixed_point.pdf
// 1. For an unsigned saturating adder, 8 bit:
// 2. For a 2’s complement saturating adder, 8 bit:
//
// http://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/
integer i;
initial begin // _try_name
r1 = -9.6;
r2 = -8.78;
// r1 <= $itor(x)/2**16;
// r2 <= r1 / ($itor(y)/2**16);
z = $rtoi(r2 * 2**14);
z_r = $itor($signed(z))/2**`F2;
// Unsigned
// Overflow detection + Saturation
a = 250;
b = 50;
// unsigned => to 9 zero extended
{ovf, s} = a + b;
if (ovf == 1'b1)
s = 8'hff;
// substr with underflow
{unf, d} = b - a;
if (unf == 1'b1)
d = 0;
// compare unsigned
// just > , <
// scaling by pow2
// mult
x1 = 3'h7;
y1 = 3'h7;
{ovf_mul, p} = x1 * y1; // overflow? if size >= size(a) + size(b) no ovf
// Signed
// resize
x2 = -7;
y2 = {{8{x2[7]}}, x2}; // { n {...}} specifies n replications
// negating
// sum
sum = {v1[11], v1} + {v2[11], v2}; // without detection
//sum = v1 + v2; // or
x3 = 124;
y3 = 10;
z3 = x3 + y3;
s_ovf = ~x3[7] & ~y3[7] & z3[7] | x3[7] & y3[7] & ~z3[7]; // ovf | unf(?)
// saturation
$display("z3 = %0d", z3);
$display("s_ovf = %0d", s_ovf);
// mult
// ???
// Mix Unsigned and Signed
//???
// Vector ops(?)
for (i = 0; i < 10; i = i + 1) begin
vec[i] = i;
// $display("data_8bit = %0d", -i);
end
end
// - Line interpol
// https://code.zmaw.de/boards/1/topics/27
// http://math.stackexchange.com/questions/828392/spatial-interpolation-for-irregular-grid
// Attention!!!
// Opencv remap calc dst -> src
// fixme: не понял что имелось ввиду
// http://www.cs.tut.fi/~dkuva2/Lecture7_SamplingAndInterpolation_v3.pdf
// Triangulation
// http://stackoverflow.com/questions/17478551/2d-interpolation-irregular-grid-fortran
//
// https://classes.soe.ucsc.edu/cmps160/Fall10/resources/barycentricInterpolation.pdf
// Barycentric interpolation
// https://dahtah.wordpress.com/2013/03/06/barycentric-interpolation-fast-interpolation-on-arbitrary-grids/
//
// - Bilinear - 2D
// https://en.wikipedia.org/wiki/Bilinear_interpolation
// fixme: if not quad
// !!!
// Non-regular grid - scattered data
// fixme: Bilinear not working - strange...
// Works say: http://stackoverflow.com/questions/23920976/bilinear-interpolation-with-non-aligned-input-points
// Trouble0: sqrt, div - но можно предвычислить
// More info
// !!! http://graphics.stanford.edu/courses/cs148-09/lectures/interpolation.pdf
// Trouble0: div, но можно предвычислить
// 0:50
reg [7:-3] div_1d [15:0];
initial begin
$readmemh("src.mif", div_1d);
for (i = 0; i < 10; i = i + 1) begin
$display("div_1d = %0d", div_1d[i]);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; const int N = 3030; const int INF = (int)2e9; int n, m; int len[N]; int f[N][N]; vector<int> g[N]; vector<int> gr[N]; vector<pair<int, int> > have[N]; vector<pair<int, int> > gave[N]; queue<int> q; void bfs(int v) { for (int i = 1; i <= n; i++) len[i] = INF; len[v] = 0; q.push(v); while (!q.empty()) { int ver = q.front(); q.pop(); for (int i = 0; i < (int)g[ver].size(); i++) { int to = g[ver][i]; if (len[to] > len[ver] + 1) { len[to] = len[ver] + 1; q.push(to); } } } for (int i = 1; i <= n; i++) { f[v][i] = len[i]; if (len[i] != INF && i != v) { gave[i].push_back(make_pair(len[i], v)); } } for (int i = 1; i <= n; i++) len[i] = INF; len[v] = 0; q.push(v); while (!q.empty()) { int ver = q.front(); q.pop(); for (int i = 0; i < (int)gr[ver].size(); i++) { int to = gr[ver][i]; if (len[to] > len[ver] + 1) { len[to] = len[ver] + 1; q.push(to); } } } for (int i = 1; i <= n; i++) { if (len[i] != INF && i != v) { have[i].push_back(make_pair(len[i], v)); } } } int main() { scanf( %d%d , &n, &m); int u, v; for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); g[u].push_back(v); gr[v].push_back(u); } for (int i = 1; i <= n; i++) { bfs(i); } for (int i = 1; i <= n; i++) { sort(have[i].begin(), have[i].end()); reverse(have[i].begin(), have[i].end()); sort(gave[i].begin(), gave[i].end()); reverse(gave[i].begin(), gave[i].end()); } int res = 0; int a, b, c, d, sz, ptr, cost; for (int i = 1; i <= n; i++) { sz = min(3, (int)gave[i].size()); for (int idx = 0; idx < sz; idx++) { for (int j = 1; j <= n; j++) { if (j == i) continue; if (f[i][j] == INF) continue; ptr = 0; while (true) { if (ptr >= (int)have[j].size()) break; if (have[j][ptr].second == i || have[j][ptr].second == gave[i][idx].second || j == gave[i][idx].second) { ++ptr; continue; } else { cost = gave[i][idx].first + f[i][j] + have[j][ptr].first; if (cost > res) { res = cost; a = gave[i][idx].second; b = i; c = j; d = have[j][ptr].second; } break; } } } } } printf( %d %d %d %d n , a, b, c, d); return 0; } |
#include<bits/stdc++.h> using namespace std; const int N=17; int n,p[1<<N];bool used[1<<N]; struct Edge{int nxt,to;}e[N*(1<<N)];int fir[1<<N]; void add(int u,int v,int i){e[i]=(Edge){fir[u],v},fir[u]=i;} int col[1<<N]; void solve(){ cin>>n; for(int i=0;i<(1<<n);++i){ used[i]=0,p[i]=fir[i]=col[i]=0; } for(int i=1;i<=n*(1<<(n-1));++i){ int u,v;scanf( %d%d ,&u,&v); add(u,v,i<<1),add(v,u,i<<1|1); } p[0]=0,used[0]=true; for(int i=fir[0],j=0;i;i=e[i].nxt,j++){ p[1<<j]=e[i].to,used[e[i].to]=true; } for(int i=1;i<(1<<n);++i){ if(p[i]) continue; vector<int> bag; set<int> fuck1,fuck2; for(int j=0;j<n;++j){ if(i&(1<<j)) bag.push_back(p[i^(1<<j)]); } for(int j=0;j<(int)bag.size();++j){ if(!j){ for(int c=fir[bag[j]];c;c=e[c].nxt) if(!used[e[c].to]) fuck2.insert(e[c].to); } else{ fuck1=fuck2,fuck2.clear(); for(int c=fir[bag[j]];c;c=e[c].nxt){ if(fuck1.find(e[c].to)==fuck1.end()) continue; fuck2.insert(e[c].to); } } } p[i]=*fuck2.begin(),used[*fuck2.begin()]=true; } for(int i=0;i<(1<<n);++i) printf( %d ,p[i]); printf( n ); if(n-(n&(-n))) return printf( -1 n ),void(); for(int i=0;i<(1<<n);++i){ int tmp=i; for(int j=0;j<n;++j) col[p[i]]^=j*(tmp&1),tmp>>=1; } for(int i=0;i<(1<<n);++i) printf( %d ,col[i]); return printf( n ),void(); } int main(){ int T;cin>>T; while(T--) solve(); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
reg [31:0] v32 [2];
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\n", $time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 >>>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
w32 = 12; w32 %= 5; if (w32 != 2) $stop;
// Increments
v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop;
v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop;
v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop;
v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop;
v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop;
v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop;
v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop;
v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop;
v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop;
v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop;
v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> #define mid (tl+tr)/2 #define mod 1000000007 #define fain(arr) for(ll i=0;i<n;i++)cin>>arr[i]; #define all(x) x.begin(),x.end() #define SPEED ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); #define bugv(n1) if(DEBUG)cout<<#n1<< is <<n1<< n ; #define buga(A) cout<<#A<< is : <<endl ; for(auto x:A)cout<<x<< ; cout<<endl; #define FILE freopen( input.txt , r ,stdin); #define rep(i, begin, end) for (__typeof(end) i = (begin) - ((begin) > (end)); i != (end) - ((begin) > (end)); i += 1 - 2 * ((begin) > (end))) #define endl n #define ll long long #define pii pair<ll,ll> #define pll pair<long long ,long long > #define pi acos(-1) #define sz(x) ((ll)x.size()) #define clr(x) memset(x, 0, sizeof(x)) #define init(x, a) memset(x, a, sizeof(x)) #define DEBUG true using namespace std; int main(){ // FILE; SPEED; ll t; cin>>t; while(t--){ int n,m; cin>>n>>m; char arr[n][m]; for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ cin>>arr[i][j]; } } int left[n][m]; int right[n][m]; int up[n][m]; for(int i=0;i<n;i++){ for(int j=m-1;j>=0;j--){ if(j==m-1){ right[i][j]=arr[i][j]== * ?1:0; } else{ if(arr[i][j]== * ) right[i][j]=right[i][j+1]+1; else right[i][j]=0; } } } for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ if(j==0){ left[i][j]=arr[i][j]== * ?1:0; } else{ if(arr[i][j]== * ) left[i][j]=left[i][j-1]+1; else left[i][j]=0; } } } int ans=0; for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ if(i==0){ up[i][j]=arr[i][j]== * ?1:0; } else{ up[i][j]=min({left[i][j],right[i][j],1+up[i-1][j]}); } ans+=up[i][j]; } } cout<<ans<<endl; } } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 100000 + 5; const long long inf = 9e17; long long ans = inf, l, r, mid1, mid2; vector<long long> g[maxn], v; long long n, m; inline long long cost(long long mid) { long long cnt = mid - g[0].size(), tmp = 0; v.clear(); for (int i = 1; i <= m; i++) { for (int j = 0; j < g[i].size(); j++) { if (g[i].size() - j >= mid) { --cnt; tmp += g[i][j]; } else v.push_back(g[i][j]); } } sort(v.begin(), v.end()); for (int i = 0; i < cnt; i++) tmp += v[i]; return tmp; } int main() { long long a, b; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; m = max(m, a); g[a].push_back(b); } for (int i = 0; i <= m; i++) sort(g[i].begin(), g[i].end()); l = g[0].size(), r = n; while (l < r) { mid1 = (l + l + r) / 3; mid2 = (l + r + r) / 3; if (cost(mid1) > cost(mid2)) { if (l == mid1) break; else l = mid1; } else { if (r == mid2) break; else r = mid2; } } ans = inf; for (int i = l; i <= r; i++) ans = min(ans, cost(i)); cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_2_V
`define SKY130_FD_SC_MS__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_2_V
|
//==================================================================================================
// Filename : submidRecursiveKOA.v
// Created On : 2016-10-27 23:28:55
// Last Modified : 2016-10-28 08:59:19
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module submidRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] Data_S_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [SW-1:0] Q_left_reg;
reg [SW-1:0] Q_right_reg;
reg [SW+1:0] Q_middle_reg;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @(posedge clk) begin : SEGMENTATION
Q_left_reg = Q_left;
Q_right_reg= Q_right;
Q_middle_reg = Q_middle;
end
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle_reg - Q_left_reg - Q_right_reg);
Data_S_o <= {leftside1,S_B,rightside1} + {Q_left_reg,Q_right_reg};
end
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2)-1:0] Q_left_reg;
reg [2*(SW/2+1)-1:0] Q_right_reg;
reg [2*(SW/2+2)-1:0] Q_middle_reg;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW(SW/2+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @(posedge clk) begin : SEGMENTATION1
Q_left_reg = Q_left;
Q_right_reg = Q_right;
Q_middle_reg = Q_middle;
end
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle_reg - Q_left_reg - Q_right_reg);
Data_S_o <= {leftside2,S_B,rightside2} + {Q_left_reg,Q_right_reg};
end
end
endcase
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_comp_gen_fx
(
input clk,
input rstn,
input [23:0] dx_fx, // 16.8
input [23:0] dy_fx, // 16.8
input [95:0] cmp_i,
output reg signed [31:0] curr_i
);
wire [31:0] sp_fx;
wire [31:0] idx_fx;
wire [31:0] idy_fx;
reg [63:0] ix;
reg [63:0] iy;
reg [25:0] ixy;
flt_fx u0_flt_fx(cmp_i[95:64], sp_fx); // flt -> 16.16.
flt_fx u1_flt_fx(cmp_i[63:32], idx_fx); // flt -> 16.16.
flt_fx u2_flt_fx(cmp_i[31:0], idy_fx); // flt -> 16.16.
always @(posedge clk) begin
ix <= {dx_fx, 8'h0} * idx_fx; // 16.16 * 16.16 = 32.32
iy <= {dy_fx, 8'h0} * idy_fx; // 16.16 * 16.16 = 32.16
ixy <= iy[31:8] + ix[31:8]; // 16.8 + 16.8 = 17.8
curr_i <= ixy[24:0] + sp_fx[31:8]; // 16.8 * 16.8 = 32.16
end
wire [47:0] ix_test = ~ix + 1;
wire [47:0] iy_test = ~iy + 1;
wire [47:0] ixy_test = ~ixy + 1;
wire [47:0] curr_i_test = ~curr_i + 1;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: progmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module progmem (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./mem/progmem.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./mem/progmem.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./mem/progmem.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL progmem_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { string x; cin >> x; int i, j; int len = x.size(); int count = 0; for (i = 0; i < len; i++) { for (j = 1; j <= len - i; j++) { string z = x.substr(i, j); if (z == Danil || z == Olya || z == Slava || z == Ann || z == Nikita ) count++; } } if (count == 1) cout << Yes ; else cout << No ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_1_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_1_V
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 2005; int n; int p[Maxn], b[Maxn]; int inb[Maxn]; int res; int best[Maxn]; vector<pair<int, int> > seq; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); inb[b[i]] = i; } for (int i = 1; i <= n; i++) p[i] = inb[p[i]]; for (int i = 1; i <= n; i++) { int pos = i; while (p[pos] != i) pos++; res += pos - i; best[i] = p[i]; for (int j = i + 1; j < pos; j++) best[j] = max(best[j - 1], p[j]); for (int j = pos - 1; j >= i; j--) if (best[j] == p[j]) { seq.push_back(pair<int, int>(j, pos)); swap(p[j], p[pos]); pos = j; } } printf( %d n , res); printf( %d n , seq.size()); for (int i = 0; i < seq.size(); i++) printf( %d %d n , seq[i].first, seq[i].second); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module DSP48E1 (
ACOUT,
BCOUT,
CARRYCASCOUT,
CARRYOUT,
MULTSIGNOUT,
OVERFLOW,
P,
PATTERNBDETECT,
PATTERNDETECT,
PCOUT,
UNDERFLOW,
A,
ACIN,
ALUMODE,
B,
BCIN,
C,
CARRYCASCIN,
CARRYIN,
CARRYINSEL,
CEA1,
CEA2,
CEAD,
CEALUMODE,
CEB1,
CEB2,
CEC,
CECARRYIN,
CECTRL,
CED,
CEINMODE,
CEM,
CEP,
CLK,
D,
INMODE,
MULTSIGNIN,
OPMODE,
PCIN,
RSTA,
RSTALLCARRYIN,
RSTALUMODE,
RSTB,
RSTC,
RSTCTRL,
RSTD,
RSTINMODE,
RSTM,
RSTP);
parameter ACASCREG = 1;
parameter ADREG = 1;
parameter ALUMODEREG = 1;
parameter AREG = 1;
parameter AUTORESET_PATDET = "NO_RESET";
parameter A_INPUT = "DIRECT";
parameter BCASCREG = 1;
parameter BREG = 1;
parameter B_INPUT = "DIRECT";
parameter CARRYINREG = 1;
parameter CARRYINSELREG = 1;
parameter CREG = 1;
parameter DREG = 1;
parameter INMODEREG = 1;
parameter MASK = 'h3fffffffffff;
parameter MREG = 1;
parameter OPMODEREG = 1;
parameter PATTERN = 0;
parameter PREG = 1;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter USE_DPORT = 0;
parameter USE_MULT = "MULTIPLY";
parameter USE_PATTERN_DETECT = "NO_PATDET";
parameter USE_SIMD = "ONE48";
output [29:0] ACOUT;
output [17:0] BCOUT;
output CARRYCASCOUT;
output [ 3:0] CARRYOUT;
output MULTSIGNOUT;
output OVERFLOW;
output [47:0] P;
output PATTERNBDETECT;
output PATTERNDETECT;
output [47:0] PCOUT;
output UNDERFLOW;
input [29:0] A;
input [29:0] ACIN;
input [ 3:0] ALUMODE;
input [17:0] B;
input [17:0] BCIN;
input [47:0] C;
input CARRYCASCIN;
input CARRYIN;
input [ 2:0] CARRYINSEL;
input CEA1;
input CEA2;
input CEAD;
input CEALUMODE;
input CEB1;
input CEB2;
input CEC;
input CECARRYIN;
input CECTRL;
input CED;
input CEINMODE;
input CEM;
input CEP;
input CLK;
input [24:0] D;
input [ 4:0] INMODE;
input MULTSIGNIN;
input [ 6:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTALLCARRYIN;
input RSTALUMODE;
input RSTB;
input RSTC;
input RSTCTRL;
input RSTD;
input RSTINMODE;
input RSTM;
input RSTP;
assign ACOUT = 30'd0;
assign BCOUT = 18'd0;
assign CARRYCASCOUT = 1'd0;
assign CARRYOUT = 4'd0;
assign MULTSIGNOUT = 1'd0;
assign OVERFLOW = 1'd0;
assign P = 48'd0;
assign PATTERNBDETECT = 1'd0;
assign PATTERNDETECT = 1'd0;
assign PCOUT = 48'd0;
assign UNDERFLOW = 1'd0;
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void solve(){ int n; scanf( %d , &n); if (n == 2){ printf( 1 n2 1 n1 n2 1 n ); } else if (n == 3){ printf( 5 n2 3 1 n2 n1 3 n2 3 n ); } else { long long t = 0; vector<int> ans; vector<pair<int, int>> vc; ans.push_back(n / 2 + 1); for (int i = 3; i <= n / 2; ++i) ans.push_back(i); ans.push_back(1); for (int i = n / 2 + 2; i <= n; ++i) ans.push_back(i); ans.push_back(2); for (int i = 2; i <= n / 2; ++i){ vc.push_back({i, n}); t += (long long)(n - i) * (n - i); } for (int i = n / 2 + 1; i <= n; ++i){ vc.push_back({i, 1}); t += (long long)(i - 1) * (i - 1); } printf( %lld n , t); for (int it : ans) printf( %d , it); printf( n ); printf( %d n , n - 1); for (auto it : vc){ printf( %d %d n , it.first, it.second); } } } int main(){ int T; scanf( %d , &T); while (T--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 7; const int inf = 0x3f3f3f3f; int a[maxn]; char s[150]; int main() { int t; cin >> t; while (t--) { int n; cin >> n; scanf( %s , s); int x = 0, y = 0; for (int i = 0; i < n; i++) { if (s[i] == < ) x++; else break; } for (int i = n - 1; i >= 0; i--) { if (s[i] == > ) y++; else break; } cout << min(x, y) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, t, c, sum = 0; cin >> t; long long int a[t]; for (i = 0; i < t; i++) { cin >> a[i]; } for (i = 0; i < t; i++) { sum += a[i]; } if (sum % 2 == 0) { cout << sum << endl; } else { long long int min = 1000000001; for (i = 0; i < t; i++) { if (a[i] <= min && a[i] % 2 != 0) { min = a[i]; } } sum = sum - min; cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool not_prime[100000]; long long int primes[100000]; int p, prime_factors[100000], pf_count[100000], q; int a[10000]; void find_primes() { long long int i, j; p = 0; for (i = 2; i < 100000; i++) { if (not_prime[i] == false) { primes[p++] = i; for (j = 2; i * j < 100000; j++) { not_prime[i * j] = false; } } } } void factor(long long int n) { q = 0; for (int i = 0; i < p; i++) { int count = 0; while (n % primes[i] == 0) { count++; n /= primes[i]; } if (count > 0) { prime_factors[q] = i; pf_count[q++] = count; } } if (n > 1) { primes[p++] = n; prime_factors[q] = p - 1; pf_count[q++] = 1; } } int rec(int d, long long int b) { int ret = 0; if (d == q) { long long int x = 1; for (int i = 0; i < q; i++) { for (int j = 0; j < a[i]; j++) x *= primes[prime_factors[i]]; } if (x <= b) return 0; else return 1; } for (int j = pf_count[d]; j >= 0; j--) { a[d] = j; int tmp = rec(d + 1, b); if (tmp == 0) break; ret += tmp; } return ret; } int main() { long long int a, b, n; int ans = 0; cin >> a >> b; n = a - b; if (a == b) { cout << infinity << endl; } else if (a < b) { cout << 0 << endl; } else { find_primes(); factor(n); cout << rec(0, b) << endl; } } |
#include <bits/stdc++.h> using namespace std; int n, a[111111]; int isp2[222222]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int i = 1, p = 1; i < 222222; i *= 2, ++p) { isp2[i] = p; } sort(a, a + n); int ans = 1e9; for (int dv = 0; a[n - 1] >= (1 << dv); ++dv) { for (int mul = 0; mul <= dv + 1; ++mul) { int val = a[n - 1]; for (int i = 0; i < dv; ++i) { val /= 2; } for (int i = 0; i < mul; ++i) { val *= 2; } int tot = 0; for (int i = 0; i < n; ++i) { int cur = a[i]; while (cur > 0 && !(val % cur == 0 && isp2[val / cur])) { cur /= 2; ++tot; } if (cur > 0) { tot += isp2[val / cur] - 1; } else { tot = 1e9; break; } } ans = min(ans, tot); } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, s = 2, ans = 0, i; cin >> n; if (n < 2) { cout << 0; return 0; } for (i = 1; i <= 1e6; ++i) { if (s > n) break; if ((n - s) % 3 == 0) ++ans; s += 3 * i + 2; } cout << ans; } |
module tester(
clk,
rst
);
parameter end_simulation = 32'hffff;
output clk,rst;
reg clk, rst;
integer clk_count;
integer tests_done;
integer tests_failed;
initial begin
forever begin
#10 clk <= ~clk;
if(clk) clk_count = clk_count + 1;
if(clk_count == end_simulation) begin
$display("not ok - Simulation took too long");
tests_failed = tests_failed+1;
print_report();
$finish;
end
end
end
initial begin
clk = 0;
rst = 0;
clk_count = 0;
tests_done = 0;
tests_failed = 0;
end
task reset_module;
begin
wait_clock();
rst = 1;
wait_clock();
wait_clock();
rst = 0;
end
endtask
task wait_clock;
begin
@( negedge clk );
end
endtask
task check_boolean;
input test_result;
input[0:400] description;
reg test_result;
reg [0:400] description;
begin
tests_done = tests_done + 1;
if(test_result) $display("ok - %s",description);
else begin
$display("not ok - %s",description);
tests_failed = tests_failed + 1;
end
end
endtask
task check_value;
parameter VALUE_WIDTH = 32;
input[VALUE_WIDTH-1:0] value,corr_value;
input[0:400] description;
reg[VALUE_WIDTH-1:0] value,corr_value;
reg[0:400] description;
begin
tests_done = tests_done + 1;
if(value === corr_value) $display("ok - %s",description);
else begin
$display("not ok - %s # found %h, expected %h",description,value,corr_value);
tests_failed = tests_failed + 1;
end
end
endtask
task print_report;
begin
if(tests_failed == 0) $display("\n#################\n# All tests passed!\n");
else $display("\n#################\n# Failed %0d/%0d tests\n",tests_failed,tests_done );
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
/**
* iso0n: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
|
#include <bits/stdc++.h> int Cmp(const void *a, const void *b); int main(void) { int i, n, x, w, gpos = -2 * 1000000000, ans = 0, grange[200000][2]; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d , &x, &w); grange[i][0] = x - w; grange[i][1] = x + w; } qsort(grange, n, sizeof(int) * 2, Cmp); for (i = 0; i < n; i++) { if (gpos <= grange[i][0]) { ans++; gpos = grange[i][1]; } } printf( %d n , ans); } int Cmp(const void *a, const void *b) { int ta = *(*(int(*)[2])a + 1), tb = *(*(int(*)[2])b + 1); if (ta > tb) return 1; else if (tb > ta) return -1; return 0; } |
#include <bits/stdc++.h> using namespace std; int N, ans = 0, overtake = 0, pspeed, plimit = 1000; stack<int> signs; int main() { cin >> N; for (int i = 0, a, b; i < N; i++) { cin >> a; if (a == 1) { cin >> b; pspeed = b; while (!signs.empty()) { if (signs.top() < b) { ans++; signs.pop(); } else { break; } } } else if (a == 2) { if (overtake > 0) { ans += overtake; overtake = 0; } } else if (a == 3) { cin >> b; signs.push(b); while (!signs.empty()) { if (signs.top() < pspeed) { ans++; signs.pop(); } else { break; } } } else if (a == 4) { overtake = 0; } else if (a == 5) { while (!signs.empty()) signs.pop(); } else { overtake++; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; inline void io() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } long long I() { long long a; cin >> a; return a; } void PV(vector<long long> v) { for (long long i = 0; i < (long long)v.size(); i++) cout << v[i] << ; cout << n ; } void PA(long long v[], long long n, long long x = 0) { for (long long i = x; i < n + x; i++) cout << v[i] << ; cout << n ; } void IA(long long a[], long long n, long long x = 0) { for (long long i = x; i < n + x; i++) cin >> a[i]; } const long long N = (2e5) + 7, N1 = 1e9 + 7, MOD = 1e9 + 7, INF = (1e17 + 7); long long fact[N]; long long power(long long a, long long b) { long long k = 1; for (; b; b /= 2, a = a * a % MOD) if (b % 2 == 1) k = k * a % MOD; return k % MOD; } void pre() { fact[0] = 1; for (long long i = 1; i < N; i++) fact[i] = (fact[i - 1] * i) % N1; } void solve() { long long n; cin >> n; long long ans = fact[2 * n] * (power(2, N1 - 2)); ans %= MOD; cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t1 = 1, x0 = 1; pre(); cin >> t1; while (t1--) { solve(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n, m, s, t, ds, dt, cnt, f; vector<pair<int, int>> ans; vector<int> G[N]; pair<int, int> xx[N], yy[N]; bool vi[N]; void dfs(int u) { vi[u] = true; for (int v : G[u]) if (!vi[v]) { ans.push_back({u, v}); dfs(v); } else if (v == s) xx[cnt] = {u, v}; else if (v == t) yy[cnt] = {u, v}; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; G[x].push_back(y); G[y].push_back(x); } cin >> s >> t >> ds >> dt; vi[s] = true; vi[t] = true; for (int i = 1; i <= n; i++) if (!vi[i]) { dfs(i); cnt++; } for (int i = 0; i < cnt; i++) if (xx[i] == make_pair(0, 0) && yy[i] == make_pair(0, 0)) { cout << No << endl; return 0; } else if (xx[i] == make_pair(0, 0)) { dt--; ans.push_back(yy[i]); f |= 2; } else if (yy[i] == make_pair(0, 0)) { ds--; ans.push_back(xx[i]); f |= 1; } if (ds <= 0 || dt <= 0) { cout << No << endl; return 0; } for (int i = 0; i < cnt; i++) if (xx[i] > make_pair(0, 0) && yy[i] > make_pair(0, 0)) { ds--; dt--; ans.push_back(xx[i]); ans.push_back(yy[i]); f = 3; yy[i] = {0, 0}; xx[i] = {0, 0}; break; } for (int i = 0; i < cnt; i++) if (xx[i] > make_pair(0, 0) && yy[i] > make_pair(0, 0) && ds > 0) { ds--; ans.push_back(xx[i]); f |= 1; yy[i] = {0, 0}; } for (int i = 0; i < cnt; i++) if (xx[i] > make_pair(0, 0) && yy[i] > make_pair(0, 0) && dt > 0) { dt--; ans.push_back(yy[i]); f |= 2; xx[i] = {0, 0}; } for (int i = 0; i < cnt; i++) if (xx[i] > make_pair(0, 0) && yy[i] > make_pair(0, 0)) { cout << No << endl; return 0; } if (ans.size() < n - 1) { ans.push_back({s, t}); ds--; dt--; } if (ds < 0 || dt < 0) cout << No << endl; else { cout << Yes << endl; for (auto z : ans) cout << z.first << << z.second << endl; } return 0; } |
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
//-----------------------------------------------------------------
// Module - Xilinx register file (async read)
//-----------------------------------------------------------------
module altor32_regfile_xil
(
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [4:0] ra_i /*verilator public*/,
input [4:0] rb_i /*verilator public*/,
input [4:0] rd_i /*verilator public*/,
output reg [31:0] reg_ra_o /*verilator public*/,
output reg [31:0] reg_rb_o /*verilator public*/,
input [31:0] reg_rd_i /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter SUPPORT_32REGS = "ENABLED";
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] reg_ra_w;
wire [31:0] reg_rb_w;
wire [31:0] ra_0_15_w;
wire [31:0] ra_16_31_w;
wire [31:0] rb_0_15_w;
wire [31:0] rb_16_31_w;
wire write_enable_w;
wire write_banka_w;
wire write_bankb_w;
//-----------------------------------------------------------------
// Register File (using RAM16X1D )
//-----------------------------------------------------------------
// Registers 0 - 15
generate
begin
genvar i;
for (i=0;i<32;i=i+1)
begin : reg_loop1
RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_0_15_w[i]), .SPO(/* open */));
RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_0_15_w[i]), .SPO(/* open */));
end
end
endgenerate
// Registers 16 - 31
generate
if (SUPPORT_32REGS == "ENABLED")
begin
genvar i;
for (i=0;i<32;i=i+1)
begin : reg_loop2
RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_16_31_w[i]), .SPO(/* open */));
RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_16_31_w[i]), .SPO(/* open */));
end
end
else
begin
assign ra_16_31_w = 32'h00000000;
assign rb_16_31_w = 32'h00000000;
end
endgenerate
//-----------------------------------------------------------------
// Combinatorial Assignments
//-----------------------------------------------------------------
assign reg_ra_w = (ra_i[4] == 1'b0) ? ra_0_15_w : ra_16_31_w;
assign reg_rb_w = (rb_i[4] == 1'b0) ? rb_0_15_w : rb_16_31_w;
assign write_enable_w = (rd_i != 5'b00000) & wr_i;
assign write_banka_w = (write_enable_w & (~rd_i[4]));
assign write_bankb_w = (write_enable_w & rd_i[4]);
// Register read ports
always @ *
begin
if (ra_i == 5'b00000)
reg_ra_o = 32'h00000000;
else
reg_ra_o = reg_ra_w;
if (rb_i == 5'b00000)
reg_rb_o = 32'h00000000;
else
reg_rb_o = reg_rb_w;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000, INDEX = 1; int n, type[MAX_N + INDEX]; string team[MAX_N + INDEX], city[MAX_N + INDEX]; bool isUsed[MAX_N + INDEX]; void get(int ind) { isUsed[ind] = true; for (int i = 1; i <= n; i++) { if (i != ind) { if (team[i][0] == team[ind][0] && team[i][1] == team[ind][1] && team[i][2] == city[ind][0]) { type[i] = 1; if (!isUsed[i]) { get(i); } } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); cin >> n; for (int i = 1; i <= n; i++) { cin >> team[i] >> city[i]; } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (team[i][0] == team[j][0] && team[i][1] == team[j][1] && team[i][2] == team[j][2]) { type[i] = 1, type[j] = 1; } } } for (int i = 1; i <= n; i++) { if (type[i] == 1 && !isUsed[i]) { get(i); } } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (team[i][0] == team[j][0] && team[i][1] == team[j][1]) { if (team[i][2] == team[j][2] && type[i] == 0 && type[j] == 0) { cout << NO << endl; return 0; } if (team[i][2] == city[j][0] && type[i] == 0 && type[j] == 1) { cout << NO << endl; return 0; } if (city[i][0] == team[j][2] && type[i] == 1 && type[j] == 0) { cout << NO << endl; return 0; } if (city[i][0] == city[j][0] && type[i] == 1 && type[j] == 1) { cout << NO << endl; return 0; } } } } cout << YES << endl; for (int i = 1; i <= n; i++) { if (type[i] == 0) { cout << team[i][0] << team[i][1] << team[i][2] << n ; } if (type[i] == 1) { cout << team[i][0] << team[i][1] << city[i][0] << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct comp { bool operator()(long long int a, long long int b) { return a > b; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, k; cin >> n >> k; vector<pair<long long int, long long int> > pow(n); vector<long long int> mon(n); vector<long long int> res(n); priority_queue<long long int, vector<long long int>, comp> least; for (int(i) = (0); (i) < (n); (i)++) { long long int power; cin >> power; pow[i] = make_pair(power, i); } sort(pow.begin(), pow.end()); for (int(i) = (0); (i) < (n); (i)++) { cin >> mon[i]; } if (k == 0) { for (int(i) = (0); (i) < (n); (i)++) { if (i) cout << << mon[i]; else cout << mon[i]; } return 0; } least.push(mon[pow[0].second]); res[pow[0].second] = mon[pow[0].second]; for (int(i) = (1); (i) < (min(n, k + 1)); (i)++) { res[pow[i].second] = res[pow[i - 1].second] + mon[pow[i].second]; least.push(mon[pow[i].second]); } for (int(i) = (k + 1); (i) < (n); (i)++) { long long int toremove = least.top(); least.pop(); res[pow[i].second] = res[pow[i - 1].second] + mon[pow[i].second] - toremove; least.push(mon[pow[i].second]); } for (int(i) = (0); (i) < (n); (i)++) { if (i) cout << << res[i]; else cout << res[i]; } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; struct circle { double x, y, r; circle() {} circle(double x, double y, double r = 0) : x(x), y(y), r(r) {} circle operator+(circle b) { return circle(x + b.x, y + b.y); } circle operator-(circle b) { return circle(x - b.x, y - b.y); } circle operator*(double d) { return circle(x * d, y * d); } double squareLength() { return ((x) * (x)) + ((y) * (y)); } double length() { return sqrt(squareLength()); } void normalize() { double d = length(); x /= d; y /= d; } }; circle dot(circle a, circle b) { return circle(a.x * b.y, a.y * b.x); } circle a, b, c; double get_angle(circle a, circle b) { return asin(a.r / (a - b).length()); } bool check(circle p) { return fabs(get_angle(a, p) - get_angle(b, p)) < 1e-8 && fabs(get_angle(b, p) - get_angle(c, p)) < 1e-8 && fabs(get_angle(c, p) - get_angle(a, p)) < 1e-8; } circle get_circle(circle a, circle b) { double br = ((b.r) * (b.r)); double ar = ((a.r) * (a.r)); double A = br - ar; double x = (br * a.x - ar * b.x) / A; double y = (br * a.y - ar * b.y) / A; double aa = ((a.y - y) * (a.y - y)); double bb = ((b.y - y) * (b.y - y)); double B = -2 * (br * a.x - ar * b.x); double C = br * (aa + ((a.x) * (a.x))) - ar * (bb + ((b.x) * (b.x))); double D = sqrt(((B) * (B)) - 4 * A * C); return circle(x, y, fabs(D / (2 * A))); } int main() { cin >> a.x >> a.y >> a.r; cin >> b.x >> b.y >> b.r; cin >> c.x >> c.y >> c.r; if (a.r == b.r && b.r == c.r) { if (fabs(c.y - b.y) < 1e-10) swap(a, b); double y = ((((c.x) * (c.x)) - ((a.x) * (a.x)) + ((c.y) * (c.y)) - ((a.y) * (a.y))) * (b.x - a.x) - (((b.x) * (b.x)) - ((a.x) * (a.x)) + ((b.y) * (b.y)) - ((a.y) * (a.y))) * (c.x - a.x)) / (2 * ((c.y - a.y) * (b.x - a.x) - (b.y - a.y) * (c.x - a.x))); double x = (((b.x) * (b.x)) - ((a.x) * (a.x)) + ((b.y) * (b.y)) - ((a.y) * (a.y)) - 2 * y * (b.y - a.y)) / (2 * (b.x - a.x)); if (check(circle(x, y))) cout << setprecision(5) << fixed << x << << y; return 0; } if (fabs(a.r - b.r) < 1e-10) swap(a, c); if (fabs(a.r - c.r) < 1e-10) swap(a, b); circle p1 = get_circle(a, b); circle p2 = get_circle(a, c); double length = (p2 - p1).length(); if (length < p1.r + p2.r + 1e-8) if (p1.r < p2.r + length + 1e-8 && p2.r < p1.r + length + 1e-8 && length < p1.r + p2.r + 1e-8) { double x = (((p2.r) * (p2.r)) - ((p1.r) * (p1.r)) - ((length) * (length))) / (-2 * length); double h = sqrt(((p1.r) * (p1.r)) - ((x) * (x))); circle vec = (p2 - p1); vec.normalize(); vec = vec * x; circle point = p1 + vec; vec = dot(circle(-1, 1), vec); vec.normalize(); vec = vec * h; circle x1 = point + vec; circle x2 = point - vec; cout << setprecision(5) << fixed; if (check(x1) && !check(x2)) cout << x1.x << << x1.y; else if (!check(x1) && check(x2)) cout << x2.x << << x2.y; else if (check(x1) && check(x2)) if (get_angle(a, x1) > get_angle(a, x2)) cout << x1.x << << x1.y; else cout << x2.x << << x2.y; } return 0; } |
module fifo # (parameter abits = 20, dbits = 8)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)//only write
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count-1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=1;
end
end
else dffw1<=0;
end
always @ (posedge clock)//only read
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1-1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=1;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.10.2017 11:51:09
// Design Name:
// Module Name: srio_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module srio_testbench();
// wire declarations
reg log_clk_t;
reg log_rst_t;
// signals into the DUT
wire iotx_tvalid_t; // Indicates that the information on the channel is valid
reg iotx_tready_t; // Indicates that the data from the source is accepted (if valid)
wire iotx_tlast_t; // Indicates the last beat of a packet
wire [63:0] iotx_tdata_t; // Packet header and data
wire [7:0] iotx_tkeep_t; // Indicates whether the content of the associated byte of data is valid
wire [31:0] iotx_tuser_t; // Consists of the Source ID and Destination ID
reg iorx_tvalid_t; // Indicates that the information on the channel is valid
wire iorx_tready_t; // Indicates that the data from the source is accepted (if valid)
reg iorx_tlast_t; // Indicates the last beat of a packet
reg [63:0] iorx_tdata_t; // Packet header and data
reg [7:0] iorx_tkeep_t; // Indicates whether the content of the associated byte of data is valid
reg [31:0] iorx_tuser_t; // Consists of the Source ID and Destination ID
reg [2:0] current_state;
reg [2:0] next_state;
reg [4:0] some_counter;
// FSM
localparam [2:0] IDLE_S = 3'h00;
localparam [2:0] SEND_SW_S = 3'h01; // erase flash
localparam [2:0] SEND_DT_S = 3'h02; // send data
localparam [2:0] SEND_RD_S = 3'h03; // set some values
localparam [2:0] PRE_SEND_S = 3'h04; // preparation to send
localparam [2:0] FINAL_S = 3'h05; // send data
srio_response srio_rx(
.log_clk ( log_clk_t ),
.log_rst ( log_rst_t ),
.src_id ( 8'hFF ),
.id_override ( 1'b0 ),
// Regs with request data (from DSP to FPGA)
.axis_iorx_tvalid ( iorx_tvalid_t ),
.axis_iorx_tready ( iorx_tready_t ),
.axis_iorx_tlast ( iorx_tlast_t ),
.axis_iorx_tdata ( iorx_tdata_t ),
.axis_iorx_tkeep ( iorx_tkeep_t ),
.axis_iorx_tuser ( iorx_tuser_t ),
// Regs with response data (from FPGA to DSP)
.axis_iotx_tvalid ( iotx_tvalid_t ),
.axis_iotx_tlast ( iotx_tlast_t ),
.axis_iotx_tdata ( iotx_tdata_t ),
.axis_iotx_tkeep ( iotx_tkeep_t ),
.axis_iotx_tuser ( iotx_tuser_t ),
.axis_iotx_tready ( iotx_tready_t )
);
initial begin
log_clk_t = 1'b1;
log_rst_t = 1'b0;
iotx_tready_t = 1'b1;
iorx_tvalid_t = 1'b0;
iorx_tlast_t = 1'b0;
iorx_tuser_t = 32'h00;
iorx_tdata_t = 64'h00;
iorx_tkeep_t = 8'b0;
current_state = IDLE_S;
some_counter = 5'b0;
$display("<< Running testbench >>");
end
always // ãåíåðàòîð clk
#10 log_clk_t = !log_clk_t; // 50 MHz
event reset_trigger; // îáúÿâëåíèå ñîáûòèé
event reset_done_trigger;
// áëîê ôîðìèðîâàíèÿ Reset
initial begin
forever begin // áåñêîíå÷íûé öèêë
@(reset_trigger); // æä¸ì ñîáûòèÿ reset_trigger
@(negedge log_clk_t); // æä¸ì negedge clk_t
log_rst_t = 1'b1; // ñáðîñ
@(negedge log_clk_t);
log_rst_t = 1'b0;
-> reset_done_trigger; // ñîîáùàåì, ÷òî reset âûïîëíåí
end
end
always @( posedge log_clk_t or posedge log_rst_t ) begin
if( log_rst_t )
current_state = IDLE_S;
else
current_state = next_state;
end
// next-state logic
always @( current_state, iotx_tlast_t, some_counter, iorx_tready_t ) begin
next_state = IDLE_S;
case( current_state )
IDLE_S: begin
next_state = PRE_SEND_S;
end
SEND_SW_S: begin
next_state = SEND_DT_S;
end
SEND_DT_S: begin
next_state = PRE_SEND_S;
end
SEND_RD_S: begin
next_state = PRE_SEND_S;
end
PRE_SEND_S: begin
if( iotx_tlast_t == 1'b1 )
next_state = FINAL_S;
else if( some_counter < 5'h04 )
next_state = SEND_RD_S;
else if( (iorx_tready_t == 1'b1) && (some_counter == 5'h00))
next_state = SEND_SW_S;
else
next_state = PRE_SEND_S;
end
FINAL_S: begin
$finish;
end
endcase
end
// Õîä ñèìóëÿöèè
/*
initial
begin: TEST_CASE
#5 -> reset_trigger; // ñäåëàòü reset
@ (reset_done_trigger); // æä¸ì çàâåðøåíèÿ reset
end
*/
always @( current_state ) begin
case( current_state )
IDLE_S: begin
#5 -> reset_trigger; // ñäåëàòü reset
@ (reset_done_trigger); // æä¸ì çàâåðøåíèÿ reset
end
SEND_SW_S: begin
iorx_tuser_t = 32'h00cb00ff;
iorx_tdata_t = 64'h006020001093de10;
iorx_tkeep_t = 8'hFF;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b0;
end
SEND_DT_S: begin
iorx_tdata_t = 64'hddbbddbbddbbddbb;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b1;
iorx_tuser_t = 32'h00cb00ff;
some_counter = some_counter + 1'b1;
end
SEND_RD_S: begin
iorx_tdata_t = 64'h012420f01093de10;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b1;
iorx_tuser_t = 32'h00cb00ff;
some_counter = some_counter + 1'b1;
end
PRE_SEND_S: begin
iorx_tvalid_t = 1'b0;
iorx_tlast_t = 1'b0;
iorx_tuser_t = 32'h00cb00ff;
iorx_tdata_t = 64'h00;
iorx_tkeep_t = 8'hFF;
end
endcase
end
endmodule
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