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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
// Very simple test for interface pathclearing
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(2) itopa();
ifc #(4) itopb();
sub ca (.isub(itopa),
.clk);
sub cb (.isub(itopb),
.clk);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
itopb.valuei <= cyc[3:0];
if (cyc==1) begin
if (itopa.WIDTH != 2) $stop;
if (itopb.WIDTH != 4) $stop;
if ($bits(itopa.valueo) != 2) $stop;
if ($bits(itopb.valueo) != 4) $stop;
if ($bits(itopa.out_modport.valueo) != 2) $stop;
if ($bits(itopb.out_modport.valueo) != 4) $stop;
end
if (cyc==4) begin
if (itopa.valueo != 2'b11) $stop;
if (itopb.valueo != 4'b0011) $stop;
end
if (cyc==5) begin
if (itopa.valueo != 2'b00) $stop;
if (itopb.valueo != 4'b0100) $stop;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface ifc
#(parameter WIDTH = 1);
// verilator lint_off MULTIDRIVEN
logic [WIDTH-1:0] valuei;
logic [WIDTH-1:0] valueo;
// verilator lint_on MULTIDRIVEN
modport out_modport (input valuei, output valueo);
endinterface
// Note not parameterized
module sub
(
ifc.out_modport isub,
input clk
);
always @(posedge clk) isub.valueo <= isub.valuei + 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4B_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_BLACKBOX_V
|
#include <cstdio> #include <cstring> #include <iostream> #include <vector> #include <cmath> #include <cstdlib> #include <ctime> #include <algorithm> #include <string> #include <map> #define ll long long #define ls id << 1 #define rs id << 1 | 1 #define mem(array, value, size, type) memset(array, value, ((size) + 5) * sizeof(type)) #define memarray(array, value) memset(array, value, sizeof(array)) #define fillarray(array, value, begin, end) fill((array) + (begin), (array) + (end) + 1, value) #define fillvector(v, value) fill((v).begin(), (v).end(), value) #define pb(x) push_back(x) #define st(x) (1LL << (x)) #define pii pair<int, int> #define mp(a, b) make_pair((a), (b)) #define Flush fflush(stdout) #define vecfirst (*vec.begin()) #define veclast (*vec.rbegin()) #define vecall(v) (v).begin(), (v).end() #define vecupsort(v) (sort((v).begin(), (v).end())) #define vecdownsort(v, type) (sort(vecall(v), greater<type>())) #define veccmpsort(v, cmp) (sort(vecall(v), cmp)) using namespace std; const int N = 500050; const int inf = 0x3f3f3f3f; const ll llinf = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; const int MOD = 1e9 + 7; const double PI = acos(-1.0); clock_t TIME__START, TIME__END; void program_end() { #ifdef ONLINE printf( n nTime used: %.6lf(s) n , ((double)TIME__END - TIME__START) / 1000); system( pause ); #endif } int n; int ask1(int x, int y) { printf( 1 %d %d n , x, y), Flush; int ret; scanf( %d , &ret); return ret; } int ask2(int x, const vector<int> &vec) { printf( 2 %d %d , x, (int)vec.size()); for (auto i : vec) printf( %d , i); putchar( n ), Flush; int ret; scanf( %d , &ret); return ret; } int ans[105][105]; vector<int> e; vector<int> mergesort(int l, int r) { vector<int> ret; if (l == r) { ret.push_back(l); return ret; } int mid = (l + r) >> 1; auto vl = mergesort(l, mid); auto vr = mergesort(mid + 1, r); int i = 0, j = 0; while (i < (int)vl.size() && j < (int)vr.size()) { int r = ask1(vl[i], vr[j]); if (r == 1) { ret.push_back(vl[i]); i++; } else { ret.push_back(vr[j]); j++; } } while (i < (int)vl.size()) ret.push_back(vl[i]), i++; while (j < (int)vr.size()) ret.push_back(vr[j]), j++; return ret; } void work1() { e.clear(); e = mergesort(0, n - 1); for (int i = 0; i < (int)e.size(); ++i) for (int j = i; j < (int)e.size(); ++j) ans[e[i]][e[j]] = 1; } inline void solve() { memarray(ans, 0); scanf( %d , &n); work1(); int u = n - 1, p = n - 2; #ifdef VINGYING printf( Hamiton: ); for (auto i : e) cout << i << ; putchar( n ); #endif while (u >= 0 && p >= 0) { vector<int> v; for (int i = 0; i <= p; ++i) v.push_back(e[i]); int r = ask2(e[u], v); if (r == 1) p--; if (p < 0) { ans[e[u]][e[0]]=1; break; } if (r == 0) { ans[e[u]][e[p+1]]=1; u--; if (p==u)p--; if (p < 0) { ans[e[u]][e[0]]=1; break; } } } for(int k=0;k<n;k++) for(int i=0;i<n;i++) for(int j=0;j<n;j++) ans[i][j]=(ans[i][j]||(ans[i][k]&&ans[k][j])); printf( 3 n ); for (int i = 0; i < n; ++i, putchar( n )) for (int j = 0; j < n; ++j) printf( %d , ans[i][j]); Flush; int resp; scanf( %d ,&resp); if(resp==-1)exit(0); } int main() { TIME__START = clock(); int Test = 1; scanf( %d , &Test); while (Test--) { solve(); // if (Test) // putchar( n ); } TIME__END = clock(); program_end(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void debug() {} int const N = 1e3 + 9, OO = 1e9; int main() { int n, q, type, a; char b; bool prd = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { scanf( %c , &b); if (j == i && b == 1 ) prd = !prd; } } scanf( %d , &q); for (int i = 0; i < q; ++i) { scanf( %d , &type); if (type != 3) scanf( %d , &a); if (type == 1 || type == 2) prd = !prd; else printf((prd) ? 1 : 0 ); } }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { char ch = getchar(); long long p = 1, data = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) p = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { data = data * 10 + (ch ^ 48); ch = getchar(); } return p * data; } inline long long qpow(long long a, long long b) { long long r = 1; while (b) { if (b & 1) r = a * r; a = a * a; b >>= 1; } return r; } inline long long gcd(long long a, long long b) { if (!a || !b) return (!a) ? b : a; while (b ^= a ^= b ^= a %= b) ; return a; } inline long long lcm(long long a, long long b) { return a * b / gcd(a, b); } void exgcd(long long a, long long b, long long &x, long long &y) { if (!b) x = 1, y = 0; else { exgcd(b, a % b, y, x); y -= x * (a / b); } } const int mod = 1e9 + 7; int main() { int n = read(); long long a[2] = {0, 0}; for (int i = 1; i <= n; i++) { long long x = read(); a[i & 1] += x / 2 + x % 2; a[1 - i & 1] += x / 2; } printf( %lld n , min(a[0], a[1])); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MN = 2011; int n, a[MN]; vector<int> ls[MN]; void solve1(int u) { cout << YES << endl; for (int turn = 0, _a = (3); turn < _a; turn++) { for (int i = (1), _b = (2000); i <= _b; i++) { if (i != u) { for (int x = 0, _a = (ls[i].size()); x < _a; x++) cout << ls[i][x] << ; } else { if (turn == 0) cout << ls[i][0] << << ls[i][1] << << ls[i][2] << ; else if (turn == 1) cout << ls[i][0] << << ls[i][2] << << ls[i][1] << ; else cout << ls[i][1] << << ls[i][0] << << ls[i][2] << ; for (int x = (3), _b = (ls[i].size() - 1); x <= _b; x++) cout << ls[i][x] << ; } } cout << endl; } } void solve2(int u, int v) { cout << YES << endl; for (int turn = 0, _a = (3); turn < _a; turn++) { for (int i = (1), _b = (2000); i <= _b; i++) { if (i != u && i != v) { for (int x = 0, _a = (ls[i].size()); x < _a; x++) cout << ls[i][x] << ; } else if (i == u) { if (turn == 0) cout << ls[i][0] << << ls[i][1] << ; else if (turn == 1) cout << ls[i][0] << << ls[i][1] << ; else cout << ls[i][1] << << ls[i][0] << ; for (int x = (2), _b = (ls[i].size() - 1); x <= _b; x++) cout << ls[i][x] << ; } else if (i == v) { if (turn == 0) cout << ls[i][0] << << ls[i][1] << ; else if (turn == 1) cout << ls[i][1] << << ls[i][0] << ; else cout << ls[i][1] << << ls[i][0] << ; for (int x = (2), _b = (ls[i].size() - 1); x <= _b; x++) cout << ls[i][x] << ; } } cout << endl; } } int main() { ios ::sync_with_stdio(false); while (cin >> n) { for (int i = (1), _b = (n); i <= _b; i++) cin >> a[i]; for (int i = (0), _b = (2000); i <= _b; i++) ls[i].clear(); for (int i = (1), _b = (n); i <= _b; i++) { ls[a[i]].push_back(i); } bool ok = false; for (int i = (0), _b = (2000); i <= _b; i++) if (ls[i].size() >= 3) { solve1(i); ok = true; break; } if (ok) continue; for (int i = (1), _b = (2000); i <= _b; i++) { for (int j = (i + 1), _b = (2000); j <= _b; j++) if (ls[i].size() >= 2 && ls[j].size() >= 2) { solve2(i, j); ok = true; break; } if (ok) break; } if (!ok) cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int p, i, j; scanf( %d , &p); int n = 1 << (p + 1); vector<int> a(n); for (i = 2; i < n; i++) scanf( %d , &a[i]); vector<int> up(n), mx(n); for (i = 1; i < n; i++) { int sum = 0; for (j = i; j > 1; j /= 2) sum += a[j]; up[i] = sum; } int maxVal = *max_element(up.begin(), up.end()); for (i = n / 2; i < n; i++) { mx[i] += maxVal - up[i]; } for (i = n - 1; i > 1; i--) { int c = min(mx[i], mx[i ^ 1]); mx[i] -= c; mx[i ^ 1] -= c; mx[i / 2] += c; } printf( %d n , accumulate(mx.begin(), mx.end(), 0)); }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; const int N = 2e5 + 5; const double pi = acos(-1); int t; int main() { cin >> t; while (t--) { int n, m; cin >> n >> m; if (n % m == 0) cout << YES << n ; else cout << NO << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; using vll = vector<ll>; const string ALPHA = abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ ; string NAME[3] = { Kuro , Shiro , Katie }; int main() { ios::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(20); ll N; while (cin >> N) { vector<string> S(3); vll ma(3); for (int(a) = (0); (a) < (int)(3); ++(a)) { cin >> S[a]; for (char b : ALPHA) { ll x = 0; for (auto &(c) : (S[a])) { if (b == c) x++; } if (N > (int)(S[a]).size() - x) { ll p = N - (int)(S[a]).size() + x; if (p == 1 && x == (int)(S[a]).size()) (ma[a]) = max((ma[a]), ((int)(S[a]).size() - p)); else (ma[a]) = max((ma[a]), ((ll)(int)(S[a]).size())); } else { (ma[a]) = max((ma[a]), (N + x)); } } } ll m = -1, cnt = 0, cat = -1; for (int(a) = (0); (a) < (int)(3); ++(a)) { if (m < ma[a]) { cat = a; m = ma[a]; } } for (int(a) = (0); (a) < (int)(3); ++(a)) if (m == ma[a]) cnt++; if (cnt > 1) cout << Draw << endl; else cout << NAME[cat] << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, kk, a, b; double dp[1123][111][111]; int arr[111]; void solve() { scanf( %d , &n); ; scanf( %d , &kk); ; kk = min(kk, 1000); double dd = n * (n + 1) / 2; double ans = 0.0; for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); ; for (int j = i + 1; j < n; j++) { dp[0][i][j] = 1.0; } } for (int k = 1; k <= kk; k++) { for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { dp[k][i][j] += dp[k - 1][i][j] * ((i * (i + 1)) / 2 + ((n - 1 - j) * (n - j)) / 2 + ((j - i - 1) * (j - i)) / 2); for (int sum = j; sum <= i + (n - 1); sum++) { a = (sum - n + 1 > 0 ? sum - n + 1 : 0); b = (i < sum - j ? i : sum - j); dp[k][i][j] += (1.0 - dp[k - 1][sum - j][sum - i]) * (b - a + 1); } for (int sum = i; sum <= i + (j - 1); sum++) { a = (sum - j + 1 > 0 ? sum - j + 1 : 0); b = (i < sum - i ? i : sum - i); dp[k][i][j] += dp[k - 1][sum - i][j] * (b - a + 1); } for (int sum = (i + 1) + j; sum <= j + (n - 1); sum++) { a = (i + 1 > sum - n + 1 ? i + 1 : sum - n + 1); b = (j < sum - j ? j : sum - j); dp[k][i][j] += dp[k - 1][i][sum - j] * (b - a + 1); } dp[k][i][j] /= dd; } } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (arr[i] > arr[j]) { ans += dp[kk][i][j]; } else { ans += 1 - dp[kk][i][j]; } } } printf( %.11f n , ans); } int main() { solve(); return 0; }
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#include <bits/stdc++.h> int main() { const int N = 8; std::string pokemons[] = { vaporeon , jolteon , flareon , espeon , umbreon , leafeon , glaceon , sylveon }; int n; scanf( %d n , &n); std::string hidden; std::cin >> hidden; std::string output = ; for (int p = 0; p < N; p++) { std::string current = pokemons[p]; if (current.size() != n) { continue; } bool possible = 1; for (int q = 0; q < n; q++) { if (hidden[q] != . && hidden[q] != current[q]) { possible = 0; break; } } if (possible) { output = current; break; } } std::cout << output << std::endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
|
//==================================================================================================
// Filename : dimmer.v
// Created On : 2015-09-08 23:27:20
// Last Modified : 2015-09-08 23:41:34
// Revision : 1
// Author : Danny Dutton
// Class : ECE4514
//
// Description : This Verilog module will cycle through 16 different duty cycles for a set of
// LEDs using PWM. KEY0 raises the duty cycle, KEY1 lowers the duty cycle. KEY3 is
// an asynchronus reset. SW0 controls the test mode which scales the speed of
// cycling through duty cycles by a factor of 10. SW9 controls the Kitt mode which
// is not present in this current code.
//
// Refresh period = 200 Hz = .005 s
// Wave Period = .005 s * 50 MHz = 250000
// Step Count = 16
// Step Delay = 250000/16 = 15625
// log2(Wave Period) = log2(250000) = 18 bits
//
// So we will refresh the LEDs every 200 Hz (.005 sec). This refresh period will be controlled by a counter going from 0 to 2^(18)-1.
// The counter will be compared to the StepDelay*StepCount.
// DutyCycle = StepDelay*StepCount/CycleCount
//
//==================================================================================================
module dimmer(clock_50, clr_n, up_n, down_n, test, mode, leds);
input clock_50; // 50 MHz clock on board
input clr_n; // System reset, active low, KEY[3]
input up_n; // KEY0, raises duty cycle
input down_n; // KEY1, lowers duty cycle
input test; // SW0, scales time factors
input mode; // SW9, controls Kitt mode
output [9:0] leds; // 10 LEDs
reg [3:0] scale; // Time scale value, either 1 or 10
reg buttonpressed; // Current state of either KEY0 or 1 being pressed
reg nextbuttonpressed; // Next state of either KEY0 or 1 being pressed
reg [4:0] stepcounter; // Step of LED brightness, 0-15
reg [4:0] nextstepcounter; // Next step of LED brightness, 0-15
reg [17:0] cyclecounter; // LED refresh rate cycle counter, 0-249999
reg [25:0] upbuttoncounter; // Timer tracking hold time of up button, 0-49999999
reg [25:0] downbuttoncounter; // Timer tracking hold time of down button, 0-49999999
// Logic for next button state, set 1 when buttons pressed
always @(negedge up_n or negedge down_n) begin
// Reset button counters and turn flag on to denote a button is being pushed
if (up_n == 0) begin
nextbuttonpressed <= 1;
end
else if (down_n == 0) begin
nextbuttonpressed <= 1;
end
// No more buttons are being pushed so reset the flag state
else begin
nextbuttonpressed <= 0;
end
end
// Logic for next step count state
always @(upbuttoncounter or downbuttoncounter) begin
// Up button is being pushed so turn up the brightness
if (!up_n && (upbuttoncounter == 0) && buttonpressed) begin
nextstepcounter <= (stepcounter < 4'd15) ? stepcounter + 4'b1 : stepcounter;
end
// Down button is being pushed so turn down the brightness
else if (!down_n && (downbuttoncounter == 0) && buttonpressed) begin
nextstepcounter <= (stepcounter > 0) ? stepcounter - 4'b1 : stepcounter;
end
// Nothing is being pushed anymore so keep state
else begin
nextstepcounter <= stepcounter;
end
end
// Logic for next counter state
always @(posedge clock_50 or negedge clr_n) begin
// Reset count values
if (clr_n == 0) begin
cyclecounter <= 0;
stepcounter <= 0;
buttonpressed <= 0;
upbuttoncounter <= 0;
downbuttoncounter <= 0;
end
else begin
// Set state to the next state
scale = test ? 4'b1010 : 1'b1;
stepcounter <= nextstepcounter;
buttonpressed <= nextbuttonpressed;
// Increment cycle count always
cyclecounter <= cyclecounter + 13'b1;
// Cycle counter next state
if (cyclecounter >= (250000/scale)) begin
cyclecounter <= 0;
end
// Set up button counter next state
if (upbuttoncounter >= (50000000/scale) || (up_n == 1)) begin
upbuttoncounter <= 0;
end
else begin
upbuttoncounter <= upbuttoncounter + 18'b1;
end
// Set down button counter next state
if (downbuttoncounter >= (50000000/scale) || (down_n == 1)) begin
downbuttoncounter <= 0;
end
else begin
downbuttoncounter <= downbuttoncounter + 18'b1;
end
end
end
// Turn on LEDs if cycle count is within the duty cycle
assign leds = (cyclecounter < stepcounter*(15625/scale)) ? 10'b1111111111 : 10'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////
// Copyright (c) 2006 Rice University //
// All Rights Reserved //
// This code is covered by the Rice-WARP license //
// See http://warp.rice.edu/license/ for details //
//////////////////////////////////////////////////////////
module analog_bridge
(
clock_in,
clock_out,
user_DAC1_A,
user_DAC1_B,
user_DAC2_A,
user_DAC2_B,
user_DAC1_sleep,
user_DAC2_sleep,
user_ADC_A,
user_ADC_B,
user_ADC_DFS,
user_ADC_DCS,
user_ADC_pdwnA,
user_ADC_pdwnB,
user_ADC_otrA,
user_ADC_otrB,
user_LED,
analog_DAC1_A,
analog_DAC1_B,
analog_DAC2_A,
analog_DAC2_B,
analog_DAC1_sleep,
analog_DAC2_sleep,
analog_ADC_A,
analog_ADC_B,
analog_ADC_DFS,
analog_ADC_DCS,
analog_ADC_pdwnA,
analog_ADC_pdwnB,
analog_ADC_otrA,
analog_ADC_otrB,
analog_LED
);
/**********************/
/* Clock & Data Ports */
/**********************/
input clock_in;
output clock_out;
input [0:13] user_DAC1_A;
input [0:13] user_DAC1_B;
input [0:13] user_DAC2_A;
input [0:13] user_DAC2_B;
input user_DAC1_sleep;
input user_DAC2_sleep;
output [0:13] user_ADC_A;
output [0:13] user_ADC_B;
reg [0:13] user_ADC_A;
reg [0:13] user_ADC_B;
input user_ADC_DFS;
input user_ADC_DCS;
input user_ADC_pdwnA;
input user_ADC_pdwnB;
output user_ADC_otrA;
output user_ADC_otrB;
input [0:2] user_LED;
output [0:13] analog_DAC1_A;
output [0:13] analog_DAC1_B;
output [0:13] analog_DAC2_A;
output [0:13] analog_DAC2_B;
reg [0:13] analog_DAC1_A;
reg [0:13] analog_DAC1_B;
reg [0:13] analog_DAC2_A;
reg [0:13] analog_DAC2_B;
output analog_DAC1_sleep;
output analog_DAC2_sleep;
reg analog_DAC1_sleep;
reg analog_DAC2_sleep;
input [0:13] analog_ADC_A;
input [0:13] analog_ADC_B;
output analog_ADC_DFS;
output analog_ADC_DCS;
output analog_ADC_pdwnA;
output analog_ADC_pdwnB;
input analog_ADC_otrA;
input analog_ADC_otrB;
output [0:2] analog_LED;
wire [0:13] temp_analog_DAC1_A;
wire [0:13] temp_analog_DAC1_B;
wire [0:13] temp_analog_DAC2_A;
wire [0:13] temp_analog_DAC2_B;
/**********************************/
/* Clocks and analog data signals */
/**********************************/
assign clock_out = clock_in;
assign temp_analog_DAC1_A = user_DAC1_A[0:13];
assign temp_analog_DAC1_B = user_DAC1_B[0:13];
assign temp_analog_DAC2_A = user_DAC2_A[0:13];
assign temp_analog_DAC2_B = user_DAC2_B[0:13];
assign analog_ADC_DFS = user_ADC_DFS;
assign analog_ADC_DCS = user_ADC_DCS;
assign analog_ADC_pdwnA = user_ADC_pdwnA;
assign analog_ADC_pdwnB = user_ADC_pdwnB;
assign user_ADC_otrA = analog_ADC_otrA;
assign user_ADC_otrB = analog_ADC_otrB;
assign analog_LED = user_LED;
// synthesis attribute iob of analog_DAC1_A is true;
// synthesis attribute iob of analog_DAC1_B is true;
// synthesis attribute iob of analog_DAC2_A is true;
// synthesis attribute iob of analog_DAC2_B is true;
always @(posedge clock_in)
begin
analog_DAC1_A <= {temp_analog_DAC1_A[0], ~temp_analog_DAC1_A[1:13]};
analog_DAC1_B <= {temp_analog_DAC1_B[0], ~temp_analog_DAC1_B[1:13]};
analog_DAC2_A <= {temp_analog_DAC2_A[0], ~temp_analog_DAC2_A[1:13]};
analog_DAC2_B <= {temp_analog_DAC2_B[0], ~temp_analog_DAC2_B[1:13]};
analog_DAC1_sleep <= user_DAC1_sleep;
analog_DAC2_sleep <= user_DAC2_sleep;
user_ADC_A <= analog_ADC_A;
user_ADC_B <= analog_ADC_B;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; string s; cin >> s; set<int> col[26]; vector<int> ans; int cnt = 0; for (int i = 0; i < n; i++) { set<int> used; for (int j = s[i] - a + 1; j < 26; j++) for (int num : col[j]) used.insert(num); int newCol = 1; while (used.count(newCol)) newCol++; col[s[i] - a ].insert(newCol); ans.push_back(newCol); cnt = max(cnt, newCol); } cout << cnt << n ; for (int i : ans) cout << i << ; return 0; }
|
// DESCRIPTION: Verilator: Simple test of unoptflat
//
// Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping
// through 2 sub-modules.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [2:0] x;
initial begin
x = 3'b000;
end
test1 test1i ( .clk (clk),
.xvecin (x[1:0]),
.xvecout (x[2:1]));
test2 test2i ( .clk (clk),
.xvecin (x[2:1]),
.xvecout (x[1:0]));
always @(posedge clk or negedge clk) begin
`ifdef TEST_VERBOSE
$write("x = %x\n", x);
`endif
if (x[1] != 0) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module test1
(/*AUTOARG*/
// Inputs
clk,
xvecin,
// Outputs
xvecout
);
input clk;
input wire [1:0] xvecin;
output wire [1:0] xvecout;
assign xvecout = {xvecin[0], clk};
endmodule // test
module test2
(/*AUTOARG*/
// Inputs
clk,
xvecin,
// Outputs
xvecout
);
input clk;
input wire [1:0] xvecin;
output wire [1:0] xvecout;
assign xvecout = {clk, xvecin[1]};
endmodule // test
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); string a; string b; cin >> a >> b; int order = 0; while (a[order] == 0 ) { order++; } a = a.substr(order); order = 0; while (b[order] == 0 ) { order++; } b = b.substr(order); if (a.size() > b.size()) { cout << > ; } else if (a.size() < b.size()) { cout << < ; } else { for (int i = 0; i < a.size(); i++) { if (a[i] > b[i]) { cout << > ; return 0; } else if (a[i] < b[i]) { cout << < ; return 0; } } cout << = ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:37:02 03/12/2015
// Design Name:
// Module Name: complex
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module complex(
input [7:0] x,
input [7:0] y,
output out
);
wire [9:0] and_outputs;
wire [4:0] or_outputs;
genvar i;
generate
for(i = 0; i < 8; i = i + 1)
begin: and_1st_row
assign and_outputs[i] = x[i] & y[i];
end
for(i = 0; i < 4; i = i + 1)
begin: or_2nd_row
assign or_outputs[i] = and_outputs[2 * i] | and_outputs[2 * i + 1];
end
assign and_outputs[8] = or_outputs[0] & or_outputs[1];
assign and_outputs[9] = or_outputs[2] & or_outputs[3];
assign or_outputs[4] = and_outputs[8] | and_outputs[9];
endgenerate
assign out = or_outputs[4];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 333333; vector<pair<int, int> > graph[N]; int vis[N], d[N]; bool has[N]; int n, m; int dfs(int u) { vis[u] = true; int cnt = 0; for (auto e : graph[u]) { if (!vis[e.first]) { if (dfs(e.first)) { has[e.second] = true; cnt++; } } } return cnt % 2 != d[u]; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = (1); i <= (n); i++) { cin >> d[i]; } for (int i = (1); i <= (m); i++) { int u, v; cin >> u >> v; graph[u].push_back(make_pair(v, i)); graph[v].push_back(make_pair(u, i)); } int cnt = 0; for (int i = (1); i <= (n); i++) { cnt += d[i] == 1; } for (int i = (1); i <= (n); i++) { if (d[i] == -1) { if (cnt & 1) { d[i] = 1; cnt++; } else { d[i] = 0; } } } if (cnt & 1) { cout << -1 << n ; return 0; } dfs(1); vector<int> v; for (int i = (1); i <= (m); i++) { if (has[i]) { v.push_back(i); } } cout << (int)(v).size() << n ; for (auto x : v) { cout << x << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 55, MAXM = 20020; int n, m, k, acc[MAXN][MAXM], dp[MAXN][MAXM], ans; struct no { int beg, end, mid, mx, lz; no *l, *r; no(int beg, int end) : beg(beg), end(end), mid((beg + end) >> 1), mx(0), lz(0) { if (beg != end) l = new no(beg, mid), r = new no(mid + 1, end); } void refresh() { if (!lz) return; mx += lz; if (beg != end) l->lz += lz, r->lz += lz; lz = 0; } void upd(int a, int b, int inc) { refresh(); if (end < a || b < beg) return; if (a <= beg && end <= b) return lz += inc, refresh(); l->upd(a, b, inc), r->upd(a, b, inc); mx = max(l->mx, r->mx); } void set(int pos, int val) { refresh(); if (beg == end) return void(mx = val); (pos <= mid ? l : r)->set(pos, val); mx = max(l->mx, r->mx); } int get(int a, int b) { refresh(); if (end < a || b < beg) return 0; if (a <= beg && end <= b) return mx; return max(l->get(a, b), r->get(a, b)); } void print() { refresh(); if (beg == end) return printf( %d , mx), void(); l->print(), r->print(); } }; int main() { scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &acc[i][j]), acc[i][j] += acc[i][j - 1]; no seg(1, m - k + 1); for (int i = n; i >= 1; --i) { for (int j = 1; j <= k; ++j) seg.upd(1, j, -(acc[i + 1][j] - acc[i + 1][j - 1])); for (int j = 1; j <= m - k + 1; ++j) { int aux = acc[i][j + k - 1] - acc[i][j - 1] + acc[i + 1][j + k - 1] - acc[i + 1][j - 1]; if (i == n) { dp[i][j] = aux; continue; } dp[i][j] = max(dp[i][j], seg.get(j - k + 1, j + k - 1)); if (j > k) dp[i][j] = max(dp[i][j], seg.get(1, j - k)); if (j + k <= m - k + 1) dp[i][j] = max(dp[i][j], seg.get(j + k, m - k + 1)); dp[i][j] += aux; seg.upd(max(1, j - k + 1), j, (acc[i + 1][j] - acc[i + 1][j - 1])); seg.upd(j + 1, j + k, -(acc[i + 1][j + k] - acc[i + 1][j + k - 1])); } for (int j = 1; j <= m - k + 1; ++j) seg.set(j, dp[i][j]); } printf( %d n , seg.get(1, m - k + 1)); }
|
#include <bits/stdc++.h> using namespace std; long long int arr[10000]; int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int a, b, c, i, j, k, n, m, state = 0; for (i = 0; i < 6; i++) cin >> arr[i]; sort(arr, arr + 6); for (i = 0; i < 3; i++) { if (arr[i] == arr[i + 1] && arr[i + 1] == arr[i + 2] && arr[i + 2] == arr[i + 3] && state == 0) { state = 1; arr[i] = 0; arr[i + 1] = 0; arr[i + 2] = 0; arr[i + 3] = 0; break; } } if (state == 0) { cout << Alien << endl; return 0; } long long int t1 = 0, t2 = 0; for (i = 0; i < 6; i++) { if (arr[i] != 0 && t1 == 0) t1 = arr[i]; else if (arr[i] != 0) t2 = arr[i]; } if (t1 == t2) cout << Elephant << endl; else cout << Bear << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, c = 0, e, i, n; cin >> n; vector<char> v; char s[n + 1]; cin >> s; for (i = 0; i < n; i++) { if ((s[i] - 0 ) % 2 != 0) { c++; v.push_back(s[i]); if (c == 2) break; } } if (c < 2) cout << -1 n ; else { for (i = 0; i < 2; i++) cout << v[i]; cout << n ; } } }
|
`timescale 1ns/1ps
//**********************************************************************
// File: i2c_slave.v
// Module:i2c_slave
// by Robin zhang
//**********************************************************************
module i2c_slave_reduced(
reset_n,
sda,
scl,
clock,
led
);
input reset_n; //extern signal
input scl;
inout sda;
input clock; //intern signal
output led;
wire sda_en;
wire sda_in;
wire sda_out;
assign sda_in = (!sda_en) ? sda : 1'bz;
assign sda = sda_en ? ((sda_out == 1'b1)? 1'bz:1'b0) : 1'bz;
//reduce the 50M HZ clk to 5M HZ
reg [3:0] clk_count;
reg clk;
always @(posedge clock or negedge reset_n) begin
if(!reset_n) begin
clk_count <= 8'h0;
clk <= 1'b0;
end
else begin
if(clk_count < 8'd10)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
clk <= ~clk;
end
end
end
i2c_slave_op_reduced i2c_slave_op_reduced_inst(
.reset_n(reset_n),
.clock(clk),
.sda_out(sda_out),
.sda_in(sda_in),
.sda_en(sda_en),
.scl(scl),
.led(led)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ji[300], k, qi, mz[400010]; char s[400010], tp[400010]; int main() { scanf( %d%s , &n, s + 1); for (int i = 1; i <= n; i++) { ji[s[i]]++; } for (int i = 0; i < 300; i++) if (ji[i] & 1) k++; qi = k; if (!qi) { for (k = 1;; k++) if (n % k == 0) break; n /= k; printf( %d n , k); if (n & 1) { for (int i = 0, tt = 0; i < 300; i++) { while (ji[i]) { mz[++tt] = i; ji[i]--; if (tt == k) goto qaz; } } qaz:; n >>= 1; for (int i = 1, p = 0; i <= k; i++) { for (int j = 1; j <= n; j++) { while (!ji[p]) p++; ji[p] -= 2; tp[j] = tp[n * 2 + 2 - j] = p; } tp[n + 1] = mz[i]; printf( %s , tp + 1); } return 0; } n >>= 1; for (int i = 1, p = 0; i <= k; i++) { for (int j = 1; j <= n; j++) { while (!ji[p]) p++; ji[p] -= 2; tp[j] = tp[n * 2 + 1 - j] = p; } printf( %s , tp + 1); } return 0; } for (;; k++) if (n % k == 0 && (n / k) & 1) break; printf( %d n , k); n /= k; int tt = 0; for (int i = 0; i < 300; i++) if (ji[i] & 1) { mz[++tt] = i; ji[i]--; } if (tt == k) goto qazz; for (int i = 0; i < 300; i++) { while (ji[i]) { mz[++tt] = i; ji[i]--; if (tt == k) goto qazz; } } qazz:; n >>= 1; for (int i = 1, p = 0; i <= k; i++) { for (int j = 1; j <= n; j++) { while (!ji[p]) p++; ji[p] -= 2; tp[j] = tp[n * 2 + 2 - j] = p; } tp[n + 1] = mz[i]; printf( %s , tp + 1); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
endclass
function int Cls::ext_f_np;
return 1;
endfunction
function int Cls::ext_f_p();
return value;
endfunction
function int Cls::ext_f_i(int in);
return in+1;
endfunction
task Cls::ext_t_np();
$write("*-* All Finished *-*\n");
endtask
task Cls::ext_t_p();
$finish;
endtask
task Cls::ext_t_i(int in);
if (in != 2) $stop;
value = in;
endtask
module t (/*AUTOARG*/);
initial begin
Cls c = new;
c.ext_t_i(2);
c.ext_t_np();
c.ext_t_p();
if (c.ext_f_np() != 1) $stop;
if (c.ext_f_p() != 2) $stop;
if (c.ext_f_i(10) != 11) $stop;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *)
(* CHECK_LICENSE_TYPE = "design_1_microblaze_0_xlconcat_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_microblaze_0_xlconcat_0,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_microblaze_0_xlconcat_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_addsub ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// addition/subtraction entity for the addition/subtraction ////
//// unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_addsub(
clk,
rst,
fpu_op_i,
fracta_i,
fractb_i,
signa_i,
signb_i,
fract_o,
sign_o);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input fpu_op_i;
input [FRAC_WIDTH+4:0] fracta_i;
input [FRAC_WIDTH+4:0] fractb_i;
input signa_i;
input signb_i;
output reg [FRAC_WIDTH+4:0] fract_o;
output reg sign_o;
wire [FRAC_WIDTH+4:0] s_fracta_i;
wire [FRAC_WIDTH+4:0] s_fractb_i;
wire [FRAC_WIDTH+4:0] s_fract_o;
wire s_signa_i, s_signb_i, s_sign_o;
wire s_fpu_op_i;
wire fracta_gt_fractb;
wire s_addop;
assign s_fracta_i = fracta_i;
assign s_fractb_i = fractb_i;
assign s_signa_i = signa_i;
assign s_signb_i = signb_i;
assign s_fpu_op_i = fpu_op_i;
always @(posedge clk or posedge rst)
if (rst)
begin
fract_o <= 'd0;
sign_o <= 1'b0;
end
else
begin
fract_o <= s_fract_o;
sign_o <= s_sign_o;
end
assign fracta_gt_fractb = s_fracta_i > s_fractb_i;
// check if its a subtraction or an addition operation
assign s_addop = ((s_signa_i ^ s_signb_i) & !s_fpu_op_i) |
((s_signa_i ^~ s_signb_i) & s_fpu_op_i);
// sign of result
assign s_sign_o = ((s_fract_o == 28'd0) & !(s_signa_i & s_signb_i)) ? 1'b0 :
(!s_signa_i & (!fracta_gt_fractb & (fpu_op_i^s_signb_i)))|
(s_signa_i & (fracta_gt_fractb | (fpu_op_i^s_signb_i)));
// add/substract
assign s_fract_o = s_addop ?
(fracta_gt_fractb ? s_fracta_i - s_fractb_i :
s_fractb_i - s_fracta_i) :
s_fracta_i + s_fractb_i;
endmodule // fpu_addsub
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_1_V
`define SKY130_FD_SC_HDLL__SEDFXBP_1_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sedfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sedfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
wire o0, o1;
sub #(1) a(.i(1'b0), .o(o0));
sub #(2) b(.i(1'b0), .o(o1));
always @(posedge clk) begin
if (o0 != 1'b0) begin
$write("Bad o0\n");
$stop;
end
if (o1 != 1'b1) begin
$write("Bad o1\n");
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub
#(
parameter int W
)
(
input wire i,
output wire o
);
typedef struct packed {
logic [W-1:0] a;
} s;
sub2 #(s) c(.i(i), .o(o));
endmodule
module sub2
# (
parameter type T = logic
)
(
input wire i,
output wire o
);
if ($bits(T) % 2 == 1) begin
assign o = i;
end else begin
assign o = ~i;
end
endmodule
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
// Major Functions:
// This code is using for configuring the output frequency of
// SI570 I2C Programable XO/VCXO
// ============================================================================
// Design Description:
//
//
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 12/02/20 :| Initial Version
// ============================================================================
module si570_controller (
input wire iCLK, // system clock 50mhz
input wire iRST_n, // system reset
input wire iStart_Go, // system set
input wire [2:0] iFREQ_MODE, //clock frequency mode 000:100Mhz, 001: 125Mhz, 010:156.25Mhz, 011:250Mhz, 100:312.5Mhz , 101:322.26Mhz , 110:644.53Mhz ,111:100Mhz
output wire oController_rdy, // high for si570 controller is rdy
output wire I2C_CLK,
inout wire I2C_DATA,
output wire [7:0] oREAD_Data,
output wire oSI570_ONE_CLK_CONFIG_DONE
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire [6:0] slave_addr;
wire [7:0] byte_addr;
wire [7:0] byte_data;
wire wr_cmd;
//wire [7:0] oREAD_Data;
//wire [2:0] iFREQ_MODE;
wire i2c_control_start;
wire i2c_reg_control_start;
wire i2c_bus_controller_state;
wire iINITIAL_ENABLE;
wire system_start;
wire i2c_clk;
wire i2c_controller_config_done;
//wire oController_rdy;
wire initial_start;
//=============================================================================
// Structural coding
//=============================================================================
i2c_reg_controller u1(
.iCLK(iCLK), // system clock 50mhz
.iRST_n(iRST_n), // system reset
.iENABLE(system_start), // i2c reg contorl enable signale , high for enable .please use pulse
.iI2C_CONTROLLER_STATE(i2c_bus_controller_state), // i2c controller state , high for i2c controller state not in idel
.iFREQ_MODE(iFREQ_MODE), // clock frequency mode
.oSLAVE_ADDR(slave_addr),
.oBYTE_ADDR(byte_addr),
.oBYTE_DATA(byte_data),
.oWR_CMD(wr_cmd), // write or read commnad for i2c controller , 1 for write command
.oStart(i2c_reg_control_start), // i2c controller start control signal, high for start to send signal
.iI2C_CONTROLLER_CONFIG_DONE(i2c_controller_config_done),
.oSI570_ONE_CLK_CONFIG_DONE(oSI570_ONE_CLK_CONFIG_DONE),
.oController_Ready(oController_rdy),
);
initial_config initial_config(
.iCLK(iCLK), // system clock 50mhz
.iRST_n(iRST_n), // system reset
.oINITIAL_START(initial_start),
.iINITIAL_ENABLE(1'b1),
);
assign system_start = iStart_Go|initial_start;
clock_divider u3(
.iCLK(iCLK),
.iRST_n(iRST_n),
.oCLK_OUT(i2c_clk),
);
i2c_bus_controller u4 (
.iCLK(i2c_clk),
.iRST_n(iRST_n),
.iStart(i2c_reg_control_start),
.iSlave_addr(slave_addr),
.iWord_addr(byte_addr),
.iSequential_read(1'b0),
.iRead_length(8'd1),
.i2c_clk(I2C_CLK),
.i2c_data(I2C_DATA),
.i2c_read_data(oREAD_Data),
.wr_data(byte_data),
.wr_cmd(wr_cmd),
.oSYSTEM_STATE(i2c_bus_controller_state),
.oCONFIG_DONE(i2c_controller_config_done),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string base, s; cin >> base >> s; int n = base.size(), m = s.size(); base = * + base; s = * + s; int f[m + 2][n + 2]; memset(f, 0, sizeof(f)); for (int i = m; i >= 1; i--) for (int j = n; j >= 1; j--) if (s[i] == base[j]) f[i][j] = f[i + 1][j + 1] + 1; int g[m + 2][n + 2]; memset(g, 0, sizeof(g)); for (int i = m; i >= 1; i--) for (int j = 1; j <= n; j++) if (s[i] == base[j]) g[i][j] = g[i + 1][j - 1] + 1; vector<pair<int, int>> ans; for (int i = 1; i <= m;) { int l1 = max_element(f[i] + 1, f[i] + n + 1) - f[i]; int l2 = max_element(g[i] + 1, g[i] + n + 1) - g[i]; if (!f[i][l1] && !g[i][l2]) { cout << -1; return 0; } if (f[i][l1] >= g[i][l2]) ans.push_back({l1, l1 + f[i][l1] - 1}); else ans.push_back({l2, l2 - g[i][l2] + 1}); i += max(f[i][l1], g[i][l2]); } cout << ans.size() << n ; for (auto p : ans) cout << p.first << << p.second << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_SYMBOL_V
`define SKY130_FD_SC_HS__XNOR2_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Mon Jul 18 16:08:19 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.5 2005/12/14 12:38:08 wig Exp $
// $Date: 2005/12/14 12:38:08 $
// $Log: ent_a.v,v $
// Revision 1.5 2005/12/14 12:38:08 wig
// Updated some testcases (verilog, padio)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No `defines in this module
`ifdef MAGMA
`define ent_aa_inst_name ent_aa
`else
`define ent_aa_inst_name ent_aa_rtl_conf
`endif
`ifdef MAGMA
`define ent_ab_inst_name ent_ab
`else
`define ent_ab_inst_name ent_ab_rtl_conf
`endif
`ifdef MAGMA
`define ent_ad_inst_name ent_ad
`else
`define ent_ad_inst_name ent_ad_rtl_conf
`endif
`ifdef MAGMA
`define ent_ae_inst_name ent_ae
`else
`define ent_ae_inst_name ent_ae_rtl_conf
`endif
module ent_a
//
// Generated module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a,
port_o_a,
sig_07,
sig_08,
sig_13,
sig_i_a2,
sig_o_a2
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
`ent_aa_inst_name inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
`ent_ab_inst_name inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
`ent_ad_inst_name inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
`ent_ae_inst_name inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; namespace io { const int L = (1 << 20) + 1; char buf[L], *S, *T, c; char getchar() { if (__builtin_expect(S == T, 0)) { T = (S = buf) + fread(buf, 1, L, stdin); return (S == T ? EOF : *S++); } return *S++; } int inp() { int x = 0, f = 1; char ch; for (ch = getchar(); !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); x = x * 10 + ch - 0 , ch = getchar()) ; return x * f; } unsigned inpu() { unsigned x = 0; char ch; for (ch = getchar(); !isdigit(ch); ch = getchar()) ; for (; isdigit(ch); x = x * 10 + ch - 0 , ch = getchar()) ; return x; } long long inp_ll() { long long x = 0; int f = 1; char ch; for (ch = getchar(); !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); x = x * 10 + ch - 0 , ch = getchar()) ; return x * f; } char B[25], *outs = B + 20, *outr = B + 20; template <class T> inline void print(register T a, register char x = 0) { if (x) *--outs = x, x = 0; if (!a) *--outs = 0 ; else while (a) *--outs = (a % 10) + 48, a /= 10; if (x) *--outs = x; fwrite(outs, outr - outs, 1, stdout); outs = outr; } }; // namespace io using io ::inp; using io ::inp_ll; using io ::inpu; using io ::print; using i32 = int; using i64 = long long; using u8 = unsigned char; using u32 = unsigned; using u64 = unsigned long long; using f64 = double; using f80 = long double; long long power(long long a, long long b, long long p) { if (!b) return 1; long long t = power(a, b / 2, p); t = t * t % p; if (b & 1) t = t * a % p; return t; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <class T> inline void freshmin(T &a, const T &b) { if (a > b) a = b; } template <class T> inline void freshmax(T &a, const T &b) { if (a < b) a = b; } const int MAXN = 100000; const int DEG = 5; const int BASE = 10; const int MAXP = 10000000; const int MOD = 1000000007; const f80 MI = f80(1) / MOD; const long long INF = 10000000000000000LL; const long long inf = 5000000000000LL; int n; int modBASE[1111], modDEG[1111]; template <class T> struct node { T v[DEG]; node(T c = 0, int k = 0) { for (int i = 0; i < DEG; ++i) v[i] = 0; v[k] = c; } node &operator+=(const node &A) { for (int i = 0; i < DEG; ++i) v[i] += A.v[i]; return *this; } friend node operator*(const node &A, const node &B) { node ret; for (int i = 0; i < DEG; ++i) for (int j = 0; j < DEG; ++j) ret.v[modDEG[i + j]] += A.v[i] * B.v[j]; return ret; } node &operator*=(const node &A) { return *this = *this * A; } node shl(int shift) { node ret; for (int i = 0; i < DEG; ++i) ret.v[modDEG[i + shift]] = (shift & 1) ? -v[i] : v[i]; return ret; } }; template <class T, class V> T power(T a, V n) { if (n == 0) return 1; T t = power(a, n / 2); t = t * t; if (n & 1) t = t * a; return t; } node<u64> a[MAXN]; void fft(bool inv = 0) { int shift = inv ? BASE - 1 : 1; for (int step = 1; step < MAXN; step *= BASE) { for (int offset = 0; offset < MAXN; ++offset) { if (offset / step % BASE != 0) continue; node<u64> to[BASE]; for (int i = 0; i < BASE; ++i) for (int j = 0; j < BASE; ++j) to[i] += a[offset + j * step].shl(modBASE[i * j * shift]); for (int i = 0; i < BASE; ++i) a[offset + i * step] = to[i]; } } } int main() { for (int i = 0; i < 1111; ++i) { modBASE[i] = i % BASE; modDEG[i] = i % DEG; } n = inp(); for (int i = 1; i <= n; ++i) a[inp()] += 1; fft(); for (int i = 0; i < MAXN; ++i) a[i] = power(a[i], n); fft(1); for (int i = 0; i < n; ++i) { u64 ans = a[i].v[0] - a[i].v[4]; ans >>= 5; ans *= 6723469279985657373ULL; print(ans & ((1ULL << 58) - 1), n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[500000 + 5], ans[500000 + 5]; int main() { int n, k, d; cin >> n >> k >> d; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); ans[n + 1] = 0; ans[n] = 1; int lptr = n - 1, dptr = n - 1; for (int i = n - 1; i >= 0; i--) { while (lptr > 0 && lptr - i > k - 1) lptr--; while (dptr > 0 && a[dptr] - a[i] > d) dptr--; if (ans[lptr + 1] - ans[dptr + 2] > 0 && lptr - i == k - 1) ans[i]++; ans[i] += ans[i + 1]; } if (ans[0] - ans[1] == 1) cout << YES << endl; else cout << NO << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:03:44 05/12/2015
// Design Name: organisation
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_organisation.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: organisation
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_organisation;
// Inputs
reg clock;
reg [2:0] reg_read_adr1;
reg [2:0] reg_read_adr2;
reg [2:0] reg_write_adr;
reg reg_write;
reg flush_e;
reg [1:0] forward1;
reg [1:0] forward2;
reg [7:0] ALU_con;
reg ALU_source2;
reg [15:0] offset;
reg mem_write;
reg mem_to_reg;
reg [15:0] processor_input;
// Outputs
wire N;
wire Z;
wire C;
wire V;
wire [15:0] processor_output;
// Instantiate the Unit Under Test (UUT)
organisation uut (
.clock(clock),
.reg_read_adr1(reg_read_adr1),
.reg_read_adr2(reg_read_adr2),
.reg_write_adr(reg_write_adr),
.reg_write(reg_write),
.flush_e(flush_e),
.forward1(forward1),
.forward2(forward2),
.ALU_con(ALU_con),
.ALU_source2(ALU_source2),
.offset(offset),
.mem_write(mem_write),
.mem_to_reg(mem_to_reg),
.processor_input(processor_input),
.N(N),
.Z(Z),
.C(C),
.V(V),
.processor_output(processor_output)
);
initial begin
// Initialize Inputs
clock = 0;
reg_read_adr1 = 0;
reg_read_adr2 = 0;
reg_write_adr = 0;
reg_write = 0;
flush_e = 0;
reg_write = 0;
forward1 = 0;
forward2 = 0;
ALU_con = 0;
ALU_source2 = 0;
offset = 0;
mem_write = 0;
mem_to_reg = 0;
processor_input = 0;
// Wait 100 ns for global reset to finish
// #100;
#2;
offset = 16'h0003;
ALU_source2 = 1;
ALU_con = 8'haf;
#2;
offset = 0;
ALU_source2 = 0;
ALU_con = 0;
forward1 = 1;
forward2 = 1;
#2;
forward1 = 0;
forward2 = 0;
reg_write = 1;
#2;
reg_write = 0;
end
always #1 clock = !clock;
endmodule
|
#include <bits/stdc++.h> const double pi = acos(-1.0); const int maxn = (5e2 + 10); const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; using namespace std; map<long long, long long> ys; long long a[200010]; int main() { cin.tie(0); ios::sync_with_stdio(false); long long n; long double ans = 0, sum = 0; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; ys[a[i]] += 1; } for (long long i = 1; i <= n; i++) { ans += sum - (long double)(n - i + 1) * (long double)a[i]; ans += ys[a[i] - 1] - ys[a[i] + 1]; sum -= a[i]; ys[a[i]] -= 1; } cout << fixed << setprecision(0) << ans; return 0; }
|
//-------------------------------------------------------------------
//-- txtest_tb.v
//-- Banco de pruebas para la tranmision de datos
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module txtest2_tb();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente
txtest2 #(.BAUD(BAUD))
dut(
.clk(clk),
.load(dtr),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("txtest2_tb.vcd");
$dumpvars(0, txtest2_tb);
#1 dtr <= 0;
//-- Enviar primer caracter
#FRAME_WAIT dtr <= 1;
#(FRAME * 3) dtr <=0;
//-- Segundo envio
#FRAME_WAIT dtr <=1;
#(FRAME * 3) dtr <=0;
#FRAME_WAIT $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include<bits/stdc++.h> using namespace std; #define fastio ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0) #define f first #define s second #define for1(i,a,b) for (int i = a; i < b; i++) #define for2(i,a,b) for (int i = a; i > b; i--) #define arrin(a,n) for (int i = 0; i < n; i++) cin >> a[i]; #define arrout(a,n) for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; #define arrin2d(a,m,n) for (int i = 0; i < m; i++){for (int j = 0; j < n; j++) cin >> a[i][j];} #define arrout2d(a,m,n) for (int i = 0; i < m; i++){for (int j = 0; j < n; j++) cout << a[i][j] << ; cout << n ;} #define w(t) int t; cin >> t; while(t--) #define strin(s) getline(cin,s) #define pushb push_back #define popb pop_back #define pushf push_front #define popf pop_front #define mp make_pair #define lower_bound lb #define upper_bound ub #define yes cout << YES n #define no cout << NO n typedef long long ll; typedef long double ld; typedef vector<int> vi; typedef vector<ll> vll; typedef vector<pair<int,int>> vp; typedef vector<char> vch; typedef vector<string> vstr; typedef set<ll> sll; typedef pair<int,int> pi; typedef map<int,int> mi; typedef map<int,char> mch; //typedef __int128_t vvlint; const int inf = 1e9 + 7; /* freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); */ void tc() { int a1,a2,a3,a4,a5,c1,c2,c3; cin >> c1 >> c2 >> c3; cin >> a1 >> a2 >> a3 >> a4 >> a5; if (a1 <= c1 && a2 <= c2 && a3 <= c3) { c1 -= a1; c2 -= a2; c3 -= a3; a4 -= min(a4,c1); a5 -= min(a5,c2); if (a4 + a5 <= c3) yes; else no; } else no; } int main() { fastio; w(t) { tc(); } return 0; }
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module watchdog(
input nLDS, RW,
input A23I, A22I,
input [21:17] M68K_ADDR_U,
//input [12:1] M68K_ADDR_L,
input WDCLK,
output nHALT,
output nRESET,
input nRST
);
reg [3:0] WDCNT;
initial
WDCNT <= 4'b0000;
// IMPORTANT:
// nRESET is an open-collector output on B1, so that the 68k can drive it (RESET instruction)
// The line has a 4.7k pullup (schematics page 1)
// nRESET changes state on posedge nBNKB (posedge mclk), but takes a slightly variable amount of time to
// return high after it is released. Low during 8 frames, released during 8 frames.
assign nRESET = nRST & ~WDCNT[3];
assign nHALT = nRESET;
// $300001 (LDS)
// 0011000xxxxxxxxxxxxxxxx1
// MAME says 00110001xxxxxxxxxxxxxxx1 but NEO-B1 doesn't have A16
assign WDRESET = &{nRST, ~|{nLDS, RW, A23I, A22I}, M68K_ADDR_U[21:20], ~|{M68K_ADDR_U[19:17]}};
always @(posedge WDCLK or posedge WDRESET or posedge ~nRST)
begin
if (WDRESET)
begin
WDCNT <= 4'b0000;
end
else if (!nRST)
begin
WDCNT <= 4'b1110; // DEBUG - Used to speed up simulation
//WDCNT <= 4'b1000; // Correct value
end
else
WDCNT <= WDCNT + 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); long long int n, x, y, cn = 0, ans = 0; string s; cin >> n >> x >> y >> s; for (int i = 0; i < n; i++) { if (s[i] == 0 ) cn++; else { if (cn) ans++; cn = 0; } } if (cn) ans++; if (!ans) cout << 0 << endl; else cout << (ans - 1) * min(x, y) + y << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Content Addressable Memory (shift register based)
*/
module cam_srl #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// width of data bus slices (4 for SRL16, 5 for SRL32)
parameter SLICE_WIDTH = 4
)
(
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ADDR_WIDTH-1:0] match_addr,
output wire match
);
// total number of slices (enough to cover DATA_WIDTH with address inputs)
localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
// depth of RAMs
localparam RAM_DEPTH = 2**ADDR_WIDTH;
localparam [1:0]
STATE_INIT = 2'd0,
STATE_IDLE = 2'd1,
STATE_WRITE = 2'd2,
STATE_DELETE = 2'd3;
reg [1:0] state_reg = STATE_INIT, state_next;
wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, compare_data};
wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}}, write_data};
reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
reg [SLICE_COUNT-1:0] shift_data;
reg [RAM_DEPTH-1:0] shift_en;
reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_data_padded_next;
reg write_busy_reg = 1'b1;
assign write_busy = write_busy_reg;
reg [RAM_DEPTH-1:0] match_raw_out[SLICE_COUNT-1:0];
reg [RAM_DEPTH-1:0] match_many_raw;
reg [RAM_DEPTH-1:0] match_many_reg = {RAM_DEPTH{1'b0}};
assign match_many = match_many_reg;
integer k;
always @* begin
match_many_raw = ~shift_en;
for (k = 0; k < SLICE_COUNT; k = k + 1) begin
match_many_raw = match_many_raw & match_raw_out[k];
end
end
priority_encoder #(
.WIDTH(RAM_DEPTH),
.LSB_PRIORITY("HIGH")
)
priority_encoder_inst (
.input_unencoded(match_many_reg),
.output_valid(match),
.output_encoded(match_addr),
.output_unencoded(match_single)
);
integer i;
// SRLs
genvar row_ind, slice_ind;
generate
for (row_ind = 0; row_ind < RAM_DEPTH; row_ind = row_ind + 1) begin : row
for (slice_ind = 0; slice_ind < SLICE_COUNT; slice_ind = slice_ind + 1) begin : slice
reg [2**SLICE_WIDTH-1:0] srl_mem = {2**SLICE_WIDTH{1'b0}};
// match
always @* begin
match_raw_out[slice_ind][row_ind] = srl_mem[compare_data_padded[SLICE_WIDTH * slice_ind +: SLICE_WIDTH]];
end
// write
always @(posedge clk) begin
if (shift_en[row_ind]) begin
srl_mem <= {srl_mem[2**SLICE_WIDTH-2:0], shift_data[slice_ind]};
end
end
end
end
endgenerate
// match
always @(posedge clk) begin
match_many_reg <= match_many_raw;
end
// write
always @* begin
state_next = STATE_IDLE;
count_next = count_reg;
shift_data = {SLICE_COUNT{1'b0}};
shift_en = {RAM_DEPTH{1'b0}};
write_addr_next = write_addr_reg;
write_data_padded_next = write_data_padded_reg;
case (state_reg)
STATE_INIT: begin
// zero out shift registers
shift_en = {RAM_DEPTH{1'b1}};
shift_data = {SLICE_COUNT{1'b0}};
if (count_reg == 0) begin
state_next = STATE_IDLE;
end else begin
count_next = count_reg - 1;
state_next = STATE_INIT;
end
end
STATE_IDLE: begin
if (write_enable) begin
write_addr_next = write_addr;
write_data_padded_next = write_data_padded;
count_next = {SLICE_WIDTH{1'b1}};
if (write_delete) begin
state_next = STATE_DELETE;
end else begin
state_next = STATE_WRITE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE: begin
// write entry
shift_en = 1'b1 << write_addr;
for (i = 0; i < SLICE_COUNT; i = i + 1) begin
shift_data[i] = count_reg == write_data_padded_reg[SLICE_WIDTH * i +: SLICE_WIDTH];
end
if (count_reg == 0) begin
state_next = STATE_IDLE;
end else begin
count_next = count_reg - 1;
state_next = STATE_WRITE;
end
end
STATE_DELETE: begin
// delete entry
shift_en = 1'b1 << write_addr;
shift_data = {SLICE_COUNT{1'b0}};
if (count_reg == 0) begin
state_next = STATE_IDLE;
end else begin
count_next = count_reg - 1;
state_next = STATE_DELETE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_INIT;
count_reg <= {SLICE_WIDTH{1'b1}};
write_busy_reg <= 1'b1;
end else begin
state_reg <= state_next;
count_reg <= count_next;
write_busy_reg <= state_next != STATE_IDLE;
end
write_addr_reg <= write_addr_next;
write_data_padded_reg <= write_data_padded_next;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long aa[15]; long long bb[15]; for (int i = 0; i < 14; i++) { scanf( %lld , &aa[i]); bb[i] = aa[i]; } long long maxx = 0; for (int i = 0; i < 14; i++) { if (!aa[i]) continue; long long sum = 0; int c = aa[i] % 14; for (int k = 1; k <= c; k++) { if (i + k < 14) bb[k + i]++; else { bb[(i + k) % 14]++; } } for (int j = 0; j < 14; j++) { if (j != i) bb[j] += aa[i] / 14; else bb[j] = aa[i] / 14; if (bb[j] % 2 == 0) sum += bb[j]; } if (sum > maxx) maxx = sum; for (int j = 0; j < 14; j++) bb[j] = aa[j]; } cout << maxx << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int ckmax(int &a, int b) { return a < b ? a = b, 1 : 0; } inline int ckmin(int &a, int b) { return a > b ? a = b, 1 : 0; } struct matrix { double x[128][128]; double *operator[](int a) { return x[a]; } void clear() { memset(x, 0, sizeof(x)); } void reset() { clear(); for (int i = 0; i < 128; ++i) x[i][i] = 1; } } p, a, ans; matrix operator*(matrix &a, matrix &b) { p.clear(); for (int i = 0; i < 128; i++) for (int j = 0; j < 128; j++) for (int k = 0; k < 128; k++) p[i][j] += a[i][k] * b[k][j]; return p; } int n, x; double pos[128]; int main() { scanf( %d%d , &n, &x); for (int i = 0; i <= x; ++i) scanf( %lf , &pos[i]); a.clear(); for (int i = 0; i < 128; ++i) for (int j = 0; j < 128; ++j) a[i][j] = pos[i ^ j]; ans.reset(); for (; n; n >>= 1, a = a * a) if (n & 1) ans = ans * a; printf( %.10f n , 1.0 - double(ans[0][0])); return 0; }
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#include <bits/stdc++.h> using namespace std; void fast() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); } void file() {} int main() { fast(); file(); int n, idx = 0; cin >> n; vector<vector<int>> v(n, vector<int>(n)); vector<bool> ans(n, 1); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> v[i][j]; if (v[i][j] == 3) { ans[i] = 0; ans[j] = 0; } else if (v[i][j] == 1) ans[i] = 0; else if (v[i][j] == 2) ans[j] = 0; } } int cnt = 0; for (int i = 0; i < n; i++) { if (ans[i]) cnt++; } cout << cnt << endl; for (int i = 0; i < n; i++) { if (ans[i]) cout << i + 1 << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long dx[8] = {0, 1, 0, -1, 1, 1, -1, -1}; long long dy[8] = {1, 0, -1, 0, -1, 1, 1, -1}; class pa3 { public: long long x; long long y, z; pa3(long long x = 0, long long y = 0, long long z = 0) : x(x), y(y), z(z) {} bool operator<(const pa3& p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; return z < p.z; } bool operator>(const pa3& p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; return z > p.z; } bool operator==(const pa3& p) const { return x == p.x && y == p.y && z == p.z; } bool operator!=(const pa3& p) const { return !(x == p.x && y == p.y && z == p.z); } }; class pa4 { public: long long x; long long y, z, w; pa4(long long x = 0, long long y = 0, long long z = 0, long long w = 0) : x(x), y(y), z(z), w(w) {} bool operator<(const pa4& p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; if (z != p.z) return z < p.z; return w < p.w; } bool operator>(const pa4& p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; if (z != p.z) return z > p.z; return w > p.w; } bool operator==(const pa4& p) const { return x == p.x && y == p.y && z == p.z && w == p.w; } }; class pa2 { public: long long x, y; pa2(long long x = 0, long long y = 0) : x(x), y(y) {} pa2 operator+(pa2 p) { return pa2(x + p.x, y + p.y); } pa2 operator-(pa2 p) { return pa2(x - p.x, y - p.y); } bool operator<(const pa2& p) const { return y != p.y ? y < p.y : x < p.x; } bool operator>(const pa2& p) const { return x != p.x ? x < p.x : y < p.y; } bool operator==(const pa2& p) const { return abs(x - p.x) == 0 && abs(y - p.y) == 0; } bool operator!=(const pa2& p) const { return !(abs(x - p.x) == 0 && abs(y - p.y) == 0); } }; string itos(long long i) { ostringstream s; s << i; return s.str(); } long long Gcd(long long v, long long b) { if (v == 0) return b; if (b == 0) return v; if (v > b) return Gcd(b, v); if (v == b) return b; if (b % v == 0) return v; return Gcd(v, b % v); } long long mod; long long extgcd(long long a, long long b, long long& x, long long& y) { if (b == 0) { x = 1; y = 0; return a; } long long d = extgcd(b, a % b, y, x); y -= a / b * x; return d; } pair<long long, long long> operator+(const pair<long long, long long>& l, const pair<long long, long long>& r) { return {l.first + r.first, l.second + r.second}; } pair<long long, long long> operator-(const pair<long long, long long>& l, const pair<long long, long long>& r) { return {l.first - r.first, l.second - r.second}; } ostream& operator<<(ostream& os, const vector<long long>& VEC) { for (auto v : VEC) os << v << ; return os; } ostream& operator<<(ostream& os, const pair<long long, long long>& PAI) { os << PAI.first << : << PAI.second; return os; } ostream& operator<<(ostream& os, const pa3& PAI) { os << PAI.x << : << PAI.y << : << PAI.z; return os; } ostream& operator<<(ostream& os, const pa4& PAI) { os << PAI.x << : << PAI.y << : << PAI.z << : << PAI.w; return os; } ostream& operator<<(ostream& os, const vector<pair<long long, long long> >& VEC) { for (auto v : VEC) os << v << ; return os; } long long beki(long long wa, long long rr, long long warukazu) { if (rr == 0) return 1 % warukazu; if (rr == 1) return wa % warukazu; wa %= warukazu; if (rr % 2 == 1) return ((long long)beki(wa, rr - 1, warukazu) * (long long)wa) % warukazu; long long zx = beki(wa, rr / 2, warukazu); return (zx * zx) % warukazu; } long long pr[1100000]; long long inv[1100000]; long long comb(long long nn, long long rr) { if (rr < 0 || rr > nn || nn < 0) return 0; long long r = pr[nn] * inv[rr]; r %= mod; r *= inv[nn - rr]; r %= mod; return r; } void gya(long long ert) { pr[0] = 1; for (long long i = 1; i <= ert; i++) { pr[i] = ((long long)pr[i - 1] * i) % mod; } inv[ert] = beki(pr[ert], mod - 2, mod); for (long long i = ert - 1; i >= 0; i--) { inv[i] = (long long)inv[i + 1] * (i + 1) % mod; } } struct seg_rangeupd_getsum { private: public: long long cor = (1 << 18); long long inff = 1000000007 * 1000000ll; vector<long long> vec; vector<long long> lazy; void shoki1() { vec.resize(2 * cor + 3, 0); lazy.resize(2 * cor + 3, inff); } void shoki2() {} long long chien(long long k, long long len) { if (lazy[k] == inff) return vec[k]; if (k < cor) { vec[k] = lazy[k] * len; lazy[2 * k] = lazy[k]; lazy[2 * k + 1] = lazy[k]; lazy[k] = inff; } else { vec[k] = lazy[k]; lazy[k] = inff; } return vec[k]; } void clear_chien(long long r) { if (r == 0) return; long long f = 31 - __builtin_clz(r); long long pos = 0; long long len = cor; for (long long i = f; i >= 0; i--) { pos *= 2; pos += !!(r & (1 << i)); chien(pos, len); len /= 2; } } void rangeupd(long long a, long long b, long long w) { a += cor, b += cor; long long aa = a / (a & (-a)) / 2; long long bb = b / (b & (-b)) / 2; long long lenaa = 2 * (a & -a); long long lenbb = 2 * (b & -b); clear_chien(aa); clear_chien(bb); while (a < b) { if (a & 1) { lazy[a] = w; a++; } if (b & 1) { b--; lazy[b] = w; } a /= 2, b /= 2; } while (aa > 0 || bb > 0) { if (aa > bb) { vec[aa] = chien(2 * aa, lenaa / 2) + chien(2 * aa + 1, lenaa / 2); aa /= 2; lenaa *= 2; } else if (aa < bb) { vec[bb] = chien(2 * bb, lenbb / 2) + chien(2 * bb + 1, lenbb / 2); bb /= 2; lenbb *= 2; } else { vec[aa] = chien(2 * aa, lenaa / 2) + chien(2 * aa + 1, lenaa / 2); aa /= 2; lenaa *= 2; bb = aa, lenbb = aa; } } } long long getsum(long long a, long long b) { a += cor, b += cor; long long aa = a / (a & (-a)) / 2; long long bb = b / (b & (-b)) / 2; clear_chien(aa); clear_chien(bb); long long ans = 0; long long len = 1; while (a < b) { if (a & 1) { ans += chien(a, len); a++; } if (b & 1) { b--; ans += chien(b, len); } a /= 2, b /= 2, len *= 2; } return ans; } long long lower_bound(long long p, long long x) { p += cor; long long ima = 0; bool fst = 1; long long len = 1; while (1) { while (!(p & 1)) p /= 2, len *= 2; if (fst) fst = 0, clear_chien(p / 2); if (ima + chien(p, len) >= x) break; ima = ima + vec[p]; p++; if (p == (p & (-p))) return cor; } while (1) { if (p >= cor) return p - cor; p *= 2; len /= 2; if (ima + chien(p, len) < x) { ima += vec[p]; p++; } } } long long upper_bound(long long p, long long x) { p += cor; long long ima = 0; bool fst = 1; long long len = 1; while (1) { while (!(p & 1)) p /= 2, len *= 2; if (fst) fst = 0, clear_chien(p / 2); if (ima + chien(p, len) > x) break; ima = ima + vec[p]; p++; if (p == (p & (-p))) return cor; } while (1) { if (p >= cor) return p - cor; p *= 2; len /= 2; if (ima + chien(p, len) <= x) { ima += vec[p]; p++; } } } }; void solve() { long long n, q, t; cin >> n >> q >> t; string s; cin >> s; seg_rangeupd_getsum ss; ss.shoki1(); ss.shoki2(); for (long long i = 0; i < n; i++) { ss.rangeupd(i, i + 1, s[i] - a ); } set<long long> se; long long dp[11][11] = {}; for (long long i = 0; i < n - 1; i++) { if (s[i] != s[i + 1]) { se.insert(i); dp[s[i] - a ][s[i + 1] - a ]++; } } se.insert(1000000007); while (q--) { long long e; cin >> e; if (e == 1) { long long l, r; char c; cin >> l >> r >> c; l--; auto it = se.lower_bound(l - 1); while (1) { if (*it >= r) break; long long mae = ss.getsum(*it, *it + 1); long long ato = ss.getsum(*it + 1, *it + 2); dp[mae][ato]--; it = se.erase(it); } ss.rangeupd(l, r, c - a ); if (l) { long long mae = ss.getsum(l - 1, l); long long ato = ss.getsum(l, l + 1); if (mae != ato) dp[mae][ato]++, se.insert(l - 1); } if (r < n) { long long mae = ss.getsum(r - 1, r); long long ato = ss.getsum(r, r + 1); if (mae != ato) dp[mae][ato]++, se.insert(r - 1); } } else { string w; cin >> w; long long ans = n; for (long long i = 0; i < t; i++) for (long long j = i + 1; j < t; j++) { ans -= dp[w[i] - a ][w[j] - a ]; } cout << ans << endl; } } } signed main() { mod = 1000000007; cin.tie(0); ios::sync_with_stdio(false); long long n = 1; for (long long i = 0; i < n; i++) solve(); return 0; }
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/*
Test bench for Clock Divider
Project: Cloud Car
Author: Nathan Larson
Date: 10/22/2016
*/
`timescale 1 ns/ 1 ps
module clockDivider_testbench();
// test vector input registers
reg clk;
reg reset;
// wires
wire newClk;
clockDivider clkDiv (
.clk(clk),
.reset(reset),
.newClk(newClk)
);
initial
begin
// code that executes only once
// insert code here --> begin
$display("Running testbench");
reset = 0;
clk = 0;
#10
reset = 1;
#20000;
// --> end
end
always #10 clk = ~clk;
// optional sensitivity list
// @(event1 or event2 or .... eventn)
endmodule
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/**
* bsg_parallel_in_serial_out_dynamic.v
*
* Paul Gao 06/2019
*
*/
`include "bsg_defines.v"
module bsg_parallel_in_serial_out_dynamic
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(max_els_p)
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Input side
,input v_i
,input [lg_max_els_lp-1:0] len_i
,input [max_els_p-1:0][width_p-1:0] data_i
,output ready_o
// Output side
,output v_o
,output len_v_o
,output [width_p-1:0] data_o
,input yumi_i
);
logic go_fifo_yumi_li;
logic [lg_max_els_lp-1:0] len_lo;
logic [max_els_p-1:0][width_p-1:0] fifo_data_lo;
// Go fifo and data fifo share the same control logic
// They always contain same number of elements in memory
// Go fifo
bsg_two_fifo
#(.width_p(lg_max_els_lp )
) go_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o(ready_o )
,.data_i (len_i )
,.v_i (v_i )
,.v_o (v_o )
,.data_o (len_lo )
,.yumi_i (go_fifo_yumi_li)
);
// Data fifo
bsg_two_fifo
#(.width_p(max_els_p*width_p)
) data_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o( )
,.data_i (data_i )
,.v_i (v_i )
,.v_o ( )
,.data_o (fifo_data_lo )
,.yumi_i (go_fifo_yumi_li )
);
logic [lg_max_els_lp-1:0] count_r, count_lo;
logic clear_li, up_li;
logic count_r_is_zero, count_r_is_last;
// fix evaluate to Z problem in simulation
assign count_lo = count_r;
assign count_r_is_zero = (count_lo == lg_max_els_lp'(0));
assign count_r_is_last = (count_lo == len_lo );
// Indicate if output word is first word of packet
assign len_v_o = count_r_is_zero;
// Count up if current word is not last word of packet.
assign up_li = yumi_i & ~count_r_is_last;
// Clear counter when whole packet finish sending
assign clear_li = yumi_i & count_r_is_last;
assign go_fifo_yumi_li = clear_li;
// Length counter
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0)
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li)
,.up_i (up_li )
,.count_o (count_r )
);
// Output mux
bsg_mux
#(.width_p(width_p )
,.els_p (max_els_p )
) data_mux
(.data_i (fifo_data_lo)
,.sel_i (count_lo )
,.data_o (data_o )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_dynamic)
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#include <bits/stdc++.h> using namespace std; char a[1000][1001], s[] = DIMA ; bool b = 0, f[1000][1000]; int q, w, d[1000][1000]; void l(short int r, short int t, short int e) { int y = 0; if ((f[r][t]) || (b)) { b = 1; return; } f[r][t] = 1; e %= 4; if ((r) && (a[r - 1][t] == s[e])) { if (d[r - 1][t] == -1) l(r - 1, t, e + 1); if (y < d[r - 1][t]) y = d[r - 1][t]; } if ((r < q - 1) && (a[r + 1][t] == s[e])) { if (d[r + 1][t] == -1) l(r + 1, t, e + 1); if (y < d[r + 1][t]) y = d[r + 1][t]; } if ((t) && (a[r][t - 1] == s[e])) { if (d[r][t - 1] == -1) l(r, t - 1, e + 1); if (y < d[r][t - 1]) y = d[r][t - 1]; } if ((t < w - 1) && (a[r][t + 1] == s[e])) { if (d[r][t + 1] == -1) l(r, t + 1, e + 1); if (y < d[r][t + 1]) y = d[r][t + 1]; } if (e == 0) y++; d[r][t] = y; } int main() { int e, r, t = 0, c; scanf( %d%d , &q, &w); for (e = 0; e < q; e++) { scanf( %s , a[e]); for (r = 0; r < w; r++) { d[e][r] = -1; f[e][r] = 0; } } for (e = 0; e < q; e++) for (r = 0; r < w; r++) if (a[e][r] == D ) { if (d[e][r] == -1) l(e, r, 1); if (b) goto stop; if (t < d[e][r]) t = d[e][r]; } stop: if (b) printf( Poor Inna! ); else if (t == 0) printf( Poor Dima! ); else printf( %d , t); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { char c; int blackweight = 0; int whiteweight = 0; int i = 0; while (cin >> c) { i++; switch (c) { case Q : whiteweight += 9; break; case R : whiteweight += 5; break; case B : whiteweight += 3; break; case N : whiteweight += 3; break; case P : whiteweight += 1; break; case q : blackweight += 9; break; case r : blackweight += 5; break; case b : blackweight += 3; break; case n : blackweight += 3; break; case p : blackweight += 1; break; } if (i == 64) { if (blackweight > whiteweight) cout << Black << endl; if (blackweight == whiteweight) cout << Draw << endl; if (blackweight < whiteweight) cout << White << endl; blackweight = whiteweight = i = 0; } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_PP_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busreceiver (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 17; int MAX[maxn << 1], lazy[maxn << 1], e[maxn]; void push_up(int now) { MAX[now] = max(MAX[now << 1], MAX[now << 1 | 1]); } void push_down(int now) { lazy[now << 1] += lazy[now]; lazy[now << 1 | 1] += lazy[now]; MAX[now << 1] += lazy[now]; MAX[now << 1 | 1] += lazy[now]; lazy[now] = 0; } void update(int now, int p, int L, int R, int l, int r) { if (R < l) return; if (R >= r) { MAX[now] += p; lazy[now] += p; return; } if (lazy[now]) push_down(now); int mid = (l + r) >> 1; update(now << 1, p, L, R, l, mid); update(now << 1 | 1, p, L, R, mid + 1, r); push_up(now); } int query(int now, int l, int r) { int mid = (l + r) >> 1; if (l == r) return l; if (lazy[now]) push_down(now); if (MAX[now << 1 | 1] > 0) return query(now << 1 | 1, mid + 1, r); else return query(now << 1, l, mid); } int main() { int m, pos, op, x; scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d%d , &pos, &op); if (op == 1) { scanf( %d , &x); e[pos] = x; update(1, 1, 1, pos, 1, m); } else { update(1, -1, 1, pos, 1, m); } if (MAX[1] > 0) { printf( %d n , e[query(1, 1, m)]); } else puts( -1 ); } return 0; }
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#include <bits/stdc++.h> using namespace std; struct tree { tree() : par(NULL), val(0) { next.clear(); }; map<int, tree *> next; tree *par; int val; void setParent(tree *p) { par = p; } }; tree *moveDown(tree *root, int n) { tree *ret = NULL; if (root->next.count(n)) { ret = root->next[n]; } else { ret = new tree(); ret->setParent(root); root->next[n] = ret; } ret->val++; return ret; } tree *moveUp(tree *root) { return root->par; } char line[1000003]; char tmp[5002]; map<string, int> f; vector<int> v; int go(tree *root, int what) { int ans = 0; for (map<int, tree *>::iterator it = root->next.begin(); it != root->next.end(); ++it) { if (it->first == what) ans += it->second->val + go(it->second, what); else ans += go(it->second, what); } return ans; } int calc(tree *root, int ind = 0) { if (ind + 1 == v.size()) { return go(root, v[ind]); } int ans = 0; for (map<int, tree *>::iterator it = root->next.begin(); it != root->next.end(); ++it) { if (it->first == v[ind]) ans += calc(it->second, ind + 1); else ans += calc(it->second, ind); } return ans; } void out(tree *root, int par = -1) { for (map<int, tree *>::iterator it = root->next.begin(); it != root->next.end(); ++it) { out(it->second, it->first); } } int main() { tree *root = new tree(), *root1 = root; char str[25] = {0}; gets(line); int l = strlen(line), tot = 0; map<string, int>::iterator it; for (int i = 0; i < l; ++i) { if (line[i] == < ) { int type = 0, len = 0; if (line[i + 1] == / ) type = 1; for (i = i + 1 + (type == 1); i < l; ++i) { if (line[i] == / ) type = 2; else if (line[i] == > ) break; else str[len++] = line[i]; } int num = 0; str[len] = 0 ; it = f.find(string(str)); if (it != f.end()) num = it->second; else f[string(str)] = num = tot++; if (type == 0) { root = moveDown(root, num); } else if (type == 1) { root = moveUp(root); } else { moveDown(root, num); } } } int q; scanf( %d n , &q); while (q--) { gets(tmp); istringstream ss(tmp); string s; bool ok = true; v.clear(); while (ss >> s) { it = f.find(s); if (it != f.end()) { v.push_back(it->second); } else { ok = false; break; } } if (ok) printf( %d n , calc(root1)); else printf( 0 n ); } return 0; }
|
// sonic_pma_v1_03
`timescale 1 ps / 1 ps
module sonic_pma_v1_05 (
input wire phy_mgmt_clk, // phy_mgmt_clk.clk
input wire phy_mgmt_clk_reset, // phy_mgmt_clk_reset.reset
input wire [8:0] phy_mgmt_address, // phy_mgmt.address
input wire phy_mgmt_read, // .read
output wire [31:0] phy_mgmt_readdata, // .readdata
output wire phy_mgmt_waitrequest, // .waitrequest
input wire phy_mgmt_write, // .write
input wire [31:0] phy_mgmt_writedata, // .writedata
output wire [3:0] tx_ready, // tx_ready.export
output wire [3:0] rx_ready, // rx_ready.export
input wire [0:0] pll_ref_clk, // pll_ref_clk.clk
output wire [3:0] pll_locked, // pll_locked.export
output wire [3:0] tx_serial_data, // tx_serial_data.export
input wire [3:0] rx_serial_data, // rx_serial_data.export
output wire [3:0] rx_is_lockedtoref, // rx_is_lockedtoref.export
output wire [3:0] rx_is_lockedtodata, // rx_is_lockedtodata.export
output wire tx_clkout0, // tx_clkout0.clk
output wire tx_clkout1, // tx_clkout0.clk
output wire tx_clkout2, // tx_clkout0.clk
output wire tx_clkout3, // tx_clkout0.clk
output wire rx_clkout0, // rx_clkout0.clk
output wire rx_clkout1, // rx_clkout0.clk
output wire rx_clkout2, // rx_clkout0.clk
output wire rx_clkout3, // rx_clkout0.clk
input wire [39:0] tx_parallel_data0, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data1, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data2, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data3, // tx_parallel_data0.data
output wire [39:0] rx_parallel_data0, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data1, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data2, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data3 // rx_parallel_data0.data
);
wire [3:0] pll_powerdown;
wire [3:0] tx_digitalreset;
wire [3:0] tx_analogreset;
wire [3:0] rx_digitalreset;
wire [3:0] rx_analogreset;
wire [3:0] tx_pma_clkout;
wire [3:0] rx_pma_clkout;
wire [3:0] tx_cal_busy;
wire [3:0] rx_cal_busy;
wire reconfig_busy;
wire [159:0] rx_pma_parallel_data;
wire [159:0] tx_pma_parallel_data;
wire [367:0] reconfig_from_xcvr;
wire [559:0] reconfig_to_xcvr;
//----------------------------------------------------------------------
// Reconfiguration Controller
//----------------------------------------------------------------------
altera_xgbe_pma_reconfig_wrapper altera_xgbe_pma_reconfig_wrapper_inst(
/* inputs */
//----------------------------------------------------------------------
// Transceiver Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr),
.reconfig_mgmt_address (phy_mgmt_address),
.reconfig_mgmt_read (phy_mgmt_read),
.reconfig_mgmt_write (phy_mgmt_write),
.reconfig_mgmt_writedata (phy_mgmt_writedata),
// Reconfiguration mMnagement
.mgmt_rst_reset (phy_mgmt_clk_reset),
.mgmt_clk_clk (phy_mgmt_clk),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// Transceiver Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr),
.reconfig_busy (reconfig_busy),
.reconfig_mgmt_readdata (phy_mgmt_readdata),
.reconfig_mgmt_waitrequest (phy_mgmt_waitrequest)
//----------------------------------------------------------------------
);
//----------------------------------------------------------------------
// Native PHY IP Transceiver Instance
//----------------------------------------------------------------------
altera_xcvr_native_sv_wrapper altera_xcvr_native_sv_wrapper_inst (
/*inputs */
//----------------------------------------------------------------------
// FPGA Fabric interface
.tx_pma_parallel_data (tx_pma_parallel_data),
.unused_tx_pma_parallel_data (),
// PLL, CDR, and Loopback
.tx_pll_refclk (pll_ref_clk),
.rx_cdr_refclk (pll_ref_clk),
.pll_powerdown (pll_powerdown),
.rx_seriallpbken (2'b0), // loopback mode
// Speed Serial I/O
.rx_serial_data (rx_serial_data),
// Reset And Calibration Status
.tx_digitalreset (tx_digitalreset),
.tx_analogreset (tx_analogreset),
.rx_digitalreset (rx_digitalreset),
.rx_analogreset (rx_analogreset),
// Transceiver Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// FPGA Fabric interface
.tx_pma_clkout (tx_pma_clkout),
.rx_pma_clkout (rx_pma_clkout),
.rx_pma_parallel_data (rx_pma_parallel_data),
.unused_rx_pma_parallel_data (),
// PLL, CDR, and Loopback
.pll_locked (pll_locked),
.rx_is_lockedtodata (rx_is_lockedtodata),
.rx_is_lockedtoref (rx_is_lockedtoref),
// Speed Serial I/O
.tx_serial_data (tx_serial_data),
// Reset And Calibration Status
.tx_cal_busy (tx_cal_busy),
.rx_cal_busy (rx_cal_busy),
// Transceiver Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr)
//----------------------------------------------------------------------
);
//----------------------------------------------------------------------
// Reset Controller
//----------------------------------------------------------------------
altera_xcvr_reset_control_wrapper altera_xcvr_reset_control_wrapper_inst (
/* inputs */
//----------------------------------------------------------------------
// PLL and Calibration Status
.pll_locked (pll_locked),
.pll_select (2'b11), // only needed for multiple PLLs
.tx_cal_busy (tx_cal_busy),
.rx_cal_busy (rx_cal_busy),
.rx_is_lockedtodata (rx_is_lockedtodata),
// Clock and Reset
.clock (phy_mgmt_clk),
.reset (phy_mgmt_clk_reset),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// TX and RX Resets and Status
.tx_digitalreset (tx_digitalreset),
.tx_analogreset (tx_analogreset),
.tx_ready (tx_ready),
.rx_digitalreset (rx_digitalreset),
.rx_analogreset (rx_analogreset),
.rx_ready (rx_ready),
// PLL Powerdown
.pll_powerdown (pll_powerdown)
//----------------------------------------------------------------------
);
assign tx_pma_parallel_data = {tx_parallel_data3,tx_parallel_data2,tx_parallel_data1,tx_parallel_data0};
assign rx_parallel_data3 = rx_pma_parallel_data[159:120];
assign rx_parallel_data2 = rx_pma_parallel_data[119:80];
assign rx_parallel_data1 = rx_pma_parallel_data[79:40];
assign rx_parallel_data0 = rx_pma_parallel_data[39:0];
assign tx_clkout = tx_pma_clkout;
assign rx_clkout = rx_pma_clkout;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Shift CK/Address/Commands/Controls
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter DQS_CNT_WIDTH = 3,
parameter N_CTL_LANES = 3,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
// Start only after PO_CIRC_BUF_DELAY decremented
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_stg2_f_incdec,
output reg po_en_stg2_f,
output reg po_stg2_c_incdec,
output reg po_en_stg2_c,
// Completed delaying CK/Address/Commands/Controls
output po_ck_addr_cmd_delay_done
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
tCK > 2500 ? 2 : 1);
localparam integer PHASER_TAP_RES = ((tCK/2)/64);
// Determine whether 300 ps or 350 ps delay required
localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
// Determine the number of Phaser_Out taps required to delay by 300 ps
// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// Increment control byte lanes
localparam TAP_CNT = 0;
//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
//Decrement control byte lanes
localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
reg delay_dec_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
(* keep = "true", max_fanout = 10 *) reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
reg [5:0] delay_cnt_r;
reg [5:0] delaydec_cnt_r;
reg po_cnt_inc;
reg po_cnt_dec;
reg [3:0] wait_cnt_r;
assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
always @(posedge clk) begin
if (rst || po_cnt_dec || po_cnt_inc)
wait_cnt_r <= #TCQ 'd8;
else if (cmd_delay_start && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
po_cnt_inc <= #TCQ 1'b0;
else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_inc <= #TCQ 1'b1;
else
po_cnt_inc <= #TCQ 1'b0;
end
//Tap decrement
always @(posedge clk) begin
if (rst || (delaydec_cnt_r == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end else begin
if (po_cnt_dec) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b1;
end else begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end
if (po_cnt_inc) begin
po_stg2_c_incdec <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b1;
end else begin
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end
end
end
// delay counter to count 2 cycles
// Increment coarse taps by 2 for all control byte lanes
// to mitigate late writes
always @(posedge clk) begin
// load delay counter with init value
if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
delay_cnt_r <= #TCQ 'd0;
else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delay_cnt_r <= #TCQ 'd1;
else if (po_cnt_inc && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// delay counter to count TAP_DEC cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_DEC
if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delaydec_cnt_r <= #TCQ TAP_DEC;
else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// All control lanes have decremented to 31 fine taps from 46
always @(posedge clk) begin
if (rst || ~cmd_delay_start) begin
delay_dec_done <= #TCQ 1'b0;
end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
delay_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_dec_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[100009]; map<int, int> mp; int main() { int n, m, x, y, index = 1; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &x, &y); if (mp[x] == 0) { mp[x] = index; v[index++].push_back(y); } else v[mp[x]].push_back(y); if (mp[y] == 0) { mp[y] = index; v[index++].push_back(x); } else v[mp[y]].push_back(x); } int bus_out = 0, bus_in = 0, ring = 0, s, cen_c = 0, cen_out = 0; for (int i = 1; i < index; i++) { s = v[i].size(); if (s == 1) { cen_out++; bus_out++; } else if (s == 2) { bus_in++; ring++; } else { cen_c++; } } if (n < m) { printf( unknown topology n ); } else if (n - 1 == m && bus_out == 2 && bus_in == n - 2) { printf( bus topology n ); } else if (ring == n && n == m) { printf( ring topology n ); } else if (n == m + 1 && cen_c == 1 && cen_out == n - 1) { printf( star topology n ); } else { printf( unknown topology n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30) - 1; const long long linf = (1ll << 62) - 1; const int N = 200; const int M = 1e9 + 7; const long long M2 = 1ll * M * M; int n; long long a[N]; int mat[N][N]; int result[N][N]; void multiply(int a[N][N], int b[N][N]) { static int c[N][N]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { long long result = 0; for (int z = 0; z < n; z++) { result += 1ll * a[i][z] * b[z][j]; if (result >= M2) { result -= M2; } } c[i][j] = result % M; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { a[i][j] = c[i][j]; } } } void power(long long n) { for (int i = 0; i < ::n; i++) { result[i][i] = 1; } for (; n > 0; n >>= 1) { if (n & 1) { multiply(result, mat); } multiply(mat, mat); } } int main() { long long k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { long long x = a[i] ^ a[j]; int cnt = 0; while (x > 0) { cnt += x & 1; x /= 2; } if (cnt % 3 == 0) { mat[i][j]++; } } } power(k - 1); int answer = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { answer += result[i][j]; if (answer >= M) { answer -= M; } } } cout << answer << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_1_V
`define SKY130_FD_SC_LP__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int a[100010], b[100010]; map<string, bool> mark; bool word(char a) { if (a >= a and a <= z ) return true; if (a >= A and a <= Z ) return true; return false; } int main() { int n; cin >> n; string a; cin >> a; int ind = 0; int inside = 0; int ans1 = 0; int ans2 = 0; while (ind < n) { if (a[ind] == _ ) { ind++; continue; } if (a[ind] == ( ) { inside++; ind++; continue; } if (a[ind] == ) ) { inside--; ind++; continue; } int leng = 0; string cur = ; while (word(a[ind]) == true) { if (ind == n - 1) { cur += a[ind]; if (inside > 0) { ans2++; } if (inside == 0) { ans1 = max(ans1, int(cur.size())); } ind++; break; } cur += a[ind]; ind++; } if (ind == n) { break; } if (inside > 0) { ans2++; } if (inside == 0) { ans1 = max(ans1, int(cur.size())); } } cout << ans1 << << ans2 << endl; }
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long arr[200005]; pair<long long, long long> pt[200005]; int main() { long long n, x, y, newX, newY, cnt = 0, ansX, ansY, val = 0; map<pair<long long, long long>, long long> mp1; cin >> n >> x >> y; for (int i = 0; i < n; i++) { cin >> pt[i].first >> pt[i].second; } newX = x + 1, newY = y; for (int i = 0; i < n; i++) { if (newX >= min(pt[i].first, x) and newX <= max(pt[i].first, x)) { if (newY >= min(pt[i].second, y) and newY <= max(pt[i].second, y)) cnt++; } } mp1[{newX, newY}] = cnt; cnt = 0; newX = x - 1, newY = y; for (int i = 0; i < n; i++) { if (newX >= min(pt[i].first, x) and newX <= max(pt[i].first, x)) { if (newY >= min(pt[i].second, y) and newY <= max(pt[i].second, y)) cnt++; } } mp1[{newX, newY}] = cnt; cnt = 0; newX = x, newY = y + 1; for (int i = 0; i < n; i++) { if (newX >= min(pt[i].first, x) and newX <= max(pt[i].first, x)) { if (newY >= min(pt[i].second, y) and newY <= max(pt[i].second, y)) cnt++; } } mp1[{newX, newY}] = cnt; cnt = 0; newX = x, newY = y - 1; for (int i = 0; i < n; i++) { if (newX >= min(pt[i].first, x) and newX <= max(pt[i].first, x)) { if (newY >= min(pt[i].second, y) and newY <= max(pt[i].second, y)) cnt++; } } mp1[{newX, newY}] = cnt; for (auto it = mp1.begin(); it != mp1.end(); it++) { if (it->second > val) { val = it->second; ansX = it->first.first; ansY = it->first.second; } } cout << val << endl; cout << ansX << << ansY << endl; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate deassign reg_ident;
module main ;
reg [31:0] value;
reg [1:0] control;
reg clock;
reg error;
always @(posedge clock)
value = 3;
always @(control)
if(control == 1)
assign value = 1;
else
if(control == 2)
assign value = 2;
else
deassign value ;
// Setup a clock generator.
always begin
#2;
clock = ~clock;
end
initial
begin
clock = 0;
error = 0;
# 3;
if(value != 3)
begin
$display("FAILED - deassign3.4A - procedural assignment(1)");
error = 1;
end
# 2;
control = 1;
# 1;
if(value != 1)
begin
$display("FAILED - deassign3.4A - procedural assignment(2)");
error = 1;
end
# 1 ;
control = 2;
# 1 ;
if(value != 2)
begin
$display("FAILED - deassign3.4A - procedural assignment(3)");
error = 1;
end
#1 ;
control = 0;
# 10;
if(value != 3)
begin
$display("FAILED - deassign3.4A - procedural assignment(4)");
error = 1;
end
if(error == 0) $display ("PASSED");
$finish ;
end
endmodule
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module ac97_graycounter
#(parameter COUNTER_WIDTH = 2)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
#include <iostream> #include <algorithm> #include <cassert> #include <fstream> using ll = long long; const int maxn = 5007; ll t, n, S[maxn], ans[maxn]; ll res; int main(int argc, char *argv[]) { std::ios::sync_with_stdio(false); std::cin.tie(0); std::cin >> t; while (t--) { res = 0; std::cin >> n; for (ll i = 0; i < n; i++) { std::cin >> S[i]; ans[i] = 0; } for (ll i = 0; i < n; i++) { ll temp = ans[i]; if (temp < S[i]-1){ res += S[i] - 1 - temp; temp += S[i] - 1 - temp; } ans[i+1] += temp - S[i] + 1; if (i+2 < n) { for (int j = i+2; j < std::min(n,i+S[i]+1); j++) { ans[j]++; } } } std::cout << res << n ; } }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire clk_200mhz_p,
input wire clk_200mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire rst_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_200mhz_ibufgds_inst(
.I(clk_200mhz_p),
.IB(clk_200mhz_n),
.O(clk_200mhz_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_200mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_1_V
`define SKY130_FD_SC_HS__EDFXTP_1_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog wrapper for edfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxtp_1 (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxtp_1 (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_1_V
|
#include <bits/stdc++.h> using namespace std; struct Player { string name; long int points; map<int, int> places; }; Player compSecond(Player a, Player b) { if (a.points > b.points) { return a; } else if (a.points < b.points) { return b; } for (int i = 1; i < 70; i++) { if (a.places[i] > b.places[i]) { return a; } if (a.places[i] < b.places[i]) { return b; } } } Player compFirst(Player a, Player b) { if (a.places[1] > b.places[1]) { return a; } else if (a.places[1] < b.places[1]) { return b; } if (a.points > b.points) { return a; } else if (a.points < b.points) { return b; } for (int i = 2; i < 70; i++) { if (a.places[i] > b.places[i]) { return a; } if (a.places[i] < b.places[i]) { return b; } } } map<string, Player> parts; vector<int> points = {25, 18, 15, 12, 10, 8, 6, 4, 2, 1}; int main() { int n; cin >> n; set<Player> st; for (int i = 0; i < n; i++) { int players; cin >> players; for (int j = 1; j <= players; j++) { string name; cin >> name; parts[name].points += (j <= 10) ? points[j - 1] : 0; parts[name].places[j]++; parts[name].name = name; } } Player min; Player first; Player second; first.points = 0; second.points = 0; for (auto i : parts) { first = compSecond(i.second, first); second = compFirst(i.second, second); } cout << first.name << endl << second.name << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, m = 0, sum = 0; cin >> n; string s; getline(cin, s); getline(cin, s); for (int i = 0; i < n; i++) { if (s[i] == ) { m = max(m, sum); sum = 0; } if (s[i] >= A && s[i] <= Z ) sum++; } m = max(m, sum); cout << m; }
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Arguments id {A} x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Local Open Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Arguments prod_curry {A B C} f p.
Arguments prod_uncurry {A B C} f x y.
|
#include <bits/stdc++.h> using namespace std; int t, n, m; int a[10][10]; int main() { cin >> t; while (t--) { cin >> n >> m; int ok = 0; for (int i = 1; i <= n; i++) { cin >> a[1][1] >> a[1][2] >> a[2][1] >> a[2][2]; if (a[1][2] == a[2][1]) { ok = 1; } } if (m % 2) ok = 0; if (ok) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 998244353; struct mat { long long a[2][2]; }; mat mul(mat a, mat b) { mat c; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { c.a[i][j] = 0; for (int k = 0; k < 2; k++) c.a[i][j] += a.a[i][k] * b.a[k][j]; c.a[i][j] %= N; } } return c; } mat make_mat(long long x, long long y) { mat ret; ret.a[0][0] = x; ret.a[1][0] = y; ret.a[0][1] = 1; ret.a[1][1] = 0; return ret; } mat val[2000005]; void pushup(int x) { val[x] = mul(val[(x << 1)], val[((x << 1) | 1)]); } void modify(int x, int l, int r, int pos, mat v) { if (l == r) { val[x] = v; return; } int mid = (l + r) >> 1; if (pos <= mid) modify((x << 1), l, mid, pos, v); if (pos > mid) modify(((x << 1) | 1), mid + 1, r, pos, v); pushup(x); } int n, m, x, y, d[500005]; string s; int main() { ios::sync_with_stdio(false); cin >> n >> m; cin >> s; reverse(s.begin(), s.end()); s = + s; for (int i = 1; i <= n; i++) { d[i] = s[i] - 0 ; modify(1, 1, n, i, make_mat(d[i] + 1, (i == 1 ? 0 : (d[i] == 1) * (9 - d[i - 1])))); } while (m--) { cin >> x >> y; x = n - x + 1; d[x] = y; modify(1, 1, n, x, make_mat(d[x] + 1, (x == 1 ? 0 : (d[x] == 1) * (9 - d[x - 1])))); if (x < n) modify(1, 1, n, x + 1, make_mat(d[x + 1] + 1, (d[x + 1] == 1) * (9 - d[x]))); cout << val[1].a[0][0] << n ; } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:58:36 04/14/2015
// Design Name: main
// Module Name: E:/Adventure/Adventure/MainTest.v
// Project Name: Adventure
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module MainTest;
// Inputs
reg clk_50MHz;
reg [3:0] SWITCH;
reg [3:0] BUTTON;
reg xin;
reg yin;
// Outputs
wire vs_vga;
wire hs_vga;
wire [2:0] RED;
wire [2:0] GREEN;
wire [1:0] BLUE;
// Instantiate the Unit Under Test (UUT)
main uut (
.clk_50MHz(clk_50MHz),
.vs_vga(xin),
.hs_vga(yin),
.RED(RED),
.GREEN(GREEN),
.BLUE(BLUE),
.SWITCH(SWITCH),
.BUTTON(BUTTON)
);
initial begin
clk_50MHz = 0;
forever
#5 clk_50MHz = ~clk_50MHz;
xin = ~xin;
yin = ~yin;
end
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
//640x480
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
end
endmodule
|
`timescale 1ns/1ns
// $ iverilog fp16bmul.v fp16bmul_test.v
module FP16BMul_Test;
reg clk, rst;
reg [15:0] s0_arg_0;
reg [15:0] s0_arg_1;
wire s0_ret_0;
wire [7:0] s0_ret_1;
wire [7:0] s0_ret_2;
wire [8:0] s0_ret_3;
reg s1_arg_0;
reg [7:0] s1_arg_1;
reg [7:0] s1_arg_2;
reg [8:0] s1_arg_3;
wire [15:0] s1_ret_0;
reg xs;
reg [7:0] xe;
reg [6:0] xf;
reg ys;
reg [7:0] ye;
reg [6:0] yf;
wire rs;
wire [7:0] re;
wire [6:0] rf;
assign rs = s1_ret_0[15:15];
assign re = s1_ret_0[14:7];
assign rf = s1_ret_0[6:0];
FP16BMulS0Of2
inst_0(.clk(clk), .rst(rst),
.arg_0(s0_arg_0), .arg_1(s0_arg_1),
.ret_0(s0_ret_0), .ret_1(s0_ret_1), .ret_2(s0_ret_2), .ret_3(s0_ret_3));
FP16BMulS1Of2
inst_1(.clk(clk), .rst(rst),
.arg_0(s1_arg_0), .arg_1(s1_arg_1), .arg_2(s1_arg_2), .arg_3(s1_arg_3),
.ret_0(s1_ret_0));
always @(s0_ret_0 or s0_ret_1 or s0_ret_2 or s0_ret_3) begin
s1_arg_0 <= s0_ret_0;
s1_arg_1 <= s0_ret_1;
s1_arg_2 <= s0_ret_2;
s1_arg_3 <= s0_ret_3;
$display("S0: %d %d %d %d", s0_ret_0, s0_ret_1, s0_ret_2, s0_ret_3);
end
always @(xs or xe or xf or ys or ye or yf) begin
s0_arg_0 = {xs, xe, xf};
s0_arg_1 = {ys, ye, yf};
end
initial begin
clk <= 0;
rst <= 1;
#105
rst <= 0;
// 0 * 0
s0_arg_0 <= 0;
s0_arg_1 <= 0;
#1
$display("0.0*0.0= %d %s", s1_ret_0, (s1_ret_0 == 0) ? "OK" : "FAIL");
// 1.0 * 1.0
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("1.0*1.0= %d %s", s1_ret_0, (rs == 0 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 1.5 * 1.5
xs <= 0; xe <= 127; xf <= 64;
ys <= 0; ye <= 127; yf <= 64;
#1
$display("1.5*1.5= %d %s", s1_ret_0, (rs == 0 && re == 128 && rf == 16) ? "OK" : "FAIL");
// 1.25 * 1.25
xs <= 0; xe <= 127; xf <= 32;
ys <= 0; ye <= 127; yf <= 32;
#1
$display("1.25*1.25= %d %s", s1_ret_0, (rs == 0 && re == 127 && rf == 72) ? "OK" : "FAIL");
// 0.75 * 0.75
xs <= 0; xe <= 126; xf <= 64;
ys <= 0; ye <= 126; yf <= 64;
#1
$display("0.75*0.75= %d %s", s1_ret_0, (rs == 0 && re == 126 && rf == 16) ? "OK" : "FAIL");
$display("%d %d %d", rs, re, rf);
// 2^-14 * 0.5
xs <= 0; xe <= 1; xf <= 0;
ys <= 0; ye <= 14; yf <= 0;
#1
$display("2^-14*0.5= %d %s", s1_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// 2^192 * 2^192
xs <= 0; xe <= 192; xf <= 0;
ys <= 0; ye <= 192; yf <= 0;
#1
$display("2^192*2^192= %d %s", s1_ret_0, (rs == 0 && re == 255 && rf == 0) ? "OK" : "FAIL");
// Use this line to debug a specific case.
$display("%d %d %d", rs, re, rf);
#10000
$display("test done");
$finish;
end
endmodule // FP16BMul_Test
|
/*
* LatticeMico32
* JTAG Test Access Port For Xilinx Sparan-6 Devices
*
* Copyright (C) 2010 Michael Walle
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module jtag_tap(
output tck,
output tdi,
input tdo,
output shift,
output update,
output reset
);
wire g_shift;
wire g_update;
wire sel;
assign shift = g_shift & sel;
assign update = g_update & sel;
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(),
.DRCK(tck),
.RESET(reset),
.RUNTEST(),
.SEL(sel),
.SHIFT(g_shift),
.TCK(),
.TDI(tdi),
.TMS(),
.UPDATE(g_update),
.TDO(tdo)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_4_V
`define SKY130_FD_SC_LS__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { char a[1000010], b[1000010]; while (scanf( %s%s , &a, &b) != EOF) { int len1 = strlen(a); int len2 = strlen(b); int ans = 0; if (len1 != len2) { ans = 1; } else { if (len1 == 1) { if (a[0] != b[0]) ans = 1; else ans = 0; } else { if (strcmp(a, b) == 0) ans = 0; else { int j1 = 0, j2 = 0; for (int i = 0; i < len1; i++) if (a[i] == 1 ) j1 = 1; for (int i = 0; i < len1; i++) if (b[i] == 1 ) j2 = 1; if (j1 && j2) ans = 0; else ans = 1; } } } if (!ans) printf( YES n ); else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc; cin >> tc; while (tc--) { long long int n, k; cin >> n >> k; long long int a[n], m = INT_MIN; for (long long int i = 0; i < n; i++) { cin >> a[i]; m = max(m, a[i]); } long long int ans[n]; if (k & 1) { for (long long int i = 0; i < n; i++) cout << m - a[i] << ; } else { long long int d = INT_MIN; for (long long int i = 0; i < n; i++) { a[i] = m - a[i]; d = max(d, a[i]); } for (long long int i = 0; i < n; i++) cout << d - a[i] << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int count1(int x) { int ans = 0; while (x) { ans += x & 1; x >>= 1; } return ans; } int main() { int n, p; cin >> n >> p; for (int x = 0; x * (p + 1) <= n; x++) if (count1(n - x * p) <= x) { cout << x; return 0; } cout << -1; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; bool operator<(const complex<double>& a, const complex<double>& b) { if (fabs(a.imag() - b.imag()) > EPS) return a.imag() < b.imag(); return a.real() + EPS < b.real(); } class cmp { public: bool operator()(const complex<double>& a, const complex<double>& b) { return a < b; } }; bool pointOnLeft(const complex<double>& p, const complex<double>& p1, const complex<double>& p2) { return imag(conj(((p2) - (p1))) * (((p) - (p1)))) > EPS; } class cmpHull { public: complex<double> about, nex; cmpHull(const complex<double>& about, const complex<double>& nex) : about(about), nex(nex) {} bool operator()(const complex<double>& a, const complex<double>& b) { double crs = imag(conj(((a) - (about))) * (((b) - (about)))); if (fabs(crs) < EPS) { if (fabs(imag(conj(((nex) - (about))) * (((a) - (about))))) < EPS) return a < b; return b < a; } return crs > 0; } }; void sortAntiClockwise(vector<complex<double> >& polygon) { int about = 0; for (int c = 1; c < (int)polygon.size(); c++) if (polygon[c] < polygon[about]) about = c; swap(polygon[about], polygon[0]); sort(polygon.begin() + 1, polygon.end(), cmpHull(polygon[0], polygon[0])); sort(polygon.begin() + 2, polygon.end(), cmpHull(polygon[0], polygon[1])); return; } vector<complex<double> > convexHull(vector<complex<double> >& polygon) { sortAntiClockwise(polygon); vector<complex<double> > hull; int sz = 0; for (int i = 0; i < (int)polygon.size(); i++) { while (sz >= 2 && pointOnLeft(polygon[i], hull[sz - 1], hull[sz - 2])) { hull.pop_back(); sz--; } sz++; hull.push_back(polygon[i]); } return hull; } vector<complex<double> > shift(const vector<complex<double> >& A, int pivot) { vector<complex<double> > ret; for (int c = pivot; c < pivot + (int)A.size(); c++) ret.push_back(A[c % A.size()]); return ret; } vector<complex<double> > A, B, all; int n, m; int main() { set<complex<double>, cmp> ss; int c, c2; scanf( %d , &n); int x, y; for (c = 0; c < n; c++) { scanf( %d%d , &x, &y); A.push_back(complex<double>(x, y)); all.push_back(complex<double>(x, y)); ss.insert(complex<double>(x, y)); } scanf( %d , &m); for (c = 0; c < m; c++) { scanf( %d%d , &x, &y); B.push_back(complex<double>(x, y)); all.push_back(complex<double>(x, y)); ss.insert(complex<double>(x, y)); } if (ss.size() < all.size()) { printf( NO n ); return 0; } reverse(A.begin(), A.end()); reverse(B.begin(), B.end()); int pivot = 0; for (c = 1; c < (int)A.size(); c++) if (A[c] < A[pivot]) pivot = c; A = shift(A, pivot); vector<complex<double> > hull = convexHull(all); if (hull.size() != A.size()) { printf( NO n ); return 0; } bool yes = true; for (c = 0; c < (int)hull.size(); c++) if (hull[c] < A[c] || A[c] < hull[c]) yes = false; if (yes) printf( YES n ); else printf( NO n ); }
|
`timescale 1ns / 1ps
// pwm_ctl.v ver 1.0
// Kazushi Yamashina
//
//
// para_in <= 0 ~ 19999
// -Interval of asserting "en_out" will change
// depending on the value of the "para_in".
// -The more you increase the value the interval will increase.
//
// dir_in <= 1: positive rotate, 0: negative rotate
module pwm_ctl(
input clk,
input rst,
input [14:0] para_in,
input [0:0] dir_in,
output [0:0] dir_out,
output [0:0] en_out
);
// //copy this instance to top module
//pwm_ctl pwm_ctl
//(
//.clk(bus_clk),
// .rst(rst),
// .para_in(para_in),
// .dir_out(dir_out),
// .en_out(en_out)
//);
parameter MAX = 19999;
reg dir;
reg dir_;
reg en;
reg [14:0] in_;
reg [31:0] counter;
wire [31:0] divflag;
reg [31:0] PWMctl_clk;
initial PWMctl_clk = MAX;
initial in_ = MAX;
assign divflag = PWMctl_clk - in_;
assign dir_out = dir;
assign en_out = en;
always @(posedge clk)begin
if(rst)begin
in_ <= 19999;
dir_ <= 0;
end
else if(0 < para_in && para_in < PWMctl_clk)begin
in_ <= para_in;
dir_ <= dir_in;
end
else
in_ <= MAX;
end
always @(posedge clk)begin
if(rst)begin
dir <= 0;
en <= 0;
end
else if(divflag > counter)begin
dir <= dir_;
en <= 1;
end
else begin
en <= 0;
end
end
always @(posedge clk)begin
if(rst)begin
counter <= 0;
end
else if(PWMctl_clk == counter)
counter <= 0;
else
counter <= counter + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int blacks(int *pos, int n); int whites(int *pos, int n); int main() { int n; cin >> n; int board[100]; for (int i = 0; i < n; i++) { board[i] = 0; } for (int i = 0; i < n / 2; i++) { int temp; cin >> temp; board[temp - 1] = 1; } cout << min(blacks(board, n), whites(board, n)); } int blacks(int *pos, int n) { int i = 0; int label = 0; int result = 0; while (i < n) { if (pos[i] == 1) { result += abs(i - label); label += 2; } i++; } return result; } int whites(int *pos, int n) { int i = 0; int label = 1; int result = 0; while (i < n) { if (pos[i] == 1) { result += abs(i - label); label += 2; } i++; } return result; }
|
#include <bits/stdc++.h> using namespace std; int d[4][2] = {{0, -1}, {1, 0}, {0, 1}, {-1, 0}}; int ans, k = 0; int egg[1000000]; int n, m, vis[1050][1050]{0}, ma[1050][1050]; void dfs(int x, int y) { for (int i = 0; i < 4; i++) { int xx = x + d[i][0]; int yy = y + d[i][1]; if ((ma[x][y] >> i) % 2 == 0 && vis[xx][yy] == 0) { vis[xx][yy] = 1; dfs(xx, yy); ans++; } } } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> ma[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (!vis[i][j]) { ans = 1; vis[i][j] = 1; dfs(i, j); egg[++k] = ans; } } } sort(egg + 1, egg + k + 1); for (int i = k; i >= 1; i--) { cout << egg[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool sortbysecdesc(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.first == b.first) return a.second > b.second; else return 0; } const long long N = 100010; bool prime[N]; void SieveOfEratosthenes() { long long n = N - 3; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } } long long i, j; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); SieveOfEratosthenes(); long long t; cin >> t; while (t--) { long long n; cin >> n; if (n == 1 || n == 2 || n == 3 || n == 5 || n == 7 || n == 11) { cout << -1 << n ; } else if (n % 4 == 0) { cout << n / 4 << n ; } else if (n == 6) { cout << 1 << n ; } else { long long temp = n / 4; long long x = n - temp * 4; if (x == 1) { cout << 1 + (n - 9) / 4 << n ; } else if (x == 2) { cout << 1 + (n - 6) / 4 << n ; } else if (x == 3) { cout << 2 + (n - 15) / 4 << n ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { puts( INTERCAL ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; char arr[108]; int main() { int i, j, k, t, n, m, a, b, c, x, y, z; cin >> n; int flag = 0; for (i = 1; i <= n; i++) { cin >> arr[i]; } int gap, cnt = 0; for (i = 1; i <= n; i++) { if (arr[i] == * ) { for (j = i + 1; j <= i + n / 4; j++) { if (arr[j] == * ) { cnt = 0; gap = j - i; for (k = j; k <= n; k += gap) { if (arr[k] == * ) { cnt++; if (cnt >= 4) { flag = 1; break; } } else break; } } if (flag == 1) break; } if (flag == 1) break; } } if (flag == 1) cout << yes ; else cout << no ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> s[222222], ss[222222]; int n, m, cnt, cnt2, h; int up[222222][22], fa[222222], deep[211111], q[211111], dfn[211111], low[211111]; void tarjan(int x) { int c, i, y; dfn[x] = low[x] = ++cnt; q[h] = x; h++; c = s[x].size(); for (i = 0; i < c; i++) { y = s[x][i]; if (dfn[y] == 0) { tarjan(y); low[x] = min(low[x], low[y]); if (low[y] >= dfn[x]) { cnt2++; while (h > 0) { h--; ss[cnt2].push_back(q[h]); ss[q[h]].push_back(cnt2); if (q[h] == y) break; } ss[cnt2].push_back(x); ss[x].push_back(cnt2); } } else low[x] = min(low[x], dfn[y]); } } void make_yfs() { int i; cnt = 0, h = 0, cnt2 = n; tarjan(1); } void dfs(int x) { int c, i, y; c = ss[x].size(); for (i = 0; i < c; i++) { y = ss[x][i]; if (fa[x] == y) continue; fa[y] = up[y][0] = x; deep[y] = deep[x] + 1; dfs(y); } } int lca(int x, int y) { int tmp = 20; if (deep[x] < deep[y]) swap(x, y); while (1) { if ((1 << tmp) <= deep[x] - deep[y]) x = up[x][tmp]; tmp--; if (tmp < 0) break; } if (x == y) return x; tmp = 20; while (1) { if (up[x][tmp] != up[y][tmp]) x = up[x][tmp], y = up[y][tmp]; tmp--; if (tmp < 0) break; } return fa[x]; } int getdis(int x, int y) { int L; L = lca(x, y); return deep[x] - deep[L] + deep[y] - deep[L]; } int main() { int i, m, x, y, q, ans; scanf( %d%d%d , &n, &m, &q); for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); s[x].push_back(y); s[y].push_back(x); } make_yfs(); dfs(1); for (int j = 1; j <= 20; j++) for (i = 1; i <= cnt2; i++) up[i][j] = up[up[i][j - 1]][j - 1]; while (q--) { scanf( %d%d , &x, &y); ans = getdis(x, y) / 2; printf( %d n , ans); } return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 6,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_dadd_3_full_dsp_64 feedforward_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1005; int N, K; long long L[MAXN], R[MAXN]; double dp[MAXN][MAXN]; double calc(long long l, long long r) { long long ret = 0, cur = 1; for (; cur <= r; cur *= 10) { if (cur == 1e18) { ret++; break; } if (cur * 10 <= l) continue; if (cur <= l && cur * 10 > l) { int a = l / cur; if (a == 1) { if (cur * 10 <= r) ret += cur * 2 - l; else { int b = r / cur; if (b == 1) ret += r - l + 1; else ret += cur * 2 - l; } } } else if (cur * 10 > r) { int b = r / cur; if (b == 1) ret += r - cur + 1; else ret += cur; } else ret += cur; } return double(ret) / (r - l + 1); } int main() { if (fopen( input.txt , r )) freopen( input.txt , r , stdin); cin >> N; for (int i = 0; i < N; i++) cin >> L[i] >> R[i]; cin >> K; K = ceil(K / 100. * N); dp[0][0] = 1; for (int i = 0; i < N; i++) { double p = calc(L[i], R[i]); for (int j = 0; j < N; j++) { dp[i + 1][j + 1] += dp[i][j] * p; dp[i + 1][j] += dp[i][j] * (1 - p); } } double ans = 0; for (int k = K; k <= N; k++) ans += dp[N][k]; cout << fixed << setprecision(10) << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; int vis[10005]; int main() { int n; scanf( %d , &n); int maxn = -1; for (int i = 1; i <= n; i++) { int tmp; scanf( %d , &tmp); vis[tmp]++; maxn = max(maxn, tmp); } long long ans1 = -1, ans2 = -1; for (int i = 1; i <= maxn; i++) { if (vis[i] != 0) { if (i > ans1) { ans1 = i; } } } for (int i = 1; i <= maxn; i++) { if (vis[i] == 2 || (ans1 % i != 0 && vis[i] == 1)) { if (i > ans2) { ans2 = i; } } } printf( %lld %lld n , ans1, ans2); }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, m; vector<long long> b(N, 0); void add(int x, int k) { while (x < N) { b[x] += k; x += x & -x; } } long long sum(int x) { long long ret = 0; while (x) { ret += b[x]; x -= x & -x; } return ret; } void add(int l, int r, int k) { if (l > r) return; add(l, k); add(r + 1, -k); } int main() { scanf( %d%d , &n, &m); vector<int> x(m + 1, 0); for (int i = 0, y; i < m; i++) { scanf( %d , &x[i]); } for (int i = 1; i < m; i++) { long long sum = 0; int u = x[i - 1]; int v = x[i]; if (u == v) continue; if (u < v) swap(u, v); add(1, v - 1, u - v); add(u + 1, n, u - v); add(v + 1, u - 1, u - v - 1); add(v, v, u - 1); add(u, u, v); } for (int i = 1; i <= n; i++) { printf( %lld%c , sum(i), n [i == n]); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, m, i, j, k, x, y, z, t; long long hh, mm, h, d, c, N; cin >> hh >> mm; cin >> h >> d >> c >> N; if (hh >= 20) { double cc = 0.8 * c; k = (h + N - 1) / N; double ans = 1.0 * k * cc; cout << fixed << setprecision(10) << ans << endl; return 0; } double ans1, ans2; k = (h + N - 1) / N; ans1 = 1.0 * k * c; x = (60 - mm) + (20 - hh - 1) * 60; h += x * d; double cc = 0.8 * c; k = (h + N - 1) / N; ans2 = 1.0 * k * cc; cout << fixed << setprecision(10) << min(ans1, ans2) << endl; }
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#include <bits/stdc++.h> using namespace std; const int Max = 1e3, Max_Q = 1e4; const int fx[8] = {0, 0, 1, 1, 1, -1, -1, -1}; const int fy[8] = {1, -1, 0, 1, -1, 0, 1, -1}; int h, w, Q, cnt, s, t, Top, siz, q[Max + 5], stk[Max + 5], Id[Max + 5][Max + 5], fa[Max * Max + 5], vis[Max * Max + 5]; char S[Max + 5][Max + 5]; map<int, int> Tag[Max * Max + 5]; struct kk { int x, y; } A[20]; inline int Get(int x) { return x == fa[x] ? x : fa[x] = Get(fa[x]); } inline int GET(int x) { return x == fa[x] ? x : GET(fa[x]); } int main() { scanf( %d%d%d , &h, &w, &Q); for (int i = 1; i <= h; i++) scanf( %s , S[i] + 1); for (int i = 1; i <= h; i++) for (int j = 1; j <= w; j++) Id[i][j] = ++cnt; s = ++cnt, t = ++cnt; for (int i = 1; i <= w; i++) Id[0][i] = s, Id[h + 1][i] = t; for (int i = 1; i <= h; i++) Id[i][0] = t, Id[i][w + 1] = s; vis[s] = vis[t] = 1; for (int i = 1; i <= h; i++) for (int j = 1; j <= w; j++) vis[Id[i][j]] = S[i][j] == # ; for (int i = 1; i <= cnt; i++) fa[i] = i; for (int i = 1; i <= h; i++) for (int j = 1; j <= w; j++) if (vis[Id[i][j]]) for (int k = 0; k < 8; k++) if (vis[Id[i + fx[k]][j + fy[k]]]) fa[Get(Id[i][j])] = Get(Id[i + fx[k]][j + fy[k]]); int flg = 0; for (int i = 1; i <= h; i++) for (int j = 1; j <= w; j++) if ((i != 1 || j != 1) && (i != h || j != w)) for (int x = 0; x < 8; x++) if (vis[Id[i + fx[x]][j + fy[x]]]) for (int y = x + 1; y < 8; y++) if (vis[Id[i + fx[y]][j + fy[y]]]) { int Fx = Get(Id[i + fx[x]][j + fy[x]]); int Fy = Get(Id[i + fx[y]][j + fy[y]]); int Fs = Get(s), Ft = Get(t); if (min(Fx, Fy) == min(Fs, Ft) && max(Fx, Fy) == max(Fs, Ft)) flg = 1; Tag[Fx][Fy] = Tag[Fy][Fx] = 1; } if (flg == 1) { for (int i = 1; i <= Q; i++) puts( NO ); return 0; } for (int i = 1; i <= cnt; i++) fa[i] = Get(i); for (int T = 1; T <= Q; T++) { int K; scanf( %d , &K); Top = siz = flg = 0; q[++siz] = Get(s), q[++siz] = Get(t); for (int i = 1; i <= K; i++) { scanf( %d%d , &A[i].x, &A[i].y); vis[Id[A[i].x][A[i].y]] = 1; q[++siz] = Get(Id[A[i].x][A[i].y]); for (int j = 0; j < 8; j++) if (vis[Id[A[i].x + fx[j]][A[i].y + fy[j]]]) q[++siz] = Get(Id[A[i].x + fx[j]][A[i].y + fy[j]]); } for (int i = 1; i <= K; i++) for (int j = 0; j < 8; j++) if (vis[Id[A[i].x + fx[j]][A[i].y + fy[j]]]) stk[++Top] = GET(Id[A[i].x + fx[j]][A[i].y + fy[j]]), fa[stk[Top]] = GET(Id[A[i].x][A[i].y]); for (int i = 1; i <= K; i++) { for (int j = 0; j < 8; j++) if (!vis[Id[A[i].x + fx[j]][A[i].y + fy[j]]]) { int nx = A[i].x + fx[j], ny = A[i].y + fy[j]; if ((nx == 1 && ny == 1) || (nx == h && ny == w)) continue; for (int x = 0; x < 8; x++) if (vis[Id[nx + fx[x]][ny + fy[x]]]) for (int y = x + 1; y < 8; y++) if (vis[Id[nx + fx[y]][ny + fy[y]]]) { int Fx = GET(Id[nx + fx[x]][ny + fy[x]]), Fy = GET(Id[nx + fx[y]][ny + fy[y]]); int Fs = GET(s), Ft = GET(t); if (min(Fx, Fy) == min(Fs, Ft) && max(Fx, Fy) == max(Fs, Ft)) flg = 1; } } } sort(q + 1, q + siz + 1); siz = unique(q + 1, q + siz + 1) - q - 1; for (int i = 1; i <= siz; i++) if (GET(q[i]) == GET(s)) for (int j = 1; j <= siz; j++) if (GET(q[j]) == GET(t) && Tag[q[i]][q[j]]) flg = 1; flg ? puts( NO ) : puts( YES ); fflush(stdout); for (int i = 1; i <= Top; i++) fa[stk[i]] = stk[i]; for (int i = 1; i <= K; i++) vis[Id[A[i].x][A[i].y]] = 0; } return 0; }
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