text stringlengths 59 71.4k |
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#include <bits/stdc++.h> int main() { int n, A[50], B[1001], i, X, C[50], t = 0; scanf( %d , &n); for (i = 0; i <= 1000; i++) { B[i] = 0; } for (i = 0; i < n; i++) { scanf( %d , &A[i]); X = A[i]; B[X] += 1; } for (i = 0; i < n; i++) { X = A[i]; if (B[X] == 1) { C[t] = X; t++; } else { B[X] -= 1; } } printf( %d n , t); for (i = 0; i < t; i++) { if (i == t - 1) { printf( %d n , C[i]); } else { printf( %d , C[i]); } } return 0; } |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_dma # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
input pcie_rx_cmd_wr_en,
input [33:0] pcie_rx_cmd_wr_data,
output pcie_rx_cmd_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [P_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n
);
wire w_pcie_rx_cmd_rd_en;
wire [33:0] w_pcie_rx_cmd_rd_data;
wire w_pcie_rx_cmd_empty_n;
wire w_pcie_tag_alloc;
wire [7:0] w_pcie_alloc_tag;
wire [9:4] w_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_pcie_rx_fifo_full_n;
wire w_fifo_wr_en;
wire [8:0] w_fifo_wr_addr;
wire [127:0] w_fifo_wr_data;
wire [9:0] w_rear_full_addr;
wire [9:0] w_rear_addr;
pcie_rx_cmd_fifo
pcie_rx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_rx_cmd_wr_en),
.wr_data (pcie_rx_cmd_wr_data),
.full_n (pcie_rx_cmd_full_n),
.rd_en (w_pcie_rx_cmd_rd_en),
.rd_data (w_pcie_rx_cmd_rd_data),
.empty_n (w_pcie_rx_cmd_empty_n)
);
pcie_rx_fifo
pcie_rx_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_fifo_wr_en),
.wr_addr (w_fifo_wr_addr),
.wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr),
.alloc_len (w_pcie_tag_alloc_len),
.full_n (w_pcie_rx_fifo_full_n),
.rd_clk (dma_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_rx_fifo_rd_en),
.rd_data (pcie_rx_fifo_rd_data),
.free_en (pcie_rx_fifo_free_en),
.free_len (pcie_rx_fifo_free_len),
.empty_n (pcie_rx_fifo_empty_n)
);
pcie_rx_tag
pcie_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_dma_fifo_tag),
.cpld_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_fifo_tag_last (cpld_dma_fifo_tag_last),
.fifo_wr_en (w_fifo_wr_en),
.fifo_wr_addr (w_fifo_wr_addr),
.fifo_wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr)
);
pcie_rx_req # (
.P_PCIE_DATA_WIDTH (P_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_rx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_rd_en (w_pcie_rx_cmd_rd_en),
.pcie_rx_cmd_rd_data (w_pcie_rx_cmd_rd_data),
.pcie_rx_cmd_empty_n (w_pcie_rx_cmd_empty_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.pcie_rx_fifo_full_n (w_pcie_rx_fifo_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_0_V
`define SKY130_FD_SC_LP__DIODE_0_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_0 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_0 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_0_V
|
#include <bits/stdc++.h> using namespace std; long long n, i, ans, a[500001], f[2][1200001]; int main() { scanf( %lld , &n); f[0][0] = 1; for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); a[i] ^= a[i - 1]; ans += f[i % 2][a[i]]; f[i % 2][a[i]]++; } printf( %lld , ans); } |
//////////////////////////////////////////////////////////////////////////////////
// BRAMPopControl for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BRAM pop controller
// Module Name: BRAMPopControl
// File Name: BRAMPopControl.v
//
// Version: v1.0.0
//
// Description: Automatically pops next data from the BRAM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module BRAMPopControl
#
(
parameter BRAMAddressWidth = 8 ,
parameter DataWidth = 32
)
(
iClock ,
iReset ,
iAddressInput ,
iAddressValid ,
oDataOut ,
oDataValid ,
iDataReady ,
oMemReadAddress ,
iMemReadData ,
oMemDataReadSig
);
input iClock ;
input iReset ;
input [BRAMAddressWidth - 1:0] iAddressInput ;
input iAddressValid ;
output [DataWidth - 1:0] oDataOut ;
output oDataValid ;
input iDataReady ;
output [BRAMAddressWidth - 1:0] oMemReadAddress ;
input [DataWidth - 1:0] iMemReadData ;
output oMemDataReadSig ;
reg [BRAMAddressWidth - 1:0] rReadAddress ;
reg rValidSigOut ;
reg rValidSigNextOut;
assign oMemReadAddress = rReadAddress;
assign oMemDataReadSig = (!rValidSigOut || iDataReady);
always @ (posedge iClock)
if (iReset)
rReadAddress <= {(BRAMAddressWidth){1'b0}};
else
if (iAddressValid)
rReadAddress <= iAddressInput;
else if (oMemDataReadSig)
rReadAddress <= rReadAddress + 1'b1;
always @ (posedge iClock)
if (iReset || iAddressValid)
begin
rValidSigOut <= 1'b0;
rValidSigNextOut <= 1'b0;
end
else
begin
if (!rValidSigOut || iDataReady)
begin
rValidSigOut <= rValidSigNextOut;
rValidSigNextOut <= oMemDataReadSig;
end
end
assign oDataOut = iMemReadData;
assign oDataValid = rValidSigOut;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846264338327950288419716939937510582097494459230; const long long MOD = 1e9 + 7; const long long INF = 1e14; long long mpow(long long a, long long b, long long p = MOD) { a = a % p; long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % p; a = (a * a) % p; b = b >> 1; } return res % p; } const long long N = 4 * 100000; long long n, m, b[N], a[N], g[N], h[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i <= (int)(n); ++i) cin >> a[i], a[i] += a[i - 1], g[i] = 1e14; for (int i = 1; i <= (int)(m); ++i) cin >> b[i], b[i] += b[i - 1], h[i] = 1e14; for (int i = 1; i <= (int)(n); ++i) for (long long j = i; j <= n; j++) g[j - i + 1] = min(g[j - i + 1], a[j] - a[i - 1]); for (int i = 1; i <= (int)(m); ++i) for (long long j = i; j <= m; j++) h[j - i + 1] = min(h[j - i + 1], b[j] - b[i - 1]); long long x; cin >> x; long long ans = 0; for (int i = 1; i <= (int)(n); ++i) for (int j = 1; j <= (int)(m); ++j) { if (g[i] * h[j] <= x) { ans = max(ans, (long long)(i * j)); } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n, m, a, b; cin >> n >> m >> a >> b; a--; b--; vector<vector<int> > graph(n); for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; graph[u].push_back(v); graph[v].push_back(u); } int x = 0; vector<bool> vis(n); function<void(int)> dfs = [&](int u) { vis[u] = true; for (int v : graph[u]) { if (vis[v] || v == x) continue; dfs(v); } }; x = b; dfs(a); int cnta = count(vis.begin(), vis.end(), false) - 1; fill(vis.begin(), vis.end(), false); x = a; dfs(b); int cntb = count(vis.begin(), vis.end(), false) - 1; cout << (long long)cnta * cntb << n ; } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module wb_regfile_2clock
(input wb_clk_i,
input wb_rst_i,
input wb_stb_i,
input wb_we_i,
input [15:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output wb_ack_o,
input alt_clk,
input alt_rst,
output reg [31:0] reg00,
output reg [31:0] reg01,
output reg [31:0] reg02,
output reg [31:0] reg03,
output reg [31:0] reg04,
output reg [31:0] reg05,
output reg [31:0] reg06,
output reg [31:0] reg07
);
reg [15:0] addr_reg;
reg [3:0] sel_reg;
reg [31:0] dat_reg;
reg wr_ret1, wr_ret2, we_reg, stb_reg;
always @(posedge wb_clk_i)
if(wb_rst_i)
begin
addr_reg <= 0;
sel_reg <= 0;
dat_reg <= 0;
end
else if(wb_stb_i & wb_we_i)
begin
addr_reg <= wb_adr_i;
sel_reg <= wb_sel_i;
dat_reg <= wb_dat_i;
end
always @(posedge wb_clk_i)
if(wb_rst_i)
{we_reg,stb_reg} <= 2'b0;
else
{we_reg,stb_reg} <= {wb_we_i,wb_stb_i};
assign wb_ack_o = stb_reg;
always @(posedge alt_clk)
if(alt_rst)
{wr_ret2, wr_ret1} <= 2'b0;
else
{wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg};
always @(posedge alt_clk)
if(alt_rst)
begin
reg00 <= 0;
reg01 <= 0;
reg02 <= 0;
reg03 <= 0;
reg04 <= 0;
reg05 <= 0;
reg06 <= 0;
reg07 <= 0;
end // if (alt_rst)
else if(wr_ret2)
case(addr_reg[4:2])
3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg00[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg00[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}};
3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg01[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg01[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}};
3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg02[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg02[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}};
3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg03[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg03[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}};
3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg04[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg04[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}};
3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg05[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg05[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}};
3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg06[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg06[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}};
3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]},
{sel_reg[2] ? dat_reg[23:16] : reg07[23:16]},
{sel_reg[1] ? dat_reg[15:8] : reg07[15:8]},
{sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}};
endcase // case(addr_reg[2:0])
endmodule // wb_regfile_2clock
|
/*
This file was generated automatically by the Mojo IDE version B1.3.6.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
DATA_IN_SIZE = 30
*/
module fifo_2x_reducer_27 (
input rst,
input clk,
input clkx2,
input [29:0] data_in,
output reg [14:0] data_out
);
localparam DATA_IN_SIZE = 5'h1e;
wire [1-1:0] M_fifo_full;
wire [30-1:0] M_fifo_dout;
wire [1-1:0] M_fifo_empty;
reg [30-1:0] M_fifo_din;
reg [1-1:0] M_fifo_wput;
reg [1-1:0] M_fifo_rget;
async_fifo_39 fifo (
.wclk(clk),
.rclk(clkx2),
.wrst(rst),
.rrst(rst),
.din(M_fifo_din),
.wput(M_fifo_wput),
.rget(M_fifo_rget),
.full(M_fifo_full),
.dout(M_fifo_dout),
.empty(M_fifo_empty)
);
reg M_flag_d, M_flag_q = 1'h0;
reg [29:0] M_word_d, M_word_q = 1'h0;
always @* begin
M_flag_d = M_flag_q;
M_word_d = M_word_q;
M_fifo_din = data_in;
M_fifo_wput = 1'h1;
M_fifo_rget = 1'h0;
if (!M_flag_q && !M_fifo_empty) begin
M_fifo_rget = 1'h1;
M_flag_d = 1'h1;
M_word_d = M_fifo_dout;
end
if (M_flag_q) begin
M_flag_d = 1'h0;
end
data_out = !M_flag_q ? M_word_q[15+14-:15] : M_word_q[0+14-:15];
end
always @(posedge clkx2) begin
M_flag_q <= M_flag_d;
M_word_q <= M_word_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int a[100002]; int mini[100002][21]; vector<pair<int, int> > vp; int f(int l, int r, int m) { if (l == r) { for (int i = 0; i < a[l] - m; i++) { vp.push_back(make_pair(l, r)); } return a[l] - m; } int i = 0; for (i = 0;; i++) if (l + (1 << i) > r) break; int minIndex = -1; if (a[mini[l][i - 1]] < a[mini[r - (1 << (i - 1)) + 1][i - 1]]) { minIndex = mini[l][i - 1]; } else { minIndex = mini[r - (1 << (i - 1)) + 1][i - 1]; } for (int i = 0; i < a[minIndex] - m; i++) { vp.push_back(make_pair(l, r)); } if (minIndex == l) { return a[minIndex] - m + f(l + 1, r, a[minIndex]); } if (minIndex == r) { return a[minIndex] - m + f(l, r - 1, a[minIndex]); } else { return a[minIndex] - m + f(l, minIndex - 1, a[minIndex]) + f(minIndex + 1, r, a[minIndex]); } } int main() { cout << setprecision(9); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) mini[i][0] = i; for (int i = 1; i < 21; i++) { for (int j = 0; j + (1 << i) - 1 < n; j++) { if (a[mini[j][i - 1]] < a[mini[j + (1 << (i - 1))][i - 1]]) { mini[j][i] = mini[j][i - 1]; } else { mini[j][i] = mini[j + (1 << (i - 1))][i - 1]; } } } cout << f(0, n - 1, 0) << endl; for (int i = 0; i < vp.size(); i++) cout << 1 + vp[i].first << << 1 + vp[i].second << endl; return 0; } |
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
\$lut #(
.WIDTH(1),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A(I0),
.Y(O)
);
endmodule
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
\$lut #(
.WIDTH(2),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I1, I0}),
.Y(O)
);
endmodule
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
\$lut #(
.WIDTH(3),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I2, I1, I0}),
.Y(O)
);
endmodule
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
\$lut #(
.WIDTH(4),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I3, I2, I1, I0}),
.Y(O)
);
endmodule
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
\$lut #(
.WIDTH(5),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I4, I3, I2, I1, I0}),
.Y(O)
);
endmodule
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
\$lut #(
.WIDTH(6),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I5, I4, I3, I2, I1, I0}),
.Y(O)
);
endmodule
|
#include <bits/stdc++.h> int main() { long long n, k; std::cin >> n >> k; long long c = std::max(n - 2 * k, 0LL); std::cout << n * (n - 1) / 2 - c * (c - 1) / 2 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n; long long arr[1005]; long long dp[1005][3 * 10000]; long long add(long long a, long long b) { return ((a % 1000000007) + (b % 1000000007)) % 1000000007; } long long f(long long idx, long long sum) { if (idx == n + 1) { return 0; } if (dp[idx][sum] != -1) return dp[idx][sum]; long long res1 = sum + arr[idx]; long long res2 = sum - arr[idx]; long long val = 0; if (res1 == 10001 || res2 == 10001) val++; long long res = add(f(1 + idx, res1), f(1 + idx, res2)); res = add(res, val); return dp[idx][sum] = res; } int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &arr[i]); memset(dp, -1, sizeof dp); long long ans = 0; for (int i = 1; i <= n; i++) { ans = add(ans, f(i, 10001)); } cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__isobufsrc dut (.SLEEP(SLEEP), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
|
#include <bits/stdc++.h> using namespace std; double eps = 1e-9; const int INF = 1e9 + 7; const int MAXN = int(2e5 + 7); int n, k, b, ans; long long cur = 1, t; int main() { cin >> k >> b >> n >> t; while (cur <= t) { cur = cur * k + b; n--; } cout << max(0, ++n); return 0; } |
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:09 EDT 2015
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkOutputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkOutputArbiter
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_dram_ddr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_dram_ddr (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/* cluster_header AUTO_TEMPLATE (
); */
cluster_header cluster_header
(/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_ddr_ddr
// Local Variables:
// verilog-library-directories:("../../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; #define endl n typedef long long ll; typedef pair<int, int> pii; typedef pair<ll, ll> pll; typedef tuple<int, int, int> tiii; typedef tuple<ll, ll, ll> tlll; const int INF = 100000000; const ll INFINITE = 4500000000000000000; int main(void) { int t; cin >> t; while (t--) { int s1, s2, s3, s4; cin >> s1 >> s2 >> s3 >> s4; if (min(s1, s2) < max(s3, s4) &&min(s3, s4) <max(s1, s2)) cout << YES << endl; else cout << NO << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_SYMBOL_V
`define SKY130_FD_SC_MS__OR4BB_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_SYMBOL_V
|
module fsm(x, y, clk, reset, state_out);
// Inputs:
input wire x, clk, reset;
// Outputs:
output wire y;
output wire [2:0] state_out;
// Internal representation (state):
reg [2:0] State;
reg [2:0] NextState;
// State Encoding Parameters:
localparam STATE_Initial = 3'b000,
STATE_1 = 3'b001,
STATE_2 = 3'b010,
STATE_3 = 3'b011,
STATE_4 = 3'b100,
STATE_5 = 3'b101,
STATE_6 = 3'b110,
STATE_7_UNUSED = 3'b111;
// Implement state updating (note non-blocking assignment operator)
always @(posedge clk) begin
if (reset) State <= STATE_Initial;
else State <= NextState;
end
// Now handle output (y) value
assign y = (State == STATE_5) | (State == STATE_6);
assign state_out = State;
// Implement the actual state transition based on the current state and the input value
// Note the use of blocking assignment here
always @(*) begin
NextState = State;
case (State)
STATE_Initial: begin
if (x) NextState = STATE_1;
else NextState = STATE_Initial;
end
STATE_1 : begin
if (x) NextState = STATE_1;
else NextState = STATE_2;
end
STATE_2 : begin
if (x) NextState = STATE_3;
else NextState = STATE_Initial;
end
STATE_3 : begin
if (x) NextState = STATE_4;
else NextState = STATE_2;
end
STATE_4 : begin
if (x) NextState = STATE_5;
else NextState = STATE_6;
end
STATE_5 : begin
if (x) NextState = STATE_1;
else NextState = STATE_2;
end
STATE_6 : begin
if (x) NextState = STATE_3;
else NextState = STATE_Initial;
end
STATE_7_UNUSED : begin
NextState = STATE_Initial;
end
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; long long x, y, m; long long ans; int main() { cin >> x >> y >> m; if (x >= m || y >= m) { cout << 0; return 0; } if (x <= 0 && y <= 0) { cout << -1; return 0; } if (y < 0) swap(x, y); if (x < 0) { ans += ceil((double)-x / y); x += y * ans; } if (x < y) swap(x, y); while (x < m) { y = y + x; if (x < y) swap(x, y); ans++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; if (n <= 3 || n == 5 || n == 7 || n == 11) { cout << -1 << n ; } else { if (n % 2 == 0) { cout << n / 4 << n ; } else { cout << n / 4 - 1 << n ; } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSHOLD0_PP_SYMBOL_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold0 (
//# {{data|Data Signals}}
inout X ,
//# {{control|Control Signals}}
input RESET,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , 3, inline ) using namespace std; string s, t; int n; void pairr() { if (cin >> t) { s += t; if (t == pair ) s += < , pairr(), s += , , pairr(), s += > ; } else { cout << Error occurred ; exit(0); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; pairr(); if (cin >> t) { cout << Error occurred ; return 0; } cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; int odd, even; bool win(int k, int odd, int even) { if (odd * 2 <= k || (even * 2 <= k && (k - even) % 2 == odd % 2)) return false; return true; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); if (x & 1) odd++; else even++; } k = n - k; if (k == 0) { if (odd & 1) printf( Stannis n ); else printf( Daenerys n ); } else if (k % 2 == 0) { if (even * 2 <= k && (k - even) % 2 != odd % 2) printf( Stannis n ); else printf( Daenerys n ); } else if (k % 2 == 1) { if ((odd > 0 && win(k - 1, odd - 1, even)) || (even > 0 && win(k - 1, odd, even - 1))) printf( Stannis n ); else printf( Daenerys n ); } return 0; } |
/*
Project: RECON 2017
Author: Jeff Lieu <>
Description: Timer module to support delay function
*/
/////////////////////////////////////////////////////////////////////////////////
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
`define MILLISEC_OFFSET 0
`define SECOND_OFFSET 1
`define IRQ_TIME_OFFSET 2
`define CTRL_OFFSET 3
`define IRQ_STATUS_OFFSET 4
`define IRQ_COUNTDOWN_ENA_BIT 0
`define IRQ_TIMER_CONTINUOUS_BIT 1
`define IRQ_TIMER_MATCH_ENA_BIT 2
module recon_timer (
//Avalon slave
address,
chipselect,
clk,
reset_n,
write,
read,
writedata,
readdata,
//IRQ
irq,
//Timing Pulses
microsec_tick,
millisec_tick,
second_tick
);
parameter CLK_FREQ = 50000000;
parameter MILLISEC = CLK_FREQ/1000-1;
parameter MICROSEC = CLK_FREQ/-1;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write;
input read;
input [ 31: 0] writedata;
output irq;
output reg microsec_tick;
output reg millisec_tick;
output reg second_tick;
wire [ 31: 0] readdata;
reg [ 31: 0] read_mux_reg;
reg [ 9: 0] microsec;
reg [ 31: 0] millisec;
reg [ 31: 0] next_millisec;
reg [ 31: 0] second;
reg [ 3: 0] ctrl_reg;
reg [ 31: 0] irq_timer;
reg [ 31: 0] irq_time;
reg [ 9: 0] timer;
reg irq_active;
reg irq_active_d;
reg irq_pulse;
//s1, which is an e_avalon_slave
always@(posedge clk)
begin
if (chipselect && read)
case(address)
`MILLISEC_OFFSET : read_mux_reg <= millisec;
`SECOND_OFFSET : read_mux_reg <= second;
`IRQ_TIME_OFFSET : read_mux_reg <= irq_time;
`CTRL_OFFSET : read_mux_reg <= {28'h0, ctrl_reg};
`IRQ_STATUS_OFFSET : read_mux_reg <= {31'h0, irq_pulse};
default : read_mux_reg <= 32'h0;
endcase
end
assign readdata = read_mux_reg;
always@(posedge clk or negedge reset_n)
if (~reset_n) begin
millisec <= 0;
second <= 0;
next_millisec <= 999;
microsec_tick <= 1'b0;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
end else begin
/* Timer */
timer <= timer + 1;
millisec_tick <= 1'b0;
second_tick <= 1'b0;
microsec_tick <= 1'b0;
if (timer == MICROSEC) begin
timer <= 0;
microsec <= microsec + 1;
microsec_tick <= 1'b1;
/* Increment millisec */
if (microsec == 999) begin
microsec <= 0;
millisec <= millisec + 1;
millisec_tick <= 1'b1;
/* Increment second */
if (millisec == next_millisec) begin
second <= second+1;
next_millisec <= next_millisec + 1000;
second_tick <= 1'b1;
end
end
end
/* CTRL Register */
if (chipselect && write && address==`CTRL_OFFSET)
ctrl_reg <= writedata;
/* Timing Interval */
if (chipselect && write && address==`IRQ_TIME_OFFSET)
irq_time <= writedata;
if (irq_active)
irq_pulse <= 1'b1;
else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[0]==1'b1)
irq_pulse <= 1'b0;
/* Interval Interrupt mode */
irq_active <= 1'b0;
if (ctrl_reg[`IRQ_COUNTDOWN_ENA_BIT]==1'b1) begin
if (millisec_tick == 1'b1) begin
irq_timer <= irq_timer + 1;
if (irq_timer == irq_time) begin
irq_active <= 1'b1;
/* If Continuous Mode is enabled, we restart the timer */
if (ctrl_reg[`IRQ_TIMER_CONTINUOUS_BIT]==1'b1) begin
irq_timer <= 0;
end
end
end
end else
/* Match Mode Interrupt */
if (ctrl_reg[`IRQ_TIMER_MATCH_ENA_BIT]==1'b1) begin
if (millisec == irq_time) begin
irq_active <= 1'b1;
end
end
end
assign irq = irq_pulse;
endmodule
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE1_SOC(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// PS2 //////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
);
wire scan_ready;
wire [7:0] scan_code;
// The BCD code generated from the binary input.
wire [11:0] bcd;
wire [7:0] ascii_code;
assign LEDR = scan_code;
ps2_controller keyboard (
.reset(!KEY[0]),
.clk(CLOCK_50),
.ps2_clock(PS2_CLK),
.ps2_data(PS2_DAT),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
ascii ascii(
.clk(CLOCK_50),
.scan_ready(scan_ready),
.scan_code(scan_code),
.ascii(ascii_code)
);
// Output the ASCII on the seven segment displays.
bin2bcd bin2bcd(
.bin(ascii_code),
.bcd(bcd)
);
// Ones
seven_segment seg0(
.val(bcd[3:0]),
.out(HEX0)
);
// Tens
seven_segment seg1(
.val(bcd[7:4]),
.out(HEX1)
);
// Hundreds
seven_segment seg2(
.val(bcd[11:8]),
.out(HEX2)
);
seven_segment seg3(
.val(4'hf),
.out(HEX3)
);
seven_segment seg4(
.val(4'hf),
.out(HEX4)
);
seven_segment seg5(
.val(4'hf),
.out(HEX5)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n; long long int a[100001]; vector<pair<long long int, long long int> > g[100001]; long long int dis[100001]; long long int rem[100001]; long long int dp[100001]; long long int child[100001]; long long int ct = 1; void simpledfs(long long int x) { rem[x] = 1; for (long long int i = 0; i < g[x].size(); i++) { simpledfs(g[x][i].first); } } void dfs1(long long int x, long long int distance) { dis[x] = distance; long long int temp = 0; long long int mi = 1e9; long long int pos = -1; for (long long int i = 0; i < g[x].size(); i++) { dfs1(g[x][i].first, distance + g[x][i].second); temp = temp + child[g[x][i].first] + 1; if (dis[g[x][i].first] < mi) { mi = dis[g[x][i].first]; pos = g[x][i].first; } } dp[x] = pos; child[x] = temp; } void dfs2(long long int x, long long int minv) { for (long long int i = 0; i < g[x].size(); i++) { long long int cur = g[x][i].first; if ((dis[cur] - minv) > a[cur]) continue; else { ct++; dfs2(cur, min(minv, dis[cur])); } } } int main() { cin >> n; for (long long int i = 1; i <= n; i++) cin >> a[i]; for (long long int i = 2; i <= n; i++) { long long int p, c; cin >> p >> c; g[p].push_back(make_pair(i, c)); } dfs1(1, 0); dfs2(1, 0); cout << n - ct; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register_asyn_syn.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/03/20 16:52:43 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_asyn_syn
( data_in,
data_out,
we,
clk,
rst,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk or posedge rst)
begin
if(rst)
data_out<=#1 RESET_VALUE;
else if (rst_sync) // synchronous reset
data_out<=#1 RESET_VALUE;
else if (we) // write
data_out<=#1 data_in;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; char bd[1100][1100]; int n, m; int rt[1100][1100]; int down[1100][1100]; int cnt[1100][1100]; int check(int width, int height, int x, int y) { int filled = 0; bool first = true; while (true) { int godown = down[x][y] - height; if (godown < 0) break; if (cnt[x][y] - cnt[x][y + width] - cnt[x + down[x][y]][y] + cnt[x + down[x][y]][y + width] == width * down[x][y]) { if (first) { filled += width * down[x][y]; first = false; } else { filled += height + width * godown; } } else break; if ((y + 1) + width <= m) { y++; x += godown; } else break; } return filled; } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , bd[i]); for (int i = n - 1; i >= 0; i--) { for (int j = m - 1; j >= 0; j--) { if (bd[i][j] == . ) { rt[i][j] = down[i][j] = 0; } else { rt[i][j] = 1 + rt[i][j + 1]; down[i][j] = 1 + down[i + 1][j]; } } } int tlx = -1; int tly = -1; int tot = 0; for (int i = n - 1; i >= 0; i--) { for (int j = m - 1; j >= 0; j--) { if (bd[i][j] == X ) { tlx = i; tly = j; tot++; } cnt[i][j] = (bd[i][j] == X ) + cnt[i + 1][j] + cnt[i][j + 1] - cnt[i + 1][j + 1]; } } int best = 1000000000; for (int height = 1; height <= down[tlx][tly]; height++) { int width = rt[tlx][tly]; int filled = check(width, height, tlx, tly); if (filled == tot) best = min(best, width * height); } for (int width = 1; width <= rt[tlx][tly]; width++) { int height = down[tlx][tly]; int filled = check(width, height, tlx, tly); if (filled == tot) best = min(best, width * height); } printf( %d n , best == 1000000000 ? -1 : best); } |
//IEEE Floating Point Adder (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if a is inf and signs don't match return nan
if ((b_e == 128) && (a_s != b_s)) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_2_V
`define SKY130_FD_SC_HS__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; vector<int> e[N]; int n, ans, f[N][2], g[N][2]; void dfs1(int x, int fa) { f[x][0] = 0; f[x][1] = 0; int d = e[x].size() - (fa != 0); for (auto i : e[x]) if (i != fa) { dfs1(i, x); f[x][0] = max(f[x][0], max(f[i][0], f[i][1]) - 1); f[x][1] = max(f[x][1], f[i][0]); } f[x][0] += d; f[x][1]++; } void upd(pair<int, int> &x, pair<int, int> &y, pair<int, int> z) { if (z > x) swap(x, z); y = max(y, z); } void dfs2(int x, int fa) { if (!fa) g[x][0] = 0, g[x][1] = 0; pair<int, int> mx1(0, x), mx2(-1, -1), mx3(0, x), mx4(-1, -1); upd(mx1, mx2, pair<int, int>(max(g[x][0], g[x][1]) - 1, -1)); upd(mx3, mx4, pair<int, int>(g[x][0], -1)); for (auto i : e[x]) if (i != fa) { upd(mx1, mx2, pair<int, int>(max(f[i][0], f[i][1]) - 1, i)); upd(mx3, mx4, pair<int, int>(f[i][0], i)); } int d = e[x].size() - 1; ans = max(ans, max(mx1.first + d + 1, mx3.first)); for (auto i : e[x]) if (i != fa) { g[i][0] = (mx1.second == i ? mx2.first : mx1.first) + d; g[i][1] = (mx3.second == i ? mx4.first : mx3.first) + 1; dfs2(i, x); } } int main() { srand(time(NULL)); scanf( %d , &n); for (int i = (int)(1); i <= (int)(n - 1); i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } dfs1(1, 0); dfs2(1, 0); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; inline int read(){ int x=0,f=1; char ch=getchar(); while(ch< 0 ||ch> 9 ){ if(ch== - ) f=-1; ch=getchar(); } while(ch>= 0 &&ch<= 9 ){ x=(x<<1)+(x<<3)+(ch^48); ch=getchar(); } return x*f; } const int maxn = 3e4 + 9; int t; int a[3]; int solve(){ int l = a[0], m = a[1], r = a[2]; int avg = (l + m + r) / 3; //printf( avg: %d n , avg); int ans = 0; if (l < avg){ if (r > avg){ if (m > avg){ ans += (m - avg) * 2 + r - avg; return ans; } else if (m < avg){ ans += avg - l + (avg - m) * 2; return ans; } else{ ans += avg - l; return ans; } } else if (r < avg){ ans += (avg - l) * 2 + avg - r; return ans; } else{ ans += (avg - l) * 2; return ans; } } else if (l == avg){ if (m == avg){ return ans; } else if (m < avg){ ans += (avg - m) * 2; return ans; } else{ ans += m - avg; return ans; } } else{ if (m < avg){ if (r > avg){ ans += (r - avg) * 2 + l - avg; return ans; } else if (r < avg){ ans += (avg - r) * 2 + avg - m; return ans; } else{ ans += avg - m; return ans; } } else if (m > avg){ ans += (l - avg) * 2 + m - avg; return ans; } else{ ans = (l - avg) * 2; return ans; } } return ans; } int main(){ t = read(); while(t--){ int n = read(); int m; a[0] = a[1] = a[2] = 0; for (int i = 1; i <= n; i++){ m = read(); a[m % 3]++; } //sort(a, a + 3); int ans = solve(); printf( %d n , ans); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxaddrcheck.v,v $
// Revision 1.9 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
`include "timescale.v"
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= #Tp 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; const int N = 100000 + 5; int n, k; char s[N]; int su[N]; int a[N]; bool check(int md) { for (int i = 1; i <= (int)(n); ++i) { int s = max(i - md, 1); int f = min(i + md, n); if (a[i] == 1 && su[f] - su[s - 1] >= k + 1) return true; } return false; } void solve() { scanf( %d%d , &n, &k); scanf( %s , s); for (int i = 1; i <= (int)(n); ++i) { a[i] = s[i - 1] - 0 ; a[i] ^= 1; } for (int i = 1; i <= (int)(n); ++i) su[i] = su[i - 1] + a[i]; int st = 0, fi = n, re = n; while (st <= fi) { int md = (st + fi) / 2; if (check(md)) { re = md; fi = md - 1; } else st = md + 1; } printf( %d n , re); } void testgen() { FILE* f = fopen( input.txt , w ); fclose(f); } int main() { cout << fixed; cout.precision(10); cerr << fixed; cerr.precision(3); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; set<long long> a = {1, n}; for (long long d = 2; d <= min((long long)sqrt(n) + 10, n - 1); d++) { if (n % d == 0) { a.insert(d); a.insert(n / d); } } long long ans = -1; if (a.size() >= k) { auto it = next(a.begin(), k - 1); ans = *it; } cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_BLACKBOX_V
`define SKY130_FD_SC_HD__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_above(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input valid_i,
output [31:0] r,
output reg valid_o
);
reg r_one;
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= valid_i;
case({a[31], b[31]})
2'b00: r_one <= a[30:0] > b[30:0];
2'b01: r_one <= 1'b1;
2'b10: r_one <= 1'b0;
2'b11: r_one <= a[30:0] < b[30:0];
endcase
end
assign r = r_one ? 32'h3f800000: 32'h00000000;
endmodule
|
//
// Paul Gao 06/2019
//
//
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_router_test_node_master
#(// Wormhole link parameters
parameter `BSG_INV_PARAM(flit_width_p )
,parameter dims_p = 2
,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0}
,parameter `BSG_INV_PARAM(len_width_p )
,parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,localparam num_nets_lp = 2
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam cord_width_lp = cord_markers_pos_p[dims_p]
)
(// Node side
input clk_i
,input reset_i
,input [num_nets_lp-1:0] en_i
,output logic [num_nets_lp-1:0] error_o
,output logic [num_nets_lp-1:0][31:0] sent_o
,output logic [num_nets_lp-1:0][31:0] received_o
// Wormhole side
,input [cord_width_lp-1:0] dest_cord_i
,input [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_i
,output [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_o
);
localparam width_lp = num_channels_p * channel_width_p;
genvar i;
/********************* Packet definition *********************/
`declare_bsg_wormhole_router_header_s(cord_width_lp,len_width_p,bsg_wormhole_router_header_s);
typedef struct packed {
logic [flit_width_p-$bits(bsg_wormhole_router_header_s)-1:0] data;
bsg_wormhole_router_header_s hdr;
} wormhole_network_header_flit_s;
// synopsys translate_off
initial
begin
assert ($bits(wormhole_network_header_flit_s)-$bits(bsg_wormhole_router_header_s) >= width_lp)
else $error("Packet data width %d is too narrow for data width %d.", $bits(wormhole_network_header_flit_s)-$bits(bsg_wormhole_router_header_s), width_lp);
end
// synopsys translate_on
/********************* Interfacing bsg_noc link *********************/
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [num_nets_lp-1:0] link_i_cast, link_o_cast;
for (i = 0; i < num_nets_lp; i++)
begin: noc_cast
assign link_i_cast[i] = link_i[i];
assign link_o[i] = link_o_cast[i];
end
/********************* Master nodes (two of them) *********************/
// ATTENTION: This loopback node is not using fwd and rev networks as usual.
// fwd_link_o sends out fwd packets, rev_link_i receives loopback packets.
// rev_link_o also sends out fwd packets, fwd_link_i receives loopback packets.
for (i = 0; i < num_nets_lp; i++)
begin: mstr
logic resp_in_v;
wormhole_network_header_flit_s resp_in_data;
logic resp_in_yumi;
logic req_out_ready;
wormhole_network_header_flit_s req_out_data;
logic req_out_v;
bsg_one_fifo
#(.width_p(flit_width_p)
) resp_in_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(link_o_cast[i].ready_and_rev)
,.v_i (link_i_cast[i].v)
,.data_i (link_i_cast[i].data)
,.v_o (resp_in_v)
,.data_o (resp_in_data)
,.yumi_i (resp_in_yumi)
);
bsg_one_fifo
#(.width_p(flit_width_p)
) req_out_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(req_out_ready)
,.v_i (req_out_v)
,.data_i (req_out_data)
,.v_o (link_o_cast[i].v)
,.data_o (link_o_cast[i].data)
,.yumi_i (link_o_cast[i].v & link_i_cast[i].ready_and_rev)
);
logic [width_lp-1:0] data_gen, data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_out
(.clk_i (clk_i)
,.reset_i(reset_i)
,.yumi_i (req_out_v & req_out_ready)
,.o (data_gen)
);
assign req_out_v = en_i[i];
assign req_out_data.hdr.cord = dest_cord_i;
assign req_out_data.hdr.len = 0;
assign req_out_data.data = {'0, data_gen};
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_in
(.clk_i (clk_i)
,.reset_i(reset_i)
,.yumi_i (resp_in_v)
,.o (data_check)
);
assign resp_in_yumi = resp_in_v;
// Count sent and received packets
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clear_i(1'b0)
,.up_i (req_out_v & req_out_ready)
,.count_o(sent_o[i])
);
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clear_i(1'b0)
,.up_i (resp_in_v)
,.count_o(received_o[i])
);
always_ff @(posedge clk_i)
if (reset_i)
error_o[i] <= 0;
else
if (resp_in_v && data_check != (width_lp'(resp_in_data.data)))
begin
$error("%m mismatched resp data %x %x",data_check, resp_in_data.data[width_lp-1:0]);
error_o[i] <= 1;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_network_test_node_master)
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Sdram_RD_FIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_RD_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire sub_wire1;
wire [8:0] sub_wire2;
wire sub_wire3;
wire [8:0] sub_wire4;
wire [15:0] q = sub_wire0[15:0];
wire rdempty = sub_wire1;
wire [8:0] rdusedw = sub_wire2[8:0];
wire wrfull = sub_wire3;
wire [8:0] wrusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M10K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; Point() {} Point(double a, double b) { x = a, y = b; } }; const double eps = 1e-10; Point operator+(Point A, Point B) { return Point(A.x + B.x, A.y + B.y); } Point operator-(Point A, Point B) { return Point(A.x - B.x, A.y - B.y); } Point operator*(Point A, double p) { return Point(A.x * p, A.y * p); } Point operator/(Point A, double p) { return Point(A.x / p, A.y / p); } bool operator<(const Point &a, const Point &b) { return a.x < b.x || (a.x == b.x && a.y < b.y); } int dcmp(double x) { if (fabs(x) < eps) return 0; else return x < 0 ? -1 : 1; } bool operator==(const Point &a, const Point &b) { return dcmp(a.x - b.x) == 0 && dcmp(a.y - b.y) == 0; } double Dot(Point A, Point B) { return A.x * B.x + A.y * B.y; } double Length(Point A) { return sqrt(Dot(A, A)); } double Angle(Point A, Point B) { return acos(Dot(A, B) / Length(A) / Length(B)); } double Cross(Point A, Point B) { return A.x * B.y - A.y * B.x; } double Area2(Point A, Point B, Point C) { return Cross(B - A, C - A); } Point Rotate(Point A, double rad) { return Point(A.x * cos(rad) - A.y * sin(rad), A.x * sin(rad) + A.y * cos(rad)); } Point Jd(Point P, Point v, Point Q, Point w) { Point u = P - Q; double t = Cross(w, u) / Cross(v, w); return P + v * t; } double Dtl(Point P, Point A, Point B) { Point v1 = B - A, v2 = P - A; return fabs(Cross(v1, v2)) / Length(v1); } double Dts(Point P, Point A, Point B) { if (A == B) return Length(P - A); Point v1 = B - A, v2 = P - A, v3 = P - B; if (dcmp(Dot(v1, v2) < 0)) return Length(v2); else if (dcmp(Dot(v1, v3)) > 0) return Length(v3); else return fabs(Cross(v1, v2)) / Length(v1); } Point Gjp(Point P, Point A, Point B) { Point v = B - A; return A + v * (Dot(v, P - A)) / (Dot(v, v)); } bool Spi(Point a1, Point a2, Point b1, Point b2) { double c1 = Cross(a2 - a1, b1 - a1), c2 = Cross(a2 - a1, b2 - a1), c3 = Cross(b2 - b1, a1 - b1), c4 = Cross(b2 - b1, a2 - a1); return dcmp(c1) * dcmp(c2) < 0 && dcmp(c3) * dcmp(c4) < 0; } bool Onseg(Point p, Point a1, Point a2) { return dcmp(Cross(a1 - p, a2 - p)) == 0 && dcmp(Dot(a1 - p, a2 - p)) < 0; } double Parea(Point *p, int n) { double area = 0; for (int i = 1; i <= n; i++) area += Cross(p[i] - p[0], p[i + 1] - p[0]); return area / 2; } bool cmp(Point a, Point b) { if (fabs(a.x - b.x) > eps) return a.x + eps < b.x; else return a.y + eps < b.y; } struct Circle { Point o; double r; Circle() {} Circle(Point _o, double _r) { o = _o, r = _r; } friend vector<Point> operator&(const Circle &c1, const Circle &c2) { double d = Length(c1.o - c2.o); if (d > c1.r + c2.r + eps || d < fabs(c1.r - c2.r) - eps) return vector<Point>(); double dt = (c1.r * c1.r - c2.r * c2.r) / d, d1 = (d + dt) / 2.0; Point dir = (c2.o - c1.o) / d, pcrs = c1.o + dir * d1; dt = sqrt(max(0.0, c1.r * c1.r - d1 * d1)); swap(dir.x, dir.y), dir.x = -dir.x; return vector<Point>{pcrs + dir * dt, pcrs - dir * dt}; } } p[10]; int f[10], rk[10], n; int find(int x) { if (f[x] != x) return f[x] = find(f[x]); else return x; } void merge(int i, int j) { int x = find(i), y = find(j); if (rk[x] > rk[y]) f[y] = x; else { f[x] = y; if (rk[x] == rk[y]) rk[y]++; } } int main() { cin >> n; for (int i = 1; i <= n; i++) f[i] = i, rk[i] = 0; for (int i = 1; i <= n; i++) cin >> p[i].o.x >> p[i].o.y >> p[i].r; int e = 0, v = 0, c = 0; vector<Point> all; for (int i = 1; i <= n; i++) { vector<Point> tmp1; for (int j = 1; j <= n; j++) { if (j == i) continue; vector<Point> tmp2 = p[i] & p[j]; if (tmp2.size()) merge(i, j); tmp1.insert(tmp1.end(), tmp2.begin(), tmp2.end()); all.insert(all.end(), tmp2.begin(), tmp2.end()); } sort(tmp1.begin(), tmp1.end(), cmp); e += unique(tmp1.begin(), tmp1.end()) - tmp1.begin(); } sort(all.begin(), all.end(), cmp); v += unique(all.begin(), all.end()) - all.begin(); set<int> st; for (int i = 1; i <= n; i++) { st.insert(find(i)); } cout << e - v + st.size() + 1 << endl; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
Test2 test2 (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
reg [31:0] dly0;
reg [31:0] dly1;
reg [31:0] dly2;
reg [31:0] dly3;
// If called in an assertion, sequence, or property, the appropriate clocking event.
// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
// Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used.
// Otherwise, if called in a procedure, the inferred clock
// Otherwise, default clocking
always @(posedge clk) begin
dly0 <= in;
dly1 <= dly0;
dly2 <= dly1;
dly3 <= dly2;
// $past(expression, ticks, expression, clocking)
// In clock expression
if (dly0 != $past(in)) $stop;
if (dly0 != $past(in,1)) $stop;
if (dly1 != $past(in,2)) $stop;
end
assert property (@(posedge clk) dly0 == $past(in));
endmodule
module Test2 (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
reg [31:0] dly0;
reg [31:0] dly1;
default clocking @(posedge clk); endclocking
assert property (@(posedge clk) dly1 == $past(in, 2));
endmodule
|
#include <bits/stdc++.h> using namespace std; bool cc(int x) { for (int i = 2; i * i <= x; i++) if (x % i == 0 && x != 2) return false; return true; } int pow(int i, int j) { int x = 1; while (j--) { x *= i; } return x; } int main() { vector<int> v; int n; cin >> n; int c = 0; for (int i = 2; i <= n; i++) { if (cc(i)) { for (int j = 1; pow(i, j) <= n; j++) { v.push_back(pow(i, j)); } } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long MOD = (long long)1e9 + 7; long long add(long long x, long long y) { x += y; if (x >= MOD) return x - MOD; return x; } long long sub(long long x, long long y) { x -= y; if (x < 0) return x + MOD; return x; } long long mult(long long x, long long y) { return (x * y) % MOD; } const int N = (int)1e6 + 7; long long f[N], rf[N]; long long pw1[N], pw2[N]; int n, m; int main() { rf[0] = rf[1] = 1; for (long long x = 2; x < N; x++) rf[x] = sub(0, mult(MOD / x, rf[MOD % x])); for (int i = 2; i < N; i++) rf[i] = mult(rf[i - 1], rf[i]); f[0] = 1; for (int i = 1; i < N; i++) f[i] = mult(f[i - 1], i); scanf( %d%d , &n, &m); pw1[0] = pw2[0] = 1; for (int i = 1; i < N; i++) { pw1[i] = mult(pw1[i - 1], n); pw2[i] = mult(pw2[i - 1], m); } long long ans = 0; for (int k = 1; k < n - 1 && k <= m; k++) { long long cur = k + 1; cur = mult(cur, pw1[n - k - 2]); cur = mult(cur, f[n - 2]); cur = mult(cur, rf[n - k - 1]); cur = mult(cur, f[m - 1]); cur = mult(cur, rf[k - 1]); cur = mult(cur, rf[m - k]); cur = mult(cur, pw2[n - 1 - k]); ans = add(ans, cur); } if (n - 1 <= m) { long long cur = f[n - 2]; cur = mult(cur, f[m - 1]); cur = mult(cur, rf[n - 2]); cur = mult(cur, rf[m - n + 1]); ans = add(ans, cur); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int Set(int N, int pos) { return N |= (1LL << pos); } int Reset(int N, int pos) { return N &= ~(1LL << pos); } bool Check(int N, int pos) { return N & (1LL << pos); } int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}, dy[] = {1, -1, 0, 0, 1, -1, -1, 1}; template <class T> void cmin(T &a, T b) { if (b < a) a = b; } template <class T> void cmax(T &a, T b) { if (b > a) a = b; } template <class T> int len(const T &c) { return (int)c.size(); } template <class T> int len(char c[]) { return (int)strlen(c); } string itos(long n) { string s; while (n) { s += (n % 10 + 48); n /= 10; } reverse(s.begin(), s.end()); return s; } long stoi(string s) { long n = 0; for (int i(0), _n(len(s)); i < _n; ++i) n = n * 10 + (s[i] - 48); return n; } long long n, ar[200005], arr[200005], m, a, p, b, aa, bb, mx = 0; pair<int, int> fun(long d) { p = upper_bound(ar, ar + n, d) - ar; a = (p * 2 + (n - p) * 3); p = upper_bound(arr, arr + m, d) - arr; b = (p * 2 + (m - p) * 3); return make_pair(a, b); } int main() { mx = -100000000000000000LL; cin >> n; for (int i(0), _n(n); i < _n; ++i) cin >> ar[i]; cin >> m; for (int i(0), _n(m); i < _n; ++i) cin >> arr[i]; sort(ar, ar + n); sort(arr, arr + m); aa = n * 3; bb = m * 3; mx = aa - bb; pair<int, int> pr; pr = fun(ar[0] - 1); a = pr.first; b = pr.second; if (a - b > mx) { mx = a - b; aa = a; bb = b; } else if (a - b == mx && a > aa) { aa = a; bb = b; } for (int i(0), _n(n); i < _n; ++i) { pr = fun(ar[i]); a = pr.first; b = pr.second; if (a - b > mx) { mx = a - b; aa = a; bb = b; } else if (a - b == mx && a > aa) { aa = a; bb = b; } } for (int i(0), _n(m); i < _n; ++i) { pr = fun(arr[i]); a = pr.first; b = pr.second; if (a - b > mx) { mx = a - b; aa = a; bb = b; } else if (a - b == mx && a > aa) { aa = a; bb = b; } } pr = fun(ar[n - 1] + 1); a = pr.first; b = pr.second; if (a - b > mx) { mx = a - b; aa = a; bb = b; } else if (a - b == mx && a > aa) { aa = a; bb = b; } cout << aa << : << bb; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3000 + 50; struct Edge { int to, next; long long w; } edge[maxn * 2]; int k = 1, head[maxn]; void add(int u, int v) { edge[++k].to = v; edge[k].next = head[u]; head[u] = k; } long long n, m, b[maxn], w[maxn], v[maxn], sz[maxn], T; pair<long long, long long> dp[maxn][maxn], temp[maxn]; void update(pair<long long, long long> &x, pair<long long, long long> y) { if (y > x) x = y; } void dfs(int u, int f) { sz[u] = 1; dp[u][1] = make_pair(0, v[u]); for (int i = head[u]; i; i = edge[i].next) { if (edge[i].to == f) continue; dfs(edge[i].to, u); for (int j = 1; j <= sz[u] + sz[edge[i].to]; j++) temp[j] = make_pair(-1, 0); for (int j = 1; j <= sz[u]; j++) { for (int k = 1; k <= sz[edge[i].to]; k++) { update(temp[j + k], make_pair(dp[u][j].first + dp[edge[i].to][k].first + (dp[edge[i].to][k].second > 0), dp[u][j].second)); update(temp[j + k - 1], make_pair(dp[u][j].first + dp[edge[i].to][k].first, dp[u][j].second + dp[edge[i].to][k].second)); } } for (int j = 1; j <= sz[u] + sz[edge[i].to]; j++) dp[u][j] = temp[j]; sz[u] += sz[edge[i].to]; } } int main() { cin >> T; while (T--) { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> b[i], v[i] -= b[i]; for (int i = 1; i <= n; i++) cin >> w[i], v[i] += w[i]; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; add(a, b); add(b, a); } dfs(1, 0); long long ans = dp[1][m].first + (dp[1][m].second > 0); cout << ans << endl; k = 1; memset(head, 0, sizeof(int) * (n + 10)); memset(v, 0, sizeof(long long) * (n + 10)); memset(sz, 0, sizeof(long long) * (n + 10)); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long int> a; vector<long long int> b; long long int fa(int l, int r) { long long int ret = 0; for (int i = l; i <= r; ++i) ret |= a[i]; return ret; } long long int fb(int l, int r) { long long int ret = 0; for (int i = l; i <= r; ++i) ret |= b[i]; return ret; } int main() { ios_base::sync_with_stdio(0); int n; long long int aux, ans = 0; cin >> n; for (int i = 0; i < n; ++i) { cin >> aux; a.push_back(aux); } for (int i = 0; i < n; ++i) { cin >> aux; b.push_back(aux); } for (int i = 0; i < n; ++i) for (int j = i; j < n; ++j) { ans = max(ans, fa(i, j) + fb(i, j)); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000000 + 100, logN = 23; long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int f[N][logN + 1]; int query(int l, int r) { long long ans = 0; for (int i = logN - 1; i >= 0; --i) { if (f[l][i] < r) { l = f[l][i]; ans += (1 << i); } } l = f[l][0]; ans++; if (l < r) return -1; return ans; } int main() { int n = read(), m = read(), mx = 0; for (int i = 1; i <= n; ++i) { int l = read() + 1, r = read() + 1; f[l][0] = max(f[l][0], r); mx = max(mx, r); } for (int i = 1; i <= mx; ++i) f[i][0] = max(f[i][0], max(i, f[i - 1][0])); for (int j = 1; j < logN; ++j) for (int i = 1; i <= mx; ++i) f[i][j] = f[f[i][j - 1]][j - 1]; while (m--) { int l = read() + 1, r = read() + 1; printf( %d n , query(l, r)); } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int INF = (int)(1e9 + 1e6); const long long LINF = (long long)(4e18); const double EPS = 1e-9; const long long mod = 1e9 + 7; mt19937 ggen; void solve(); int main() { iostream::sync_with_stdio(false); cin.tie(0); ggen = mt19937(1337); solve(); } void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } int x, f; cin >> x >> f; long long ans = 0; long long ft = x + f; for (int i = 0; i < n; ++i) { long long gh = static_cast<long long>(a[i]); long long mt = gh / ft; ans += mt * f; if (gh - mt * ft > x) { ans += f; } } cout << ans; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 "
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter nCK_PER_CLK = 4,
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
if (FAMILY == "SPARTAN6")
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
else
// if (nCK_PER_CLK == 2 )
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
// else
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) ))
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
mig_7series_v2_0_afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x + _y; if (_ >= _mod) _ -= _mod; return _; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x - _y; if (_ < 0) _ += _mod; return _; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x * _y; if (_ >= _mod) _ %= _mod; return _; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1ll; long long _tmp = mypow(_a, _x / 2, _mod); _tmp = mul(_tmp, _tmp, _mod); if (_x & 1) _tmp = mul(_tmp, _a, _mod); return _tmp; } long long mymul(long long _a, long long _x, long long _mod) { if (_x == 0) return 0ll; long long _tmp = mymul(_a, _x / 2, _mod); _tmp = add(_tmp, _tmp, _mod); if (_x & 1) _tmp = add(_tmp, _a, _mod); return _tmp; } inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int __ = 1, _cs; void build() {} int n, q; void init() { n = getint(); q = getint(); } set<pair<int, int> > S; set<int> v[303030]; void solve() { int cnt = 0; while (q--) { int cmd = getint(); int xi = getint(); if (cmd == 1) { v[xi].insert(++cnt); S.insert({cnt, xi}); } else if (cmd == 2) { for (int ii : v[xi]) S.erase({ii, xi}); v[xi].clear(); } else { while (S.size() && S.begin()->first <= xi) { v[S.begin()->second].erase(S.begin()->first); S.erase(S.begin()); } } printf( %d n , (int)S.size()); } } int main() { build(); while (__--) { init(); solve(); } } |
#include <bits/stdc++.h> #define int long long #define F0R(i, n) for(int i = 0; i < (n); i++) using namespace std; signed main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int T; cin >> T; F0R(cas,T) { int N; cin >> N; vector<int> a(N); for(int &x : a) cin >> x; sort(a.begin(),a.end(),greater<int>()); int evsum = 0, odsum = 0; F0R(i,N) { if(i%2 && a[i]%2) odsum += a[i]; if((i%2 == 0) && (a[i]%2 == 0)) evsum += a[i]; } if(evsum > odsum) cout << Alice n ; if(evsum == odsum) cout << Tie n ; if(evsum < odsum) cout << Bob n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double esp = 0.00000001; const int N = 60; const int PSize = 100; const double PCross = 0.3; const double PMuta = 0.05; int a[200010], t[200010]; int n, T; vector<int> res; bool cmp(pair<int, int> a, pair<int, int> b) { return a.second < b.second; } bool ok(int k, vector<pair<int, int> > e) { if (k > e.size()) return false; int ans = 0; sort(e.begin(), e.end(), cmp); for (int i = 0; i < k; i++) ans += e[i].second; if (ans > T) return false; res.clear(); for (int i = 0; i < k; i++) res.push_back(e[i].first); return true; } int main() { cin >> n >> T; for (int i = 0; i < n; i++) cin >> a[i] >> t[i]; int l = 0, r = n; while (l < r) { int mid = (l + r + 1) >> 1; vector<pair<int, int> > e; for (int i = 0; i < n; i++) if (a[i] >= mid) e.push_back(make_pair(i, t[i])); if (ok(mid, e)) l = mid; else r = mid - 1; } cout << l << endl << res.size() << endl; for (int i = 0; i < res.size(); i++) { if (i) cout << ; cout << res[i] + 1; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); string s; cin >> s; string ans = 0 ; int curr = 0; for (int i = 1; i < n; i++) { if (s[i] == ( ) curr = curr ^ 1; ans += (char)(curr + 0 ); if (s[i] == ) ) curr = curr ^ 1; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s[1005], ss[1005]; cin >> s[0] >> ss[0]; int n; cin >> n; for (int i = 1; i <= n; i++) cin >> s[i] >> ss[i]; for (int i = 0; i <= n; i++) { if (i == 0) { cout << s[0] << << ss[0] << endl; continue; } else if (s[i] == s[i - 1]) { s[i] = ss[i]; ss[i] = ss[i - 1]; cout << s[i] << << ss[i] << endl; } else if (s[i] == ss[i - 1]) { s[i] = s[i - 1]; cout << s[i] << << ss[i] << endl; } } return 0; } |
`timescale 1ns/1ps
`define prop_delay (0.05)
module AND2 (o, a, b);
output o;
input a, b;
and #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module AND3 (o, a, b, c);
output o;
input a, b, c;
and #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module NAND2 (o, a, b);
output o;
input a, b;
nand #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module NAND3 (o, a, b, c);
output o;
input a, b, c;
nand #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module OR2 (o, a, b);
output o;
input a, b;
or #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module OR3 (o, a, b, c);
output o;
input a, b, c;
or #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module NOR2 (o, a, b);
output o;
input a, b;
nor #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module NOR3 (o, a, b, c);
output o;
input a, b, c;
nor #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module AO22 (o, a1, a2, b1, b2);
output o;
input a1, a2, b1, b2;
wire a, b;
and (a, a1, a2);
and (b, b1, b2);
or #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module AO222 (o, a1, a2, b1, b2, c1, c2);
output o;
input a1, a2, b1, b2, c1, c2;
wire a, b, c;
and (a, a1, a2);
and (b, b1, b2);
and (c, c1, c2);
or #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module BUFF (o, i);
output o;
input i;
assign o = i;
endmodule
module INV (o, i);
output o;
input i;
not #(`prop_delay,`prop_delay) (o, i);
endmodule
module GND (o);
output o;
supply0 gnd;
assign o = gnd;
endmodule
module C2 (o, a, b);
output o;
input a, b;
UDP_C2 #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module C2R (o, a, b, r);
output o;
input a, b, r;
UDP_C2R #(`prop_delay,`prop_delay) (o, a, b, r);
endmodule
module AC2 (o, a, u); // FIXME, change to C1U1
output o;
input a, u;
UDP_C1U1 #(`prop_delay,`prop_delay) (o, a, u);
endmodule
module C3 (o, a, b, c);
output o;
input a, b, c;
UDP_C3 #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module MUTEX (ar, br, ag, bg);
input ar, br;
output ag, bg;
// FIXME
// assign ag = ar;
// assign bg = br;
UDP_mutex_top_half #(`prop_delay, `prop_delay) (ag, ar, br, bg);
UDP_mutex_bottom_half #(`prop_delay, `prop_delay) (bg, br, ar, ag);
endmodule
primitive UDP_C2 (o, a, b);
output o;
input a, b;
reg o;
table /*
a b : o : o' */
1 1 : ? : 1;
0 0 : ? : 0;
1 0 : ? : -;
0 1 : ? : -;
endtable
endprimitive
primitive UDP_C1U1 (o, a, u);
output o;
input a, u;
reg o;
table /*
a u : o : o' */
1 1 : ? : 1;
0 ? : ? : 0;
1 0 : ? : -;
endtable
endprimitive
primitive UDP_C2R (o, a, b, r);
output o;
input a, b, r;
reg o;
table /*
a b r : o : o' */
1 1 0 : ? : 1;
0 0 0 : ? : 0;
1 0 0 : ? : -;
0 1 0 : ? : -;
? ? 1 : ? : 0;
endtable
endprimitive
primitive UDP_C3 (o, a, b, c);
output o;
input a, b, c;
reg o;
table /*
a b c : o : o' */
1 1 1 : ? : 1;
0 0 0 : ? : 0;
1 0 0 : ? : -;
1 1 0 : ? : -;
0 1 0 : ? : -;
0 1 1 : ? : -;
0 0 1 : ? : -;
1 0 1 : ? : -;
endtable
endprimitive
/*
module top;
reg a, b;
wire o;
C2 I0 (o, a, b);
initial begin
$monitor ("%t a = %x b = %x o = %x", $time, a, b, o);
a = 0; b = 0;
#1 a = 1; b = 0;
#1 a = 1; b = 1;
#1 a = 1; b = 0;
#1 a = 0; b = 0;
end
endmodule
*/
primitive UDP_mutex_bottom_half (G, R1, R2, G2state);
output G;
input R1, R2, G2state;
reg G;
table
// ,--------- R1
// | ,-------- R2
// | | ,------- G2state
// | | | ,---- G
// | | | | ,- G'
// v v v : v : v
0 ? ? : ? : 0;
1 ? 1 : ? : 0;
1 0 0 : ? : 1;
1 x 0 : ? : 1;
1 ? x : ? : 1;
1 1 0 : 0 : 0;
1 1 0 : 1 : 1;
x x x : ? : x;
endtable
endprimitive
primitive UDP_mutex_top_half (G, R1, R2, G2state);
output G;
input R1, R2, G2state;
table
// ,-------- R1
// | ,------- R2
// | | ,------ G2state
// | | | ,--- G
// v v v : v
0 ? ? : 0;
1 ? 1 : 0;
1 ? 0 : 1;
1 ? x : 1;
x x x : x;
endtable
endprimitive
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
#include <bits/stdc++.h> #define ll long long using namespace std; int t; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> t; while (t--) { int n; cin >> n; vector<pair<int, int> > a(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i].first; a[i].second = i; } sort(a.begin() + 1, a.end()); if (a[1].first == a[2].first) { cout << a[n].second << endl; } else { cout << a[1].second << endl; } } return 0; } |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Z80 CPU plug into TV80 core
module cpu_z80(
input CLK_4M,
input nRESET,
inout [7:0] SDD,
output [15:0] SDA,
output reg nIORQ, nMREQ,
output reg nRD, nWR,
input nINT, nNMI
);
reg [7:0] SDD_IN_REG;
wire [7:0] SDD_IN;
wire [7:0] SDD_OUT;
wire [6:0] T_STATE;
wire [6:0] M_CYCLE;
wire nINTCYCLE;
wire NO_READ;
wire WRITE;
wire IORQ;
assign SDD = nWR ? 8'bzzzzzzzz : SDD_OUT;
assign SDD_IN = nRD ? 8'bzzzzzzzz : SDD;
tv80_core TV80( , IORQ, NO_READ, WRITE, , , , SDA, SDD_OUT, M_CYCLE,
T_STATE, nINTCYCLE, , , nRESET, CLK_4M, 1'b1, 1'b1,
nINT, nNMI, 1'b1, SDD_IN, SDD_IN_REG);
always @(posedge CLK_4M)
begin
if (!nRESET)
begin
nRD <= #1 1'b1;
nWR <= #1 1'b1;
nIORQ <= #1 1'b1;
nMREQ <= #1 1'b1;
SDD_IN_REG <= #1 8'b00000000;
end
else
begin
nRD <= #1 1'b1;
nWR <= #1 1'b1;
nIORQ <= #1 1'b1;
nMREQ <= #1 1'b1;
if (M_CYCLE[0])
begin
if (T_STATE[1])
begin
nRD <= #1 ~nINTCYCLE;
nMREQ <= #1 ~nINTCYCLE;
nIORQ <= #1 nINTCYCLE;
end
end
else
begin
if ((T_STATE[1]) && NO_READ == 1'b0 && WRITE == 1'b0)
begin
nRD <= #1 1'b0;
nIORQ <= #1 ~IORQ;
nMREQ <= #1 IORQ;
end
if ((T_STATE[1]) && WRITE == 1'b1)
begin
nWR <= #1 1'b0;
nIORQ <= #1 ~IORQ;
nMREQ <= #1 IORQ;
end
end
if (T_STATE[2]) SDD_IN_REG <= #1 SDD_IN;
end
end
endmodule
|
//#############################################################################
//# Purpose: MIO Transmit IO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module mtx_io #(parameter IOW = 64, // IO width
parameter TARGET = "GENERIC" // target selector
)
(// reset, clk, cfg
input nreset, // async active low reset
input io_clk, // clock from divider
input ddr_mode, // send data as ddr
input [1:0] iowidth, // iowidth *8,16,32,64
// chip IO interface
output [IOW-1:0] tx_packet, // data for IO
output reg tx_access, // access signal for IO
input tx_wait, // IO wait signals
// core side
input [7:0] io_valid, // per byte valid indicator
input [IOW-1:0] io_packet, // packet
output io_wait // pushback to serializer in sdr mode
);
//local wires
reg [63:0] shiftreg;
reg [2:0] tx_state;
reg [IOW-1:0] tx_packet_sdr;
reg [7:0] io_valid_reg;
wire [IOW/2-1:0] tx_packet_ddr;
wire tx_wait_sync;
wire transfer_active;
wire [7:0] io_valid_next;
wire [IOW/2-1:0] ddr_data_even;
wire [IOW/2-1:0] ddr_data_odd;
wire dmode8;
wire dmode16;
wire dmode32;
wire dmode64;
wire io_nreset;
wire reload;
//########################################
//# STATE MACHINE
//########################################
assign dmode8 = (iowidth[1:0]==2'b00);
assign dmode16 = ((iowidth[1:0]==2'b01) & ~ddr_mode) |
(iowidth[1:0]==2'b00) & ddr_mode;
assign dmode32 = ((iowidth[1:0]==2'b10) & ~ddr_mode) |
(iowidth[1:0]==2'b01) & ddr_mode;
assign dmode64 = ((iowidth[1:0]==2'b11) & ~ddr_mode) |
(iowidth[1:0]==2'b10) & ddr_mode;
assign io_valid_next[7:0] = dmode8 ? {1'b0,io_valid_reg[7:1]} :
dmode16 ? {2'b0,io_valid_reg[7:2]} :
dmode32 ? {4'b0,io_valid_reg[7:4]} :
8'b0;
assign reload = ~transfer_active | dmode64 | (io_valid_next[7:0]==8'b0);
always @ (posedge io_clk or negedge io_nreset)
if(!io_nreset)
io_valid_reg[7:0] <= 'b0;
else if(reload)
io_valid_reg[7:0] <= io_valid[7:0];
else
io_valid_reg[7:0] <= io_valid_next[7:0];
assign transfer_active = |io_valid_reg[7:0];
//pipeline access signal
always @ (posedge io_clk or negedge io_nreset)
if(!io_nreset)
tx_access <= 1'b0;
else
tx_access <= transfer_active;
assign io_wait = tx_wait_sync | ~reload;
//########################################
//# SHIFT REGISTER (SHIFT DOWN)
//########################################
always @ (posedge io_clk)
if(reload)
shiftreg[63:0] <= io_packet[IOW-1:0];
else if(dmode8)//8 bit
shiftreg[63:0] <= {8'b0,shiftreg[IOW-1:8]};
else if(dmode16)//16 bit
shiftreg[63:0] <= {16'b0,shiftreg[IOW-1:16]};
else if(dmode32)//32 bit
shiftreg[63:0] <= {32'b0,shiftreg[IOW-1:32]};
//########################################
//# DDR OUTPUT
//########################################
// pipeline sdr to compensate for ddr
always @ (posedge io_clk)
tx_packet_sdr[IOW-1:0] <= shiftreg[IOW-1:0];
// ddr circuit (one stage pipeline delay!)
assign ddr_data_even[IOW/2-1:0] = shiftreg[IOW/2-1:0];
assign ddr_data_odd[IOW/2-1:0] = (iowidth[1:0]==2'b00) ? shiftreg[7:4] : //byte
(iowidth[1:0]==2'b01) ? shiftreg[15:8] : //short
(iowidth[1:0]==2'b10) ? shiftreg[31:16] : //word
shiftreg[63:32]; //double
oh_oddr#(.DW(IOW/2))
data_oddr (.out (tx_packet_ddr[IOW/2-1:0]),
.clk (io_clk),
.din1 (ddr_data_even[IOW/2-1:0]),
.din2 (ddr_data_odd[IOW/2-1:0]));
//select between ddr/sdr
assign tx_packet[IOW-1:0] = ddr_mode ? {{(IOW/2){1'b0}},tx_packet_ddr[IOW/2-1:0]}:
tx_packet_sdr[IOW-1:0];
//########################################
//# Synchronizers
//########################################
// synchronize reset to io clock
oh_rsync sync_reset(.nrst_out (io_nreset),
.clk (io_clk),
.nrst_in (nreset));
//synchronize wait
oh_dsync sync_wait(.nreset (io_nreset),
.clk (io_clk),
.din (tx_wait),
.dout (tx_wait_sync));
endmodule // mtx_io
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int a) { long long int pdt = 1, i = 0, t = 19; while (i++ < min(a, t)) pdt *= 2; return pdt; } int main() { long long int n, b, i, j, cnt = 0, k = 0; cin >> n >> b; long long int a[n], c[n]; b = power((b * 8) / n); for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < n; i++) { j = i + 1; while (j < n && a[j] == a[i]) j++; cnt++; c[k++] = j - i; i = j - 1; } if (cnt < b) cout << 0; else { long long int maxi = 0; for (i = 0; i < k; i++) { if (i > 0) c[i] += c[i - 1]; if (i - b >= 0) maxi = max(maxi, c[i] - c[i - b]); else if (!(i - b + 1)) maxi = max(maxi, c[i]); } cout << n - maxi << endl; } return 0; } |
#include <bits/stdc++.h> inline long long read() { long long x = 0, f = 1; char c = getchar(); for (; c > 9 || c < 0 ; c = getchar()) { if (c == - ) f = -1; } for (; c >= 0 && c <= 9 ; c = getchar()) { x = x * 10 + c - 0 ; } return x * f; } int dp[200005]; int a[85], r[85]; inline void work() { int n = read(), m = read(); dp[m + 1] = 0; for (int i = 1; i <= n; i++) a[i] = read(), r[i] = read(); for (int i = m; i; i--) { dp[i] = dp[i + 1] + 1; for (int j = 1; j <= n; j++) { if (a[j] >= i) { if (a[j] - r[j] <= i) { dp[i] = std::min(dp[i], dp[std::min(m + 1, a[j] + r[j] + 1)]); } else { dp[i] = std::min( dp[i], a[j] - r[j] - i + dp[std::min(m + 1, 2 * a[j] - i + 1)]); } } else { if (a[j] + r[j] >= i) { dp[i] = std::min(dp[i], dp[std::min(m + 1, a[j] + r[j] + 1)]); } } } } printf( %d n , dp[1]); } int main() { work(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Teske Virtual System
// Engineer: Lucas Teske
//
// Create Date: 20:23:28 07/04/2013
// Design Name: Video LVDS Serializer
// Module Name: video_lvds
// GitHub: https://github.com/racerxdl/LVDS-7-to-1-Serializer
//////////////////////////////////////////////////////////////////////////////////
module video_lvds(
input DotClock,
input HSync,
input VSync,
input DataEnable,
input [5:0] Red,
input [5:0] Green,
input [5:0] Blue,
output channel1_p,
output channel1_n,
output channel2_p,
output channel2_n,
output channel3_p,
output channel3_n,
output clock_p,
output clock_n
);
wire clk35, notclk35, c1,c2,c3,lvdsclk, rst_clk, DataClock;
wire [20:0] VideoData;
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel1_obuf (.I(c1), .O(channel1_p), .OB(channel1_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel2_obuf (.I(c2), .O(channel2_p), .OB(channel2_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel3_obuf (.I(c3), .O(channel3_p), .OB(channel3_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_clock_obuf (.I(lvdsclk), .O(clock_p), .OB(clock_n) );
lvds_clockgen clockgenerator (
.clk(DotClock),
.clk35(clk35),
.nclk35(notclk35),
.rstclk(rst_clk),
.dataclock(DataClock),
.lvdsclk(lvdsclk)
);
serializer channel1_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[6:0]),
.rst(rst_clk),
.out(c1)
);
serializer channel2_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[13:7]),
.rst(rst_clk),
.out(c2)
);
serializer channel3_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[20:14]),
.rst(rst_clk),
.out(c3)
);
assign VideoData[20:14] = {Blue[2],Blue[3],Blue[4],Blue[5],HSync,VSync,DataEnable};
assign VideoData[13:7] = {Green[1],Green[2],Green[3],Green[4],Green[5],Blue[0],Blue[1]};
assign VideoData[6:0] = {Red[0],Red[1],Red[2],Red[3],Red[4],Red[5],Green[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); inline int cmp(double x, double y = 0, double tol = 1e-8) { return (x <= y + tol) ? (x + tol < y) ? -1 : 0 : 1; } struct point { double x, y; point(double x = 0, double y = 0) : x(x), y(y) {} point operator+(point q) { return point(x + q.x, y + q.y); } point operator-(point q) { return point(x - q.x, y - q.y); } point operator*(double t) { return point(x * t, y * t); } point operator/(double t) { return point(x / t, y / t); } double operator*(point q) { return x * q.x + y * q.y; } double operator%(point q) { return x * q.y - y * q.x; } double mod() { return sqrt(x * x + y * y); } point rotate(double t) { return point(x * cos(t) - y * sin(t), x * sin(t) + y * cos(t)); } int cmp(point q) const { if (int t = ::cmp(x, q.x)) return t; return ::cmp(y, q.y); } bool operator==(point q) const { return cmp(q) == 0; } bool operator!=(point q) const { return cmp(q) != 0; } bool operator<(point q) const { return cmp(q) < 0; } static point pivot; }; point point::pivot; double poly_area(vector<point>& T) { double s = 0; int n = T.size(); for (int i = 0; i < n; i++) s += T[i] % T[(i + 1) % n]; return s / 2; } point line_intersect(point p, point q, point r, point s) { point a = q - p, b = s - r, c = point(p % q, r % s); return point(point(a.x, b.x) % c, point(a.y, b.y) % c) / (a % b); } vector<point> halfplane(vector<point>& p, pair<point, point> semiplano) { vector<point> q; point p1 = semiplano.first, p2 = semiplano.second; int n = p.size(); for (int i = 0; i < n; i++) { double c = (p2 - p1) % (p[i] - p1); double d = (p2 - p1) % (p[(i + 1) % n] - p1); if (cmp(c) >= 0) q.push_back(p[i]); if (cmp(c * d) < 0) q.push_back(line_intersect(p1, p2, p[i], p[(i + 1) % n])); } return q; } vector<point> semi_plano_cruzado(vector<pair<point, point> > semiplano) { vector<point> p; p.push_back(point(-1e9, -1e9)); p.push_back(point(-1e9, +1e9)); p.push_back(point(+1e9, +1e9)); p.push_back(point(+1e9, -1e9)); int n = semiplano.size(); for (int i = 0; i < n; i++) { p = halfplane(p, semiplano[i]); if (p.size() == 0) break; } return p; } int main() { double w, h, a; cin >> w >> h >> a; double gama = atan(w / h); double beta = atan(h / w); vector<point> p, q; p.push_back(point(-0.5 * w, -0.5 * h)); p.push_back(point(-0.5 * w, 0.5 * h)); p.push_back(point(0.5 * w, 0.5 * h)); p.push_back(point(0.5 * w, -0.5 * h)); a = a * Pi / 180; double teta = 0.5 * Pi + a - gama - beta; q.push_back(point(-0.5 * w, -0.5 * h)); q.push_back(point(-0.5 * w, 0.5 * h)); q.push_back(point(0.5 * w, 0.5 * h)); q.push_back(point(0.5 * w, -0.5 * h)); for (int i = 0; i < 4; i++) q[i] = q[i].rotate(teta); for (int i = 0; i < 4; i++) { p = halfplane(p, make_pair(q[(i + 1) % 4], q[i])); } printf( %.9lf n , fabs(poly_area(p))); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: ADRIAN CERVANTES SEGURA
//
// Create Date: 03.03.2016 01:49:40
// Design Name:
// Module Name: LUT_SHIFT
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LUT_SHIFT #(parameter P = 5) (
input wire CLK,
input wire EN_ROM1,
input wire [4:0] ADRS,
output reg [P-1:0] O_D
);
always @(posedge CLK)
if (EN_ROM1)
case (ADRS)
5'b00000: O_D <= 5'b00000;
5'b00001: O_D <= 5'b00000;
5'b00010: O_D <= 5'b00001;
5'b00011: O_D <= 5'b00010;
5'b00100: O_D <= 5'b00011;
5'b00101: O_D <= 5'b00100;
5'b00110: O_D <= 5'b00100;
5'b00111: O_D <= 5'b00101;
5'b01000: O_D <= 5'b00110;
5'b01001: O_D <= 5'b00111;
5'b01010: O_D <= 5'b01000;
5'b01011: O_D <= 5'b01001;
5'b01100: O_D <= 5'b01010;
5'b01101: O_D <= 5'b01011;
5'b01110: O_D <= 5'b01100;
5'b01111: O_D <= 5'b01101;
5'b10000: O_D <= 5'b01101;
5'b10001: O_D <= 5'b01110;
5'b10010: O_D <= 5'b01111;
5'b10011: O_D <= 5'b10000;
5'b10100: O_D <= 5'b10001;
5'b10101: O_D <= 5'b10010;
5'b10110: O_D <= 5'b10011;
5'b10111: O_D <= 5'b10100;
5'b11000: O_D <= 5'b10101;
5'b11001: O_D <= 5'b10110;
5'b11010: O_D <= 5'b10111;
5'b11011: O_D <= 5'b11000;
5'b11100: O_D <= 5'b11001;
5'b11101: O_D <= 5'b11010;
5'b11110: O_D <= 5'b11011;
5'b11111: O_D <= 5'b11100;
default: O_D <= 5'b00000;
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; namespace debug { void __(short x) { cout << x; } void __(int x) { cout << x; } void __(long long x) { cout << x; } void __(unsigned long long x) { cout << x; } void __(double x) { cout << x; } void __(long double x) { cout << x; } void __(char x) { cout << x; } void __(const char* x) { cout << x; } void __(const string& x) { cout << x; } void __(bool x) { cout << (x ? true : false ); } template <class P1, class P2> void __(const pair<P1, P2>& x) { __( ( ), __(x.first), __( , ), __(x.second), __( ) ); } template <class T> void __(const vector<T>& x) { __( { ); bool _ffs = 0; for (const auto& v : x) __(_ffs ? , : ), __(v), _ffs = 1; __( } ); } void screm() { __( n ); } template <class T1, class... T2> void screm(const T1& t1, const T2&... t2) { __(t1); if (sizeof...(t2)) __( | ), screm(t2...); else __( n ); } void pr() { __( n ); } template <class T1, class... T2> void pr(const T1& t1, const T2&... t2) { __(t1); if (sizeof...(t2)) __( ), pr(t2...); else __( n ); } } // namespace debug using namespace debug; long long h, m, k, ans, h1, h2, m1, m2, ms, mh, mmm; int main() { scanf( %lld%lld%lld%lld%lld%lld%lld , &h, &m, &k, &h1, &m1, &h2, &m2); long long sw = m - 1; while (sw) { if (sw % 10 != 0) ms++; sw /= 10; } sw = h - 1; while (sw) { if (sw % 10 != 0) mh++; sw /= 10; } int ch = max(0LL, k - ms - 1); long long mn = 1, hr = 1; for (int i = 0; i < k - 1; i++) mn *= 10; for (int i = 0; i < ch; i++) hr *= 10; if (h1 == h2 && m1 <= m2) { ans += (m2 / mn); if (m1 > 1) ans -= (m1 / mn); printf( %lld n , ans); return 0; } if (m1) ans += ((m - 1) / mn) - (m1 / mn); long long rr = h1; ans -= (h1 / hr); int flg = 0; if (m1) { h1++; m1 = 0; if (h1 == h) { h1 = 0; if (ms + mh >= k) ans++; } else if ((h1 / hr) != (rr / hr)) ans++, flg = 1; } if (m2) ans += (m2 / mn), m2 = 0; long long kek = (m - 1) / mn; if (h1 > h2) { ans += ((h - 1) / hr) + (h2 / hr) - flg; long long delta = (h - h1) + (h2); ans += delta * kek; if (ms + mh >= k) ans++; } else { ans += (rr / hr) - (h1 / hr) + (h2 / hr) + kek * (h2 - h1); } printf( %lld n , ans); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// 2D packed arrays
logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
logic [1:0] array_unpk [3:2][1:0];
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
initial begin
`checkh($dimensions (array_unpk), 3);
`ifndef VCS
`checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009
`endif
`checkh($bits (array_unpk), 2*2*2);
`checkh($low (array_unpk), 2);
`checkh($high (array_unpk), 3);
`checkh($left (array_unpk), 3);
`checkh($right(array_unpk), 2);
`checkh($increment(array_unpk), 1);
`checkh($size (array_unpk), 2);
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
integer slc_next;
// calculation of dimention sizes
always @ (posedge clk) begin
// slicing type counter
case (cnt[3:2])
2'd0 : begin slc_next = 0; end // full array
2'd1 : begin slc_next = 1; end // single array element
2'd2 : begin slc_next = 2; end // half array
default: begin slc_next = 0; end
endcase
slc <= slc_next;
// dimension counter
case (cnt[1:0])
2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end
2'd1 : begin dim <= 2; wdt <= WB; end
2'd2 : begin dim <= 3; wdt <= WC; end
default: begin dim <= 0; wdt <= 0; end
endcase
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
`endif
if (cnt[30:4]==1) begin
// big endian
if (slc==0) begin
// full array
`checkh($dimensions (array_bg), 3);
`checkh($bits (array_bg), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_bg, dim), wdt+1);
`checkh($right (array_bg, dim), 2 );
`checkh($low (array_bg, dim), 2 );
`checkh($high (array_bg, dim), wdt+1);
`checkh($increment (array_bg, dim), 1 );
`checkh($size (array_bg, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_bg[2]), 2);
`checkh($bits (array_bg[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_bg[2], dim-1), wdt+1);
`checkh($right (array_bg[2], dim-1), 2 );
`checkh($low (array_bg[2], dim-1), 2 );
`checkh($high (array_bg[2], dim-1), wdt+1);
`checkh($increment (array_bg[2], dim-1), 1 );
`checkh($size (array_bg[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_bg[WA/2+1:2]), 3);
`checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_bg[WA/2+1:2], dim), wdt+1);
`checkh($right (array_bg[WA/2+1:2], dim), 2 );
`checkh($low (array_bg[WA/2+1:2], dim), 2 );
`checkh($high (array_bg[WA/2+1:2], dim), wdt+1);
`checkh($increment (array_bg[WA/2+1:2], dim), 1 );
`checkh($size (array_bg[WA/2+1:2], dim), wdt);
end
`endif
end
end else if (cnt[30:4]==2) begin
// little endian
if (slc==0) begin
// full array
`checkh($dimensions (array_lt), 3);
`checkh($bits (array_lt), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_lt, dim), 2 );
`checkh($right (array_lt, dim), wdt+1);
`checkh($low (array_lt, dim), 2 );
`checkh($high (array_lt, dim), wdt+1);
`checkh($increment (array_lt, dim), -1 );
`checkh($size (array_lt, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_lt[2]), 2);
`checkh($bits (array_lt[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_lt[2], dim-1), 2 );
`checkh($right (array_lt[2], dim-1), wdt+1);
`checkh($low (array_lt[2], dim-1), 2 );
`checkh($high (array_lt[2], dim-1), wdt+1);
`checkh($increment (array_lt[2], dim-1), -1 );
`checkh($size (array_lt[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_lt[2:WA/2+1]), 3);
`checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_lt[2:WA/2+1], dim), 2 );
`checkh($right (array_lt[2:WA/2+1], dim), wdt+1);
`checkh($low (array_lt[2:WA/2+1], dim), 2 );
`checkh($high (array_lt[2:WA/2+1], dim), wdt+1);
`checkh($increment (array_lt[2:WA/2+1], dim), -1 );
`checkh($size (array_lt[2:WA/2+1], dim), wdt );
end
`endif
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 100; vector<int> G[MAXN]; map<int, int> cnt; bool vis[MAXN]; int sz; int cN, c[MAXN], b[MAXN]; int dp[MAXN]; void dfs(int u) { vis[u] = true; sz++; for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (!vis[v]) dfs(v); } } inline int smin(int &a, int b) { return a = min(a, b); } bool lucky(int x) { while (x) { if (x % 10 != 7 && x % 10 != 4) return false; x /= 10; } return true; } int main() { ios::sync_with_stdio(false); cout.tie(0); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; G[a].push_back(b); G[b].push_back(a); } for (int u = 0; u < n; u++) if (!vis[u]) { sz = 0; dfs(u); cnt[sz]++; } for (map<int, int>::iterator iter = cnt.begin(); iter != cnt.end(); iter++) { int x = iter->first, pw = 1; int temp = iter->second; while (temp >= pw) { c[cN++] = x * pw, b[cN - 1] = pw, temp -= pw; pw *= 2; } if (temp) { c[cN++] = x * temp; b[cN - 1] = temp; } } fill(dp, dp + MAXN, -1u / 4); dp[0] = 0; for (int i = 0; i < cN; i++) { int val = c[i]; for (int j = MAXN - 1; j >= 0; j--) if (val + j < MAXN) smin(dp[j + val], dp[j] + b[i]); } int ans = -1u / 4; for (int i = 1; i < MAXN; i++) if (lucky(i)) smin(ans, dp[i]); cout << (ans < MAXN ? ans - 1 : -1) << endl; } |
/*main function
1)parsing packet header
2)fetch the keys from packet header include l3_protocol ,tos,l4_protocol,source ip,derection ip,source port derection port ,tcp_flag icmp layer_type and icmp code
3)combine keys to prepad
*/
/******************************* the prepad format********************************************/
/*
four pats prepad format:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
ipv4_uc|ipv4_mc|umknown|arp|rarp|mpls_uc|ttl 0or1|option|ppp_ctrl|ipv6_mc|fragment|subsequent|isis|ipv6_link_local|drop|out_vlan|in_vlan|L3infhandle|local__port_port_index|l2_stake|pad2|l3_stake|net_diagnosis|pad|timestamp_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
timestamp_6B|L3_protocol|Tos|L4_protocol|source ip|derection ip_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
derection ip_2B|source port|derection port|tcp_flag|pad_9B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
pad_16B
*/
//*********************the structure of packet parsing******************************************/
/*
|--->TCP
| --->IP----
| |----ICMP
ethernet----
|
| --->unknown
*/
`timescale 1 ps / 1 ps
module CLASSIFY(
input clk,
input reset,
input in_ingress_key_wr,// the key write request of inputctrl to classfy
input [133:0] in_ingress_key,// the key of inputctrl to classfy
input in_ingress_valid_wr,//the valid flag write request of inputctrl to classfy
input in_ingress_valid,//the valid flag of inputctrl to classfy
output out_ingress_key_almostfull,//the valid fifo almostfull signal of classfy to inputctrl
output reg out_offset_key_wr,// the key write request of classfy to inputctrl
output reg [133:0] out_offset_key,// the key of classfy to inputctrl
output reg out_offset_valid,// the valid flag of classfy to inputctrl
output reg out_offset_valid_wr,//the valid flag write request of classfy to inputctrl
input in_offset_key_almostfull//the valid fifo almostfull signal of inputctrl to classfy
);
reg [2:0] state;
wire in_ingress_valid_q; //the output valid flag from the valid flag fifo
wire in_ingress_valid_empty;//the empty signal of the valid flag fifo
reg out_ingress_valid_rd; //the read request of the valid flag fifo
wire [7:0] out_ingress_key_usedw;//the usedw signal of the key fifo
assign out_ingress_key_almostfull = out_ingress_key_usedw[7];
reg out_ingress_key_rd;//the read request of the key fifo
wire [133:0]in_ingress_key_q;//the output key from the valid flag fifo
reg is_unknown;
reg [7:0]tos;
reg [15:0]l3_protocol;
reg [7:0]l4_protocol;
reg [31:0]sip;
reg [31:0]dip;
reg [15:0]sport;
reg [15:0]dport;
reg [7:0]tcp_flag;
reg [7:0]layer_type;
reg [7:0]code;
reg tcp_icmp;
parameter idle=3'd0,
l2=3'd1,
l3=3'd2,
l4=3'd3,
prepad1=3'd4,
prepad2=3'd5,
prepad3=3'd6,
prepad4=3'd7;
always @(posedge clk or negedge reset) begin
if(!reset)begin
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
state<=idle;
end
else begin
case(state)
idle:begin// according to the in_offset_key_almostfull and in_ingress_valid_empty signals to judge whether or not the classfy module can receive packet from inputctrl
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
if(in_offset_key_almostfull==1'b0 && in_ingress_valid_empty==1'b0 )begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
state<=l2;
end
else begin
state<=idle;
end
end
l2: begin//according to the layer_type field of the ethrnet hearder to parsing packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
state<=l3;
if(in_ingress_key_q[31:16]==16'h0800 &&in_ingress_key_q[11:8] ==4'd5)//judge the packet whether or not a IP packet and its header length equal the 20bytes
begin
l3_protocol<=in_ingress_key_q[31:16];
tos<=in_ingress_key_q[7:0];
end
else
begin
is_unknown<=1'b1;
end
end
l3:begin//according to the protocol field of the IP hearder to judge the packet whether or not a TCP packet or ICMP packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=l4;
end
else if(in_ingress_key_q[71:64]==8'd6|| in_ingress_key_q[71:64]==8'd1)//judge the packet whether or not a TCP packet or ICMP packet
begin
l4_protocol<=in_ingress_key_q[71:64];
sip<=in_ingress_key_q[47:16];
dip[31:16]<=in_ingress_key_q[15:0];
end
else
begin
is_unknown<=1'b1;
end
state<=l4;
end
l4:begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=prepad1;
end
else if(l4_protocol==8'd6)
begin
dip[15:0]<=in_ingress_key_q[127:112];
sport<=in_ingress_key_q[111:96];
dport<=in_ingress_key_q[95:80];
tcp_flag<=in_ingress_key_q[7:0];
state<=prepad1;
end
else if(l4_protocol==8'd1)
begin
dip[15:0]<=in_ingress_key_q[127:112];
layer_type<=in_ingress_key_q[111:104];
code<=in_ingress_key_q[103:96];
tcp_flag<=8'b0;
end
else
begin
is_unknown<=1'b1;
end
state<=prepad1;
end
prepad1:begin//to structure the first pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b010000,3'b001,125'b0};
state<=prepad2;
end
prepad2:begin//to structure the second pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b110000,48'b0,l3_protocol,tos,l4_protocol,sip,dip[31:16]};
state<=prepad3;
end
prepad3:begin//to structure the third pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
if(tcp_icmp==1'b0)
begin
out_offset_key<={6'b110000,dip[15:0],sport,dport,tcp_flag,72'b0};
end
else
begin
out_offset_key<={6'b110000,dip[15:0],layer_type,code,96'b0};
end
state<=prepad4;
end
prepad4:begin//to structure the fourth pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b100000,128'b0};
out_offset_valid<=1'b1;
out_offset_valid_wr<=1'b1;
state<=idle;
end
endcase
end
end
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_key_input (
.aclr(!reset),
.data(in_ingress_key),
.clock(clk),
.rdreq(out_ingress_key_rd),
.wrreq(in_ingress_key_wr),
.q(in_ingress_key_q),
.usedw(out_ingress_key_usedw)
);
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, min, max, i, t, f = 0; cin >> n >> m; cin >> min; max = min; for (i = 1; i < n; i++) { cin >> t; if (t > max) max = t; else if (t < min) min = t; } if (2 * min > max) max = 2 * min; for (i = 0; i < m; i++) { cin >> t; if (t <= max) f = 1; } if (f == 1) cout << -1 n ; else cout << max << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[m]; for (int i = 0; i < m; i++) { cin >> a[i]; if (a[i] > n - i) { cout << -1 << endl; return 0; } } long long suf_sum[m + 1]; suf_sum[m] = 0; for (int i = m - 1; i >= 0; i--) { suf_sum[i] = suf_sum[i + 1] + a[i]; } if (suf_sum[0] < n) { cout << -1 << endl; return 0; } for (int i = 0; i < m; i++) { cout << max((long long)i + 1, n - suf_sum[i] + 1) << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<int, int> nrs; for (int i = 0; i < n; i++) { int x; cin >> x; nrs[x]++; } int max_times = nrs.begin()->second; for (auto it : nrs) max_times = max(it.second, max_times); if (max_times > (n + 1) / 2) cout << NO << endl; else cout << YES << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; int left0 = 0; for (int i = 0; i < n; i++) { if (s[i] == 0 ) { left0 = i + 1; } else { break; } } int right1 = 0; for (int i = n - 1; i >= 0; i--) { if (s[i] == 1 ) { right1 = right1 + 1; } else { break; } } for (int i = 0; i < left0; i++) { cout << 0; } if (left0 + right1 == n - 1 && (left0 != 0 || right1 != 0)) { cout << s[left0]; } else if (left0 + right1 != n) { cout << 0; } for (int i = 0; i < right1; i++) { cout << 1; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000 + 2; double x[4], y[4], r[4]; double dx, dy; double Fun(double dx, double dy) { double ap[4]; for (int i = 0; i < 3; i++) { ap[i] = sqrt(((x[i] - dx) * (x[i] - dx)) + ((y[i] - dy) * (y[i] - dy))) / r[i]; } double res = 0.0; for (int i = 0; i < 3; i++) { res += ((ap[i] - ap[(i + 1) % 3]) * (ap[i] - ap[(i + 1) % 3])); } return res; } int main() { dx = dy = 0.0; for (int i = 0; i < 3; i++) { scanf( %lf%lf%lf , &x[i], &y[i], &r[i]); dx += x[i] / 3; dy += y[i] / 3; } double i = 1.0; while (i > 1e-5) { if (Fun(dx + i, dy) < Fun(dx, dy)) dx += i; else if (Fun(dx - i, dy) < Fun(dx, dy)) dx -= i; else if (Fun(dx, dy + i) < Fun(dx, dy)) dy += i; else if (Fun(dx, dy - i) < Fun(dx, dy)) dy -= i; else i *= 0.75; } if (Fun(dx, dy) < 1e-5) printf( %.5lf %.5lf n , dx, dy); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:47:01 05/24/2016
// Design Name:
// Module Name: Contador_AD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD(
input rst,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 6;
parameter X = 59;
always @(posedge clk)
if (en == 2'd0)
begin
if (rst)
Cuenta <= 0;
else if (Cambio == 8'h75 && got_data)
begin
if (Cuenta == X)
Cuenta <= 0;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 0)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else Cuenta <= Cuenta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int INF = 1e9; const long long mod = 1e9 + 7; bool dp[105][55][2][2][205]; string s; int n, sz, realans; int offset(int x) { return x + 100; } bool f(int idx, int sisa, bool flip, bool arah, int ans) { if (idx == sz + 1) { if (sisa == 0) { realans = max(realans, abs(ans)); } return 1; } bool &res = dp[idx][sisa][flip][arah][offset(ans)]; if (res == 1) return res; char now = s[idx - 1]; if (flip) { if (now == F ) now = T ; else now = F ; } if (now == F ) { res = f(idx + 1, sisa, 0, arah, ans + (arah ? 1 : -1)); if (sisa) res = f(idx, sisa - 1, !flip, arah, ans); } else if (now == T ) { res = f(idx + 1, sisa, 0, !arah, ans); if (sisa) res = f(idx, sisa - 1, !flip, arah, ans); } return res = 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> s; cin >> n; sz = s.size(); f(1, n, 0, 1, 0); cout << realans << endl; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; long long int fastPow(long long int x, long long int y) { long long int p = mod; long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int arr[200005]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cin.tie(0), cout.tie(0), cout.precision(15); long long int n, m, A, res = 1; cin >> n >> m >> A; for (long long int i = 1; i <= m; i++) { cin >> arr[i]; } res = fastPow(A, n - 2 * arr[m]); for (long long int i = m - 1; i >= 0; i--) { long long int tmp = fastPow(A, arr[i + 1] - arr[i]) % mod; long long int tmp2 = (tmp * ((tmp - 1 + mod) % mod) / 2) % mod; long long int tmp3 = (tmp + tmp2) % mod; res = (res * tmp3) % mod; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int a[N], n, ans[N], b[N]; int main() { scanf( %d , &n); if (n == 1) { printf( 1 n ); return 0; } for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { b[0] = 0; int to = (int)sqrt((double)a[i]), k = 0; for (int j = 1; j <= to; j++) if (a[i] % j == 0) { if (j > 1) b[++b[0]] = j, k = max(k, ans[j]); if (j * j != a[i]) b[++b[0]] = a[i] / j, k = max(k, ans[a[i] / j]); } for (int j = 1; j <= b[0]; j++) ans[b[j]] = max(ans[b[j]], k + 1); } for (int i = 1; i <= (int)1e5; i++) ans[0] = max(ans[0], ans[i]); printf( %d n , ans[0]); return 0; } |
`ifdef __ICARUS__
`define SUPPORT_REAL_MODULUS_IN_IVTEST
`endif
module test();
function real pre_inc(input real x);
begin
++x;
pre_inc = x;
end
endfunction
function real pre_dec(input real x);
begin
--x;
pre_dec = x;
end
endfunction
function real post_inc(input real x);
begin
x++;
post_inc = x;
end
endfunction
function real post_dec(input real x);
begin
x--;
post_dec = x;
end
endfunction
localparam pre_inc_5 = pre_inc(5);
localparam pre_dec_5 = pre_dec(5);
localparam post_inc_5 = post_inc(5);
localparam post_dec_5 = post_dec(5);
function real add2(input real x);
begin
x += 2;
add2 = x;
end
endfunction
function real sub2(input real x);
begin
x -= 2;
sub2 = x;
end
endfunction
function real mul2(input real x);
begin
x *= 2;
mul2 = x;
end
endfunction
function real div2(input real x);
begin
x /= 2;
div2 = x;
end
endfunction
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
function real mod2(input real x);
begin
x %= 2;
mod2 = x;
end
endfunction
`endif
localparam add2_5 = add2(5);
localparam sub2_5 = sub2(5);
localparam mul2_5 = mul2(5);
localparam div2_5 = div2(5);
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
localparam mod2_5 = mod2(5);
`endif
function real add3(input real x);
begin
add3 = x;
add3 += 3;
end
endfunction
function real sub3(input real x);
begin
sub3 = x;
sub3 -= 3;
end
endfunction
function real mul3(input real x);
begin
mul3 = x;
mul3 *= 3;
end
endfunction
function real div4(input real x);
begin
div4 = x;
div4 /= 4;
end
endfunction
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
function real mod3(input real x);
begin
mod3 = x;
mod3 %= 3;
end
endfunction
`endif
localparam add3_5 = add3(5);
localparam sub3_5 = sub3(5);
localparam mul3_5 = mul3(5);
localparam div4_5 = div4(5);
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
localparam mod3_5 = mod3(5);
`endif
reg failed = 0;
initial begin
$display("pre_inc_5 = %0f", pre_inc_5);
if (pre_inc_5 != pre_inc(5)) failed = 1;
if (pre_inc_5 != 6.0) failed = 1;
$display("pre_dec_5 = %0f", pre_dec_5);
if (pre_dec_5 != pre_dec(5)) failed = 1;
if (pre_dec_5 != 4.0) failed = 1;
$display("post_inc_5 = %0f", post_inc_5);
if (post_inc_5 != post_inc(5)) failed = 1;
if (post_inc_5 != 6.0) failed = 1;
$display("post_dec_5 = %0f", post_dec_5);
if (post_dec_5 != post_dec(5)) failed = 1;
if (post_dec_5 != 4.0) failed = 1;
$display("add2_5 = %0f", add2_5);
if (add2_5 != add2(5)) failed = 1;
if (add2_5 != 7.0) failed = 1;
$display("sub2_5 = %0f", sub2_5);
if (sub2_5 != sub2(5)) failed = 1;
if (sub2_5 != 3.0) failed = 1;
$display("mul2_5 = %0f", mul2_5);
if (mul2_5 != mul2(5)) failed = 1;
if (mul2_5 != 10.0) failed = 1;
$display("div2_5 = %0f", div2_5);
if (div2_5 != div2(5)) failed = 1;
if (div2_5 != 2.5) failed = 1;
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
$display("mod2_5 = %0f", mod2_5);
if (mod2_5 != mod2(5)) failed = 1;
if (mod2_5 != 1.0) failed = 1;
`endif
$display("add3_5 = %0f", add3_5);
if (add3_5 != add3(5)) failed = 1;
if (add3_5 != 8.0) failed = 1;
$display("sub3_5 = %0f", sub3_5);
if (sub3_5 != sub3(5)) failed = 1;
if (sub3_5 != 2.0) failed = 1;
$display("mul3_5 = %0f", mul3_5);
if (mul3_5 != mul3(5)) failed = 1;
if (mul3_5 != 15.0) failed = 1;
$display("div4_5 = %0f", div4_5);
if (div4_5 != div4(5)) failed = 1;
if (div4_5 != 1.25) failed = 1;
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
$display("mod3_5 = %0f", mod3_5);
if (mod3_5 != mod3(5)) failed = 1;
if (mod3_5 != 2.0) failed = 1;
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-8; const long double PI = 3.1415926535897932384626433832795; const long double E = 2.7182818284; const int INF = 1000000000; const int inf = 100000; int main(void) { int n, m, i, j; char c; scanf( %d%d , &n, &m); char a[n + 2][m + 2]; c = getchar(); for (int i = 0; i < int(n); i++) { for (int j = 0; j < int(m); j++) { scanf( %c , &a[i][j]); } c = getchar(); } int tab[n + 2][m + 2]; for (int i = 0; i < int(n); i++) { int t = inf; for (int j = 0; j < int(2 * m); j++) { if (a[i][j % m] == 1 ) { tab[i][j % m] = 0; t = 1; } else { tab[i][j % m] = t; if (t != inf) t++; } } } for (int i = 0; i < int(n); i++) { int t = inf; for (j = 2 * m - 1; j >= 0; j--) { if (a[i][j % m] == 1 ) { tab[i][j % m] = 0; t = 1; } else { tab[i][j % m] = min(tab[i][j % m], t); if (t != inf) t++; } } } int res = -1; for (int i = 0; i < int(m); i++) { int sum = 0; for (int j = 0; j < int(n); j++) { if (tab[j][i] == inf) { printf( -1 n ); return 0; } sum += tab[j][i]; } if (sum < res || res == -1) res = sum; } cout << res; return 0; } |
// 32-bit adder
// Using Carry Lookahead adders
module adder
(
input wire [31:0] op1,
input wire [31:0] op2,
input wire cin,
output wire [31:0] sum,
output wire carry,
output wire v_flag
);
wire[6:0] cout;
wire[7:0] flag_v;
assign v_flag = flag_v[7];
carry_lookahead_adder CLA1(op1[3:0], op2[3:0], cin, sum[3:0], cout[0], flag_v[0]);
carry_lookahead_adder CLA2(op1[7:4], op2[7:4], cout[0], sum[7:4], cout[1], flag_v[1]);
carry_lookahead_adder CLA3(op1[11:8], op2[11:8], cout[1], sum[11:8], cout[2], flag_v[2]);
carry_lookahead_adder CLA4(op1[15:12], op2[15:12], cout[2], sum[15:12], cout[3], flag_v[3]);
carry_lookahead_adder CLA5(op1[19:16], op2[19:16], cout[3], sum[19:16], cout[4], flag_v[4]);
carry_lookahead_adder CLA6(op1[23:20], op2[23:20], cout[4], sum[23:20], cout[5], flag_v[5]);
carry_lookahead_adder CLA7(op1[27:24], op2[27:24], cout[5], sum[27:24], cout[6], flag_v[6]);
carry_lookahead_adder CLA8(op1[31:28], op2[31:28], cout[6], sum[31:28], carry, flag_v[7]);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T pow2(T a) { return a * a; } template <class T> inline bool mineq(T a, T b) { if (a > b) { a = b; return true; } return false; } void print(long long a) { string str; while (a) { str.push_back(a % 10 + 0 ); a /= 10; } while (str.size() != 9) str.push_back( 0 ); reverse(str.begin(), str.end()); cout << str; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long a, b, mod; cin >> a >> b >> mod; long long t = (long long)1e9 % mod, n = -t; if (a > 1e7 + 10) a = 1e7 + 10; for (int i = 0; i < a + 1; i++) { n += t; if (n > mod) n -= mod; if (n + b < mod && n != 0) { cout << 1 ; print(i); return 0; } } cout << 2; } |
#include <bits/stdc++.h> using namespace std; long long x, off = 10; vector<long long> vec[15]; inline long long mul(long long a, long long b) { bool neg = false; long long res = 0; if (b < 0) { neg = true; b = -b; } while (b) { if (b & 1) res = (res + a) % off; a = (a + a) % off; b >>= 1; } return neg ? (off - res) % off : res; } inline pair<long long, long long> fib(long long n) { if (!n) return make_pair(0, 1); if (n & 1) { pair<long long, long long> res = fib(n - 1); return make_pair(res.second, (res.first + res.second) % off); } pair<long long, long long> res = fib(n >> 1); return make_pair( mul(res.first, 2 * res.second - res.first), (mul(res.first, res.first) + mul(res.second, res.second)) % off); } int main() { scanf( %lld , &x); for (int i = 0; i < 60; i++) { if (fib(i).first == x % off) vec[0].push_back(i); } long long step = 60; for (int i = 0; i < 12; i++) { off *= 10; for (long long y : vec[i]) { for (int j = 0; j < 10; j++) { if (fib(y + j * step).first == x % off) vec[i + 1].push_back(y + j * step); } } step *= 10; } if (!vec[12].size()) printf( -1 n ); else printf( %lld n , *min_element(vec[12].begin(), vec[12].end())); return 0; } |
#include <bits/stdc++.h> using namespace std; const int NMax = 101000; int N; vector<pair<int, int> > A, B, C, D; bool cmp1(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return 1; if (a.first > b.first) return 0; if (a.second < b.second) return 1; return 0; } bool cmp2(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return 1; if (a.first > b.first) return 0; if (a.second > b.second) return 1; return 0; } bool cmp3(pair<int, int> a, pair<int, int> b) { if (a.first > b.first) return 1; if (a.first < b.first) return 0; if (a.second > b.second) return 1; return 0; } bool cmp4(pair<int, int> a, pair<int, int> b) { if (a.first > b.first) return 1; if (a.first < b.first) return 0; if (a.second < b.second) return 1; return 0; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { int first, second; scanf( %d%d , &first, &second); if (first >= 0 && second >= 0) A.push_back(make_pair(first, second)); else if (first >= 0 && second <= 0) B.push_back(make_pair(first, second)); else if (first <= 0 && second <= 0) C.push_back(make_pair(first, second)); else D.push_back(make_pair(first, second)); } int ret = 0; for (int i = 0; i < A.size(); i++) { if (A[i].first) ret += 2; if (A[i].second) ret += 2; ret += 2; } for (int i = 0; i < B.size(); i++) { if (B[i].first) ret += 2; if (B[i].second) ret += 2; ret += 2; } for (int i = 0; i < C.size(); i++) { if (C[i].first) ret += 2; if (C[i].second) ret += 2; ret += 2; } for (int i = 0; i < D.size(); i++) { if (D[i].first) ret += 2; if (D[i].second) ret += 2; ret += 2; } printf( %d n , ret); sort(A.begin(), A.end(), cmp1); for (int i = 0; i < A.size(); i++) { if (A[i].first) printf( 1 %d R n , A[i].first); if (A[i].second) printf( 1 %d U n , A[i].second); printf( 2 n ); if (A[i].second) printf( 1 %d D n , A[i].second); if (A[i].first) printf( 1 %d L n , A[i].first); printf( 3 n ); } sort(B.begin(), B.end(), cmp2); for (int i = 0; i < B.size(); i++) { if (B[i].first) printf( 1 %d R n , B[i].first); if (B[i].second) printf( 1 %d D n , -B[i].second); printf( 2 n ); if (B[i].second) printf( 1 %d U n , -B[i].second); if (B[i].first) printf( 1 %d L n , B[i].first); printf( 3 n ); } sort(C.begin(), C.end(), cmp3); for (int i = 0; i < C.size(); i++) { if (C[i].first) printf( 1 %d L n , -C[i].first); if (C[i].second) printf( 1 %d D n , -C[i].second); printf( 2 n ); if (C[i].second) printf( 1 %d U n , -C[i].second); if (C[i].first) printf( 1 %d R n , -C[i].first); printf( 3 n ); } sort(D.begin(), D.end(), cmp4); for (int i = 0; i < D.size(); i++) { if (D[i].first) printf( 1 %d L n , -D[i].first); if (D[i].second) printf( 1 %d U n , D[i].second); printf( 2 n ); if (D[i].second) printf( 1 %d D n , D[i].second); if (D[i].first) printf( 1 %d R n , -D[i].first); printf( 3 n ); } return 0; } |
#include <bits/stdc++.h> using ul = std::uint32_t; using li = std::int32_t; using ull = std::uint64_t; using ll = std::int64_t; std::vector<ul> v; std::string s; int main() { std::getline(std::cin, s); std::stringstream ss(s); while (std::getline(ss, s, , )) { std::stringstream ss(s); ul t; ss >> t; v.push_back(t); } std::sort(v.begin(), v.end()); bool flag = false; for (ul i = 0, j = 0; i != v.size(); i = j) { for (++j; j != v.size() && v[j - 1] + 1 >= v[j]; ++j) ; if (flag) { std::putchar( , ); } flag = true; if (v[j - 1] == v[i]) { std::printf( %u , v[i]); } else { std::printf( %u-%u , v[i], v[j - 1]); } } std::putchar( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a[60], b[60]; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; cin >> m; for (int i = 0; i < m; i++) cin >> b[i]; int BG = -1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!(b[j] % a[i])) { if (b[j] / a[i] > BG) { BG = b[j] / a[i]; } } } } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!(b[j] % a[i]) && b[j] / a[i] == BG) { ans++; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 25; const int mo = 1000000007; const int inf = (int)1e9; inline int IN() { char ch; (ch = getchar()); int f = 0, x = 0; for (; ((ch) == n || (ch) == r || (ch) == t || (ch) == ); (ch = getchar())) ; if (ch == - ) f = 1, (ch = getchar()); for (; !((ch) == n || (ch) == r || (ch) == t || (ch) == ); (ch = getchar())) x = x * 10 + ch - 0 ; return (f) ? (-x) : (x); } int Pow(int x, int y, int p) { int A = 1; for (; y; y >>= 1, x = (long long)x * x % p) if (y & 1) A = (long long)A * x % p; return A; } int n, m, laba[N], labb[N], visa[N], visb[N], tim, mat[N], ans; int w[N][N], a[N][N], b[N][N], c[N][N], tot_done; bool extend(int x) { if (!x) return 1; visa[x] = tim; for (int i = (int)1; i <= (int)n; i++) { if (visb[i] != tim && laba[x] + labb[i] == w[x][i]) { visb[i] = tim; if (extend(mat[i])) { mat[i] = x; return 1; } } } return 0; } void change() { int delta = inf; for (int i = (int)1; i <= (int)n; i++) if (visa[i] == tim) for (int j = (int)1; j <= (int)n; j++) if (visb[j] != tim) { delta = min(delta, laba[i] + labb[j] - w[i][j]); } for (int i = (int)1; i <= (int)n; i++) if (visa[i] == tim) laba[i] -= delta; for (int i = (int)1; i <= (int)n; i++) if (visb[i] == tim) labb[i] += delta; } int KM() { for (int i = (int)1; i <= (int)n; i++) visa[i] = visb[i] = mat[i] = 0; for (int i = (int)1; i <= (int)n; i++) laba[i] = w[i][0], labb[i] = 0; tim = 0; for (int i = (int)1; i <= (int)n; i++) { for (;;) { ++tim; if (extend(i)) break; change(); } } int re = 0; for (int i = (int)1; i <= (int)n; i++) re += w[mat[i]][i]; return re; } void dfs(int x, int cnt) { int now = KM(); if (now <= ans) return; if (x == n) { ans = now; return; } ++tot_done; if (tot_done >= 1e5) return; ++x; if (m - cnt < n - x + 1) { for (int i = (int)0; i <= (int)n; i++) w[x][i] = a[x][i]; dfs(x, cnt); } if (cnt < m) { for (int i = (int)0; i <= (int)n; i++) w[x][i] = b[x][i]; dfs(x, cnt + 1); } for (int i = (int)0; i <= (int)n; i++) w[x][i] = c[x][i]; } int main() { scanf( %d , &n); m = n >> 1; for (int i = (int)1; i <= (int)n; i++) for (int j = (int)1; j <= (int)n; j++) { a[i][j] = IN(); a[i][0] = max(a[i][0], a[i][j]); } for (int i = (int)1; i <= (int)n; i++) for (int j = (int)1; j <= (int)n; j++) { b[i][j] = IN(); b[i][0] = max(b[i][0], b[i][j]); } for (int i = (int)1; i <= (int)n; i++) for (int j = (int)1; j <= (int)n; j++) { w[i][j] = c[i][j] = max(a[i][j], b[i][j]); w[i][0] = c[i][0] = max(w[i][0], c[i][j]); } dfs(0, 0); printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; constexpr int power(int x, int e) { return e ? x * power(x, e - 1) : 1; } template <typename T> void transpose(std::vector<std::vector<T>>& M) { auto tmp = M; M.resize(tmp[0].size()); for (auto& row : M) row.resize(tmp.size()); for (int i = 0; i < (int)M.size(); i++) { for (int j = 0; j < (int)M[0].size(); j++) { M[i][j] = tmp[j][i]; } } } class FFT { public: using cd = std::complex<double>; using vcd = std::vector<cd>; using vvcd = std::vector<vcd>; static int get_lg(int x) { return x ? 32 - __builtin_clz(x - 1) : 0; } static void precompute(int lg) { int size = 1 << lg; if ((int)reverse.size() <= lg) { reverse.resize(lg + 1); ws.resize(lg + 1); } if (reverse[lg].empty()) { reverse[lg].assign(size, 0); for (int i = 1, j = 0; i < size; i++) { int bit = size >> 1; for (; j & bit; bit >>= 1) j ^= bit; j ^= bit; reverse[lg][i] = j; } } if (ws[lg - 1].empty()) { ws[lg - 1].resize(size >> 1); for (int i = 0; i < (size >> 1); i++) { double ang = 2 * PI * i / size; ws[lg - 1][i] = {cos(ang), sin(ang)}; } for (int j = lg - 2; j >= 0 && ws[j].empty(); j--) { int sz_level = ws[j + 1].size() >> 1; ws[j].resize(sz_level); for (int i = 0; i < sz_level; i++) ws[j][i] = ws[j + 1][i << 1]; } } } static void fft(vcd& a, bool inv) { int lg = get_lg(a.size()); int size = 1 << lg; precompute(lg); auto& rev = reverse[lg]; for (int i = 0; i < size; i++) { if (i < rev[i]) swap(a[i], a[rev[i]]); } for (int k = 0; k < lg; k++) { int len = 1 << k; auto& w = ws[k]; for (int i = 0; i < size; i += 2 * len) { for (int j = 0; j < len; j++) { cd u = a[i + j], v = a[i + j + len] * w[j]; a[i + j] = u + v; a[i + j + len] = u - v; } } } if (inv) { for (cd& x : a) x /= size; std::reverse(a.begin() + 1, a.end()); } } static void multiply(vcd& fa, vcd& fb) { int result_size = fa.size() + fb.size() + 1; int size = 1 << get_lg(result_size); fa.resize(size); fb.resize(size); fft(fa, false); fft(fb, false); for (int i = 0; i < size; i++) fa[i] *= fb[i]; fft(fa, true); fa.resize(result_size); } template <typename T> static std::vector<long long> multiply_brute_force(std::vector<T> const& a, std::vector<T> const& b) { vector<long long> result(a.size() + b.size() + 1, 0); for (auto i = 0u; i < a.size(); i++) { for (auto j = 0u; j < b.size(); j++) { result[i + j] += a[i] * b[j]; } } return result; } template <typename T> static std::vector<long long> multiply(std::vector<T> const& a, std::vector<T> const& b) { vector<long long> result; int result_size = a.size() + b.size() + 1; if (result_size <= 0) { result = multiply_brute_force(a, b); } else { vcd fa(a.begin(), a.end()), fb(b.begin(), b.end()); multiply(fa, fb); result.resize(result_size); for (int i = 0; i < result_size; i++) result[i] = std::llround(fa[i].real()); } return result; } private: static std::vector<std::vector<int>> reverse; static std::vector<vcd> ws; static const double PI; }; std::vector<std::vector<int>> FFT::reverse; std::vector<FFT::vcd> FFT::ws; const double FFT::PI = std::acos(-1); class BigInteger { public: BigInteger(long long x = 0) { if (x > 0) sign = 1; else if (x == 0) sign = 0; else sign = -1; x *= sign; while (x) { data.push_back(x % BASE); x /= BASE; } } BigInteger& operator+=(BigInteger const& o) { data.resize(max(data.size(), o.data.size()) + 1, 0); int carry = 0; for (auto i = 0u; i < o.data.size() || carry; i++) { if (i < o.data.size()) carry += o.data[i]; if (i < data.size()) carry += data[i]; data[i] = carry % BASE; carry /= BASE; } pop_zeros(); return *this; } BigInteger& operator*=(int o) { if (o == 0) { sign = 0; data.clear(); } else { if (o < 0) { sign *= -1; o = std::abs(o); } int n = data.size(); data.resize(n + 9, 0); long long carry = 0; for (int i = 0; i < n || carry; i++) { carry += (long long)data[i] * o; data[i] = carry % BASE; carry /= BASE; } pop_zeros(); } return *this; } BigInteger& operator*=(BigInteger const& o) { sign *= o.sign; if (sign == 0) { data.clear(); } else { auto result = FFT::multiply(data, o.data); data.resize(result.size()); long long carry = 0; for (auto i = 0u; i < result.size(); i++) { carry += result[i]; data[i] = carry % BASE; carry /= BASE; } pop_zeros(); } return *this; } void pop_zeros() { while (!data.empty() && data.back() == 0) data.pop_back(); } friend std::ostream& operator<<(std::ostream& stream, BigInteger const& b) { if (b.data.empty()) { stream << 0; } else { if (b.sign == -1) stream << - ; stream << b.data.back(); for (int i = b.data.size() - 2; i >= 0; i--) { stream.width(DIGITS); stream.fill( 0 ); stream << b.data[i]; } } return stream; } friend std::istream& operator>>(std::istream& is, BigInteger& b) { std::string s; is >> s; int start = 0; if (s == 0 ) { b.sign = 0; b.data.clear(); } else { if (s[0] == - ) { b.sign = -1; start++; } else { b.sign = 1; } b.data.resize((s.size() - start + DIGITS - 1) / DIGITS); for (int i = 0, idx = s.size() - 1; i < (int)b.data.size(); i++, idx -= DIGITS) { int value = 0; for (int j = max(start, idx - DIGITS + 1); j <= idx; j++) value = value * 10 + s[j] - 0 ; b.data[i] = value; } } return is; } unsigned int digits() const { if (data.empty()) return 0; unsigned int d = (data.size() - 1) * DIGITS; int x = data.back(); while (x > 0) { d++; x /= 10; } return d; } int compare(BigInteger const& o) const { if (sign < o.sign) return -1; if (sign > o.sign) return 1; if (data.size() != o.data.size()) return (data.size() < o.data.size()) == (sign == 1) ? -1 : 1; for (int i = data.size() - 1; i >= 0; i--) { if (data[i] != o.data[i]) return (data[i] < o.data[i]) == (sign == 1) ? -1 : 1; } return 0; } bool operator==(BigInteger const& o) const { return compare(o) == 0; } bool operator!=(BigInteger const& o) const { return compare(o) != 0; } bool operator<(BigInteger const& o) const { return compare(o) == -1; } bool operator<=(BigInteger const& o) const { return compare(o) <= 0; } bool operator>(BigInteger const& o) const { return compare(o) == 1; } bool operator>=(BigInteger const& o) const { return compare(o) >= 0; } private: static const int DIGITS = 4; static const int BASE = power(10, DIGITS); int sign; vector<int> data; }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); BigInteger a; cin >> a; if (a < 5) { cout << a << n ; return 0; } int p = max(0, (int)(a.digits() * log(10) / log(3) - 3)); int sum = p * 3; BigInteger x = 1; BigInteger base = 3; while (p) { if (p & 1) x *= base; base *= base; p >>= 1; } int best = std::numeric_limits<int>::max(); for (int twos = 0; twos < 3; twos++) { int sum_cur = sum; BigInteger y = x; for (int i = 0; i < twos; i++) { sum_cur += 2; y *= 2; } while (y < a) { sum_cur += 3; y *= 3; } best = min(best, sum_cur); } cout << best << n ; } |
module decode_tb;
//wires
reg clk;
reg rst;
reg wave_instr_valid;
reg[5:0] wave_wfid;
reg[8:0] wave_sgpr_base;
reg[9:0] wave_vgpr_base;
reg[15:0] wave_lds_base;
reg[31:0] wave_instr_pc, wave_instr;
wire issue_wf_halt, issue_valid, issue_vcc_wr, issue_vcc_rd, issue_scc_wr,
issue_scc_rd, issue_exec_rd, issue_exec_wr, issue_m0_rd, issue_m0_wr,
issue_barrier, issue_branch, issue_waitcnt, wave_ins_half_rqd, tracemon_colldone;
wire[1:0] issue_fu;
wire[5:0] issue_wfid, wave_ins_half_wfid;
wire[15:0] issue_lds_base;
wire[12:0] issue_source_reg2, issue_source_reg3, issue_dest_reg2;
wire[13:0] issue_source_reg1, issue_source_reg4, issue_dest_reg1;
wire[15:0] issue_imm_value0;
wire[31:0] issue_opcode, issue_imm_value1, issue_instr_pc;
wire[63:0] tracemon_collinstr;
//instantiation of dut
decode decode0(
.wave_instr_pc(wave_instr_pc),
.wave_instr_valid(wave_instr_valid),
.wave_instr(wave_instr),
.wave_wfid(wave_wfid),
.wave_vgpr_base(wave_vgpr_base),
.wave_sgpr_base(wave_sgpr_base),
.wave_lds_base(wave_lds_base),
.issue_fu(issue_fu),
.issue_wfid(issue_wfid),
.issue_opcode(issue_opcode),
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3),
.issue_source_reg4(issue_source_reg4),
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2),
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_valid(issue_valid),
.issue_instr_pc(issue_instr_pc),
.issue_vcc_wr(issue_vcc_wr),
.issue_vcc_rd(issue_vcc_rd),
.issue_scc_wr(issue_scc_wr),
.issue_scc_rd(issue_scc_rd),
.issue_exec_rd(issue_exec_rd),
.issue_exec_wr(issue_exec_wr),
.issue_m0_rd(issue_m0_rd),
.issue_m0_wr(issue_m0_wr),
.issue_wf_halt(issue_wf_halt),
.issue_barrier(issue_barrier),
.issue_branch(issue_branch),
.issue_waitcnt(issue_waitcnt),
.issue_lds_base(issue_lds_base),
.wave_ins_half_wfid(wave_ins_half_wfid),
.wave_ins_half_rqd(wave_ins_half_rqd),
.tracemon_collinstr(tracemon_collinstr),
.tracemon_colldone(tracemon_colldone),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
wave_instr_valid = 1'b0;
#10 rst = 1'b0;
#2000;
$finish;
end
initial begin
#41;
//Test1: SOP1
wave_instr_valid = 1'b1;
wave_wfid = 6'd37;
wave_instr_pc = 32'hcafe_0000;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b101111101_0000010_00000111_00000111;
// /SOP1-----/SDST7--/OP------/SSRC8---/
#10;
wave_instr_valid = 1'b0;
#10;
//Test2: SOP1 with literal constant
wave_instr_valid = 1'b1;
wave_wfid = 6'd37;
wave_instr_pc = 32'hcafe_0000;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b101111101_0000010_00000111_11111111;
// /SOP1-----/SDST7--/OP------/SSRC8---/
#10;
wave_instr_valid = 1'b0;
#50;
wave_instr_valid = 1'b1;
wave_wfid = 6'd37;
wave_instr_pc = 32'hcafe_0000;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b101111101_0000010_00000111_00000111;
//This is just a literal constant
#10;
wave_instr_valid = 1'b0;
#10;
//Test3: MTBUF
wave_instr_valid = 1'b1;
wave_wfid = 6'd27;
wave_instr_pc = 32'hcafe_f00d;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b111010_xxxxxxx_100_xx11_110011001100;
// /MTBUF-/?------/OP3/flag/OFFSET12----/
//MTBUF - 1st word
#10;
wave_instr_valid = 1'b0;
#10;
wave_instr_valid = 1'b1;
wave_wfid = 6'd27;
wave_instr_pc = 32'hcafe_f011;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b00110011_xxx_11111_00001111_11110000;
// /SOFFSET8/flg/srsc5/VDATA8--/VADDR8--/
//MTBUF - 2nd word
//Test4: SOPP (halt)
#10;
wave_instr_valid = 1'b0;
#10;
wave_instr_valid = 1'b1;
wave_wfid = 6'd0;
wave_instr_pc = 32'hdead_babe;
wave_sgpr_base = 9'd256;
wave_vgpr_base = 10'd512;
wave_lds_base = {16{1'bx}};
wave_instr = 32'b101111111_0000001_xxxxxxxxxxxxxxxx;
// /SOPP-----/OP7----/SIMM16----------/
//halt
#10;
wave_instr_valid = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor("rst = %b", rst);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,decode_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream& operator<<(ostream& os, const pair<T1, T2>& p) { os << { << p.first << , << p.second << } ; return os; } template <class T> ostream& operator<<(ostream& os, const vector<T>& p) { os << [ ; int i = 0; for (typename vector<T>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class T> ostream& operator<<(ostream& os, const set<T>& p) { os << [ ; int i = 0; for (typename set<T>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class K, class V> ostream& operator<<(ostream& os, const map<K, V>& p) { os << [ ; int i = 0; for (typename map<K, V>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class T> string toString(const T& o) { stringstream ss; ss << o; string ret; getline(ss, ret); return ret; } template <class T> vector<T> subv(const vector<T>& v, int from, int to) { return vector<T>(v.begin() + min(max(0, from), (int)v.size()), v.begin() + min(max(0, to), (int)v.size())); } pair<int, int> operator+(const pair<int, int>& a, const pair<int, int>& b) { return make_pair(a.first + b.first, a.second + b.second); } pair<int, int> operator*(const int& a, const pair<int, int>& b) { return make_pair(a * b.first, a * b.second); } int main() { int n; cin >> n; if (n == 1) { cout << a na nb nb n ; } else if (n == 2) { cout << aa nbb ncc ndd n ; } else { if (n % 2 == 0) { for (int i = 0; i < n / 2; ++i) cout << (i % 2 == 0 ? aa : bb ); cout << endl; for (int i = 0; i < n / 2; ++i) cout << (i % 2 != 0 ? aa : bb ); cout << endl; cout << e ; for (int i = 0; i < n / 2 - 1; ++i) cout << (i % 2 == 0 ? cc : dd ); cout << e << endl; cout << e ; for (int i = 0; i < n / 2 - 1; ++i) cout << (i % 2 != 0 ? cc : dd ); cout << e << endl; } else { for (int i = 0; i < n / 2; ++i) cout << (i % 2 == 0 ? aa : bb ); cout << e << endl; for (int i = 0; i < n / 2; ++i) cout << (i % 2 != 0 ? aa : bb ); cout << e << endl; cout << e ; for (int i = 0; i < n / 2; ++i) cout << (i % 2 == 0 ? cc : dd ); cout << endl; cout << e ; for (int i = 0; i < n / 2; ++i) cout << (i % 2 != 0 ? cc : dd ); cout << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, a1, a2, b1, b2, max1, max2; cin >> t; while (t > 0) { cin >> a1 >> b1; cin >> a2 >> b2; max1 = max(a1, b1); max2 = max(a2, b2); if (max1 == max2) { int min1, min2; min1 = min(a1, b1); min2 = min(a2, b2); if ((min1 + min2) == max1) { cout << Yes << endl; } else { cout << No << endl; } } else { cout << No << endl; } t--; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_1_V
`define SKY130_FD_SC_HD__HA_1_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_1_V
|
#include <bits/stdc++.h> using namespace std; int t, n, m; long long r, ans[800005]; stack<int> s; vector<pair<char, vector<int>>> v; char x[800005 * 6]; void dfs(int a) { if (v[a].first == _ ) return; vector<int> tv; for (int i : v[a].second) { dfs(i); if (v[a].first == v[i].first) { if (tv.size() < v[i].second.size()) tv.swap(v[i].second); tv.insert(tv.end(), v[i].second.begin(), v[i].second.end()); } else tv.push_back(i); } v[a].second.swap(tv); if (v[a].first == S ) { int best = v[a].second.front(); for (int i : v[a].second) if (v[i].second.size() < v[best].second.size()) best = i; v[a].first = v[best].first; v[a].second.swap(v[best].second); } } int main() { scanf( %d , &t); while (t--) { scanf( %lld , &r); fgets(x, sizeof(x), stdin); x[n = strlen(x) - 1] = 0; if (n == 1) { printf( REVOLTING %lld n , r); continue; } m = 0; s = stack<int>(); s.push(0); v = {{ S , vector<int>()}}; for (int i = 0; i < n; i++) { if (x[i] == ( ) { s.push(v.size()); v.emplace_back( ? , vector<int>()); } else if (x[i] == ) ) { int tmp = s.top(); s.pop(); v[s.top()].second.push_back(tmp); } else if (x[i] == * ) { v[s.top()].second.push_back(v.size()); v.emplace_back( _ , vector<int>{m++}); } else if (x[i] != ) v[s.top()].first = x[i]; } dfs(0); if (v[0].first == _ ) ans[v[0].second.front()] = r; else for (int i : v[0].second) ans[v[i].second.front()] = (long long)r * v[0].second.size(); printf( REVOLTING ); for (int i = 0; i < m; i++) { printf( %lld , ans[i]); ans[i] = 0; } puts( ); } } |
#include <bits/stdc++.h> using namespace std; int count_on(int mask) { int ans = 0; while (mask) { if (mask & 1) { ans++; } mask >>= 1; } return ans; } int dp[1 << 20]; string bin(int mask) { string str = ; while (mask) { if (mask & 1) { str += ( 1 ); } else { str += ( 0 ); } mask >>= 1; } reverse(str.begin(), str.end()); if (str == ) { str = 0 ; } return str; } int main() { string str; cin >> str; vector<int> masks; int N = str.size(); for (int i = 0; i < N; i++) { int mask = 0; for (int j = 0; i + j < N && j < 20; j++) { int dig = str[i + j] - a ; if (mask & (1 << dig)) { break; } mask |= (1 << dig); masks.push_back(mask); dp[mask] = count_on(mask); } } for (int i = 0; i < (1 << 20); i++) { for (int j = 0; j < 20; j++) { if (i & (1 << j)) { dp[i] = max(dp[i], dp[i ^ (1 << j)]); } } } int best = 0; for (auto mask : masks) { int ans = dp[mask] + dp[((1 << 20) - 1) ^ mask]; best = max(best, ans); } cout << best << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int NMAX = 210, INF = 0x3f3f3f3f, VMAX = 20010; int N, A[NMAX], Source, Sink, Flow[NMAX][NMAX], Cap[NMAX][NMAX], Father[NMAX], Even, Odd; bool Used[NMAX], Prime[VMAX]; vector<int> G[NMAX], FlowG[NMAX], CurrentTable; vector<vector<int> > Ans; bool BFS() { queue<int> Q; for (int i = 0; i <= N + 1; ++i) Used[i] = Father[i] = 0; Used[Source] = 1; Q.push(Source); while (!Q.empty()) { int Node = Q.front(); Q.pop(); if (Node == Sink) return 1; for (int i = 0; i < G[Node].size(); ++i) { int Vec = G[Node][i]; if (!Used[Vec] && Cap[Node][Vec] > Flow[Node][Vec]) Used[Vec] = 1, Father[Vec] = Node, Q.push(Vec); } } return Used[Sink]; } void DFS(int Node, int StartNode) { if (Node == StartNode && CurrentTable.size() >= 3) return; CurrentTable.push_back(Node); Used[Node] = 1; for (int i = 0; i < FlowG[Node].size(); ++i) if (!Used[FlowG[Node][i]]) DFS(FlowG[Node][i], StartNode); } void BuildGraph() { Source = 0; Sink = N + 1; for (int i = 1; i <= N; ++i) if (A[i] % 2 == 1) { G[Source].push_back(i); G[i].push_back(Source); Cap[Source][i] = 2; } else { G[i].push_back(Sink); G[Sink].push_back(i); Cap[i][Sink] = 2; } for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) if (A[i] % 2 == 1 && A[j] % 2 == 0 && Prime[A[i] + A[j]]) { G[i].push_back(j); G[j].push_back(i); Cap[i][j] = 1; } } void MaxFlow() { int CntFlow = 0; while (BFS()) { for (int i = 0; i < G[Sink].size(); ++i) { int Vec = G[Sink][i]; if (Used[Vec] && Cap[Vec][Sink] != Flow[Vec][Sink]) { int MinFlow = INF; Father[Sink] = Vec; for (int Node = Sink; Node != Source; Node = Father[Node]) MinFlow = min(MinFlow, Cap[Father[Node]][Node] - Flow[Father[Node]][Node]); for (int Node = Sink; Node != Source; Node = Father[Node]) { Flow[Father[Node]][Node] += MinFlow; Flow[Node][Father[Node]] -= MinFlow; } CntFlow += MinFlow; } } } if (CntFlow != N) printf( Impossible n ); else { for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) if (A[i] % 2 == 1 && A[j] % 2 == 0 && Prime[A[i] + A[j]] && Flow[i][j] == 1) FlowG[i].push_back(j), FlowG[j].push_back(i); for (int i = 1; i <= N; ++i) Used[i] = 0; for (int i = 1; i <= N; ++i) if (!Used[i]) { CurrentTable.clear(); DFS(i, i); Ans.push_back(CurrentTable); } printf( %i n , Ans.size()); for (int i = 0; i < Ans.size(); ++i) { printf( %i , Ans[i].size()); for (int j = 0; j < Ans[i].size(); ++j) printf( %i , Ans[i][j]); printf( n ); } return; } } int main() { for (int i = 2; i < VMAX; ++i) Prime[i] = 1; for (int i = 2; i < VMAX; ++i) if (Prime[i]) for (int j = i + i; j < VMAX; j += i) Prime[j] = 0; scanf( %i , &N); for (int i = 1; i <= N; ++i) { scanf( %i , &A[i]); Even += (A[i] % 2 == 0); Odd += (A[i] % 2 == 1); } if (Even != Odd) { printf( Impossible n ); return 0; } BuildGraph(); MaxFlow(); return 0; } |
// Check that all types of constant expression are supported for attributes
module test;
localparam [7:0] x = 1;
// Binary operators
(* attr = x + x *) reg attr0;
(* attr = x - x *) reg attr1;
(* attr = x * x *) reg attr2;
(* attr = x / x *) reg attr3;
(* attr = x % x *) reg attr4;
(* attr = x == x *) reg attr5;
(* attr = x != x *) reg attr6;
(* attr = x === x *) reg attr7;
(* attr = x !== x *) reg attr8;
(* attr = x && x *) reg attr9;
(* attr = x || x *) reg attr10;
(* attr = x ** x *) reg attr11;
(* attr = x < x *) reg attr12;
(* attr = x <= x *) reg attr13;
(* attr = x > x *) reg attr14;
(* attr = x >= x *) reg attr15;
(* attr = x & x *) reg attr16;
(* attr = x | x *) reg attr17;
(* attr = x ^ x *) reg attr18;
(* attr = x ^~ x *) reg attr19;
(* attr = x >> x *) reg attr20;
(* attr = x << x *) reg attr21;
(* attr = x >>> x *) reg attr22;
(* attr = x <<< x *) reg attr23;
// Unary operators
(* attr = +x *) reg attr24;
(* attr = -x *) reg attr25;
(* attr = !x *) reg attr26;
(* attr = ~x *) reg attr27;
(* attr = &x *) reg attr28;
(* attr = ~&x *) reg attr29;
(* attr = |x *) reg attr30;
(* attr = ~|x *) reg attr31;
(* attr = ^x *) reg attr32;
(* attr = ~^x *) reg attr33;
// Ternary operator
(* attr = x ? x : x *) reg attr34;
// Concat
(* attr = {x,x} *) reg attr35;
(* attr = {3{x}} *) reg attr36;
// Part select
(* attr = x[0] *) reg attr37;
(* attr = x[1:0] *) reg attr38;
(* attr = x[0+:1] *) reg attr39;
(* attr = x[1-:1] *) reg attr40;
// Parenthesis
(* attr = (x) *) reg attr41;
// Literals
(* attr = 10 *) reg attr42;
(* attr = 32'h20 *) reg attr43;
(* attr = "test" *) reg attr44;
// System function
(* attr = $clog2(10) *) reg attr45;
// Function
function fn;
input x;
fn = x*2;
endfunction
(* attr = fn(10) *) reg attr46;
initial begin
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[55], s[55]; long double p[55]; long double dp[55][5005]; bool vis[55][5005]; int main() { int n, r; scanf( %d%d , &n, &r); for (int i = 1; i <= n; i++) { scanf( %d%d%Lf , &f[i], &s[i], &p[i]); p[i] /= 100; } long double lo = 0, hi = 1e18, ans = 0; for (int i = 0; i < 200; i++) { long double mid = (lo + hi) / 2; memset(vis, 0, sizeof(vis)); memset(dp, 0, sizeof(dp)); vis[n + 1][0] = 1; for (int i = n; i >= 1; i--) { for (int j = 0; j <= r; j++) { long double res = 0; if (j >= s[i]) { res += (f[i] + dp[i + 1][j - f[i]]) * p[i]; res += (s[i] + dp[i + 1][j - s[i]]) * (1 - p[i]); res = min(res, mid); dp[i][j] = res; vis[i][j] = 1; } else if (j >= f[i]) { res += (f[i] + dp[i + 1][j - f[i]]) * p[i]; res += (s[i] + mid) * (1 - p[i]); res = min(res, mid); dp[i][j] = res; vis[i][j] = 1; } else { res += (f[i] + mid) * p[i]; res += (s[i] + mid) * (1 - p[i]); res = min(res, mid); dp[i][j] = mid; vis[i][j] = mid; } } } bool ok = 0; for (int j = 0; j <= r; j++) { if (!vis[1][j]) continue; if (dp[1][j] < mid) ok = 1; } if (ok) ans = mid, hi = mid; else lo = mid; } printf( %.20Lf n , ans); } |
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