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#include <bits/stdc++.h> using namespace std; map<char, long long> mp; long long arr[2][1234]; int main() { string s; long long idx1, idx2; char repeating; cin >> s; long long i; for (i = 0; i < s.size(); i++) mp[s[i]]++; for (auto it : mp) if (it.second == 2) repeating = it.first; 0; long long c1 = 0, c2 = 0, c3 = 0, nc1, nc3; for (i = 0; i < s.size(); i++) if (s[i] == repeating) { idx1 = idx2; idx2 = i; } if (idx2 == idx1 + 1) { cout << Impossible ; return 0; } 0; c2 = idx2 - idx1 - 1; c3 = 26 - idx2; c1 = idx1; 0; 0; if (c2 % 2 == 0) { long long sum = c1 + c3; nc3 = sum / 2; nc1 = nc3 + 1; if (nc1 < c1) { long long give = c1 - nc1; string tmp = s.substr(0, give); s = s.substr(give, 27 - tmp.size()); s += tmp; 0; } else if (nc1 > c1) { long long give = nc1 - c1; string tmp = s.substr(27 - give, give); s = tmp + s.substr(0, 27 - give); 0; } } else if (c2 % 2 == 1) { long long sum = c1 + c3; nc3 = sum / 2; nc1 = nc3; if (nc1 < c1) { long long give = c1 - nc1; string tmp = s.substr(0, give); s = s.substr(give, 27 - tmp.size()); s += tmp; 0; } else if (nc1 > c1) { long long give = nc1 - c1; string tmp = s.substr(27 - give, give); s = tmp + s.substr(0, 27 - give); 0; } } 0; for (i = 0; i < s.size(); i++) if (s[i] == repeating) { idx1 = idx2; idx2 = i; } long long curr = 0; if (c2 % 2 == 0) { for (i = 0; i < idx1; i++) arr[1][curr++] = s[i] - A ; curr--; 0; arr[0][curr] = repeating - A ; curr++; for (i = idx1 + 1; i <= (idx1 + c2 / 2); i++) arr[0][curr++] = s[i] - A ; 0; curr--; for (i = idx1 + c2 / 2 + 1; i <= (idx1 + c2); i++) arr[1][curr--] = s[i] - A ; curr--; for (i = idx2 + 1; i < 27; i++) arr[0][curr--] = s[i] - A ; for (i = 0; i < 2; i++) { for (long long j = 0; j < 13; j++) { cout << char(arr[i][j] + A ); } cout << endl; } } else { for (i = 0; i < idx1; i++) arr[1][curr++] = s[i] - A ; 0; arr[1][curr] = repeating - A ; for (i = idx1 + 1; i <= ((idx1 + c2 / 2) + 1); i++) arr[0][curr++] = s[i] - A ; 0; curr--; for (i = idx1 + c2 / 2 + 2; i <= (idx1 + c2); i++) arr[1][curr--] = s[i] - A ; curr--; for (i = idx2 + 1; i < 27; i++) arr[0][curr--] = s[i] - A ; for (i = 0; i < 2; i++) { for (long long j = 0; j < 13; j++) { cout << char(arr[i][j] + A ); } cout << endl; } } }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that an array of modules in supported.
//
module my_and (out,a,b);
input a,b;
output out;
and u0 (out,a,b);
endmodule
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
my_and foo [0:15] (out,a,b);
always @(a or b)
rslt = a & b;
initial
begin // {
error = 0;
# 1;
for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1)
begin // {
for(b = 16'hffff; b !== 16'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module alu (
output reg [31:0] alu_out,
input [31:0] op1,
input [31:0] op2,
input [31:0] multiplier_result,
input [4:0] alu_sel
);
always @ (*) begin
case (alu_sel)
`ALU_ADD: alu_out = op1 + op2;
`ALU_SLL: alu_out = op1 << op2;
`ALU_SLT: alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
`ALU_XOR: alu_out = op1 ^ op2;
`ALU_SRL: alu_out = op1 >> op2;
`ALU_SRA: alu_out = $signed(op1) >>> op2;
`ALU_OR: alu_out = op1 | op2;
`ALU_AND: alu_out = op1 & op2;
`ALU_MUL: alu_out = multiplier_result;
`ALU_DIV: alu_out = $signed(op1) / $signed(op2);
`ALU_DIVU: alu_out = op1 / op2;
`ALU_REM: alu_out = $signed(op1) % $signed(op2);
`ALU_REMU: alu_out = op1 % op2;
`ALU_LUI: alu_out = op1 << 12;
`ALU_NONE: alu_out = 0;
endcase
end
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ReadConfigStruct #(parameter MAX_NUM_CONFIG_CL = 2)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire get_config_struct,
input wire [57:0] base_addr,
input wire [31:0] config_struct_length,
// User Module TX RD
output reg [57:0] cs_tx_rd_addr,
output reg [8:0] cs_tx_rd_tag,
output reg cs_tx_rd_valid,
input wire cs_tx_rd_free,
// User Module RX RD
input wire [8:0] cs_rx_rd_tag,
input wire [511:0] cs_rx_rd_data,
input wire cs_rx_rd_valid,
//
output wire [(MAX_NUM_CONFIG_CL<<9)-1:0] afu_config_struct,
output wire afu_config_struct_valid
);
wire rd_done;
wire all_reads_done;
reg [31:0] numReadsSent;
reg [31:0] numReadsDone;
reg [31:0] rd_cnt;
reg [511:0] config_lines[MAX_NUM_CONFIG_CL];
reg config_lines_valid[MAX_NUM_CONFIG_CL];
genvar i;
generate for( i = 0; i < MAX_NUM_CONFIG_CL; i = i + 1) begin: configLines
always@(posedge clk) begin
if(~rst_n) begin
//config_lines[ i ] <= 0;
config_lines_valid[ i ] <= 0;
end
else if(cs_rx_rd_valid) begin
config_lines[ i ] <= (cs_rx_rd_tag[1:0] == i)? cs_rx_rd_data : config_lines[ i ];
config_lines_valid[ i ] <= (cs_rx_rd_tag[1:0] == i)? 1'b1 : config_lines_valid[ i ];
end
end
assign afu_config_struct[512*(i+1) - 1 : 512*i] = config_lines[ i ];
end
endgenerate
/////////////////////////////// Generating Read Requests //////////////////////////////
//
assign all_reads_done = (numReadsSent == numReadsDone) & (numReadsSent != 0);
assign afu_config_struct_valid = rd_done & all_reads_done;
assign rd_done = (rd_cnt == config_struct_length);
always@(posedge clk) begin
if(~rst_n) begin
cs_tx_rd_valid <= 1'b0;
rd_cnt <= 0;
cs_tx_rd_addr <= 0;
cs_tx_rd_tag <= 0;
end
else if(cs_tx_rd_free | ~cs_tx_rd_valid) begin
if( ~rd_done & get_config_struct ) begin
rd_cnt <= rd_cnt + 1'b1;
cs_tx_rd_valid <= 1'b1;
cs_tx_rd_addr <= ({1'b0, base_addr} + {1'b0, rd_cnt});
cs_tx_rd_tag <= rd_cnt[8:0];
end
else begin
cs_tx_rd_valid <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
numReadsSent <= 0;
numReadsDone <= 0;
end
else begin
numReadsSent <= (cs_tx_rd_valid & cs_tx_rd_free)? numReadsSent + 1'b1 : numReadsSent;
numReadsDone <= (cs_rx_rd_valid)? numReadsDone + 1'b1 : numReadsDone;
end
end
endmodule
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: Line_Buffer.v
// Megafunction Name(s):
// altshift_taps
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Line_Buffer (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [15:0] shiftin;
output [15:0] shiftout;
output [15:0] taps;
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] taps = sub_wire0[15:0];
wire [15:0] shiftout = sub_wire1[15:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire1));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 1,
altshift_taps_component.tap_distance = 640,
altshift_taps_component.width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "640"
// Retrieval info: PRIVATE: WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "1"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "640"
// Retrieval info: CONSTANT: WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 16 0 INPUT NODEFVAL shiftin[15..0]
// Retrieval info: USED_PORT: shiftout 0 0 16 0 OUTPUT NODEFVAL shiftout[15..0]
// Retrieval info: USED_PORT: taps 0 0 16 0 OUTPUT NODEFVAL taps[15..0]
// Retrieval info: CONNECT: @shiftin 0 0 16 0 shiftin 0 0 16 0
// Retrieval info: CONNECT: shiftout 0 0 16 0 @shiftout 0 0 16 0
// Retrieval info: CONNECT: taps 0 0 16 0 @taps 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 100005; const int Maxm = 500; int T; int n, m, k; vector<int> un; int my[Maxn]; bool has[Maxm][Maxm]; set<int> neigh[Maxn]; void Solve(priority_queue<pair<int, int> > &Q) { bool assigned = false; int inside = n; while (!Q.empty() && -Q.top().first < k) { int v = Q.top().second, d = -Q.top().first; Q.pop(); if (neigh[v].size() != d) continue; if (neigh[v].size() == k - 1) { if (!assigned && inside < Maxm) { int pnt = 0; for (int i = 1; i <= n; i++) if (!neigh[i].empty()) my[i] = pnt++; for (int i = 0; i < pnt; i++) fill(has[i], has[i] + pnt, false); for (int i = 1; i <= n; i++) for (auto u : neigh[i]) has[my[i]][my[u]] = true; assigned = true; } vector<int> seq; for (auto u : neigh[v]) seq.push_back(u); bool ok = true; for (int i = 0; i < seq.size() && ok; i++) for (int j = i + 1; j < seq.size() && ok; j++) if (assigned) ok = has[my[seq[i]]][my[seq[j]]]; else ok = neigh[seq[i]].find(seq[j]) != neigh[seq[i]].end(); if (ok) { printf( 2 n ); printf( %d , v); for (int i = 0; i < seq.size(); i++) printf( %d , seq[i]); printf( n ); return; } } for (auto u : neigh[v]) { neigh[u].erase(v); if (assigned) has[my[v]][my[u]] = has[my[u]][my[v]] = false; Q.push(pair<int, int>(-int(neigh[u].size()), u)); } neigh[v].clear(); inside--; } vector<int> seq; while (!Q.empty()) { int v = Q.top().second, d = -Q.top().first; Q.pop(); if (neigh[v].size() != d) continue; seq.push_back(v); } if (seq.empty()) printf( -1 n ); else { printf( 1 %d n , int(seq.size())); for (int i = 0; i < seq.size(); i++) printf( %d%c , seq[i], i + 1 < seq.size() ? : n ); } } int main() { scanf( %d , &T); while (T--) { scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) neigh[i].clear(); for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); neigh[a].insert(b); neigh[b].insert(a); } priority_queue<pair<int, int> > Q; for (int i = 1; i <= n; i++) Q.push(pair<int, int>(-int(neigh[i].size()), i)); Solve(Q); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, i, a[1000021], j; int main() { scanf( %d%d , &n, &k); if (n / k <= 2) { cout << -1; exit(0); } for (i = 1; i <= k * ((n / k) - 1); i++) a[i] = (i - 1) / ((n / k) - 1) + 1; j = ((n / k) - 1) * k; while (j <= n) for (i = 1; i <= k; i++) if (j <= n) a[++j] = i; for (i = 1; i <= n; i++) printf( %d , a[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; signed main() { long long int n, m; cin >> n >> m; if (m == 0) { cout << 0; return 0; } vector<vector<long long int>> v[n + 1]; long long int in[n + 1]; memset(in, 0, sizeof(in)); for (long long int i = 0; i < m; i++) { long long int x, y, z; cin >> x >> y >> z; v[x].push_back({y, z}); in[y] += 1; } queue<vector<long long int>> q; for (long long int i = 1; i <= n; i++) { if (in[i] == 0 && v[i].size()) { q.push({i, INT_MAX, i}); } } vector<vector<long long int>> ans; while (q.size()) { vector<long long int> p = q.front(); q.pop(); if (p.size() && v[p[0]].size() == 0) { ans.push_back({p[2], p[0], p[1]}); } for (auto x : v[p[0]]) { in[x[0]] -= 1; if (in[x[0]] == 0) { q.push({x[0], min(p[1], x[1]), p[2]}); } } } cout << ans.size() << n ; sort(ans.begin(), ans.end()); for (auto x : ans) { for (auto y : x) cout << y << ; cout << n ; } }
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } int n, a[300100], q; struct node { int x; int val; }; bool operator<(node a, node b) { return a.val < b.val; } priority_queue<node> heap; set<int> tree; int main() { n = read(), q = read(); for (int i = 1; i <= n; ++i) { a[i] = read(); tree.insert(a[i]); } sort(a + 1, a + 1 + n); for (int i = 1; i < n; ++i) { heap.push({a[i], a[i + 1] - a[i]}); } if (tree.size() <= 2) { puts( 0 ); } else { cout << (*(--tree.end())) - (*tree.begin()) - heap.top().val << endl; } for (int i = 1; i <= q; ++i) { int t = read(), p = read(); if (t == 0) { set<int>::iterator it; it = tree.lower_bound(p); set<int>::iterator lst = it; lst--; if (it != tree.end()) { set<int>::iterator nxt = it; nxt++; heap.push({(*lst), (*nxt) - (*lst)}); tree.erase(it); } } else { tree.insert(p); set<int>::iterator it; it = tree.lower_bound(p); set<int>::iterator nxt = it; nxt++; set<int>::iterator lst = it; lst--; heap.push({(*lst), (*it) - (*lst)}); heap.push({(*it), (*nxt) - (*it)}); } bool flag = false; do { flag = false; int x = heap.top().x, val = heap.top().val; set<int>::iterator it; it = tree.find(x); set<int>::iterator nxt = it; if (it != tree.end()) nxt++; if (it == tree.end() || nxt == tree.end()) { heap.pop(); flag = true; } else { if (val != (*nxt) - (*it)) { heap.pop(); flag = true; } } } while (flag && heap.size()); if (tree.size() <= 2) { puts( 0 ); } else { cout << (*(--tree.end())) - (*tree.begin()) - heap.top().val; puts( ); } } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:42:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_stub.v
// Design : system_vga_sync_ref_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_0_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FixedRoundSigned
:Function
Round for signed fixed number.
Give the first output after 3 cycles.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FixedRoundSigned(
clk,
fixed_num,
round
);
parameter num_width = 42;
parameter fixed_pos = 16;
parameter res_width = 12;
input clk;
input signed [num_width - 1 : 0] fixed_num;
output reg signed [res_width : 0] round;
reg signed [num_width - 1 : 0] num_orig;
reg num_orig_sflag, num_orig_rflag;
reg signed [res_width : 0] num_comp;
always @(posedge clk) begin
num_orig <= fixed_num[num_width - 1] == 0 ? fixed_num :
{fixed_num[num_width - 1], ~(fixed_num[num_width - 2 : 0] - 1)};
num_comp <= num_orig[num_width - 1] == 0 ?
{num_orig[num_width - 1], num_orig[res_width + fixed_pos - 1 : fixed_pos]} :
{num_orig[num_width - 1], ~num_orig[res_width + fixed_pos - 1 : fixed_pos] + 1};
num_orig_sflag <= num_orig[num_width - 1];
num_orig_rflag <= num_orig[fixed_pos - 1];
//Why not use num_comp[25] to judge? : if 0
case(num_orig_sflag)
0 : round <= num_orig_rflag == 0 ? num_comp : num_comp + 1;
1 : round <= num_orig_rflag == 0 ? num_comp : num_comp - 1;
default : /* default */;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mn = 410, mm = 101000, inf = 1 << 30; bool vis[mn]; int X[mm], Y[mm], du[mn]; int n, m, K, t, S, T, ans[mm], answer; int dis[mm], pre[mm], Q[mm]; struct network { int tt, la[mn], next[mm], y[mm], f[mm], co[mm]; void clear() { tt = 1; memset(la, 0, (T + 2) * 4); } void add(int i, int j, int u, int v) { ++tt, next[tt] = la[i], la[i] = tt, y[tt] = j, f[tt] = u, co[tt] = v; ++tt, next[tt] = la[j], la[j] = tt, y[tt] = i, f[tt] = 0, co[tt] = -v; } } e; int spfa() { memset(vis, 0, T + 2); memset(pre, 0, (T + 2) * 4); fill(dis + 1, dis + 1 + T, inf); dis[S] = 0; int st = 1, ed = 2; Q[1] = S, vis[S] = 1; while (st != ed) { int r = Q[st]; for (int p = e.la[r], i; p; p = e.next[p]) { if (!e.f[p]) continue; i = e.y[p]; if (dis[r] + e.co[p] < dis[i]) { dis[i] = dis[r] + e.co[p], pre[i] = p; if (!vis[i]) { Q[ed] = i, vis[i] = 1; ed = (ed + 1) % (T + 2); } } } st = (st + 1) % (T + 2); vis[r] = 0; } return dis[T]; } void repair() { for (int i = T, p; i != S; i = e.y[p ^ 1]) { p = pre[i]; --e.f[p], ++e.f[p ^ 1]; } } int main() { scanf( %d%d%d%d , &n, &m, &K, &t); for (int i = 1; i <= K; ++i) { scanf( %d%d , X + i, Y + i); ++du[X[i]], ++du[Y[i] + n]; } for (int i = 1; i <= n + m; ++i) answer += (du[i] % t) != 0; S = n + m + 1, T = S + 1; while (t) { e.clear(); for (int i = 1; i <= K; ++i) { if (ans[i]) continue; e.add(X[i], Y[i] + n, 1, 0); } for (int i = 1; i <= n; ++i) { e.add(S, i, du[i] / t, 0); if (du[i] % t != 0) e.add(S, i, 1, 1); } for (int i = n + 1; i <= n + m; ++i) { e.add(i, T, du[i] / t, 0); if (du[i] % t != 0) e.add(i, T, 1, 1); } while (spfa() < inf) repair(); int tot = 0; for (int i = 1; i <= K; ++i) { if (ans[i]) continue; ++tot; if (e.f[tot * 2] == 0) { ans[i] = t; --du[X[i]], --du[Y[i] + n]; } } --t; } printf( %d n , answer); for (int i = 1; i <= K - 1; ++i) printf( %d , ans[i]); printf( %d n , ans[K]); return 0; }
|
/* ********************************************************************************************* */
/* * Top Module * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* * Luciano Falqueto * */
/* * Wallison de Oliveira * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina, Luciano Falqueto and Wallison de Oliveira * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module TOP(
SYS_CLK,
PB,
USER_LED,
I2C_SCL,
I2C_SDA,
GPIO_A
);
/* Input clock (50 Mhz) */
input SYS_CLK;
/* Push buttons */
input [4:1] PB;
/* LEDs */
output [8:1] USER_LED;
/* SPI: SCLK */
input I2C_SCL;
/* SPI: MOSI */
input I2C_SDA;
/* SPI: MISO */
output GPIO_A;
wire [255:0] wPMosi;
wire [255:0] wPMiso;
wire wPValid;
wire wShaResetN;
wire wShaInit;
wire wShaNext;
wire wShaMode;
wire [511:0] wShaBlock;
wire [255:0] wShaDigest;
wire [1:0] wUserLed;
assign USER_LED = {6'h3f, wUserLed[1], wUserLed[0]};
/* SPI Slave Module */
SPISlaveDelayedResponse#(256, 40) spiinst(
.rst_n(PB[1]),
.s_sclk(I2C_SCL),
.s_mosi(I2C_SDA),
.s_miso(GPIO_A),
.p_mosi(wPMosi),
.p_miso(wPMiso),
.p_valid(wPValid)
);
/* Communication and SHA-256 module manager */
Manager manager(
.clk(SYS_CLK),
.rst_n(PB[1]),
.p_mosi(wPMosi),
.p_miso(wPMiso),
.p_valid(wPValid),
.sha_reset_n(wShaResetN),
.sha_init(wShaInit),
.sha_next(wShaNext),
.sha_mode(wShaMode),
.sha_block(wShaBlock),
.sha_digest(wShaDigest)
);
/* SHA-256 Module */
sha256_core shainst(
.clk(SYS_CLK),
.reset_n(wShaResetN),
.init(wShaInit),
.next(wShaNext),
.mode(wShaMode),
.block(wShaBlock),
.ready(),
.digest(wShaDigest),
.digest_valid()
);
/* Activity LED for SPI */
ActivityLED act1(
.clk(SYS_CLK),
.rst_n(PB[1]),
.sig_in(I2C_SCL),
.led_out(wUserLed[0])
);
/* Activity LED for SHA-256 */
ActivityLED act2(
.clk(SYS_CLK),
.rst_n(PB[1]),
.sig_in(wShaInit),
.led_out(wUserLed[1])
);
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input rgmii_0_rxc ,
output rgmii_0_txc ,
output rgmii_0_tx_en ,
output [3:0] rgmii_0_txd ,
input rgmii_0_rx_dv ,
input [3:0] rgmii_0_rxd ,
input rgmii_1_rxc ,
output rgmii_1_txc ,
output rgmii_1_tx_en ,
output [3:0] rgmii_1_txd ,
input rgmii_1_rx_dv ,
input [3:0] rgmii_1_rxd ,
input rgmii_2_rxc ,
output rgmii_2_txc ,
output rgmii_2_tx_en ,
output [3:0] rgmii_2_txd ,
input rgmii_2_rx_dv ,
input [3:0] rgmii_2_rxd ,
input rgmii_3_rxc ,
output rgmii_3_txc ,
output rgmii_3_tx_en ,
output [3:0] rgmii_3_txd ,
input rgmii_3_rx_dv ,
input [3:0] rgmii_3_rxd ,
inout rgmii_0_mdio ,
output rgmii_0_mdc ,
inout rgmii_1_mdio ,
output rgmii_1_mdc ,
inout rgmii_2_mdio ,
output rgmii_2_mdc ,
inout rgmii_3_mdio ,
output rgmii_3_mdc ,
input rgmii_phy_int ,
output rgmii_phy_rstn ,
output [1:0] pl_led ,
output [1:0] pl_pmod
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.mdio_0_io ( rgmii_0_mdio ),
.mdio_0_mdc ( rgmii_0_mdc ),
.mdio_1_io ( rgmii_1_mdio ),
.mdio_1_mdc ( rgmii_1_mdc ),
.mdio_2_io ( rgmii_2_mdio ),
.mdio_2_mdc ( rgmii_2_mdc ),
.mdio_3_io ( rgmii_3_mdio ),
.mdio_3_mdc ( rgmii_3_mdc ),
.phy_rst_n_0 ( rgmii_phy_rstn ),
.phy_rst_n_1 ( ),
.phy_rst_n_2 ( ),
.phy_rst_n_3 ( ),
.rgmii_0_rd ( rgmii_0_rxd ),
.rgmii_0_rx_ctl ( rgmii_0_rx_dv ),
.rgmii_0_rxc ( rgmii_0_rxc ),
.rgmii_0_td ( rgmii_0_txd ),
.rgmii_0_tx_ctl ( rgmii_0_tx_en ),
.rgmii_0_txc ( rgmii_0_txc ),
.rgmii_1_rd ( rgmii_1_rxd ),
.rgmii_1_rx_ctl ( rgmii_1_rx_dv ),
.rgmii_1_rxc ( rgmii_1_rxc ),
.rgmii_1_td ( rgmii_1_txd ),
.rgmii_1_tx_ctl ( rgmii_1_tx_en ),
.rgmii_1_txc ( rgmii_1_txc ),
.rgmii_2_rd ( rgmii_2_rxd ),
.rgmii_2_rx_ctl ( rgmii_2_rx_dv ),
.rgmii_2_rxc ( rgmii_2_rxc ),
.rgmii_2_td ( rgmii_2_txd ),
.rgmii_2_tx_ctl ( rgmii_2_tx_en ),
.rgmii_2_txc ( rgmii_2_txc ),
.rgmii_3_rd ( rgmii_3_rxd ),
.rgmii_3_rx_ctl ( rgmii_3_rx_dv ),
.rgmii_3_rxc ( rgmii_3_rxc ),
.rgmii_3_td ( rgmii_3_txd ),
.rgmii_3_tx_ctl ( rgmii_3_tx_en ),
.rgmii_3_txc ( rgmii_3_txc ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m )
);
endmodule
|
//-------------------------------------------------------------------
//-- inv_tb.v Banco de pruebas para el inversor
//-------------------------------------------------------------------
//-- (c) BQ August 2015. Written by Juan Gonzalez
//-------------------------------------------------------------------
//-- GPL LICENSE
//-------------------------------------------------------------------
//-- Pruebas del inversor. Se instancia el inversor. Se conecta un
//-- cable a su salida y un registro a su entrada. Desde el programa
//-- principal se dan valores a las entradas (mediante din) y se
//-- comprueba si la salida es la correcta
//-------------------------------------------------------------------
module inv_tb();
//-- Registro de 1 bit conectado a la entrada del inversor
reg din;
//-- Cable conectado a la salida del inversor
wire dout;
//-- Instaciar el inversor, conectado din a la entrada A, y dout a la salida B
inv NOT1 (
.A (din),
.B (dout)
);
//-- Comenzamos las pruebas
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("inv_tb.vcd");
$dumpvars(0, inv_tb);
//-- Ponemos la entrada del inversor a 0
//-- OJO! Esto lo estamos haciendo a partir del instante 5.
//-- Antes su estado es indefinido, por lo que la salida tambien
//-- estará en un estado indefinido
#5 din = 0;
//-- Tras 5 unidades de tiempo comprobamos la salida
# 5 if (dout != 1)
$display("---->¡ERROR! Esperado: 1. Leido: %d", dout);
//-- Tras otras 5 unidades ponemos un 1 en la entrada
# 5 din = 1;
//-- Tras 5 unidades comprobamos si hay un 0 en la entrada
# 5 if (dout != 0)
$display("---> ¡ERROR! Esperado: 0. Leido: %d", dout);
# 5 $display("FIN de la simulacion");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
# 10 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s15 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr36(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [35:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 36'hF0F0AA55;
end
else if(ena) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[30] <= word[31];
word[29] <= word[30];
word[28] <= word[29];
word[27] <= word[28];
word[26] <= word[27];
word[25] <= word[26];
word[24] <= word[25] ^ word[0];
word[23] <= word[24];
word[22] <= word[23];
word[21] <= word[22];
word[20] <= word[21];
word[19] <= word[20];
word[18] <= word[19];
word[17] <= word[18];
word[16] <= word[17];
word[15] <= word[16];
word[14] <= word[15];
word[13] <= word[14];
word[12] <= word[13];
word[11] <= word[12];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6];
word[4] <= word[5];
word[3] <= word[4];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Min = -10000000; int Max = -Min; int A[8] = {1, 1, 0, 0, 1, 1, 1, 1}; int B[8] = {0, 0, 1, 1, 1, 1, -1, -1}; int C[8]; struct Nodes { int x, y; } p[100010]; bool operator<(Nodes &p1, Nodes p2) { if (p1.x == p2.x) return p1.y < p2.y; return p1.x < p2.x; } long long cross(long long x1, long long y1, long long x2, long long y2) { return x1 * y2 - y1 * x2; } int main() { int i, j, k; int n; long long a, b, c, res; while (scanf( %d , &n) != EOF) { for (i = 0; i < 8; i++) { if (i & 1) { C[i] = Max; } else C[i] = Min; } for (i = 1; i <= n; i++) { scanf( %d%d , &p[i].x, &p[i].y); C[0] = max(C[0], p[i].x); C[1] = min(C[1], p[i].x); C[2] = max(C[2], p[i].y); C[3] = min(C[3], p[i].y); C[4] = max(C[4], p[i].x + p[i].y); C[5] = min(C[5], p[i].x + p[i].y); C[6] = max(C[6], p[i].x - p[i].y); C[7] = min(C[7], p[i].x - p[i].y); } res = 0; for (i = 0; i < 8; i++) { Nodes p1, p2; p1.x = p1.y = Min; p2.x = p2.y = Max; for (j = 0; j < 8; j += 2) { Nodes tmp[2]; for (k = j; k < j + 2; k++) { c = cross(A[i], B[i], A[k], B[k]); a = cross(A[i], C[i], A[k], C[k]); b = cross(C[i], B[i], C[k], B[k]); if (c == 0) break; if (b % c || a % c) break; tmp[k - j].x = b / c; tmp[k - j].y = a / c; } if (k < j + 2) continue; if (tmp[1] < tmp[0]) swap(tmp[0], tmp[1]); if (p1 < tmp[0]) p1 = tmp[0]; if (tmp[1] < p2) p2 = tmp[1]; } res += max(abs(p2.x - p1.x), abs(p2.y - p1.y)); } cout << res + 4 << endl; } return 0; }
|
module top();
reg p_clk, rst_in, reg_req_t;
wire out;
weird_ff uut(p_clk, rst_in, reg_req_t, out);
initial begin
p_clk = 0;
rst_in = 1;
reg_req_t = 0;
#1;
rst_in = 0;
#1;
p_clk = 1;
#2;
p_clk = 0;
$display("%d", out);
if (out != 1'bx) begin
$display("FAILED 1 - ff was reset");
$finish;
end
#1;
rst_in = 1;
#1;
p_clk = 1;
#1;
p_clk = 0;
$display("%d", out);
if (out != 1'b0) begin
$display("FAILED 2 - ff was not reset");
$finish;
end
$display("PASSED");
end
endmodule // top
module weird_ff(p_clk, rst_in, reg_req_t, out);
input p_clk;
input rst_in;
input reg_req_t;
output out;
reg [1:0] wr_req_pipe;
parameter G_ASYNC_RESET = 0;
wire a_rst = (G_ASYNC_RESET != 0) ? rst_in : 1'b0;
wire s_rst = (G_ASYNC_RESET == 0) ? rst_in : 1'b0;
always @(posedge p_clk or posedge a_rst)
if (a_rst | s_rst)
wr_req_pipe <= 'b0;
else
wr_req_pipe <= {wr_req_pipe, reg_req_t};
assign out = wr_req_pipe[1];
endmodule // weird_ff
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_0_aw_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_0_aw_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_W\
IDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_aw_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_TB_V
`define SKY130_FD_SC_HS__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C_N = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C_N = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_TB_V
|
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
module VTAMemDPI #
( parameter LEN_BITS = 8,
parameter ADDR_BITS = 64,
parameter DATA_BITS = 64
)
(
input clock,
input reset,
input dpi_req_valid,
input dpi_req_opcode,
input [LEN_BITS-1:0] dpi_req_len,
input [ADDR_BITS-1:0] dpi_req_addr,
input dpi_wr_valid,
input [DATA_BITS-1:0] dpi_wr_bits,
output logic dpi_rd_valid,
output logic [DATA_BITS-1:0] dpi_rd_bits,
input dpi_rd_ready
);
import "DPI-C" function void VTAMemDPI
(
input byte unsigned req_valid,
input byte unsigned req_opcode,
input byte unsigned req_len,
input longint unsigned req_addr,
input byte unsigned wr_valid,
input longint unsigned wr_value,
output byte unsigned rd_valid,
output longint unsigned rd_value,
input byte unsigned rd_ready
);
typedef logic dpi1_t;
typedef logic [7:0] dpi8_t;
typedef logic [31:0] dpi32_t;
typedef logic [63:0] dpi64_t;
dpi1_t __reset;
dpi8_t __req_valid;
dpi8_t __req_opcode;
dpi8_t __req_len;
dpi64_t __req_addr;
dpi8_t __wr_valid;
dpi64_t __wr_value;
dpi8_t __rd_valid;
dpi64_t __rd_value;
dpi8_t __rd_ready;
always_ff @(posedge clock) begin
__reset <= reset;
end
// delaying outputs by one-cycle
// since verilator does not support delays
always_ff @(posedge clock) begin
dpi_rd_valid <= dpi1_t ' (__rd_valid);
dpi_rd_bits <= __rd_value;
end
assign __req_valid = dpi8_t ' (dpi_req_valid);
assign __req_opcode = dpi8_t ' (dpi_req_opcode);
assign __req_len = dpi_req_len;
assign __req_addr = dpi_req_addr;
assign __wr_valid = dpi8_t ' (dpi_wr_valid);
assign __wr_value = dpi_wr_bits;
assign __rd_ready = dpi8_t ' (dpi_rd_ready);
// evaluate DPI function
always_ff @(posedge clock) begin
if (reset | __reset) begin
__rd_valid = 0;
__rd_value = 0;
end
else begin
VTAMemDPI(
__req_valid,
__req_opcode,
__req_len,
__req_addr,
__wr_valid,
__wr_value,
__rd_valid,
__rd_value,
__rd_ready);
end
end
endmodule
|
module lba
(/*AUTOnotARG*/
// Outputs
);
/* autoinst_bits_lba_gi AUTO_TEMPLATE (
.WWCmdI (WWCmdI[]));
*/
autoinst_bits_lba_gi gi (/*AUTOINST*/
// Outputs
.WWCmdI (WWCmdI[8:0]), // Templated
.WWADI (WWADI[31:0]),
// Inouts
.WWADB (WWADB[31:0]),
.WWCmdB (WWCmdB[8:0]),
// Inputs
.CLK (CLK),
.WWADoe (WWADoe),
.WWCoe (WWCoe),
.WWCmdIfOE (WWCmdIfOE[8:0]),
.WWADHold (WWADHold),
.iWWADO (iWWADO[31:0]));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int left[n], right[n]; int leftOpen = 0, leftClose = 0, rightOpen = 0, rightClose = 0; for (int i = 0; i < n; i++) { cin >> left[i]; cin >> right[i]; if (left[i]) leftOpen += 1; else leftClose += 1; if (right[i]) rightOpen += 1; else rightClose += 1; } int minCount = 0; if (leftOpen > leftClose) minCount += leftClose; else minCount += leftOpen; if (rightOpen > rightClose) minCount += rightClose; else minCount += rightOpen; cout << minCount << endl; }
|
#include <bits/stdc++.h> using namespace std; int n; pair<long long, long long> x[4000]; long long d[4000]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) cin >> x[i].first >> x[i].second; sort(x + 1, x + n + 1); d[n] = x[n].second; for (int i = n - 1; i >= 1; i--) { d[i] = 1000000000000000000LL; long long s = 0; for (int j = i + 1; j <= n; j++) d[i] = min(d[i], s + d[j]), s += x[j].first - x[i].first; d[i] = min(d[i], s); d[i] += x[i].second; } cout << d[1] << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int x[1010], y[1010]; int lef(int x1, int y1, int x2, int y2) { if (x1) x1 = (x1 > 0 ? 1 : -1); if (y1) y1 = (y1 > 0 ? 1 : -1); if (x2) x2 = (x2 > 0 ? 1 : -1); if (y2) y2 = (y2 > 0 ? 1 : -1); if (x1 == 0 && y1 == 1) { if (x2 == 1) return 0; else return 1; } if (x1 == 0 && y1 == -1) { if (x2 == 1) return 1; else return 0; } return lef(-x2, -y2, -x1, -y1) > 0 ? 0 : 1; } int main() { int n, i, num1, num2; while (cin >> n) { for (i = 0; i <= n; i++) { scanf( %d %d , &x[i], &y[i]); } x[n + 1] = x[1]; y[n + 1] = y[1]; num1 = num2 = 0; for (i = 1; i <= n; i++) { if (lef((x[i] - x[i - 1]), (y[i] - y[i - 1]), (x[i + 1] - x[i]), (y[i + 1] - y[i]))) num1++; else num2++; } cout << min(num1, num2) << endl; } }
|
#include <bits/stdc++.h> int main() { char n[10005]; scanf( %[^ n] , n); int len = strlen(n); char temp[len + 1]; int j = 0; for (int i = 0; i < len; i++) { if (n[i] >= a && n[i] <= z ) { temp[j] = n[i]; j++; } else if (n[i] == ) { if (n[i - 1] == ) { continue; } else if (n[i + 1] == && n[i - 1] == ) { continue; } else { temp[j] = n[i]; j++; } } else if (n[i] == , || n[i] == ? || n[i] == . || n[i] == ! ) { if (n[i - 1] == ) { j--; temp[j] = n[i]; j++; } else { temp[j] = n[i]; j++; } if (n[i + 1] != ) { temp[j] = ; j++; } } } temp[j] = 0 ; printf( %s n , temp); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a = 0, b = 0, x = 0, y = 0; cin >> a >> b; x = min(a, b); y = max(a, b); cout << x << << (y - x) / 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int check(long long int a) { if (a >= 1000000000 + 7) a %= 1000000000 + 7; return a; } long long int check2(long long int a) { if (a > 0) return a; long long int b = a / 1000000000 + 7; a -= b * 1000000000 + 7; if (a < 0) a += 1000000000 + 7; return a; } long long int exp(long long int a, long long int n) { if (n == 0) return 1; if (n == 1) return check(a); long long int b = exp(a, n / 2); if (n % 2 == 0) return check(b * b); return check(b * check(b * a)); } int arr[4][4]; int main() { ios::sync_with_stdio(false); cin.tie(0); for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) cin >> arr[i][j]; for (int i = 0; i < 4; i++) { if (arr[i][3] == 1) for (int j = 0; j < 3; j++) if (arr[i][j] == 1) { cout << YES ; return 0; } } for (int i = 0; i < 4; i++) { for (int j = 0; j < 3; j++) { int k = (i + 1 + j) % 4; if (arr[i][3] == 1 && arr[i][3] == arr[k][j]) { cout << YES ; return 0; } } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int pr[2 * 100 * 1000 + 10]; int a[2 * 100 * 1000 + 10]; int main() { int max_n = 0; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > max_n) max_n = a[i]; } for (int i = 0; i <= max_n; i++) pr[i] = 1; for (int i = 2; i <= max_n; i++) if (pr[i]) { int k = 2; while (i * k <= max_n) { pr[i * k] = 0; k++; } } long long ans = 1; for (long long i = 2; i <= max_n; i++) { if (!pr[i]) continue; int bad_index = -1; long long cur = i; while (cur <= max_n) { int cnt = 0; int new_bad = -1; for (int j = 0; j < n; j++) if (j != bad_index && a[j] % cur) { cnt++; new_bad = j; if (cnt > 1) break; } if (cnt > 1) break; if (bad_index != -1 && new_bad != -1) break; if (bad_index == -1) bad_index = new_bad; ans *= i; cur *= i; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e3 + 5, mod = 1e9 + 7; struct p { int x, y; } c[N]; int n, D, num; int h[N], w[N]; int f[N][N]; int read() { int x(0); char ch = getchar(); for (; !isdigit(ch); ch = getchar()) ; for (; isdigit(ch); x = x * 10 + ch - 48, ch = getchar()) ; return x; } void add(int x, int y) { c[++num] = (p){h[x], y}, h[x] = num; } void dfs(int x = 1) { for (int i = 1; i <= n; ++i) f[x][i] = 1; for (int i = h[x]; i; i = c[i].x) { dfs(c[i].y); for (int j = 1; j <= n; ++j) f[x][j] = 1ll * f[x][j] * f[c[i].y][j] % mod; } for (int i = 1; i <= n; ++i) { f[x][i] += f[x][i - 1]; if (f[x][i] >= mod) f[x][i] -= mod; } } int Pow(int a, int b) { int ans = 1; for (; b; b >>= 1, a = 1ll * a * a % mod) if (b & 1) ans = 1ll * ans * a % mod; return ans; } int L(int x) { int ans = 1; for (int i = 0; i <= n; ++i) if (x != i) ans = (1ll * ans * (D - i) % mod * (x - i < 0 ? -1 : 1) * w[x - i < 0 ? i - x : x - i] % mod + mod) % mod; return ans; } void Solve() { if (n >= D) return void(printf( %d , f[1][D])); int ans = 0; for (int i = 1; i <= n; ++i) w[i] = Pow(i, mod - 2); for (int i = 0; i <= n; ++i) { ans += 1ll * f[1][i] * L(i) % mod; if (ans >= mod) ans -= mod; } printf( %d , ans); } int main() { n = read(), D = read(); for (int i = 2; i <= n; ++i) add(read(), i); return dfs(), Solve(), 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); int main() { double d, h, v, e; while (scanf( %lf%lf%lf%lf , &d, &h, &v, &e) != EOF) { double t = v / (PI * (d / 2) * (d / 2)); if (t > e) { printf( YES n ); double ti = h / (t - e); printf( %lf n , ti); } else printf( NO n ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cx4_datrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cx4_datrom (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({24{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "cx4_datrom.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "cx4_datrom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "cx4_datrom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int i; double a, b, c, d, base, top, mid, x11, x22, y11, y22, minim1, minim2, maxim1, maxim2; int main() { scanf( %lf%lf%lf%lf , &a, &b, &c, &d); base = 0.0; top = 1000000000.0; for (i = 1; i <= 100; i++) { mid = (base + top) / 2.0; x11 = a - mid; x22 = a + mid; y11 = d - mid; y22 = d + mid; minim1 = min(min(x11 * y11, x11 * y22), min(x22 * y11, x22 * y22)); maxim1 = max(max(x11 * y11, x11 * y22), max(x22 * y11, x22 * y22)); x11 = b - mid; x22 = b + mid; y11 = c - mid; y22 = c + mid; minim2 = min(min(x11 * y11, x11 * y22), min(x22 * y11, x22 * y22)); maxim2 = max(max(x11 * y11, x11 * y22), max(x22 * y11, x22 * y22)); if (maxim1 < minim2 || maxim2 < minim1) base = mid; else top = mid; } printf( %.9lf n , top); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
wire GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
wire GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long nxt(long long x) { long long mn = 10; long long mx = 0; long long xx = x; while (x > 0) { mn = min(mn, x % 10); mx = max(mx, x % 10); x /= 10; } return xx + mn * mx; } signed main() { long long t; cin >> t; while (t--) { long long a1, k; cin >> a1 >> k; k--; while (k--) { if (a1 == nxt(a1)) break; a1 = nxt(a1); } cout << a1 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; vector<int> p; int a[27] = {0}; for (int i = 0; i < s.size(); i++) { if (s[i] == ? ) { p.push_back(i); } else { a[int(s[i]) - 96]++; } } if (p.size() == 0) { cout << s; return 0; } int i = 0, j = 0; while (j < p.size()) { if (i == t.size()) { i = 0; } if (a[int(t[i]) - 96] > 0) { a[int(t[i]) - 96]--; } else { s[p[j]] = t[i]; j++; } i++; } cout << s << endl; }
|
`include "commands.vh"
module communication(
input wire clk,
output reg transmit=0,
output reg [7:0] tx_byte=0,
input wire received,
input wire [7:0] rx_byte,
output reg en=0,
output wire [39:0] m,
output reg set=0,
output reg error=0
);
reg [7:0] state=0;
reg [7:0] command=0;
reg [7:0] m0=0, m1=0, m2=0, m3=0, m4=0;
reg [23:0] count=0;
assign m = {m4, m3, m2, m1, m0};
// state machine to receive data from the UART
always @ (posedge clk)
begin
case(state)
0: begin
if (received == 1) begin
case(rx_byte)
`BYTE0: begin
command = rx_byte;
state=1;
end
`BYTE1: begin
command = rx_byte;
state=1;
end
`BYTE2: begin
command = rx_byte;
state=1;
end
`BYTE3: begin
command = rx_byte;
state=1;
end
`BYTE4: begin
command = rx_byte;
state=1;
end
`ENABLE: state = 2;
`DISABLE: state = 3;
`SET: state = 4;
default: state = 8;
endcase
end
end
1: begin
if (received == 1)
begin
case(command)
`BYTE0: m0 = rx_byte;
`BYTE1: m1 = rx_byte;
`BYTE2: m2 = rx_byte;
`BYTE3: m3 = rx_byte;
`BYTE4: m4 = rx_byte;
endcase
state=6;
end
end
2: begin
en=1;
state=6;
end
3: begin
en=0;
state=6;
end
4: begin
set=1;
state=5;
end
5: begin
set=0;
state=6;
end
6: begin
tx_byte=`ACK;
transmit=1;
state=7;
end
7: begin
transmit=0;
state=0;
end
8: begin // error state
error=1;
count=count+1;
if (count>12000000) state=9;
end
9: begin
error=0;
count=0;
state=0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<vector<pair<int, int>>> g; vector<int> p; vector<bool> was; vector<int> sz; long long res; void calcSz(int v, int par = -1) { sz[v] = 1; for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (to != par && !was[to]) { calcSz(to, v); sz[v] += sz[to]; } } } int findCentroid(int v, int n, int par = -1) { for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (to != par && !was[to] && 2 * sz[to] > n) { return findCentroid(to, n, v); } } return v; } int getInc(int v, int edge, int par = -1) { int res = 1; for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (to != par && !was[to] && g[v][i].second >= edge) { res += getInc(to, g[v][i].second, v); } } return res; } int getDec(int v, int edge, int par = -1) { int res = 1; for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (to != par && !was[to] && g[v][i].second <= edge) { res += getDec(to, g[v][i].second, v); } } return res; } int build(int v) { calcSz(v); v = findCentroid(v, sz[v]); was[v] = true; int inc0 = 0; int inc1 = 0; int dec0 = 0; int dec1 = 0; for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (!was[to]) { int inc = getInc(to, g[v][i].second, v); int dec = getDec(to, g[v][i].second, v); if (g[v][i].second == 0) { res += inc * 1ll * (dec0 + 1); res += dec * 1ll * (inc0 + inc1 + 1); inc0 += inc; dec0 += dec; } else { res += inc * 1ll * (dec0 + dec1 + 1); res += dec * 1ll * (inc1 + 1); inc1 += inc; dec1 += dec; } } } for (int i = 0; i < (int)g[v].size(); ++i) { int to = g[v][i].first; if (!was[to]) { p[build(to)] = v; } } return v; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; g.resize(n); p.resize(n); was.resize(n); sz.resize(n); for (int i = 0; i < n - 1; ++i) { int a, b, c; cin >> a >> b >> c; --a; --b; g[a].push_back({b, c}); g[b].push_back({a, c}); } build(0); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[128][128][15]; int board[128][128]; int dy[] = {-1, 1}; int N, M, K; int solve(int x, int y, int k) { if (dp[x][y][k] != -2) return dp[x][y][k]; if (x == 0) { if (board[x][y] % K == k) return dp[x][y][k] = board[x][y]; else return dp[x][y][k] = -1; } int curr = board[x][y]; int ans = -1; int req = (K + k - (curr % K)) % K; for (int i = 0; i < 2; i++) { int nx = x - 1, ny = y + dy[i]; if (nx < 0 || ny < 0 || nx >= N || ny >= M) continue; int ret = solve(nx, ny, req); if (ret != -1) { ans = max(ans, curr + ret); } } return dp[x][y][k] = ans; } void print(int x, int y, int k) { int curr = board[x][y]; int req = (K + k - (curr % K)) % K; for (int i = 0; i < 2; i++) { int nx = x - 1, ny = y + dy[i]; if (nx < 0 || ny < 0 || nx >= N || ny >= M) continue; if (dp[x][y][k] == curr + dp[nx][ny][req]) { if (i == 0) cout << L ; else cout << R ; print(nx, ny, req); return; } } } int main() { cin >> N >> M >> K; K += 1; for (int i = 0; i < N; i++) { string s; cin >> s; for (int j = 0; j < M; j++) board[i][j] = s[j] - 0 ; } for (int i = 0; i < N; i++) for (int j = 0; j < M; j++) for (int k = 0; k < K; k++) dp[i][j][k] = -2; int ans = -1; int maxI = 0; for (int i = 0; i < M; i++) { int ret = solve(N - 1, i, 0); if (ret != -1 && ret > ans) { ans = ret; maxI = i; } } if (ans == -1) { cout << -1 << endl; return 0; } cout << ans << endl; cout << maxI + 1 << endl; print(N - 1, maxI, 0); cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[1000]; int n, k; scanf( %d , &n); scanf( %d , &k); for (int i = 0; i < 2 * n + 1; i++) { scanf( %d , &a[i]); } for (int i = 1; i < 2 * n + 1; i += 2) { if (a[i] - 1 > a[i + 1] && a[i] - 1 > a[i - 1]) { a[i]--; k--; } if (k == 0) { break; } } for (int i = 0; i < 2 * n + 1; i++) { if (i) { printf( ); } printf( %d , a[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { for (auto v : V) os << v << ; return cout << ; } template <class T> ostream& operator<<(ostream& os, set<T> S) { for (auto s : S) os << s << ; return cout << ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << P.first << << P.second; } const long long mod = 1e9 + 7; long long inv(long long i) { if (i == 1) return 1; return (mod - ((mod / i) * inv(mod % i)) % mod) % mod; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long pwr(long long a, long long b) { a %= mod; long long res = 1; while (b > 0) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T = 1; cin >> T; while (T--) { int n, c0, c1, h, x = 0, y = 0; cin >> n >> c0 >> c1 >> h; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == 0 ) x++; else y++; } if (c0 >= c1 + h) { cout << x * h + n * c1 << n ; } else if (c1 >= c0 + h) { cout << y * h + n * c0 << n ; } else { cout << x * c0 + y * c1 << n ; } } }
|
#include <bits/stdc++.h> int r, g, b; int mins; int total; int tour; int cycles; int main() { scanf( %d %d %d , &r, &g, &b); if (r >= 2) { r -= 2; } else if (r == 1) { r -= 1; } mins = 30; tour = 1; total = r + g + b; while (total > 0) { if (tour == 1) { if (g >= 2) { g -= 2; } else if (g == 1) { g -= 1; } tour = 2; } else if (tour == 2) { if (b >= 2) { b -= 2; } else if (b == 1) { b -= 1; } tour = 0; } else if (tour == 0) { if (r >= 2) { r -= 2; } else if (r == 1) { r -= 1; } tour = 1; } total = r + g + b; cycles++; } mins += cycles; printf( %d , mins); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:21 09/19/2015
// Design Name: figuras_Gato
// Module Name: /home/manzumbado/Development/HDL/Xilinx/GatoTDD/trunk/figuras_test.v
// Project Name: GatoTDD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: figuras_Gato
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module figuras_test;
// Inputs
reg video_mostrar;
reg [3:0] entrada;
reg [9:0] pixel_x;
reg [9:0] pixel_y;
// Outputs
wire [2:0] salida_rgb;
// Instantiate the Unit Under Test (UUT)
figuras_Gato uut (
.video_mostrar(video_mostrar),
.entrada(entrada),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.salida_rgb(salida_rgb)
);
initial begin
// Initialize Inputs
video_mostrar = 1;
entrada = 0;
pixel_x = 9'd160;
pixel_y = 9'd120;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
end
always @ (*) begin
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
#10
pixel_x= pixel_x+1;
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_0_1 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [13 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(2)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int safeop(int n, int mod) { return (n + mod) % mod; } int main() { int n; cin >> n; vector<int> v(n, 0); vector<pair<int, int>> ans(n); for (int i = 0; i < n; i++) { cin >> v[i]; } int vn = n; int v1 = -1; stack<int> bal1; stack<int> bal2; stack<int> bal3; for (int i = 0; i < n; i++) { if (v[i] == 3) { if (vn - v1 == 1) { cout << -1; return 0; } vn--; ans[i] = make_pair(vn, -1); if (!bal3.empty()) { int tmp = bal3.top(); bal3.pop(); ans[tmp].second = i; bal3.push(i); } else { bal3.push(i); } } else if (v[i] == 2) { if (vn - v1 == 1) { cout << -1; return 0; } v1++; ans[i] = make_pair(v1, -1); if (!bal3.empty()) { int tmp = bal3.top(); bal3.pop(); ans[tmp].second = i; bal2.push(i); } else { bal2.push(i); } } else if (v[i] == 1) { if (!bal2.empty()) { int tmp = bal2.top(); bal2.pop(); ans[tmp].second = i; ans[i] = make_pair(ans[tmp].first, 0); } else if (!bal3.empty()) { if (vn - v1 == 1) { cout << -1; return 0; } vn--; ans[i] = make_pair(vn, 0); int tmp = bal3.top(); bal3.pop(); ans[tmp].second = i; } else { if (vn - v1 == 1) { cout << -1; return 0; } vn--; ans[i] = make_pair(vn, 0); } } else { continue; } } for (int i = 0; i < n; i++) { if (ans[i].second == -1) { cout << -1 << endl; return 0; } } set<pair<int, int>> ansset; for (int i = 0; i < n; i++) { if (v[i] == 1) { ansset.insert(make_pair(i + 1, ans[i].first + 1)); } if (v[i] == 2) { ansset.insert(make_pair(i + 1, ans[i].first + 1)); ansset.insert(make_pair(ans[i].second + 1, ans[i].first + 1)); } if (v[i] == 3) { ansset.insert(make_pair(i + 1, ans[i].first + 1)); ansset.insert(make_pair(ans[i].second + 1, ans[i].first + 1)); ansset.insert(make_pair(ans[i].second + 1, ans[ans[i].second].first + 1)); } } cout << ansset.size() << endl; for (auto it = ansset.begin(); it != ansset.end(); ++it) { cout << n + 1 - it->second << << it->first << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, k, l, m, n; cin >> n; if (n & 1) cout << 1 << endl; else cout << 2 << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, k, A[2005], DP[2005]; inline int ok(int X) { memset(DP, 0, sizeof(DP)); int i, j; long long l1, r1, l2, r2; for (i = 1; i <= n; i++) DP[i] = i - 1; for (i = 2; i <= n; i++) if (abs(A[i] - A[i - 1]) <= X) DP[i] = 0; else break; for (i = 1; i <= n; i++) for (j = i + 1; j <= n; j++) { l1 = (long long)A[i] - (long long)X * (j - i - 1); r1 = (long long)A[i] + (long long)X * (j - i - 1); l2 = A[j] - X; r2 = A[j] + X; if (!(l2 > r1 || l1 > r2)) DP[j] = min(DP[j], DP[i] + j - i - 1); } for (i = 1; i <= n; i++) if (DP[i] + n - i <= k) return 1; return 0; } int cbin() { int i, step = (1 << 30); for (i = -1; step; step >>= 1) if (!ok(i + step)) i += step; return ++i; } int main() { scanf( %d%d , &n, &k); int i; for (i = 1; i <= n; i++) scanf( %d , &A[i]); printf( %d n , cbin()); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, mod; pair<long long, long long> a[200100]; long long d[200100]; long long first(int t, int k) { long long res = 1; for (int i = 1; i <= k; i++) d[i] = i; for (int j = 2; t;) if (d[j] % 2) j += 2; else while (d[j] % 2 == 0 && t) { d[j] /= 2; t--; } for (int i = 1; i <= k; i++) res = (res * d[i]) % mod; return res; } int main() { cin >> n; for (int i = 0; i < 2 * n; ++i) { cin >> a[i].first; a[i].second = (i % n) + 1; } sort(a, a + 2 * n); cin >> mod; long long r = 1; for (int i = 0; i < 2 * n; i++) { long long k, t = 0; for (k = i + 1; k < 2 * n && a[k].first == a[i].first; k++) if (a[k].second == a[k - 1].second) t++; k--; r = (r * first(t, k - i + 1)) % mod; i = k; } cout << r; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } bool sortinrev(const pair<int, int>& a, const pair<int, int>& b) { if (a.first == b.first) return b.second > a.second; return a.first > b.first; } void run(vector<int> v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } int modInverse(long long int a, long long int m) { long long int m0 = m; long long int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long int q = a / m; long long int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } void numberOfNodes(int n, vector<long long int> adj[], vector<long long int>& count1, int s, int e) { vector<long long int>::iterator u; count1[s] = 1; for (u = adj[s].begin(); u != adj[s].end(); u++) { if (*u == e) continue; numberOfNodes(n, adj, count1, *u, s); count1[s] += count1[*u]; } } void solve() { int n, k, unhappy = 0; cin >> n >> k; vector<pair<int, int>> edges; vector<int> adj[n + 1]; unordered_map<int, int> mp[n + 1]; vector<bool> vis(n + 1, 0); for (int i = 0; i < k; i++) { int x, y; cin >> x >> y; if (mp[x].find(y) == mp[x].end()) { mp[x][y]++; mp[y][x]++; edges.push_back({x, y}); adj[x].push_back(y); adj[y].push_back(x); } } unhappy += (k - edges.size()); k -= unhappy; queue<int> q; int ans = 0; for (int i = 1; i <= n; i++) { if (!vis[i]) { q.push(i); vector<int> vec; vis[i] = 1; vec.push_back(i); while (!q.empty()) { int p = q.front(); q.pop(); for (int j = 0; j < adj[p].size(); j++) { if (!vis[adj[p][j]]) { vec.push_back(adj[p][j]); vis[adj[p][j]] = 1; q.push(adj[p][j]); } } } ans += (vec.size() - 1); } } cout << unhappy + k - ans << endl; } int main() { int t; t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; while (scanf( %d%d , &n, &m) != EOF) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (i % 2 == 0) { printf( # ); } else { if (i / 2 % 2 == 0 && j == m - 1) printf( # ); else if (i / 2 % 2 != 0 && j == 0) printf( # ); else printf( . ); } } puts( ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_1_V
`define SKY130_FD_SC_LS__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_1_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module SDPRAM_16A9024X32B4512 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [15 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [12 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [31 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("SDPRAM_16A9024X32B4512.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(9024),
.C_READ_DEPTH_A(9024),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(4512),
.C_READ_DEPTH_B(4512),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(1),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 8.994245 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(32'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; set<string> f; int main() { int n; cin >> n; int ans = 0; for (int i = 0; i < n; ++i) { string s = ; while (1) { char c; cin >> c; if (isdigit(c)) s += c; if (((int)(s).size()) == 4) break; } swap(s[2], s[3]); string t = s; for (int i = 0; i < 4; ++i) { char c = s[0]; for (int j = 0; j < 3; ++j) s[j] = s[j + 1]; s[3] = c; if (s < t) t = s; } if (!f.count(t)) ++ans; f.insert(t); } cout << ans << endl; return 0; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/08/11 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
|
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const int maxn = 1e5 + 5; const int mod = 1e9 + 7; const double eps = 1e-7; using namespace std; long long ans, n, s, a[maxn], b[maxn], num1, num2; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > to1, to2; void init() { ans = 0; num1 = 0; num2 = 0; while (to1.size()) to1.pop(); while (to2.size()) to2.pop(); memset(a, 0, sizeof(a)), memset(b, 0, sizeof(b)); } int main() { while (~scanf( %lld%lld , &n, &s)) { init(); for (int i = 0; i <= n - 1; ++i) { long long s, a, b; scanf( %lld%lld%lld , &s, &a, &b); if (a > b) { num1 += s; ans += s * a; to2.push(pair<long long, long long>(a - b, s)); } else { num2 += s; ans += s * b; to1.push(pair<long long, long long>(b - a, s)); } } num1 %= s, num2 %= s; if (num1 + num2 > s) { printf( %lld n , ans); continue; } else { long long tmp1 = num1, tmp2 = num2, cost1 = 0, cost2 = 0; while (tmp1) { pair<long long, long long> tmp = to2.top(); to2.pop(); long long num = min(tmp1, tmp.second); tmp1 -= num; cost1 += num * tmp.first; } while (tmp2) { pair<long long, long long> tmp = to1.top(); to1.pop(); int num = min(tmp2, tmp.second); tmp2 -= num; cost2 += num * tmp.first; } printf( %lld n , max(ans - cost1, ans - cost2)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, k; pair<int, int> a[N]; long long b, s; int main() { cin >> n >> k; cin >> b; for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + n, greater<pair<int, int> >()); for (int i = 1; i <= k; i++) s += a[i].first; long long res = n; if (s > b) for (int i = 1; i <= k; i++) res = min(res, (long long)a[i].second); for (int i = k + 1; i < n; i++) if (s - a[k].first + a[i].first > b) res = min(res, (long long)a[i].second); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long int t; cin >> t; while (t--) { long long int a, b, c, d; cin >> a >> b; if (a % b == 0) cout << 0 << endl; else if (b > a) cout << (b - a) << endl; else { c = a / b; c++; c = c * b; cout << (c - a) << endl; } } return 0; }
|
//
// Copyright 2011, Kevin Lindsey
// See LICENSE file for licensing information
//
// Based on code from Richard Haskell and Darrin Hanna's,
// "Learning by Example Using Verilog: Basic Digital Design", 2008
// Chapter 5, Example 15, 7-Segment Displays
//
module hex_7_segment(
input wire [15:0] x,
input wire clk,
input wire clr,
output reg [6:0] a_to_g,
output reg [3:0] an
);
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [18:0] clkdiv;
assign s = clkdiv[18:17];
//assign aen[3] = x[15] | x[14] | x[13] | x[12];
//assign aen[2] = x[15] | x[14] | x[13] | x[12]
// | x[11] | x[10] | x[9] | x[8];
//assign aen[1] = x[15] | x[14] | x[13] | x[12]
// | x[11] | x[10] | x[9] | x[8]
// | x[7] | x[6] | x[5] | x[4];
//assign aen[0] = 1;
assign aen = 4'b1111;
always @(*)
case (s)
0: digit = x[3:0];
1: digit = x[7:4];
2: digit = x[11:8];
3: digit = x[15:12];
default: digit = x[3:0];
endcase
always @(*)
case (digit)
'h0: a_to_g = 7'b0000001;
'h1: a_to_g = 7'b1001111;
'h2: a_to_g = 7'b0010010;
'h3: a_to_g = 7'b0000110;
'h4: a_to_g = 7'b1001100;
'h5: a_to_g = 7'b0100100;
'h6: a_to_g = 7'b0100000;
'h7: a_to_g = 7'b0001111;
'h8: a_to_g = 7'b0000000;
'h9: a_to_g = 7'b0000100;
'ha: a_to_g = 7'b0001000;
'hb: a_to_g = 7'b1100000;
'hc: a_to_g = 7'b0110001;
'hd: a_to_g = 7'b1000010;
'he: a_to_g = 7'b0110000;
'hf: a_to_g = 7'b0111000;
default: a_to_g = 7'b0000001;
endcase
always @(*)
begin
an = 4'b0000;
if (aen[s] == 1)
an[s] = 1;
end
always @(posedge clk or posedge clr)
begin
if (clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
|
#include <bits/stdc++.h> int main() { int tc; std::cin >> tc; while (tc--) { int64_t a, b, c; std::cin >> a >> b >> c; std::cout << a + b + c - 1 << std::endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int S; cin >> S; if (S == 1) { cout << 1 << << 1 << n ; cout << 1 << n ; return 0; } cout << (S - 1) * 2 << << 2 << n ; cout << 1 << << 2; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> a(n), b(n); for (int i = 0; i < n; ++i) cin >> a[i] >> b[i]; int maxCap = b[0], curCap = b[0]; for (int i = 1; i < n; ++i) { curCap = curCap - a[i] + b[i]; maxCap = max(maxCap, curCap); } cout << maxCap << n ; return 0; }
|
module memory_tb;
// Constants
parameter data_width = 32;
parameter address_width = 32;
parameter depth = ;
parameter bytes_in_word = 4-1; // -1 for 0 based indexed
parameter bits_in_bytes = 8-1; // -1 for 0 based indexed
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
reg clock;
reg [address_width-1:0] address;
reg [data_width-1:0] data_in;
reg [1:0] access_size;
reg rw;
reg enable;
// Output Ports
wire busy;
wire [data_width-1:0] data_out;
// fileIO stuff
integer fd;
integer scan_fd;
integer status_read, status_write;
integer sscanf_ret;
integer words_read;
integer words_written;
reg [31:0] line;
reg [31:0] data_read;
// Instantiate the memory
memory M0 (
.clock (clock),
.address (address),
.data_in (data_in),
.access_size (access_size),
.rw (rw),
.enable (enable),
.busy (busy),
.data_out (data_out)
);
initial begin
fd = $fopen("SumArray.x", "r");
if (!fd)
$display("Could not open");
clock = 0;
address = start_addr;
scan_fd = $fscanf(fd, "%x", data_in);
//data_in = 0;
access_size = 2'b0_0;
enable = 1;
rw = 0; // Start writing first.
words_read = 0;
words_written = 1;
end
always @(posedge clock) begin
if (rw == 0) begin
enable = 1;
//rw = 0;
scan_fd = $fscanf(fd, "%x", line);
if (!$feof(fd)) begin
data_in = line;
$display("line = %x", data_in);
address = address + 4;
words_written = words_written + 1;
end
else begin
rw = 1;
address = 32'h80020000;
end
end
else if ($feof(fd) && (words_read < words_written)) begin
// done writing, now read...
rw = 1;
enable = 1;
data_read = data_out;
$display("data_read = %x", data_read);
address = address + 4;
words_read = words_read + 1;
end
else if (words_read >= words_written) begin
// TODO: Add logic to end simulation.
end
end
always
#5 clock = ! clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> using V = vector<T>; const long long mod = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); string s; V<V<size_t> > p[2]; p[0].resize(8); p[1].resize(8); for (__typeof(8) i = (0) - ((0) > (8)); i != (8) - ((0) > (8)); i += ((0) > (8) ? -1 : 1)) { cin >> s; for (__typeof(s.size()) j = (0) - ((0) > (s.size())); j != (s.size()) - ((0) > (s.size())); j += ((0) > (s.size()) ? -1 : 1)) { if (s[j] == B ) p[0][j].push_back(i); else if (s[j] == W ) p[1][j].push_back(i); } } size_t mnA = INT_MAX, mnB = INT_MAX; for (__typeof(8) i = (0) - ((0) > (8)); i != (8) - ((0) > (8)); i += ((0) > (8) ? -1 : 1)) { if (!p[1][i].empty() && (p[0][i].empty() || p[0][i][0] > p[1][i][0])) { mnA = min(mnA, p[1][i][0]); } if (!p[0][i].empty() && (p[1][i].empty() || p[1][i].back() < p[0][i].back())) { mnB = min(mnB, 7 - p[0][i].back()); } } cout << (mnA <= mnB ? A : B ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:18:04 03/09/2015
// Design Name:
// Module Name: Instruction_Memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Instruction_Memory(
output [15 : 0] data_out,
input [15 : 0] address
);
//reg [7 : 0] memory [255 : 0];
reg [15 : 0] memory [255 : 0];
initial
begin
/*memory[0] = 16'b0110100100001000;
memory[1] = 16'b0110101100000100;
memory[2] = 16'b0100100100000001;
memory[3] = 16'b1110000101100111;
memory[4] = 16'b1101100101100001;
memory[5] = 16'b1001101100100010;
memory[6] = 16'b0010100100000001;
memory[7] = 16'b1110100000000000;
memory[8] = 16'b0110110000001011;
memory[9] = 16'b1111010000000001;
memory[10] = 16'b1111000100000000;
memory[11] = 16'b0111100100000000;
memory[12] = 16'b1110100110001101;
memory[13] = 16'b0000100000000000;
memory[14] = 16'b1110100101000000;
memory[15] = 16'b0111000100001111;
memory[16] = 16'b0110000111111111;
memory[17] = 16'b1110100101101100;
memory[18] = 16'b0011000100100110;
memory[19] = 16'b1110101100100100;
memory[20] = 16'b1000000000000000;*/
memory[0] = 16'h6fbf;
memory[1] = 16'h37e0;
memory[2] = 16'h6901;
memory[3] = 16'h6a01;
memory[4] = 16'h6c01;
memory[5] = 16'hdf40;
memory[6] = 16'hdf80;
memory[7] = 16'he944;
memory[8] = 16'hdf40;
memory[9] = 16'he451;
memory[10] = 16'hdf80;
memory[11] = 16'heb42;
memory[12] = 16'h6101;
memory[13] = 16'h10f9;
memory[14] = 16'h6901;
memory[15] = 16'h6a0f;
memory[16] = 16'h7c20;
memory[17] = 16'hea84;
memory[18] = 16'hdf80;
memory[19] = 16'h6a03;
memory[20] = 16'hea87;
memory[21] = 16'hdf80;
memory[22] = 16'h6a04;
memory[23] = 16'hea87;
memory[24] = 16'hdf80;
memory[25] = 16'hea87;
memory[26] = 16'hdf80;
memory[27] = 16'hea87;
memory[28] = 16'hdf80;
memory[29] = 16'h6901;
memory[30] = 16'h6a0f;
memory[31] = 16'h7c20;
memory[32] = 16'hea84;
memory[33] = 16'hea87;
memory[34] = 16'h6900;
memory[35] = 16'h6a04;
memory[36] = 16'h6b0c;
memory[37] = 16'h4901;
memory[38] = 16'h6d0f;
memory[39] = 16'he9ac;
memory[40] = 16'hea84;
memory[41] = 16'hec2d;
memory[42] = 16'hdf80;
memory[43] = 16'hea84;
memory[44] = 16'hec2d;
memory[45] = 16'hdf80;
memory[46] = 16'hea84;
memory[47] = 16'hec2d;
memory[48] = 16'hdf80;
memory[49] = 16'hea84;
memory[50] = 16'hec2d;
memory[51] = 16'hdf80;
memory[52] = 16'h4901;
memory[53] = 16'he9ac;
memory[54] = 16'heb24;
memory[55] = 16'hea86;
memory[56] = 16'hec2d;
memory[57] = 16'hdf80;
memory[58] = 16'hea86;
memory[59] = 16'hec2d;
memory[60] = 16'hdf80;
memory[61] = 16'hea86;
memory[62] = 16'hec2d;
memory[63] = 16'hdf80;
memory[64] = 16'hea86;
memory[65] = 16'hec2d;
memory[66] = 16'hdf80;
memory[67] = 16'heb26;
memory[68] = 16'he96a;
memory[69] = 16'h61df;
memory[70] = 16'h8000;
/*memory[0] = 16'b0110111110111111;
memory[1] = 16'b0011011111100000;
memory[2] = 16'b0110100101001000;
memory[3] = 16'b0110101100000000;
memory[4] = 16'b1101101100100000;
memory[5] = 16'b0110100101100101;
memory[6] = 16'b1101101100100001;
memory[7] = 16'b0110100101101100;
memory[8] = 16'b1101101100100010;
memory[9] = 16'b0110100101101100;
memory[10] = 16'b1101101100100011;
memory[11] = 16'b0110100101101111;
memory[12] = 16'b1101101100100100;
memory[13] = 16'b0110100100101100;
memory[14] = 16'b1101101100100101;
memory[15] = 16'b0110100100100000;
memory[16] = 16'b1101101100100110;
memory[17] = 16'b0110100101110111;
memory[18] = 16'b1101101100100111;
memory[19] = 16'b0110100101101111;
memory[20] = 16'b1101101100101000;
memory[21] = 16'b0110100101110010;
memory[22] = 16'b1101101100101001;
memory[23] = 16'b0110100101101100;
memory[24] = 16'b1101101100101010;
memory[25] = 16'b0110100101100100;
memory[26] = 16'b1101101100101011;
memory[27] = 16'b0110100100100001;
memory[28] = 16'b1101101100101100;
memory[29] = 16'b0110100100000000;
memory[30] = 16'b1101101100101101;
memory[31] = 16'b0110110000000000;
memory[32] = 16'b0110100100000000;
memory[33] = 16'b1001100101100000;
memory[34] = 16'b0010001100000111;
memory[35] = 16'b0100100100000001;
memory[36] = 16'b0101101101111011;
memory[37] = 16'b0110000011111011;
memory[38] = 16'b0101101101100001;
memory[39] = 16'b0110000111111001;
memory[40] = 16'b0100110000000001;
memory[41] = 16'b0001011111110111;
memory[42] = 16'b1101111110000000;
memory[43] = 16'b1000000000000000;*/
end
//assign data_out = {memory[address], memory[address+1]}; // big-end or little-end?
assign data_out = memory[address];
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long SIZE = (long long)1e6 + 50; const long long NUM = 15; const long long TOT = 5; const long long SUM = (long long)1e2 + 50; const long long inf = (long long)1e18 + 50; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return f * x; } long long n, ans; long long num[SIZE], high[SIZE], ls[SIZE], rs[SIZE], cnt[SIZE]; signed main() { n = read(); long long indax = 0; for (long long i = 0; i < n; ++i) num[i] = read(); for (long long i = 1; i < n; ++i) if (num[i] > num[indax]) indax = i; for (long long i = 0; i <= n; ++i) high[i] = num[(i + indax) % n]; for (long long i = 1; i <= n; ++i) { ls[i] = i - 1; while (ls[i] && high[i] >= high[ls[i]]) ls[i] = ls[ls[i]]; } for (long long i = n - 1; i >= 0; --i) { rs[i] = i + 1; while (rs[i] < n && high[i] > high[rs[i]]) rs[i] = rs[rs[i]]; if (rs[i] < n && high[i] == high[rs[i]]) { cnt[i] = cnt[rs[i]] + 1; rs[i] = rs[rs[i]]; } } for (long long i = 0; i < n; ++i) { ans += cnt[i]; if (high[i] < high[0]) { ans += 2; if (!ls[i] && rs[i] == n) ans--; } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double epsilon = 1e-9; int main() { int n; cin >> n; vector<int> a(n), b(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; vector<pair<int, int> > moves; for (int i = 0; i < n; i++) { if (b[i] != a[i]) { for (int j = i + 1; j < n; j++) { if (b[j] == a[i]) { for (int k = j; k > i; k--) { moves.push_back(make_pair(k - 1, k)); swap(b[k], b[k - 1]); } break; } } } } cout << moves.size() << endl; for (int i = 0; i < moves.size(); i++) cout << moves[i].first + 1 << << moves[i].second + 1 << endl; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: IPfifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module IPfifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrempty,
wrusedw);
input aclr;
input [9:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [9:0] q;
output rdempty;
output [13:0] rdusedw;
output wrempty;
output [13:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire1;
wire [13:0] sub_wire2;
wire sub_wire3;
wire [13:0] sub_wire4;
wire [9:0] q = sub_wire0[9:0];
wire rdempty = sub_wire1;
wire [13:0] rdusedw = sub_wire2[13:0];
wire wrempty = sub_wire3;
wire [13:0] wrusedw = sub_wire4[13:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrempty (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrfull ());
defparam
dcfifo_component.add_usedw_msb_bit = "ON",
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 8192,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 10,
dcfifo_component.lpm_widthu = 14,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "8192"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "10"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "10"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "14"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 14 0 OUTPUT NODEFVAL "rdusedw[13..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 14 0 OUTPUT NODEFVAL "wrusedw[13..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 14 0 @rdusedw 0 0 14 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 14 0 @wrusedw 0 0 14 0
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[100000]; bool b[100000]; int c[3][100000 / 3]; int main() { int n; while (cin >> n) { memset(a, 0, sizeof(a)); memset(b, true, sizeof(b)); bool flag = true; int sum1 = 0; int sum2, sum3; sum2 = sum3 = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 5 || a[i] == 7) flag = false; if (a[i] == 1) sum1++; if (a[i] == 2 || a[i] == 3) sum2++; if (a[i] == 4 || a[i] == 6) sum3++; } if (sum1 != n / 3 || sum2 != n / 3 || sum3 != n / 3) flag = false; if (!flag) cout << -1 << endl; else { sort(a, a + n); for (int i = 0; i < n / 3; i++) { c[0][i] = a[i]; c[1][i] = a[i + n / 3]; c[2][i] = a[i + 2 * n / 3]; if (c[1][i] == 3 && c[2][i] == 4) flag = false; } if (flag) { for (int i = 0; i < n / 3; i++) cout << c[0][i] << << c[1][i] << << c[2][i] << endl; } else cout << -1 << endl; } } return 0; }
|
#include <bits/stdc++.h> int m, n, W, i, j, k, a[555555], b[555555], c[555555]; long long w[555555], rs; double rq; void solve(int l, int r, long long x) { if (l == r) { rs += (x * c[b[l]]) / w[b[l]]; rq += double((x * c[b[l]]) % w[b[l]]) / w[b[l]]; return; } int i = l, j = r, k, h = b[(l + r) >> 1]; long long e, f; while (i <= j) { while (c[b[i]] * w[h] < c[h] * w[b[i]]) i++; while (c[b[j]] * w[h] > c[h] * w[b[j]]) j--; if (i <= j) { k = b[i]; b[i++] = b[j]; b[j--] = k; } } for (f = e = 0, k = l; k < i; k++) { f += w[b[k]]; e += c[b[k]]; if (f >= x) break; } if (k == i) { rs += e; solve(i, r, x - f); } else if (k > j) { f -= w[b[k]]; e -= c[b[k]]; rs += e + ((x - f) * c[b[k]]) / w[b[k]]; rq += double(((x - f) * c[b[k]]) % w[b[k]]) / w[b[k]]; } else solve(l, j, x); } int main() { srand(time(0)); scanf( %d%d%d , &m, &n, &W); for (i = 0; i < n; i++) { scanf( %I64d , &w[i]); b[i] = i; } for (i = 0; i < n; i++) scanf( %d , &c[i]); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (j = 0; j < m; j++) { if (j) for (i = 0; i < n; i++) c[i] -= a[i]; solve(0, n - 1, W); } rs += int(rq); rq -= int(rq); rq += rs % 10; rs /= 10; if (rs != 0) printf( %I64d , rs); printf( %.11lf n , rq); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_1_V
`define SKY130_FD_SC_HDLL__CLKMUX2_1_V
/**
* clkmux2: Clock mux.
*
* Verilog wrapper for clkmux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkmux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_1_V
|
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// ClockInvToBool.v
// 2010-02-05 ssiegel Creation
// 2010-02-06 ssiegel Flop added
//
module ClockInvToBool(
input CLK_SLOW,
input CLK_FAST,
output CLK_VAL);
FDRSE#(.INIT(1'b0)) FRDSE_inst (.Q(CLK_VAL), .C(CLK_FAST), .CE(1'b1), .D(CLK_SLOW), .R(1'b0), .S(1'b0));
// Without the flop, invert the slow clock
//wire CLK_VAL;
//assign CLK_VAL = !CLK_SLOW;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a[100005], b[100005], fa[100005], s[100005], q[100005], l, p = -2147483647; inline long long find(long long x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } inline long long M(long long u, long long v) { return u > v ? u : v; } int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &a[i]); for (long long i = 1; i <= n; i++) scanf( %lld , &b[i]); for (long long i = n; i >= 1; i--) { long long k = b[i]; if (!fa[k]) fa[k] = k, s[k] = a[k]; long long fk = find(k); if (fa[k - 1] && k - 1 > 0) { long long fl = find(k - 1); if (fk != fl) s[k] += s[fl], s[fl] = 0, fa[fl] = k; } if (fa[k + 1] && k + 1 <= n) { long long fr = find(k + 1); if (fk != fr) s[k] += s[fr], s[fr] = 0, fa[fr] = k; } p = M(p, s[k]), q[++l] = p; } for (long long i = n - 1; i >= 0; i--) printf( %lld n , q[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 1e5 + 5; int main() { int n, f[MaxN], cnt[MaxN], mm = 0, ans = 0; scanf( %d , &n); memset(f, 0, sizeof(f)); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) { int a; scanf( %d , &a); cnt[f[a]]--; f[a]++; cnt[f[a]]++; mm = max(mm, f[a]); bool flag = 0; if (cnt[1] == i) flag = 1; else if (cnt[i] == 1) flag = 1; else if (cnt[1] == 1 && cnt[mm] * mm == i - 1) flag = 1; else if (cnt[mm - 1] * (mm - 1) == i - mm && cnt[mm] == 1) flag = 1; if (flag == 1) ans = i; } printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:36 12/10/2012
// Design Name: top
// Module Name: C:/Documents and Settings/SPItoUART_Loopback/tb.v
// Project Name: SPItoUART_Loopback
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb;
// Inputs
reg rxd;
reg rst;
reg clk;
// Outputs
wire txd;
// Instantiate the Unit Under Test (UUT)
top uut (
.txd(txd),
.rxd(rxd),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
rxd = 0;
rst = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rxd = 1;
rst = 1;
#100;
rst = 0;
#10000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 0; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 0101
#100000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 1; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 1101
end
always begin
#20 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long infll = powl(2, 62) - 1; const long long mod = pow(10, 9) + 7; int64_t extGcd(int64_t a, int64_t b, int64_t& x, int64_t& y) { if (!a) { x = 0; y = 1; return b; } int64_t x1, y1; int64_t d = extGcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } inline long long addMod(long long a, long long b, long long m = mod) { return ((int64_t)a + b) % m; } inline long long mulMod(long long a, long long b, long long m = mod) { return ((int64_t)a * b) % m; } inline long long divMod(long long a, long long b, long long m = mod) { int64_t x, y; int64_t g = extGcd(b, m, x, y); if (g != 1) { cerr << Bad gcd! << endl; for (;;) ; } x = (x % m + m) % m; return mulMod(a, x, m); } const long long factRange = 1000000; long long fact[factRange]; inline void precalcFactorials() { fact[0] = 1; for (long long i = 1; i < factRange; i++) { fact[i] = mulMod(fact[i - 1], i); } } inline long long F(long long n) { return (n < 0) ? 0 : fact[n]; } inline long long C(long long n, long long k) { return divMod(F(n), mulMod(F(n - k), F(k))); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); precalcFactorials(); string bracket; cin >> bracket; vector<long long> open(bracket.size()), close(bracket.size()); long long count = 0; for (long long i = 0; i < (long long)(bracket.size()); ++i) { if (bracket[i] == ( ) count++; open[i] = count; } count = 0; for (long long i = (long long)(bracket.size()) - 1; i >= 0; --i) { if (bracket[i] == ) ) count++; close[i] = count; } long long ans = 0; for (long long i = 0; i < (long long)(bracket.size()); ++i) { if (bracket[i] != ( || close[i] == 0) continue; if (bracket[i] == ( ) { ans += C(open[i] + close[i] - 1, open[i]); ans %= mod; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const long long LLINF = 0x3f3f3f3f3f3f3f3f; using namespace std; class otr { public: long long len = 0; long long* D = nullptr; otr(long long alen) { len = alen; D = new long long[alen]; } ~otr() { delete[] D; } }; void Flip(long long* left, long long* right, long long flix, bool isleft) { while (flix != -1) { long long t = left[flix]; left[flix] = right[flix]; right[flix] = t; flix = isleft ? right[flix] : left[flix]; } } int main() { ios::sync_with_stdio(0); cin.tie(0); std::cout.tie(0); std::istream* istr = &cin; const long long mdl = 1000000007; long long q; (*istr) >> q; for (long long qi = 0; qi < q; qi++) { long long n, m, a, b, c; (*istr) >> n; otr** data = new otr*[n - 1]; for (long long i = 0; i < n - 1; i++) { (*istr) >> m; data[i] = new otr(m); for (long long j = 0; j < m; j++) (*istr) >> data[i]->D[j]; } for (long long i = 0; i < n - 2; i++) for (long long j = i + 1; j < n - 1; j++) if (data[i]->len > data[j]->len) { otr* t = data[i]; data[i] = data[j]; data[j] = t; } long long skippedcnt = 0; long long* left = new long long[n]; long long* right = new long long[n]; long long start = -1; long long end = -1; long long qend = -1; map<long long, bool> mp; long long ix = 0; bool* skip = new bool[n - 1]; while (ix < n - 1 && data[ix]->len == 2) { for (long long i = 0; i < n - 1; i++) skip[i] = false; skippedcnt = 0; for (long long i = 0; i < n; i++) { left[i] = -1; right[i] = -1; } mp.clear(); right[data[ix]->D[0] - 1] = data[ix]->D[1] - 1; left[data[ix]->D[1] - 1] = data[ix]->D[0] - 1; long long lastskippedcnt = skippedcnt; skip[ix] = true; skippedcnt++; mp[data[ix]->D[0] - 1] = true; mp[data[ix]->D[1] - 1] = true; start = data[ix]->D[0] - 1; end = data[ix]->D[1] - 1; qend = end; bool isq = true; bool isok = true; while (skippedcnt < n - 1) { long long iy = 0; lastskippedcnt = skippedcnt; while (iy < n - 1) { if (!skip[iy]) { bool startisthere = false; bool endisthere = false; long long newone = -1; long long newonecount = 0; for (long long i = 0; i < data[iy]->len; i++) { if (data[iy]->D[i] - 1 == start) startisthere = true; if (data[iy]->D[i] - 1 == qend) endisthere = true; if (mp.find(data[iy]->D[i] - 1) == mp.end()) { newone = data[iy]->D[i] - 1; newonecount++; } } if (newonecount > 1) { iy++; continue; } skip[iy] = true; skippedcnt++; if (startisthere && !endisthere) { Flip(left, right, qend, true); long long t = start; start = qend; qend = t; if (isq) end = t; if (left[start] >= 0) { left[left[start]] = qend; right[qend] = left[start]; left[start] = -1; } } left[newone] = end; right[end] = newone; end = newone; mp[newone] = true; if (isq && data[iy]->len == 2) qend = end; else isq = false; break; } iy++; } if (lastskippedcnt == skippedcnt) { isok = false; break; } } if (isok) break; ix++; } long long v = start; while (v >= 0) { cout << v + 1 << ; v = right[v]; } cout << endl; for (long long i = 0; i < n - 1; i++) delete data[i]; delete[] data; } }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module prot_eng_tx_tb();
localparam BASE = 128;
reg clk = 0;
reg rst = 1;
reg clear = 0;
initial #1000 rst = 0;
always #50 clk = ~clk;
reg [31:0] f36_data;
reg [1:0] f36_occ;
reg f36_sof, f36_eof;
wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
reg src_rdy_f36i = 0;
wire dst_rdy_f36i;
wire [35:0] casc_do;
wire src_rdy_f36o, dst_rdy_f36o;
wire [35:0] prot_out;
wire src_rdy_prot, dst_rdy_prot;
wire [35:0] realign_out;
wire src_rdy_realign;
reg dst_rdy_realign = 1;
reg [15:0] count;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
fifo_short #(.WIDTH(36)) fifo_cascade36
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
.dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o));
prot_eng_tx #(.BASE(BASE)) prot_eng_tx
(.clk(clk), .reset(rst), .clear(0),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.datain(casc_do),.src_rdy_i(src_rdy_f36o),.dst_rdy_o(dst_rdy_f36o),
.dataout(prot_out),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot));
ethtx_realign ethtx_realign
(.clk(clk), .reset(rst), .clear(0),
.datain(prot_out),.src_rdy_i(src_rdy_prot),.dst_rdy_o(dst_rdy_prot),
.dataout(realign_out),.src_rdy_o(src_rdy_realign),.dst_rdy_i(dst_rdy_realign));
reg [35:0] printer;
task WriteSREG;
input [7:0] addr;
input [31:0] data;
begin
@(posedge clk);
set_addr <= addr;
set_data <= data;
set_stb <= 1;
@(posedge clk);
set_stb <= 0;
end
endtask // WriteSREG
always @(posedge clk)
if(src_rdy_realign)
$display("Read: %h",realign_out);
task ReadFromFIFO36;
begin
$display("Read from FIFO36");
#1 dst_rdy_realign <= 1;
while(~src_rdy_prot)
@(posedge clk);
while(1)
begin
while(~src_rdy_prot)
@(posedge clk);
$display("Read: %h",realign_out);
@(posedge clk);
end
end
endtask // ReadFromFIFO36
task PutPacketInFIFO36;
input [31:0] data_start;
input [31:0] data_len;
begin
count <= 4;
src_rdy_f36i <= 1;
f36_data <= 32'h0001_000c;
f36_sof <= 1;
f36_eof <= 0;
f36_occ <= 0;
$display("Put Packet in FIFO36");
while(~dst_rdy_f36i)
@(posedge clk);
@(posedge clk);
$display("PPI_FIFO36: Entered First Line");
f36_sof <= 0;
f36_data <= data_start;
while(~dst_rdy_f36i)
@(posedge clk);
@(posedge clk);
while(count+4 < data_len)
begin
f36_data <= f36_data + 32'h01010101;
count <= count + 4;
while(~dst_rdy_f36i)
@(posedge clk);
@(posedge clk);
$display("PPI_FIFO36: Entered New Line");
end
f36_data <= f36_data + 32'h01010101;
f36_eof <= 1;
if(count + 4 == data_len)
f36_occ <= 0;
else if(count + 3 == data_len)
f36_occ <= 3;
else if(count + 2 == data_len)
f36_occ <= 2;
else
f36_occ <= 1;
while(~dst_rdy_f36i)
@(posedge clk);
@(posedge clk);
f36_occ <= 0;
f36_eof <= 0;
f36_data <= 0;
src_rdy_f36i <= 0;
$display("PPI_FIFO36: Entered Last Line");
end
endtask // PutPacketInFIFO36
initial $dumpfile("prot_eng_tx_tb.vcd");
initial $dumpvars(0,prot_eng_tx_tb);
initial
begin
#10000;
@(posedge clk);
//ReadFromFIFO36;
end
initial
begin
@(negedge rst);
@(posedge clk);
WriteSREG(BASE, 32'h89AB_CDEF);
WriteSREG(BASE+1, 32'h1111_2222);
WriteSREG(BASE+2, 32'h3333_4444);
WriteSREG(BASE+3, 32'h5555_6666);
WriteSREG(BASE+4, 32'h7777_8888);
WriteSREG(BASE+5, 32'h9999_aaaa);
WriteSREG(BASE+6, 32'hbbbb_cccc);
WriteSREG(BASE+7, 32'hdddd_eeee);
WriteSREG(BASE+8, 32'h0f0f_0011);
WriteSREG(BASE+9, 32'h0022_0033);
WriteSREG(BASE+10, 32'h0044_0055);
WriteSREG(BASE+11, 32'h0066_0077);
WriteSREG(BASE+12, 32'h0088_0099);
@(posedge clk);
PutPacketInFIFO36(32'hA0B0C0D0,16);
@(posedge clk);
@(posedge clk);
#10000;
@(posedge clk);
//PutPacketInFIFO36(32'hE0F0A0B0,36);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
initial #20000 $finish;
endmodule // prot_eng_tx_tb
|
#include <bits/stdc++.h> using namespace std; int n, m; long long a[200000], b[200000]; bool ok(long long x) { int p(1); long long q(0); for (int i = 1; i <= (m); ++i) if (b[i] > q) { while (p <= n && a[p] + x < b[i]) ++p; if (a[p] - x > b[i] || p > n) return false; if (a[p] <= b[i]) q = a[p] + x; else q = max(b[i] + x - (a[p] - b[i]), a[p] + (x - (a[p] - b[i])) / 2); ++p; } return true; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= (n); ++i) scanf( %I64d , &a[i]); for (int i = 1; i <= (m); ++i) scanf( %I64d , &b[i]); long long L = -1, R = 1LL << 40; while (L + 1 < R) (ok(L + R >> 1) ? R : L) = L + R >> 1; printf( %I64d n , R); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { bool flag = false; int n, boro; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i] >> b[i]; for (int i = 0; i < 1; i++) { boro = max(a[i], b[i]); } for (int i = 1; i < n; i++) { if (max(a[i], b[i]) <= boro) { boro = max(a[i], b[i]); } else if (min(a[i], b[i]) <= boro) { boro = min(a[i], b[i]); } else { flag = true; break; } } if (flag == false) cout << YES n ; else cout << NO n ; return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_gemac
(input clk125, input reset,
// GMII
output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
// Flow Control Interface
input pause_req, input [15:0] pause_time_req, input pause_respect_en,
// Settings
input [47:0] ucast_addr, input [47:0] mcast_addr,
input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
// RX Client Interface
output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack,
// TX Client Interface
output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
output [31:0] debug
);
localparam SGE_IFG = 8'd12; // 12 should be the absolute minimum
wire rst_rxclk, rst_txclk;
reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
wire [15:0] pause_quanta_rcvd;
wire pause_rcvd, pause_apply, paused;
simple_gemac_tx simple_gemac_tx
(.clk125(clk125),.reset(rst_txclk),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
.ifg(SGE_IFG), .mac_addr(ucast_addr),
.pause_req(pause_req), .pause_time(pause_time_req), // We request flow control
.pause_apply(pause_apply), .paused(paused) // We respect flow control
);
simple_gemac_rx simple_gemac_rx
(.reset(rst_rxclk),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
.ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
.pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
.pass_pause(pass_pause), .pass_all(pass_all),
.pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd),
.debug(debug)
);
flow_ctrl_tx flow_ctrl_tx
(.rst(rst_txclk), .tx_clk(tx_clk),
.tx_pause_en(pause_respect_en),
.pause_quanta(pause_quanta_rcvd), // 16 bit value
.pause_quanta_val(pause_rcvd),
.pause_apply(pause_apply),
.paused(paused)
);
endmodule // simple_gemac
|
#include <bits/stdc++.h> using namespace std; int main() { long long int s, x; cin >> s >> x; long long int i, c = 1, f = 0; long long int a = (s - x) / 2; if ((s - x) % 2 != 0) cout << 0; else { for (i = 0; i < 64; i++) { long long int x1 = ((x >> i) & 1); long long int a1 = ((a >> i) & 1); if (x1 == 0 && a1 == 1) f = 1; if (x1 == 1 && a1 == 0) c = c * 2; if (x1 == 1 && a1 == 1) { f = 1; c = 0; } } if (f == 1) cout << c; else cout << (c - 2); } }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } inline int sbt(int x) { return __builtin_popcount(x); } inline long long gl(long long a, long long b) { return (b - a + 1); } inline long long mul(long long a, long long b, long long m = (long long)(1e9 + 7)) { return ((a % m) * (b % m)) % m; } inline long long add(long long a, long long b, long long m = (long long)(1e9 + 7)) { return (a + b) % m; } inline long long sub(long long a, long long b, long long m = (long long)(1e9 + 7)) { return (a - b + m) % m; } long long fastpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = mul(res, a); a = mul(a, a); b >>= 1; } return res; } long long modinv(long long a) { return fastpow(a, (long long)(1e9 + 7) - 2); } void get_ac() { long long n, k; cin >> n >> k; string s; cin >> s; vector<vector<long long>> v; bool f; long long mink = 0, maxk = 0; while (1) { f = 0; vector<long long> va; for (int i = 0; i < n - 1; i++) { if (s[i] == R && s[i + 1] == L ) { swap(s[i], s[i + 1]); f = 1; va.push_back(i); i++; } } if (!f) break; v.push_back(va); maxk += (long long)(va.size()); mink++; } if (k < mink || k > maxk) { cout << -1; return; } long long i = 0, j = 0; while (k > mink - i) { cout << 1 << << v[i][j] + 1; cout << n ; j++; if (j == (long long)(v[i].size())) { i++; j = 0; } k--; } for (int l = i; l < mink; l++) { cout << ((long long)(v[l].size()) - j) << ; for (int m = j; m < (long long)(v[l].size()); m++) { cout << v[l][m] + 1 << ; } j = 0; cout << n ; } } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin.tie(NULL); { get_ac(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } void solve() { int n, m; cin >> n >> m; map<vector<int>, int> tiles; for (int i = 0; i < n; i++) { vector<int> temp; for (int j = 0; j < 4; j++) { int a; cin >> a; temp.push_back(a); } tiles[temp]++; } if (m & 1) { cout << NO n ; return; } for (auto &i : tiles) { if (i.first[1] == i.first[2]) { cout << YES n ; return; } } cout << NO n ; } int main() { fast(); int t; cin >> t; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_SYMBOL_V
`define SKY130_FD_SC_HD__O32AI_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o32ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_SYMBOL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { long long r, x1, y1, x2, y2; while (cin >> r >> x1 >> y1 >> x2 >> y2) { double dis = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2) + 0.0); cout << ceil(dis / 2 / r) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace io { const int SI = 1 << 21 | 1; char IB[SI], *IS, *IT, OB[SI], *OS = OB, *OT = OS + SI - 1, c, ch[100]; int f, t; inline void flush() { fwrite(OB, 1, OS - OB, stdout), OS = OB; } inline void pc(char x) { *OS++ = x; if (OS == OT) flush(); } template <class I> inline void rd(I &x) { for (f = 1, c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++); c < 0 || c > 9 ; c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++)) if (c == - ) f = -1; for (x = 0; c >= 0 && c <= 9 ; x = (x << 3) + (x << 1) + (c & 15), c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++)) ; x *= f; } inline void rds(char *s, int &x) { for (c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++); c < 33 || c > 126; c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++)) ; for (x = 0; c >= 33 && c <= 126; s[++x] = c, c = (IS == IT ? (IT = (IS = IB) + fread(IB, 1, SI, stdin), IS == IT ? EOF : *IS++) : *IS++)) ; s[x + 1] = 0 ; } template <class I> inline void print(I x, char k = n ) { if (!x) pc( 0 ); if (x < 0) pc( - ), x = -x; while (x) ch[++t] = x % 10 + 0 , x /= 10; while (t) pc(ch[t--]); pc(k); } inline void prints(string s) { int x = s.length(); while (t < x) pc(s[t++]); pc( n ), t = 0; } struct Flush { ~Flush() { flush(); } } flusher; } // namespace io using io::print; using io::prints; using io::rd; using io::rds; const int N = 3e5 + 7; int n, a[N], sx[N], tx, sn[N], tn; map<int, int> p; struct T { int l, r, x, c, z; } t[N << 2]; long long ans; void build(int p, int l, int r) { t[p].l = l, t[p].r = r, t[p].c = r - l + 1; if (l == r) return; build((p << 1), l, ((t[p].l + t[p].r) >> 1)), build(((p << 1) | 1), ((t[p].l + t[p].r) >> 1) + 1, r); } inline void add(int p, int x) { t[p].x += x, t[p].z += x; } void upd(int p, int l, int r, int x) { if (t[p].l >= l && t[p].r <= r) return add(p, x); if (t[p].z) add((p << 1), t[p].z), add(((p << 1) | 1), t[p].z), t[p].z = 0; if (l <= ((t[p].l + t[p].r) >> 1)) upd((p << 1), l, r, x); if (r > ((t[p].l + t[p].r) >> 1)) upd(((p << 1) | 1), l, r, x); t[p].x = min(t[(p << 1)].x, t[((p << 1) | 1)].x); t[p].c = (t[(p << 1)].x == t[p].x ? t[(p << 1)].c : 0) + (t[((p << 1) | 1)].x == t[p].x ? t[((p << 1) | 1)].c : 0); } int main() { rd(n); for (int i = 1, x, y; i <= n; i++) rd(x), rd(y), a[x] = y; build(1, 1, n); for (int i = 1; i <= n; i++) { while (tx && a[sx[tx]] < a[i]) upd(1, sx[tx - 1] + 1, sx[tx], -a[sx[tx]]), --tx; while (tn && a[sn[tn]] > a[i]) upd(1, sn[tn - 1] + 1, sn[tn], a[sn[tn]]), --tn; upd(1, p[a[i]] + 1, i, -1), p[a[i]] = sx[++tx] = sn[++tn] = i; upd(1, sx[tx - 1] + 1, i, a[i]), upd(1, sn[tn - 1] + 1, i, -a[i]); ans += t[1].c; } print(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, x, y; cin >> n >> x >> y; long long int maxi = x + y - 2 + 1; maxi = min(maxi, n); long long int mini = x + y - n; if (mini <= 0) mini = 1; else mini++; mini = min(mini, n); cout << mini << << maxi << endl; } }
|
module adv3224 (
// avalon-bus
input clk,
input reset,
input avs_slave_write,
input avs_slave_read,
input [7:0]avs_slave_writedata,
output [7:0]avs_slave_readdata,
input [2:0]avs_slave_address,
// adv3224
output cps_reset_n,
output cps_ce_n,
output cps_update_n,
output cps_clk,
output cps_datain
);
//
// parameters
//
parameter divider = 5;
//
// regs / wires
//
reg [8:0]clk_counter;
reg div_clk;
reg clk_en;
reg [39:0]shift_buffer;
reg shift_busy;
reg [5:0]shift_counter;
reg [4:0]outputs[0:7];
//
// ip
//
assign cps_reset_n = !reset;
assign cps_ce_n = 0;
assign avs_slave_readdata = shift_busy;
assign cps_clk = clk_en ? div_clk : 1'b1;
assign cps_update_n = (!clk_en && shift_busy) ? !div_clk : 1'b1;
assign cps_datain = shift_buffer[39];
always @(posedge clk or posedge reset)
begin
if(reset)
begin
clk_counter <= 1;
div_clk <= 1;
clk_en <= 0;
shift_busy <= 0;
shift_counter <= 0;
outputs[0] <= 5'b00000;
outputs[1] <= 5'b00000;
outputs[2] <= 5'b00000;
outputs[3] <= 5'b00000;
outputs[4] <= 5'b00000;
outputs[5] <= 5'b00000;
outputs[6] <= 5'b00000;
outputs[7] <= 5'b00000;
end
else
begin // posedge clk
if(shift_busy)
begin
if(clk_counter == (divider/2))
begin
clk_counter <= 1;
div_clk <= !div_clk;
if(!div_clk)
begin
if(!clk_en)
begin
shift_busy <= 0;
end
else
begin
if(shift_counter == 39)
begin
clk_en <= 0;
end
else
begin
shift_counter <= shift_counter + 6'd1;
shift_buffer <= shift_buffer << 1;
end
end
end
end
else
begin
clk_counter = clk_counter + 9'd1;
end
end
else
begin
clk_counter <= 1;
shift_counter <= 0;
div_clk <= 1;
if(avs_slave_write)
begin
if(avs_slave_writedata[7])
begin
shift_buffer <= {outputs[7], outputs[6], outputs[5], outputs[4], outputs[3], outputs[2], outputs[1], outputs[0]};
shift_busy <= 1;
clk_en <= 1;
end
else
begin
outputs[avs_slave_address] <= {!avs_slave_writedata[4], avs_slave_writedata[3:0]};
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 1) { cout << 1 1 << endl << 1 ; return 0; } cout << 5 * (n - 1) << << 2 << endl << 1 5 ; }
|
/*
* NAME
* ----
*
* main.v - SPI slave, switch input, LED display
*
* DESCRIPTION
* -----------
*
* This module takes input from input switches (in_sw) and
* outputs them over the SPI (MISO pin).
* And the input it receives over the SPI is written to the
* external LEDs (led_ext).
*
* The following SPI settings used by this module:
*
* MSB first
* CPOL = 0
* CPHA = 0
* SS_L (enable on low)
*
* The slave select line (SS_L) is used in a somewhat unique way.
* On the cleared (enabled) to set (disabled) transition the
* new data is latched in to the register.
* This was done because in the other orientation it was impossible
* to determine when to initialize the data because ss_l was
* the same value when it is sampling/propagating.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <>
*
*/
module main(
input wire rst_l,
input wire ss_l,
input wire sclk,
input wire mosi,
output wire miso,
output wire [7:0] led_ext,
input wire [7:0] in_sw
);
GSR GSR_INST(.GSR(rst_l));
// N is the last offset of data that is transferred.
// Currently there are 8-bits (0 - 7).
// This could be changed to support 16 bits
// needed.
parameter N=7;
// provide user feedback for switch actuation
wire [N:0] n_in_sw; // negated version of in_sw, sw closed -> set
assign n_in_sw = ~(in_sw);
// read register and next read register
reg [N:0] r_reg;
wire [N:0] r_next;
// write register, for storing received data
reg [N:0] w_reg;
// store the received data on the external led's
assign led_ext = ~(w_reg); // invert so 0 -> off, 1 -> on
// ### main SPI control: sample, propagate ###
assign r_next = {r_reg[N-1:0], mosi_sample};
assign miso = r_reg[N] & ~(ss_l);
// SAMPLE
reg mosi_sample;
always @(posedge sclk) begin
mosi_sample <= mosi;
end
always @(negedge sclk or negedge rst_l) begin
if (~rst_l) begin
r_reg <= 8'b0;
w_reg <= 8'b0;
end else begin
if (ss_l) begin
// RESET
// reset when sclk falls while ss_l is high (disabled)
r_reg <= n_in_sw; // switch input
w_reg <= r_next; // update the write register with the last read
// use r_next (not r_reg) so we don't miss the last mosi (SAMPLE)
end else begin
// PROPAGATE
r_reg <= r_next;
//w_reg <= w_reg;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a, b, c, d, e; cin >> a >> b >> c >> d >> e; int f[5] = {a, b, c, d, e}, mn = a + b + c + d + e, ans = a + b + c + d + e; sort(f, f + 5); map<int, int> mp; for (int i = 0; i < 5; i++) { mp[f[i]]++; if (mp[f[i]] == 2) ans = min(ans, mn - f[i] * 2); else if (mp[f[i]] == 3) ans = min(ans, mn - f[i] * 3); } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probec_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
|
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