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module lc3_pipeline_stage2(
input reset,
input clk,
input stall,
input [5:0] state,
input [15:0] I_npc,
input [19:0] I_SR1,
input [19:0] I_SR2,
input [19:0] I_DR,
input [1:0] I_WBtype,
input [1:0] I_ALUopr,
input I_SetCC,
input [4:0] I_BRtype,
input [15:0] I_Forcast_pc,
input [2:0] I_Memtype,
input [1:0] I_Errtype,
output reg [19:0] O_DR,
output [1:0] O_WBtype,
output [2:0] O_Memtype,
output [15:0] O_aluout,
input [15:0] PSR,
output reg SetCC,
output NeedCC,
output reg [2:0] CC,
output reg [1:0] Errtype,
output reg [15:0] Checked_pc,
output reg Forcast_fail,
output reg [15:0] IntINTvec,
output [19:0] sr1,
output [19:0] sr2,
input [19:0] dr3,
input [19:0] dr4,
input [19:0] dr5
);
reg [15:0] NUMA,NUMB;
LC3_ALU alu0(
.NUMA(NUMA),
.NUMB(NUMB),
.ALUK(ALUopr),
.ALUout(O_aluout)
);
reg [19:0] SR1;
reg [19:0] SR2;
assign sr1=SR1;
assign sr2=SR2;
reg [19:0] DR;
reg [1:0] WBtype;
reg [1:0] ALUopr;
reg [4:0] BRtype;
reg [15:0] Forcast_pc;
reg [2:0] Memtype;
assign O_Memtype=Memtype;
assign O_WBtype=WBtype;
always@(negedge clk or posedge reset) begin
if(reset) begin
//seems nothing to do
end else begin
if(~stall) begin
SR1<=I_SR1;
SR2<=I_SR2;
DR <=I_DR;
WBtype<=I_WBtype;
ALUopr<=I_ALUopr;
SetCC <=I_SetCC;
BRtype<=I_BRtype;
Forcast_pc<=I_Forcast_pc;
Memtype<=I_Memtype;
Errtype<=I_Errtype;
end else begin
DR <=O_DR;
SR1[15:0]<=NUMA;
SR2[15:0]<=NUMB;
end
end
end
/*branch detect*/
always@(*) begin
case (BRtype[4:3])
2'b00:
{Forcast_fail,Checked_pc}={1'b0,Forcast_pc};
2'b01:
{Forcast_fail,Checked_pc}={state[2]&~stall&( (BRtype[2:0]&PSR[2:0])!=3'b000 )& (O_aluout!=Forcast_pc),Forcast_fail?O_aluout:Forcast_pc};
2'b10:
{Forcast_fail,Checked_pc}={state[2]&~stall&(O_aluout!=Forcast_pc),O_aluout};
2'b11:
{Forcast_fail,Checked_pc}={1'b0,Forcast_pc};
endcase
end
/*TODO data forward*/
assign NeedCC=(BRtype[4:3]==2'b01);
always@(*) begin
if(state[3]&dr3[19]&SR1[19]&(SR1[18:16]==dr3[18:16]))
NUMA=dr3[15:0];
else if(state[4]&dr4[19]&SR1[19]&(SR1[18:16]==dr4[18:16]))
NUMA=dr4[15:0];
else if(state[5]&dr5[19]&SR1[19]&(SR1[18:16]==dr5[18:16]))
NUMA=dr5[15:0];
else
NUMA=SR1[15:0];
end
always@(*) begin
if(state[3]&dr3[19]&SR2[19]&(SR2[18:16]==dr3[18:16]))
NUMB=dr3[15:0];
else if(state[4]&dr4[19]&SR2[19]&(SR2[18:16]==dr4[18:16]))
NUMB=dr4[15:0];
else if(state[5]&dr5[19]&SR2[19]&(SR2[18:16]==dr5[18:16]))
NUMB=dr5[15:0];
else
NUMB=SR2[15:0];
end
always@(*) begin
if(state[3]&dr3[19]&DR[19]&(DR[18:16]==dr3[18:16]))
O_DR={DR[19:16],dr3[15:0]};
else if(state[4]&dr4[19]&DR[19]&(DR[18:16]==dr4[18:16]))
O_DR={DR[19:16],dr4[15:0]};
else if(state[5]&dr5[19]&DR[19]&(DR[18:16]==dr5[18:16]))
O_DR={DR[19:16],dr5[15:0]};
else if(~WBtype[1]|WBtype[0])
O_DR={DR[19:0]};
else
O_DR={DR[19:16],O_aluout};
end
always@(*) begin
if(O_aluout==16'b0)
CC=3'b010;
else if(O_aluout[15]==1)
CC=3'b100;
else
CC=3'b001;
end
always@(*) begin
case(Errtype)
2'b00:
IntINTvec=16'bx;
2'b01:
IntINTvec=O_aluout;
2'b10:
IntINTvec=16'h0044;
2'b11:
IntINTvec=16'h0044;
endcase
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Wed Apr 30 22:30:36 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_stub.v
// Design : clk_adc
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_adc(clk_in1_p, clk_in1_n, clk_250Mhz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1_p,clk_in1_n,clk_250Mhz,locked" */;
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
endmodule
|
#include <bits/stdc++.h> int n, m, i, ans; int main() { scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &m), ans += (i + 1) * m; printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A41O_BEHAVIORAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m, k; cin >> n >> m >> k; long long p[m]; for (long long int i = 0; i < m; i++) cin >> p[i]; sort(p, p + m); long long an = 0, x = 0, c = 0, cp = 1; while (1) { long long y = x, pg = ceil((long double)(p[x] - x) / (k)); while (y < m && ceil((long double)(p[y] - x) / (k)) == pg) y++; if (y == m) { cout << an + 1; return; } an++; x = y; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long TESTS = 1; while (TESTS--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > g[100100]; int fa[100100][18], typ[100100], n; int sum[100100][2], dep[100100]; void dfs(int u) { for (int i = 1; i < 18; ++i) fa[u][i] = fa[fa[u][i - 1]][i - 1]; for (auto v : g[u]) { int A = v.first, tp = v.second; sum[A][0] = sum[u][0]; sum[A][1] = sum[u][1]; ++sum[A][tp]; dep[A] = dep[u] + 1; dfs(A); } } int LCA(int u, int v) { if (dep[u] > dep[v]) swap(u, v); int hu = dep[u], hv = dep[v]; int tu = u, tv = v; for (int det = hv - hu, i = 0; det; det >>= 1, i++) if (det & 1) tv = fa[tv][i]; if (tu == tv) return tu; for (int i = 17; i >= 0; --i) { if (fa[tu][i] == fa[tv][i]) continue; tu = fa[tu][i]; tv = fa[tv][i]; } return fa[tu][0]; } int tmp[2]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &fa[i][0], &typ[i]); if (fa[i][0] == -1) fa[i][0] = typ[i] = 0; } for (int i = 1; i <= n; ++i) g[fa[i][0]].push_back(pair<int, int>(i, typ[i])); dfs(0); int q; scanf( %d , &q); while (q--) { int tp, u, v; scanf( %d%d%d , &tp, &u, &v); int lca = LCA(u, v); if (!lca || lca == v) { puts( NO ); continue; } if (tp == 1) { if (lca != u) { puts( NO ); continue; } tmp[0] = sum[v][0] - sum[u][0]; tmp[1] = sum[v][1] - sum[u][1]; if (tmp[1]) { puts( NO ); continue; } puts( YES ); } else { tmp[0] = sum[u][0] - sum[lca][0]; tmp[1] = sum[u][1] - sum[lca][1]; if (tmp[1]) { puts( NO ); continue; } tmp[0] = sum[v][0] - sum[lca][0]; tmp[1] = sum[v][1] - sum[lca][1]; if (tmp[0]) { puts( NO ); continue; } puts( YES ); } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg rst;
// Two phases, random so nothing optimizes away, and focused so get hits
logic inval;
wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]});
wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]});
wire wdat_val = 1'b1;
wire camen = crc[32];
wire ren = crc[33];
wire wen = crc[34];
wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]});
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic hit_d2r; // From cam of cam.v
logic [7:0] hitidx_d1r; // From cam of cam.v
logic [255:0] hitvec_d1r; // From cam of cam.v
logic [30:0] rdat_d2r; // From cam of cam.v
logic rdat_val_d2r; // From cam of cam.v
// End of automatics
cam cam (/*AUTOINST*/
// Outputs
.hitvec_d1r (hitvec_d1r[255:0]),
.hitidx_d1r (hitidx_d1r[7:0]),
.hit_d2r (hit_d2r),
.rdat_d2r (rdat_d2r[30:0]),
.rdat_val_d2r (rdat_val_d2r),
// Inputs
.clk (clk),
.rst (rst),
.camen (camen),
.inval (inval),
.cdat (cdat[30:0]),
.ren (ren),
.wen (wen),
.wdat (wdat[30:0]),
.wdat_val (wdat_val),
.rwidx (rwidx[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
rst <= 1'b1;
end
else if (cyc<10) begin
sum <= '0;
rst <= 1'b0;
end
else if (cyc==70) begin
inval <= 1'b1;
end
else if (cyc==71) begin
inval <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h5182640870b07199
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module cam
(
input clk,
input rst,
input camen,
input inval,
input [30:0] cdat,
output logic [255:0] hitvec_d1r,
output logic [7:0] hitidx_d1r,
output logic hit_d2r,
input ren,
input wen,
input [30:0] wdat,
input wdat_val,
input [7:0] rwidx,
output logic [30:0] rdat_d2r,
output logic rdat_val_d2r
);
logic camen_d1r;
logic inval_d1r;
logic ren_d1r;
logic wen_d1r;
logic [7:0] rwidx_d1r;
logic [30:0] cdat_d1r;
logic [30:0] wdat_d1r;
logic wdat_val_d1r;
always_ff @(posedge clk) begin
camen_d1r <= camen;
inval_d1r <= inval;
ren_d1r <= ren;
wen_d1r <= wen;
cdat_d1r <= cdat;
rwidx_d1r <= rwidx;
wdat_d1r <= wdat;
wdat_val_d1r <= wdat_val;
end
typedef struct packed {
logic [30:0] data;
logic valid;
} entry_t;
entry_t [255:0] entries;
always_ff @(posedge clk) begin
if (camen_d1r) begin
for (int i = 0; i < 256; i = i + 1) begin
hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r);
end
end
end
always_ff @(posedge clk) begin
hit_d2r <= | hitvec_d1r;
end
always_ff @(posedge clk) begin
if (rst) begin
for (int i = 0; i < 256; i = i + 1) begin
entries[i] <= '0;
end
end
else if (wen_d1r) begin
entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r};
end
else if (inval_d1r) begin
for (int i = 0; i < 256; i = i + 1) begin
entries[i] <= '{valid:'0, data:entries[i].data};
end
end
end
always_ff @(posedge clk) begin
if (ren_d1r) begin
rdat_d2r <= entries[rwidx_d1r].data;
rdat_val_d2r <= entries[rwidx_d1r].valid;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_4_V
`define SKY130_FD_SC_HD__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int p[N], a[N], idx, pre[N]; void xxs() { int kns = 0; for (int i = 2; i <= N; i++) { if (!a[i]) { p[++idx] = i; kns++; } for (int j = 1; j <= idx && i * p[j] <= N; j++) { a[i * p[j]] = 1; if (i % p[j] == 0) break; } pre[i] = kns; } } int main() { xxs(); int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); int k = sqrt(n); printf( %d n , pre[n] - pre[k] + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool is_prime[100000]; void gen_is_primes(int n); void gen_prime_groups(int n, vector<bool>& to_match, list<int>& candidate_primes, list<pair<int, int> >& groups); void gen_prime_groups(int n, int p, vector<bool>& to_match, list<pair<int, int> >& groups); void gen_unmatched_multiples(int n, int i, vector<bool>& to_match, list<int>& unmatched_multiples); void gen_even_groups(vector<bool>& to_match, list<pair<int, int> >& groups); void gen_is_primes(int n) { fill_n(is_prime, n, true); is_prime[0] = false; is_prime[1] = false; for (int i = 2; i <= n / 2; i++) { if (is_prime[i]) { for (int j = 2 * i; j <= n; j += i) { is_prime[j] = false; } } } } void gen_prime_groups(int n, vector<bool>& to_match, list<int>& candidate_primes, list<pair<int, int> >& groups) { for (list<int>::iterator i = candidate_primes.begin(); i != candidate_primes.end(); i++) { gen_prime_groups(n, *i, to_match, groups); } } void gen_prime_groups(int n, int p, vector<bool>& to_match, list<pair<int, int> >& groups) { list<int>* unmatched_multiples = new list<int>(); gen_unmatched_multiples(n, p, to_match, *unmatched_multiples); for (list<int>::iterator it = unmatched_multiples->begin(); it != unmatched_multiples->end(); it++) { int curr = *it; int curr_partner = *(++it); to_match[curr] = false; to_match[curr_partner] = false; groups.push_back(make_pair(curr, curr_partner)); } delete unmatched_multiples; } void gen_unmatched_multiples(int n, int i, vector<bool>& to_match, list<int>& unmatched_multiples) { for (int curr_multiple = i; curr_multiple <= n; curr_multiple += i) { if (to_match[curr_multiple]) { unmatched_multiples.push_back(curr_multiple); } } if (unmatched_multiples.size() % 2 != 0) { unmatched_multiples.remove(2 * i); } } void gen_even_groups(vector<bool>& to_match, list<pair<int, int> >& groups) { list<int> unmatched; for (vector<bool>::iterator i = to_match.begin(); i != to_match.end(); i++) { if (*i) { int i_index = i - to_match.begin(); unmatched.push_back(i_index); } } if (unmatched.size() % 2 != 0) { unmatched.erase(unmatched.begin()); } for (list<int>::iterator i = unmatched.begin(); i != unmatched.end(); i++) { int curr = *i; int curr_partner = *(++i); groups.push_back(make_pair(curr, curr_partner)); } } int main() { int n; cin >> n; gen_is_primes(n); vector<bool> to_match(n, false); for (int i = 2; i <= n; i++) { to_match[i] = !is_prime[i] || (i <= n / 2); } list<int>* candidate_primes = new list<int>; for (int i = n / 2; i >= 3; i--) { if (is_prime[i]) { candidate_primes->push_back(i); } } list<pair<int, int> >* groups = new list<pair<int, int> >; gen_prime_groups(n, to_match, *candidate_primes, *groups); gen_even_groups(to_match, *groups); cout << groups->size() << endl; for (list<pair<int, int> >::iterator it = groups->begin(); it != groups->end(); it++) { cout << it->first << << it->second << endl; } delete groups; return 0; }
|
module top(
input PACKAGEPIN,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
.PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCORE (PLLOUTCORE ),
.PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int int_inf = 0x7fffffff; const long long ll_inf = ~(1ll << 63); const double eps = 1e-7; char *p1, *p2, buf[1 << 20]; inline int read() { int f = 1, x = 0; char ch; while (!isdigit( ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 20, stdin), p1 == p2) ? EOF : *p1++))) if (ch == - ) f = -1; x = ch - 0 ; while (isdigit( ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 20, stdin), p1 == p2) ? EOF : *p1++))) x = x * 10 + ch - 0 ; return x * f; } const int N = 1e6 + 10; unordered_map<long long, int> m; long long sa[N], sb[N]; int a[N], b[N], s[N], n; int main() { n = read(); for (int i = 1; i <= n; i++) a[i] = read(), sa[i] = sa[i - 1] + a[i]; for (int i = 1; i <= n; i++) b[i] = read(), sb[i] = sb[i - 1] + b[i]; m[0] = 0; for (int i = 1; i <= n; i++) { int p = s[i - 1]; while (sb[p] <= sa[i] && p <= n) p++; s[i] = p - 1; long long delt = sa[i] - sb[p - 1]; if (m.count(delt)) { int x = m[delt]; cout << (i - x) << endl; for (int j = x + 1; j <= i; j++) cout << j << ; cout << endl; cout << (s[i] - s[x]) << endl; for (int j = s[x] + 1; j <= s[i]; j++) cout << j << ; return 0; } m[delt] = i; } cout << -1; return 0; }
|
/**
* bsg_cache_to_test_dram_rx.v
*
*/
`include "bsg_defines.v"
module bsg_cache_to_test_dram_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter `BSG_INV_PARAM(dram_channel_addr_width_p)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
)
(
input core_clk_i
, input core_reset_i
, output logic [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input dram_clk_i
, input dram_reset_i
, input dram_data_v_i
, input [dram_data_width_p-1:0] dram_data_i
, input [dram_channel_addr_width_p-1:0] dram_ch_addr_i
);
// ch_addr CDC
//
logic ch_addr_afifo_full;
logic ch_addr_afifo_deq;
logic [dram_channel_addr_width_p-1:0] ch_addr_lo;
logic ch_addr_v_lo;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4)))
,.width_p(dram_channel_addr_width_p)
) ch_addr_afifo (
.w_clk_i(dram_clk_i)
,.w_reset_i(dram_reset_i)
,.w_enq_i(dram_data_v_i)
,.w_data_i(dram_ch_addr_i)
,.w_full_o(ch_addr_afifo_full)
,.r_clk_i(core_clk_i)
,.r_reset_i(core_reset_i)
,.r_deq_i(ch_addr_afifo_deq)
,.r_data_o(ch_addr_lo)
,.r_valid_o(ch_addr_v_lo)
);
// data CDC
//
logic data_afifo_full;
logic data_afifo_deq;
logic [dram_data_width_p-1:0] dram_data_lo;
logic dram_data_v_lo;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4)))
,.width_p(dram_data_width_p)
) data_afifo (
.w_clk_i(dram_clk_i)
,.w_reset_i(dram_reset_i)
,.w_enq_i(dram_data_v_i)
,.w_data_i(dram_data_i)
,.w_full_o(data_afifo_full)
,.r_clk_i(core_clk_i)
,.r_reset_i(core_reset_i)
,.r_deq_i(data_afifo_deq)
,.r_data_o(dram_data_lo)
,.r_valid_o(dram_data_v_lo)
);
// reorder buffer
//
logic [num_cache_p-1:0] reorder_v_li;
for (genvar i = 0; i < num_cache_p; i++) begin: re
bsg_cache_to_test_dram_rx_reorder #(
.data_width_p(data_width_p)
,.dma_data_width_p(dma_data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_data_width_p(dram_data_width_p)
,.dram_channel_addr_width_p(dram_channel_addr_width_p)
) reorder0 (
.core_clk_i(core_clk_i)
,.core_reset_i(core_reset_i)
,.dram_v_i(reorder_v_li[i])
,.dram_data_i(dram_data_lo)
,.dram_ch_addr_i(ch_addr_lo)
,.dma_data_o(dma_data_o[i])
,.dma_data_v_o(dma_data_v_o[i])
,.dma_data_ready_i(dma_data_ready_i[i])
);
end
// using the ch address, forward the data to the correct cache.
logic [lg_num_cache_lp-1:0] cache_id;
if (num_cache_p == 1) begin
assign cache_id = 1'b0;
end
else begin
assign cache_id = ch_addr_lo[dram_channel_addr_width_p-1-:lg_num_cache_lp];
end
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux0 (
.i(cache_id)
,.v_i(ch_addr_v_lo & dram_data_v_lo)
,.o(reorder_v_li)
);
assign data_afifo_deq = ch_addr_v_lo & dram_data_v_lo;
assign ch_addr_afifo_deq = ch_addr_v_lo & dram_data_v_lo;
// synopsys translate_off
always_ff @ (negedge dram_clk_i) begin
if (~dram_reset_i & dram_data_v_i) begin
assert(~data_afifo_full) else $fatal("data async_fifo full!");
assert(~ch_addr_afifo_full) else $fatal("ch_addr async_fifo full!");
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_rx)
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, a, b, dp[200005][2]; cin >> n >> a >> b; string t; cin >> t; memset(dp, 0x3f, sizeof(dp)); dp[0][0] = b; for (int i = 0; i < n; i++) { if (t[i] == 1 ) dp[i + 1][1] = dp[i][1] + a + 2 * b; else { dp[i + 1][0] = min(dp[i][0] + a + b, dp[i][1] + 2 * a + b); dp[i + 1][1] = min(dp[i][0] + 2 * (a + b), dp[i][1] + a + 2 * b); } } cout << dp[n][0] << endl; } int main() { int t; scanf( %d , &t); while (t--) solve(); return 0; }
|
/*
Title: RCFilter
Filters a single bit using a counter with optional hysteresis. The counter
increments when bitIn is high and decrements when it is low. bitOut is set when
bits FILT_WIDTH-1:HYST_BIT of the counter are all high, and clears when they are
all low. To remove hysteresis, just set HYST_BIT to equal FILT_WIDTH-1.
Parameters:
input clk - System Clock
input rst - Reset, active high synchronous
input en - Sample filter input when high
input bitIn - Filter input
output bitOut - Filter output
*/
module RCFilter #(
parameter FILT_WIDTH = 8,
parameter HYST_BIT = 5
)
(
input clk, // System Clock
input rst, // Reset, active high synchronous
input en, // Sample filter input when high
input bitIn, // Filter input
output reg bitOut // Filter output
);
reg [FILT_WIDTH-1:0] counter;
initial begin
counter <= 'd0;
bitOut <= 1'b0;
end
always @(posedge clk) begin
if (rst) begin
counter <= 'd0;
bitOut <= 1'b0;
end
else if (en) begin
// Set when all checked bits are 1, clear when all checked bits are 0.
bitOut <= bitOut ? (|counter[FILT_WIDTH-1:HYST_BIT])
: (&counter[FILT_WIDTH-1:HYST_BIT]);
// Counter Logic
if (~&counter && bitIn) begin // Counter < maximum, count up if bitIn
counter <= counter + 2'd1;
end
else if (|counter && ~bitIn) begin // Counter > 0, count down if ~bitIn
counter <= counter - 2'd1;
end
end
end
endmodule
|
// bsg_fifo_1r1w_small
//
// bsg_fifo with 1 read and 1 write
//
// When harden=0 (default), it uses async-read memory implementation
// Otherwise, it uses sync-read hardened memory implementation
// *** Two implementations above are functionally equivalent ***
//
// used for smaller fifos.
//
// input handshake protocol (based on ready_THEN_valid_p parameter):
// valid-and-ready or
// ready-then-valid
//
// output protocol is valid-yumi (like typical fifo)
// aka valid-then-ready
//
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_small #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter harden_p = 0
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input v_i
, output ready_o
, input [width_p-1:0] data_i
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
if (harden_p == 0)
begin: unhardened
if (els_p == 2) begin:tf
bsg_two_fifo #(.width_p(width_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) twof
(.*);
end
else begin:un
bsg_fifo_1r1w_small_unhardened #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) fifo
(.*);
end
end
else
begin: hardened
bsg_fifo_1r1w_small_hardened #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) fifo
(.*);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small)
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> template <class T1, class T2> inline bool cmin(T1 &a, const T2 &b) { return b < a ? (a = b, true) : false; } template <class T1, class T2> inline bool cmax(T1 &a, const T2 &b) { return a < b ? (a = b, true) : false; } template <class Type> Type read() { Type a; bool b; unsigned char c; while (c = getchar() - 48, (c > 9) & (c != 253)) ; for (a = (b = c == 253) ? 0 : c; (c = getchar() - 48) <= 9; a = a * 10 + c) ; return b ? -a : a; } int (*rd)() = read<int>; namespace G { const int N = 2e5 + 10, M = 1e6 + 10; int n, m, s, t, to[M], cap[M], head[N], next[M], deg[N], dis[N], cur[N]; void init(int v, int src, int dst) { n = v, m = 0, s = src, t = dst; memset(head, -1, n * sizeof(int)); memset(deg, 0, n * sizeof(int)); } void edge(int u, int v, int w) { to[m] = v, cap[m] = w, next[m] = head[u], head[u] = m++; to[m] = u, cap[m] = 0, next[m] = head[v], head[v] = m++; } void add_edge(int u, int v, int min, int max) { if (max > min) edge(u, v, max - min); deg[u] += min; deg[v] -= min; } bool bfs() { static int queue[N]; int *qhead = queue, *qtail = queue; memset(dis, -1, n * sizeof(int)); dis[ *qtail++ = t] = 0; while (qhead != qtail) { int u = *qhead++; for (int i = head[u]; ~i; i = next[i]) if (cap[i ^ 1] && dis[to[i]] == -1) { dis[ *qtail++ = to[i]] = dis[u] + 1; if (to[i] == s) return true; } } return false; } int dfs(int u, int lim) { if (u == t) return lim; int rem = lim; for (int &i = cur[u]; ~i; i = next[i]) if (cap[i] && dis[to[i]] + 1 == dis[u]) { int now = dfs(to[i], std::min(cap[i], rem)); cap[i] -= now; cap[i ^ 1] += now; if ((rem -= now) == 0) break; } return lim - rem; } int flow(int ss, int tt) { int msave = m, ans = deg[ss]; edge(tt, ss, 1e9); for (int i = 0; i < n; ++i) { if (deg[i] < 0) edge(s, i, -deg[i]); if (deg[i] > 0) edge(i, t, deg[i]); } while (bfs()) { memcpy(cur, head, n * sizeof(int)); dfs(s, 1e9); } for (int i = head[s]; ~i; i = next[i]) if (cap[i]) return -1; for (int i = 0; i < n; ++i) while (~head[i] && head[i] >= msave) head[i] = next[head[i]]; s = ss, t = tt; while (bfs()) { memcpy(cur, head, n * sizeof(int)); dfs(s, 1e9); } for (int i = head[s]; ~i; i = next[i]) ans += cap[i ^ 1]; return ans; } } // namespace G const int N = 1e5; int x[N], y[N], nx, ny, rx[N], ry[N], cnt[2 * N], lim[2 * N]; char ans[N + 1]; int main() { int n, m, r, b; bool rev = false; n = rd(), m = rd(), r = rd(), b = rd(); if (r > b) rev = true, std::swap(r, b); for (int i = 0; i < n; ++i) { x[i] = rx[i] = rd(); y[i] = ry[i] = rd(); } std::sort(rx, rx + n); nx = std::unique(rx, rx + n) - rx; std::sort(ry, ry + n); ny = std::unique(ry, ry + n) - ry; G::init(nx + ny + 4, nx + ny + 2, nx + ny + 3); for (int i = 0; i < n; ++i) { x[i] = std::lower_bound(rx, rx + nx, x[i]) - rx; y[i] = std::lower_bound(ry, ry + ny, y[i]) - ry; ++cnt[x[i]], ++cnt[nx + y[i]]; G::add_edge(x[i], nx + y[i], 0, 1); } std::fill(lim, lim + nx + ny, n); while (m--) { int t = rd(), l = rd(), d = rd(); if (t == 1) { int i = std::lower_bound(rx, rx + nx, l) - rx; if (rx[i] == l) cmin(lim[i], d); } else { int i = std::lower_bound(ry, ry + ny, l) - ry; if (ry[i] == l) cmin(lim[nx + i], d); } } for (int i = 0; i < nx + ny; ++i) { lim[i] -= (lim[i] + cnt[i]) & 1; if (lim[i] < 0) { puts( -1 ); return 0; } int min = std::max(0, (cnt[i] - lim[i]) / 2), max = (lim[i] + cnt[i]) / 2; if (i < nx) G::add_edge(nx + ny, i, min, max); else G::add_edge(i, nx + ny + 1, min, max); } int f = G::flow(nx + ny, nx + ny + 1); if (f == -1) { puts( -1 ); return 0; } for (int i = 0; i < n; ++i) ans[i] = rb [rev ^ G::cap[2 * i]]; printf( %lld n%s n , (long long)r * f + (long long)b * (n - f), ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; string multiply(string num1, string num2) { int len1 = num1.size(); int len2 = num2.size(); if (len1 == 0 || len2 == 0) return 0 ; vector<int> result(len1 + len2, 0); int i_n1 = 0; int i_n2 = 0; for (int i = len1 - 1; i >= 0; i--) { int carry = 0; int n1 = num1[i] - 0 ; i_n2 = 0; for (int j = len2 - 1; j >= 0; j--) { int n2 = num2[j] - 0 ; int sum = n1 * n2 + result[i_n1 + i_n2] + carry; carry = sum / 10; result[i_n1 + i_n2] = sum % 10; i_n2++; } if (carry > 0) result[i_n1 + i_n2] += carry; i_n1++; } int i = result.size() - 1; while (i >= 0 && result[i] == 0) i--; if (i == -1) return 0 ; string s = ; while (i >= 0) s += std::to_string(result[i--]); return s; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T; cin >> T; while (T--) { long int n; cin >> n; n = n / 2; string n1, n2, n3, ans1, ans; int temp; if (n % 3 == 0) { temp = 4 * n / 3; n1 = to_string(temp); n2 = to_string(n + 1); n3 = to_string(2 * n + 1); ans1 = multiply(n1, n2); ans = multiply(ans1, n3); } else if (n % 3 == 2) { temp = 4 * (n + 1) / 3; n1 = to_string(temp); n2 = to_string(n); n3 = to_string(2 * n + 1); ans1 = multiply(n1, n2); ans = multiply(ans1, n3); } else { temp = 4 * (2 * n + 1) / 3; n1 = to_string(temp); n2 = to_string(n + 1); n3 = to_string(n); ans1 = multiply(n1, n2); ans = multiply(ans1, n3); } cout << ans << endl; } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
output xfer_req,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output m_axis_last,
output fifo_ready,
input fifo_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_xlast,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
reg req_xlast_d = 1'b0;
assign sync_id_ret = sync_id;
wire data_enabled;
wire _fifo_ready;
wire m_axis_last_s;
// We are not allowed to just de-assert valid, but if the streaming target does
// not accept any samples anymore we'd lock up the DMA core. So retain the last
// beat when disabled until it is accepted. But if in the meantime the DMA core
// is re-enabled and new data becomes available overwrite the old.
always @(posedge s_axis_aclk) begin
if(req_ready == 1'b1) begin
req_xlast_d <= req_xlast;
end
end
assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.m_axi_last(m_axis_last_s),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
assign fifo_ready = _fifo_ready | ~enabled;
endmodule
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
//32 bit registers - 32 Nos.
module Reg(
input wire clk, // Clock
input wire [`REG_ADDR_LEN - 1:0] ra,
input wire [`REG_ADDR_LEN - 1:0] rb,
output wire [`WIDTH - 1:0] dataA,
output wire [`WIDTH - 1:0] dataB,
output reg st_A, // output strobe
output reg st_B, // output strobe
input wire r_en_A,
input wire r_en_B,
input wire [`REG_ADDR_LEN - 1:0] rc,
input wire [`WIDTH -1 :0] dataC,
input wire w_en,
input wire [1:0] w_mode //w_mode: 0-word, 1-halfword, 2-byte
);
reg [`WIDTH - 1:0] RegFile [`NUM_REGS - 1:0];
assign dataA = (st_A == 1)?((ra!=0)?RegFile[ra]:0):32'bz;
assign dataB = (st_B == 1)?((rb!=0)?RegFile[rb]:0):32'bz;
always @(posedge clk) begin
if (w_en) begin
if(rc != 0) begin
case(w_mode)
0: RegFile[rc] <= dataC;
1: RegFile[rc] <= {16'b0, dataC[15:0]};
2: RegFile[rc] <= {24'b0, dataC[7:0]};
endcase
end
end
end
always @(negedge clk) begin
st_A = 0;
if (r_en_A) begin
// if(ra != 0)
// dataA = RegFile[ra];
// else
// dataA = 'd0;
st_A = 1;
//st_A = 0;
end
end
always @(negedge clk) begin
st_B = 0;
if (r_en_B) begin
// if(rb != 0)
// dataB = RegFile[rb];
// else
// dataB = 'd0;
st_B = 1;
//st_B = 0;
end
end
`ifdef TRACE_REG
integer i,j,k;
always @(posedge clk) begin
k=0;
for(i=0;i<32;i=i+4)
begin
//$write("R[%d] = ", k);
for(j=0;j<4;j=j+1)
begin
$write("R[%d] = %h\t", k, RegFile[k]);
k = k + 1;
end
$write("\n");
end
end
`endif
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: recv_credit_flow_ctrl.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Monitors the receive completion credits for headers and
// data to make sure the rx_port modules don't request too
// much data from the root complex, as this could result in
// some data being dropped/lost.
// Author: Matt Jacobsen
// Author: Dustin Richmond
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module recv_credit_flow_ctrl
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
input RX_ENG_RD_DONE, // Read completed
input TX_ENG_RD_REQ_SENT, // Read completion request issued
output RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
);
reg rCreditAvail=0;
reg rCplDAvail=0;
reg rCplHAvail=0;
reg [12:0] rMaxRecv=0;
reg [11:0] rCplDAmt=0;
reg [7:0] rCplHAmt=0;
reg [11:0] rCplD=0;
reg [7:0] rCplH=0;
reg rInfHCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
reg rInfDCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
assign RXBUF_SPACE_AVAIL = rCreditAvail;
// Determine the completions required for a max read completion request.
always @(posedge CLK) begin
rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
rCplDAmt <= #1 (rMaxRecv>>4);
rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
end
// Count the number of outstanding read completion requests.
always @ (posedge CLK) begin
if (RST) begin
rCplH <= #1 0;
rCplD <= #1 0;
end
else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH;
rCplD <= #1 rCplD;
end
else if (TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH + rCplHAmt;
rCplD <= #1 rCplD + rCplDAmt;
end
else if (RX_ENG_RD_DONE) begin
rCplH <= #1 rCplH - rCplHAmt;
rCplD <= #1 rCplD - rCplDAmt;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, d, sum, ans; char s[105]; int main() { scanf( %d %d , &n, &d); for (int i = 0; i < d; i++) { scanf( %s , s); bool ok = true; for (int j = 0; j < n; j++) if (s[j] == 0 ) ok = false; if (ok) sum = 0; else sum++, ans = max(ans, sum); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<array<int, 2>> a(n); map<int, int> hhor; map<int, int> hver; set<array<int, 2>> hor[n]; set<array<int, 2>> ver[n]; int idhor = 0, idver = 0; for (int i = 0; i < n; i++) { auto &[x, y] = a[i]; cin >> x >> y; if (hhor.find(y) == hhor.end()) hhor[y] = idhor++; if (hver.find(x) == hver.end()) hver[x] = idver++; hor[hhor[y]].insert({x, i}); ver[hver[x]].insert({y, i}); } auto one = [&](int x, int y) -> array<int, 2> { array<int, 2> tmp = {-1, -1}; int idx = 0; if (hhor.find(y) == hhor.end()) return tmp; int id = hhor[y]; auto it = hor[id].lower_bound({x, -1}); if (it != hor[id].end()) tmp[idx++] = ((*it)[1]); if (it != hor[id].begin()) { it--; tmp[idx++] = ((*it)[1]); } return tmp; }; auto two = [&](int x, int y) -> array<int, 2> { array<int, 2> tmp = {-1, -1}; int idx = 0; if (hver.find(x) == hver.end()) return tmp; int id = hver[x]; auto it = ver[id].lower_bound({y, -1}); if (it != ver[id].end()) tmp[idx++] = ((*it)[1]); if (it != ver[id].begin()) { it--; tmp[idx++] = ((*it)[1]); } return tmp; }; vector<vector<vector<array<int, 4>>>> pre( n, vector<vector<array<int, 4>>>(n, vector<array<int, 4>>(2))); auto ini = [&](int x, int y, int i, int j, int e) { array<int, 4> &now = pre[i][j][e]; array<int, 2> tmp = one(x, y); now[0] = tmp[0]; now[1] = tmp[1]; tmp = two(x, y); now[2] = tmp[0]; now[3] = tmp[1]; }; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { auto [x1, y1] = a[i]; auto [x2, y2] = a[j]; if (x1 == x2) ini(x1, (y1 + y2) / 2, i, j, 0); else if (y1 == y2) ini((x1 + x2) / 2, y1, i, j, 0); else { ini(x1, y2, i, j, 0); ini(x2, y1, i, j, 1); } } } const long long lim = (1ll << 31); long long l = 0, r = lim; while (l < r - 1) { int m = (l + r) / 2; vector<int> v[n]; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { auto [x1, y1] = a[i]; auto [x2, y2] = a[j]; if ((x1 == x2 && abs(y1 - y2) <= m) || (y1 == y2 && abs(x1 - x2) <= m)) { v[i].push_back(j); v[j].push_back(i); } } } vector<int> c(n, -1); int now = 0; for (int i = 0; i < n; i++) { if (c[i] != -1) continue; c[i] = now; queue<int> q; q.push(i); while (!q.empty()) { int e = q.front(); q.pop(); for (int to : v[e]) { if (c[to] != -1) continue; c[to] = now; q.push(to); } } now++; } bool ok = (now == 1); if (now <= 4) { auto go = [&](int x, int y, int i, int j, int e) { vector<int> z(now, 0); for (int b : pre[i][j][e]) if (b != -1 && abs(x - a[b][0]) + abs(y - a[b][1]) <= m) z[c[b]] = 1; bool b = 1; for (int k = 0; k < now; k++) b &= z[k]; if (b) ok = 1; }; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { auto [x1, y1] = a[i]; auto [x2, y2] = a[j]; if (x1 == x2) go(x1, (y1 + y2) / 2, i, j, 0); else if (y1 == y2) go((x1 + x2) / 2, y1, i, j, 0); else { go(x1, y2, i, j, 0); go(x2, y1, i, j, 1); } } } } if (ok) r = m; else l = m; } if (r < lim) cout << r << n ; else cout << -1 n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 50505; const int LMAX = 1600505; int N, A[NMAX]; vector<int> G[NMAX]; int currIdx; unordered_map<int, int> allValues; vector<int> newValues; int L[NMAX]; bool mark[NMAX]; vector<int> R; void read() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d , &A[i]); } for (int i = 1; i <= N; i++) { G[i].reserve(30); } } inline int bit(int idx) { return 1 << (idx - 1); } inline bool hasBit(int mask, int idx) { return mask & bit(idx); } void findCandidates(int x, int maxV, vector<int>& result) { int fstBit; for (int i = 30; i >= 1; i--) { if (hasBit(x, i)) { fstBit = i; break; } } int curr = 0; for (int i = fstBit; i >= 1; i--) { curr = (curr << 1) + hasBit(x, i); if (curr > maxV) { break; } result.push_back(curr); } } void clearPrevIter() { allValues.clear(); newValues.clear(); for (int i = 1; i <= N; i++) { G[i].clear(); } currIdx = N; } bool pairup(int x) { mark[x] = true; for (auto& y : G[x]) { if (!R[y] || (!mark[R[y]] && pairup(R[y]))) { L[x] = y; R[y] = x; return true; } } return false; } bool canMatch() { memset(L, 0, sizeof(L)); R.assign(currIdx + 1, 0); bool improve = true; int currMatches = 0; while (improve) { improve = false; memset(mark, false, sizeof(mark)); for (int i = 1; i <= N; i++) { if (!L[i] && pairup(i)) { improve = true; currMatches++; } } } return currMatches == N; } bool check(int maxV) { vector<int> currCandidates; currCandidates.reserve(30); clearPrevIter(); for (int i = 1; i <= N; i++) { currCandidates.clear(); findCandidates(A[i], maxV, currCandidates); for (auto& cand : currCandidates) { auto it = allValues.find(cand); int matchIdx; if (it == allValues.end()) { allValues[cand] = ++currIdx; newValues.push_back(cand); matchIdx = currIdx; } else { matchIdx = it->second; } G[i].push_back(matchIdx); } } return canMatch(); } int bSearch() { int i, step = (1 << 30); for (i = 0; step; step >>= 1) { if (!check(i + step)) { i += step; } } return ++i; } void solve() { int maxElem = bSearch(); check(maxElem); for (int i = 1; i <= N; i++) { if (i > 1) { printf( ); } printf( %d , newValues[L[i] - N - 1]); } printf( n ); } int main() { read(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s; cin >> s1 >> s; int a[10] = {0}, b[10] = {0}; for (int i = 0; i < s1.size(); i++) { int m = s1[i] - 0 ; if (m == 5 || m == 2) a[2]++; else if (m == 6 || m == 9) a[6]++; else a[m]++; } for (int i = 0; i < s.size(); i++) { int m = s[i] - 0 ; if (m == 5 || m == 2) b[2]++; else if (m == 6 || m == 9) b[6]++; else b[m]++; } int ans = 1000; for (int i = 0; i < 10; i++) { if (a[i]) { int k = b[i] / a[i]; if (ans > k) ans = k; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int gi() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int sum = 0; while ( 0 <= c && c <= 9 ) sum = sum * 10 + c - 48, c = getchar(); return sum; } const int maxn = 100005; int n, a[maxn], cnt[maxn], p[maxn][3], val[maxn]; priority_queue<pair<int, int>> que; int main() { n = gi(); for (int i = 1; i <= n; ++i) a[i] = gi(); sort(a + 1, a + n + 1); for (int i = 1, m = 0, lst = -1; i <= n; ++i) if (a[i] == lst) ++cnt[m]; else lst = a[i], ++m, val[m] = a[i], ++cnt[m]; for (int i = 1; i <= n; ++i) if (cnt[i]) que.push(make_pair(cnt[i], val[i])); pair<int, int> x, y, z; int ans = 0; while (que.size() >= 3) { x = que.top(); que.pop(); y = que.top(); que.pop(); z = que.top(); que.pop(); ++ans; p[ans][0] = x.second; p[ans][1] = y.second; p[ans][2] = z.second; sort(p[ans], p[ans] + 3, greater<int>()); if (x.first > 1) --x.first, que.push(x); if (y.first > 1) --y.first, que.push(y); if (z.first > 1) --z.first, que.push(z); } printf( %d n , ans); for (int i = 1; i <= ans; ++i) printf( %d %d %d n , p[i][0], p[i][1], p[i][2]); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_upconfig_fix_3451_v6.v
// Version : 1.7
//--
//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_upconfig_fix_3451_v6 # (
parameter UPSTREAM_FACING = "TRUE",
parameter PL_FAST_TRAIN = "FALSE",
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08
)
(
input pipe_clk,
input pl_phy_lnkup_n,
input [5:0] pl_ltssm_state,
input pl_sel_lnk_rate,
input [1:0] pl_directed_link_change,
input [3:0] cfg_link_status_negotiated_width,
input [15:0] pipe_rx0_data,
input [1:0] pipe_rx0_char_isk,
output filter_pipe
);
parameter TCQ = 1;
reg reg_filter_pipe;
reg [15:0] reg_tsx_counter;
wire [15:0] tsx_counter;
wire [5:0] cap_link_width;
// Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
// the core to see the TS1s on all the lanes being configured at the same time
// R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
// 225 pipe_clk cycles-sim_fast_train
// 60000 pipe_clk cycles-without sim_fast_train
// Not taking any action when PLDIRECTEDLINKCHANGE is set
// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
// data0 will be the first symbol on lane 0, data1 will be the next symbol.
// Don't look for PAD on data1 since it's unnecessary.
// COM=0xbc and PAD=0xf7 (and isk).
// detect if (data & 0xb4) == 0xb4 and isk, and then
// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
// no more than a 6-input LUT, so should be "free".
reg reg_filter_used, reg_com_then_pad;
reg reg_data0_b4, reg_data0_08, reg_data0_43;
reg reg_data1_b4, reg_data1_08, reg_data1_43;
reg reg_data0_com, reg_data1_com, reg_data1_pad;
wire data0_b4 = pipe_rx0_char_isk[0] &&
((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);
wire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);
wire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);
wire data1_b4 = pipe_rx0_char_isk[1] &&
((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);
wire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);
wire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);
wire data0_com = reg_data0_b4 && reg_data0_08;
wire data1_com = reg_data1_b4 && reg_data1_08;
wire data0_pad = reg_data0_b4 && reg_data0_43;
wire data1_pad = reg_data1_b4 && reg_data1_43;
wire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;
wire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;
wire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;
wire filter_used = (pl_ltssm_state == 6'h20) &&
(reg_filter_pipe || reg_filter_used);
always @(posedge pipe_clk) begin
reg_data0_b4 <= #TCQ data0_b4;
reg_data0_08 <= #TCQ data0_08;
reg_data0_43 <= #TCQ data0_43;
reg_data1_b4 <= #TCQ data1_b4;
reg_data1_08 <= #TCQ data1_08;
reg_data1_43 <= #TCQ data1_43;
reg_data0_com <= #TCQ data0_com;
reg_data1_com <= #TCQ data1_com;
reg_data1_pad <= #TCQ data1_pad;
reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;
reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;
end
always @ (posedge pipe_clk) begin
if (pl_phy_lnkup_n) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end else if ((pl_ltssm_state == 6'h20) &&
reg_com_then_pad &&
(cfg_link_status_negotiated_width != cap_link_width) &&
(pl_directed_link_change[1:0] == 2'b00)) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b1;
end else if (filter_pipe == 1'b1) begin
if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin
reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
reg_filter_pipe <= #TCQ 1'b1;
end else begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end
end
end
assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
assign tsx_counter = reg_tsx_counter;
assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module contains counter for the width and height of frames for the *
* video clipper core. *
* *
******************************************************************************/
module altera_up_video_clipper_counters (
// Inputs
clk,
reset,
increment_counters,
// Bi-Directional
// Outputs
start_of_outer_frame,
end_of_outer_frame,
start_of_inner_frame,
end_of_inner_frame,
inner_frame_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter LEFT_OFFSET = 0;
parameter RIGHT_OFFSET = 0;
parameter TOP_OFFSET = 0;
parameter BOTTOM_OFFSET = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input increment_counters;
// Bi-Directional
// Outputs
output start_of_outer_frame;
output end_of_outer_frame;
output start_of_inner_frame;
output end_of_inner_frame;
output inner_frame_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [WW: 0] width;
reg [HW: 0] height;
reg inner_width_valid;
reg inner_height_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
// Internal registers
always @(posedge clk)
begin
if (reset)
width <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
width <= 'h0;
else if (increment_counters)
width <= width + 1;
end
always @(posedge clk)
begin
if (reset)
height <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
height <= 'h0;
else
height <= height + 1;
end
end
always @(posedge clk)
begin
if (reset)
inner_width_valid <= (LEFT_OFFSET == 0);
else if (increment_counters)
begin
if (width == (IMAGE_WIDTH - 1))
inner_width_valid <= (LEFT_OFFSET == 0);
else if (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1))
inner_width_valid <= 1'b0;
else if (width == (LEFT_OFFSET - 1))
inner_width_valid <= 1'b1;
end
end
always @(posedge clk)
begin
if (reset)
inner_height_valid <= (TOP_OFFSET == 0);
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
inner_height_valid <= (TOP_OFFSET == 0);
else if (height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1))
inner_height_valid <= 1'b0;
else if (height == (TOP_OFFSET - 1))
inner_height_valid <= 1'b1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign start_of_outer_frame = (width == 'h0) & (height == 'h0);
assign end_of_outer_frame = (width == (IMAGE_WIDTH - 1)) &
(height == (IMAGE_HEIGHT - 1));
assign start_of_inner_frame = (width == LEFT_OFFSET) &
(height == TOP_OFFSET);
assign end_of_inner_frame = (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1)) &
(height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1));
assign inner_frame_valid = inner_width_valid & inner_height_valid;
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`include "defines.v"
`include "connectRouter_2SNoBuffer.v"
`timescale 1ns/1ps
module tb_connectRouters(
);
reg clk, rst;
reg `control_w port_in, inj;
reg bfull;
wire `control_w port_out, eject;
wire accept, push;
connectRouter_nobuffer r(
.clk(clk),
.rst(rst),
.port_in(port_in),
.inj(inj),
.port_out(port_out),
.accept(accept),
.bfull(bfull),
.eject(eject),
.push(push)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
bfull = 1;
port_in = 144'h011111111111111111111111111111111854; // MSHR 1; valid / seq 0; source 5; dest 7
// inj = 144'h0000000000000000000000000000000fffff;
inj = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
port_in = 144'h0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = 0\n, port_out %04x\n, accept %04x\n, eject %04x\n, push %04x\n",
port_out, accept, eject, push);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = 1\n, port_out %04x\n, accept %04x\n, eject %04x\n, push %04x\n",
port_out, accept, eject, push);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
/**
\file "startup-set.v"
Test case with set commands from a prsimrc source.
*/
`timescale 1ps/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg back, probe, g1, g2;
clk_gen #(.HALF_PERIOD(10), .PHASE_SHIFT(2)) clk(in);
// prsim stuff
initial
begin
// @haco@ startup-set.haco-c
$prsim("startup-set.haco-c");
`include "addpath_srcdir.v"
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.in", "foo");
$from_prsim("foo", "TOP.back");
$from_prsim("Vdd1", "TOP.probe");
$from_prsim("GND", "TOP.g1");
$from_prsim("GND", "TOP.g2");
#5 $prsim_cmd("source startup-set.prsimrc");
$prsim_cmd("queue");
#40 $finish;
end
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(back)
begin
$display("at time %7.3f, observed back %b", $realtime,back);
end
always @(probe)
begin
$display("at time %7.3f, observed probe %b", $realtime,probe);
end
always @(g1)
begin
$display("at time %7.3f, observed g1 %b", $realtime,g1);
end
always @(g2)
begin
$display("at time %7.3f, observed g2 %b", $realtime,g2);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> V; vector<int> E[200005]; int d[200005]; int p[200005]; int find(int x) { while (p[x] != x) p[x] = p[p[x]], x = p[x]; return x; } int rnk[200005]; void meld(int x, int y) { x = find(x), y = find(y); if (rnk[x] > rnk[y]) swap(x, y); p[x] = y; rnk[y] = rnk[x] == rnk[y] ? rnk[y] + 1 : rnk[y]; } int s, t; void build() { fill(begin(d), end(d), 1e9); queue<int> Q; for (auto x : V) Q.emplace(x), d[x] = 0; while (!Q.empty()) { auto x = Q.front(); Q.pop(); for (auto y : E[x]) { if (d[y] == 1e9) d[y] = d[x] + 1, Q.emplace(y); } } } int n, m, k; bool test(int mid) { iota(begin(p), end(p), 0); fill(begin(rnk), end(rnk), 0); for (int x = 1; x <= n; ++x) { if (d[x] + 1 > mid) continue; for (auto y : E[x]) if (d[x] + d[y] + 1 <= mid) meld(x, y); } return find(s) == find(t); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k; for (int i = 1; i <= k; ++i) { int x; cin >> x; V.push_back(x); } for (int i = 1; i <= m; ++i) { int u, v; cin >> u >> v; E[u].push_back(v); E[v].push_back(u); } cin >> s >> t; if (find(begin(V), end(V), t) == end(V)) V.push_back(t); build(); int l = 1, r = n; while (l < r) { int mid = (l + r) / 2; if (test(mid)) r = mid; else l = mid + 1; } if (test(l)) cout << l << endl; else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int min(int _a, int _b) { return _a < _b ? _a : _b; } inline int max(int _a, int _b) { return _a > _b ? _a : _b; } template <class _T> inline void rd(_T &_a) { int _f = 0, _ch = getchar(); _a = 0; while (_ch < 0 || _ch > 9 ) { if (_ch == - ) _f = 1; _ch = getchar(); } while (_ch >= 0 && _ch <= 9 ) _a = _a * 10 + _ch - 0 , _ch = getchar(); if (_f) _a = -_a; } const int inf = 0x3f3f3f3f; const double eps = 1e-8; const int mod = 1e9 + 7, N = 15; int mp[N][N], f[N][N], ct[N], n, m, k, ans; void dfs(int x, int y) { if (y > m) x++, y = 1; if (x > n) { ans++; ans %= mod; return; } int st = f[x - 1][y] | f[x][y - 1], pre, d = -1; if (n + m - x - y + 1 > k - __builtin_popcount(st)) return; for (int i = 1; i <= k; i++) if (!(st >> i - 1 & 1) && (!mp[x][y] || mp[x][y] == i)) { f[x][y] = st | (1 << i - 1); ct[i]++; if (ct[i] == 1) { if (~d) ans += d; else { pre = ans; dfs(x, y + 1); d = ans - pre; } } else dfs(x, y + 1); ans %= mod; ct[i]--; } } int main() { rd(n); rd(m); rd(k); if (n + m - 1 > k) return puts( 0 ), 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { rd(mp[i][j]); if (mp[i][j]) ct[mp[i][j]]++; } dfs(1, 1); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k, ans = 0; cin >> n >> k; if (n % k > (k / 2)) { cout << (n / k) * k + (k / 2) << endl; } else { cout << n << endl; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
|
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)
(uart_tx, ledout,
sys_clk_i, sys_rst_i,
bt_tx, bt_rx,ledres,mclk,micLRSel,micData, ampPWM,ampSD);
input sys_clk_i, sys_rst_i;
output uart_tx;
output ledout;
input bt_rx;
output bt_tx;
output mclk;
output ledres;
output micLRSel;
input micData;
output trigg;
input echo;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:8]cs; // CHIP-SELECT
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
wire [15:0] bt_dout;
wire [15:0] audio_dout;
wire [15:0] ultra_dout;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[5]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[6]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[7]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
peripheral_bt per_bt (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[8]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(bt_dout), .uart_tx(bt_tx), .uart_rx(bt_rx));
peripheral_audio per_audio (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(audio_dout),.mclk(mclk),. ledres(ledres),. micLRSel(micl),.micData(micData) );
peripheral_altavoz per_altavoz (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[1]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(audio_dout),.mclk(mclk),. ledres(ledres),. ampPWM(ampPWM),.ampSD(ampSD) );
peripheral_ultra per_ultra ( .clk(sys_clk_i) , .rst(sys_rst_i) , .d_in(j1_io_dout) , .cs(cs[2]) , .addr(j1_io_addr[3:0]) , .rd(j1_io_rd) , .wr(j1_io_wr), .d_out(ultra_dout), .trigg(trigg), .echo(echo) )
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[9]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8])
8'h63: cs= 8'b10000000; // direcciones - altavoz
8'h64: cs= 8'b01000000; //ultra
8'h65: cs= 8'b00100000; //audio
8'h66: cs= 8'b00010000; //bt
8'h67: cs= 8'b00001000; //mult
8'h68: cs= 8'b00000100; //div
8'h69: cs= 8'b00000010; //uart
8'h70: cs= 8'b00000001; //dp_ram
default: cs= 8'b0000000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
8'b10000000: j1_io_din = pwm_dout;
8'b01000000: j1_io_din = ultra_dout;
8'b00100000: j1_io_din = audio_dout;
8'b00010000: j1_io_din = bt_dout;
8'b00001000: j1_io_din = mult_dout;
8'b00000100: j1_io_din = div_dout;
8'b00000010: j1_io_din = uart_dout;
8'b00000001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
#include <bits/stdc++.h> using namespace std; int main() { long long int x; cin >> x; cout << x / 2520; }
|
#include <bits/stdc++.h> using namespace std; const int Nmax = 1000005, Mod = 1e9 + 7; const int Mod1 = 1e9 + 7, Mod2 = 1e9 + 9; char A[Nmax], B[Nmax]; int hash1[Nmax], hash2[Nmax]; int inv_hash1[Nmax], inv_hash2[Nmax]; int main() { ios::sync_with_stdio(false); int N, M; cin >> N >> M; cin >> (B + 1); int K = strlen(B + 1); for (int i = 1; i <= K; ++i) { hash1[i] = (27LL * hash1[i - 1] + B[i] - a + 1) % Mod1; hash2[i] = (27LL * hash2[i - 1] + B[i] - a + 1) % Mod2; } for (int i = K, pw1 = 1, pw2 = 1; i > 0; --i) { inv_hash1[i] = (inv_hash1[i + 1] + 1LL * (B[i] - a + 1) * pw1) % Mod1; inv_hash2[i] = (inv_hash2[i + 1] + 1LL * (B[i] - a + 1) * pw2) % Mod2; pw1 = 27LL * pw1 % Mod1; pw2 = 27LL * pw2 % Mod2; } set<int> insertions; bool goodSol = true; while (M-- > 0) { int left; cin >> left; int right = left + K - 1; auto it = insertions.upper_bound(left); if (it != insertions.begin()) { --it; int p = *it; if (p + K - 1 >= left) { int p1 = p + K - left, p2 = K - p1 + 1; if (hash1[p1] != inv_hash1[p2] || hash2[p1] != inv_hash2[p2]) { goodSol = false; break; } } } it = insertions.lower_bound(left); if (it != insertions.end()) { int p = *it; if (p <= right) { int p1 = right - p + 1, p2 = K - p1 + 1; if (hash1[p1] != inv_hash1[p2] || hash2[p1] != inv_hash2[p2]) { goodSol = false; break; } } } insertions.insert(left); } if (goodSol == false) cout << 0 n ; else { int ans = 1; for (int i = 1; i <= N; ++i) { auto it = insertions.upper_bound(i); if (it != insertions.begin()) { --it; int p = *it; if (p + K - 1 < i) ans = 26LL * ans % Mod; } else { ans = 26LL * ans % Mod; } } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 6; int x, f[12] = {0}; for (int i = 0; i < n; i++) { cin >> x; f[x]++; } bool res = 0; for (int i = 0; i < 10; i++) { if (f[i] >= 4) { res = 1; f[i] -= 4; for (int j = 0; j < 10; j++) { if (f[j] == 2) { cout << Elephant n ; return 0; } else if (f[j]) { cout << Bear n ; return 0; } } } } cout << Alien n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long INF = 1LL << 60; long long MOD = 1e9 + 7; namespace output { void pr(short x) { cout << x; } void pr(signed x) { cout << x; } void pr(long x) { cout << x; } void pr(long long x) { cout << x; } void pr(unsigned short x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(long double x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { cout << x; } template <size_t sz> void pr(const bitset<sz>& x) { cout << x; } template <class T> void pr(const complex<T>& x) { cout << x; } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T1, class T2, class T3> void pr(const tuple<T1, T2, T3>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( ( , x.first, , , x.second, ) ); } template <class T1, class T2, class T3> void pr(const tuple<T1, T2, T3>& x) { pr( ( , get<0>(x), , , get<1>(x), , , get<2>(x), ) ); } template <class T> void pr(const T& x) { pr( [ ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( ] ); } void print() { pr( n ); } template <class T, class... Ts> void print(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); print(ts...); } } // namespace output using namespace output; template <class T1, class T2> istream& operator>>(istream& is, pair<T1, T2>& x) { is >> x.first >> x.second; return is; } template <class T1, class T2, class T3> istream& operator>>(istream& is, tuple<T1, T2, T3>& x) { is >> get<0>(x) >> get<1>(x) >> get<2>(x); return is; } template <class T> istream& operator>>(istream& is, vector<T>& v) { for (auto& x : v) is >> x; return is; } long long powa(long long base, long long exp) { long long res = 1; while (exp) { if (exp & 1) res = res * base % MOD; base = base * base % MOD; exp >>= 1; } return res; } bool mini(long long& a, long long b) { return b < a ? a = b, 1 : 0; } bool maxi(long long& a, long long b) { return b > a ? a = b, 1 : 0; } signed main() { ios::sync_with_stdio(0), cin.tie(0); vector<vector<long long> > silly = {{1, 2, 4}, {5, 3, 8}, {9, 6, 7}}; long long n; cin >> n; if (n <= 2) print(-1); else { vector<vector<long long> > grid(n, vector<long long>(n)); long long cnt = 1; bool vert = false; for (long long(i) = (n - 1); (i) > (2); --(i)) { if (!vert) { for (long long(j) = (0); (j) < (i + 1); ++(j)) grid[i][j] = cnt++; for (long long(j) = (i - 1); (j) > (-1); --(j)) grid[j][i] = cnt++; } else { for (long long(j) = (0); (j) < (i + 1); ++(j)) grid[j][i] = cnt++; for (long long(j) = (i - 1); (j) > (-1); --(j)) grid[i][j] = cnt++; } vert = !vert; } for (long long(i) = (0); (i) < (3); ++(i)) for (long long(j) = (0); (j) < (3); ++(j)) grid[i][j] = silly[i][j] + cnt - 1; for (long long(i) = (0); (i) < (n); ++(i)) { for (long long(j) = (0); (j) < (n); ++(j)) cout << grid[i][j] << ; cout << n ; } } }
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#include <bits/stdc++.h> using namespace std; long long ansp[200001]; int main() { long long k; memset(ansp, 0, sizeof(ansp)); scanf( %lld , &k); char s[200001], t[200001], ans[200001]; scanf( %s %s , s, t); long long add = 0, dec = 0, again = 0; long long i, j; for (i = 0; i < k; i++) { long long x = s[i] - a , y = t[i] - a + add; add = 0; if ((x + y) % 2 != 0) { add = 26; y--; } long long now = (x + y) / 2; ansp[i] = now; } for (i = k - 1; i >= 0; i--) { ansp[i - 1] += ansp[i] / 26; ansp[i] %= 26; } for (i = 0; i < k; i++) printf( %c , (char)(ansp[i] + a )); }
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#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef pair<int,int> PII; const int maxn=111111,mod=998244353; const double PI=3.141592653589793; #define MP make_pair #define PB push_back #define lson o<<1,l,mid #define rson o<<1|1,mid+1,r #define FOR(i,a,b) for(int i=(a);i<=(b);i++) #define ROF(i,a,b) for(int i=(a);i>=(b);i--) #define MEM(x,v) memset(x,v,sizeof(x)) inline ll read(){ char ch=getchar();ll x=0,f=0; while(ch< 0 || ch> 9 ) f|=ch== - ,ch=getchar(); while(ch>= 0 && ch<= 9 ) x=x*10+ch- 0 ,ch=getchar(); return f?-x:x; } inline int qpow(int a,int b){ int ans=1; for(;b;b>>=1,a=1ll*a*a%mod) if(b&1) ans=1ll*ans*a%mod; return ans; } int n,at,id[maxn],a[maxn],cnt,ans[maxn][2],al; bool vis[maxn]; struct point{ int x,y,id; point operator-(const point &p)const{return (point){x-p.x,y-p.y,id};} double ang()const{return atan2(y,x);} bool operator<(const point &p)const{ if(p.id==at) return false; if(id==at) return true; return ang()<p.ang(); } }p[maxn],q[maxn]; inline void add(int x,int y){ ans[++al][0]=x; ans[al][1]=y; swap(a[x],a[y]); } void dfs(int x){ id[x]=cnt; if(!id[a[x]]) dfs(a[x]); } int main(){ n=read(); FOR(i,1,n) p[i].x=read(),p[i].y=read(),a[i]=read(),p[i].id=i; FOR(i,1,n) if(i!=a[i]){ if(!at || MP(p[i].x,p[i].y)<MP(p[at].x,p[at].y)) at=i; } if(!at) return puts( 0 ),0; FOR(i,1,n) if(!id[i]) cnt++,dfs(i); FOR(i,1,n) if(i!=at) p[i]=p[i]-p[at]; sort(p+1,p+n+1); if(p[n].ang()-p[2].ang()>PI){ ROF(i,n,2) if(p[i].ang()-p[2].ang()<PI){ q[1]=p[1]; FOR(j,i+1,n) q[j-i+1]=p[j]; FOR(j,2,i) q[n-i+j]=p[j]; break; } } else FOR(i,1,n) q[i]=p[i]; vis[id[q[2].id]]=true; FOR(i,3,n) if(!vis[id[q[i].id]]){ add(q[i].id,q[i-1].id); vis[id[q[i].id]]=true; } while(a[at]!=at) add(a[at],at); printf( %d n ,al); FOR(i,1,al) printf( %d %d n ,ans[i][0],ans[i][1]); }
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#include <bits/stdc++.h> using namespace std; int main() { string s; int pearls = 0, links = 0; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == - ) links++; else pearls++; } if (pearls == 0) cout << yes << endl; else if (links % pearls == 0) cout << yes << endl; else cout << no << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; void JIZZ(string output = ) { cout << output; exit(0); } const long double PI = 3.14159265358979323846264338327950288; const long double eps = 1e-13; const long long mod = 1e9 + 7; struct node { node *l, *r; int mx; node() : l(0), r(0), mx(-(1 << 30)) {} } * root, pool[100000]; int pptr = -1; int a[20005], pre[20005], dp[53][20005]; node *nnode() { ++pptr; pool[pptr].l = pool[pptr].r = 0; pool[pptr].mx = -(1 << 30); return &pool[pptr]; } void build(node *now, int l, int r) { if (l == r) return; build(now->l = nnode(), l, ((l + r) >> 1)); build(now->r = nnode(), ((l + r) >> 1) + 1, r); } void modify(node *now, int l, int r, int x, int v) { if (l == r) { now->mx = max(now->mx, v); return; } if (x <= ((l + r) >> 1)) modify(now->l, l, ((l + r) >> 1), x, v); else modify(now->r, ((l + r) >> 1) + 1, r, x, v); now->mx = max(now->l->mx, now->r->mx); } int query(node *now, int l, int r, int ql, int qr) { ; ; if (qr < l || r < ql) return -(1 << 30); if (ql <= l && r <= qr) return now->mx; return max(query(now->l, l, ((l + r) >> 1), ql, qr), query(now->r, ((l + r) >> 1) + 1, r, ql, qr)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, k, p; cin >> n >> k >> p; for (int i = 1; i <= n; ++i) cin >> a[i], a[i] %= p; for (int i = 1; i <= n; ++i) pre[i] = (pre[i - 1] + a[i]) % p; for (int i = 1; i <= n; ++i) dp[0][i] = -(1 << 30); for (int i = 1; i <= k; ++i) { pptr = -1; build(root = nnode(), 0, p - 1); modify(root, 0, p - 1, 0, 0); for (int j = 1; j <= n; ++j) { dp[i][j] = pre[j] + query(root, 0, p - 1, 0, pre[j]); if (pre[j] != p - 1) dp[i][j] = max(dp[i][j], pre[j] + query(root, 0, p - 1, pre[j] + 1, p - 1) + p); modify(root, 0, p - 1, pre[j], -pre[j] + dp[i - 1][j]); ; ; } } cout << dp[k][n] << endl; }
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#include <bits/stdc++.h> using namespace std; const long long int MOD = 1000000000 + 7; long long int arr[200005]; int main() { ios::sync_with_stdio(0); cin.tie(0); long long int t; cin >> t; while (t--) { long long int n, sum = 0; cin >> n; for (long long int i = 0; i < n; i++) cin >> arr[i]; long long int i = 0; vector<long long int> vec; while (1) { long long int maxp = INT_MIN; long long int maxn = INT_MIN; for (; i < n; i++) { if (arr[i] < 0) break; else { maxp = max(maxp, arr[i]); } } if (maxp != INT_MIN) vec.push_back(maxp); if (i == n) break; for (; i < n; i++) { if (arr[i] >= 0) break; else { maxn = max(maxn, arr[i]); } } if (maxn != INT_MIN) vec.push_back(maxn); if (i == n) break; } for (long long int i = 0; i < vec.size(); i++) sum += vec[i]; cout << sum << endl; } return 0; }
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// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_di_buffer_wrap(
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter DATA_WIDTH = 18;
parameter READ_DATA_SIZE = 9;
parameter WRITE_TO_READ_RATIO_2_EXPONENT = 2;
localparam WRITE_TO_READ_RATIO = 2 ** WRITE_TO_READ_RATIO_2_EXPONENT;
input clock;
input [DATA_WIDTH-1:0] data;
input [WRITE_TO_READ_RATIO_2_EXPONENT + 1 : 0] rdaddress;
input [1:0] wraddress;
input wren;
output [READ_DATA_SIZE - 1 : 0] q;
wire [DATA_WIDTH-1:0] q_wire;
rw_manager_di_buffer rw_manager_di_buffer_i(
.clock(clock),
.data(data),
.rdaddress(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT + 1 : WRITE_TO_READ_RATIO_2_EXPONENT]),
.wraddress(wraddress),
.wren(wren),
.q(q_wire));
generate
if(WRITE_TO_READ_RATIO_2_EXPONENT > 0) begin
rw_manager_datamux rw_manager_datamux_i(
.datain(q_wire),
.sel(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0]),
.dataout(q)
);
defparam rw_manager_datamux_i.DATA_WIDTH = READ_DATA_SIZE;
defparam rw_manager_datamux_i.SELECT_WIDTH = WRITE_TO_READ_RATIO_2_EXPONENT;
defparam rw_manager_datamux_i.NUMBER_OF_CHANNELS = WRITE_TO_READ_RATIO;
end
else begin
assign q = q_wire;
end
endgenerate
endmodule
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`timescale 1ns / 1ps
//**********************************************************************
// File: spi_master.v
// Module:spi_master
// by Robin zhang
//**********************************************************************
module spi_master_kl(
clk,rst_n,
spi_miso,spi_mosi,spi_clk,
spi_tx_en,spi_rx_en,spi_over,mode_select,receive_status,
cs
);
input clk;
input rst_n;
input spi_miso;
output spi_mosi;
output spi_clk;
output cs;
input spi_tx_en;
output spi_over;
output receive_status;
input spi_rx_en;
input mode_select;
reg[7:0] data_count;
reg[7:0] recv_detect;
reg[7:0] spi_tx_db;
reg[4:0] cnt8;
reg spi_clkr;
reg spi_mosir;
reg spi_mosir1;
reg receive_status;
reg[7:0] spi_rx_dbr;
reg[7:0] spi_rx_dbr1;
reg frame_delay;
reg start_delay;
reg cs;
reg[7:0] frame_delay_cnt;
reg[7:0] start_delay_cnt;
wire[7:0] spi_rx_db;
wire[4:0] mode_reg;
wire[4:0] start_reg;
/***********************************************************************
*detect spi mode
***********************************************************************/
assign mode_reg = mode_select ? 5'd18 : 5'd17;
assign start_reg = mode_select ? 5'd1 : 5'd0;
/***********************************************************************
*control the spi timimg
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt8 <= 5'd0;
data_count <= 8'h0;
spi_tx_db <= 8'h0;
recv_detect <= 8'h0;
cs <= 1'b1;
end
else if((spi_tx_en || spi_rx_en) && (data_count < 8'd64) && (start_delay == 1'b1)) begin
if(cnt8 < mode_reg)begin
cnt8 <= cnt8+1'b1;
cs <= 1'b0;
end
else begin
if(spi_tx_en && spi_rx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
else begin
if(spi_tx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
end
else if(frame_delay == 1'b0) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
end
end
end
else begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count;
end
end
/***********************************************************************
*start delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
start_delay <= 1'b0;
start_delay_cnt <= 'h0;
end
else begin
if((spi_tx_en || spi_rx_en) && (start_delay_cnt < 'd250))begin
start_delay_cnt <= start_delay_cnt + 1'b1;
end
else begin
start_delay <= 1'b1;
end
end
end
/***********************************************************************
*frame to frame delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
frame_delay <= 1'b1;
frame_delay_cnt <= 'h0;
end
else begin
if((cnt8 >= (mode_reg - 1'b1)) && (frame_delay_cnt < 'd250))begin
frame_delay <= 1'b1;
frame_delay_cnt <= frame_delay_cnt + 1'b1;
end
else begin
frame_delay <= 1'b0;
frame_delay_cnt <= 'h0;
end
end
end
/***********************************************************************
*generate spi clk
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_clkr <= mode_select ? 1'b1 : 1'b0;
else if(cnt8 > start_reg && cnt8 < mode_reg)
spi_clkr <= ~spi_clkr;
else
spi_clkr <= spi_clkr;
end
assign spi_clk = spi_clkr;
/***********************************************************************
*spi master output data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd0: spi_mosir <= spi_tx_db[7];
4'd1: spi_mosir <= spi_tx_db[6];
4'd2: spi_mosir <= spi_tx_db[5];
4'd3: spi_mosir <= spi_tx_db[4];
4'd4: spi_mosir <= spi_tx_db[3];
4'd5: spi_mosir <= spi_tx_db[2];
4'd6: spi_mosir <= spi_tx_db[1];
4'd7: spi_mosir <= spi_tx_db[0];
default: spi_mosir <= 1'b1;
endcase
end
else
spi_mosir <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir1 <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd1: spi_mosir1 <= spi_tx_db[7];
4'd2: spi_mosir1 <= spi_tx_db[6];
4'd3: spi_mosir1 <= spi_tx_db[5];
4'd4: spi_mosir1 <= spi_tx_db[4];
4'd5: spi_mosir1 <= spi_tx_db[3];
4'd6: spi_mosir1 <= spi_tx_db[2];
4'd7: spi_mosir1 <= spi_tx_db[1];
4'd8: spi_mosir1 <= spi_tx_db[0];
default: spi_mosir1 <= 1'b1;
endcase
end
else
spi_mosir1 <= 1'b1;
end
assign spi_mosi = mode_select ? spi_mosir1 : spi_mosir;
/***********************************************************************
*spi master input data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd1: spi_rx_dbr[7] <= spi_miso;
5'd3: spi_rx_dbr[6] <= spi_miso;
5'd5: spi_rx_dbr[5] <= spi_miso;
5'd7: spi_rx_dbr[4] <= spi_miso;
5'd9: spi_rx_dbr[3] <= spi_miso;
5'd11: spi_rx_dbr[2] <= spi_miso;
5'd13: spi_rx_dbr[1] <= spi_miso;
5'd15: spi_rx_dbr[0] <= spi_miso;
default: spi_rx_dbr <= spi_rx_dbr;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr1 <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd3: spi_rx_dbr1[7] <= spi_miso;
5'd5: spi_rx_dbr1[6] <= spi_miso;
5'd7: spi_rx_dbr1[5] <= spi_miso;
5'd9: spi_rx_dbr1[4] <= spi_miso;
5'd11: spi_rx_dbr1[3] <= spi_miso;
5'd13: spi_rx_dbr1[2] <= spi_miso;
5'd15: spi_rx_dbr1[1] <= spi_miso;
5'd17: spi_rx_dbr1[0] <= spi_miso;
default: spi_rx_dbr1 <= spi_rx_dbr1;
endcase
end
end
assign spi_rx_db = mode_select ? spi_rx_dbr1 : spi_rx_dbr;
assign spi_over = (data_count == 8'd64) ? 1'b1 :1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <= (recv_detect == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int read() { int num = 0; bool f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { f = (ch == - ); ch = getchar(); } while (ch >= 0 && ch <= 9 ) { num = (num << 1) + (num << 3) + ch - 0 ; ch = getchar(); } return f ? -num : num; } int main() { int num[111]; int n = read(), cnt = 0, t = 0, ans = 0; memset(num, 0, sizeof(num)); while (n) { num[cnt++] = n % 2; n >>= 1; } swap(num[0], num[4]); swap(num[2], num[3]); for (int i = 0; i <= 5; i++) if (num[i]) ans += pow(2, i); printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000005; int N; vector<int> G[MAX_N]; int cyid[MAX_N], Q[MAX_N]; vector<vector<int>> cycles, newcycles; void find_cycle(int s, int curid) { cyid[s] = curid; cycles.back().push_back(s); for (int i = 0; i < G[s].size(); i++) { if (cyid[G[s][i]] == -1) { find_cycle(G[s][i], curid); } } } void get_cycles() { fill(cyid + 1, cyid + N + 1, -1); int nCycles = 0; for (int i = 1; i <= N; i++) { if (cyid[i] == -1) { cycles.push_back(vector<int>()); find_cycle(i, ++nCycles); } } } void construct_root_permutation() { int numEven = 0, numOdd = 0; for (vector<int> p : cycles) { if (p.size() % 2 == 0) numEven++; else numOdd++; } if (numEven % 2 == 1) { printf( -1 n ); return; } sort(cycles.begin(), cycles.end(), [](vector<int> a, vector<int> b) { return a.size() < b.size(); }); for (int i = 0; i < cycles.size();) { if (cycles[i].size() % 2 == 1) { if (cycles[i].size() == 1) newcycles.push_back({cycles[i][0]}); else { vector<int> newcyk; int ptr1 = 0, ptr2 = (cycles[i].size() - 1) / 2 + 1; for (int j = 0; j < cycles[i].size() / 2; j++) { newcyk.push_back(cycles[i][ptr1++]); newcyk.push_back(cycles[i][ptr2++]); } newcyk.push_back(cycles[i][ptr1]); newcycles.emplace_back(newcyk); } i++; } else { if (i + 1 < cycles.size()) { if (cycles[i].size() != cycles[i + 1].size()) { printf( -1 n ); return; } else { vector<int> merged; for (int j = 0; j < cycles[i].size(); j++) { merged.push_back(cycles[i][j]); merged.push_back(cycles[i + 1][j]); } newcycles.emplace_back(merged); i += 2; } } else { printf( -1 n ); return; } } } for (int i = 0; i < newcycles.size(); i++) { if (newcycles[i].size() == 1) Q[newcycles[i][0]] = newcycles[i][0]; else { newcycles[i].push_back(newcycles[i][0]); for (int j = 0; j < newcycles[i].size() - 1; j++) { int next = newcycles[i][j + 1]; Q[newcycles[i][j]] = next; } } } for (int i = 1; i <= N; i++) printf( %d , Q[i]); printf( n ); } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { int pi; scanf( %d , &pi); G[i].push_back(pi); } get_cycles(); construct_root_permutation(); return 0; }
|
/*
* Arithmetic and logical operations for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_arlog (
input [15:0] x,
input [15:0] y,
input [ 2:0] f,
output [15:0] o,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire [15:0] outadd;
wire [15:0] outlog;
wire ci;
wire cfoadd;
wire log;
wire xs;
wire ys;
wire os;
// Module instances
zet_fulladd16 fulladd16 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (outadd),
.s (f[0])
);
// Assignemnts
assign op2 = f[0] ? ~y /* sbb,sub,cmp */
: y; /* add, adc */
assign ci = f[2] | ~f[2] & f[1] & (!f[0] & cfi
| f[0] & ~cfi);
assign log = f[2:0]==3'd1 || f[2:0]==3'd4 || f[2:0]==3'd6;
assign afo = !log & (x[4] ^ y[4] ^ outadd[4]);
assign cfo = !log & (word_op ? cfoadd : (x[8]^y[8]^outadd[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? outadd[15] : outadd[7];
assign ofo = !log &
(f[0] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os));
assign outlog = f[2] ? (f[1] ? x^y : x&y) : x|y;
assign o = log ? outlog : outadd;
endmodule
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ()
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* reg_slice.v
*
* General purpose register bank. For correct operation, this block requires
* a running clock on i_clk at all times.
*
* i_ena high defines "normal mode", and the data on vi_regs appears at
* vo_regs on each rising edge of i_clk. The vio_tbus is tristated.
*
* In normal mode, the signals i_step and i_wr are ignored. Bringing i_rd
* high will cause a sample of the data in the register to appear on vio_tbus.
* This sample will be taken on the next rising edge if i_clk after i_rd
* goes high. As long as i_rd is held high, the data which was initially
* sampled will continue to appear on vio_tbus. One period after data appears
* on vio_tbus, the signal o_success will go high, indicating that vio_tbus
* can be read. This will stay high for 1.5-2 periods after i_rd goes low.
*
* i_ena low defines "test mode". In this mode, the register clock is
* synchronously disabled, and the register will retain the last value.
* In test mode, i_rd behaves the same as in normal mode. If i_wr goes
* high, the value on vio_tbus (driven externally) will be latched into
* the register 1-1.5 periods after i_wr goes high. 2-2.5 periods after
* i_wr goes high, o_success will go high, indicating the data was latched.
* This will stay high 2.5-3 periods after i_wr goes low.
*
* In test mode, i_step can also be used to allow the register to receive
* a single rising edge. The register will latch vi_regs identically to
* normal operation, hence this is a method to single-step the clock.
* o_success has a similar behavior where it goes high 1.5-2 periods after
* i_step goes high, indicating that the register was cycled.
*
* It is important that only one of the signals i_rd, i_wr, and i_step are
* active at a time. Having more than one active at a time causes bus
* contention and is undefined. it is also important to have AT LEAST 6
* periods between when one signal becomes inactive and another becomes
* active.
*
*/
module reg_slice (/*AUTOARG*/
// Outputs
vo_regs,
// Inouts
io_success, vio_tbus,
// Inputs
i_clk, i_rstb, i_ena, vi_regs, i_step, i_rd, i_wr
);
parameter DWIDTH = 16; // Register size
input i_clk; // Master clock
input i_rstb; // Master reset
input i_ena; // Asynchronous enable signal
input [DWIDTH-1:0] vi_regs; // Data to register
output [DWIDTH-1:0] vo_regs; // Data in register
input i_step; // Manually step the clock
input i_rd; // Put register data on test bus
input i_wr; // Load data on test bus into register
inout io_success; // Indicates a successful transaction
inout [DWIDTH-1:0] vio_tbus;
// Synchronize the ena, rd, wr and step signals
wire ena_sync, rd_sync, wr_sync, step_sync;
negedge_sync ena_synchro(.i_clk(i_clk), .i_async(i_ena),
.o_sync(ena_sync));
negedge_sync rd_synchro(.i_clk(i_clk), .i_async(i_rd),
.o_sync(rd_sync));
negedge_sync wr_synchro(.i_clk(i_clk), .i_async(i_wr),
.o_sync(wr_sync));
negedge_sync step_synchro(.i_clk(i_clk), .i_async(i_step),
.o_sync(step_sync));
/*
* Generate the clock to the main register. When enabled, this clock
* is simply i_clk. When the register is disabled, the register is
* clocked by clk_pulse, which is either the write or step clock.
*/
wire clk_pulse;
wire clk_regs = ena_sync ? i_clk : clk_pulse;
reg r_wr_prev, r_wr_pprev, r_step_prev;
wire clk_pulse_wr, clk_pulse_step;
always @( posedge i_clk or negedge i_rstb ) begin : main_clk_reg
if ( !i_rstb ) begin
r_wr_prev <= 0;
r_wr_pprev <= 0;
r_step_prev <= 0;
end
else begin
r_wr_prev <= wr_sync;
r_wr_pprev <= r_wr_prev;
r_step_prev <= step_sync;
end
end // block: main_clk_reg
assign clk_pulse_wr = r_wr_prev && !r_wr_pprev;
assign clk_pulse_step = step_sync && !r_step_prev;
assign clk_pulse = wr_sync ? clk_pulse_wr : clk_pulse_step;
/*
* Generate clock to load the shadow register. This is a pulse which
* rises on the falling edge of i_clk, and lasts half an i_clk period.
* This is to ensure that there is no race condition between the Q output
* of the main register (changes on the rising edge of i_clk).
*/
reg r_rd_prev;
wire clk_pulse_rd;
always @( posedge i_clk or negedge i_rstb ) begin : shadow_clk_reg
if ( !i_rstb )
r_rd_prev <= 0;
else
r_rd_prev <= rd_sync;
end
assign clk_pulse_rd = rd_sync && !r_rd_prev;
reg [DWIDTH-1:0] rv_shadow;
always @( posedge clk_pulse_rd or negedge i_rstb ) begin : shadow_reg
if ( !i_rstb )
rv_shadow <= 0;
else
rv_shadow <= vo_regs;
end
assign vio_tbus = (rd_sync && i_rd) ? rv_shadow : {DWIDTH{1'bz}};
/*
* Main register file. Input is v_regs_pre, which is multiplexed from
* either the normal input when enabled, or the test bus when disabled.
*/
reg [DWIDTH-1:0] vo_regs;
wire [DWIDTH-1:0] v_regs_pre;
assign v_regs_pre = ( !ena_sync && wr_sync ) ? vio_tbus : vi_regs;
always @( posedge clk_regs or negedge i_rstb ) begin : main_reg
if ( !i_rstb )
vo_regs <= 0;
else
vo_regs <= v_regs_pre;
end
/*
* Generate the handshaking signal back to the register interface state
* machine, indicating that the current action (rd, wr, step) completed
*/
wire pre_io_success = r_rd_prev || ( !ena_sync && r_wr_pprev );
assign io_success = ( i_rd || i_wr ) ? pre_io_success : 1'bz;
endmodule
|
`include "bsg_defines.v"
module bsg_fsb_to_nasti_slave_connector
import bsg_fsb_pkg::RingPacketType;
import bsg_nasti_pkg::bsg_nasti_addr_channel_s;
import bsg_nasti_pkg::bsg_nasti_write_data_channel_s;
import bsg_nasti_pkg::bsg_nasti_read_data_channel_s;
import bsg_nasti_pkg::bsg_nasti_write_response_channel_s;
#(parameter ring_width_p=$bits(bsg_fsb_pkg::RingPacketType)
, destid_p="inv")
(
input clk_i
, input reset_i
, output bsg_nasti_addr_channel_s nasti_read_addr_ch_o
, input logic nasti_read_addr_ch_ready_i
, output bsg_nasti_addr_channel_s nasti_write_addr_ch_o
, input logic nasti_write_addr_ch_ready_i
, output bsg_nasti_write_data_channel_s nasti_write_data_ch_o
, input logic nasti_write_data_ch_ready_i
, input bsg_nasti_read_data_channel_s nasti_read_data_ch_i
, output logic nasti_read_data_ch_ready_o
, input bsg_nasti_write_response_channel_s nasti_write_resp_ch_i
, output logic nasti_write_resp_ch_ready_o
// from fsb
, input fsb_v_i
, input [ring_width_p-1:0] fsb_data_i
, output logic fsb_ready_o
// to fsb
, output logic fsb_v_o
, output logic [ring_width_p-1:0] fsb_data_o
, input fsb_yumi_i
);
// first buffer all of the signals with a fifo
// because we cannot reliable assert ready without
// inspecting the input packets
logic [ring_width_p-1:0] in_fifo_data;
logic in_fifo_yumi;
logic in_fifo_v;
bsg_two_fifo #( .width_p(ring_width_p)) fifo_in
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(fsb_ready_o)
,.v_i (fsb_v_i )
,.data_i (fsb_data_i )
,.v_o (in_fifo_v)
,.data_o(in_fifo_data)
,.yumi_i(in_fifo_yumi)
);
RingPacketType ring_data_in, ring_data_out;
// demultiplex incoming data
assign ring_data_in = in_fifo_data;
// handle channels going to nasti
// we demultiplex packets going from fsb to nasti
always @(*)
begin
nasti_read_addr_ch_o.v = 1'b0;
nasti_read_addr_ch_o.addr = ring_data_in.data[31:0];
nasti_read_addr_ch_o.id = ring_data_in.data[32+:5];
nasti_read_addr_ch_o.size = 3'b11; // fixme; hardcode this to correct val
nasti_read_addr_ch_o.len = 8'b111; // fixme; hardcode this to correct val
nasti_write_addr_ch_o.v = 1'b0;
nasti_write_addr_ch_o.addr = ring_data_in.data[31:0];
nasti_write_addr_ch_o.id = ring_data_in.data[32+:5];
nasti_write_addr_ch_o.size = 3'b11; // fixme; hardcode this to correct val
nasti_write_addr_ch_o.len = 8'b111; // fixme; hardcode this to correct val
nasti_write_data_ch_o.v = 1'b0;
nasti_write_data_ch_o.data = ring_data_in.data[63:0];
nasti_write_data_ch_o.strb = 8'b1111_1111; // fixme; hardcode this to correct val
nasti_write_data_ch_o.last = 1'b0;
in_fifo_yumi = 1'b0;
if (in_fifo_v & ~ring_data_in.cmd)
begin
// note, these are only requests from master to slave
unique casez (ring_data_in.opcode)
// read request addr
7'b000_0100:
begin
nasti_read_addr_ch_o.v = 1'b1;
in_fifo_yumi = nasti_read_addr_ch_ready_i;
end
// write request addr
7'b000_0101:
begin
nasti_write_addr_ch_o.v = 1'b1;
in_fifo_yumi = nasti_write_addr_ch_ready_i;
end
// write request data not last
7'b000_0110:
begin
nasti_write_data_ch_o.v = 1'b1;
in_fifo_yumi = nasti_write_data_ch_ready_i;
end
// write request data last
7'b000_0111:
begin
nasti_write_data_ch_o.v = 1'b1;
nasti_write_data_ch_o.last = 1'b1;
in_fifo_yumi = nasti_write_data_ch_ready_i;
end
default:
begin
$display("*** %m unmatched opcode for fsb_to_nasti_slave",ring_data_in.opcode);
end
endcase // unique casez {
end // if (in_fifo_v && ring_data_in.cmd)
end // always @ (*)
logic out_fifo_ready;
RingPacketType out_fifo_data;
logic out_fifo_v;
bsg_two_fifo #( .width_p(ring_width_p)) fifo_out
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(out_fifo_ready)
,.v_i (out_fifo_v )
,.data_i (out_fifo_data )
,.v_o (fsb_v_o )
,.data_o(fsb_data_o)
,.yumi_i(fsb_yumi_i)
);
// these are channels coming in from nasti slave
// we need to multiplex them onto the FSB
// interconnect. what's more important, read
// responses or write responses?
assign out_fifo_data = ring_data_out;
always @(*)
begin
out_fifo_v = nasti_read_data_ch_i.v
| nasti_write_resp_ch_i.v;
ring_data_out.data = nasti_read_data_ch_i.data;
ring_data_out.cmd = 1'b0;
// per AXI4 spec, valid must be continuously asserted
// once first asserted
// but not so for ready signal
nasti_read_data_ch_ready_o = 1'b0;
nasti_write_resp_ch_ready_o = 1'b0;
if (nasti_read_data_ch_i.v)
begin : rd
ring_data_out.opcode[6] = 1'b1;
ring_data_out.opcode[5] = nasti_read_data_ch_i.last;
ring_data_out.opcode[4:0] = nasti_read_data_ch_i.id;
nasti_read_data_ch_ready_o = out_fifo_ready;
end
else
begin : wr
ring_data_out.opcode=7'b0001000;
nasti_write_resp_ch_ready_o = out_fifo_ready;
ring_data_out.data[4:0] = nasti_write_resp_ch_i.id;
ring_data_out.data[6:5] = nasti_write_resp_ch_i.resp;
// fixme: where does the ID go?
end
ring_data_out.srcid = 4'b0; // fixme
// we have a hardcoded destid_p, which is okay
// because this thing will be in FPGA
ring_data_out.destid = destid_p ;
end // always @ (*)
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:39:56 02/27/2014
// Design Name:
// Module Name: seven_seg_dev
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_seg (
clk,
clr,
disp_num,
Scanning,
SW,
AN,
SEGMENT
);
input wire clk, clr;
input wire [ 1: 0] Scanning;
input wire [ 1: 0] SW;
input wire [31: 0] disp_num;
output reg [ 3: 0] AN;
output wire [ 7: 0] SEGMENT;
reg [ 3: 0] digit = 4'h0;
reg [ 7: 0] temp_seg = 8'h0,
digit_seg = 8'h0;
wire [15: 0] disp_current;
assign SEGMENT = SW[0] ? digit_seg : temp_seg; // 0: Pic mode, 1: Text mode
assign disp_current = SW[1] ? disp_num[31:16] : disp_num[15:0]; // 0: Low, 1: High
// 7-Seg docode
always @(posedge clk)begin
case (digit)
4'h0: digit_seg = 8'b10000001;
4'h1: digit_seg = 8'b11001111;
4'h2: digit_seg = 8'b10010010;
4'h3: digit_seg = 8'b10000110;
4'h4: digit_seg = 8'b11001100;
4'h5: digit_seg = 8'b10100100;
4'h6: digit_seg = 8'b10100000;
4'h7: digit_seg = 8'b10001111;
4'h8: digit_seg = 8'b10000000;
4'h9: digit_seg = 8'b10000100;
4'hA: digit_seg = 8'b10001000;
4'hB: digit_seg = 8'b11100000;
4'hC: digit_seg = 8'b10110001;
4'hD: digit_seg = 8'b11000010;
4'hE: digit_seg = 8'b10110000;
4'hF: digit_seg = 8'b10111000;
default: digit_seg = 8'b00000000;
endcase
end
always @(posedge clk)begin
case (Scanning) // temp_seg for Pic mode
0: begin // disp_num[ 7: 0]
digit = disp_current[ 3: 0]; // TextMode: D[ 3: 0] or D[19:16]
temp_seg = { disp_num[24], disp_num[ 0], disp_num[ 4], disp_num[16],
disp_num[25], disp_num[17], disp_num[ 5], disp_num[12]};
AN = 4'b1110;
end
1: begin // disp_num[15:8]
digit = disp_current[ 7: 4]; // TextMode: D[ 7: 4] or D[23:20]
temp_seg = { disp_num[26], disp_num[ 1], disp_num[ 6], disp_num[18],
disp_num[27], disp_num[19], disp_num[ 7], disp_num[13]};
AN = 4'b1101;
end
2: begin // disp_num[23:16]
digit = disp_current[11: 8]; // TextMode: D[11: 8] or D[27:24]
temp_seg = { disp_num[28], disp_num[ 2], disp_num[ 8], disp_num[20],
disp_num[29], disp_num[21], disp_num[ 9], disp_num[14]};
AN = 4'b1011;
end
3: begin // disp_num[31:24]
digit = disp_current[15:12]; // TextMode: D[15:2] or D[31:28]
temp_seg = { disp_num[30], disp_num[ 3], disp_num[10], disp_num[22],
disp_num[31], disp_num[23], disp_num[11], disp_num[15]};
AN = 4'b0111;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_BLACKBOX_V
`define SKY130_FD_SC_HD__PROBE_P_BLACKBOX_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_BLACKBOX_V
|
//caution do not edit this file manually it is a template in tenjin format
`define Buff_size 32
////////////////////////////////////////////
module top(clk,rst_n,rs232_rx, BusA, led);
///////////////////////////////////////////
input clk; // 50MHz
input rst_n; //reset, neg edge.
input rs232_rx; // RS232 rec
//output rs232_tx; // RS232 transfer
/////////////////////////////////////////
inout [84:82] BusA;
////////////////////////////////////////
output led; // debug led
// state control
parameter IDLE = 3'b000;
parameter S1 = 3'b001;
parameter WAIT = 3'b010;
parameter SAVE = 3'b100;
// commond reg
parameter A=8'h41 ;
parameter B=8'h42 ;
parameter C=8'h43 ;
parameter D=8'h44 ;
parameter E=8'h45 ;
parameter F=8'h46 ;
parameter G=8'h47 ;
parameter H=8'h48 ;
parameter I=8'h49 ;
parameter J=8'h4a ;
parameter K=8'h4b ;
parameter L=8'h4c ;
parameter M=8'h4d ;
parameter N=8'h4e ;
parameter O=8'h4f ;
parameter P=8'h50 ;
parameter Q=8'h51 ;
parameter R=8'h52 ;
parameter S=8'h53 ;
parameter T=8'h54 ;
parameter U=8'h55 ;
parameter V=8'h56 ;
parameter W=8'h57 ;
parameter X=8'h58 ;
parameter Y=8'h59 ;
parameter Z=8'h5a ;
parameter Z0=8'h30 ;
parameter I1=8'h31 ;
parameter II=8'h32 ;
parameter III=8'h33 ;
parameter IV=8'h34 ;
parameter V5=8'h35 ;
parameter VI=8'h36 ;
parameter VII=8'h37 ;
parameter VIII=8'h38 ;
parameter VIIII=8'h39 ;
//definition of inputs/outputs
wire test;
wire Flag; // signal the uart has data
wire rs232_rx;
wire clk,rst_n;
wire bps_start; // start receive
wire bps_start_t; // start tranmit
wire clk_bps; // uart bps
wire clk_bps_t; // uart bps
wire[7:0] rx_data; // receive data to parser
wire rx_int; // receive interrupt
wire rx_error;
wire tx_error;
wire rx_complete;
wire tx_complete;
wire[7:0] tx_data;
wire rs232_tx;
wire scl_rd;
wire rd_receive_status;
////////////////////////////////////////////////////////////////////////////////////////////////
//debug led
reg led;
reg cmd_red;
// settings for log register
reg [`Buff_size-1:0] Buff_temp;
reg [`Buff_size-9:0] Rx_cmd;
reg [2:0] Current, Next;
reg Flag_temp;
//build in module enable
reg linkBIM;
reg capture_rst;
reg linkUART;
reg linkIRR;
reg RD_EN;
reg WR_EN;
reg i2c_rd_rst;
reg linkIRW;
assign BusA[82] = linkIRR ? scl_rd : 1'bz;
`define sda BusA[84]
assign BusA[82] = linkIRW ? scl_rd : 1'bz;
speed_select speed_select( .clk(clk), //baudrate selection
.rst_n(rst_n),
.rx_enable(bps_start),
.tx_enable(bps_start_t),
.buad_clk_rx(clk_bps),
.buad_clk_tx(clk_bps_t)
);
my_uart_rx my_uart_rx( .rst_n(rst_n),
.baud_clk(clk_bps),
.uart_rx(rs232_rx),
.rx_data(rx_data),
.rx_enable(bps_start),
.rx_complete(rx_complete),
.rx_error(rx_error)
);
my_uart_tx my_uart_tx( .rst_n(capture_rst),
.baud_clk(clk_bps_t),
.tx_start(led_tx_start & button_tx_start),
.tx_data(tx_data),
.tx_enable(bps_start_t),
.tx_complete(tx_complete),
.uart_tx(rs232_tx)
);
I2C_MASTER_reduced I2C_MASTER_reduced_instance(
.clk(clk),
.rst_n(i2c_rd_rst),
.sda(`sda),
.scl(scl_rd),
.RD_EN(RD_EN),
.WR_EN(WR_EN),
.receive_status(rd_receive_status)
);
/////////////////////////////////////////////////////////////////////////////////////////////////////
reg flag_reg;
always @ (negedge bps_start or negedge rst_n)
begin
if (!rst_n)
flag_reg <= 1'b0;
else if (!bps_start)
flag_reg <= ~flag_reg;
end
assign Flag = flag_reg;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
Current <= IDLE;
else
Current <= Next;
end
// the state machine for receive data bytes
always @ (*)
begin
Next = IDLE;
case (Current)
IDLE:
if (rx_data == 8'h24) //$
Next = S1;
else
Next = IDLE;
S1:
if (Flag_temp != Flag)
begin
if (rx_data != 8'h0d) //\n
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
WAIT:
if (Flag_temp!=Flag)
begin
if (rx_data != 8'h0d)
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
default: Next = IDLE;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
Flag_temp <= 1'b0;
end
else
begin
Flag_temp <= Flag;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
Buff_temp <= `Buff_size'b0;
Rx_cmd <= `Buff_size'b0;
cmd_red <= 1'b0;
end
else
begin
case (Current)
IDLE:
begin
Buff_temp <= `Buff_size'b0;
end
S1:
begin
cmd_red <= 1'b1;
Buff_temp <= {{Buff_temp[`Buff_size - 9 : 0]}, rx_data};
end
WAIT:
begin
Buff_temp <= Buff_temp;
end
SAVE:
begin
Rx_cmd <= Buff_temp[`Buff_size - 9 : 0];
Buff_temp <= `Buff_size'b0;
cmd_red <= 1'b0;
end
default:
begin
end
endcase
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//////////////////add link here////////////////
linkIRR <= 1'b0;
linkIRW <= 1'b0;
///////////////////////////////////////////////
led <= 1'b0; // for debug led
linkBIM <= 1'b1;
end
else if(cmd_red) begin
i2c_rd_rst <= 1'b0;
RD_EN <= 1'b0;
WR_EN <= 1'b0;
linkIRR <= 1'b0;
linkIRW <= 1'b0;
led <= 1'b0;
capture_rst <= 1'b0;
end
else
begin
case(Rx_cmd)
///////////////////add case here/////////////
{I,R, R}: //{C,M,D}
begin
linkIRR <= 1'b1;
i2c_rd_rst <= 1'b1;
RD_EN <= 1'b1;
WR_EN <= 1'b0;
led <= 1'b1;
end
{I,R, W}: //{C,M,D}
begin
linkIRW <= 1'b1;
i2c_rd_rst <= 1'b1;
RD_EN <= 1'b0;
WR_EN <= 1'b1;
led <= 1'b1;
end
/////////////////////////////////////////////
{R,S,T}: //RESET
begin
i2c_rd_rst <= 1'b0;
RD_EN <= 1'b0;
WR_EN <= 1'b0;
linkIRR <= 1'b0;
linkIRW <= 1'b0;
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
default:
begin
i2c_rd_rst <= 1'b0;
RD_EN <= 1'b0;
WR_EN <= 1'b0;
linkIRR <= 1'b0;
linkIRW <= 1'b0;
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
endcase
end
end
/////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> char S[1000000 + 5], T[1000000 + 5]; int c[1000000 + 5][26], l[1000000 + 5], f[1000000 + 5], tn, df[1000000 + 5], ff[1000000 + 5], s[1000000 + 5], F[1000000 + 5]; int main() { int n, i, j, x; scanf( %s , S + 1); n = strlen(S + 1); T[0] = 255; for (i = 1; i <= n / 2; ++i) T[2 * i - 1] = S[i] - a , T[2 * i] = S[n - i + 1] - a ; f[0] = 1; l[++tn] = -1; for (F[0] = i = x = 1; i <= n; ++i) { while (T[i] != T[i - l[x] - 1]) x = f[x]; if (!c[x][T[i]]) { for (j = f[x]; T[i - l[j] - 1] != T[i]; j = f[j]) ; f[++tn] = c[j][T[i]]; l[c[x][T[i]] = tn] = l[x] + 2; df[tn] = l[tn] - l[f[tn]]; ff[tn] = df[tn] == df[f[tn]] ? ff[f[tn]] : tn; } x = c[x][T[i]]; for (j = x; j; j = f[ff[j]]) { s[j] = F[i - l[ff[j]]]; if (ff[j] != j) s[j] = (s[j] + s[f[j]]) % 1000000007; if (~i & 1) F[i] = (F[i] + s[j]) % 1000000007; } } printf( %d , F[n]); }
|
#include <bits/stdc++.h> using namespace std; int len; char s[109]; int main() { cin >> len; cin >> s; int interval = 0; for (int i = 0; i < len; i += interval) { cout << s[i]; interval++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; long long a[n], b[n]; long long sum = 0, tum = 0, cnt = 0, aod = 0, aev = 0, bod = 0, bev = 0; for (long long i = 0; i < n; i++) { cin >> a[i] >> b[i]; if (a[i] % 2 == 0) aev++; if (a[i] % 2 == 1) aod++; if (b[i] % 2 == 0) bev++; if (b[i] % 2 == 1) bod++; sum += a[i]; tum += b[i]; } if (sum % 2 == 0 and tum % 2 == 0) { cout << 0; return; } else if (sum % 2 == 1 and tum % 2 == 1) { for (long long i = 0; i < n; i++) { if ((a[i] % 2 == 1 and b[i] % 2 == 0) or (b[i] % 2 == 1 and a[i] % 2 == 0)) { cout << 1; return; } } cout << -1; } else cout << -1; } int32_t main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; const int mod = 1e9 + 7; const int maxn = 2e6 + 100; const int maxm = 2e6 + 100; const int inf = 0x3f3f3f3f; const double pi = acos(-1.0); int t; pair<long long, long long> a[maxn]; long long s; int n; int vis[maxn]; bool cmp2(pair<long long, long long> a, pair<long long, long long> b) { return a.second < b.second; } vector<long long> mm, rr, lll; int ck(long long x) { int L = 0, R = 0, M = 0; lll.clear(); rr.clear(); mm.clear(); for (int i = 1; i <= n; i++) { if (a[i].first <= x && a[i].second >= x) { mm.push_back(a[i].first); M++; continue; } if (a[i].first > x) { R++; rr.push_back(a[i].first); } if (a[i].second < x) { L++; lll.push_back(a[i].first); } } if (L > n / 2) return false; long long res = 0; sort(mm.begin(), mm.end()); if (L < n / 2) { int to = M; for (int i = 0; i < to; i++) { lll.push_back(mm[i]); L++; M--; if (L == n / 2) break; } } if (R < n / 2 + 1) { if (R + M != n / 2 + 1) return false; res += 1ll * M * x; } for (int i = 0; i < (int)lll.size(); i++) { res += lll[i]; } for (int i = 0; i < (int)rr.size(); i++) { res += max(rr[i], x); } return res <= s; } int main() { scanf( %d , &t); while (t--) { long long mx = 0; scanf( %d %lld , &n, &s); for (int i = 1; i <= n; i++) { scanf( %lld %lld , &a[i].first, &a[i].second); mx = max(mx, a[i].second); } long long ans = 0; sort(a + 1, a + 1 + n); long long l = a[n / 2 + 1].first; sort(a + 1, a + 1 + n, cmp2); long long r = a[n / 2 + 1].second; while (l <= r) { long long mid = l + r >> 1; if (ck(mid)) { l = mid + 1; ans = mid; } else r = mid - 1; } printf( %lld n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_asinpi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arcsinpi_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; int orig[n]; int product = 1; int counter = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; orig[i] = arr[i]; if (arr[i] >= 0) { arr[i] = -arr[i] - 1; } if (arr[i] < 0) { counter++; } } if (counter % 2 == 0) { for (int i = 0; i < n; i++) { cout << arr[i] << ; } } else { int maxAbsVal = 0; int maxIndex = 0; for (int i = 0; i < n; i++) { if (abs(arr[i]) >= maxAbsVal) { maxAbsVal = abs(arr[i]); maxIndex = i; } } if (arr[maxIndex] == orig[maxIndex]) { arr[maxIndex] = -arr[maxIndex] - 1; } else { arr[maxIndex] = orig[maxIndex]; } for (int i = 0; i < n; i++) { cout << arr[i] << ; } } }
|
// file: Clock35MHz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____35.000______0.000______50.0______771.429____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock35MHz,clk_wiz_v3_6,{component_name=Clock35MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock35MHz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (7),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; bool f = 1; char s = getchar(); while ((s < 0 || s > 9 ) && s > 0) { if (s == - ) f ^= 1; s = getchar(); } while (s >= 0 && s <= 9 ) x = (x << 1) + (x << 3) + s - 0 , s = getchar(); return f ? x : -x; } int n, m, ans[500005]; int IN, dfn[500005], low[500005], bl[500005], tot; stack<int> st; int d1[500005], sd[500005], d2[500005], ccg[500005]; vector<int> G[500005], cl[500005]; inline void dfs0(int x, int fa) { dfn[x] = low[x] = ++IN, st.push(x); for (unsigned i = 0; i < G[x].size(); i++) { int v = G[x][i]; if (v == fa) continue; if (!dfn[v]) dfs0(v, x), low[x] = min(low[x], low[v]); else low[x] = min(low[x], dfn[v]); } if (low[x] == dfn[x]) { tot++; while (!st.empty() && dfn[st.top()] >= dfn[x]) bl[st.top()] = tot, cl[tot].push_back(st.top()), st.pop(); } } queue<int> q; int db[500005]; inline void bfs1(int x) { for (int i = 1; i <= n; i++) db[i] = -1; db[x] = 0, q.push(x); while (!q.empty()) { int u = q.front(); q.pop(); for (unsigned i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (db[v] < 0) db[v] = db[u] + 1, q.push(v); } } } inline void dfs1(int x) { d1[x] = 1; for (unsigned i = 0; i < G[x].size(); i++) { int v = G[x][i]; if (db[v] == db[x] + 1) { if (!d1[v]) dfs1(v); d1[x] = max(d1[x], d1[v] + 1); } } } struct node { int x, y; node() {} node(int X, int Y) { x = X, y = Y; } }; int dq[500005 << 1], hd, tl; bool vis[500005]; inline void dfs2(int x) { vis[x] = 1; int len = cl[x].size(), cj = len >> 1; for (int id = 0; id < len; id++) { int u = cl[x][id]; sd[u] = ans[u] = 1; for (unsigned i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (bl[u] != bl[v]) sd[u] = max(sd[u], d1[v] + 1); } } hd = tl = 0; for (int i = cj, lim = len << 1; i < lim; i++) { int u = cl[x][i % len], p; while (hd < tl && i - dq[hd] > cj) hd++; if (hd < tl) p = dq[hd], ans[u] = max(ans[u], i - p + sd[cl[x][p % len]]); while (hd < tl && ((p = dq[tl - 1]) || 1) && i - p + sd[cl[x][p % len]] < sd[u]) tl--; dq[tl++] = i; } hd = tl = 0; for (int i = cj, g = (len << 1) - 1; i <= g; i++) { int u = cl[x][(g - i) % len], p; while (hd < tl && i - dq[hd] > cj) hd++; if (hd < tl) p = dq[hd], ans[u] = max(ans[u], i - p + sd[cl[x][(g - p) % len]]); while (hd < tl && ((p = dq[tl - 1]) || 1) && i - p + sd[cl[x][(g - p) % len]] < sd[u]) tl--; dq[tl++] = i; } for (int id = 0; id < len; id++) { int u = cl[x][id]; hd = tl = 0; for (unsigned i = 0; i < G[u].size(); i++) if (bl[G[u][i]] != x) { int v = G[u][i]; while (hd < tl && d1[dq[tl - 1]] < d1[v]) tl--; dq[tl++] = v; } for (unsigned i = 0; i < G[u].size(); i++) if (bl[G[u][i]] != x) { int v = G[u][i], cg = ans[u]; if (hd < tl && dq[hd] == v) hd++; if (hd < tl) cg = max(cg, d1[dq[hd]] + 1); while (hd < tl && d1[dq[tl - 1]] < d1[v]) tl--; dq[tl++] = v; if (!vis[bl[v]]) ccg[v] = cg; } for (unsigned i = 0; i < G[u].size(); i++) if (bl[G[u][i]] != x) { int v = G[u][i]; if (!vis[bl[v]]) swap(d1[u], ccg[v]), dfs2(bl[v]), swap(d1[u], ccg[v]); } } } signed main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int u = read(), v = read(); G[u].push_back(v), G[v].push_back(u); } dfs0(1, 0); bfs1(1), dfs1(1); dfs2(bl[1]); for (int i = 1; i <= n; i++) printf( %d , max(ans[i], sd[i]) - 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200005], c[200005], b[200005], ans[200005]; struct node { int x, y; } e[200005]; int main() { int n, m, Max = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= m; i++) { scanf( %d%d , &e[i].x, &e[i].y); } int p = 0, cnt = 1; for (int i = m; i >= 1; i--) { if (e[i].y > p) { c[cnt] = e[i].x; b[cnt++] = e[i].y; p = e[i].y; } } sort(a + 1, a + b[cnt - 1] + 1); int l = 1, r = n, f = 1; p = 0; for (; r > b[cnt - 1]; r--) ans[p++] = a[r]; for (int i = cnt - 1; i > 0; i--) { int x = b[i] - b[i - 1]; if (f == c[i]) { while (x--) { ans[p++] = a[r--]; } } else { while (x--) { ans[p++] = a[l++]; } } } for (int i = n - 1; i >= 0; i--) { printf( %d , ans[i]); } printf( n ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_PP_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; string ToStr(char k) { stringstream ss; ss << k; return ss.str(); } bool check(string str) { int n = (int)str.length(); for (int i = 0; i < n / 2; i++) { if (str[i] != str[n - i - 1]) return false; } return true; } int main() { string s; cin >> s; for (int i = 0; i <= (int)s.length(); i++) { for (int j = 0; j < 26; j++) { string tmp = s; tmp.insert(i, ToStr( a + j)); if (check(tmp)) { cout << tmp << endl; return 0; } } } cout << NA << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int N = 2e5 + 10; int T, n, a[N], vis[N], d[N], mi, mx; signed main() { cin >> T; while (T--) { cin >> n; mi = 0x3f3f3f3f, mx = -999; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), vis[a[i]] = i; for (int i = 1; i <= n; i++) { mi = min(mi, vis[i]), mx = max(mx, vis[i]); if (mx - mi == i - 1) putchar( 1 ); else putchar( 0 ); } puts( ); } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_complete
*/
module test_ip_complete;
// Parameters
parameter ARP_CACHE_ADDR_WIDTH = 2;
parameter ARP_REQUEST_RETRY_COUNT = 4;
parameter ARP_REQUEST_RETRY_INTERVAL = 150;
parameter ARP_REQUEST_TIMEOUT = 400;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [7:0] s_eth_payload_axis_tdata = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg arp_response_valid = 0;
reg arp_response_error = 0;
reg [47:0] arp_response_mac = 0;
reg s_ip_hdr_valid = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [7:0] s_ip_payload_axis_tdata = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [31:0] gateway_ip = 0;
reg [31:0] subnet_mask = 0;
reg clear_arp_cache = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [7:0] m_eth_payload_axis_tdata;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire arp_request_valid;
wire [31:0] arp_request_ip;
wire m_ip_hdr_valid;
wire [47:0] m_ip_eth_dest_mac;
wire [47:0] m_ip_eth_src_mac;
wire [15:0] m_ip_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [7:0] m_ip_payload_axis_tdata;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire m_ip_payload_axis_tuser;
wire rx_busy;
wire tx_busy;
wire rx_error_header_early_termination;
wire rx_error_payload_early_termination;
wire rx_error_invalid_header;
wire rx_error_invalid_checksum;
wire tx_error_payload_early_termination;
wire tx_error_arp_failed;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
s_ip_hdr_valid,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
m_ip_hdr_ready,
m_ip_payload_axis_tready,
local_mac,
local_ip,
gateway_ip,
subnet_mask,
clear_arp_cache
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
m_ip_hdr_valid,
m_ip_eth_dest_mac,
m_ip_eth_src_mac,
m_ip_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tuser,
rx_busy,
tx_busy,
rx_error_header_early_termination,
rx_error_payload_early_termination,
rx_error_invalid_header,
rx_error_invalid_checksum,
tx_error_payload_early_termination,
tx_error_arp_failed
);
// dump file
$dumpfile("test_ip_complete.lxt");
$dumpvars(0, test_ip_complete);
end
ip_complete #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.rx_busy(rx_busy),
.tx_busy(tx_busy),
.rx_error_header_early_termination(rx_error_header_early_termination),
.rx_error_payload_early_termination(rx_error_payload_early_termination),
.rx_error_invalid_header(rx_error_invalid_header),
.rx_error_invalid_checksum(rx_error_invalid_checksum),
.tx_error_payload_early_termination(tx_error_payload_early_termination),
.tx_error_arp_failed(tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
endmodule
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
// Copyright 2013 David Turnbull AE9RB
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 10/21/2012 at 15:53
// Component: SyncSOF
module SyncSOF (
input clock,
input sod,
input sof
);
//`#start body` -- edit after this line, do not edit this line
// This will sync the PSoC PLL to 38.864 MHz with a digital lock using
// the 1kHz from USB sof (start-of-frame). Counting begins at the start
// of buffer 0 obtained from the DMA communicating with the DelSigs.
// We want exactly exactly 36864 cycles per 1ms USB frame.
wire [6:0] clockcount1;
cy_psoc3_count7 #(.cy_period(7'b0111111))
Counter0 (
/* input */ .clock(clock),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount1),
/* output */ .tc(clocktc1)
);
wire [6:0] clockcount2;
cy_psoc3_count7 #(.cy_period(7'b0111111))
Counter1 (
/* input */ .clock(clocktc1),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount2),
/* output */ .tc(clocktc2)
);
wire [6:0] clockcount3;
cy_psoc3_count7 #(.cy_period(7'b0001000))
Counter2 (
/* input */ .clock(clocktc2),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount3),
/* output */ .tc()
);
// Report to the CPU where we are in the frame
reg [7:0] frame_pos_hi;
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
FRAME_POS_HI ( .status( frame_pos_hi ));
reg frame_pos_ready;
reg [6:0] frame_pos_lo;
cy_psoc3_status #(.cy_md_select(8'h01), .cy_force_order(`TRUE))
FRAME_POS_LO (
.status( {frame_pos_lo, frame_pos_ready} ),
.clock(clock)
);
// Which buffer to use for USB DMA.
reg [1:0] buffer;
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
BUFFER ( .status({6'b0, buffer}) );
reg sof_sync;
always @(posedge sof or posedge sod)
begin
if (sod) buffer <= 1;
else
begin
sof_sync <= ~sof_sync;
if (buffer == 2 ) buffer <= 0;
else buffer <= buffer + 1;
end
end
reg sof_prev;
always @(posedge clock)
begin
if (sof_sync != sof_prev)
begin
sof_prev <= sof_sync;
frame_pos_hi = {clockcount3[3:0], clockcount2[5:2]};
frame_pos_lo = {clockcount2[1:0], clockcount1[5:1]};
frame_pos_ready = 1;
end
else frame_pos_ready = 0;
end
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_sync_ref_0_0 -prefix
// system_vga_sync_ref_0_0_ system_vga_sync_ref_1_0_stub.v
// Design : system_vga_sync_ref_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_0_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
module dut (output reg[31:0] size,
output reg signed [31:0] ival,
output reg [31:0] hval);
parameter string foo = "1234";
string tmp;
real rval;
initial begin
size = foo.len();
ival = foo.atoi();
hval = foo.atohex();
rval = foo.atoreal();
tmp = foo;
$display("foo=%0s, tmp=%0s", foo, tmp);
if (tmp != foo) begin
$display("FAILED");
$finish;
end
$display("rval=%f", rval);
if (rval != ival) begin
$display("FAILED -- rval=%f, ival=%0d", rval, ival);
$finish;
end
end
endmodule // dut
module main;
wire [31:0] dut0_size, dut1_size, dut2_size;
wire signed [31:0] dut0_ival, dut1_ival, dut2_ival;
wire unsigned [31:0] dut0_hval, dut1_hval, dut2_hval;
// Instantate module with string parameter, use default value.
dut dut0 (dut0_size, dut0_ival, dut0_hval);
// Instantate module with string parameter, use override value.
dut #(.foo("12345")) dut1 (dut1_size, dut1_ival, dut1_hval);
// Instantate module with string parameter, use defparam value.
defparam dut2.foo = "123456";
dut dut2 (dut2_size, dut2_ival, dut2_hval);
initial begin
#100 ;
$display("dut0_size=%0d", dut0_size);
if (dut0_size !== 4) begin
$display("FAILED");
$finish;
end
$display("dut1_size=%0d", dut1_size);
if (dut1_size !== 5) begin
$display("FAILED");
$finish;
end
$display("dut2_size=%0d", dut2_size);
if (dut2_size !== 6) begin
$display("FAILED");
$finish;
end
$display("dut0_ival=%0d", dut0_ival);
if (dut0_ival !== 1234) begin
$display("FAILED");
$finish;
end
$display("dut1_ival=%0d", dut1_ival);
if (dut1_ival !== 12345) begin
$display("FAILED");
$finish;
end
$display("dut2_ival=%0d", dut2_ival);
if (dut2_ival !== 123456) begin
$display("FAILED");
$finish;
end
$display("dut0_hval=%0h", dut0_hval);
if (dut0_hval !== 32'h1234) begin
$display("FAILED");
$finish;
end
$display("dut1_hval=%0h", dut1_hval);
if (dut1_hval !== 32'h12345) begin
$display("FAILED");
$finish;
end
$display("dut2_hval=%0h", dut2_hval);
if (dut2_hval !== 32'h123456) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_2_V
`define SKY130_FD_SC_LS__SDFBBN_2_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_2_V
|
`timescale 1ns/1ps
`include "../global.v"
module FPU_top_exception_tb();
reg clk, reset;
reg [3:0] opCode;
reg [1:0] roundingMode;
reg [31:0] A;
reg [31:0] B;
reg [31:0] ER; //expected result
wire resultReady;
wire [31:0] result;
wire invalidOperation, divisionByZero, overflow, underflow, inexact;
reg [31:0] PINF;
reg [31:0] NINF;
reg [31:0] NAN;
reg [31:0] PZERO;
reg [31:0] NZERO;
//instantiate DUT
FPU_top DUT(clk, reset, opCode, roundingMode, A, B, resultReady, result,
invalidOperation, divisionByZero, overflow, underflow, inexact);
//clock
parameter HCP = 10;
initial forever begin
#HCP clk = ~clk;
end
initial begin
PINF = 32'h7F800000;
NINF = 32'hFF800000;
NAN = 32'h7FC00000;
PZERO = 32'h00000000;
NZERO = 32'h80000000;
clk = 1'b0;
reset = 1'b1;
roundingMode = `ROUNDING_MODE_TRUNCATE;
$display("---------------- Exception testbench ----------------");
$display("\tTesting Invalid Operations.....");
$display("\t\t 0*Inf"); runSingleTest(`FPU_INSTR_MUL, PZERO, PINF, NAN);
$display("\t\t Inf*0"); runSingleTest(`FPU_INSTR_MUL, PINF, PZERO, NAN);
$display("\t\t +Inf + -Inf"); runSingleTest(`FPU_INSTR_ADD, PINF, NINF, NAN);
$display("\t\t -Inf + +Inf"); runSingleTest(`FPU_INSTR_ADD, NINF, PINF, NAN);
$display("\t\t +Inf - +Inf"); runSingleTest(`FPU_INSTR_SUB, PINF, PINF, NAN);
$display("\t\t -Inf - -Inf"); runSingleTest(`FPU_INSTR_SUB, NINF, NINF, NAN);
$display("\t\t 0 / 0"); runSingleTest(`FPU_INSTR_DIV, PZERO, PZERO, NAN);
$display("\t\t Inf / Inf"); runSingleTest(`FPU_INSTR_DIV, PINF, PINF, NAN);
$display("----------------");
$display("\tTesting Division-by-Zero.....");
$display("\t\t 5.0f / +0"); runSingleTest(`FPU_INSTR_DIV, 32'h40A00000, PZERO, PINF);
$display("\t\t -5.0f / +0"); runSingleTest(`FPU_INSTR_DIV, 32'hC0A00000, PZERO, NINF);
$display("\t\t 5.0f / -0"); runSingleTest(`FPU_INSTR_DIV, 32'h40A00000, NZERO, NINF);
$display("\t\t -5.0f / -0"); runSingleTest(`FPU_INSTR_DIV, 32'hC0A00000, NZERO, PINF);
$display("----------------");
#20
$finish;
end
task runSingleTest;
input [3:0] operation;
input [31:0] A_in, B_in, ER_in;
begin
opCode = operation;
A = A_in;
B = B_in;
ER = ER_in;
#(2*HCP) reset = 1'b0;
@(posedge resultReady) #5;
if (ER !== result) begin
$display("Wrong result!");
$display("A: %b\t%x\t%b\n", A[31], A[30:23], A[22:0]);
$display("B: %b\t%x\t%b\n", B[31], B[30:23], B[22:0]);
$display("ER: %b\t%x\t%b (%x)\n", ER[31], ER[30:23], ER[22:0], ER);
$display("R: %b\t%x\t%b (%x)\n", result[31], result[30:23], result[22:0], result);
end else begin
/*$display("Vector %d: Correct result", cnt);
$display("A: %b\t%x\t%b\n", A[31], A[30:23], A[22:0]);
$display("B: %b\t%x\t%b\n", B[31], B[30:23], B[22:0]);
$display("ER: %b\t%x\t%b\n", ER[31], ER[30:23], ER[22:0]);
$display("R: %b\t%x\t%b\n", result[31], result[30:23], result[22:0]);*/
end
reset = 1'b1;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long HASH = 1e16 + 7; const long long INF = 1e9; long long tavan(long long a, long long b) { return b ? (tavan(a * a, b >> 1) * (b & 1 ? a : 1)) : 1; } long long gcd(long long a, long long b) { return (a < b) ? gcd(b, a) : ((a % b == 0) ? b : gcd(b, a % b)); } bool isprime(long long x) { for (long long i = 2; i <= sqrt(x); i++) if (!(x % i)) return false; return true; } ifstream fin( input.txt ); ofstream fout( output.txt ); long long n, a[1100]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int t = 0; t < n + 1000; t++) { bool ex = 1; for (int i = 0; i < n; i++) { if (i % 2 == 0) a[i]++; else a[i]--; if (a[i] == n) a[i] = 0; if (a[i] == -1) a[i] = n - 1; if (a[i] != i) ex = 0; } if (ex) { cout << YES ; return 0; } } cout << NO ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlave.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlave (
i2c_address,
clk,
rst,
sda,
scl,
regAddr,
dataIn,
writeEn,
dataOut
);
input [7:1]i2c_address;
input clk;
input rst;
inout sda;
input scl;
output [7:0] regAddr;
input [7:0] dataIn;
output writeEn;
output [7:0] dataOut;
// local wires and regs
reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;
reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;
assign sda = (sdaOut == 1'b0) ? 1'b0 : 1'bz;
assign sdaIn = sda;
// sync rst rsing edge to clk
always @(posedge clk) begin
if (rst == 1'b1)
rstPipe <= 2'b11;
else
rstPipe <= {rstPipe[0], 1'b0};
end
assign rstSyncToClk = rstPipe[1];
// debounce sda and scl
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sdaPipe <= {`DEB_I2C_LEN{1'b1}};
sdaDeb <= 1'b1;
sclPipe <= {`DEB_I2C_LEN{1'b1}};
sclDeb <= 1'b1;
end
else begin
sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sclDeb <= 1'b1;
else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sclDeb <= 1'b0;
if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sdaDeb <= 1'b1;
else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sdaDeb <= 1'b0;
end
end
// delay scl and sda
// sclDelayed is used as a delayed sampling clock
// sdaDelayed is only used for start stop detection
// Because sda hold time from scl falling is 0nS
// sda must be delayed with respect to scl to avoid incorrect
// detection of start/stop at scl falling edge.
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sclDelayed <= {`SCL_DEL_LEN{1'b1}};
sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
end
else begin
sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
end
end
// start stop detection
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
startStopDetState <= `NULL_DET;
startEdgeDet <= 1'b0;
end
else begin
if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startEdgeDet <= 1'b1;
else
startEdgeDet <= 1'b0;
if (clearStartStopDet == 1'b1)
startStopDetState <= `NULL_DET;
else if (sclDeb == 1'b1) begin
if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0)
startStopDetState <= `STOP_DET;
else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startStopDetState <= `START_DET;
end
end
end
serialInterface u_serialInterface (
.i2c_address(i2c_address),
.clk(clk),
.rst(rstSyncToClk | startEdgeDet),
.dataIn(dataIn),
.dataOut(dataOut),
.writeEn(writeEn),
.regAddr(regAddr),
.scl(sclDelayed[`SCL_DEL_LEN-1]),
.sdaIn(sdaDeb),
.sdaOut(sdaOut),
.startStopDetState(startStopDetState),
.clearStartStopDet(clearStartStopDet)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int a[10] = {0}; int n; string d; cin >> n; cin >> d; for (int i = 0; i < d.size(); i++) { if (d[i] == L ) { for (int j = 0; j < 10; j++) { if (a[j] == 0) { a[j] = 1; break; } } } else if (d[i] == R ) { for (int j = 9; j >= 0; j--) { if (a[j] == 0) { a[j] = 1; break; } } } else { a[d[i] - 0 ] = 0; } } for (int i = 0; i < 10; i++) printf( %d , a[i]); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; vector<int> v; struct mmp { int to, next, len; mmp() {} mmp(int a, int b, int c) { to = a, next = b, len = c; } } e[maxn << 1]; int vis[maxn], st, ed, cnt, head[maxn], val[maxn], len; void add(int u, int v, int len) { e[++cnt] = mmp(v, head[u], len); head[u] = cnt; } void add(int x) { for (int i = 0; i < (int)v.size(); i++) { x = min(x, x ^ v[i]); } if (x) v.push_back(x); } void dfs(int x, int now) { vis[x] = 1; for (int i = head[x]; i; i = e[i].next) { int to = e[i].to; if (vis[to]) add(val[to] ^ now ^ e[i].len); else { val[to] = now ^ e[i].len; dfs(to, val[to]); } } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d%d , &st, &ed, &len); add(st, ed, len); add(ed, st, len); } dfs(1, 0); for (int i = 0; (int)i < v.size(); i++) { val[n] = min(val[n], val[n] ^ v[i]); } return 0 * printf( %d , val[n]); }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; bool inBound(int x) { return x >= 0 && x < 30001; } int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); std::cout.tie(0); int n, d; cin >> n >> d; int mx = 30000; vector<int> gems(mx + 1, 0); for (int i = 0; i < n; i++) { int temp; cin >> temp; gems[temp]++; } vector<vector<int> > dp; dp.resize(mx + 1, vector<int>(500, 0)); for (int i = mx; i >= d; i--) { for (int prev = 0; prev < 500; prev++) { dp[i][prev] = gems[i]; int prevJump = d + prev - 250; int nextPos = i + prevJump; int choice1 = (inBound(nextPos - 1) && prev - 1 >= 0 && (prevJump - 1) > 0) ? dp[nextPos - 1][prev - 1] : 0; int choice2 = (inBound(nextPos) && (prevJump) > 0) ? dp[nextPos][prev] : 0; int choice3 = (inBound(nextPos + 1) && prev + 1 < 500 && (prevJump + 1) > 0) ? dp[nextPos + 1][prev + 1] : 0; dp[i][prev] += max(choice1, max(choice2, choice3)); } } cout << dp[d][250] << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_LP_V
`define SKY130_FD_SC_LP__DLRBN_LP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_LP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)3e3 + 5; const long long INF = (long long)1e15; pair<int, long long> dp[MAXN][MAXN]; vector<int> adj[MAXN]; int arr[MAXN]; int sub[MAXN]; int n, m; void dfs(int v, int pr = -1) { fill(dp[v], dp[v] + n + 1, make_pair(-n, -INF)); dp[v][0] = make_pair(0, 0); sub[v] = 1; for (int to : adj[v]) { if (to == pr) { continue; } dfs(to, v); } vector<pair<int, long long> > ndp(n + 5, make_pair(-n, -INF)); for (int to : adj[v]) { if (to == pr) { continue; } for (int i = 0; i <= sub[v] + sub[to] + 3; ++i) { ndp[i] = make_pair(-n, -INF); } for (int i = sub[v]; i >= 0; --i) { for (int j = sub[to]; j >= 0; --j) { if (dp[v][i].second == -INF || dp[to][j].second == -INF || dp[v][i].first < 0 || dp[to][j].first < 0) { continue; } if (dp[to][j].second > 0) { ndp[i + j + 1] = max( ndp[i + j + 1], make_pair(dp[v][i].first + dp[to][j].first + 1, dp[v][i].second)); } else { ndp[i + j + 1] = max(ndp[i + j + 1], make_pair(dp[v][i].first + dp[to][j].first, dp[v][i].second)); } ndp[i + j] = max(ndp[i + j], make_pair(dp[v][i].first + dp[to][j].first, dp[v][i].second + dp[to][j].second)); } } for (int j = 0; j < n; ++j) { dp[v][j] = ndp[j]; } sub[v] += sub[to]; } for (int i = 0; i < n; ++i) { if (dp[v][i].second != -INF) { dp[v][i].second += arr[v]; } } } void solve() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; ++i) { adj[i].clear(); arr[i] = 0; } for (int i = 1, x; i <= n; ++i) { scanf( %d , &x); arr[i] = -x; } for (int i = 1, x; i <= n; ++i) { scanf( %d , &x); arr[i] += x; } for (int i = 1; i < n; ++i) { int u, v; scanf( %d %d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } dfs(1); printf( %d n , dp[1][m - 1].first + (dp[1][m - 1].second > 0)); } int main() { int tt; scanf( %d , &tt); while (tt--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, p, start[390000], fin[390000]; map<pair<int, int>, int> mp; int main() { scanf( %d %d , &n, &p); vector<int> cnt(n, 0); for (int i = 0; i < n; i++) { int x, y; scanf( %d %d , &x, &y); x--; y--; if (x > y) swap(x, y); start[i] = x; fin[i] = y; cnt[x]++; cnt[y]++; mp[make_pair(x, y)]++; } vector<int> cnt2(cnt.begin(), cnt.end()); sort(cnt.begin(), cnt.end()); long long ans = 0; int j = n; for (int i = 0; i < n; i++) { while (j - 1 >= i && cnt[i] + cnt[j - 1] >= p) j--; if (j < i + 1) j = i + 1; ans += n - j; } for (int i = 0; i < n; i++) { if (cnt2[start[i]] + cnt2[fin[i]] < p) continue; if (cnt2[start[i]] + cnt2[fin[i]] - mp[make_pair(start[i], fin[i])] < p) ans--; mp[make_pair(start[i], fin[i])] = 0; } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long cubes[100001], x; long long my_pow(long long x) { return x * x * x; } pair<long long, long long> best; void rec(long long m, long long steps, long long subtracted) { if (m == 0) { best = max(best, make_pair(steps, subtracted)); return; } long long x = 1; while (my_pow(x + 1) <= m) ++x; rec(m - my_pow(x), steps + 1, subtracted + my_pow(x)); if (x - 1 >= 0) rec(my_pow(x) - 1 - my_pow(x - 1), steps + 1, subtracted + my_pow(x - 1)); } int main() { long long m; scanf( %I64d , &m); rec(m, 0, 0); printf( %I64d %I64d , best.first, best.second); return 0; }
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#include <bits/stdc++.h> using namespace std; enum STATE { IN, OUT, BOUNDRY }; const double PI = acos(-1.0); void fast_in_out() { std::ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); } int dx[] = {0, 0, -1, 1, -1, 1, -1, 1, 0}; int dy[] = {-1, 1, 0, 0, -1, -1, 1, 1, 0}; int lx[] = {2, 2, -1, 1, -2, -2, -1, 1}; int ly[] = {-1, 1, 2, 2, 1, -1, -2, -2}; const int N = 19, M = 200 + 10, mod = 998244353; const double eps = 1e-9; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int n; double ar[N][N]; double dp[N][(1 << N)]; int main() { fast_in_out(); cout << fixed << setprecision(9); cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cin >> ar[i][j]; dp[i][1 << i] = 1; } for (int mask = 3; mask < (1 << n); mask++) { int cnt = __builtin_popcount(mask); if (cnt == 1) continue; cnt = cnt * (cnt - 1) / 2; double lose[N]{0}; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n && (mask & (1 << i)); j++) { if (mask & (1 << j)) { lose[j] += ar[i][j] / cnt; lose[i] += ar[j][i] / cnt; } } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n && (mask & (1 << i)); j++) { if (mask & (1 << j)) { dp[j][mask] += dp[j][mask - (1 << i)] * lose[i]; dp[i][mask] += dp[i][mask - (1 << j)] * lose[j]; } } } } for (int i = 0; i < n; i++) cout << dp[i][(1 << n) - 1] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long INF = 1e15; using Graph = vector<vector<long long>>; signed main() { long long T; cin >> T; for (long long t = 0; t < T; t++) { long long N; cin >> N; vector<long long> A(N); for (long long i = 0; i < N; i++) cin >> A[i]; sort(A.begin(), A.end()); long long ans = 1000000; for (long long i = 1; i < N; i++) { ans = min(ans, A[i] - A[i - 1]); } cout << ans << endl; } }
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#include <bits/stdc++.h> using namespace std; template <class T> using vec = vector<T>; template <typename Iter> ostream &_IterOutput_(ostream &o, Iter b, Iter e, const string ss = , const string se = ) { o << ss; for (auto it = b; it != e; it++) o << (it == b ? : , ) << *it; return o << se; } template <typename T1, typename T2> ostream &operator<<(ostream &o, const pair<T1, T2> &pair) { return o << ( << pair.first << , << pair.second << ) ; } template <typename T> ostream &operator<<(ostream &o, const vector<T> &vec) { return _IterOutput_(o, begin(vec), end(vec), [ , ] ); } template <typename T> ostream &operator<<(ostream &o, const set<T> &st) { return _IterOutput_(o, begin(st), end(st), { , } ); } template <typename T, size_t N> ostream &operator<<(ostream &o, const array<T, N> &arr) { return _IterOutput_(o, begin(arr), end(arr), | , | ); } template <typename T1, typename T2> ostream &operator<<(ostream &o, const map<T1, T2> &mp) { o << { ; for (auto it = mp.begin(); it != mp.end(); it++) { o << (it == mp.begin() ? : , ) << it->first << : << it->second; } o << } ; return o; } void lucky_test() { std::random_device rd; std::mt19937 gen_(rd()); std::normal_distribution<double> dist_(0.0, 1.0); if (dist_(gen_) >= 4.44444444) { cout << Not lucky << endl; exit(0); } } int N; const int MX = 131072 * 4; const int INF = 1e9; int ZZ = 0; struct Seg { int val[MX]; int nl[MX], nr[MX]; int lz[MX]; void init(int id, int ql, int qr) { nl[id] = ql; nr[id] = qr; val[id] = -INF; if (ql == qr - 1) { return; } int md = (ql + qr) / 2; init(id * 2, ql, md); init(id * 2 + 1, md, qr); } void push(int id) { ZZ++; int l = nl[id], r = nr[id]; int v = lz[id]; lz[id] = 0; if (l == r - 1) { return; } adj(id * 2, v); adj(id * 2 + 1, v); return; } void pull(int id) { ZZ++; int l = nl[id], r = nr[id]; if (l == r - 1) return; val[id] = max(val[id * 2], val[id * 2 + 1]); } void adj(int id, int v) { lz[id] += v; val[id] += v; } void add(int id, int ql, int qr, int v) { push(id); int l = nl[id], r = nr[id]; if (l == ql and r == qr) { adj(id, v); return; } int md = (l + r) / 2; if (qr <= md) add(id * 2, ql, qr, v); else if (ql >= md) add(id * 2 + 1, ql, qr, v); else { add(id * 2, ql, md, v); add(id * 2 + 1, md, qr, v); } pull(id); } int walk(int id) { push(id); if (val[id] < 0) return -1; int l = nl[id], r = nr[id]; if (l == r - 1) { return val[id] >= 0 ? l : -1; } if (val[id * 2 + 1] >= 0) return walk(id * 2 + 1); else return walk(id * 2); } } tree; struct Hao { int val[MX]; int n; void init(int id, int l, int r) { n = r; for (int i = l; i < r; i++) val[i] = -INF; } void add(int id, int l, int r, int v) { for (int i = l; i < r; i++) val[i] += v; } int walk(int id) { for (int i = n - 1; i >= 0; i--) if (val[i] >= 0) return i; return -1; } void dmp() { for (int i = 0; i < n; i++) cout << val[i] << ; cout << endl; } }; int V[MX]; int32_t main() { do { ios_base::sync_with_stdio(0); cin.tie(0); } while (0); cin >> N; tree.init(1, 0, N + 5); for (int i = 0; i < N; i++) { int p, t; cin >> p >> t; if (t == 0) { tree.add(1, 0, p, -1); } else { cin >> V[p]; tree.add(1, p, p + 1, INF); tree.add(1, 0, p, 1); } int pos = tree.walk(1); if (pos == -1) cout << -1 << n ; else cout << V[pos] << n ; } return 0; }
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#include <bits/stdc++.h> #define ed end() #define bg begin() #define mp make_pair #define pb push_back #define vv(T) v(v(T)) #define v(T) vector<T> #define all(x) x.bg,x.ed #define newline puts( ) #define si(x) ((int)x.size()) #define rep(i,n) for(int i=1;i<=n;++i) #define rrep(i,n) for(int i=0;i<n;++i) #define srep(i,s,t) for(int i=s;i<=t;++i) #define drep(i,s,t) for(int i=t;i>=s;--i) #define DEBUG #define d1(x) std::cout << #x = << (x) << std::endl #define d2(x, y) std::cout << #x = << (x) << , #y = << (y) << std::endl #define disp(arry, fr, to) { std::cout << #arry : ; for(int _i = fr; _i <= to; _i++) std::cout << arry[_i] << ; std::cout << std::endl; } using namespace std; typedef long long ll; typedef pair<int,int> pii; const int Maxn = 2e5+10; const int Inf = 0x7f7f7f7f; const ll Inf_ll = 1ll*Inf*Inf; const int Mod = 1e9+7; const double eps = 1e-7; int n, a[Maxn], tol; ll Sum, sum[Maxn], s[Maxn]; int calc(int l, int r, ll x){ // if( l > r ) return 0; int ll = l, rr = r, ans = l-1; while( ll <= rr ) { int mid = (ll+rr) >> 1; if( s[mid] - s[l-1] <= x ) ll = mid+1, ans = mid; else rr = mid-1; } // printf( l = %d, r = %d, x = %lld, ans = %d n , l, r, x, ans-l+1 + (x>=0)); return ans-l+1 + (x>=0); } ll work(){ tol = 0; ll ans = 0, las = 0; for(int i=1;i<=n;i+=2) { s[++tol] = las + a[i]; las += a[i]; } for(int i=1,j=1;i<=n;i+=2,j++) { if( n&1 ) { ll tmp = (Sum-1)/2 - sum[i]; ans += calc(j+1, tol-1, tmp); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]); if( i != 1 ) { ans += calc(j+1, tol-1, tmp+a[1]); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]+a[1]); } } else { ll tmp = (Sum-1)/2 - sum[i]; ans += calc(j+1, tol, tmp); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]); if( i != 1 ) { ans += calc(j+1, tol, tmp+a[1]); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]+a[1]); } } // d2(i, ans); } las = tol = 0; for(int i=2;i<=n;i+=2) { s[++tol] = las + a[i]; las += a[i]; } for(int i=2,j=1;i<=n;i+=2,j++) { if( n&1 ) { ll tmp = (Sum-1)/2 - sum[i]; ans += calc(j+1, tol, tmp); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]); if( i != 1 ) { ans += calc(j+1, tol, tmp+a[1]); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]+a[1]); } } else { ll tmp = (Sum-1)/2 - sum[i]; ans += calc(j+1, tol-1, tmp); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]); if( i != 1 ) { ans += calc(j+1, tol-1, tmp+a[1]); if( i+1 < n ) ans += calc(j+1, tol-1, tmp-a[n]+a[1]); } } // d2(i, ans); } las = 0; for(int i=n;i>=3;i--) { las += a[i]; if( las*2 >= Sum ) break; ans++; } return ans + 1; } void solve(){ scanf( %d ,&n); Sum = 0; for(int i=1;i<=n;i++) { scanf( %d ,&a[i]); Sum += a[i]; sum[i] = sum[i-1] + a[i]; } printf( %lld n , work()%998244353); } int main(){ int T; scanf( %d ,&T); for(int _=1;_<=T;_++) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long a, b, x, y; long long best, ansp, ansq; int main() { while (cin >> a >> b >> x >> y) { long long gg = gcd(x, y); x /= gg; y /= gg; best = -1; long long maxr = min(a / x, b / y); if (maxr <= 0) cout << 0 << << 0 << endl; else cout << x * maxr << << y * maxr << endl; } }
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#include <bits/stdc++.h> using namespace std; const long long int N = 100005; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { long long int i, j, k, n, m, ans = 0, cnt = 0, sum = 0; cin >> n; vector<long long int> v; long long int a[n]; j = 0; ans = 0; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] < 0) { j++; if (j == 3) { v.push_back(i - ans); cnt++; ans = i; j = 1; } } if (i == n - 1) { v.push_back(i - ans + 1); cnt++; } } cout << max((long long int)1, cnt) << endl; for (auto x : v) { cout << x << ; } } }
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#include <bits/stdc++.h> using namespace std; void read() { freopen( input.txt , r , stdin); } bool check(string s) { long long ans = s[0] - 0 ; ans = ans * 10ll + (s[1] - 0 ); if (ans % 4 == 0) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; cin >> s; long long ans = 0; for (long long i = 0; i < (long long)s.size(); i++) { if ((s[i] - 0 ) % 4 == 0) ans++; } string temp = ; for (long long i = 0; i < (long long)s.size() - 1; i++) { temp += s.substr(i, 2); if (check(temp)) { ans += i + 1; } temp = ; } cout << ans << endl; return 0; }
|
/*
* File: pippo_barrel.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Assigner:
* Description: barrel shifter
* Task
* [TBD]ºÏ²¢32λºÍ64λÒÆλÂß¼£»
* [TBO]¶àÖÜÆÚ²ÎÊý»¯
*/
module pippo_barrel (
shift_in,
shift_cnt,
shift_left,
shift_arith,
shift_mode_32b,
shrot_out
);
parameter width = `OPERAND_WIDTH;
input [width-1:0] shift_in; // data to be shifted
input [5:0] shift_cnt; // fully encoded shift amount
input shift_left; // =1 for left shift, =0 for right
input shift_arith; // =1 for arith shift, =0 for logical
input shift_mode_32b; // =0 for 64bit shift, =1 for 32bit shift
output [width-1:0] shrot_out;
//
// 32b mode shift
//
wire fill_32b;
reg [95:0] shifted_32b;
wire [95:0] sht_operand_32b;
wire [64:0] shift_out_32b;
assign fill_32b = shift_in[31] & shift_arith & shift_mode_32b;
assign sht_operand_32b = {({32{fill}}), shift_in[31:0], 32'b0};
always @ (sht_operand or shift_left or shift_cnt) begin
if (shift_left)
shifted_32b = sht_operand_32b << shift_cnt[4:0];
else
shifted_32b = sht_operand_32b >> shift_cnt[4:0];
end
assign shift_out_32b = {32{shifted_32b[63]}, shifted_32b[63:32]};
//
// 64b mode shift
//
wire fill_64b;
reg [191:0] shifted_64b;
wire [191:0] sht_operand_64b;
wire [63:0] shift_out_64b;
assign fill_64b = shift_in[63] & shift_arith & (!shift_mode_32b);
assign sht_operand_64b = {({64{fill}}), shift_in[63:0], 64'b0};
always @ (sht_operand_64b or shift_left_64b or shift_cnt) begin
if (shift_left)
shifted_64b = sht_operand_64b << shift_cnt[5:0];
else
shifted_64b = sht_operand_64b >> shift_cnt[5:0];
end
assign shift_out_64b = shifted_64b[127:64];
//
// shrot result
//
assign shrot_out = shift_mode_32b ? shift_out_32b : shift_out_64b;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CHARMAP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CHARMAP (
address,
clock,
q);
input [8:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../charmap/charmap.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../charmap/charmap.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; int n, m; string s, t; vector<char> vv; int main() { cin >> n >> m; cin >> s; for (int i = 0; i < n; i++) vv.push_back(s[i]); sort(vv.begin(), vv.end()); if (((int)(s).size()) < m) { t = s; for (int i = ((int)(s).size()); i < m; i++) t += vv[0]; cout << t << endl; return 0; } else if (((int)(s).size()) == m) { t = s; int k = 1; while (1) { if (s[((int)(s).size()) - k] == vv[((int)(vv).size()) - 1]) { t[((int)(s).size()) - k] = vv[0]; k++; continue; } int bb = upper_bound((vv).begin(), (vv).end(), t[((int)(s).size()) - k]) - vv.begin(); t[((int)(s).size()) - k] = vv[bb]; break; } cout << t << endl; return 0; } else { t = s.substr(0, m); int k = 1; while (1) { if (s[m - k] == vv[((int)(vv).size()) - 1]) { t[m - k] = vv[0]; k++; continue; } int bb = upper_bound((vv).begin(), (vv).end(), t[m - k]) - vv.begin(); t[m - k] = vv[bb]; break; } cout << t << endl; return 0; } }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2 * 1000 + 17; int n, init[MAXN][MAXN], hope[MAXN][MAXN], c[MAXN][MAXN], r[MAXN], cnt = 1, comp[MAXN << 2]; vector<int> out[MAXN << 2], in[MAXN << 2], order, trash; vector<pair<string, int>> ans; void add(int i, bool f1, int j, bool f2) { int v = (i << 1) | f1, u = (j << 1) | f2; out[v].push_back(u); in[u].push_back(v); out[u ^ 1].push_back(v ^ 1); in[v ^ 1].push_back(u ^ 1); } void scc(int v, vector<int> g[], vector<int> &vec) { comp[v] = cnt; for (auto i : g[v]) if (!comp[i]) scc(i, g, vec); vec.push_back(v); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); char C; cin >> n; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> C, init[i][j] = int(C - 0 ); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> C, hope[i][j] = int(C - 0 ), c[i][j] = init[i][j] ^ hope[i][j]; for (int i = 1; i <= n; i++) cin >> C, r[i] = int(C - 0 ); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (c[i][j] && r[i] && r[j]) add(i, true, n + j, false), add(i, false, n + j, true); else if (c[i][j] && r[i] && !r[j]) add(i, true, n + j, true), add(i, false, n + j, true); else if (c[i][j] && !r[i] && r[j]) add(n + j, true, i, true), add(n + j, false, i, true); else if (c[i][j] && !r[i] && !r[j]) return cout << -1 << endl, 0; else if (!c[i][j] && r[i] && r[j]) add(i, true, n + j, true), add(i, false, n + j, false); else if (!c[i][j] && r[i] && !r[j]) add(i, true, n + j, false), add(i, false, n + j, false); else if (!c[i][j] && !r[i] && r[j]) add(n + j, true, i, false), add(n + j, false, i, false); else ; for (int i = 1; i <= ((n << 2) | 1); i++) if (!comp[i]) scc(i, out, order); cnt = 0; memset(comp, 0, sizeof(comp)); for (int i = (n << 1); ~i; i--) { int v = order[i]; if (!comp[v]) cnt++, scc(v, in, trash); } for (int i = 1; i <= (n << 1); i++) { if (comp[i << 1] == comp[i << 1 | 1]) return cout << -1 << endl, 0; if (comp[i << 1 | 1] > comp[i << 1]) { if (i > n) ans.push_back({ col , i - n - 1}); else ans.push_back({ row , i - 1}); } } cout << ans.size() << endl; for (auto i : ans) cout << i.first << << i.second << endl; return 0; }
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// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// FILE DETAILS
// Project : GPIO for LM32
// File : tpio.v
// Title : Tri State IO control
// Dependencies : system_conf.v
// Description : Implements the logic to interface tri-state IO with
// Wishbone bus.
// =============================================================================
// REVISION HISTORY
// Version : 7.0
// Mod. Date : Jun 27, 2005
// Changes Made : Initial Creation
//
// Version : 7.0SP2, 3.0
// Mod. Date : 20 Nov. 2007
// Changes Made : Code clean up and add the BB for the inout port.
//
// Version : 3.1
// Mod. Date : 11 Oct. 2008
// Changes Made : Update the Edge Capture Register clean method
// Make IRQ Mask register readable
// =============================================================================
`ifndef TPIO_V
`define TPIO_V
`include "system_conf.v"
module TRI_PIO #(parameter DATA_WIDTH = 16,
parameter IRQ_MODE = 1,
parameter LEVEL = 0,
parameter EDGE = 1,
parameter POSE_EDGE_IRQ = 1,
parameter NEGE_EDGE_IRQ = 0,
parameter EITHER_EDGE_IRQ = 0)
(RST_I,
CLK_I,
DAT_I,
DAT_O,
PIO_IO,
IRQ_O,
PIO_TRI_WR_EN,
PIO_TRI_RE_EN,
PIO_DATA_RE_EN,
PIO_DATA_WR_EN,
IRQ_MASK_RE_EN,
IRQ_MASK_WR_EN,
EDGE_CAP_WR_EN);
parameter UDLY = 1;//user delay
input RST_I;
input CLK_I;
input DAT_I;
input PIO_TRI_RE_EN;
input PIO_TRI_WR_EN;
input PIO_DATA_RE_EN;
input PIO_DATA_WR_EN;
output DAT_O;
input IRQ_MASK_RE_EN;
input IRQ_MASK_WR_EN;
input EDGE_CAP_WR_EN;
output IRQ_O;
inout PIO_IO;
wire PIO_IO_I;
wire DAT_O;
wire IRQ_O;
reg PIO_DATA_O;
reg PIO_DATA_I;
reg PIO_TRI;
reg IRQ_MASK;
reg IRQ_TEMP;
reg EDGE_CAPTURE;
reg PIO_DATA_DLY;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_TRI <= #UDLY 0;
else if (PIO_TRI_WR_EN)
PIO_TRI <= #UDLY DAT_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_O <= #UDLY 0;
else if (PIO_DATA_WR_EN)
PIO_DATA_O <= #UDLY DAT_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_I <= #UDLY 0;
else if (PIO_DATA_RE_EN)
PIO_DATA_I <= #UDLY PIO_IO_I;
BB tpio_inst(.I(PIO_DATA_O), .T(~PIO_TRI), .O(PIO_IO_I), .B(PIO_IO));
assign DAT_O = PIO_TRI_RE_EN ? PIO_TRI :
IRQ_MASK_RE_EN ? IRQ_MASK : PIO_DATA_I;
//IRQ_MODE
generate
if (IRQ_MODE == 1) begin
//CONFIG THE IRQ_MASK REG.
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
IRQ_MASK <= #UDLY 0;
else if (IRQ_MASK_WR_EN)
IRQ_MASK <= #UDLY DAT_I;
end
endgenerate
generate
if (IRQ_MODE == 1 && LEVEL == 1) begin
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
IRQ_TEMP <= #UDLY 0;
else
IRQ_TEMP <= #UDLY PIO_IO_I & IRQ_MASK & ~PIO_TRI;//bit-and
assign IRQ_O = IRQ_TEMP;
end
else if (IRQ_MODE == 1 && EDGE == 1) begin
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_DLY <= #UDLY 0;
else
PIO_DATA_DLY <= PIO_IO_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
EDGE_CAPTURE <= #UDLY 0;
else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && POSE_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && NEGE_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
else if ( (~IRQ_MASK) & DAT_I & IRQ_MASK_WR_EN )
// interrupt mask's being set, so clear edge-capture
EDGE_CAPTURE <= #UDLY 0;
else if ( EDGE_CAP_WR_EN )
// user's writing to the edge-register, so update edge-capture
// register
EDGE_CAPTURE <= #UDLY EDGE_CAPTURE & DAT_I;
assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
end
else // IRQ_MODE ==0
assign IRQ_O = 0;
endgenerate
endmodule
`endif // TPIO_V
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#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a[n + 10]; for (int i = 1; i <= n; ++i) scanf( %lld , &a[i]); long long x, y; cin >> x >> y; long long h = x + y; long long sum = 0; for (int i = 1; i <= n; ++i) { sum = sum + y * (a[i] / (h)); a[i] = a[i] % h; if (a[i] > x) sum += y; } cout << sum; return 0; }
|
/*module ds8dac1(clk, in_data, sout);
input clk;
input [7:0] in_data;
output reg sout;
reg [8:0] PWM_accumulator;
reg [7:0] PWM_add;
initial
begin
PWM_accumulator <= 0;
PWM_add <=0;
end
always @(posedge clk) begin
PWM_accumulator <= PWM_accumulator[7:0] + PWM_add;
PWM_add <= in_data;
end
always @(negedge clk) begin
sout <= PWM_accumulator[8];
end
endmodule*/
// Delta-Sigma DAC
module ds8dac1(clk, DACin, DACout);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [7:0] DACin; // DAC input
input clk;
reg [9:0] DeltaAdder; // Output of Delta adder
reg [9:0] SigmaAdder; // Output of Sigma adder
reg [9:0] SigmaLatch; // Latches output of Sigma adder
reg [9:0] DeltaB; // B input of Delta adder
initial
begin
DeltaAdder = 10'd0;
SigmaAdder = 10'd0;
SigmaLatch = 10'd0;
DeltaB = 10'd0;
end
always @(SigmaLatch) DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clk)
begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[9];
end
endmodule
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