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#include <bits/stdc++.h> using namespace std; int N, K; int A[300005]; int DP[300005]; bool chk(int d) { int mxp = 0; for (int i = K; i <= N; i++) { if (A[i] - A[DP[i - K] + 1] <= d) mxp = i; DP[i] = mxp; } return mxp == N; } int main() { cin >> N >> K; for (int i = 1; i <= N; i++) cin >> A[i]; sort(A + 1, A + 1 + N); int l = -1, r = 1e9; while (l + 1 < r) { int md = (l + r) / 2; if (chk(md)) r = md; else l = md; } cout << r << n ; }
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#include <bits/stdc++.h> using namespace std; int n, x; long long f[200010]; vector<pair<int, long long> > ke[200010]; struct te { int l, r; long long s; } a[200010]; bool cmp(te i, te j) { return ((i.l < j.l) || (i.l == j.l && i.r < j.r)); } int main() { if (fopen( a.txt , r )) { freopen( a.txt , r , stdin); } else ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> x; for (int i = 1; i <= n; i++) cin >> a[i].l >> a[i].r >> a[i].s; sort(a + 1, a + n + 1, cmp); int cur = 0; for (int i = 0; i <= x; i++) f[i] = (1LL << 61); long long res = (1LL << 61); for (int i = 1; i <= n; i++) { while (cur < a[i].l - 1) { cur++; for (auto tmp : ke[cur]) { f[tmp.first] = min(f[tmp.first], tmp.second); } } if (x > a[i].r - a[i].l + 1) res = min(res, a[i].s + f[x - a[i].r + a[i].l - 1]); ke[a[i].r].push_back(make_pair(a[i].r - a[i].l + 1, a[i].s)); } if (res >= (1LL << 61)) res = -1; cout << res; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: ROM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module ROM_test #(parameter W=32)(
input wire [9:0] address,
output reg [W-1:0] data
);
localparam ROM_FILE32 = "/home/carlos/Documents/0.-0.58495_HEX.txt";
localparam ROM_FILE64= "C:/Users/XXXXX/Desktop/RTL/NORMALIZACION_V.txt";
//(* rom_style="{distributed | block}" *)
reg [W-1:0] rom_test [1023:0];
generate
if(W==32)
initial
begin
$readmemh( ROM_FILE32 , rom_test, 0, 1023);
end
else
initial
begin
$readmemh(ROM_FILE64, rom_test, 0, 1023);
end
endgenerate
always @*
begin
data = rom_test[address];
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, s = 0; cin >> a >> b; while (b > 1) { if (b > a) swap(a, b); s += a / b; a -= (b * (a / b)); if (a < 1) break; } s += a; cout << s << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, a[110]; double f[110][110][110], C[110][110]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d , &a[i]); C[0][0] = 1; for (int i = 1; i <= 55; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; } for (int i = 0; i <= n; i++) f[0][0][i] = i; for (int i = 1; i <= m; i++) for (int j = 0; j <= n; j++) for (int k = 0; k <= n; k++) for (int c = 0; c <= j; c++) { int _max = max(k, (c % a[i] == 0) ? (c / a[i]) : (c / a[i] + 1)); f[i][j][k] += f[i - 1][j - c][_max] * pow(i - 1, j - c) / pow(i, j) * C[j][c]; } printf( %.10f n , f[m][n][0]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; vector<vector<int> > v(n, vector<int>(7, 0)); for (int i = 0; i < n; i++) { cin >> s; for (int j = 0; j < 7; j++) v[i][j] = s[j] - 0 ; } vector<int> cnt(7, 0); for (int i = 0; i < 7; i++) { for (int j = 0; j < n; j++) cnt[i] += v[j][i]; } int m = 0; for (int i = 0; i < 7; i++) { if (cnt[i] > m) m = cnt[i]; } cout << m; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
`define SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
/**
* sregsbp: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 3
*/
//`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// Behavioral model for the SIPO convertor
module SIPO(data_out, out_valid, serial_in, in_valid, reset_b, clk);
// Output signals representing the end of the transaction
// Output of the SIPO convertor
output [7:0] data_out;
/**
* Indicate if the data is valid at data_out
* out_valid = 1 when data is valid; it is ZERO otherwise
*/
output out_valid;
// ===============================================================
// Input signals
// Input data bit coming in to the SIPO convertor
input serial_in;
// Clock signal to facilitate state transitions
input clk;
// Active low reset signal to bring all outputs to ZERO
input reset_b;
/**
* Active high flag to enable data to be loaded at the positive
* edge of the clock
*/
input in_valid;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg out_valid; // Output signal
reg [7:0] data_out; // Output signal
// Outputs of the D flip-flops in the SIPO converter
reg [7:0] q_dff; // Output of the D flip-flops
// Flag to indicate if the flip-flops have their outputs set
reg flag1; // flag of the 1st D flip-flop
reg flag2; // flag of the 2nd D flip-flop
reg flag3; // flag of the 3rd D flip-flop
reg flag4; // flag of the 4th D flip-flop
reg flag5; // flag of the 5th D flip-flop
reg flag6; // flag of the 6th D flip-flop
reg flag7; // flag of the 7th D flip-flop
reg flag8; // flag of the 8th D flip-flop
// ===============================================================
// Definitions for the states in the SIPO convertor
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Logic for active low reset signal to reset the SIPO convertor
always @(~reset_b)
begin
// When "reset_b" goes low, out_valid=0
out_valid<=1'd0;
// Set the output of the SIPO convertor to ZERO
data_out<=8'd0;
// Set the output of the D flip-flops to ZERO
q_dff<=8'd0;
// Set the flags for the flip-flops to zero
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
end
// ===============================================================
// 1st D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if(flag1==1)
begin
$display($time,"Process input #1",serial_in);
q_dff[0]<=serial_in;
flag1<=1'd0;
end
end
end
// ===============================================================
// 2nd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag2==1) && (flag1==0))
begin
$display($time,"Process input #2",serial_in);
q_dff[1]<=serial_in;
flag2<=1'd0;
end
end
end
// ===============================================================
// 3rd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag3==1) && (flag2==0))
begin
$display($time,"Process input #3",serial_in);
q_dff[2]<=serial_in;
flag3<=1'd0;
end
end
end
// ===============================================================
// 4th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag4==1) && (flag3==0))
begin
$display($time,"Process input #4",serial_in);
q_dff[3]<=serial_in;
flag4<=1'd0;
end
end
end
// ===============================================================
// 5th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag5==1) && (flag4==0))
begin
$display($time,"Process input #5",serial_in);
q_dff[4]<=serial_in;
flag5<=1'd0;
end
end
end
// ===============================================================
// 6th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag6==1) && (flag5==0))
begin
$display($time,"Process input #6",serial_in);
q_dff[5]<=serial_in;
flag6<=1'd0;
end
end
end
// ===============================================================
// 7th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag7==1) && (flag6==0))
begin
$display($time,"Process input #7",serial_in);
q_dff[6]<=serial_in;
flag7<=1'd0;
end
end
end
// ===============================================================
// 8th/Final/Last D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag8==1) && (flag7==0))
begin
$display($time,"Process input #8",serial_in);
q_dff[7]<=serial_in;
flag8<=1'd0;
out_valid<=1'd1;
end
end
else if(out_valid)
begin
$display($time,"Produce the output and reset data",serial_in);
data_out<=q_dff;
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
out_valid<=1'd0;
q_dff<=8'd0;
end
end
endmodule
|
module trigTable_tb ();
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire signed [17:0] sin;
wire signed [17:0] cos;
reg signed [17:0] expectedSin;
reg signed [17:0] expectedCos;
reg [11:0] angle;
reg [11:0] angleD1;
reg clk;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
always #1 clk = ~clk;
initial begin
clk = 1'b0;
angle = 0;
angleD1 = 0;
// Let sine table start outputting valid data
@(posedge clk);
@(posedge clk);
// Run sine table over several frequencies
for (i=1; i<2**11; i=i<<1) begin // double frequency each time
@(posedge clk) angle = angle + i;
while (angle != 0) begin
@(posedge clk) angle = angle + i;
if ((sin - expectedSin > 1) || (sin - expectedSin < -1)) begin
$display("FAILED SIN @ angle=%d", angleD1);
end
if ((cos - expectedCos > 1) || (cos - expectedCos < -1)) begin
$display("FAILED COS @ angle=%d", angleD1);
end
end
end
$display("PASSED");
$finish(2);
end
always @(posedge clk) begin
angleD1 <= angle;
expectedSin <= $rtoi($floor($sin(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
expectedCos <= $rtoi($floor($cos(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
end
trigTable #(
.ANGLE_WIDTH(12),
.OUT_WIDTH(18)
) uut (
.clk(clk), ///< System Clock
.angle(angle), ///< [ANGLE_WIDTH-1:0] Angle to take sine of
.sin(sin), ///< [OUT_WIDTH-1:0] Sine of angle
.cos(cos) ///< [OUT_WIDTH-1:0] Cosine of angle
);
endmodule
|
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_32x512a.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_32x512a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
output [9:0] wrusedw;
wire sub_wire0;
wire [9:0] sub_wire1;
wire sub_wire2;
wire [31:0] sub_wire3;
wire rdempty = sub_wire0;
wire [9:0] wrusedw = sub_wire1[9:0];
wire wrfull = sub_wire2;
wire [31:0] q = sub_wire3[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3)
// synopsys translate_off
,
.wrempty (),
.rdusedw (),
.rdfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_wave*.jpg FALSE
|
// limbus_cpu.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_cpu (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [21:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [21:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
limbus_cpu_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
module bram_tb #(
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
bram uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
WR_DATA = xorshift64_state;
xorshift64_next;
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;
#1; clk <= 1;
#1; clk <= 0;
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s",
i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd,
expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 5; const long long SQRTN = 1003; const long long LOGN = 22; const double PI = acos(-1.0); const long long INF = 1e18; const long long MOD = 1e9 + 7; const long long FMOD = 998244353; const double eps = 1e-9; void __print(long long x) { cerr << x; } void __print(long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { long long f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } mt19937 RNG(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> T gcd(T a, T b) { if (b == 0) return a; a %= b; return gcd(b, a); } template <typename T> T lcm(T a, T b) { return (a * (b / gcd(a, b))); } long long add(long long a, long long b, long long c = MOD) { long long res = a + b; return (res >= c ? res % c : res); } long long sub(long long a, long long b, long long c = MOD) { long long res; if (abs(a - b) < c) res = a - b; else res = (a - b) % c; return (res < 0 ? res + c : res); } long long mul(long long a, long long b, long long c = MOD) { long long res = (long long)a * b; return (res >= c ? res % c : res); } long long muln(long long a, long long b, long long c = MOD) { long long res = (long long)a * b; return ((res % c) + c) % c; } long long mulmod(long long a, long long b, long long m = MOD) { long long q = (long long)(((long double)a * (long double)b) / (long double)m); long long r = a * b - q * m; if (r > m) r %= m; if (r < 0) r += m; return r; } template <typename T> T binpow(T e, T n) { T x = 1, p = e; while (n) { if (n & 1) x = x * p; p = p * p; n >>= 1; } return x; } template <typename T> T binpow2(T e, T n, T m = MOD) { T x = 1, p = e; while (n) { if (n & 1) x = mul(x, p, m); p = mul(p, p, m); n >>= 1; } return x; } template <typename T> T extended_euclid(T a, T b, T &x, T &y) { T xx = 0, yy = 1; y = 0; x = 1; while (b) { T q = a / b, t = b; b = a % b; a = t; t = xx; xx = x - q * xx; x = t; t = yy; yy = y - q * yy; y = t; } return a; } template <typename T> T mod_inverse(T a, T n = MOD) { T x, y, z = 0; T d = extended_euclid(a, n, x, y); return (d > 1 ? -1 : sub(x, z, n)); } const long long FACSZ = 1e4; long long fact[FACSZ], ifact[FACSZ]; void precom(long long c = MOD) { fact[0] = 1; for (long long i = 1; i < FACSZ; i++) fact[i] = mul(fact[i - 1], i, c); ifact[FACSZ - 1] = mod_inverse(fact[FACSZ - 1], c); for (long long i = FACSZ - 1 - 1; i >= 0; i--) { ifact[i] = mul(i + 1, ifact[i + 1], c); } } vector<long long> primes; void prime_precom() { primes.push_back(2); for (long long x = 3; primes.size() <= MAXN; x += 2) { bool isPrime = true; for (auto p : primes) { if (x % p == 0) { isPrime = false; break; } if (p * p > x) { break; } } if (isPrime) { primes.push_back(x); } } } long long ncr(long long n, long long k) { if (n < k) return 0; if (k == 0) return 1; long long res = 1; if (k > n - k) k = n - k; for (long long i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); } return res; } long long ncr_modp(long long n, long long k, long long c = MOD) { if (n < k) return 0; if (k == 0) return 1; long long res = 1; if (k > n - k) k = n - k; for (long long i = 0; i < k; ++i) { res = mul(res, n - i, c); res = mul(res, binpow2(i + 1, c - 2, c), c); } return res; } vector<long long> factors; void factorize(long long a) { factors.clear(); for (long long i = 1; i * i <= a; i++) { if (a % i == 0) { factors.push_back(i); factors.push_back(a / i); } } sort(factors.begin(), factors.end()); } long long ncr_precom(long long n, long long r, long long c = MOD) { return mul(mul(ifact[r], ifact[n - r], c), fact[n], c); } long long ceil(long long a, long long b) { return (a + b - 1) / b; } bool is_prime(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { return 0; } } return 1; } bool diophantine_checker(long long a, long long b, long long n) { for (long long i = 0; i * a <= n; i++) { if ((n - (i * a)) % b == 0) { return true; } } return false; } long long count_divisors(long long n) { long long c; long long ans = 1; for (long long i = 2; i * i <= n; i++) { c = 0; while (n % i == 0) { c++; n /= i; } ans *= (c + 1); } if (n > 2) { return ans * 2; } return ans; } string to_binary(long long n) { string r; while (n != 0) { r = (n % 2 == 0 ? 0 : 1 ) + r; n /= 2; } return r; } bool ispower2(long long x) { return x && (!(x & (x - 1))); } vector<long long> spf; void sieve() { spf.resize(MAXN); spf[1] = 1; for (long long i = 2; i < MAXN; i++) { spf[i] = i; } for (long long i = 4; i < MAXN; i += 2) { spf[i] = 2; } for (long long i = 3; i * i <= MAXN; i++) { if (spf[i] == i) { for (long long j = i * i; j < MAXN; j += i) { if (spf[j] == j) { spf[j] = i; } } } } } void pfactor(long long x, vector<long long> &ret) { while (x != 1) { ret.push_back(spf[x]); x = x / spf[x]; } } struct point { long long x, y; void read() { cin >> x >> y; } point operator-=(const point &b) { return {x -= b.x, y -= b.y}; } long long operator*(const point &b) { return x * b.y - y * b.x; } point operator-(const point &b) { return {x - b.x, y - b.y}; } }; long long n, k; long double dist[MAXN], angle[MAXN]; bool check(long double r) { vector<pair<long double, long long>> val; long long cnt = 0; for (long long i = 0; i < n; i++) { if (dist[i] + eps >= 2 * r) { continue; } long double bd = acos(dist[i] / (2. * r)); long double mn = angle[i] - bd, mx = angle[i] + bd; while (mn < -PI) { mn += 2 * PI; } while (mx < -PI) { mx += 2 * PI; } while (mn > PI) { mn -= 2 * PI; } while (mx > PI) { mx -= 2 * PI; } val.push_back(make_pair(mn, 1)); val.push_back(make_pair(mx, -1)); if (mn > mx) { cnt += 1; } } long long ans = cnt; sort(val.begin(), val.end()); for (auto x : val) { cnt += x.second, ans = max(ans, cnt); } return ans >= k; } void solvethetestcase() { cin >> n >> k; vector<point> vv; for (long long i = 0; i < n; i++) { long long xx, yy; cin >> xx >> yy; if (xx == 0 && yy == 0) { --k, --n, --i; } else { vv.push_back(point{xx, yy}); } } if (k <= 0) { cout << 0.0 << n ; return; } for (long long i = 0; i < n; i++) { angle[i] = atan2(vv[i].y, vv[i].x); dist[i] = sqrtl(1. * vv[i].x * vv[i].x + 1. * vv[i].y * vv[i].y); } long double l = 0, r = 2e5; for (long long i = 0; i < 50; i++) { long double md = (l + r) * 0.5; if (check(md)) { r = md; } else { l = md; } } cout << r << n ; } signed main() { cout << fixed << setprecision(12); ; ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; for (long long testcase = 1; testcase < t + 1; testcase++) { solvethetestcase(); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 300001; int n, a, b, c, d, start, len; vector<int> T; long long dp[2][N + 2], seg[4 * N]; void build(int p, int s, int e) { if (s == e) { seg[p] = dp[1][s]; return; } build(2 * p, s, (s + e) / 2); build(2 * p + 1, (s + e) / 2 + 1, e); seg[p] = min(seg[2 * p], seg[2 * p + 1]); } long long get(int p, int s, int e, int a, int b) { if (s >= a && e <= b) return seg[p]; if (s > b || e < a) return 1e15; return min(get(2 * p, s, (s + e) / 2, a, b), get(2 * p + 1, (s + e) / 2 + 1, e, a, b)); } int main() { scanf( %d%d%d%d%d%d%d , &n, &a, &b, &c, &d, &start, &len); dp[0][0] = start; dp[1][0] = start; T.push_back(0); for (int i = 1, t, q; i <= n; i++) { scanf( %d%d , &t, &q); dp[0][i] = dp[0][i - 1], dp[1][i] = dp[1][i - 1]; if (q) dp[0][i] += a, dp[1][i] += c; else dp[0][i] -= b, dp[1][i] -= d; T.push_back(t); } build(1, 0, n); int j = n, c = 0; auto it = lower_bound(T.begin(), T.end(), c + len); if (it != T.end()) j = *it - 1; if (get(1, 0, n, 0, j) >= 0) { printf( %d n , c); return 0; } for (int i = 0; i < T.size(); i++) { if (dp[0][i] < 0) break; c = T[i] + 1; j = lower_bound(T.begin(), T.end(), c + len) - T.begin() - 1; if (i == n || j < i + 1 || get(1, 0, n, i + 1, j) - dp[1][i] + dp[0][i] >= 0) { printf( %d n , c); return 0; } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long leader[110000], p[110000]; long long n, m, i, j, k; bool can(long long cost) { for (i = 0, j = 0; i < n && j < m; ++i) { long long summ = cost; if (leader[i] == p[j] && j < m) ++j; if (j >= m) break; summ -= abs(leader[i] - p[j]); long long temp = leader[i] - p[j]; if (summ < 0) continue; if (temp > 0) { int t = j; while (p[j] <= leader[i] && j < m) ++j; while (cost >= p[j] - p[t] + min(p[j] - leader[i], leader[i] - p[t]) && j < m) ++j; if (j >= m) break; } else { while (p[j] <= leader[i] + cost && j < m) ++j; if (j >= m) break; } } if (j >= m) return 1; else return 0; } int main() { long long cost = 0; scanf( %I64d%I64d , &n, &m); for (i = 0; i < n; ++i) scanf( %I64d , &leader[i]); for (i = 0; i < m; ++i) scanf( %I64d , &p[i]); i = 0, j = 0; long long l = -1, r = max(p[m - 1] * 2, leader[n - 1] * 2); if (n != 1) while (r - l > 1) { long long mid = l + (r - l) / 2; if (can(mid)) r = mid; else l = mid; } if (n != 1) printf( %I64d , r); else { if (leader[0] < p[0]) printf( %I64d , p[m - 1] - leader[0]); else if (leader[0] > p[m - 1]) printf( %I64d , leader[0] - p[0]); else { printf( %I64d , p[m - 1] - p[0] + min(leader[0] - p[0], p[m - 1] - leader[0])); } } return 0; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the use of memories within tasks.
*/
module test;
parameter addrsiz = 14;
parameter ramsiz = 1 << addrsiz;
task loadram;
integer i, j;
reg [15:0] memword;
reg [15:0] tempram[0:(2*ramsiz)-1];
begin
for (i = 0; i < 16; i = i + 2)
tempram[i] = i;
for (i = 0; i < 16; i = i + 2)
if (tempram[i] !== i) begin
$display("FAILED -- %m.tempram[%d] = %b", i, tempram[i]);
$finish;
end
$display("PASSED");
end
endtask // loadram
initial loadram;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a1, a2; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> a1 >> a2; int res = 0; if (a1 == 1 && a2 == 1) { cout << 0 << n ; return 0; } while (a1 > 0 && a2 > 0) { if (a1 < a2) ++a1, a2 -= 2; else ++a2, a1 -= 2; ++res; } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool comp(int a, int b) { return a < b; } int main() { stack<int> s; int N, t; cin >> N; while (N--) { cin >> t; if (s.empty()) { s.push(t); } else { if (((s.top()) & 1) == (t & 1)) s.pop(); else s.push(t); } } if (s.size() < 2) cout << YES << endl; else cout << NO << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N (
Q ,
D ,
GATE ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, ans = 1e9; vector<vector<int> > cnt(65); vector<set<int> > ed; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; ed.resize(n + 1); bool tw = false; for (int i = 0; i < n; i++) { long long a; cin >> a; int d = 0; while (a && !(tw)) { if (a & 1) { for (int k : cnt[d]) { if (ed[k].find(i) == ed[k].end()) { ed[k].insert(i); ed[i].insert(k); } } cnt[d].push_back(i); if (cnt[d].size() > 2) tw = true; } a >>= 1, d++; } } if (tw) { cout << 3 << n ; return 0; } for (int j = 0; j < 64; j++) { unordered_set<int> vis; if (cnt[j].size() == 2) { queue<pair<int, int> > q; for (int k : ed[cnt[j][0]]) if (k != cnt[j][1]) q.push(make_pair(k, 1)); vis.insert(cnt[j][0]); while (!q.empty()) { pair<int, int> cur = q.front(); q.pop(); if (vis.find(cur.first) != vis.end()) continue; vis.insert(cur.first); if (cur.first == cnt[j][1]) { ans = min(ans, cur.second); break; } for (int k : ed[cur.first]) q.push(make_pair(k, cur.second + 1)); } } } if (ans == 1e9) cout << -1 << n ; else cout << ans + 1 << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; set<int> s; int n, t; char a[maxn]; int pos; int main() { register int i, tail, g; scanf( %d%d , &n, &t); scanf( %s , a + 1); for (i = 1; i <= n; i++) if (a[i] == . ) { pos = i; break; } g = pos; for (i = pos; i <= n; i++) if (a[i] >= 5 ) { g = i; break; } a[0] = 0 ; bool f; tail = n; while (t-- && (g > pos && a[g] >= 5 )) { a[g] = 0 ; tail = g; if (g != pos + 1) { a[g - 1]++; f = true; g = g - 1; } else { a[g - 2]++; g = g - 2; } while (g >= 0 && a[g] == : ) { if (g - 1 == pos) { a[g] = 0 ; a[g - 2]++; g -= 2; } else { a[g] = 0 ; a[g - 1]++; --g; } } } if (a[0] != 0 ) printf( %c , a[0]); for (i = 1; i < pos; i++) printf( %c , a[i]); while (a[tail] == 0 ) --tail; if (tail != pos) { printf( %c , 46); for (i = pos + 1; i <= tail; i++) printf( %c , a[i]); } puts( ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> a[n]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x; cin >> x; x--; a[i].push_back(x); } } int ans = 0; for (int j = 0; j < m; j++) { vector<int> cnt(n); int c = 0; for (int i = 0; i < n; i++) { if (a[i][j] % m != j || a[i][j] / m > n) c++; else { if (i >= a[i][j] / m) cnt[i - a[i][j] / m]++; else cnt[i + n - a[i][j] / m]++; } } int mn = 1e9; for (int i = 0; i < n; i++) { mn = min(mn, n - cnt[i] + i); } ans += mn; } cout << ans << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the +verilog1995ext+ and +verilog2001ext+ flags.
//
// This source code contains constructs that are valid in Verilog 2001 and
// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we
// set the language to be 1995, but not 2001.
//
// Compile only test, so no need for "All Finished" output.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] res;
// Instantiate the test
test test_i (/*AUTOINST*/
// Outputs
.res (res),
// Inputs
.clk (clk),
.in (1'b1));
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
// This is a Verilog 2001 test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5005, MAXC = 1000005; int a[MAXN], b[MAXC], c[MAXC]; int n, k, _max; int main() { if (0) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); }; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), _max = max(_max, a[i]); for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) b[abs(a[i] - a[j])]++; for (int res = n - k; res <= 1000001; res++) { int cnt = 0; bool ok = true; for (int i = res; i <= _max; i += res) { cnt += b[i]; if (cnt > (k + 1) * k / 2) { ok = false; break; } } if (!ok) continue; int x = 0; for (int i = 1; i <= n; i++) { if (c[a[i] % res]) x++; c[a[i] % res]++; } if (x <= k) { cout << res << endl; return 0; } for (int i = 1; i <= n; i++) c[a[i] % res] = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void enable_comma() {} string tostring(char c) { string s = ; s += c; return s; } string tostring(string s) { return + s + ; } string tostring(const char *c) { return tostring((string)c); } string tostring(long long x) { if (x < 0) return - + tostring(-x); if (x > 9) return tostring(x / 10) + tostring(char( 0 + x % 10)); else return tostring(char( 0 + x)); } string tostring(int x) { return tostring((long long)x); } string tostring(unsigned long long x) { if (x > 9) return tostring((long long)(x / 10)) + tostring(char( 0 + x % 10)); else return tostring(char( 0 + x)); } string tostring(unsigned x) { return tostring((long long)x); } string tostring(double x) { static char res[114]; sprintf(res, %lf , x); string s = tostring(res); return s.substr(1, (int)s.size() - 2); } string tostring(long double x) { return tostring((double)x); } template <class A, class B> string tostring(pair<A, B> p) { return ( + tostring(p.first) + , + tostring(p.second) + ) ; } template <class T> string tostring(T v) { string res = ; for (auto p : v) res += (res.size() ? , : { ) + tostring(p); return res.size() ? res + } : {} ; } template <class A> string tostring(A *a, int L, int R) { return tostring(vector<A>(a + L, a + R + 1)); }; template <class A> string tostring(A a, int L, int R) { return tostring(a.data(), L, R); } string tostrings() { return ; } template <typename Head, typename... Tail> string tostrings(Head H, Tail... T) { return tostring(H) + + tostrings(T...); } long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f = ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return f ? -x : x; } template <class T> void ckmax(T &x, const T y) { if (x < y) x = y; } template <class T> void ckmin(T &x, const T y) { if (x > y) x = y; } const int N = 100005; struct op { int tp; long long a, b; }; vector<op> res; int a[60]; set<long long> S; long long gao(int tp, long long a, long long b) { (!(S.count(a) && S.count(b)) ? cout << Assertion failed! << endl << function: << __FUNCTION__ << endl << line: << 149 << endl << expression: << S.count(a) && S.count(b) << endl, exit(3), 0 : 1); res.push_back({tp, a, b}); long long res = tp ? a ^ b : a + b; S.insert(res); (!(0 <= res && res <= 5000000000000000000LL) ? cout << Assertion failed! << endl << function: << __FUNCTION__ << endl << line: << 153 << endl << expression: << 0 <= res && res <= 5000000000000000000LL << endl, exit(3), 0 : 1); return res; } int Log(long long x) { int ans = 0; while (x > 1) { ans++; x >>= 1; } return ans; } int main() { long long x = read(); srand(time(NULL)); S.clear(); res.clear(); S.insert(x); while (x > 1) { vector<long long> v = {x}; while (1) { int p = (int)v.size() - 1; while (p > 0 && rand() % 5 != 0) p--; long long a = v.back(), b = gao(0, a, a), c = gao(0, v[p], b); if (Log(b) != Log(c)) { v.push_back(c); continue; } else { long long t = b ^ c; for (int i = ((int)v.size() - 1); i >= (0); i--) { if (Log(t) == Log(v[i] * 2)) t ^= v[i] * 2; if (Log(t) == Log(v[i])) t ^= v[i]; } if (~t & 1) { v.push_back(c); continue; } t = gao(1, b, c); for (int i = ((int)v.size() - 1); i >= (0); i--) { if (Log(t) == Log(v[i] * 2)) t = gao(1, t, v[i] * 2); if (Log(t) == Log(v[i])) t = gao(1, t, v[i]); } (!(Log(t) < Log(x)) ? cout << Assertion failed! << endl << function: << __FUNCTION__ << endl << line: << 198 << endl << expression: << Log(t) < Log(x) << endl, exit(3), 0 : 1); x = t; break; } } } printf( %d n , (int)res.size()); for (auto v : res) printf( %I64d %c %I64d n , v.a, +^ [v.tp], v.b); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, x, n; void input() { cin >> a >> b >> n >> x; return; } long long powmod(long long a, long long b) { if (b == 1) return a; if (b < 1) return 1; long long t = powmod(a, b / 2) % 1000000007; t = (t * t) % 1000000007; if (b % 2 == 1) { t = (t * a) % 1000000007; } return t; } void solve() { if (a == 1) { cout << (b * (n % 1000000007) + x) % 1000000007; return; } long long tmp = powmod(a, n); long long ans = ((tmp - 1) * powmod(a - 1, 1000000007 - 2)) % 1000000007; tmp = (tmp * x) % 1000000007; ans = (ans * b) % 1000000007; cout << (tmp + ans) % 1000000007; return; } void output() { return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); { input(); solve(); output(); } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx TEST ONLY Library Component
// / / Delay Element.
// /___/ /\ Filename : ZHOLD_DELAY.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/14/10 - Initial version.
// 05/12/11 - 609212 -- fix for ncsim
// 07/11/11 - 616630 -- Change/Combine attributes
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/10/12 - 659430 - remove GSR ref, ANSI ports, mti simprim error (add #1)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ZHOLD_DELAY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif // ifdef XIL_TIMING
parameter [0:0] IS_DLYIN_INVERTED = 1'b0,
parameter ZHOLD_FABRIC = "DEFAULT", // {"DEFAULT", "0", .... "31"}
parameter ZHOLD_IFF = "DEFAULT" // {"DEFAULT", "0", .... "31"}
) (
output DLYFABRIC,
output DLYIFF,
input DLYIN
);
localparam MODULE_NAME = "ZHOLD_DELAY";
//------------------- constants ------------------------------------
localparam MAX_IFF_DELAY_COUNT = 31;
localparam MIN_IFF_DELAY_COUNT = 0;
localparam MAX_IDELAY_COUNT = 31;
localparam MIN_IDELAY_COUNT = 0;
`ifndef XIL_TIMING
real TAP_DELAY = 200.0;
`endif // ifndef XIL_TIMING
integer idelay_count=0;
integer iff_idelay_count=0;
// inputs
wire dlyin_in;
`ifndef XIL_TIMING
// outputs
reg tap_out_fabric = 0;
reg tap_out_iff = 0;
`endif // ifndef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Output ------------------------------
//----------------------------------------------------------------------
`ifdef XIL_TIMING
assign #1 DLYFABRIC = dlyin_in;
assign #1 DLYIFF = dlyin_in;
`else // ifdef XIL_TIMING
assign DLYFABRIC = tap_out_fabric;
assign DLYIFF = tap_out_iff;
`endif // ifdef XIL_TIMING
//----------------------------------------------------------------------
//------------------------------- Input -------------------------------
//----------------------------------------------------------------------
assign dlyin_in = IS_DLYIN_INVERTED ^ DLYIN;
//------------------------------------------------------------
//--------------------- Initialization --------------------
//------------------------------------------------------------
initial begin
//-------- ZHOLD_FABRIC check
case (ZHOLD_FABRIC)
"DEFAULT" : idelay_count = 0;
"0" : idelay_count = 0;
"1" : idelay_count = 1;
"2" : idelay_count = 2;
"3" : idelay_count = 3;
"4" : idelay_count = 4;
"5" : idelay_count = 5;
"6" : idelay_count = 6;
"7" : idelay_count = 7;
"8" : idelay_count = 8;
"9" : idelay_count = 9;
"10" : idelay_count = 10;
"11" : idelay_count = 11;
"12" : idelay_count = 12;
"13" : idelay_count = 13;
"14" : idelay_count = 14;
"15" : idelay_count = 15;
"16" : idelay_count = 16;
"17" : idelay_count = 17;
"18" : idelay_count = 18;
"19" : idelay_count = 19;
"20" : idelay_count = 20;
"21" : idelay_count = 21;
"22" : idelay_count = 22;
"23" : idelay_count = 23;
"24" : idelay_count = 24;
"25" : idelay_count = 25;
"26" : idelay_count = 26;
"27" : idelay_count = 27;
"28" : idelay_count = 28;
"29" : idelay_count = 29;
"30" : idelay_count = 30;
"31" : idelay_count = 31;
default : begin
$display("Attribute Syntax Error : The attribute ZHOLD_FABRIC on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\" ..... \"31\"",MODULE_NAME,ZHOLD_FABRIC);
$finish;
end
endcase
//-------- ZHOLD_IFF check
case (ZHOLD_IFF)
"DEFAULT" : iff_idelay_count = 0;
"0" : iff_idelay_count = 0;
"1" : iff_idelay_count = 1;
"2" : iff_idelay_count = 2;
"3" : iff_idelay_count = 3;
"4" : iff_idelay_count = 4;
"5" : iff_idelay_count = 5;
"6" : iff_idelay_count = 6;
"7" : iff_idelay_count = 7;
"8" : iff_idelay_count = 8;
"9" : iff_idelay_count = 9;
"10" : iff_idelay_count = 10;
"11" : iff_idelay_count = 11;
"12" : iff_idelay_count = 12;
"13" : iff_idelay_count = 13;
"14" : iff_idelay_count = 14;
"15" : iff_idelay_count = 15;
"16" : iff_idelay_count = 16;
"17" : iff_idelay_count = 17;
"18" : iff_idelay_count = 18;
"19" : iff_idelay_count = 19;
"20" : iff_idelay_count = 20;
"21" : iff_idelay_count = 21;
"22" : iff_idelay_count = 22;
"23" : iff_idelay_count = 23;
"24" : iff_idelay_count = 24;
"25" : iff_idelay_count = 25;
"26" : iff_idelay_count = 26;
"27" : iff_idelay_count = 27;
"28" : iff_idelay_count = 28;
"29" : iff_idelay_count = 29;
"30" : iff_idelay_count = 30;
"31" : iff_idelay_count = 31;
default : begin
$display("Attribute Syntax Error : The attribute ZHOLD_IFF on %s instance %m is set to %s. Legal values for this attribute are \"DEFAULT\", \"0\", \"1\"...\"31\"",MODULE_NAME,ZHOLD_IFF);
$finish;
end
endcase
end // initial begin
`ifndef XIL_TIMING
always@(dlyin_in) begin
tap_out_fabric <= #(TAP_DELAY*idelay_count) dlyin_in;
tap_out_iff <= #(TAP_DELAY*iff_idelay_count) dlyin_in;
end // end always
`endif // ifndef XIL_TIMING
specify
`ifdef XIL_TIMING
( DLYIN => DLYFABRIC) = (0:0:0, 0:0:0);
( DLYIN => DLYIFF) = (0:0:0, 0:0:0);
`endif // ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // ZHOLD_DELAY
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { unordered_map<char, int> mp; int n; cin >> n; string arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; for (auto c : arr[i]) { mp[c]++; } } bool ok = true; for (auto p : mp) { if (p.second % n != 0) { ok = false; break; } } cout << ((ok) ? YES n : NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int n, m, h, t, u, v, src[MAXN], dst[MAXN], num[MAXN], used[MAXN]; vector<int> g[MAXN]; void out(vector<int> &v) { for (int i = 0; i < v.size(); ++i) { cout << v[i] << n [i == v.size() - 1]; } } bool check(int u, int v, int ver) { int cnt = 0; num[u] = num[v] = -1; for (int i = 0; i < g[u].size() && i < h + t; ++i) { int w = g[u][i]; if (w == v) continue; used[w] = ver; num[w] = 1; ++cnt; } for (int i = 0; i < g[v].size() && i < h + t; ++i) { int w = g[v][i]; if (w == u) continue; if (used[w] == ver) { num[w] = 2; continue; } used[w] = ver; num[w] = 1; ++cnt; } int degu = g[u].size() - 1, degv = g[v].size() - 1; if (h >= t != degu >= degv) swap(degu, degv); return degu >= h && degv >= t && cnt >= h + t; } void solve() { for (int mm = 0; mm < m; ++mm) { if (check(src[mm], dst[mm], mm + 1)) { cout << YES n ; u = src[mm], v = dst[mm]; if (h >= t != g[u].size() >= g[v].size()) swap(u, v); cout << u << << v << endl; vector<int> ans; for (int i = 0; i < g[u].size() && ans.size() < h; ++i) { int v = g[u][i]; if (num[v] == 1) { num[v] == -1; ans.push_back(v); } } for (int i = 0; i < g[u].size() && ans.size() < h; ++i) { int v = g[u][i]; if (num[v] > 1) { ans.push_back(v); num[v] = -1; } } out(ans); ans.clear(); swap(u, v); for (int i = 0; i < g[u].size() && ans.size() < t; ++i) { int v = g[u][i]; if (num[v] != -1) ans.push_back(v); } out(ans); return; } } cout << NO n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout << setprecision(6) << fixed; clog.copyfmt(cout); cin >> n >> m >> h >> t; for (int i = 0; i < m; ++i) { cin >> u >> v; src[i] = u, dst[i] = v; g[u].push_back(v); g[v].push_back(u); } solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int fx[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const int fxx[8][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; int gcD(int a, int b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } const int MAXN = 2e5 + 10; int a[MAXN]; int N; int main() { scanf( %d , &N); int g = 0; for (int i = 0; i < N; i++) { scanf( %d , &a[i]); g = gcD(a[i], g); } for (int i = 0; i < N; i++) { a[i] /= g; while ((a[i] & 1) == 0) a[i] = a[i] >> 1; while (a[i] % 3 == 0) a[i] /= 3; if (a[i] != 1) { printf( No n ); return 0; } } printf( Yes n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_4_V
`define SKY130_FD_SC_LS__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int j, t, n, m = 0, i; unsigned long long p = 0, q = 0; char a[1000001]; cin >> a; n = strlen(a); for (j = 0; j < n; j++) { if (a[j] == ^ ) { break; } } for (i = j - 1; i >= 0; i--) { if ((a[i] >= 1 ) && (a[i] <= 9 )) { t = abs(j - i); p += (t * ((int)a[i] - 48)); } } for (i = j + 1; i < n; i++) { if ((a[i] >= 1 ) && (a[i] <= 9 )) { t = abs(j - i); q += (t * ((int)a[i] - 48)); } } if (p == q) { cout << balance << endl; } else if (p > q) { cout << left << endl; } else { cout << right << endl; } }
|
#include <bits/stdc++.h> using ld = long double; using ll = long long; using namespace std; int MOD = 998244353; void solve() { int n; cin >> n; vector<vector<int>> p(n + n, vector<int>(n)); for (int i = 0; i < 2 * n; i++) { for (int j = 0; j < n; j++) { cin >> p[i][j]; p[i][j]--; } } vector<int> cnt(n); bool good = 1; vector<int> result; vector<int> del(n + n); vector<int> cros(n + n); int cringe = 0; auto accept = [&](int k) { del[k] = 1; for (int i = 0; i < n + n; i++) { if (del[i]) continue; for (int j = 0; j < n; j++) { if (p[i][j] == p[k][j]) { del[i] = 1; cringe = 1; break; } } } cros[k] = 1; result.push_back(k); }; while (good) { good = 0; for (int i = 0; i < n; i++) { fill(cnt.begin(), cnt.end(), 0); for (int j = 0; j < n + n; j++) if (!del[j]) cnt[p[j][i]]++; for (int j = 0; j < n; j++) { if (cnt[j] == 1) { good = 1; for (int k = 0; k < n + n; k++) { if (!del[k] && p[k][i] == j) { accept(k); break; } } break; } } if (good) break; } } vector<vector<int>> g(n + n); for (int i = 0; i < n + n; i++) { for (int j = 0; j < n + n; j++) { for (int k = 0; k < n; k++) { if (del[i] && !cros[i]) continue; if (del[j] && !cros[j]) continue; if (p[i][k] == p[j][k]) g[i].push_back(j); } } } vector<int> col(n + n, -1); int rs = 1; function<void(int, int)> dfs = [&](int v, int c=0) { if (col[v] != -1) return; col[v] = c; for (auto u : g[v]) dfs(u, 1-c); }; for (int i = 0; i < n + n; i++) { if (cros[i]) { if (col[i] == -1) dfs(i, 1); } } for (int i = 0; i < n + n; i++) { if (!del[i]) if (col[i] == -1) rs = rs * 2 % MOD, dfs(i, 1); } cout << rs << n ; for (int i = 0; i < n + n; i++) { if (col[i] == 1) cout << i + 1 << ; } cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(30); int t; cin >> t; while (t--) solve(); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module tri_intersect_data_array_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 576;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module tri_intersect_data_array(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd576;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
tri_intersect_data_array_ram tri_intersect_data_array_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) #pragma GCC optimize( -ffloat-store ) #define fastio ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #define int long long #define endl n #define sz(a) ((int)(a).size()) #define all(v) (v).begin(), (v).end() #define rall(v) (v).rbegin(), (v).rend() #define tr(c, it) for (auto it = (c).begin(); (it) != (c).end(); it++) #define pres(c, val) ((c).find(val) != (c).end()) // for sets, multisets, maps etc. #define cpres(c, val) (find((c).begin(), (c).end(), val) != (c).end()) // for others #define pb push_back #define mp make_pair #define F first #define S second #define forf(i, a, b) for (int i = (a); i < (b); i++) #define forb(i, a, b) for (int i = (b); i >= (a); i--) #define fo(i, n) forf(i, 0, n) #define fob(i, n) forb(i, 0, n - 1) typedef vector<int> vi; typedef vector<vector<int>> vvi; typedef pair<int, int> pii; typedef vector<pair<int, int>> vpii; const int INF = 9e18; const int N = 1000000007; //const int N = 998244353; const double eps = 1e-9; const auto start_time = std::chrono::high_resolution_clock::now(); void TIME() { #ifndef ONLINE_JUDGE auto end_time = std::chrono::high_resolution_clock::now(); std::chrono::duration<double> diff = end_time - start_time; cerr << Time Taken: << diff.count() << s n ; #endif } #ifndef ONLINE_JUDGE #include ./header.h #else #define debug(args...) 42 #endif /* ------------------ Actual Coding Starts ------------------ */ void solve() { int x; cin >> x; int rem = x%11, q = x/11; int num = (x-rem)/11-10*rem; if(num<0) cout << NO n ; else cout << YES n ; } int32_t main() { fastio; #ifndef ONLINE_JUDGE freopen( txt.in , r , stdin); freopen( txt.out , w , stdout); #endif //cout << fixed << setprecision(10); int t; cin >> t; while(t--) solve(); TIME(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__PROBEC_P_BLACKBOX_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probec_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 32000; const int mod = 1000000007; const int inf = 2 * mod; int dp[5001][5001]; pair<long long, long long> hashVal[5001]; pair<long long, long long> powVal[5001]; const long long base1 = 37; const long long base2 = 2017; const long long mod1 = 1e9 + 7; const long long mod2 = 1e9 + 297; int ans[50001]; string s; inline int ceil(int p, int q) { return (p + q - 1) / q; } int call(int l, int r) { if (l > r) return 0; if (l == r) return 1; if (l == r - 1) return (s[l] == s[r] ? 2 : 0); if (dp[l][r] != -1) return dp[l][r]; int ret; if (s[l] != s[r] || call(l + 1, r - 1) == 0) ret = 0; else ret = 1 + call(l, ceil(l + r, 2) - 1); return dp[l][r] = ret; } int main() { cin >> s; int len = s.length(); memset(dp, -1, sizeof(dp)); for (int i = 0; i < len; i++) { for (int j = 0; j < len; j++) { ans[call(i, j)]++; } } for (int i = len - 1; i >= 1; i--) ans[i] += ans[i + 1]; for (int i = 1; i <= len; i++) { cout << ans[i] << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[200001]; long long search(long long l, long long h, long long target) { if (h - l <= 1) { if (a[l] > target) return l; else return h; } long long mid = (l + h) / 2; if (a[mid] > target) return search(l, mid, target); else return search(mid + 1, h, target); } int main() { int N, M; cin >> N >> M; for (int i = 0; i < N; i++) { cin >> a[i]; } sort(a, a + N); for (int j = 0; j < M; j++) { int b; cin >> b; if (a[N - 1] > b) { cout << search(0, N - 1, b) << ; } else { cout << N << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, q; cin >> n >> m >> q; vector<long long> a(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; vector<int> weights(m, 0); vector<int> heavyListsIds; vector<vector<int> > lists(m, vector<int>()); int heavyBorder = ceil(sqrt(0.0 + n)); int heavyCount = 0; for (int i = 0; i < m; ++i) { int length; cin >> length; if (length > heavyBorder) { weights[i] = 42; ++heavyCount; heavyListsIds.push_back(i); } else weights[i] = 1; lists[i].resize(length); for (int j = 0; j < length; ++j) cin >> lists[i][j], --lists[i][j]; sort((lists[i]).begin(), (lists[i]).end()); } vector<vector<int> > intersectionSize(m, vector<int>(heavyCount, 0)); for (int i = 0; i < (lists).size(); ++i) for (int j = 0; j < (heavyListsIds).size(); ++j) { int first = i, second = heavyListsIds[j]; if (first == second) continue; if ((lists[first]).size() > (lists[second]).size()) { int temp = first; first = second; second = temp; } for (int k = 0; k < (lists[first]).size(); ++k) if (binary_search(lists[second].begin(), lists[second].end(), lists[first][k])) ++intersectionSize[first][j]; } vector<long long> cachedResults(heavyCount, 0), cachedUpdates(heavyCount, 0); for (int i = 0; i < heavyCount; ++i) { int listId = heavyListsIds[i]; for (int j = 0; j < (lists[listId]).size(); ++j) cachedResults[i] += a[lists[listId][j]]; } for (int i = 0; i < q; ++i) { char c; cin >> c; if (c == + ) { long long k, x; cin >> k >> x; --k; if (weights[k] == 42) { int heavy_k = 0; for (int j = 0; j < heavyCount; ++j) if (heavyListsIds[j] == k) { heavy_k = j; break; } cachedUpdates[heavy_k] += x; } else { for (int j = 0; j < (lists[k]).size(); ++j) a[lists[k][j]] += x; for (int j = 0; j < heavyCount; ++j) cachedResults[j] += intersectionSize[k][j] * x; } } else { int k; cin >> k; --k; if (weights[k] == 1) { long long result = 0; for (int j = 0; j < (lists[k]).size(); ++j) result += a[lists[k][j]]; for (int j = 0; j < heavyCount; ++j) result += intersectionSize[k][j] * cachedUpdates[j]; cout << result << endl; } else { int heavy_k = 0; for (int j = 0; j < heavyCount; ++j) if (heavyListsIds[j] == k) { heavy_k = j; break; } long long result = cachedResults[heavy_k] + cachedUpdates[heavy_k] * (lists[k]).size(); for (int j = 0; j < heavyCount; ++j) result += intersectionSize[k][j] * cachedUpdates[j]; cout << result << endl; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A32O_PP_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; long long ans = 0; long long L = -4 * 45, R = 45; map<long long, long long> vls; for (long long i = L; i <= R; i++) vls[i] = 1e18; for (long long i = 0; i < 100; i++) { for (long long j = 0; j < 100; j++) { for (long long k = 0; k < 100; k++) { long long nm = -4 * i + 5 * j + 45 * k; if (nm >= L && nm <= R) vls[nm] = min(vls[nm], i + j + k); } } } for (long long i = L; i <= R; i++) { if (vls[i] <= n) { ans++; } } for (long long i = L; i < L + 4; i++) { long long op = vls[i]; if (op < n) ans += n - op; } for (long long i = R - 44; i <= R; i++) { long long op = vls[i]; if (op < n) ans += n - op; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, n, m, k, a, b; long long x[3], y[3]; for (i = 0; i < 3; i++) cin >> x[i] >> y[i]; cout << 3 << endl; for (i = 0; i < 3; i++) cout << (x[i] + x[(i + 1) % 3]) - x[(i + 2) % 3] << << (y[i] + y[(i + 1) % 3]) - y[(i + 2) % 3] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int L[100007], R[100007]; int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , L + i, R + i); } sort(L + 1, L + n + 1); sort(R + 1, R + n + 1); long long ans = 0; for (int i = 1; i <= n; i++) { ans += max(L[i], R[i]); } printf( %I64d n , ans + n); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:16:03 03/03/2016
// Design Name:
// Module Name: data_memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_memory( memclock_in,address,writeData,memWrite,memRead,readData);
input memclock_in;
input [31:0] address;
input [31:0] writeData;
input memWrite;
input memRead;
output [31:0] readData;
reg [31:0] memFile[0:127];
reg [31:0] readData;
integer i;
initial
begin
//$readmemh("data.txt",memFile, 8'h0);
memFile[0] = 32'h00000000;
memFile[1] = 32'h00000001;
memFile[2] = 32'h00000002;
memFile[3] = 32'h00000003;
memFile[4] = 32'h00000004;
memFile[5] = 32'h00000005;
memFile[6] = 32'h00000006;
memFile[7] = 32'h00000007;
memFile[8] = 32'h00000008;
memFile[9] = 32'h00000009;
memFile[10] = 32'h0000000a;
memFile[11] = 32'h0000000b;
memFile[12] = 32'h0000000c;
memFile[13] = 32'h0000000d;
memFile[14] = 32'h0000000e;
memFile[15] = 32'h0000000f;
memFile[16] = 32'h00000010;
memFile[17] = 32'h00000011;
memFile[18] = 32'h00000012;
memFile[19] = 32'h00000013;
memFile[20] = 32'h00000014;
memFile[21] = 32'h00000015;
memFile[22] = 32'h00000016;
memFile[23] = 32'h00000017;
memFile[24] = 32'h00000018;
memFile[25] = 32'h00000019;
memFile[26] = 32'h0000001a;
memFile[27] = 32'h0000001b;
memFile[28] = 32'h0000001c;
memFile[29] = 32'h0000001d;
memFile[30] = 32'h0000001e;
memFile[31] = 32'h0000001f;
end
always @ (memRead or address or memWrite) //Ïò´æ´¢Æ÷ÖжÁÊý¾Ý
begin
readData = memFile[address];
end
always @ (negedge memclock_in) //Ïò´æ´¢Æ÷ÖÐдÊý¾Ý
begin
if(memWrite)
memFile[address] = writeData;
end
endmodule
|
#include <bits/stdc++.h> const int MX = 2e6 + 7; const int N = 1e9 + 1; const int mod = 998244353; const double pi = acos(-1); double esp = 1e-13; using namespace std; long long qpow(long long a, long long b, long long MOD = mod) { for (long long ans = 1;; a = a * a % MOD, b >>= 1) { if (b & 1) ans = ans * a % MOD; if (!b) return ans; } } long long inv(long long a, long long MOD = mod) { return qpow(a, MOD - 2, MOD); } long long exgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1, y = 0; return a; } long long ret = exgcd(b, a % b, y, x); y -= a / b * x; return ret; } long long getInv(int a, int mod) { long long x, y; long long d = exgcd(a, mod, x, y); return d == 1 ? (x % mod + mod) % mod : -1; } long long add(long long a, long long b) { long long ans = (a + b) % mod; return ans >= 0 ? ans : ans + mod; } void mul(long long &a, long long b) { a = a % mod * (b % mod) % mod; } int main() { ios::sync_with_stdio(0), cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; priority_queue<pair<int, int>> Q; for (int i = 1; i <= n; i++) { int x; cin >> x; Q.push(make_pair(x, i)); } int tmp = 0, res = 0; while (!Q.empty()) { auto x = Q.top(); Q.pop(); if (x.second == res) { if (Q.empty()) { break; } else { tmp++; auto y = Q.top(); Q.pop(); y.first--; if (y.first != 0) Q.push(y); res = y.second; Q.push(x); } } else { tmp++; x.first--; if (x.first != 0) Q.push(x); res = x.second; } } cout << (tmp % 2 == 0 ? HL : T ) << n ; } }
|
#include <bits/stdc++.h> using namespace std; set<int> Tmp, Trans; int dp[(500 + 5)][(500 + 5)], n, m, A[(500 + 5)], B[(500 + 5)]; int from[(500 + 5)][(500 + 5)][2], rkA[(500 + 5)], rkB[(500 + 5)]; int trans[(500 + 5)][(500 + 5)]; int getrk(int x) { int TP = 0; for (set<int>::iterator i = Trans.begin(); i != Trans.end(); ++i) { ++TP; if (*i == x) return TP; } return -1; } void output(int x, int y) { if (y == 0 || x == 0) return; output(from[x][y][0], from[x][y][1]); cout << B[y] << ; } int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> A[i]; Tmp.insert(A[i]); } cin >> m; for (int i = 1; i <= m; ++i) { cin >> B[i]; if (Tmp.find(B[i]) != Tmp.end()) Trans.insert(B[i]); } for (int i = 1; i <= n; ++i) { if (Trans.find(A[i]) != Trans.end()) rkA[i] = getrk(A[i]); else rkA[i] = 0; } for (int i = 1; i <= m; ++i) { if (Trans.find(B[i]) != Trans.end()) rkB[i] = getrk(B[i]); else rkB[i] = 0; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= (int)Trans.size(); ++j) { trans[i][j] = max(trans[i - 1][j], (rkA[i] == j) * i); } } for (int x = 1; x <= n; ++x) { for (int i = 1; i <= m; ++i) { if (A[x] != B[i]) continue; for (int k = 0; k < i; ++k) { if (rkB[k] >= rkB[i]) continue; if (dp[trans[x - 1][rkB[k]]][k] + 1 > dp[x][i]) { dp[x][i] = dp[trans[x - 1][rkB[k]]][k] + 1; from[x][i][0] = trans[x - 1][rkB[k]]; from[x][i][1] = k; } } } } int Ans = 0, x, y, z; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (A[i] == B[j] && dp[i][j] > Ans) { Ans = dp[i][j]; x = i, y = j; } } } cout << Ans << endl; if (Ans != 0) output(x, y); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 11:05:08 05/26/2016
// Design Name:
// Module Name: microcontrolador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module microcontrolador
(
input wire clk, reset,
input wire interrupt,
input wire [7:0] in_port,
output wire write_strobe, k_write_strobe, read_strobe,
output wire interrupt_ack,
output wire [7:0] port_id,
output wire [7:0] out_port
);
//Conexiones entre la memoria de programa y el kcpsm6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
assign kcpsm6_reset = reset | rdl;
assign kcpsm6_sleep = 1'b0;
//Instanciaciones del procesador y la memoria de programa
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
instancia_processor(
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
ROM_programa #(
.C_FAMILY ("S6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (0)) //Include JTAG Loader when set to '1'
instancia_ROM_programa ( //Name to match your PSM file
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int i = 0; i < (n / 2); i++) printf( 01 ); if (n % 2) printf( 0 ); printf( n ); return 0; }
|
//*****************************************************************************
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// Description
// This module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_clock_synchronizer # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_NUM_STAGES = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire synch_in ,
output wire synch_out
);
////////////////////////////////////////////////////////////////////////////////
// Local Parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
xpm_cdc_single #(
.DEST_SYNC_FF ( C_NUM_STAGES ) ,
.SRC_INPUT_REG ( 0 ) ,
.SIM_ASSERT_CHK ( 0 )
)
inst_xpm_cdc_single (
.src_clk ( 1'b0 ) ,
.src_in ( synch_in ) ,
.dest_out ( synch_out ) ,
.dest_clk ( clk )
);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 100; class Node { public: int l, r; bool operator<(const Node &a) const { return r < a.r; } }; Node n[maxn]; int main() { int N; scanf( %d , &N); for (int i = 0; i < N; i++) scanf( %d%d , &n[i].l, &n[i].r); sort(n, n + N); int ans = 1, ps = 0; for (int i = 1; i < N; i++) if (n[i].l > n[ps].r) { ans++; ps = i; } printf( %d n , ans); }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate repeat concatenation literal behavior.
//
module test ();
wire [7:0] result;
assign result = {2{4'b1011}};
initial
begin
#1;
if(result === 8'b10111011)
$display("PASSED");
else
$display("FAILED - {2{4'b1011}} s/b 8'b10111011 - is %b",result);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7; const long long inf = 1e17 + 7; pair<long long, long long> a[maxn]; pair<long long, long long> A[maxn]; pair<pair<long long, long long>, pair<long long, long long> > S[maxn]; int pos; inline long long elf(pair<long long, long long> z, long long x) { return z.first * x + z.second; } inline long long earl(pair<long long, long long> z, long long v) { long long a = z.first, b = z.second; long long x = (v - b) / a; if (a * x >= v - b) return x; return x + 1; } inline long double intx(pair<long long, long long> l1, pair<long long, long long> l2) { long long a1 = l1.first, a2 = l2.first, b1 = l1.second, b2 = l2.second; return (long double)(b2 - b1) / (long double)(a1 - a2); } void ins(long long a, long long b) { while (pos >= 2 && intx(S[pos].first, S[pos - 1].first) >= intx(make_pair(a, b), S[pos].first)) pos--; S[pos].second.second = ceil(intx(S[pos].first, make_pair(a, b))) - 1; pos++; S[pos] = make_pair(make_pair(a, b), make_pair(ceil(intx(S[pos - 1].first, make_pair(a, b))), inf)); } int main() { int n; long long s; scanf( %d %lld , &n, &s); for (int i = 1; i <= n; i++) { scanf( %lld %lld , &a[i].first, &a[i].second); } sort(a + 1, a + n + 1); a[0].first = -1; long long cur = -1; long long best = inf; int idx = 0; for (int i = n; i >= 0; i--) { if (a[i].first != cur) { if (cur > 0) { idx++; A[idx] = make_pair(cur, best); } cur = a[i].first; best = inf; } best = min(best, a[i].second); } n = idx; for (int i = 1; i <= n; i++) a[i] = A[i]; best = inf; idx = 0; for (int i = 1; i <= n; i++) { if (a[i].second >= best) continue; idx++; A[idx] = a[i]; best = min(best, a[i].second); } n = idx; reverse(A + 1, A + n + 1); long long ans = inf; pos = 1; S[pos] = make_pair(make_pair(A[1].first, 0), make_pair(0, inf)); int fp = 1; for (int i = 2; i <= n; i++) { while (fp < pos && elf(S[fp].first, S[fp].second.second) < A[i].second) fp++; long long cx = earl(S[fp].first, A[i].second); long long fcx = elf(S[fp].first, cx); ins(A[i].first, fcx - A[i].second - A[i].first * cx); fp = min(fp, pos); } for (int i = 1; i <= pos; i++) { ans = min(ans, earl(S[i].first, s)); } printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; bool forms(long long a, long long b, long long c) { if ((a * a) + (b * b) == (c * c)) return true; return false; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t, n; cin >> t; while (t--) { cin >> n; cout << n / 2 << endl; } return 0; }
|
module testbench();
parameter NO_GPIO = 8;
parameter SO_GPIO = 8;
parameter EA_GPIO = 8;
parameter WE_GPIO = 8;
parameter NO_DOMAINS = 2;
parameter SO_DOMAINS = 2;
parameter EA_DOMAINS = 2;
parameter WE_DOMAINS = 2;
// Beginning of automatic inputs (from unused autoinst inputs)
wire [EA_GPIO*8-1:0] ea_cfg; // To i0 of oh_padring.v
wire [EA_GPIO-2:0] ea_dout; // To i0 of oh_padring.v
wire [EA_GPIO-1:0] ea_ie; // To i0 of oh_padring.v
wire [EA_GPIO-1:0] ea_oen; // To i0 of oh_padring.v
wire [NO_GPIO*8-1:0] no_cfg; // To i0 of oh_padring.v
wire [NO_GPIO-2:0] no_dout; // To i0 of oh_padring.v
wire [NO_GPIO-1:0] no_ie; // To i0 of oh_padring.v
wire [NO_GPIO-1:0] no_oen; // To i0 of oh_padring.v
wire [SO_GPIO*8-1:0] so_cfg; // To i0 of oh_padring.v
wire [SO_GPIO-2:0] so_dout; // To i0 of oh_padring.v
wire [SO_GPIO-1:0] so_ie; // To i0 of oh_padring.v
wire [SO_GPIO-1:0] so_oen; // To i0 of oh_padring.v
wire [WE_GPIO*8-1:0] we_cfg; // To i0 of oh_padring.v
wire [WE_GPIO-2:0] we_dout; // To i0 of oh_padring.v
wire [WE_GPIO-1:0] we_ie; // To i0 of oh_padring.v
wire [WE_GPIO-1:0] we_oen; // To i0 of oh_padring.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [EA_GPIO-1:0] ea_din; // From i0 of oh_padring.v
wire [EA_GPIO-1:0] ea_pad; // To/From i0 of oh_padring.v
wire [EA_DOMAINS-1:0] ea_vddio; // To/From i0 of oh_padring.v
wire [EA_DOMAINS-1:0] ea_vssio; // To/From i0 of oh_padring.v
wire [NO_GPIO-1:0] no_din; // From i0 of oh_padring.v
wire [NO_GPIO-1:0] no_pad; // To/From i0 of oh_padring.v
wire [NO_DOMAINS-1:0] no_vddio; // To/From i0 of oh_padring.v
wire [NO_DOMAINS-1:0] no_vssio; // To/From i0 of oh_padring.v
wire [SO_GPIO-1:0] so_din; // From i0 of oh_padring.v
wire [SO_GPIO-1:0] so_pad; // To/From i0 of oh_padring.v
wire [SO_DOMAINS-1:0] so_vddio; // To/From i0 of oh_padring.v
wire [SO_DOMAINS-1:0] so_vssio; // To/From i0 of oh_padring.v
wire vdd; // To/From i0 of oh_padring.v
wire vss; // To/From i0 of oh_padring.v
wire [WE_GPIO-1:0] we_din; // From i0 of oh_padring.v
wire [WE_GPIO-1:0] we_pad; // To/From i0 of oh_padring.v
wire [WE_DOMAINS-1:0] we_vddio; // To/From i0 of oh_padring.v
wire [WE_DOMAINS-1:0] we_vssio; // To/From i0 of oh_padring.v
// End of automatics
oh_padring #(.TYPE("SOFT"),
.NO_DOMAINS(NO_DOMAINS),
.NO_GPIO(NO_GPIO),
.SO_DOMAINS(SO_DOMAINS),
.SO_GPIO(SO_GPIO),
.EA_DOMAINS(EA_DOMAINS),
.EA_GPIO(EA_GPIO),
.WE_DOMAINS(WE_DOMAINS),
.WE_GPIO(WE_GPIO))
i0 (/*AUTOINST*/
// Outputs
.no_din (no_din[NO_GPIO-1:0]),
.so_din (so_din[SO_GPIO-1:0]),
.ea_din (ea_din[EA_GPIO-1:0]),
.we_din (we_din[WE_GPIO-1:0]),
// Inouts
.vss (vss),
.vdd (vdd),
.no_vddio (no_vddio[NO_DOMAINS-1:0]),
.no_vssio (no_vssio[NO_DOMAINS-1:0]),
.no_pad (no_pad[NO_GPIO-1:0]),
.so_vddio (so_vddio[SO_DOMAINS-1:0]),
.so_vssio (so_vssio[SO_DOMAINS-1:0]),
.so_pad (so_pad[SO_GPIO-1:0]),
.ea_vddio (ea_vddio[EA_DOMAINS-1:0]),
.ea_vssio (ea_vssio[EA_DOMAINS-1:0]),
.ea_pad (ea_pad[EA_GPIO-1:0]),
.we_vddio (we_vddio[WE_DOMAINS-1:0]),
.we_vssio (we_vssio[WE_DOMAINS-1:0]),
.we_pad (we_pad[WE_GPIO-1:0]),
// Inputs
.no_dout (no_dout[NO_GPIO-1-1:0]),
.no_cfg (no_cfg[NO_GPIO*8-1:0]),
.no_ie (no_ie[NO_GPIO-1:0]),
.no_oen (no_oen[NO_GPIO-1:0]),
.so_dout (so_dout[SO_GPIO-1-1:0]),
.so_cfg (so_cfg[SO_GPIO*8-1:0]),
.so_ie (so_ie[SO_GPIO-1:0]),
.so_oen (so_oen[SO_GPIO-1:0]),
.ea_dout (ea_dout[EA_GPIO-1-1:0]),
.ea_cfg (ea_cfg[EA_GPIO*8-1:0]),
.ea_ie (ea_ie[EA_GPIO-1:0]),
.ea_oen (ea_oen[EA_GPIO-1:0]),
.we_dout (we_dout[WE_GPIO-1-1:0]),
.we_cfg (we_cfg[WE_GPIO*8-1:0]),
.we_ie (we_ie[WE_GPIO-1:0]),
.we_oen (we_oen[WE_GPIO-1:0]));
initial
begin
$dumpvars;
#1000 $finish;
end
endmodule // top
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
|
module uc(input wire clock,reset,z, input wire [1:0] id_out, input wire [5:0] opcode,
output reg s_inc, s_inm, we3, rwe1, rwe2, rwe3, rwe4, sec, sece, s_es, s_rel, swe, s_ret, output wire [2:0] op);
assign op = opcode[2:0];
always @(*)
begin
rwe1 <= 1'b0; //Desactivar puertos de E/S
rwe2 <= 1'b0; //Desactivar puertos de E/S
rwe3 <= 1'b0; //Desactivar puertos de E/S
rwe4 <= 1'b0; //Desactivar puertos de E/S
swe <= 1'b0; //desactivar registro especial(subrutina)
s_ret <= 1'b0; //no tomar valor de retorno
sece <= 1'b0; //Desactivar Salida de E/S
if (reset == 1'b1)
begin
we3 <= 1'b0; //No escribir en el banco de registros
s_inm <= 1'b0; //Da igual el valor, no se trabaja con registros
s_inc <= 1'b1; //Para que el PC coja la siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
swe <= 1'b0; //desactivar registro especial(subrutina)
s_ret <= 1'b0; //no tomar valor de retorno
end
else
begin
casex (opcode)
// Instrucciones ariméticas (4ºbit a 0)
6'bxx0xxx:
begin
//op <= opcode[2:0]; //Código de operación de ALU
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b0; //Escoger resultado de la ALU
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: Carga Inmediata
6'bxx1010:
begin
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b1; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: Salto Incondicional
6'bxx1001:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
s_inc <= 1'b0; //Escoger el salto indicado
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
end
// Instrucción: LES cargar desde E/S
6'bxx1011:
begin
we3 <= 1'b1; //Permitir escritura en registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registro
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b1; //Activar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Instrucción: PRINT muestra por pantalla un registro
// 6'bxx1100:
// begin
// // we3 <= 1'b0; // No trabaja con registros
// // s_inm <= 1'b0; // Da igual el valor porque no se trabaja con registro
// // sec <= 1'b1; // Se envia a la E/S desde un registro
// // s_es <= 1'b0; //Desactivar entrada desde E/S
// // s_inc <= 1'b1; //Siguiente instrucción
// // s_rel <= 1'b0; //Despreciar salto relativo
// // rwe1 <= 1'b1;
// // rwe2 <= 1'b1;
// // rwe3 <= 1'b1;
// // rwe4 <= 1'b1;
// end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Instrucción: Envia a la E/S desde el registro
6'bxx1101:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b1; //A 1 = Registro
sece <= 1'b1; //Activar Salida de E/S
s_es <= 1'b0; //Desctivar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
if (id_out == 2'b00)
rwe1 <= 1'b1;
else if(id_out == 2'b01)
rwe2 <= 1'b1;
else if(id_out == 2'b10)
rwe3 <= 1'b1;
else
rwe4 <= 1'b1;
end
// Instrucción: Envia a la E/S desde la memoria
6'bxx1110:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //A 0 = Memoria
sece <= 1'b1; //Activar Salida de E/S
s_es <= 1'b0; //Desctivar entrada desde E/S
s_inc <= 1'b1; //Siguiente instrucción
s_rel <= 1'b0; //Despreciar salto relativo
if (id_out == 2'b00)
rwe1 <= 1'b1;
else if(id_out == 2'b01)
rwe2 <= 1'b1;
else if(id_out == 2'b10)
rwe3 <= 1'b1;
else
rwe4 <= 1'b1;
end
// Instrucción: Salto Condicional (si z=0)
6'b011111:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
if (z == 1'b0)
s_inc <= 1'b0; //Saltar
else
s_inc <= 1'b1; //Siguiente instrucćión
end
// Instrucción: Salto Condicional (si z=1)
6'b001111:
begin
we3 <= 1'b0; //No trabaja con registros
s_inm <= 1'b0; //Da igual el valor porque no se trabaja con registros
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Despreciar salto relativo
if (z == 1'b0)
s_inc <= 1'b1; //Siguiente instrucción
else
s_inc <= 1'b0; //Saltar
end
//Instrucción: Salto relativo
6'b011000:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger el salto relativo
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b1; //Escoger salto relativo
end
//Instrucción: Salto a subrutina
6'b101000:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b0; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Escoger siguiente instrucción
swe <= 1'b1; //activar registro especial(subrutina)
end
//Instrucción: Retorno subrutina
6'b111000:
begin
we3 <= 1'b0; //denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b0; //da igual
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //Da igual
s_ret <= 1'b1; //Tomar el valor de retorno
end
//Instrucción: NOP
6'b111111:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //No activar salto relativo
s_ret <= 1'b0; //No tomar el valor de retorno
end
default:
begin
we3 <= 1'b0; //Denegar escritura en registros
s_inm <= 1'b0; //La ALU no nos interesa
s_inc <= 1'b1; //Escoger siguiente instrucción
sec <= 1'b0; //Da igual
sece <= 1'b0; //Desactivar Salida de E/S
s_es <= 1'b0; //Desactivar E/S
s_rel <= 1'b0; //No activar salto relativo
s_ret <= 1'b0; //No tomar el valor de retorno
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int n, k, a[1010][1010]; vector<pair<int, int>> ans; int main() { int is = 0; ans.clear(); memset(a, 0, sizeof(a)); cin >> n >> k; for (int i = 1; i <= n; ++i) { int cnt = 0; for (int j = 1; j <= n; ++j) { if (i == j) continue; if (cnt == k) break; if (a[j][i] == 0) { a[i][j] = 1; ++cnt; ans.push_back({i, j}); } } if (cnt != k) { cout << -1 ; return 0; } } if (!is) { cout << ans.size() << n ; for (auto i : ans) { cout << i.first << << i.second << n ; } } }
|
// CPU and memory bundled together,
// exposing the UART bare wires
module tiny1_cpu(
input clk,
input rst, // external reset button
input [7:0] uart_din,
input uart_valid,
input uart_ready,
output [7:0] uart_out,
output uart_rd,
output uart_wr,
output reg [7:0] leds
);
wire [15:0] for_mem_addr;
wire [15:0] for_mem_data_i_ram;
wire [15:0] for_mem_data_o;
wire for_mem_wr;
wire for_mem_re;
// 16kb ram, one for all of the following:
// 16x16 virtual registers
// 16x16 IRQ mode virtual registers
// 32x16 microcode handlers table
// large microcode buffer
// and everything else
ram16k ram(.clk(clk),
.addr(for_mem_addr[14:1]),
.data_out(for_mem_data_i_ram),
.data_in(for_mem_data_o),
.we(for_mem_wr),
.re(for_mem_re));
// May be a memory-mapped I/O instead of a genuine memory access
wire mem_wr_from_core;
wire mem_re_from_core;
// Thin UART interface via mmap
wire irqack;
wire [15:0] mem_data_i_for_core;
wire [15:0] mem_data_o_from_core;
wire [15:0] mem_addr_from_core;
assign for_mem_addr = mem_addr_from_core;
assign for_mem_data_o = mem_data_o_from_core;
reg irq;
tiny1_core cpu(.clk(clk),
.rst(rst),
.irq(/*irq*/ 1'b0),
.irqack(irqack),
.mem_addr(mem_addr_from_core),
.mem_data_o(mem_data_o_from_core),
.mem_data_i(mem_data_i_for_core),
.ram_data_i(for_mem_data_i_ram),
.mem_wr(mem_wr_from_core),
.mem_rd(mem_re_from_core));
reg [15:0] mem_data_i_mmap;
wire [15:0] data_i_mmap_cl;
wire mmap;
assign mmap = mem_addr_from_core[15]; // if bit 15 set, it's mmap io
assign for_mem_wr = !mmap?mem_wr_from_core:0;
assign for_mem_re = !mmap?mem_re_from_core:0;
assign mem_data_i_for_core = mmap?mem_data_i_mmap:for_mem_data_i_ram;
// IRQ logic:
// if uart_valid && !irqack, set IRQ
// mmap io:
// Read ports:
// IO_UART_VALID - valid input from UART
// IO_UART_DIN - 8 bits from UART
// IO_UART_READY - 1 if ready to send
// Write ports:
// IO_UART_DOUT - 8 bits to UART
parameter IO_UART_VALID = 0;
parameter IO_UART_DIN = 2;
parameter IO_UART_READY = 4;
parameter IO_UART_DOUT = 6;
parameter IO_LEDS = 8;
wire [10:0] mmapaddr;
assign mmapaddr = mem_addr_from_core[10:0];
assign data_i_mmap_cl = (mmapaddr == IO_UART_VALID)?{15'b0, uart_valid}:
(mmapaddr == IO_UART_DIN)?{8'b0,uart_din}:
(mmapaddr == IO_UART_READY)?{15'b0, uart_ready}:16'b0;
assign uart_wr = (mmap && mmapaddr == IO_UART_DOUT && mem_wr_from_core);
assign uart_rd = (mmap && mmapaddr == IO_UART_DIN && mem_re_from_core);
assign uart_out = mem_data_o_from_core[7:0];
// register the mmap output
always @(posedge clk)
begin
mem_data_i_mmap <= data_i_mmap_cl;
if (mmap && mmapaddr == IO_LEDS && mem_wr_from_core) begin
leds[7:0] <= mem_data_o_from_core[7:0];
end
end
always @(posedge clk)
if (!rst) begin
irq <= 0;
end else begin
if (!irq && uart_valid) begin
irq <= 1;
end else if (irq && irqack) begin
irq <= 0;
end
end
endmodule
module tiny1_soc(
input clk,
input rst, // external reset button
input RXD,
output TXD,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
`ifndef ICESTICK
,output LED6,
output LED7,
output LED8
`endif
);
reg [7:0] resetn_counter = 0;
wire resetn = &resetn_counter;
always @(posedge clk) begin
if (!resetn)
resetn_counter <= resetn_counter + 1;
end
wire [7:0] leds;
wire [7:0] rleds;
outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(leds[0]), .rd(rleds[0]));
outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(leds[1]), .rd(rleds[1]));
outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(leds[2]), .rd(rleds[2]));
outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(leds[3]), .rd(rleds[3]));
outpin led4 (.clk(clk), .we(1'b1), .pin(LED5), .wd(leds[4]), .rd(rleds[4]));
`ifndef ICESTICK
outpin led5 (.clk(clk), .we(1'b1), .pin(LED6), .wd(leds[5]), .rd(rleds[5]));
outpin led6 (.clk(clk), .we(1'b1), .pin(LED7), .wd(leds[6]), .rd(rleds[6]));
outpin led7 (.clk(clk), .we(1'b1), .pin(LED8), .wd(leds[7]), .rd(rleds[7]));
`endif
wire [7:0] uart_din;
wire uart_valid;
wire uart_ready;
wire uart_wr;
wire uart_rd;
wire [7:0] uart_dout;
tiny1_cpu cpu(.clk(clk),
.rst(resetn),
.uart_din(uart_din),
.uart_valid(uart_valid),
.uart_ready(uart_ready),
.uart_out(uart_dout),
.uart_rd(uart_rd),
.uart_wr(uart_wr),
.leds(leds)
);
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));
wire uart_busy;
assign uart_ready = ~uart_busy;
buart _uart (
.clk(clk),
.resetq(1'b1),
.rx(uart_RXD),
.tx(TXD),
.rd(uart_rd),
.wr(uart_wr),
.valid(uart_valid),
.busy(uart_busy),
.tx_data(uart_dout),
.rx_data(uart_din));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O32AI_PP_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; char s1[1010], s2[1010]; int dp[1010][1010][15][2], n, m, k; int main() { scanf( %d%d%d , &n, &m, &k); scanf( %s%s , s1, s2); for (int i = 1; i <= k; i++) { for (int j1 = 1; j1 <= n; j1++) { for (int j2 = 1; j2 <= m; j2++) { if (s1[j1 - 1] == s2[j2 - 1]) { dp[j1][j2][i][1] = 1 + max(dp[j1 - 1][j2 - 1][i][1], max(dp[j1 - 1][j2 - 1][i - 1][0], dp[j1 - 1][j2 - 1][i - 1][1])); } dp[j1][j2][i][0] = max(dp[j1 - 1][j2][i][1], dp[j1 - 1][j2][i][0]); dp[j1][j2][i][0] = max(max(dp[j1][j2 - 1][i][1], dp[j1][j2 - 1][i][0]), dp[j1][j2][i][0]); } } } int ans = max(dp[n][m][k][1], dp[n][m][k][0]); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > upd; struct query { int l, r, t, id, ans; query() {} query(int _l, int _r, int _t, int _id) { l = _l; r = _r; t = _t; id = _id; } }; vector<query> que; stack<pair<int, int> > S; vector<int> V; int M[1005][105]; int sz[1005]; int cnt[300005]; int data[100005]; int B; int l = 1, r = 0, t = 0, Ans = 1; int cmp(query a, query b) { if (a.l / B != b.l / B) return a.l < b.l; if (a.r / B != b.r / B) return a.r < b.r; return a.t < b.t; } int cmpid(query a, query b) { return a.id < b.id; } int Upd() { for (int i = (Ans / 100); i < (1000); i++) if (sz[i] < 100) { for (int j = (0); j < (100); j++) if (!M[i][j]) { return i * 100 + j; } } } void Add(int a) { if (!M[a / 100][a % 100]) sz[a / 100]++; M[a / 100][a % 100]++; if (Ans == a) Ans = Upd(); } void Del(int a) { M[a / 100][a % 100]--; if (!M[a / 100][a % 100]) { sz[a / 100]--; if (Ans > a) Ans = a; } } void add(int a) { Del(cnt[a]); Add(++cnt[a]); } void del(int a) { Del(cnt[a]); Add(--cnt[a]); } int main() { M[0][0] = 1e9; int n, m; scanf( %d%d , &n, &m); B = pow(n, 2.0 / 3); for (int i = (1); i < (n + 1); i++) scanf( %d , &data[i]), V.push_back(data[i]); while (m--) { int co, a, b; scanf( %d%d%d , &co, &a, &b); if (co == 1) que.push_back(query(a, b, (int)(upd).size(), (int)(que).size())); else upd.push_back(make_pair(a, b)), V.push_back(b); } sort(V.begin(), V.end()); V.erase(unique(V.begin(), V.end()), V.end()); for (int i = (1); i < (n + 1); i++) data[i] = lower_bound(V.begin(), V.end(), data[i]) - V.begin() + 1; for (int i = (0); i < ((int)(upd).size()); i++) upd[i].second = lower_bound(V.begin(), V.end(), upd[i].second) - V.begin() + 1; sort(que.begin(), que.end(), cmp); for (int i = (0); i < ((int)(que).size()); i++) { while (l > que[i].l) { l--; add(data[l]); } while (r < que[i].r) { r++; add(data[r]); } while (r > que[i].r) { del(data[r]); r--; } while (l < que[i].l) { del(data[l]); l++; } while (t < que[i].t) { int pos = upd[t].first; S.push(make_pair(pos, data[pos])); if (l <= pos && pos <= r) del(data[pos]); data[pos] = upd[t].second; if (l <= pos && pos <= r) add(data[pos]); t++; } while (t > que[i].t) { t--; int pos = S.top().first; if (l <= pos && pos <= r) del(data[pos]); data[pos] = S.top().second; if (l <= pos && pos <= r) add(data[pos]); S.pop(); } que[i].ans = Ans; } sort(que.begin(), que.end(), cmpid); for (int i = (0); i < ((int)(que).size()); i++) printf( %d n , que[i].ans); return 0; }
|
`define bsg_mux_one_hot_gen_macro(words,bits) \
if (harden_p && els_p == words && width_p == bits) \
begin: macro \
bsg_rp_tsmc_250_mux_w``words``_b``bits w``words``_b``bits \
(.* \
); \
end
module bsg_mux_one_hot #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [els_p-1:0] sel_one_hot_i
,output [width_p-1:0] data_o
);
wire [els_p-1:0][width_p-1:0] data_masked;
genvar i,j;
`bsg_mux_one_hot_gen_macro(3,14)
else
`bsg_mux_one_hot_gen_macro(3,4)
else
begin : notmacro
for (i = 0; i < els_p; i++)
begin : mask
assign data_masked[i] = data_i[i] & { width_p { sel_one_hot_i[i] } };
end
for (i = 0; i < width_p; i++)
begin: reduce
wire [els_p-1:0] gather;
for (j = 0; j < els_p; j++)
assign gather[j] = data_masked[j][i];
assign data_o[i] = | gather;
end
end
endmodule // bsg_mux_one_hot
`BSG_ABSTRACT_MODULE(bsg_mux_one_hot)
|
#include <bits/stdc++.h> template <class T> inline void checkmax(T &x, T y) { if (x < y) x = y; } template <class T> inline void checkmin(T &x, T y) { if (x > y) x = y; } template <class T> inline T Min(T x, T y) { return (x > y ? y : x); } template <class T> inline T Max(T x, T y) { return (x < y ? y : x); } using namespace std; vector<int> a[111111], ans; int n, m, b[111111], c[111111]; int main() { while (scanf( %d%d , &n, &m) == 2) { for (int i = 1; i <= n; ++i) a[i].clear(); ans.clear(); memset(c, 0, sizeof(c)); for (int i = 1; i <= m; ++i) { int u, v; scanf( %d%d , &u, &v); a[u].push_back(v); a[v].push_back(u); } for (int i = 1; i <= n; ++i) scanf( %d , b + i); queue<int> q; for (int i = 1; i <= n; ++i) if (!b[i]) q.push(i); while (!q.empty()) { int v = q.front(); q.pop(); if (b[v] == c[v]) ans.push_back(v); else continue; c[v]++; for (int i = 0; i < a[v].size(); ++i) { c[a[v][i]]++; if (b[a[v][i]] == c[a[v][i]]) q.push(a[v][i]); } } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); ++i) printf( %d , ans[i]); if (ans.size()) puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[256], n, k, p; cin >> n >> k; memset(a, -1, sizeof(a)); for (int i = 0; i < n; i++) { cin >> p; if (a[p] == -1) { for (int j = max(0, p - k + 1); j <= p; j++) if (a[j] == -1 || a[j] == j) { for (int x = j; x <= p; x++) a[x] = j; break; } } cout << a[p] << ; } }
|
#include <bits/stdc++.h> using namespace std; int const MOD = 1000000007; void add(int &a, int b) { a += b; if (a >= MOD) a -= MOD; } int f[42], when[42]; int main() { int n, k; scanf( %d%d , &n, &k); int s = 1; int c = getchar(); while (c <= 32) { c = getchar(); } int cn = 0; while (c > 32) { int olds = s; add(s, s); add(s, MOD - f[c - a ]); f[c - a ] = olds; when[c - a ] = ++cn; c = getchar(); } for (int i = 0; i < n; i++) { int v = -1; for (int j = 0; j < k; j++) { if (v < 0 || when[v] > when[j]) { v = j; } } when[v] = ++cn; int olds = s; add(s, s); add(s, MOD - f[v]); f[v] = olds; } printf( %d n , s); }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 100010; int n, parent[maxN], child[maxN]; long long f[maxN], g[maxN], res; struct ioi { int v, w; }; vector<ioi> adj[maxN]; void dfs(int u) { child[u] = 1; for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i].v; if (parent[u] == v) continue; parent[v] = u; dfs(v); child[u] = child[u] + child[v]; f[u] += ((adj[u][i].w) ? child[v] : f[v]); } } void dfs_g(int u) { for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i].v; if (parent[u] == v) continue; int tmp = ((adj[u][i].w) ? child[v] : f[v]); g[v] = (adj[u][i].w) ? (n - child[v]) : (f[u] + g[u] - tmp); dfs_g(v); } } bool check(int x) { while (x) { if (((x % 10) != 4) && ((x % 10) != 7)) return false; x /= 10; } return true; } int main() { scanf( %d , &n); for (int i = 1; i <= n - 1; ++i) { int u, v, w; scanf( %d%d%d , &u, &v, &w); w = check(w); ioi tmp; tmp.v = v; tmp.w = w; adj[u].push_back(tmp); tmp.v = u; tmp.w = w; adj[v].push_back(tmp); } dfs(1); dfs_g(1); for (int i = 1; i <= n; ++i) res += ((f[i] + g[i]) * (f[i] + g[i] - 1)); cout << res; fclose(stdin); fclose(stdout); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long by = (n / 2) + (n / 3) + (n / 5) + (n / 7) - (n / 6) - (n / 10) - (n / 14) - (n / 15) - (n / 35) - (n / 21); by += (n / 30) + (n / 42) + (n / 70) + (n / 105); by -= (n / 210); cout << n - by << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string str; cin >> str; set<char> a; for (int i = 0; i < n; i++) { a.insert(tolower(str[i])); } if (a.size() == 26) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:16:31 03/03/2016
// Design Name: signext
// Module Name: G:/ceshi/lab4.3/test_for_signext.v
// Project Name: lab4.3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: signext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_signext;
// Inputs
reg [15:0] inst;
// Outputs
wire [31:0] data;
// Instantiate the Unit Under Test (UUT)
signext uut (
.inst(inst),
.data(data)
);
initial begin
// Initialize Inputs
inst = 0;
// Wait 100 ns for global reset to finish
#100;
#100 inst = 16'b1111111100000000;
#100 inst = 16'b0000000000111111;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1e7 + 10, M = 998244353; int n, m, k, inv[Maxn], s[Maxn], idk[Maxn]; int mo2(int x) { return (x < 0) ? x + M : x; } int fpow(int a, int p = M - 2) { int ret = 1; for (; p; p >>= 1, a = 1ll * a * a % M) if (p & 1) ret = 1ll * ret * a % M; return ret; } void init(int n) { inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = M - 1ll * inv[M % i] * (M / i) % M; } void get_idk(int k) { for (int i = 0; i <= k; i++) idk[i] = fpow(i, k); } int main() { scanf( %d%d%d , &n, &m, &k); int p = fpow(m); init(k); s[k] = 1; int pw = 1, C = 1; for (int i = k - 1; i >= 0; i--) { pw = 1ll * pw * (M - p) % M; C = 1ll * C * (n - i - 1 + M) % M * inv[k - i] % M; s[i] = (1ll * (1 - p + M) * s[i + 1] + 1ll * C * pw) % M; } int E = 0; pw = C = 1; get_idk(k); for (int i = 1; i <= k; i++) { pw = 1ll * pw * p % M; C = 1ll * C * (n - i + 1 + M) % M * inv[i] % M; E = (E + 1ll * idk[i] * C % M * pw % M * s[i]) % M; } printf( %d n , E); return 0; }
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
//include "registers.v"
module oq_regs_dual_port_ram
#(
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter NUM_OUTPUT_QUEUES = 8,
parameter REG_FILE_ADDR_WIDTH = log2(NUM_OUTPUT_QUEUES)
)
(
input [REG_FILE_ADDR_WIDTH-1:0] addr_a,
input we_a,
input [REG_WIDTH-1:0] din_a,
output reg [REG_WIDTH-1:0] dout_a,
input clk_a,
input [REG_FILE_ADDR_WIDTH-1:0] addr_b,
input we_b,
input [REG_WIDTH-1:0] din_b,
output reg [REG_WIDTH-1:0] dout_b,
input clk_b
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Uncomment the following synthesis attribute to force the memory into
// Block RAM.
//
// Note: The attribute must appear immediately above the RAM register
// declaraion.
//
(* ram_style = "block" *)
reg [REG_WIDTH-1:0] ram[0:NUM_OUTPUT_QUEUES-1];
always @(posedge clk_a) begin
if (we_a)
ram[addr_a] <= din_a;
dout_a <= ram[addr_a];
end
always @(posedge clk_b) begin
if (we_b)
ram[addr_b] <= din_b;
dout_b <= ram[addr_b];
end
endmodule // oq_dual_port_num
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 06:09:53 PM
// Design Name: Seven Segment Master
// Module Name: segMaster
// Project Name: SD2017
// Description: This module receives an 4-digit hexadecimal number and displays it.
// DP is set "ON" when Invalid number received.
// Target Devices: Basys3
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module segMaster(
input clk,
input [15:0] num,
input [3:0] aen, // high = disable digit n
output [6:0] seg,
output [3:0] an,
output dp
);
reg [2:0] ctr = 0;
wire [1:0] i;
assign i = ctr [2:1];
wire [3:0] BCD;
assign BCD = (i == 0 ? num[3:0] : (i == 1 ? num[7:4] :(i == 2 ? num[11:8] : num[15:12] )));
reg [7:0] SevenSeg;
always @ (posedge clk)
case(BCD)
4'h0: SevenSeg = 8'b11000000;
4'h1: SevenSeg = 8'b11111001;
4'h2: SevenSeg = 8'b10100100;
4'h3: SevenSeg = 8'b10110000;
4'h4: SevenSeg = 8'b10011001;
4'h5: SevenSeg = 8'b10010010;
4'h6: SevenSeg = 8'b10000010;
4'h7: SevenSeg = 8'b11111000;
4'h8: SevenSeg = 8'b10000000;
4'h9: SevenSeg = 8'b10010000;
4'hA: SevenSeg = 8'b10001000;
4'hB: SevenSeg = 8'b10000011;
4'hC: SevenSeg = 8'b11000110;
4'hD: SevenSeg = 8'b10100001;
4'hE: SevenSeg = 8'b10000110;
4'hF: SevenSeg = 8'b10001110;
default: SevenSeg = 8'b01111111;
endcase
assign {dp, seg[6:0]} = SevenSeg;
always @ (posedge clk) begin
ctr = ctr + 1;
end
assign an[3] = aen[3] || ~ctr[0] || ~(i == 3);
assign an[2] = aen[2] || ~ctr[0] || ~(i == 2);
assign an[1] = aen[1] || ~ctr[0] || ~(i == 1);
assign an[0] = aen[0] || ~ctr[0] || ~(i == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_2_V
`define SKY130_FD_SC_MS__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_2_V
|
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long INFL = LLONG_MAX; int N, M, ans[200100], n, m; int main() { cin >> N >> M; n = m = 0; ans[0] = 0; n++; for (int(i) = 1; (i) <= (N + M - 1); (i)++) { if (i & 1) { if (ans[i - 1]) { if (n < N) { ans[i] = 0; n++; } else { ans[i] = 1; m++; } } else { if (m < M) { ans[i] = 1; m++; } else { ans[i] = 0; n++; } } } else { if (ans[i - 1]) { if (m < M) { ans[i] = 1; m++; } else { ans[i] = 0; n++; } } else { if (n < N) { ans[i] = 0; n++; } else { ans[i] = 1; m++; } } } } int s11 = 0; int s12 = 0; for (int(i) = 1; (i) <= (N + M - 1); (i)++) { if (ans[i - 1] == ans[i]) s11++; else s12++; } n = m = 0; ans[0] = 1; m++; for (int(i) = 1; (i) <= (N + M - 1); (i)++) { if (i & 1) { if (ans[i - 1]) { if (n < N) { ans[i] = 0; n++; } else { ans[i] = 1; m++; } } else { if (m < M) { ans[i] = 1; m++; } else { ans[i] = 0; n++; } } } else { if (ans[i - 1]) { if (m < M) { ans[i] = 1; m++; } else { ans[i] = 0; n++; } } else { if (n < N) { ans[i] = 0; n++; } else { ans[i] = 1; m++; } } } } int s21 = 0; int s22 = 0; for (int(i) = 1; (i) <= (N + M - 1); (i)++) { if (ans[i - 1] == ans[i]) s21++; else s22++; } if (s11 < s21) { cout << s21 << << s22 << endl; } else { cout << s11 << << s12 << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LFSR PRBS checker
*/
module lfsr_prbs_check #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// Initial state
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}},
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// bit-reverse input and output
parameter REVERSE = 0,
// invert input
parameter INVERT = 1,
// width of data input and output
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_valid,
output wire [DATA_WIDTH-1:0] data_out
);
/*
Fully parametrizable combinatorial parallel LFSR PRBS checker. Implements an unrolled LFSR
PRBS checker.
Ports:
clk
Clock input
rst
Reset input, set state to LFSR_INIT
data_in
PRBS data input (DATA_WIDTH bits)
data_in_valid
Shift input data through LFSR when asserted
data_out
Error output (DATA_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_INIT
Initial state of LFSR. Defaults to all 1s.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR output. Shifts MSB first by default, set REVERSE for LSB first.
INVERT
Bitwise invert PRBS input.
DATA_WIDTH
Specify width of output data bus.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT;
reg [DATA_WIDTH-1:0] output_reg = 0;
wire [DATA_WIDTH-1:0] lfsr_data;
wire [LFSR_WIDTH-1:0] lfsr_state;
assign data_out = output_reg;
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(1),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
lfsr_inst (
.data_in(INVERT ? ~data_in : data_in),
.state_in(state_reg),
.data_out(lfsr_data),
.state_out(lfsr_state)
);
always @(posedge clk) begin
if (rst) begin
state_reg <= LFSR_INIT;
output_reg <= 0;
end else begin
if (data_in_valid) begin
state_reg <= lfsr_state;
output_reg <= lfsr_data;
end
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "alu.syn.v"
`include "control.h"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/alu.sdf",a_l_u,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
r_A=128'h0102030405060708f00a0b0cff0eff00;
r_B=128'h01010202030303031004f505ff09fe10;
e_r=128'h00010006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000000; struct UnionFind { int par[MAX_N], ra[MAX_N]; void init(int n) { for (int(i) = 0; (i) < (n); (i)++) par[i] = i, ra[i] = 0; } int find(int x) { return par[x] == x ? x : par[x] = find(par[x]); } bool same(int x, int y) { return find(x) == find(y); } void unite(int x, int y) { if ((x = find(x)) != (y = find(y))) { if (ra[x] < ra[y]) swap(x, y); par[y] = x, ra[x] += (ra[x] == ra[y]); } } }; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long A, B; string a, b; int pp[1000000][26]; int sz[1000000]; UnionFind uf; int main() { scanf( %I64d%I64d , &A, &B); cin >> a >> b; long long al = a.size(), bl = b.size(); long long st = al * bl; st /= gcd(al, bl); uf.init(al); for (int(i) = 0; (i) < (al); (i)++) uf.unite(i, (i + bl) % al); for (int(i) = 0; (i) < (al); (i)++) { int ns = uf.find(i); pp[ns][a[i] - a ]++; sz[ns]++; } long long ans = 0; for (int(i) = 0; (i) < (bl); (i)++) { int ns = uf.find(i % al); for (int(j) = 0; (j) < (26); (j)++) if (j != b[i] - a ) ans += pp[ns][j]; } long long kkd = A * al / st; cout << ans * kkd << endl; }
|
#include <bits/stdc++.h> using namespace std; long long int a[100001]; vector<long long int> adj[100001]; long long int ans[21] = {}; long long int dp[100001][21][2]; void dfs(long long int i, long long int par) { long long int u = 0; for (long long int j = 0; j < adj[i].size(); j++) { long long int x = adj[i][j]; if (x != par) { dfs(x, i); if (u == 0) { u = 1; long long int z = a[i]; for (long long int k = 0; k <= 20; k++) { if (z % 2) { dp[i][k][1] = dp[x][k][0] + 1; dp[i][k][0] = dp[x][k][1]; } else { dp[i][k][1] = dp[x][k][1]; dp[i][k][0] = dp[x][k][0] + 1; } z = z / 2; ans[k] += dp[i][k][1]; } } else { long long int z = a[i]; for (long long int k = 0; k <= 20; k++) { ans[k] += dp[i][k][1] * dp[x][k][0] + dp[i][k][0] * dp[x][k][1]; if (z % 2) { dp[i][k][1] += dp[x][k][0]; dp[i][k][0] += dp[x][k][1]; } else { dp[i][k][1] += dp[x][k][1]; dp[i][k][0] += dp[x][k][0]; } z = z / 2; } } } } if (u == 0) { long long int z = a[i]; for (long long int k = 0; k <= 20; k++) { if (z % 2) { ans[k]++; dp[i][k][1]++; } else { dp[i][k][0]++; } z = z / 2; } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; for (long long int i = 1; i <= n; i++) cin >> a[i]; for (long long int i = 1; i < n; i++) { long long int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs(1, 0); long long int f = 1, pt = 0; for (long long int i = 0; i <= 20; i++) { pt += f * ans[i]; f = f * 2; } cout << pt; return 0; }
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import String.
Require Import List.
Require Import Arith.
Require Import Program.
Require Import EquivDec.
Require Import Morphisms.
Require Import Utils.
Require Import DataSystem.
Require Import cNNRC.
Require Import TcNNRC.
Section TcNNRCInfer.
Context {m:basic_model}.
Context (τconstants:tbindings).
(** Type inference for NNRC when given the type of the environment *)
Fixpoint infer_nnrc_core_type (tenv:tbindings) (n:nnrc) {struct n} : option rtype :=
match n with
| NNRCGetConstant v =>
tdot τconstants v
| NNRCVar v =>
lookup equiv_dec tenv v
| NNRCConst d => infer_data_type (normalize_data brand_relation_brands d)
| NNRCBinop b n1 n2 =>
let binf (τ₁ τ₂:rtype) := infer_binary_op_type b τ₁ τ₂ in
olift2 binf (infer_nnrc_core_type tenv n1) (infer_nnrc_core_type tenv n2)
| NNRCUnop u n1 =>
let unf (τ₁:rtype) := infer_unary_op_type u τ₁ in
olift unf (infer_nnrc_core_type tenv n1)
| NNRCLet v n1 n2 =>
let τ₁ := infer_nnrc_core_type tenv n1 in
let let_infer τ := infer_nnrc_core_type ((v,τ)::tenv) n2 in
olift let_infer τ₁
| NNRCFor v n1 n2 =>
let τ₁ := infer_nnrc_core_type tenv n1 in
let for_infer τ := lift Coll (infer_nnrc_core_type ((v,τ)::tenv) n2) in
olift for_infer (olift tuncoll τ₁)
| NNRCIf n0 n1 n2 =>
match infer_nnrc_core_type tenv n0 with
| Some τ₀ =>
match `τ₀ with
| Bool₀ =>
let oτ₁ := infer_nnrc_core_type tenv n1 in
let oτ₂ := infer_nnrc_core_type tenv n2 in
match (oτ₁, oτ₂) with
| (Some τ₁, Some τ₂) =>
if (rtype_eq_dec τ₁ τ₂) (* Probably should be generalized using join... *)
then Some τ₁
else None
| (_, _) => None
end
| _ => None
end
| None => None
end
| NNRCEither n0 v1 n1 v2 n2 =>
match olift tuneither (infer_nnrc_core_type tenv n0) with
| Some (τl, τr) =>
let oτ₁ := infer_nnrc_core_type ((v1,τl)::tenv) n1 in
let oτ₂ := infer_nnrc_core_type ((v2,τr)::tenv) n2 in
match (oτ₁, oτ₂) with
| (Some τ₁, Some τ₂) =>
if (rtype_eq_dec τ₁ τ₂) (* Probably should be generalized using join... *)
then Some τ₁
else None
| (_, _) => None
end
| _ => None
end
| NNRCGroupBy g sl n1 =>
None (* For core, always fails *)
end.
Lemma infer_nnrc_core_type_correct {τout} (tenv:tbindings) (n:nnrc) :
infer_nnrc_core_type tenv n = Some τout ->
nnrc_core_type τconstants tenv n τout.
Proof.
revert tenv τout.
nnrc_cases (induction n) Case; intros; simpl in *.
- Case "NNRCGetConstant"%string.
apply type_cNNRCGetConstant; assumption.
- Case "NNRCVar"%string.
apply type_cNNRCVar; assumption.
- Case "NNRCConst"%string.
apply type_cNNRCConst.
apply infer_data_type_correct. assumption.
- Case "NNRCBinop"%string.
specialize (IHn1 tenv); specialize (IHn2 tenv).
destruct (infer_nnrc_core_type tenv n1); destruct (infer_nnrc_core_type tenv n2); simpl in *;
try discriminate.
specialize (IHn1 r eq_refl); specialize (IHn2 r0 eq_refl).
apply (@type_cNNRCBinop m τconstants r r0 τout tenv); try assumption.
apply infer_binary_op_type_correct; assumption.
- Case "NNRCUnop"%string.
specialize (IHn tenv).
destruct (infer_nnrc_core_type tenv n); simpl in *;
try discriminate.
specialize (IHn r eq_refl).
apply (@type_cNNRCUnop m τconstants r τout tenv); try assumption.
apply infer_unary_op_type_correct; assumption.
- Case "NNRCLet"%string.
specialize (IHn1 tenv).
destruct (infer_nnrc_core_type tenv n1); simpl in *; try discriminate.
specialize (IHn2 ((v,r) :: tenv)).
destruct (infer_nnrc_core_type ((v, r) :: tenv) n2); simpl in *; try discriminate.
inversion H; subst; clear H.
specialize (IHn1 r eq_refl).
specialize (IHn2 τout eq_refl).
apply (type_cNNRCLet τconstants v tenv n1 n2 IHn1 IHn2).
- Case "NNRCFor"%string.
specialize (IHn1 tenv).
destruct (infer_nnrc_core_type tenv n1); simpl in *; try discriminate.
case_eq (tuncoll r); intros; rewrite H0 in *; simpl in H.
+ apply tuncoll_correct in H0.
specialize (IHn2 ((v,r0) :: tenv)).
destruct (infer_nnrc_core_type ((v, r0) :: tenv) n2); simpl in *; try discriminate.
inversion H; subst; clear H.
specialize (IHn1 (Coll r0) eq_refl).
specialize (IHn2 r1 eq_refl).
apply (type_cNNRCFor τconstants v tenv n1 n2 IHn1 IHn2).
+ discriminate.
- Case "NNRCIf"%string.
specialize (IHn1 tenv).
specialize (IHn2 tenv).
specialize (IHn3 tenv).
destruct (infer_nnrc_core_type tenv n1); simpl in *; try discriminate.
destruct r; try congruence; simpl in H.
destruct x; try congruence; simpl in H.
destruct (infer_nnrc_core_type tenv n2); simpl in *; try discriminate.
destruct (infer_nnrc_core_type tenv n3); simpl in *; try discriminate.
destruct (rtype_eq_dec r r0); simpl in *; try congruence.
rewrite e0 in *; clear e0.
inversion H; clear H; subst.
assert (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) Bool₀ e = Bool) by (apply rtype_fequal; reflexivity).
rewrite H in IHn1; clear H.
specialize (IHn1 Bool eq_refl).
specialize (IHn2 τout eq_refl).
specialize (IHn3 τout eq_refl).
apply type_cNNRCIf; assumption.
- Case "NNRCEither"%string.
specialize (IHn1 tenv).
destruct (infer_nnrc_core_type tenv n1); simpl in *; try discriminate.
unfold tuneither in H.
destruct r; simpl in H; try discriminate.
destruct x; simpl in H; try discriminate.
match_case_in H; intros; rewrite H0 in H; try discriminate.
match_case_in H; intros; rewrite H1 in H; try discriminate.
match_destr_in H.
red in e0.
invcs H; subst.
specialize (IHn1 (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true)
(Either₀ x1 x2) e) eq_refl).
specialize (IHn2 _ _ H0).
specialize (IHn3 _ _ H1).
eapply type_cNNRCEither; eauto.
erewrite <- Either_canon; eauto.
- Case "NNRCGroupBy"%string.
congruence. (* Type checking always fails for groupby in core NNRC *)
Qed.
End TcNNRCInfer.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
module t (/*AUTOARG*/);
typedef enum int {
PADTYPE_DEFAULT = 32'd0,
PADTYPE_GPIO,
PADTYPE_VDD,
PADTYPE_GND
} t_padtype;
localparam int STR_PINID [0:15]
= '{
"DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR",
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
};
typedef struct packed {
t_padtype padtype;
int aux;
} t_pin_descriptor;
localparam t_pin_descriptor
PINOUT[ 1: 6]
= '{
'{default:0, padtype:PADTYPE_GPIO, aux:1},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_VDD},
'{default:0, padtype:PADTYPE_GND}
};
localparam int PINOUT_SIZE = 6;
localparam int PINOUT_WA[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
const int pinout_static_const[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
// Make sure consants propagate
checkstr #(.PINID(STR_PINID[1]),
.EXP("ERR"))
substr1 ();
checkstr #(.PINID(STR_PINID[8]),
.EXP("PA0"))
substr8 ();
initial begin
$display("PINID1 %s", STR_PINID[1]);
$display("PINID8 %s", STR_PINID[8]);
if (STR_PINID[1] != "ERR") $stop;
if (STR_PINID[8] != "PA0") $stop;
if (pinout_static_const[1][0] != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module checkstr;
parameter int PINID = " ";
parameter int EXP = " ";
initial begin
$display("PID %s EXP %s", PINID, EXP);
if (EXP != "ERR" && EXP != "PA0") $stop;
if (PINID != EXP) $stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_4_V
`define SKY130_FD_SC_HDLL__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, ta, tb; cin >> a >> ta >> b >> tb; int t, m; char c; cin >> t >> c >> m; m += 60 * t; int cur = 5 * 60; int res = 0; while (cur < 24 * 60) { if (min(cur + tb, m + ta) > max(cur, m)) ++res; cur += b; } cout << res; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
|
module Tx8b10b_tb ();
reg clk; // System clock
reg rst; // Reset; synchronous and active high
reg en; // Enable bit
reg [7:0] dataIn; // Data to transmit
reg writeStrobe; // Write data to transmit FIFO
wire dataPresent; // FIFO has data still in it
wire halfFull; // FIFO halfway full
wire full; // FIFO is completely full. Don't write to it.
wire tx; // Transmit bit
integer i;
integer dcOffset;
always #1 clk = ~clk;
initial begin
dcOffset = 1'b0;
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
writeStrobe = 1'b0;
@(posedge clk)
@(posedge clk)
rst = 1'b0;
for (i=0; i<50000; i=i+1) begin
wait(~full);
@(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
@(posedge clk) writeStrobe = 1'b0;
@(posedge clk);
end
$stop(2);
end
always @(posedge clk) begin
dcOffset <= dcOffset + $signed({tx, 1'b1});
end
Tx8b10b #(
.FILL_WORD_RD0(10'b0011111010), // Send when no data present & RD=-1
.FILL_WORD_RD1(10'b1100000101), // Send when no data present & RD=1
.FILL_WORD_FLIP(1'b1), // Flip status of Running Disparity when using fill word
.LOG2_DEPTH(4) // log2(depth of FIFO buffer). Must be an integer.
)
uut (
.clk(clk), // System clock
.rst(rst), // Reset, synchronous and active high
.en(en), // Enable strobe for transmitting
.dataIn(dataIn), // [7:0] Data to transmit
.writeStrobe(writeStrobe), // Write data to transmit FIFO
.dataPresent(dataPresent), // FIFO has data still in it
.halfFull(halfFull), // FIFO halfway full
.full(full), // FIFO is completely full. Don't write to it.
.tx(tx) // Transmit bit
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_SYMBOL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s25 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_SYMBOL_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 9; const double eps = 1e-11; const int inf = (int)2e9; const int mod = (int)1e9 + 7; const double pi = 3.1415926535897932384626433832795; int a[N]; int main() { int n, k; scanf( %d %d , &n, &k); int ex = 0; for (int i = 1; i <= n; i++) { a[i] = i; ex += i * (n - i + 1); } int cnt = 0; do { int cur = 0; for (int i = 1; i <= n; i++) { int mn = inf; for (int j = i; j <= n; j++) { mn = min(mn, a[j]); cur += mn; } } if (cur == ex) { k--; if (!k) { for (int i = 1; i <= n; i++) { printf( %d%c , a[i], n [i == n]); } } } } while (next_permutation(a + 1, a + n + 1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool check(int a, int b, int frst, int s) { return a * frst / (double)s >= (double)b; } int main() { int n, a, b, *arr; cin >> n >> a >> b; arr = new int[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr + 1, arr + n); for (int i = 1; i < n; i++) { arr[i] = arr[i] + arr[i - 1]; } int l = 0, r = n - 1, ans; while (l <= r) { int mid = (l + r) / 2; bool now = check(a, b, arr[0], arr[mid]); bool nx = check(a, b, arr[0], arr[mid + 1]); if (mid == n - 1 || (now && !nx)) { ans = mid; break; } else if (now && nx) { l = mid + 1; } else { r = mid - 1; } } cout << n - (ans + 1) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void read(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void readc(char &x) { char c; while (((c = getchar()) == ) || c == n ) ; x = c; } inline void writes(string s) { puts(s.c_str()); } inline void writeln() { writes( ); } inline void writei(int x) { if (x < 0) { putchar( - ); x = abs(x); } if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } inline void writell(long long x) { if (x < 0) { putchar( - ); x = abs(x); } if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } const int dx[9] = {0, -2, -2, -1, -1, 1, 1, 2, 2}, dy[9] = {0, -1, 1, -2, 2, -2, 2, -1, 1}; int n, m, i, j, dis[1005][1005][2], x, y, xx, yy; int a, b; bool inmap(int x, int y) { return 1 <= x && x <= n && 1 <= y && y <= m; } void bfs(int x, int y, int typ) { dis[x][y][typ] = 0; queue<int> qx, qy; qx.push(x); qy.push(y); while (!qx.empty()) { int x = qx.front(), y = qy.front(); int i; qx.pop(); qy.pop(); for (((i)) = (1); ((i)) <= ((8)); ((i))++) { int nx = x + dx[i], ny = y + dy[i]; if (inmap(nx, ny) && dis[nx][ny][typ] > dis[x][y][typ] + 1) { dis[nx][ny][typ] = dis[x][y][typ] + 1; qx.push(nx); qy.push(ny); } } } } void solve(int x, int y, int typ) { for (;;) { if (dis[x][y][typ] == 0) break; int i; for (((i)) = (1); ((i)) <= ((8)); ((i))++) { int nx = x + dx[i], ny = y + dy[i]; if (nx == a && ny == b) { printf( %d %d n , nx, ny); return; } } for (((i)) = (1); ((i)) <= ((8)); ((i))++) { int nx = x + dx[i], ny = y + dy[i]; if (inmap(nx, ny) && dis[nx][ny][typ] == dis[x][y][typ] - 1) { printf( %d %d n , nx, ny); fflush(stdout); x = nx; y = ny; if (dis[x][y][typ] == 0) return; scanf( %d%d , &a, &b); break; } } } } int main() { scanf( %d%d , &n, &m); scanf( %d%d%d%d , &x, &y, &xx, &yy); memset((dis), (0x16), (sizeof((dis)))); bfs(n / 2, m / 2, 0); bfs(n / 2 + 1, m / 2, 1); double wg = dis[x][y][0]; double wb = dis[x][y][1]; double bg = dis[xx][yy][1] + 0.5; double bb = dis[xx][yy][0] + 0.5; if ((x + y) % 2 == (xx + yy) % 2) { if (bg < wg) { puts( BLACK ); fflush(stdout); scanf( %d%d , &a, &b); solve(xx, yy, 1); return 0; } if (bb < wg + 1) { puts( BLACK ); fflush(stdout); scanf( %d%d , &a, &b); solve(xx, yy, 0); solve(n / 2, m / 2, 1); return 0; } puts( WHITE ); fflush(stdout); solve(x, y, 0); } else { if (wg < bg) { puts( WHITE ); fflush(stdout); solve(x, y, 0); return 0; } if (wb < bg + 1) { puts( WHITE ); fflush(stdout); solve(x, y, 1); solve(n / 2 + 1, m / 2, 0); return 0; } puts( BLACK ); fflush(stdout); scanf( %d%d , &a, &b); solve(xx, yy, 1); } return 0; }
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#include <bits/stdc++.h> int ans = 0; double H = 100, len = 100000; int F[110000], T[110000], FF[110000], TT[110000]; bool vis[110000]; int judge(bool fuck, double st, double t) { int ret = 0; int top, flo; double point = st; memset(vis, 0, sizeof(vis)); while (point < len) { top = (int)ceil(point); flo = (int)floor(point); if (fuck) { if (T[top] < 0 || T[flo] < 0 || T[top] != T[flo]) { return -1; } if (vis[TT[top]] == 1) return -1; ret += T[top]; vis[TT[top]] = 1; fuck = !fuck; } else { if (F[top] < 0 || F[flo] < 0 || F[top] != F[flo]) { return -1; } if (vis[FF[top]] == 1) return -1; ret += F[top]; vis[FF[top]] = 1; fuck = !fuck; } point += t; } if (ans < ret) ans = ret; return ret; } int work() { int n, i, j, val, x, y; char c; double A, B, t; double hl, hr; scanf( %lf%lf%d , &hl, &hr, &n); memset(T, -1, sizeof(T)); memset(F, -1, sizeof(F)); for (i = 1; i <= n; i++) { scanf( %d %c%d%d , &val, &c, &x, &y); if (c == T ) { for (j = x; j <= y; j++) T[j] = val, TT[j] = i; } else { for (j = x; j <= y; j++) F[j] = val, FF[j] = i; } } A = hl / H; B = hr / H; for (i = 0; i <= 100; i++) { if ((i & 1) == 0) { t = len / (A + B + i); judge(0, A * t, t); } if ((i & 1) == 1) { t = len / ((1 - A) + B + i); judge(1, (1 - A) * t, t); } if ((i & 1) == 1) { t = len / (A + (1 - B) + i); judge(0, A * t, t); } if ((i & 1) == 0) { t = len / ((1 - A) + (1 - B) + i); judge(1, (1 - A) * t, t); } } printf( %d n , ans); return 1; } int main() { work(); return 0; }
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module dispatches group ids to possibly multiple work item iterators.
// Each work-item iterator should be separated by a fifo from the dispatcher.
module acl_work_group_dispatcher
#(
parameter WIDTH = 32, // width of all the counters
parameter NUM_COPIES = 1, // number of kernel copies to manage
parameter RUN_FOREVER = 0 // flag for infinitely running kernel
)
(
input clock,
input resetn,
input start, // Assert to restart the iterators
// Populated during kernel startup
input [WIDTH-1:0] num_groups[2:0],
input [WIDTH-1:0] local_size[2:0],
// Handshaking with iterators for each kernel copy
input [NUM_COPIES-1:0] stall_in,
output [NUM_COPIES-1:0] valid_out,
// Export group_id to iterators.
output reg [WIDTH-1:0] group_id_out[2:0],
output reg [WIDTH-1:0] global_id_base_out[2:0],
output start_out,
// High when all groups have been dispatched to id iterators
output reg dispatched_all_groups
);
//////////////////////////////////
// Group id register updates.
reg started; // one cycle delayed after start goes high. stays high
reg delayed_start; // two cycles delayed after start goes high. stays high
reg [WIDTH-1:0] max_group_id[2:0];
reg [WIDTH-1:0] group_id[2:0];
wire last_group_id[2:0];
assign last_group_id[0] = (group_id[0] == max_group_id[0] );
assign last_group_id[1] = (group_id[1] == max_group_id[1] );
assign last_group_id[2] = (group_id[2] == max_group_id[2] );
wire last_group = last_group_id[0] & last_group_id[1] & last_group_id[2];
wire group_id_ready;
wire bump_group_id[2:0];
assign bump_group_id[0] = 1'b1;
assign bump_group_id[1] = last_group_id[0];
assign bump_group_id[2] = last_group_id[0] && last_group_id[1];
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
global_id_base_out[0] <= {WIDTH{1'b0}};
global_id_base_out[1] <= {WIDTH{1'b0}};
global_id_base_out[2] <= {WIDTH{1'b0}};
max_group_id[0] <= {WIDTH{1'b0}};
max_group_id[1] <= {WIDTH{1'b0}};
max_group_id[2] <= {WIDTH{1'b0}};
started <= 1'b0;
delayed_start <= 1'b0;
dispatched_all_groups <= 1'b0;
end else if ( start ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
global_id_base_out[0] <= {WIDTH{1'b0}};
global_id_base_out[1] <= {WIDTH{1'b0}};
global_id_base_out[2] <= {WIDTH{1'b0}};
max_group_id[0] <= num_groups[0] - 2'b01;
max_group_id[1] <= num_groups[1] - 2'b01;
max_group_id[2] <= num_groups[2] - 2'b01;
started <= 1'b1;
delayed_start <= started;
dispatched_all_groups <= 1'b0;
end else // We presume that start and issue are mutually exclusive.
begin
if ( started & stall_in != {NUM_COPIES{1'b1}} & ~dispatched_all_groups ) begin
if ( bump_group_id[0] ) group_id[0] <= last_group_id[0] ? {WIDTH{1'b0}} : (group_id[0] + 2'b01);
if ( bump_group_id[1] ) group_id[1] <= last_group_id[1] ? {WIDTH{1'b0}} : (group_id[1] + 2'b01);
if ( bump_group_id[2] ) group_id[2] <= last_group_id[2] ? {WIDTH{1'b0}} : (group_id[2] + 2'b01);
// increment global_id_base here so it's always equal to
// group_id x local_size.
// without using any multipliers.
if ( bump_group_id[0] ) global_id_base_out[0] <= last_group_id[0] ? {WIDTH{1'b0}} : (global_id_base_out[0] + local_size[0]);
if ( bump_group_id[1] ) global_id_base_out[1] <= last_group_id[1] ? {WIDTH{1'b0}} : (global_id_base_out[1] + local_size[1]);
if ( bump_group_id[2] ) global_id_base_out[2] <= last_group_id[2] ? {WIDTH{1'b0}} : (global_id_base_out[2] + local_size[2]);
if ( last_group && RUN_FOREVER == 0 )
dispatched_all_groups <= 1'b1;
end
// reset these registers so that next kernel invocation will work.
if ( dispatched_all_groups ) begin
started <= 1'b0;
delayed_start <= 1'b0;
end
end
end
// will have 1 at the lowest position where stall_in has 0.
wire [NUM_COPIES-1:0] single_one_from_stall_in = ~stall_in & (stall_in + 1'b1);
assign group_id_ready = delayed_start & ~dispatched_all_groups;
assign start_out = start;
assign group_id_out = group_id;
assign valid_out = single_one_from_stall_in & {NUM_COPIES{group_id_ready}};
endmodule
// vim:set filetype=verilog:
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7, siz = 1e6 + 5; long long q, n, m, a[siz], rot[66]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> q; while (q--) { long long op; cin >> op; if (op <= 2) { long long node, k; cin >> node >> k; long long dep = log2l(node); long long sz = 1LL << dep; if (k >= 0) k %= sz; else { k = sz + k; k %= sz; } rot[dep] += k; rot[dep] %= sz; if (op == 2) { long long incr = 2 * k; for (long long i = dep + 1; i <= 60; i++) { rot[i] += incr; rot[i] %= (1LL << i); incr *= 2; } } continue; } long long node; cin >> node; long long dep = log2l(node); long long pos_start = node - (1LL << dep); long long pos = (rot[dep] + pos_start) % (1LL << dep); vector<long long> out; while (dep > 0) { long long nxt = pos; long long incr = (1LL << dep) - rot[dep]; long long new_pos = (pos + incr) % (1LL << dep); long long inp = (1LL << dep) + new_pos; out.push_back(inp); pos = nxt + (1LL << dep); pos /= 2; dep--; } out.push_back(1); for (auto x : out) cout << x << ; cout << endl; } }
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#include <bits/stdc++.h> using namespace std; map<long long, long long> m; long long f(string s) { long long ff[27] = {0}, ans = 0, i, j; for (i = 0; i < s.size(); i++) { ff[s[i] - a ]++; } for (i = 0; i < 26; i++) { if (ff[i] % 2) { ans |= (1LL << i); } } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, i, j; cin >> n; string s[n + 1]; vector<long long> v; for (i = 0; i < n; i++) { cin >> s[i]; v.push_back(f(s[i])); } for (i = 0; i < v.size(); i++) m[v[i]]++; long long ans = 0; for (auto i : m) { ans += (i.second * (i.second - 1)) / 2; } for (i = 0; i < 26; i++) { map<long long, long long> mm; for (j = 0; j < n; j++) if (v[j] & (1 << i)) mm[v[j] ^ (1LL << i)]++; for (auto j : mm) { ans += m[j.first] * j.second; } } cout << ans; return 0; }
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/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Note that detune produces an output even for fnum==0, is that correct?
Based on jt51_phasegen.v, from JT51
*/
module jt12_pg_dt(
input [ 2:0] block,
input [10:0] fnum,
input [ 2:0] detune,
output reg [ 4:0] keycode,
output reg signed [5:0] detune_signed
);
reg [5:0] detune_kf;
reg [4:0] pow2;
reg [5:0] detune_unlimited;
reg [4:0] detune_limit, detune_limited;
always @(*) begin
keycode = { block, fnum[10], fnum[10] ? (|fnum[9:7]) : (&fnum[9:7])};
case( detune[1:0] )
2'd1: detune_kf = { 1'b0, keycode } - 6'd4;
2'd2: detune_kf = { 1'b0, keycode } + 6'd4;
2'd3: detune_kf = { 1'b0, keycode } + 6'd8;
default:detune_kf = { 1'b0, keycode };
endcase
case( detune_kf[2:0] )
3'd0: pow2 = 5'd16;
3'd1: pow2 = 5'd17;
3'd2: pow2 = 5'd19;
3'd3: pow2 = 5'd20;
3'd4: pow2 = 5'd22;
3'd5: pow2 = 5'd24;
3'd6: pow2 = 5'd26;
3'd7: pow2 = 5'd29;
endcase
case( detune[1:0] )
2'd0: detune_limit = 5'd0;
2'd1: detune_limit = 5'd8;
2'd2: detune_limit = 5'd16;
2'd3: detune_limit = 5'd22;
endcase
case( detune_kf[5:3] )
3'd0: detune_unlimited = { 5'd0, pow2[4] }; // <2
3'd1: detune_unlimited = { 4'd0, pow2[4:3] }; // <4
3'd2: detune_unlimited = { 3'd0, pow2[4:2] }; // <8
3'd3: detune_unlimited = { 2'd0, pow2[4:1] };
3'd4: detune_unlimited = { 1'd0, pow2[4:0] };
3'd5: detune_unlimited = { pow2[4:0], 1'd0 };
default:detune_unlimited = 6'd0;
endcase
detune_limited = detune_unlimited > {1'b0, detune_limit} ?
detune_limit : detune_unlimited[4:0];
detune_signed = !detune[2] ? {1'b0,detune_limited} : (~{1'b0,detune_limited}+6'd1);
end
endmodule
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#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (a == 0) return b; else return gcd(b % a, a); } long long int power(long long int a, long long int b, long long int m) { long long int ans = 1; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, k; cin >> n >> k; long long int ans = 6; if (n == 2) { cout << ans << endl; return 0; } if (k == 1 || k == n) { ans = ans + 3 * (n - 2); } else { k = min(k, n - k + 1); for (long long int i = 1; i < k - 1; i++) ans = ans + 3; ans = ans + (k - 1); ans = ans + 3 * (n - k); } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; int n, m; int first[maxn], second[maxn]; void solve() { cin >> n >> m; for (int i = 1; i <= m; ++i) cin >> first[i] >> second[i]; int a, b; a = first[1]; b = -1; for (int i = 1; i <= m; ++i) { if (first[i] != a && second[i] != a) { if (first[i] != b && second[i] != b) { if (b == -1) b = first[i]; else break; } } if (i == m) { puts( YES ); return; } } a = -1; b = second[1]; for (int i = 1; i <= m; ++i) { if (first[i] != b && second[i] != b) { if (first[i] != a && second[i] != a) { if (a == -1) a = first[i]; else break; } } if (i == m) { puts( YES ); return; } } a = -1; b = second[1]; for (int i = 1; i <= m; ++i) { if (first[i] != b && second[i] != b) { if (first[i] != a && second[i] != a) { if (a == -1) a = second[i]; else break; } } if (i == m) { puts( YES ); return; } } a = first[1]; b = -1; for (int i = 1; i <= m; ++i) { if (first[i] != a && second[i] != a) { if (first[i] != b && second[i] != b) { if (b == -1) b = second[i]; else break; } } if (i == m) { puts( YES ); return; } } puts( NO ); } int main() { solve(); }
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