text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int N = 300 * 1000 + 20; int n, a[N]; multiset<int> e; long long ans; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (e.size()) if (*e.begin() < a[i]) { ans += a[i] - *e.begin(); e.erase(e.begin()); e.insert(a[i]); } e.insert(a[i]); } return cout << ans << endl, 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_reg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_exu_reg (/*AUTOARG*/
// Outputs
data_out,
// Inputs
clk, se, thr_out, wen_w, thr_w, data_in_w
) ;
parameter SIZE = 3;
input clk;
input se;
input [3:0] thr_out;
input wen_w;
input [3:0] thr_w;
input [SIZE -1:0] data_in_w;
output [SIZE-1:0] data_out;
wire [SIZE-1:0] data_thr0;
wire [SIZE-1:0] data_thr1;
wire [SIZE-1:0] data_thr2;
wire [SIZE-1:0] data_thr3;
wire [SIZE-1:0] data_thr0_next;
wire [SIZE-1:0] data_thr1_next;
wire [SIZE-1:0] data_thr2_next;
wire [SIZE-1:0] data_thr3_next;
wire wen_thr0_w;
wire wen_thr1_w;
wire wen_thr2_w;
wire wen_thr3_w;
//////////////////////////////////
// Output selection for reg
//////////////////////////////////
`ifdef FPGA_SYN_1THREAD
assign data_out[SIZE -1:0] = data_thr0[SIZE -1:0];
assign wen_thr0_w = (thr_w[0] & wen_w);
// mux between new and current value
mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]),
.in0(data_thr0[SIZE -1:0]),
.in1(data_in_w[SIZE -1:0]),
.sel0(~wen_thr0_w),
.sel1(wen_thr0_w));
dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
.se(se), .si(), .so());
`else // !`ifdef FPGA_SYN_1THREAD
// mux between the 4 regs
mux4ds #(SIZE) mux_data_out1(.dout(data_out[SIZE -1:0]), .sel0(thr_out[0]),
.sel1(thr_out[1]), .sel2(thr_out[2]),
.sel3(thr_out[3]), .in0(data_thr0[SIZE -1:0]),
.in1(data_thr1[SIZE -1:0]), .in2(data_thr2[SIZE -1:0]),
.in3(data_thr3[SIZE -1:0]));
//////////////////////////////////////
// Storage of reg
//////////////////////////////////////
// enable input for each thread
assign wen_thr0_w = (thr_w[0] & wen_w);
assign wen_thr1_w = (thr_w[1] & wen_w);
assign wen_thr2_w = (thr_w[2] & wen_w);
assign wen_thr3_w = (thr_w[3] & wen_w);
// mux between new and current value
mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]),
.in0(data_thr0[SIZE -1:0]),
.in1(data_in_w[SIZE -1:0]),
.sel0(~wen_thr0_w),
.sel1(wen_thr0_w));
mux2ds #(SIZE) data_next1_mux(.dout(data_thr1_next[SIZE -1:0]),
.in0(data_thr1[SIZE -1:0]),
.in1(data_in_w[SIZE -1:0]),
.sel0(~wen_thr1_w),
.sel1(wen_thr1_w));
mux2ds #(SIZE) data_next2_mux(.dout(data_thr2_next[SIZE -1:0]),
.in0(data_thr2[SIZE -1:0]),
.in1(data_in_w[SIZE -1:0]),
.sel0(~wen_thr2_w),
.sel1(wen_thr2_w));
mux2ds #(SIZE) data_next3_mux(.dout(data_thr3_next[SIZE -1:0]),
.in0(data_thr3[SIZE -1:0]),
.in1(data_in_w[SIZE -1:0]),
.sel0(~wen_thr3_w),
.sel1(wen_thr3_w));
// store new value
dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
.se(se), .si(), .so());
dff_s #(SIZE) dff_reg_thr1(.din(data_thr1_next[SIZE -1:0]), .clk(clk), .q(data_thr1[SIZE -1:0]),
.se(se), .si(), .so());
dff_s #(SIZE) dff_reg_thr2(.din(data_thr2_next[SIZE -1:0]), .clk(clk), .q(data_thr2[SIZE -1:0]),
.se(se), .si(), .so());
dff_s #(SIZE) dff_reg_thr3(.din(data_thr3_next[SIZE -1:0]), .clk(clk), .q(data_thr3[SIZE -1:0]),
.se(se), .si(), .so());
`endif // !`ifdef FPGA_SYN_1THREAD
endmodule // sparc_exu_reg
|
#include <bits/stdc++.h> using namespace std; int t = 0; int ans = 1; long long int prime(long long int n) { while (n % 2 == 0) { if (t == 2) break; n = n / 2; t++; ans *= 2; } for (int i = 3; i <= sqrt(n); i += 2) { while (n % i == 0) { if (t == 2) break; n = n / i; t++; ans *= i; } if (t == 2) break; } if (n > 2 && t != 2) { ans *= n; t++; n = 1; } return n; } int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); long long int n; cin >> n; if (n == 1) cout << 1 << n << 0; else { long long int final = prime(n); if (final == 1 && t == 1) cout << 1 << endl << 0; else if (final == 1 && t == 2) cout << 2; else if (t == 2) cout << 1 << n << ans; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; int count25 = 0; int count50 = 0; int ans = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] == 25) { count25++; } else if (arr[i] == 50) { if (count25 > 0) { count25--; count50++; } else { ans = -1; } } else if (arr[i] == 100) { if ((count25 > 0 && count50 > 0) || (count25 >= 3 && count50 == 0)) { if (count50 == 0) { count25--; count25--; count25--; } else { count25--; count50--; } } else { ans = -1; } } } if (ans == -1) { cout << NO ; } else { cout << YES ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e; while (e--) { long long int A, B, C, D; cin >> A >> B >> C >> D; if (A == C) { cout << max(B, D) - min(B, D) << endl; } else { if (B <= c && D <= c) { cout << max(A, C) - min(A, C) + c - B + c - D << endl; } else if (B >= d && D >= d) { cout << max(A, C) - min(A, C) + B - d + D - d << endl; } else { cout << max(A, C) - min(A, C) + max(B, D) - min(B, D) << endl; } } } }
|
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module data_fifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
parameter WIDTH = 24;
input [WIDTH-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [WIDTH-1:0] q;
output rdempty;
output wrfull;
wire [WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WIDTH,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int s, v1, v2, t1, t2; cin >> s >> v1 >> v2 >> t1 >> t2; int res1 = (s * v1) + (t1 * 2); int res2 = (s * v2) + (t2 * 2); if (res1 < res2) { cout << First ; } if (res1 > res2) { cout << Second ; } if (res1 == res2) { cout << Friendship ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 10; int n, u, v, dp[maxn], d[2]; long long f[maxn], ans, sum; vector<int> a[maxn]; void dfs(int nod, int pa, int x) { d[x]++; for (int i : a[nod]) { if (i != pa) { dfs(i, nod, x ^ 1); dp[nod] += dp[i]; f[nod] += (f[i] + dp[i]); } } for (int i : a[nod]) { if (i != pa) { ans += (f[nod] - f[i] - dp[i]) * dp[i]; } } ans += f[nod]; dp[nod]++; return; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); a[u].push_back(v); a[v].push_back(u); } dfs(1, 0, 0); printf( %lld n , (ans + (1ll * d[0] * d[1])) / 2); }
|
`timescale 1ns / 1ps
module square_root_comb #(parameter N = 8, M = 16)(
input [N-1:0] A,
output [N/2-1:0] O
);
wire [N/2-1:0] Y[0:M];
wire [N/2-1:0] Y0[0:M];
assign Y[0] = {1'b1,{(N/2-1){1'b0}}};
assign Y0[0] = {1'b1,{(N/2-1){1'b0}}};
assign O = Y[M];
genvar gv;
generate
for (gv = 0; gv < M; gv = gv + 1)
begin: sqr_rt
squar_root_unit #(.N(N)) squar_root_unit(
.x(A),
.y_in(Y[gv]),
.y0_in(Y0[gv]),
.y(Y[gv+1]),
.y0(Y0[gv+1])
);
end
endgenerate
endmodule
module squar_root_unit #(parameter N = 8)(
input [N-1:0] x,
input [N/2-1:0] y_in, y0_in,
output [N/2-1:0] y, y0
);
wire t;
wire [N/2-1:0] y_min_y0, y_mid;
wire [N-1:0] y_sqr;
wire [1:0] temp;
//assign y_sqr = y_in * y_in;
MULT #(.N(N/2), .M(N/2)) MULT1 (.A(y_in), .B(y_in), .O(y_sqr));
//assign t = (y_sqr > x) ? 1 : 0;
COMP #(.N(N)) COMP1 (.A(x), .B(y_sqr), .O(t));
//assign y_min_y0 = y_in - y0_in;
SUB_ #(.N(N/2), .M(N/2)) SUB1 (.A(y_in), .B(y0_in), .O({temp[0], y_min_y0}));
//assign y_mid = t? y_min_y0 : y_in;
MUX #(.N(N/2)) MUX1 (.A(y_min_y0), .B(y_in), .S(t), .O(y_mid));
assign y0 = y0_in >> 1;
//assign y = y_mid + y0;
ADD_ #(.N(N/2), .M(N/2)) ADD1 (.A(y_mid), .B(y0), .O({temp[1],y}));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e5 + 5; const long long mod = 1e9 + 7; long long fact[MAXN]; long long invfact[MAXN]; bool sieve[MAXN]; long long powe(long long x, long long y, long long mod) { long long res = 1; while (y > 0) { if (y & 1) res = (res * x) % mod; y = y >> 1; x = (x * x) % mod; } return res; } void makesieve() { for (long long i = 0; i < MAXN; ++i) { sieve[i] = 1; } sieve[0] = 0; sieve[1] = 0; for (long long i = 2; i * i <= MAXN; ++i) { for (long long j = 2 * i; j < MAXN; j += i) { sieve[j] = 0; } } } void pre() { fact[0] = 1; invfact[0] = 1; for (long long i = 1; i < MAXN; ++i) { fact[i] = (fact[i - 1] * i) % mod; invfact[i] = powe(fact[i], mod - 2, mod); } makesieve(); } long long comb(long long n, long long r) { if (r == 0 || n == r) return 1; if (r > n) return 0; long long A = (fact[n] * invfact[r]) % mod; return (A * invfact[n - r]) % mod; } long long gcde(long long a, long long b) { if (a == 0) return b; return gcde(b % a, a); } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long modInverse(long long a, long long m) { long long x, y; long long g = gcdExtended(a, m, &x, &y); return (x % m + m) % m; } bool ifcontains(string str, string smlstr) { if (str.length() < smlstr.length()) return false; for (long long i = 0; i < str.length(); ++i) { bool fg = 0; for (long long j = 0; j < smlstr.length(); ++j) { if (i + j >= str.length()) { fg = 1; break; } if (smlstr[j] != str[i + j]) { fg = 1; break; } } if (!fg) return true; } return false; } int main() { pre(); long long n, k; cin >> n >> k; long long ans = 0; for (long long i = 0; i <= n; ++i) { for (long long j = 0; j <= n; ++j) { long long sign; if ((i + j) % 2 == 0) sign = 1; else sign = -1; long long total_cells = (i + j) * n - i * j; long long rest_cells = n * n - total_cells; long long temp = (powe(k - 1, total_cells, mod) * powe(k, rest_cells, mod)) % mod * sign; temp = (temp + mod) % mod; temp *= (comb(n, i) * comb(n, j)) % mod; temp %= mod; ans += temp; ans %= mod; } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; scanf( %d%d , &a, &b); if (a < b) { for (int i = b + 1; i <= (a + b + 1); i++) printf( %d , i); for (int j = b; j >= 1; j--) printf( %d , j); } else { for (int i = 1; i <= a; i++) printf( %d , i); for (int j = (a + b + 1); j > a; j--) printf( %d , j); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_nsr.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); bool f = 1; for (long long i = 1; i < n; i++) { if (arr[i] - arr[i - 1] > 1) f = 0; } if (f) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int c = 0, r, d, a, s; a = n; while (n) { if (n >= 10) { r = n / 10; n -= r * 10; n += r; c += r * 10; } else { c += n; n /= 10; } } cout << c << endl; } }
|
#include <bits/stdc++.h> using namespace std; void Yahia74() {} const int N = 1e5 + 74, M = 1e5 + 74, OO = 0x3f3f3f3f; int main() { Yahia74(); int n, cnt[N] = {}; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; if (i < n / 2) { if (x - i >= 0) cnt[x - i]++; } else { if (x - (n - i - 1) >= 0) cnt[x - (n - i - 1)]++; } } int mx = 0; for (int i = 1; i < 100001; i++) mx = max(mx, cnt[i]); cout << n - mx << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline string tostring(const T &x) { ostringstream os; os << x; return os.str(); } inline int toint(const string &s) { istringstream is(s); int x; is >> x; return x; } inline int todecimal(string s) { int a = 0; for (int i = 0; i < s.size(); i++) a = 2 * a + (s[i] - 0 ); return a; } inline string tobinary(int a) { string s; while (a != 0) { s = (char)(a % 2 + 0 ) + s; a >>= 1; } return s; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> T gcd(T a, T b) { return (b == 0) ? abs(a) : gcd(b, a % b); } inline int isvowel(char c) { if (c == a || c == e || c == i || c == o || c == u ) return 1; return 0; } inline int isprime(int a) { for (int i = 2; i * i <= a; i++) if (!(a % i)) return 0; return 1; } inline void inp(int &n) { n = 0; int ch = getchar(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar(); n = n * sign; } const int dx4[4] = {0, 0, 1, -1}; const int dy4[4] = {1, -1, 0, 0}; const int dx8[8] = {0, 0, 1, 1, 1, -1, -1, -1}; const int dy8[8] = {1, -1, 0, 1, -1, 1, 0, -1}; class node { public: int x, y, z; node(int a, int b, int c) { x = a; y = b; z = c; } }; bool operator<(const node &a, const node &b) { return a.x > b.x; } bool compare(const node &a, const node &b) { return a.x < b.x; } void solve() {} void input() { int n, k; cin >> n >> k; int ans = INT_MIN; int f, t; for (int i = 0; i < n; i++) { cin >> f >> t; if (t > k) ans = max(ans, f - t + k); else ans = max(ans, f); } cout << ans << endl; } int main() { int testcase = 1; for (int i = 0; i < testcase; i++) { input(); solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 50, mo = 998244353; int head[N], nn[N << 1][2], cnt; void link(int u, int v) { nn[++cnt][1] = v, nn[cnt][0] = head[u], head[u] = cnt; nn[++cnt][1] = u, nn[cnt][0] = head[v], head[v] = cnt; return; } int f[N][3]; void dfs(int x, int fa) { f[x][0] = 1; for (int i = head[x], y; i; i = nn[i][0]) if ((y = nn[i][1]) != fa) { dfs(y, x); int s1 = f[x][1], s2 = f[x][2]; f[x][1] = (1ll * (f[x][0] + s2) * (f[y][0] + f[y][2]) % mo + 2ll * s1 * f[y][1] % mo + 1ll * s1 * f[y][0]) % mo; f[x][2] = (2ll * s2 * f[y][1] + 1ll * f[x][0] * f[y][1] + 1ll * s2 * f[y][0]) % mo; f[x][0] = 1ll * f[x][0] * (f[y][0] + f[y][1]) % mo; } return; } int main() { int n, u, v; cin >> n; for (int i = 1; i < n; ++i) scanf( %d%d , &u, &v), link(u, v); dfs(1, 0); cout << (f[1][0] + f[1][1]) % mo; return 0; }
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 4, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output reg [575:0] out; /* to "f_permutation" module */
output out_ready; /* to "f_permutation" module */
input f_ack; /* from "f_permutation" module */
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
reg done; /* == 1: out_ready should be 0 */
reg [17:0] i; /* length of "out" buffer */
wire [31:0] v0; /* output of module "padder1" */
reg [31:0] v1; /* to be shifted into register "out" */
wire accept, /* accept user input? */
update;
assign buffer_full = i[17];
assign out_ready = buffer_full;
assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= {out[575-32:0], v1};
always @ (posedge clk)
if (reset)
i <= 0;
else if (f_ack | update)
i <= {i[16:0], 1'b1} & {18{~ f_ack}};
/* if (f_ack) i <= 0; */
/* if (update) i <= {i[16:0], 1'b1}; // increase length */
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
always @ (posedge clk)
if (reset)
done <= 0;
else if (state & out_ready)
done <= 1;
padder1 p0 (in, byte_num, v0);
always @ (*)
begin
if (state)
begin
v1 = 0;
v1[7] = v1[7] | i[16]; // "v1[7]" is the MSB of the last byte of "v1"
end
else if (is_last == 0)
v1 = in;
else
begin
v1 = v0;
v1[7] = v1[7] | i[16];
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:54:44 10/08/2014
// Design Name: pwm
// Module Name: /home/bjones/src/fpga-led-counter/test/pwm_tb.v
// Project Name: fpga-led-counter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pwm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pwm_tb;
// Inputs
reg clk;
reg rst;
reg [23:0] compare0;
reg [23:0] period0;
// Outputs
wire pwm_out;
// Instantiate the Unit Under Test (UUT)
pwm uut (
.clk(clk),
.rst(rst),
.period(period0),
.compare(compare0),
.pwm(pwm_out)
);
// clock and reset block
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#10;
// toggle clock a bit
repeat(4) #1 clk = ~clk;
// bring rst low
rst = 0;
// generate the clock forever
forever #1 clk = ~clk;
end
// set parameters for pwm modules
initial begin
compare0 = 0;
period0 = 0;
@(negedge rst); // wait for reset to lower
compare0 = 192; // 75%
period0 = 256;
repeat(1000) @(posedge clk);
$finish;
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY BER monitor
*/
module eth_phy_10g_rx_ber_mon #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2(COUNT_125US);
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
reg [3:0] ber_count_reg = 4'd0, ber_count_next;
reg rx_high_ber_reg = 1'b0, rx_high_ber_next;
assign rx_high_ber = rx_high_ber_reg;
always @* begin
if (time_count_reg > 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = time_count_reg;
end
ber_count_next = ber_count_reg;
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end else begin
// invalid header
if (ber_count_reg == 4'd15) begin
rx_high_ber_next = 1'b1;
end else begin
ber_count_next = ber_count_reg + 1;
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end
if (time_count_reg == 0) begin
// 125 us timer expired
ber_count_next = 4'd0;
time_count_next = COUNT_125US;
end
end
always @(posedge clk) begin
if (rst) begin
time_count_reg <= COUNT_125US;
ber_count_reg <= 4'd0;
rx_high_ber_reg <= 1'b0;
end else begin
time_count_reg <= time_count_next;
ber_count_reg <= ber_count_next;
rx_high_ber_reg <= rx_high_ber_next;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_SWITCH.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:41 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_SWITCH (
input IN_0,
input IN_1,
input SW ,
output OUT
);
assign OUT=SW?IN_1:IN_0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_1_V
`define SKY130_FD_SC_MS__DLXBP_1_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_1_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int mode, t; const int INF = 1e9 + 7; void solve() { int n, k; cin >> n >> k; string s; cin >> s; int rot = 0; if (s[0] == s[n - 1]) { int start = -1; for (int i = 0; i < n - 1; i++) { if (s[i] != s[i + 1]) { start = i + 1; break; } } if (start < 0) { cout << s << endl; return; } rotate(s.begin(), s.begin() + start, s.end()); rot = start; } vector<int> sizes; char prev = s[0]; int size = 0; for (char c : s) { if (c == prev) { size++; } else { sizes.push_back(size); prev = c; size = 1; } } sizes.push_back(size); int groups = sizes.size(); vector<int> dist(groups, INF); for (int i = 0; i < 2 * groups; i++) { if (sizes[i % groups] > 1) { dist[i % groups] = 0; } else { dist[i % groups] = min(dist[i % groups], 1 + dist[(i - 1 + groups) % groups]); } } for (int i = 2 * groups - 1; i >= 0; i--) { dist[i % groups] = min(dist[i % groups], 1 + dist[(i + 1 + groups) % groups]); } vector<char> answer(n); int i = 0; char curr = s[0]; for (int group_no = 0; group_no < groups; group_no++) { if (sizes[group_no] > 1) { for (int rep = 0; rep < sizes[group_no]; rep++) { answer[i] = curr; i++; } } else { if (k <= dist[group_no]) { if (k % 2) { answer[i] = B + W - curr; } else { answer[i] = curr; } } else { if (dist[group_no] % 2) { answer[i] = B + W - curr; } else { answer[i] = curr; } } i++; } curr = B + W - curr; } rotate(answer.begin(), answer.begin() + n - rot, answer.end()); for (char c : answer) { cout << c; } cout << endl; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); mode = 0; if (mode == 0) { solve(); } else { cin >> t; while (t--) { solve(); } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:59:45 11/30/2014
// Design Name:
// Module Name: ALUNeuronalNetwork
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUNeuronalNetwork #(parameter Width = 4, Magnitud = 2, Precision = 1, Signo = 1)
(CLK,reset,EnableLoadCoeff, EnableMul,EnableSum,InDato,Acumulador,SELCoeff,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,
Coeff19,Offset,Error,OutDato);
input CLK, reset, EnableLoadCoeff,EnableMul,EnableSum;
input [4:0] SELCoeff;
input signed [Width-1:0] InDato,Acumulador,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,
Coeff18,Coeff19,Offset;
output Error;
output signed [Width-1:0] OutDato;
wire signed [Width-1:0] CoefficienteEntrenamiento, OutMult;
wire Error1,Error2;
RegistroWithMuxInput #(.Width(Width)) RegistroWithMuxInputcopiaCargaCoeff (
.CLK(CLK), //************************
.EnableRegisterIn(EnableLoadCoeff), //************************
.reset(reset), //************************
.SEL(SELCoeff), //************************
.Coeff00(Coeff00), //************************
.Coeff01(Coeff01), //************************
.Coeff02(Coeff02), //************************
.Coeff03(Coeff03), //************************
.Coeff04(Coeff04), //************************
.Coeff05(Coeff05), //************************
.Coeff06(Coeff06), //************************
.Coeff07(Coeff07), //************************
.Coeff08(Coeff08), //************************
.Coeff09(Coeff09), //************************
.Coeff10(Coeff10), //************************
.Coeff11(Coeff11), //************************
.Coeff12(Coeff12), //************************
.Coeff13(Coeff13), //************************
.Coeff14(Coeff14), //************************
.Coeff15(Coeff15), //************************
.Coeff16(Coeff16), //************************
.Coeff17(Coeff17), //************************
.Coeff18(Coeff18), //************************
.Coeff19(Coeff19), //************************
.Offset(Offset), //************************
.OutCoeff(CoefficienteEntrenamiento) //*************************
);
multiplicadorPuntoFijo #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
multiplicadorPuntoFijoNeuronalNetwork (
.EnableMul(EnableMul), //*************************
.In(InDato), //*************************
.Coeff(CoefficienteEntrenamiento), //*************************
.OutMul(OutMult), //*************************
.Error(Error1) //*************************
);
sumadorPuntoFijo #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
sumadorPuntoFijoNeuronalNetwork (
.EnableSum(EnableSum), //**********************
.In(OutMult), //*************************
.Acumulador(Acumulador), //*************************
.OutSum(OutDato), //*************************
.Error(Error2) //*************************
);
assign Error = Error1 | Error2;
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int x; cin >> x; while (x--) { int n, m, ans = 0; cin >> n >> m; char a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> a[i][j]; } int i = n - 1; for (int j = 0; j < m - 1; j++) { if (a[i][j] == D ) ans++; } int j = m - 1; for (i = 0; i < n - 1; i++) { if (a[i][j] == R ) ans++; } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e4; long long a[maxn]; int v[maxn]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); for (long long i = 1; i < maxn; i++) { a[i] = i * (i - 1) / 2; } int T; cin >> T; while (T--) { long long n; cin >> n; int tn = 0; for (int i = maxn - 1; i && n; i--) { while (n >= a[i]) { n -= a[i]; v[++tn] = i; } } v[tn + 1] = 0; for (int i = 1; i <= tn; i++) { cout << 1; for (int j = 0; j < v[i] - v[i + 1]; j++) cout << 3; } cout << 7 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); vector<int> w(n, 0); w[0] = v[0]; for (int i = 1; i < n; i++) w[i] = w[i - 1] + v[i]; int score = 0, penalty = 0; for (int i = 0; i < n; i++) { if (w[i] <= 60 * 12 - 10) score++; else break; if (w[i] > 60 * 6 - 10) penalty += w[i] - 60 * 6 + 10; } cout << score << << penalty << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A311OI_PP_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_PP_SYMBOL_V
|
// "flop_it-c.v"
// @vcs-flags@ -P pli.tab
`timescale 1ps / 1ps
// `include "standard.v"
`include "standard.v-wrap"
`include "clkgen.v"
//-----------------------------------------------------------------------------
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a;
wire clk;
wire z;
clk_gen #(.HALF_PERIOD(50)) cg(clk);
initial
begin
// @haco@ flop_it.haco-c
$prsim("flop_it.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.clk", "clk");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
// test using escaped identifiers
HAC_POS_FLOP #(.prsim_name("F.f[0]")) \F.f[0] ();
HAC_POS_FLOP #(.prsim_name("F.f[1]")) \F.f[1] ();
HAC_POS_FLOP #(.prsim_name("F.f[2]")) \F.f[2] ();
HAC_POS_FLOP #(.prsim_name("F.f[3]")) \F.f[3] ();
initial
begin
#20 a <= 1'b0;
#400 a <= 1'b1;
#400 a <= 1'b0;
#100 a <= 1'b1;
#100 a <= 1'b0;
#100 a <= 1'b1;
#300 a <= 1'b0;
#50 $finish;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
// - - - - - - - - - -ADC- - - - - - - - - - - - - - -
module adv_adc (clock, reset, go, sclk, cs_n, din, dout, done, reading0, reading1,
reading2, reading3, reading4, reading5, reading6, reading7);
input go, dout, clock, reset;
output reg done;
output reg sclk, din, cs_n;
output reg [11:0] reading0, reading1, reading2, reading3, reading4, reading5, reading6, reading7;
parameter T_SCLK = 8'd16;
parameter NUM_CH = 4'd8;
//FSM state values
parameter resetState = 3'd0, waitState=3'd1, transState=3'd2, doneState=3'd3, pauseState=3'd4;
reg [2:0] currState, nextState;
reg [10:0] shift_reg;
reg [5:0] addr_shift_reg;
reg [7:0] counter;
reg [3:0] sclk_counter;
reg [2:0] address, next_addr;
always @(posedge clock)
currState <=nextState;
// - - - - -NextState Selection Logic - - - - - - - -
always @(*)
begin
din = addr_shift_reg[5];
if (reset)
nextState=resetState;
case (currState)
resetState:begin
cs_n=1;
done=0;
nextState=waitState;
end
waitState:begin
cs_n=1;
done=0;
if (go)
nextState=transState;
else
nextState=waitState;
end
transState:begin
cs_n=0;
done=0;
if (sclk_counter==4'd15&& counter==0 && !sclk)
nextState=pauseState;
else
nextState=transState;
end
pauseState:begin
cs_n=0;
done=0;
if(address==3'd0)
nextState=doneState;
else
nextState=transState;
end
doneState:begin
cs_n=1;
done=1;
if (go)
nextState=doneState;
else
nextState=waitState;
end
default:begin
cs_n=1;
done=0;
nextState = resetState;
end
endcase
end
// - - - - - - - - - counter logic - - - - - - - - - -
always @(posedge clock or posedge reset)
if (reset)
counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
else if (cs_n)
counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
else if (counter == 0)
counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
else
counter <= counter - 8'b1;
// - - - - - - - - ADC_SCLK generation - - - - - - - - -
always @(posedge clock or posedge reset)
if (reset)
sclk <= 1;
else if (cs_n)
sclk <= 1;
else if (counter == 0)
sclk <= ~sclk;
// - - - - - - - - - - - sclk_counter logic - - - - - - - -
always @ (posedge clock)
if (currState == doneState || currState == waitState)
sclk_counter <=4'b0;
else if (counter == 0 && !sclk)
sclk_counter <= sclk_counter + 4'b1;
// - - - - - - - - - - readings logic - - - - - - - - - -
always @(posedge clock)
if (sclk_counter == 4'd15 && counter == 0 && !sclk)
if (address == 0)
case (NUM_CH)
4'd2: reading1 <= {shift_reg[10:0],dout};
4'd3: reading2 <= {shift_reg[10:0],dout};
4'd4: reading3 <= {shift_reg[10:0],dout};
4'd5: reading4 <= {shift_reg[10:0],dout};
4'd6: reading5 <= {shift_reg[10:0],dout};
4'd7: reading6 <= {shift_reg[10:0],dout};
4'd8: reading7 <= {shift_reg[10:0],dout};
endcase
else
case (address)
3'd1: reading0 <= {shift_reg[10:0],dout};
3'd2: reading1 <= {shift_reg[10:0],dout};
3'd3: reading2 <= {shift_reg[10:0],dout};
3'd4: reading3 <= {shift_reg[10:0],dout};
3'd5: reading4 <= {shift_reg[10:0],dout};
3'd6: reading5 <= {shift_reg[10:0],dout};
3'd7: reading6 <= {shift_reg[10:0],dout};
endcase
// - - - - - - - - - address logic - - - - - - - - -
always @(posedge clock)
if (currState == resetState)
address <= 3'd1;
else if (currState == pauseState)
if (address >= (NUM_CH-1))
address <= 3'd0;
else
address <= next_addr;
// - - - - - - - - - - shift_reg logic - - - - - - - - - - - -
always @(posedge clock)
if (counter==0 && !sclk && sclk_counter != 4'd15)
shift_reg [10:0] <= {shift_reg [9:0], dout};
// - - - - - - - - - - addr_shift_reg logic - - - - - - - - -
always @(posedge clock)
if (currState == waitState && go)
addr_shift_reg <= 6'b000001;
else if (currState == pauseState)
if (address >= (NUM_CH-1))
addr_shift_reg <= 6'b0;
else
addr_shift_reg <= {3'b0, next_addr,};
else if (counter==0 && sclk)
addr_shift_reg <={addr_shift_reg[4:0],1'b0};
// - - - - - - - - - - next_addr logic - - - - - - - - - - - -
always @(posedge clock)
next_addr <= address + 3'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_1_V
`define SKY130_FD_SC_LS__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_LP_V
`define SKY130_FD_SC_LP__MUX4_LP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_lp (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_lp (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_LP_V
|
#include <bits/stdc++.h> using namespace std; long long arr[100005], tree[100005], used[100005], l[100005], r[100005], d[100005], b[100005], query[100005], x, y, n, m, k; template <class T> inline T lowbit(T n) { return (n & -n); } void update(long long s[], int index, long long val) { while (index <= 100005) { s[index] += val; index += (index & (-index)); } } long long getS(long long s[], int l, int r) { if (l > r) return 0; else if (l == 1) { long long res = 0; for (; r > 0; r -= lowbit(r)) res += s[r]; return res; } else { return getS(s, 1, r) - getS(s, 1, l - 1); } } int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < m; i++) { cin >> l[i] >> r[i] >> d[i]; } for (int i = 0; i < k; i++) { cin >> x >> y; update(tree, x, 1); update(tree, y + 1, -1); } for (int i = 1; i <= m; i++) { used[i] = getS(tree, 1, i); } for (int i = 0; i < m; i++) { update(b, l[i], d[i] * used[i + 1]); update(b, r[i] + 1, -d[i] * used[i + 1]); } for (int i = 0; i < n; i++) { query[i + 1] = getS(b, 1, i + 1); } for (int i = 1; i <= n; i++) { cout << arr[i - 1] + query[i]; if (i != n) { cout << ; } else { cout << endl; } } }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module scales down the frame size of video streams for the DE boards. *
* *
******************************************************************************/
module altera_up_video_scaler_shrink (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter WW = 9; // Image In: width's address width
parameter HW = 9; // Image In: height's address width
parameter WIDTH_IN = 640; // Image In's width in pixels
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire drop;
wire capture_inputs;
wire transfer_data;
// Internal Registers
reg saved_startofpacket;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [WW: 0] width_counter;
reg [HW: 0] height_counter;
reg [ 3: 0] drop_pixel;
reg [ 3: 0] drop_line;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= data;
stream_out_startofpacket <= startofpacket;
stream_out_endofpacket <= endofpacket;
stream_out_valid <= valid;
end
else if (stream_out_ready & stream_out_valid)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
end
// Internal Registers
always @(posedge clk)
if (reset)
saved_startofpacket <= 1'b0;
else if (capture_inputs)
saved_startofpacket <= 1'b0;
else if (stream_in_ready)
saved_startofpacket <= saved_startofpacket | stream_in_startofpacket;
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (capture_inputs)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket | saved_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
else if (stream_in_ready)
endofpacket <= endofpacket | stream_in_endofpacket;
end
always @(posedge clk)
begin
if (reset)
width_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket | (width_counter == (WIDTH_IN - 1)))
width_counter <= 'h0;
else
width_counter <= width_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
height_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
height_counter <= 'h0;
else if (width_counter == (WIDTH_IN - 1))
height_counter <= height_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
drop_pixel <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_pixel <= WIDTH_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_pixel <= WIDTH_DROP_MASK;
else
drop_pixel <= {drop_pixel[2:0], drop_pixel[3]};
end
end
always @(posedge clk)
begin
if (reset)
drop_line <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_line <= HEIGHT_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_line <= {drop_line[2:0], drop_line[3]};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (drop | ~valid | transfer_data);
// Internal Assignments
assign drop = drop_pixel[0] | drop_line[0];
assign capture_inputs = stream_in_ready & ~drop;
assign transfer_data = ~stream_out_valid & stream_in_valid & ~drop;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int result = 0; for (int i = 0; i < n; i++) { int k, a; cin >> k >> a; long x = k * a; int c = 0; if (a % 4 == 0) a--; while (a) { a /= 4; c++; } result = (((result) < (k + c)) ? (k + c) : (result)); } cout << result; }
|
module stimulus (output reg A, B);
initial begin
{A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
2'b00: gate_output = 0;
2'b01: gate_output = 1;
2'b10: gate_output = 1;
2'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in XOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
xor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:23 10/06/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_tx(clk, reset, wren, rden, din, dout, txout, addr);
input clk, reset, wren, rden;
input [7:0] din;
output [7:0] dout;
output txout; //serial data out
input [2:0] addr;
// corgen fifo
/*module fifo(clk, rst, din, wr_en, rd_en, dout, full, empty
);
input clk;
input rst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;*/
/*baud generator
module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
input wren, rden, reset, clk, sclr;
input [7:0] din;
output baud;
output [7:0] dout;
*/
reg [7:0] control, dout;
reg [9:0] shift_out;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [1:0] nstate, pstate;
parameter PERIOD = 8'h1A;
wire [7:0] to_shift, dout_baud;
wire [9:0] shift;
wire baud, full, empty;
`define period 3'b000
`define TXreg 3'b001
`define control 3'b011
`define WAIT 2'b00
`define SHIFT1 2'b01
`define SHIFT2 2'b10
`define TXFULL control[0]
`define TXDONE control[1]
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
fifo fifo1(
.clk (clk),
.rst (reset),
.din (din),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (to_shift),
.full (full),
.empty (empty)
);
// assign shift_in
assign shift = ({1'b1, to_shift, 1'b0});
assign txout = shift_out[0];
// shift register
always @(posedge clk or posedge reset) begin
if(reset)
shift_out <= 10'b1111111111;
else begin
if (rd_shift)begin
//txout = shift_out[0];
shift_out <= {1'b1, shift_out[9:1]};
end
if (ld_shift)
shift_out <= shift;
end
end
// control register
always @(posedge clk or posedge reset) begin
if(reset) begin
control[7:0] = 8'b00000001;
end
else begin
`TXFULL = full;
if(finish)
`TXDONE = 1;
if(wr_control)
`TXDONE = 0;
end
end
// address mux logic
always @* begin
wr_baud = 0;
wr_fifo = 0; wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`TXreg: begin
if(wren)
wr_fifo = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
// out mux
always @* begin
rd_baud = 0;
dout = 8'b00000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `WAIT;
else
pstate <= nstate;
end
// fsm
always @* begin
rd_fifo = 0; ld_shift = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0;
nstate = pstate;
case (pstate)
`WAIT: begin
stop = 1;
if(~empty) begin
stop = 0;
rd_fifo = 1;
ld_shift = 1;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `WAIT;
finish = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
rd_shift = 1;
nstate = `SHIFT1;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long s, xo; cin >> s >> xo; if ((s - xo) % 2 != 0 || (s < xo)) { cout << 0 << endl; return 0; } if ((((s - xo) / 2) & xo) != 0) { cout << 0 << endl; return 0; } if (xo == 0) { cout << 1 << endl; return 0; } long long f = 1; long long ans = 0; long long nx = xo; while (xo != 0) { if ((f & xo) != 0) { xo -= f; ans++; } f = f * 2; } ans = pow(2, ans); if (s == nx) ans -= 2; cout << ans << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define il inline #define rg register #define int long long #define M 998244353 const int P=3,Pn=332748118; il int read() { int re=0,k=1;char ch=getchar(); while(ch> 9 ||ch< 0 ){if(ch== - )k=-1;ch=getchar();} while(ch<= 9 &&ch>= 0 ){re=re*10+ch-48;ch=getchar();} return re*k; } il void write(long long x) { if(x<0)return putchar( - ),write(-x),void(); if(x<10)return putchar(x+ 0 ),void(); return write(x/10),putchar(x%10+ 0 ),void(); } signed main() { int T,a,b,c,d; T=read(); while(T--) { d=read();a=read();b=read();c=read(); int ans=min((a-d%a)%a,min((b-d%b)%b,(c-d%c)%c)); write(ans);puts( ); } }
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Missing pin: VPA
// All address decoding was checked except BITW1, nCTRL1_ZONE, and nCTRL2_ZONE
module neo_c1(
input [21:17] M68K_ADDR,
output [15:8] M68K_DATA,
input A22Z, A23Z,
input nLDS, nUDS,
input RW, nAS,
output nROMOEL, nROMOEU,
output nPORTOEL, nPORTOEU,
output nPORTWEL, nPORTWEU,
output nPORT_ZONE,
output nWRL, nWRU,
output nWWL, nWWU,
output nSROMOEL, nSROMOEU,
output nSRAMOEL, nSRAMOEU,
output nSRAMWEL, nSRAMWEU,
output nLSPOE, nLSPWE,
output nCRDO, nCRDW, nCRDC,
output nSDW,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nCD1, nCD2, nWP,
input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
inout [7:0] SDD,
input nSDZ80R, nSDZ80W, nSDZ80CLR,
input CLK_68KCLK,
output nDTACK,
output nBITW0, nBITW1, nDIPRD0, nDIPRD1,
output nPAL_ZONE,
input SYSTEM_MODE
);
wire nIO_ZONE; // Internal
wire nC1REGS_ZONE; // Internal
wire nROM_ZONE; // Internal
wire nWRAM_ZONE; // Internal (external for PCB)
wire nPORT_ZONE; // Internal (external for PCB)
wire nCTRL1_ZONE; // Internal (external for PCB)
wire nICOM_ZONE; // Internal
wire nCTRL2_ZONE; // Internal (external for PCB)
wire nSTATUSB_ZONE; // Internal (external for PCB)
wire nLSPC_ZONE; // Internal
wire nCARD_ZONE; // Internal
wire nSROM_ZONE; // Internal
wire nSRAM_ZONE; // Internal (external for PCB)
c1_regs C1REGS(nICOM_ZONE, RW, M68K_DATA, SDD, nSDZ80R, nSDZ80W, nSDZ80CLR, nSDW);
c1_wait C1WAIT(CLK_68KCLK, nAS, nROM_ZONE, nPORT_ZONE, nCARD_ZONE, nROMWAIT, nPWAIT0,
nPWAIT1, PDTACK, nDTACK);
c1_inputs C1INPUTS(nCTRL1_ZONE, nCTRL2_ZONE, nSTATUSB_ZONE, M68K_DATA, P1_IN[9:0], P2_IN[9:0],
nWP, nCD2, nCD1, SYSTEM_MODE);
// 000000~0FFFFF read/write
assign nROM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], M68K_ADDR[20]};
// 100000~1FFFFF read/write
assign nWRAM_ZONE = |{A23Z, A22Z, M68K_ADDR[21], ~M68K_ADDR[20]};
// 200000~2FFFFF read/write
assign nPORT_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], M68K_ADDR[20]};
// 300000~3FFFFF read/write
assign nIO_ZONE = |{A23Z, A22Z, ~M68K_ADDR[21], ~M68K_ADDR[20]};
// 300000~3FFFFE even bytes read/write
assign nC1REGS_ZONE = nUDS | nIO_ZONE;
// 300000~31FFFE even bytes read only
assign nCTRL1_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 320000~33FFFE even bytes read/write
assign nICOM_ZONE = nC1REGS_ZONE | |{M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17]};
// 340000~35FFFE even bytes read only - Todo: MAME says A17 is used, see right below
assign nCTRL2_ZONE = nC1REGS_ZONE | ~RW | |{M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 360000~37FFFF is not mapped ?
// 30xxxx 31xxxx odd bytes read only
assign nDIPRD0 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], ~RW, nLDS};
// 32xxxx 33xxxx odd bytes read only
assign nDIPRD1 = |{nIO_ZONE, M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17], ~RW, nLDS};
// 38xxxx 39xxxx odd bytes write only
assign nBITW0 = |{nIO_ZONE, ~M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17], RW, nLDS};
// 380000~39FFFE even bytes read only
assign nSTATUSB_ZONE = nC1REGS_ZONE | ~RW | |{~M68K_ADDR[19], M68K_ADDR[18], M68K_ADDR[17]};
// 3A0001~3BFFFF odd bytes write only
assign nBITW1 = |{nIO_ZONE, ~M68K_ADDR[19], M68K_ADDR[18], ~M68K_ADDR[17], RW, nLDS};
// 3C0000~3DFFFF
assign nLSPC_ZONE = |{nIO_ZONE, ~M68K_ADDR[19], ~M68K_ADDR[18], M68K_ADDR[17]};
// 3E0000~3FFFFF is not mapped ? To check
// 400000~7FFFFF
assign nPAL_ZONE = |{A23Z, ~A22Z, (nLDS & nUDS)};
// 800000~BFFFFF
assign nCARD_ZONE = |{~A23Z, A22Z};
// C00000~CFFFFF
assign nSROM_ZONE = |{~A23Z, ~A22Z, M68K_ADDR[21], M68K_ADDR[20]};
// D00000~DFFFFF
assign nSRAM_ZONE = |{~A23Z, ~A22Z, M68K_ADDR[21], ~M68K_ADDR[20]};
// Outputs:
assign nROMOEL = ~RW | nLDS | nROM_ZONE;
assign nROMOEU = ~RW | nUDS | nROM_ZONE;
assign nPORTOEL = ~RW | nLDS | nPORT_ZONE;
assign nPORTOEU = ~RW | nUDS | nPORT_ZONE;
assign nPORTWEL = RW | nLDS | nPORT_ZONE;
assign nPORTWEU = RW | nUDS | nPORT_ZONE;
assign nWRL = ~RW | nLDS | nWRAM_ZONE;
assign nWRU = ~RW | nUDS | nWRAM_ZONE;
assign nWWL = RW | nLDS | nWRAM_ZONE;
assign nWWU = RW | nUDS | nWRAM_ZONE;
assign nSROMOEL = ~RW | nLDS | nSROM_ZONE;
assign nSROMOEU = ~RW | nUDS | nSROM_ZONE;
assign nSRAMOEL = ~RW | nLDS | nSRAM_ZONE;
assign nSRAMOEU = ~RW | nUDS | nSRAM_ZONE;
assign nSRAMWEL = RW | nLDS | nSRAM_ZONE;
assign nSRAMWEU = RW | nUDS | nSRAM_ZONE;
// Todo: Check if TG68k duplicates byte on data bus on byte writes (it should !)
assign nLSPWE = RW | nUDS | nLSPC_ZONE;
assign nLSPOE = ~RW | nUDS | nLSPC_ZONE;
assign nCRDO = ~RW | nCARD_ZONE | nUDS;
assign nCRDW = RW | nCARD_ZONE | nUDS;
assign nCRDC = nCARD_ZONE | nAS;
endmodule
|
#include <bits/stdc++.h> using namespace std; clock_t __stt; inline void TStart() { __stt = clock(); } inline void TReport() { cerr << fixed << setprecision(3) << nCurrent Case Taken Time : << (double)(clock() - __stt) / CLOCKS_PER_SEC << sec n ; } template <typename T> T MIN(T a, T b) { return a < b ? a : b; } template <typename T> T MAX(T a, T b) { return a > b ? a : b; } template <typename T> T ABS(T a) { return a > 0 ? a : (-a); } template <typename T> void UMIN(T &a, T b) { if (b < a) a = b; } template <typename T> void UMAX(T &a, T b) { if (b > a) a = b; } int n, m, p[100005], s[100005], b[100005], inc[100005], pref[100005]; struct ele { int A, B, C, id; void set(int _A, int _B, int _C, int _id) { A = _A; B = _B; C = _C; id = _id; } } es[100005], et[100005]; struct qry { int Al, Ar, B, C; void set(int _Al, int _Ar, int _B, int _C) { Al = _Al; Ar = _Ar; B = _B; C = _C; } } qs[100005], qt[100005]; namespace BIT { int arr[300005]; void add(int p, int v = 1) { ++p; while (p <= 300002) { arr[p] += v; p += (p & (-p)); } } void clr(int p) { ++p; while (p <= 300002) { arr[p] = 0; p += (p & (-p)); } } int sum(int p) { int r = 0; ++p; while (p) { r += arr[p]; p -= (p & (-p)); } return r; } } // namespace BIT bool cmpB(ele a, ele b) { return a.B < b.B; } bool cmpC(ele a, ele b) { return a.C < b.C; } bool cmpBq(qry a, qry b) { return a.B < b.B; } bool cmpCq(qry a, qry b) { return a.C < b.C; } vector<int> vs; int id(int v) { return lower_bound(vs.begin(), vs.end(), v) - vs.begin(); } int res[100005]; void solve2d(ele *E, int ec, qry *Q, int qc) { int i, j, k; sort(E, E + ec, cmpB); sort(Q, Q + qc, cmpBq); reverse(Q, Q + qc); reverse(E, E + ec); j = 0; for (i = 0; i < ec; ++i) { int cB = E[i].B; while (j < qc && Q[j].B >= cB) { BIT::add(Q[j].Al, 1); BIT::add(Q[j].Ar + 1, -1); ++j; } res[E[i].id] += BIT::sum(E[i].A); } for (i = 0; i < qc; ++i) { BIT::clr(Q[i].Al); BIT::clr(Q[i].Ar + 1); } } void solve(int cl, int cr, int ql, int qr, int el, int er) { if (ql > qr || el > er) return; int i, j, k; if (cl == cr) { solve2d(es + el, er - el + 1, qs + ql, qr - ql + 1); return; } memcpy(et + el, es + el, sizeof(ele) * (er - el + 1)); memcpy(qt + ql, qs + ql, sizeof(qry) * (qr - ql + 1)); int cM = ((long long)cl + (long long)cr) / 2ll, qM, eM; for (qM = ql; qM <= qr; ++qM) { if (qt[qM].C <= cM && (qM == qr || qt[qM + 1].C > cM)) break; } if (qt[ql].C > cM) qM = ql - 1; for (eM = el; eM <= er; ++eM) { if (et[eM].C <= cM && (eM == er || et[eM + 1].C > cM)) break; } if (et[el].C > cM) eM = el - 1; if (er > eM && qM >= ql) solve2d(et + eM + 1, er - eM, qt + ql, qM - ql + 1); solve(cl, cM, ql, qM, el, eM); solve(cM + 1, cr, qM + 1, qr, eM + 1, er); } int main() { int i, j, k; scanf( %d%d , &n, &m); for (i = 0; i < n; ++i) scanf( %d , p + i); for (i = 0; i < n; ++i) scanf( %d , s + i); for (i = 0; i < n; ++i) scanf( %d , b + i); for (i = 0; i < m; ++i) scanf( %d , inc + i); for (i = 0; i < m; ++i) scanf( %d , pref + i); for (i = 0; i < n; ++i) { qs[i].Al = p[i]; qs[i].Ar = s[i]; vs.push_back(p[i]); vs.push_back(s[i]); qs[i].B = b[i] - p[i]; qs[i].C = b[i] + p[i]; } for (j = 0; j < m; ++j) { es[j].A = inc[j]; vs.push_back(inc[j]); es[j].B = pref[j] - inc[j]; es[j].C = pref[j] + inc[j]; es[j].id = j; } sort(vs.begin(), vs.end()); vs.erase(unique(vs.begin(), vs.end()), vs.end()); for (i = 0; i < n; ++i) { qs[i].Al = id(qs[i].Al); qs[i].Ar = id(qs[i].Ar); } for (j = 0; j < m; ++j) { es[j].A = id(es[j].A); } sort(es, es + m, cmpC); sort(qs, qs + n, cmpCq); solve(0, (int)2e9 + 5, 0, n - 1, 0, m - 1); for (i = 0; i < m; ++i) { printf( %d , res[i]); } return 0; }
|
module sevenseg(input [15:0] value, input clk, output reg [3:0] an, output [6:0] seg);
// Duty Cycle controls the brightness of the seven segment display (0..15)
parameter SEVEN_SEG_DUTY_CYCLE = 0;
reg [15:0] counter;
reg [3:0] binary;
reg [6:0] sseg;
always @(posedge clk) begin
counter <= counter + 1;
// important to enable anode with a low duty cycle, as no resistors!
if (counter[13:10] <= SEVEN_SEG_DUTY_CYCLE) begin
case (counter[15:14])
2'b00:
{ an[0], binary} <= {1'b0, value[15:12]};
2'b01:
{ an[1], binary} <= {1'b0, value[11:8]};
2'b10:
{ an[2], binary} <= {1'b0, value[7:4]};
2'b11:
{ an[3], binary} <= {1'b0, value[3:0]};
endcase
end else begin
an <= 4'b1111;
end
end
always @(binary)
case (binary)
4'b0000 :
sseg <= 7'b1111110; // ABCDEFG
4'b0001 :
sseg <= 7'b0110000;
4'b0010 :
sseg <= 7'b1101101;
4'b0011 :
sseg <= 7'b1111001;
4'b0100 :
sseg <= 7'b0110011;
4'b0101 :
sseg <= 7'b1011011;
4'b0110 :
sseg <= 7'b1011111;
4'b0111 :
sseg <= 7'b1110000;
4'b1000 :
sseg <= 7'b1111111;
4'b1001 :
sseg <= 7'b1111011;
4'b1010 :
sseg <= 7'b1110111;
4'b1011 :
sseg <= 7'b0011111;
4'b1100 :
sseg <= 7'b1001110;
4'b1101 :
sseg <= 7'b0111101;
4'b1110 :
sseg <= 7'b1001111;
4'b1111 :
sseg <= 7'b1000111;
endcase
// segements are active low
assign seg = sseg ^ 7'b1111111;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int Time = 0; string s; bool dp[2][(int)1e5 + 10]; struct Node { int nxt[26]; bool leaf; Node() { for (int i = 0; i < 26; i++) nxt[i] = -1; leaf = 1; } } trie[(int)1e5 + 10]; void dodaj(string s) { int niz[100010]; for (int i = 0; i < s.size(); i++) niz[i] = s[i] - a ; int tr = 0; for (int i = 0; i < s.size(); i++) { if (trie[tr].nxt[niz[i]] == -1) trie[tr].nxt[niz[i]] = ++Time; trie[tr].leaf = 0; tr = trie[tr].nxt[niz[i]]; } } bool uradi0(int tr, bool minn) { if (trie[tr].leaf) { dp[0][tr] = 1; return 1; } for (int i = 0; i < 26; i++) { if (trie[tr].nxt[i] != -1) minn = min(minn, uradi0(trie[tr].nxt[i], 1)); } dp[0][tr] = 1 ^ minn; return dp[0][tr]; } bool uradi1(int tr, bool minn) { if (trie[tr].leaf) { dp[1][tr] = 0; return 0; } for (int i = 0; i < 26; i++) { if (trie[tr].nxt[i] != -1) minn = min(minn, uradi1(trie[tr].nxt[i], 1)); } dp[1][tr] = 1 ^ minn; return dp[1][tr]; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> s; dodaj(s); } uradi0(0, 1); uradi1(0, 1); if (dp[0][0] == 1 && dp[1][0] == 1) cout << First << endl; else if (dp[0][0] == 1) cout << Second << endl; else if (dp[1][0] == 1) cout << ((k % 2 == 1) ? First : Second ) << endl; else cout << Second << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
input SET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[8], pro[1 << 8]; int bit_cnt[1 << 8]; vector<long long> pp; bitset<1000000> p; map<long long, int> H; int N, an; int qq(long long x) { if (H.count(x)) return H[x]; long long X = x; int res = 0; for (int i = 0; i < ((int)(pp).size()) && pp[i] * pp[i] <= x; i++) { while (x % pp[i] == 0) { x /= pp[i]; res++; } } if (x != 1) res++; return H[X] = res; } int qq2(long long x) { if (H.count(x)) { int tmp = H[x]; if (tmp == 1) return 0; return tmp; } long long X = x; int res = 0; for (int i = 0; i < ((int)(pp).size()) && pp[i] * pp[i] <= x; i++) { while (x % pp[i] == 0) { x /= pp[i]; res++; } } if (x != 1) res++; H[X] = res; if (res == 1) return 0; return res; } void dfs(int x, int mask, int v, int head) { if (x == -1) { if (head == 1) an = min(an, v); else an = min(an, v + 1); return; } if (!((mask >> x) & 1)) { v++; head++; } for (int i = 0; i < (1 << x); ++i) { if (!i) { dfs(x - 1, mask, v + qq2(a[x]), head); } else if (!(mask & i) && a[x] % pro[i] == 0) { dfs(x - 1, mask | i, v + bit_cnt[i] + qq(a[x] / pro[i]), head); } } } int main() { for (int i = 3; i < 1000; i += 2) { for (int j = i * i; j < 1000000; j += i + i) p[j] = 1; } pp.push_back(2); for (int i = 3; i < 1000000; i += 2) { if (!p[i]) pp.push_back(i); } int(n); scanf( %d , &n); N = n; for (int i = 0; i < (n); ++i) cin >> a[i]; sort(a, a + n); pro[0] = 1; for (int i = (1); i < (1 << n); ++i) { int k = 0; while (!((i >> k) & 1)) k++; bit_cnt[i] = bit_cnt[i - (1 << k)] + 1; long long tmp1 = pro[i - (1 << k)]; long long tmp2 = a[k]; if (tmp1 > 10000000000000ll / tmp2) pro[i] = 10000000000000ll; else pro[i] = tmp1 * tmp2; } an = 1000000; dfs(n - 1, 0, 0, 0); printf( %d n , an); return 0; }
|
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Programmable interval timer
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* Programmable interval timer
* Registers:
* 0x00 - control register;
* Bits:
* [31:3] - ignored;
* [2] - reload value (1);
* [1] - mask (0) or unmask (1) interrupt;
* [0] - enable (1) and disable (0) timer.
* 0x04 - counter register;
* 0x08 - current count register (read only).
*/
module interval_timer(
clk,
nrst,
/* Interrupt output */
o_intr,
/* OCP interface */
i_MAddr,
i_MCmd,
i_MData,
i_MByteEn,
o_SCmdAccept,
o_SData,
o_SResp
);
/* Timer counter states */
localparam [2:0] STOP = 3'b001;
localparam [2:0] RELOAD = 3'b010;
localparam [2:0] COUNT = 3'b100;
/* Register offsets */
localparam [`ADDR_WIDTH-1:0] CTRLREG = 32'h000; /* Control register */
localparam [`ADDR_WIDTH-1:0] CNTRREG = 32'h004; /* Counter register */
localparam [`ADDR_WIDTH-1:0] CURRREG = 32'h008; /* Current counter */
/* Inputs and outputs */
input wire clk;
input wire nrst;
output reg o_intr;
input wire [`ADDR_WIDTH-1:0] i_MAddr;
input wire [2:0] i_MCmd;
input wire [`DATA_WIDTH-1:0] i_MData;
input wire [`BEN_WIDTH-1:0] i_MByteEn;
output wire o_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_SData;
output reg [1:0] o_SResp;
/* Internal registers */
reg [`DATA_WIDTH-1:0] initval; /* Initial value */
reg [`DATA_WIDTH-1:0] currval; /* Current value */
reg enable; /* Timer enabled */
reg imask; /* Interrupt mask */
reg reload; /* Reload counter automatically */
/* Counter FSM state */
reg [2:0] ctr_state;
reg reload_en; /* Force counter reload */
assign o_SCmdAccept = 1'b1; /* Always ready to accept command */
/* Bus logic */
always @(*)
begin
case(i_MCmd)
`OCP_CMD_WRITE: begin
o_SData = {(`DATA_WIDTH){1'b0}};
o_SResp = `OCP_RESP_DVA;
end
`OCP_CMD_READ: begin
if(i_MAddr == CTRLREG)
begin
o_SData = { {(`DATA_WIDTH-3){1'b0}},
reload, imask, enable };
end
else if(i_MAddr == CNTRREG)
begin
o_SData = { {(`DATA_WIDTH-32){1'b0}}, initval };
end
else if(i_MAddr == CURRREG)
begin
o_SData = { {(`DATA_WIDTH-32){1'b0}}, currval };
end
else
o_SData = 32'hDEADDEAD;
o_SResp = `OCP_RESP_DVA;
end
default: begin
o_SData = {(`DATA_WIDTH){1'b0}};
o_SResp = `OCP_RESP_NULL;
end
endcase
end
/* Configuration update */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
enable <= 1'b0;
imask <= 1'b0;
initval <= {(`DATA_WIDTH){1'b0}};
reload <= 1'b0;
reload_en <= 1'b0;
end
else if(i_MCmd == `OCP_CMD_WRITE)
begin
/* Force reload if updating initial count value */
reload_en <= i_MAddr == CNTRREG ? 1'b1 : 1'b0;
if(i_MAddr == CTRLREG)
begin
enable <= i_MData[0];
imask <= i_MData[1];
reload <= i_MData[2];
end
else if(i_MAddr == CNTRREG)
begin
initval <= i_MData[31:0];
end
end
else
reload_en <= 1'b0;
end
/* Counter FSM */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
currval <= 0;
o_intr <= 1'b0;
ctr_state <= STOP;
end
else if(reload_en)
begin
/* Update current value and restart timer */
currval <= initval;
ctr_state <= STOP;
end
else
begin
case(ctr_state)
STOP: begin
o_intr <= 1'b0;
if(enable)
ctr_state <= COUNT;
end
COUNT: begin
if(currval == 0)
o_intr <= 1'b1 & imask; /* Set interrupt */
else
currval <= currval - 1;
/* After zero reached next state depends on reload flag */
ctr_state <= enable ?
(currval == 0 ?
(reload ? RELOAD : STOP) : COUNT) : STOP;
end
RELOAD: begin
o_intr <= 1'b0;
currval <= initval - 1;
ctr_state <= enable ? COUNT : STOP;
end
default: ctr_state <= STOP;
endcase
end
end
endmodule /* interval_timer */
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_1_0_stub.v
// Design : system_buffer_register_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "buffer_register,Vivado 2016.4" *)
module system_buffer_register_1_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100010]; int us[100010], w[3][100010], z1, z2, dooc; void dfs(int v, int in = 1) { us[v] = in; for (int i = 0; i < g[v].size(); i++) if (us[g[v][i]] == 0) { dfs(g[v][i], (in == 1 ? 2 : 1)); } else if (us[g[v][i]] == in) { dooc = -1; } } int main() { int n, m, u, v, i; cin >> n >> m; while (m--) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (i = 1; i <= n; i++) if (!us[i]) dfs(i); if (dooc == -1) { cout << -1; return 0; } for (i = 1; i <= n; i++) { if (us[i] == 1) w[1][++z1] = i; if (us[i] == 2) w[2][++z2] = i; } cout << z1 << n ; for (i = 1; i <= z1; i++) cout << w[1][i] << ; cout << n << z2 << n ; for (i = 1; i <= z2; i++) cout << w[2][i] << ; }
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 9; vector<int> ans[N]; vector<char> arr; int k, n, q, a, hash[N][50], ar[N], s; char c; string str; bool flag; int main() { cin >> k; cin >> str; int n = str.size(); for (int i = 1; i <= k; i++) for (int j = 0; j < n; j++) arr.push_back(str[j]); for (int i = 0; i < arr.size(); i++) ans[arr[i]].push_back(i); cin >> q; for (int i = 1; i <= q; i++) { cin >> a >> c; arr[ans[c][a - 1]] = 0 ; ans[c].erase(ans[c].begin() + a - 1); } for (int i = 0; i < arr.size(); i++) if (arr[i] != 0 ) cout << arr[i]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { char c; bool nega = 0; while ((!isdigit(c = getchar())) && (c != - )) ; if (c == - ) { nega = 1; c = getchar(); } x = c - 48; while (isdigit(c = getchar())) x = x * 10 + c - 48; if (nega) x = -x; } template <typename T> inline void writep(T x) { if (x > 9) writep(x / 10); putchar(x % 10 + 48); } template <typename T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } writep(x); } template <typename T> inline void writeln(T x) { write(x); putchar( n ); } int n, h[300003], dp[300003]; set<int> st[300003]; vector<pair<int, int> > ve; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int i, j; cin >> n; for (i = 0; i < n; i++) cin >> h[i]; pair<int, int> t; ve.push_back({0, h[0]}); for (i = 1; i < n; i++) { t = ve.back(); while (h[i] <= t.second) { st[t.first].insert(i); ve.pop_back(); if (ve.empty()) break; t = ve.back(); } ve.push_back({i, h[i]}); } ve.clear(); ve.push_back({0, h[0]}); for (i = 1; i < n; i++) { t = ve.back(); while (h[i] >= t.second) { st[t.first].insert(i); ve.pop_back(); if (ve.empty()) break; t = ve.back(); } ve.push_back({i, h[i]}); } ve.clear(); ve.push_back({n - 1, h[n - 1]}); for (i = n - 2; i >= 0; i--) { t = ve.back(); while (h[i] >= t.second) { st[i].insert(t.first); ve.pop_back(); if (ve.empty()) break; t = ve.back(); } ve.push_back({i, h[i]}); } ve.clear(); ve.push_back({n - 1, h[n - 1]}); for (i = n - 2; i >= 0; i--) { t = ve.back(); while (h[i] <= t.second) { st[i].insert(t.first); ve.pop_back(); if (ve.empty()) break; t = ve.back(); } ve.push_back({i, h[i]}); } dp[n - 1] = 0; set<int>::iterator it; for (i = n - 2; i >= 0; i--) { dp[i] = 0x3f3f3f3f; for (it = st[i].begin(); it != st[i].end(); it++) { dp[i] = ((dp[i]) < (dp[*it] + 1) ? (dp[i]) : (dp[*it] + 1)); } } cout << dp[0] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t; long long x, y; int main() { cin >> t; while (t--) { cin >> x >> y; if (x == y) cout << x << endl; else if (x > y) cout << x + y << endl; else cout << y - y % x / 2 << endl; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_pad_txrx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_pad_txrx(/*AUTOARG*/
// Outputs
out,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
);
// INPUTS
input [7:0] vrefcode; // impedence control bits
input odt_enable; // ODT control
input vdd_h; // IO power
input [8:1] cbu; // Impedence Control bits for Pullup driver
input [8:1] cbd; // Impedence Control bits for Pulldn driver
input data; // Data input to Driver
input oe; // Output tristate control (active high)
// INOUTS
inout pad; // Output/Input pad of Driver/Receiver
// OUTPUTS
output out; // Receiver output
//////////////////////////
// CODE
//////////////////////////
assign pad = oe ? data : 1'bz;
assign out = pad;
// FIX FOR MAKING INPUT DQS WEAK 0/1 WHEN BUS IS IN "Z" STATE.
//wire pad_in;
//pulldown p1(pad_in); // pulldown by default if no driver
//assign out = (pad === 1'bz) ? pad_in : pad;
endmodule
|
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.1.0.96
// Netlist written on Wed May 14 14:43:33 2014
//
// Verilog Description of module Lolhi
//
module Lolhi (A, B, C, AnalogLDir, AnalogRDir, Len, Ldir, Ren,
Rdir) /* synthesis syn_module_defined=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(1[8:13])
input A; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(2[8:9])
input B; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(3[8:9])
input C; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(4[8:9])
input AnalogLDir; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(5[8:18])
input AnalogRDir; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(6[8:18])
output Len; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(7[9:12])
output Ldir; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(8[9:13])
output Ren; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(9[9:12])
output Rdir; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(10[9:13])
wire A_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(2[8:9])
wire B_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(3[8:9])
wire C_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(4[8:9])
wire AnalogLDir_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(5[8:18])
wire AnalogRDir_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(6[8:18])
wire Len_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(7[9:12])
wire Ldir_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(8[9:13])
wire Ren_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(9[9:12])
wire Rdir_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(10[9:13])
wire Z_B; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(14[7:10])
wire Len_int; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(17[7:14])
wire Ren_int; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(19[7:14])
wire GND_net, VCC_net, n63, n62;
VHI i18 (.Z(VCC_net));
GSR GSR_INST (.GSR(VCC_net));
section2_schematic lab2Logic (.n63(n63), .Z_B(Z_B), .n62(n62), .Len_int(Len_int),
.Ren_int(Ren_int)) /* synthesis syn_module_defined=1 */ ;
inverter_nick_yay_U0 invB (.B_c(B_c), .Z_B(Z_B)) /* synthesis syn_module_defined=1 */ ;
IB AnalogRDir_pad (.I(AnalogRDir), .O(AnalogRDir_c));
inverter_nick_yay invC (.C_c(C_c), .AnalogLDir_c(AnalogLDir_c), .AnalogRDir_c(AnalogRDir_c),
.Rdir_c(Rdir_c), .n62(n62)) /* synthesis syn_module_defined=1 */ ;
IB AnalogLDir_pad (.I(AnalogLDir), .O(AnalogLDir_c));
IB C_pad (.I(C), .O(C_c));
IB B_pad (.I(B), .O(B_c));
IB A_pad (.I(A), .O(A_c));
OB Rdir_pad (.I(Rdir_c), .O(Rdir));
OB Ren_pad (.I(Ren_c), .O(Ren));
OB Ldir_pad (.I(Ldir_c), .O(Ldir));
OB Len_pad (.I(Len_c), .O(Len));
inverter_nick_yay_U1 invA (.A_c(A_c), .AnalogLDir_c(AnalogLDir_c), .AnalogRDir_c(AnalogRDir_c),
.Ldir_c(Ldir_c), .n63(n63)) /* synthesis syn_module_defined=1 */ ;
LUT4 i1_2_lut_3_lut (.A(AnalogLDir_c), .B(AnalogRDir_c), .C(Len_int),
.Z(Len_c)) /* synthesis lut_function=(A (B (C))) */ ;
defparam i1_2_lut_3_lut.init = 16'h8080;
PUR PUR_INST (.PUR(VCC_net));
defparam PUR_INST.RST_PULSE = 1;
VLO i52 (.Z(GND_net));
LUT4 i1_2_lut_3_lut_adj_1 (.A(AnalogLDir_c), .B(AnalogRDir_c), .C(Ren_int),
.Z(Ren_c)) /* synthesis lut_function=(A (B (C))) */ ;
defparam i1_2_lut_3_lut_adj_1.init = 16'h8080;
endmodule
//
// Verilog Description of module section2_schematic
//
module section2_schematic (n63, Z_B, n62, Len_int, Ren_int) /* synthesis syn_module_defined=1 */ ;
input n63;
input Z_B;
input n62;
output Len_int;
output Ren_int;
wire N_1; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/lab4_smarttekbotremote/section2_schematic.v(12[6:9])
wire N_3; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/lab4_smarttekbotremote/section2_schematic.v(13[6:9])
wire Ldir_int; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(16[7:15])
wire Rdir_int; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(18[7:15])
wire N_8; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/lab4_smarttekbotremote/section2_schematic.v(11[6:9])
wire N_4; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/lab4_smarttekbotremote/section2_schematic.v(14[6:9])
AND2 I2 (.A(n63), .B(Z_B), .Z(N_1)) /* synthesis syn_instantiated=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
AND2 I3 (.A(Z_B), .B(n62), .Z(N_3)) /* synthesis syn_instantiated=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
AND3 I1 (.A(Ldir_int), .B(N_8), .C(Rdir_int), .Z(N_4)) /* synthesis syn_instantiated=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
OR2 I4 (.A(N_1), .B(N_4), .Z(Len_int)) /* synthesis syn_instantiated=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
OR2 I5 (.A(N_4), .B(N_3), .Z(Ren_int)) /* synthesis syn_instantiated=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
INV I6 (.A(n62), .Z(Rdir_int)); // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
INV I8 (.A(n63), .Z(Ldir_int)); // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
INV I7 (.A(Z_B), .Z(N_8)); // c:/lscc/diamond/3.1_x64/bin/nt64/lab4_smarttekbotremote/section4_verilog.v(29[21] 36[13])
endmodule
//
// Verilog Description of module inverter_nick_yay_U0
//
module inverter_nick_yay_U0 (B_c, Z_B) /* synthesis syn_module_defined=1 */ ;
input B_c;
output Z_B;
LUT4 i4_1_lut (.A(B_c), .Z(Z_B)) /* synthesis lut_function=(!(A)) */ ;
defparam i4_1_lut.init = 16'h5555;
endmodule
//
// Verilog Description of module inverter_nick_yay
//
module inverter_nick_yay (C_c, AnalogLDir_c, AnalogRDir_c, Rdir_c, n62) /* synthesis syn_module_defined=1 */ ;
input C_c;
input AnalogLDir_c;
input AnalogRDir_c;
output Rdir_c;
output n62;
LUT4 i1_3_lut_3_lut (.A(C_c), .B(AnalogLDir_c), .C(AnalogRDir_c),
.Z(Rdir_c)) /* synthesis lut_function=(A (C)+!A !(B+!(C))) */ ;
defparam i1_3_lut_3_lut.init = 16'hb0b0;
LUT4 i4_1_lut_rep_1 (.A(C_c), .Z(n62)) /* synthesis lut_function=(!(A)) */ ;
defparam i4_1_lut_rep_1.init = 16'h5555;
endmodule
//
// Verilog Description of module inverter_nick_yay_U1
//
module inverter_nick_yay_U1 (A_c, AnalogLDir_c, AnalogRDir_c, Ldir_c,
n63) /* synthesis syn_module_defined=1 */ ;
input A_c;
input AnalogLDir_c;
input AnalogRDir_c;
output Ldir_c;
output n63;
LUT4 i1_3_lut_3_lut (.A(A_c), .B(AnalogLDir_c), .C(AnalogRDir_c),
.Z(Ldir_c)) /* synthesis lut_function=(A (B)+!A !((C)+!B)) */ ;
defparam i1_3_lut_3_lut.init = 16'h8c8c;
LUT4 i4_1_lut_rep_2 (.A(A_c), .Z(n63)) /* synthesis lut_function=(!(A)) */ ;
defparam i4_1_lut_rep_2.init = 16'h5555;
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box.
//
|
#include <bits/stdc++.h> using namespace std; vector<long long> per, obs; long long n, k, p; bool check(long long t) { long long i = 0; for (long long j = 0; j <= obs.size() - 1; j++) { if (abs(per[i] - obs[j]) + abs(p - obs[j]) <= t) { i++; if (i == n) return 1; } } return 0; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; t = 1; for (long long test = 1; test <= t; test++) { cin >> n >> k >> p; per.resize(n); obs.resize(k); for (long long i = 0; i <= n - 1; i++) cin >> per[i]; for (long long i = 0; i <= k - 1; i++) cin >> obs[i]; sort(per.begin(), per.end()); sort(obs.begin(), obs.end()); long long ans = 1e10, st = 0, end = 1e10; while (st <= end) { long long mid = (st + end) >> 1; if (check(mid)) { ans = min(ans, mid); end = mid - 1; } else st = mid + 1; } cout << ans; } return 0; }
|
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 09:15:09 09/22/2011
// Module Name: uart_light_rx_dp
//////////////////////////////////////////////////////////////////////////////////
module uart_light_rx_dp
#(
parameter WORD_SIZE = 8,
parameter BC_SIZE = 3, //2^BC_SIZE >= WORD_SIZE
parameter SAMPLING_COUNT = 15,
parameter SC_SIZE = 4,
parameter FIFO_ADDR_BITS = 5
)(
input wire reset,
input wire clk_peri,
input wire clk_rx,
input wire rx,
//Interfaces zum SPMC
output wire [WORD_SIZE-1:0] word_rx,
//Interfaces zum Controller-Module, welche durch clk_rx getrieben werden
input wire sc_inc,
input wire sc_clr,
input wire bc_inc,
input wire bc_clr,
input wire shift,
input wire fifo_write_enable,
output wire bit_eq_0,
output wire sc_halb,
output wire sc_full,
output wire frame_done,
//Interfaces zum Controller-Module, welche durch clk_peri getrieben werden
input wire fifo_read_enable,
output wire fifo_full,
output wire fifo_empty
);
reg rx0, rx1; // zur Synchronisierung von rx mit clk_rx
reg [WORD_SIZE-1:0] shfreg_rx;
reg [BC_SIZE:0] bit_counter;
reg [SC_SIZE-1:0] sampling_counter;
assign bit_eq_0 = (rx1 == 1'b0);
assign sc_halb = (sampling_counter == ((SAMPLING_COUNT-1)/2) - 1'b1);
assign sc_full = (sampling_counter == SAMPLING_COUNT - 1'b1);
assign frame_done = (bit_counter == WORD_SIZE);
always @(posedge clk_rx, posedge reset) begin
if(reset==1'b1) begin
bit_counter <= {(BC_SIZE+1){1'b0}};
sampling_counter <= {(SC_SIZE){1'b0}};
shfreg_rx <= {(WORD_SIZE){1'b0}};
rx0 <= 1'b1;
rx1 <= 1'b1;
end
else begin
rx0 <= rx;
rx1 <= rx0;
if(sc_clr)
sampling_counter <= {(SC_SIZE){1'b0}};
else if(sc_inc)
sampling_counter <= sampling_counter + 1'b1;
if(bc_clr)
bit_counter <= {(BC_SIZE+1){1'b0}};
else if(bc_inc)
bit_counter <= bit_counter + 1'b1;
if(shift)
shfreg_rx <= {rx1,shfreg_rx[WORD_SIZE-1:1]};
end
end
yaf #
(
.DSIZE (WORD_SIZE),
.ASIZE (FIFO_ADDR_BITS)
)
yaf_rx0
(
.rdata( word_rx ), //Daten zum MC
.wfull( ), //FIFO voll mit wclk synchronisiert
.rfull( ), //FIFO voll mit rclk synchronisiert
.rwfull( fifo_full ), //FIFO voll = rfull | wfull
.wempty( ), //FIFO leer mit wclk synchronisiert
.rempty( ), //FIFO leer mit rclk synchronisiert
.rwempty( fifo_empty ), //FIFO leer = rempty & wempty
.fill( ), //Output wird nicht verwendet.
.wdata( shfreg_rx[WORD_SIZE-1:0]), //Daten vom Transceiver lesen
.winc( fifo_write_enable ), //Transceiver schreibt Daten
.wclk( clk_rx ),
.wrst_n( ~reset ),
.rinc( fifo_read_enable ), //MC liest Daten solange read=1 ist.
.rclk( clk_peri ),
.rrst_n ( ~reset ),
.rptr_upd( 1'b0 ),
.rptr_rest( 1'b0 ),
.wptr_upd( 1'b0 ),
.wptr_rest( 1'b0 )
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int Maxn = 600010, Maxm = 300005, Mo = 1000000007, sp[8][2] = {{-1, 0}, {1, 0}, {0, 1}, {0, -1}, {1, 1}, {-1, -1}, {1, -1}, {-1, 1}}; const long long oo = (1LL << 62); typedef int IArr[Maxn]; typedef long long LArr[Maxn]; typedef double DArr[Maxn]; struct SA { int fl, dep, nt[28], ct[11]; } sa[Maxn]; int total, tl, M_dep; void init() { memset((sa), 0, sizeof((sa))); fill(sa[0].nt, sa[0].nt + 27, 1); sa[0].dep = -1; total = tl = 1; } void ins(int c) { int p = tl; int np = tl = ++total; sa[np].dep = sa[p].dep + 1; for (; !sa[p].nt[c]; p = sa[p].fl) sa[p].nt[c] = np; int q = sa[p].nt[c]; if (sa[p].dep + 1 == sa[q].dep) sa[np].fl = q; else { int nq = ++total; sa[nq] = sa[q]; sa[nq].dep = sa[p].dep + 1; sa[np].fl = sa[q].fl = nq; for (; sa[p].nt[c] == q; p = sa[p].fl) sa[p].nt[c] = nq; } } int n; IArr ck; vector<int> e[Maxn]; string st, s; void dfs(int u) { for (int i = 0; i < e[u].size(); i++) { int v = e[u][i]; dfs(v); for (int j = 1; j <= n; j++) sa[u].ct[j] += sa[v].ct[j]; } } int main() { ios::sync_with_stdio(0); cin >> st; init(); for (int i = 0; i < st.size(); i++) ins(st[i] - a ); cin >> n; int l[20], r[20]; for (int i = 1; i <= n; i++) { cin >> s; cin >> l[i] >> r[i]; int p = 1; for (int j = 0; j < s.size(); j++) { int c = s[j] - a ; while (!sa[p].nt[c]) p = sa[p].fl; int q = sa[p].nt[c]; if (sa[p].dep + 1 == sa[q].dep) p = q; else { int nq = ++total; sa[nq] = sa[q]; memset((sa[nq].ct), 0, sizeof((sa[nq].ct))); sa[nq].dep = sa[p].dep + 1; sa[q].fl = nq; for (; sa[p].nt[c] == q; p = sa[p].fl) sa[p].nt[c] = nq; p = total; } sa[p].ct[i]++; } } for (int i = 2; i <= total; i++) e[sa[i].fl].push_back((i)); dfs(1); long long ans = 0; for (int i = 2; i <= total; i++) { ck[i] = 1; for (int j = 1; j <= n; j++) ck[i] &= ((l[j] <= sa[i].ct[j]) && (sa[i].ct[j] <= r[j])); if (ck[i]) ans += sa[i].dep - sa[sa[i].fl].dep; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, k; string s; int main() { cin >> n >> k >> s; int del = (n - k) / 2; stack<int> st; for (char ch : s) { if (ch == ( ) { if (del) { st.push(1); del--; } else { st.push(0); putchar( ( ); } } else { int v = st.top(); st.pop(); if (v == 0) putchar( ) ); } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module my_video_filter_mul_16ns_32ns_48_3_Mul3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[48 - 1 : 0] p;
reg [16 - 1 : 0] a_reg0;
reg [32 - 1 : 0] b_reg0;
wire [48 - 1 : 0] tmp_product;
reg [48 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module my_video_filter_mul_16ns_32ns_48_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 my_video_filter_mul_16ns_32ns_48_3_Mul3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
module mac_tb;
parameter INTERMEDIATOR_DEPTH = 1024;
parameter LOG2_INTERMEDIATOR_DEPTH = log2(INTERMEDIATOR_DEPTH - 1);
parameter MATRIX_FILENAME = "../../src/tmp/cant/cant.mtx";
reg clk, rst, wr;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row;
reg [63:0] v0, v1;
wire push_out;
wire [63:0] v_out;
reg eof;
wire stall;
reg stall_out;
mac #(INTERMEDIATOR_DEPTH) dut(clk, rst, wr, row, v0, v1, push_out, v_out, eof, stall, stall_out);
initial begin
clk = 0;
forever #5 clk = !clk;
end
reg [63:0] floats [0:10000000];
reg [63:0] row_index [0:10000000];
reg [63:0] col_index [0:10000000];
integer file;
integer bufferSize = 100;
reg [100 * 8 - 1:0] string;
integer M, N, nnz;
integer r;
integer i = 0;
integer tmp1, tmp2;
real tmp3;
initial begin
$readmemh("floats.hex", floats);
$readmemh("row.hex", row_index);
$readmemh("col.hex", col_index);
file = $fopen(MATRIX_FILENAME, "r");
r = $fgets(string, file);
r = $fscanf(file, "%d%d%d", M, N, nnz);
for(i = 0; i < nnz; i = i + 1) begin
$fscanf(file, "%d%d%f", tmp1, tmp2, tmp3);
//$display("tmp1: %d", tmp1);
row_index[i] = tmp1 - 1;
col_index[i] = tmp2 - 1;
floats[i] = $realtobits(tmp3);
end
$display("finshed reading mtx file");
end
integer stall_count = 0;
initial begin
rst = 1;
wr = 0;
row = 0;
v0 = 0;
v1 = 0;
eof = 0;
stall_out = 0;
#1000 rst = 0;
#100;
for(i = 0; i < nnz; i = i + 1) begin
while(stall) begin
stall_count = stall_count + 1;
wr = 0;
#10;
end
wr = 1;
row = row_index[i];
v0 = floats[i];
v1 = floats[col_index[i]];
//$display("pushing: row: %d, v0: %f, v0: %f", row, $bitstoreal(v0), $bitstoreal(v1));
#10;
end
wr = 0;
//eof = 1;
#10000 eof = 1;
#10 eof = 0;
end
wire multiplier_push_ieee;
wire [63:0] ieee_multiplier_out;
flopoco_to_ieee conv_after_mult(clk, dut.multiplier_push, dut.multiplier_out, multiplier_push_ieee, ieee_multiplier_out);
wire adder_push_ieee;
wire [63:0] ieee_adder_out;
flopoco_to_ieee conv_after_add(clk, dut.adder_push_out, dut.adder_out, adder_push_ieee, ieee_adder_out);
wire [63:0] before_adder_v0, before_adder_v1;
wire push_before_adder;
flopoco_to_ieee conv_before_add0(clk, dut.intermediator_push_to_adder, dut.intermediator_v0_to_adder, push_before_adder, before_adder_v0);
flopoco_to_ieee conv_before_add1(clk, dut.intermediator_push_to_adder, dut.intermediator_v1_to_adder, , before_adder_v1);
integer out_count;
initial begin
# $display("watchdog reached");
$display("out_count: %d", out_count);
$display("stall_count: %d", stall_count);
$finish;
end
initial begin
#20000 $display("endgame:");
$display("window end: %d", dut.intermediator_inst.window_end);
end
initial out_count = 0;
always @(posedge clk) begin
if(out_count == M) begin
$display("reached the end");
$display("@verilog:out_count: %d", out_count);
$display("@verilog:stall_count: %d : %d", stall_count, nnz);
$finish;
end
if(push_out) begin
//$display("push_out: %d, %f", v_out, $bitstoreal(v_out));
out_count = out_count + 1;
end
/*
if(dut.flopoco_conv_push)
$display("flopoco_conv_push");
if(dut.multiplier_push)
$display("multiplier_push: row: %d", dut.multiplier_row);
if(dut.intermediator_push_to_adder)
$display("adder push");
if(dut.adder_push_out)
$display("adder output");
if(multiplier_push_ieee)
$display("multiplier_out: %f", $bitstoreal(ieee_multiplier_out));
if(dut.adder_push_out)
$display("flopoco adder out: %H", dut.adder_out);
if(adder_push_ieee)begin
$display("adder_out: %H %f", ieee_adder_out, $bitstoreal(ieee_adder_out));
end
if(push_before_adder) begin
$display("before adder: v0: %f v1: %f", $bitstoreal(before_adder_v0), $bitstoreal(before_adder_v1));
end
*/
/*
if(dut.multiplier_push)
$display("flopoco multiplier_out: %H", dut.multiplier_out);
*/
/*
if(dut.intermediator_inst.p0_stage_0)
$display("intermediator p0_stage_0");
if(dut.intermediator_inst.p0_stage_1)
$display("intermediator p0_stage_1");
if(dut.intermediator_inst.p0_stage_2)
$display("intermediator p0_stage_2");
if(dut.intermediator_inst.p0_stage_3)
$display("intermediator p0_stage_3");
if(dut.intermediator_inst.p0_stage_5)
$display("intermediator p0_stage_5");
if(dut.intermediator_inst.p0_stage_6)
$display("intermediator p0_stage_6");
if(dut.intermediator_inst.to_adder_stage_7)
$display("intermediator to adder stage 7");
if(dut.intermediator_inst.overflow_fifo_pop_stage_5)
$display("intermediator popping overflow fifo");
*/
/*
$display("overflow_fifo_empty: %d", dut.intermediator_inst.overflow_fifo_empty);
$display("p1_stage_5: %d", dut.intermediator_inst.p1_stage_5);
$display("p1_stage_3: %d", dut.intermediator_inst.p1_stage_3);
$display("p1_stage_0: %d", dut.intermediator_inst.p1_stage_0);
*/
end
`include "common.vh"
endmodule
|
// file: Clock48MHZ_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module Clock48MHZ_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
Clock48MHZ clknetwork
(// Clock in ports
.CLK_100 (CLK_IN1),
// Clock out ports
.CLK_48 (clk_int[1]),
.CLK_OUT1 (clk_int[2]),
.CLK_OUT2 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
// Status and control signals
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
assign clk[4] = clk_int[4];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, num, m; map<long long, bool> isInsert; priority_queue<long long, vector<long long>, greater<long long> > pq; vector<string> vs; vector<long long> vi; int main() { m = 0; cin >> n; while (n--) { string s; cin >> s; if (s == insert ) { cin >> num; pq.push(num); isInsert[num] = true; vs.push_back(s); vi.push_back(num); m++; } else if (s == getMin ) { cin >> num; if (!pq.empty() && pq.top() == num) { vs.push_back(s); vi.push_back(num); m++; } else { if (!isInsert[num]) { pq.push(num); isInsert[num] = true; vs.push_back( insert ); vi.push_back(num); m++; } while (pq.top() != num) { isInsert[pq.top()] = false; vs.push_back( removeMin ); vi.push_back(-10000000000); m++; pq.pop(); } vs.push_back(s); vi.push_back(num); m++; } } else { m++; if (pq.empty()) { pq.push(2); isInsert[2] = true; vs.push_back( insert ); vi.push_back(2); m++; } isInsert[pq.top()] = false; pq.pop(); vs.push_back(s); vi.push_back(-10000000000); } } cout << m << n ; int size = vs.size(); for (int i = 0; i < size; ++i) { cout << vs[i] << ; if (vi[i] != -10000000000) cout << vi[i] << n ; else cout << n ; } return 0; }
|
/**
* processor.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "aludefs.v"
module processor(
/* inputs */
input wire clk, /* clock */
input wire res, /* reset */
input wire [15 : 0] instruction_in, /* instruction word */
input wire [ 7 : 0] mdr_in, /* memory data input */
/* outputs */
output wire [ 7 : 0] pc_out, /* program counter */
output wire [ 7 : 0] mdr_out, /* memory data output */
output wire [ 7 : 0] mar_out, /* memory address */
output wire write_mem /* memory write enable */
);
/* internal signals */
wire [15 : 0] instruction; /* instruction register output */
wire [`FWIDTH - 1 : 0] flags; /* ALU flags register */
wire [ 7 : 0] opcode, /* intruction opcode */
immediate; /* instruction immediate constant */
wire [ 1 : 0] ac_source; /* accumulator register source */
wire write_ac, /* write accumulator register */
mar_source, /* memory address register source */
write_mar; /* write memory address register */
wire [ 1 : 0] mdr_source; /* memory data register source */
wire write_mdr, /* write memory data register */
write_flags; /* write flags register */
wire [ 1 : 0] pc_source; /* program counter register source */
wire write_pc, /* write program counter register */
write_ir; /* write instruction register */
wire [ 2 : 0] ALU_op_select; /* ALU operator select */
wire [`ALUCTLW - 1 : 0] ALUctl; /* ALU control signal bus */
assign opcode = instruction[15 : 8];
assign immediate = instruction[ 7 : 0];
/* instruction register */
ff_d #(.WIDTH(16)) ir (
.D(instruction_in),
.en(write_ir),
.clk(clk),
.res(res),
.Q(instruction)
);
/* control unit */
controller_unit cr0 (
/* inputs */
.opcode(opcode),
.flags(flags),
.clk(clk),
.res(res),
/* outputs */
.ac_source(ac_source),
.write_ac(write_ac),
.mar_source(mar_source),
.write_mar(write_mar),
.mdr_source(mdr_source),
.write_mdr(write_mdr),
.write_flags(write_flags),
.pc_source(pc_source),
.write_pc(write_pc),
.write_ir(write_ir),
.write_mem(write_mem),
.ALU_op_select(ALU_op_select),
.ALUctl(ALUctl)
);
/* datapath */
datapath dp0 (
.immediate(immediate),
.mdr_in(mdr_in),
.clk(clk),
.res(res),
.ac_source(ac_source),
.write_ac(write_ac),
.mar_source(mar_source),
.write_mar(write_mar),
.mdr_source(mdr_source),
.write_mdr(write_mdr),
.write_flags(write_flags),
.pc_source(pc_source),
.write_pc(write_pc),
.ALU_op_select(ALU_op_select),
.ALUctl(ALUctl),
.mar_out(mar_out),
.mdr_out(mdr_out),
.pc_out(pc_out),
.flags(flags)
);
endmodule
`include "aluundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int n; struct vec { long long x, y, idx; } a, b; long double pos_ang_with_x_axis(vec a) { long double res = atan2(a.y, a.x) * 180 / acos(-1); if (res < 0) res += 360; return res; } int dot(vec a, vec b) { return a.x * b.x + a.y * b.y; } long double norm(vec a) { return (long double)sqrt(a.x * a.x + a.y * a.y); } long double angle(vec a, vec b) { long double ang1 = pos_ang_with_x_axis(a); long double ang2 = pos_ang_with_x_axis(b); return fabs(ang1 - ang2); } vector<vec> v; bool cmp(vec a, vec b) { vec c; c.x = c.y = 0; long double ang1 = pos_ang_with_x_axis(a); long double ang2 = pos_ang_with_x_axis(b); return ang1 < ang2; } int main() { ios::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a.x >> a.y; a.idx = i + 1; v.push_back(a); } sort(v.begin(), v.end(), cmp); int idx1, idx2; long double mn = 1e18; v.push_back(v[0]); for (int i = 1; i <= n; i++) { long double d = angle(v[i], v[i - 1]); d = min(d, (long double)360 - d); if (d < mn) mn = d, idx1 = v[i - 1].idx, idx2 = v[i].idx; } cout << idx1 << << idx2 << endl; return 0; }
|
// Filename: mersenne.v
//
// Author: Andrew Wild <>
//
// Version: 1.0
// Description: Verilog synthesizable implementation of the Mersenne Twister
// Originally developed for hardware based Monte Carlo simulator
//
`define MERSENNE_N 624 // dimensions
`define MERSENNE_M 397
`define MERSENNE_MATRIX_A 32'h9908b0df // constant vector a
`define MERSENNE_UPPER_MASK 32'h80000000 // most significant w-r bits
`define MERSENNE_LOWER_MASK 32'h7fffffff // least significant r bits
`define TEMPERING_MASK_B 32'h9d2c5680
`define TEMPERING_MASK_C 32'hefc60000
`define TEMPERING_SHIFT_U 11
`define TEMPERING_SHIFT_S 7
`define TEMPERING_SHIFT_T 15
`define TEMPERING_SHIFT_L 18
`define INITIAL_SEED 32'd8891
module mersenne8(clk, rst, ce, rnd);
input clk;
output rnd; reg [31:0] rnd;
reg [10:0] i, j, k; // three divide by N counters
input rst; wire rst;
input ce; wire ce;
reg isSeeded;
reg w1;
reg [31:0] mt1 [`MERSENNE_N:0]; /* the array for the state vector */
reg [31:0] mt2 [`MERSENNE_N:0]; /* the array for the state vector */
reg bih; // High bit of word 'i'
reg [31:0] sbihjl; // right shift of bihjl
reg [31:0] mbihjl; // MATRIX_A result from bihjl
reg [31:0] prj; // Previous read of word 'j'
reg [31:0] l1,l2;
reg [31:0] rj; // Memory read of word 'j'
reg [31:0] rk; // Memory read of work 'k'
//always@(posedge rst)
initial
begin
i <= 1;
l2 <= `INITIAL_SEED-1;
isSeeded <= 0;
end
always@(posedge clk)
begin
if (!isSeeded) begin
// seed loop runs from clock for first MERSENNE_N ticks
l1 <= l2 + 1;
#4 w1 <= l1;
//#5 mt1[i] <= l1;
//#5 mt2[i] <= l1;
#5 l2 <= l1 * 69069;
#5 i <= i+1;
#5 isSeeded = (i >= `MERSENNE_N);
#6 if(isSeeded) begin
#7 i <= 0;
#7 j <= 1;
#7 k <= `MERSENNE_M;
#8 prj <= `INITIAL_SEED;
end
end else begin
bih <= prj[31];
#1 rj <= mt1[j];
#1 rk <= mt2[k];
#2 prj <= rj;
#3 mbihjl <= rj[0] ? `MERSENNE_MATRIX_A : 0;
#3 sbihjl <= {bih, rj[30:0]}>>>1;
#3 rnd <= rk ^ sbihjl ^ mbihjl;
#4 w1 <= rnd;
//#5 mt1[i] <= rnd;
//#5 mt2[i] <= rnd;
#6 i <= i+1;
#6 j <= j+1;
#6 k <= k+1;
// conditioning
#6 rnd <= rnd ^ (rnd[31:`TEMPERING_SHIFT_U]); //(rnd >> `TEMPERING_SHIFT_U);
#7 rnd <= rnd ^ ((rnd << `TEMPERING_SHIFT_S) & `TEMPERING_MASK_B);
#8 rnd <= rnd ^ ((rnd << `TEMPERING_SHIFT_T) & `TEMPERING_MASK_C);
#9 rnd <= rnd ^ (rnd[31:`TEMPERING_SHIFT_L]); // (rnd >> `TEMPERING_SHIFT_L);
if(i==`MERSENNE_N) i <= 0;
if(j==`MERSENNE_N) j <= 0;
if(k==`MERSENNE_N) k <= 0;
end //if !seeded
#5 mt1[i] <= w1;
#5 mt2[i] <= w1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { map<int, int> m1, m2, m3; int n, m; cin >> n >> m; int a, b, c; for (int i = 0; i < m; i++) { cin >> a >> b >> c; if (m1[a] == 0 && m1[b] == 0 && m1[c] == 0) { m1[a] = 1; m1[b] = 2; m1[c] = 3; } else if (m1[a] != 0) { if (m1[a] == 1) { m1[b] = 2; m1[c] = 3; } else if (m1[a] == 2) { m1[b] = 1; m1[c] = 3; } else if (m1[a] == 3) { m1[b] = 1; m1[c] = 2; } } else if (m1[b] != 0) { if (m1[b] == 1) { m1[a] = 2; m1[c] = 3; } else if (m1[b] == 2) { m1[a] = 1; m1[c] = 3; } else if (m1[b] == 3) { m1[a] = 1; m1[c] = 2; } } else if (m1[c] != 0) { if (m1[c] == 1) { m1[a] = 2; m1[b] = 3; } else if (m1[c] == 2) { m1[a] = 1; m1[b] = 3; } else if (m1[c] == 3) { m1[a] = 1; m1[b] = 2; } } } for (int i = 1; i <= n; i++) { cout << m1[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int read() { int f = 1, x = 0; char c = getchar(); while (c < 0 || 9 < c) { if (c == - ) f = -1; c = getchar(); } while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return f * x; } const int MAXN = 100000; const int INF = 0x3f3f3f3f; int ans; void Query(int L, int R, int l1, int r1, int l2, int r2) { if (l1 > r1 || l2 > r2) return; int le = max(l1, l2), ri = min(r1, r2); ans = max(ans, ri - le + 1); if ((l1 <= l2 && r2 <= r1) || (l2 <= l1 && r1 <= r2)) return; int Mid = (L + R) >> 1; Query(L, Mid - 1, l1, min(r1, Mid - 1), l2, min(r2, Mid - 1)); Query(L, Mid - 1, l1, min(r1, Mid - 1), max(l2, Mid + 1) - Mid, r2 - Mid); Query(L, Mid - 1, max(l1, Mid + 1) - Mid, r1 - Mid, l2, min(r2, Mid - 1)); Query(L, Mid - 1, max(l1, Mid + 1) - Mid, r1 - Mid, max(l2, Mid + 1) - Mid, r2 - Mid); return; } int main() { int l1 = read(), r1 = read(), l2 = read(), r2 = read(); Query(1, 1073741823, l1, r1, l2, r2); printf( %d n , ans); return 0; }
|
module testbench
();
`include "c_constants.v"
parameter width = 4;
parameter index = 0;
parameter Tclk = 2;
wire [0:width-1] feedback;
c_fbgen
#(.width(width),
.index(index))
fbgen
(.feedback(feedback));
reg clk;
reg reset;
reg complete;
reg load;
reg run;
reg [0:width-1] d;
wire [0:width-1] lfsr_q;
c_lfsr
#(.width(width))
lfsr
(.clk(clk),
.reset(reset),
.load(load),
.run(run),
.feedback(feedback),
.complete(complete),
.d(d),
.q(lfsr_q));
wire [0:width-1] ulfsr_q;
c_lfsr
#(.width(width),
.iterations(width))
ulfsr
(.clk(clk),
.reset(reset),
.load(load),
.run(run),
.feedback(feedback),
.complete(complete),
.d(d),
.q(ulfsr_q));
always
begin
clk <= 1'b1;
#(Tclk/2);
clk <= 1'b0;
#(Tclk/2);
end
integer i;
initial
begin
reset = 1'b1;
#(Tclk);
#(Tclk/2);
reset = 1'b0;
complete = 1'b0;
load = 1'b1;
run = 1'b0;
d = {width{1'b1}};
#(Tclk);
load = 1'b0;
run = 1'b1;
d = {width{1'b0}};
$display("feedback=%x, complete=%b:", feedback, complete);
for(i = 0; i < (1 << width); i = i + 1)
begin
$display("%8d | %b (%x) | %b (%x)",
i, lfsr_q, lfsr_q, ulfsr_q, ulfsr_q);
#(Tclk);
end
complete = 1'b1;
load = 1'b1;
run = 1'b0;
d = {width{1'b1}};
#(Tclk);
load = 1'b0;
run = 1'b1;
d = {width{1'b0}};
$display("feedback=%x, complete=%b:", feedback, complete);
for(i = 0; i < ((1 << width) + 1); i = i + 1)
begin
$display("%8d | %b (%x) | %b (%x)",
i, lfsr_q, lfsr_q, ulfsr_q, ulfsr_q);
#(Tclk);
end
$finish;
end
endmodule
|
module opc2cpu( inout[7:0] data, output[9:0] address, output rnw, input clk, input reset_b);
parameter FETCH0=0, FETCH1=1, RDMEM=2, RDMEM2=3, EXEC=4 ;
parameter LDBP=4'b11_00, LDBI=4'b10_00, LDB=4'b10_01, STAP=4'b10_10;
parameter JPC =4'b01_00, JPZ=4'b01_01, STA =4'b01_10, JAL=4'b01_11;
parameter ADC =4'b00_00, NOT=4'b00_01, AND =4'b00_10, AXB=4'b00_11;
reg [9:0] PC_q, OR_q;
reg [7:0] ACC_q, B_q;
reg [2:0] FSM_q;
reg [3:0] IR_q;
reg C_q;
wire writeback_w = ((FSM_q == EXEC) && (IR_q==STA || IR_q==STAP)) & reset_b ;
assign rnw = ~writeback_w ;
assign data = (writeback_w)?ACC_q:8'bz ;
assign address = ( writeback_w || FSM_q == RDMEM || FSM_q==RDMEM2)? OR_q:PC_q;
always @ (posedge clk or negedge reset_b )
if (!reset_b)
FSM_q <= FETCH0;
else
case(FSM_q)
FETCH0 : FSM_q <= (data[7] || data[6])?FETCH1:EXEC; // 1 Byte instrs go direct to EXEC
FETCH1 : FSM_q <= (IR_q[3] && IR_q != LDBI )?RDMEM:EXEC ;
RDMEM : FSM_q <= (IR_q[2])?RDMEM2:EXEC;
RDMEM2 : FSM_q <= EXEC;
EXEC : FSM_q <= FETCH0;
endcase
always @ (posedge clk)
begin
IR_q <= (FSM_q == FETCH0)? data[7:4] : IR_q;
// Zero LSNybble of IR_q on FETCH1, used as upper nybble of operand but zero for pointer writes/reads
OR_q[9:8] <= (FSM_q == FETCH0)? data[1:0] : (FSM_q == RDMEM)? 2'b0: OR_q[9:8];
OR_q[7:0] <= data; // OR_q is dont care in FETCH0 and at end of EXEC
if ( FSM_q == EXEC )
case(IR_q)
AXB : {B_q,ACC_q} <= {ACC_q,B_q};
AND : {C_q, ACC_q} <= {1'b0, ACC_q & B_q};
NOT : ACC_q <= ~ACC_q;
ADC : {C_q,ACC_q} <= ACC_q + C_q + B_q;
JAL : {B_q,ACC_q} <= {6'b0,PC_q} ;
LDB : B_q <= OR_q[7:0];
LDBP: B_q <= OR_q[7:0];
LDBI: B_q <= OR_q[7:0];
endcase // case ( IR_q )
end
always @ (posedge clk or negedge reset_b )
if (!reset_b) // On reset start execution at 0x100 to leave page zero clear for variables
PC_q <= 10'h100;
else
if ( FSM_q == FETCH0 || FSM_q == FETCH1 )
PC_q <= PC_q + 1;
else if ( FSM_q == EXEC )
case (IR_q)
JAL : PC_q <= {B_q[1:0],ACC_q};
JPC : PC_q <= (C_q)?OR_q:PC_q;
endcase
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 02:55:00
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.sgf_result_o(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
// soft_tbm.v
`timescale 1 ns / 1 ps
module soft_tbm
(
input clk,
input sync,
input reset,
input [4:0]trg_in_tbm,
input [4:0]trg_in_ctr,
input [3:0]trg_pos,
output tin,
input tout,
output deser_ena,
output ctr,
output daq_write,
output reg [15:0]daq_data,
input [15:0]token_timeout,
input enable_tout_delay
);
wire ro_enable; // a readout can be started
wire trg_pass; // trigger sent to ROC/TBM
wire queue_read;
wire queue_clear;
wire queue_clear_token;
wire queue_empty;
wire queue_full;
wire [3:0]queue_size;
wire queue_tok;
wire [7:0]queue_trigger_counter;
wire [3:0]queue_trg_pos;
wire [5:0]queue_flags;
wire tout_int;
wire tout_missing;
wire syn; // sync event
wire trg; // trigger event
wire rsr; // ROC reset event
wire rst; // TBM reset event
wire cal; // calibrate
reg set_rsr;
wire rsr_int = rsr || set_rsr;
assign queue_clear = rst;
assign queue_clear_token = rsr_int;
assign trg_pass = trg && !queue_full;
// === tout delay for ADC ===========================================
reg [15:0]tout_delay;
always @(posedge clk or posedge reset)
begin
if (reset) tout_delay <= 0;
else if (sync) tout_delay <= {tout_delay[14:0], tout};
end
assign tout_int = enable_tout_delay ? tout_delay[15] : tout;
// === receive and decode events ====================================
assign syn = trg_in_tbm[0];
assign trg = trg_in_tbm[1];
assign rsr = trg_in_tbm[2];
assign rst = trg_in_tbm[3];
assign cal = trg_in_tbm[4];
wire trg_dir = trg_in_ctr[1];
wire rsr_dir = trg_in_ctr[2];
wire rst_dir = trg_in_ctr[3];
wire cal_dir = trg_in_ctr[4];
/* commands
* cal
send cal to ROC
set(flag_cal)
* syn
clear(trigger_counter)
set(flag_sync)
* rsr
queue_clear_token
reset ROC
set flag_resr
if (read_in_progress)
{
stop running readout
add trailer
}
* rst
queue_clear
reset ROC
set flag_resr
set flag_rest
if (read_in_progress)
{
stop running readout
}
* trg
queue_write
if (!queue_full)
{
send ROC trigger
}
else set flag_stkf
*/
// === Send Event to ROC/MODULE (CTR Generator) =====================
ctr_encoder ctr_enc
(
.clk(clk),
.sync(sync),
.reset(reset),
.cal(cal || cal_dir),
.trg(trg_pass || trg_dir),
.res_roc(rsr_int || rst || rsr_dir),
.res_tbm(rst || rst_dir),
.res_req(1'b0),
.nmr_req(1'b0),
.trg_veto(1'b0),
.res_veto(1'b0),
.running(),
.ctr_out(ctr),
.trg_out(),
.res_out()
);
// === Flags ========================================================
reg flag_rest; // TBM reset occured
reg flag_resr; // ROC reset occured
reg flag_cal; // calibrate received
reg flag_sync; // sync signal received
reg flag_stkf; // stack full
reg flag_ares; // auto reset sent
reg flag_pkam; // PKAM reset (not queued)
wire [5:0]flags = {flag_ares, flag_stkf, flag_sync, flag_cal, flag_resr, flag_rest};
always @(posedge clk or posedge reset)
begin
if (reset)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else if (sync)
begin
if (trg_pass)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else
if (cal) flag_cal <= 1;
if (syn) flag_sync <= 1;
if (rsr_int || rst) flag_resr <= 1;
if (rst) flag_rest <= 1;
if (trg && queue_full) flag_stkf <= 1;
end
end
// === Trigger Counter ==============================================
reg [7:0]trigger_counter;
always @(posedge clk or posedge reset) begin
if (reset) trigger_counter <= 0;
else if (sync) begin
if (syn) trigger_counter <= 0;
else if (trg_pass) trigger_counter <= trigger_counter + 8'd1;
end
end
// === enables start of a new readout id data in trigger stack
// first readout after buffer empty must be delayed
reg [4:0]ro_delay;
wire ro_veto = !ro_delay[4];
always @(posedge clk or posedge reset) begin
if (reset) begin
ro_delay <= 5'd0;
end
else if (sync) begin
if (trg_pass && (queue_size <= 1)) ro_delay = 5'd10;
else if (ro_veto) ro_delay = ro_delay - 5'd1;
end
end
assign ro_enable = !queue_empty && !ro_veto;
// === header/trailer generator =====================================
/*
** header format **
A | 0 | ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0
8 | 0 | 0 0 0 0 pos3 pos2 pos1 pos0
** trailer format **
E | 0 | ntok rest resr 0 sync clt cal stkf
C | 0 | ares pkam 0 0 stk3 stk2 stk1 stk0
*/
reg [16:0]token_timeout_counter;
assign tout_missing = token_timeout_counter[16];
reg [5:0]sm_readout;
localparam SM_IDLE = 6'b00_0000;
localparam SM_HDR1 = 6'b00_0010;
localparam SM_HDR2 = 6'b01_0010;
localparam SM_TOUT = 6'b00_1100;
localparam SM_WAIT = 6'b00_1000;
localparam SM_PCAM1 = 6'b01_1000;
localparam SM_PCAM2 = 6'b01_0000;
localparam SM_TRL0 = 6'b11_1000;
localparam SM_TRL1 = 6'b10_0010;
localparam SM_TRL2 = 6'b00_0011;
localparam SM_TRL3 = 6'b10_0000;
assign queue_read = sm_readout[0];
assign daq_write = sm_readout[1] && sync;
assign tin = sm_readout[2];
assign deser_ena = sm_readout[3];
// trailer delay counter
reg [2:0]trldel;
wire trl_start = trldel[2];
always @(posedge clk or posedge reset)
begin
if (reset) trldel <= 0;
else if (sync)
begin
if (~&sm_readout[5:4]) trldel <= 0;
else if (!trl_start) trldel <= trldel + 3'd1;
end
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sm_readout <= SM_IDLE;
token_timeout_counter <= 0;
set_rsr <= 0;
flag_pkam <= 0;
end
else if (sync)
begin
case (sm_readout)
SM_IDLE:
if (ro_enable) sm_readout <= SM_HDR1;
SM_HDR1:
sm_readout <= SM_HDR2;
SM_HDR2:
sm_readout <= queue_tok ? SM_TOUT : SM_TRL1;
SM_TOUT:
begin
token_timeout_counter <= {1'b0, token_timeout};
sm_readout <= SM_WAIT;
end
SM_WAIT:
begin
token_timeout_counter <= token_timeout_counter - 17'd1;
if (tout_missing) sm_readout <= SM_PCAM1;
else if (tout_int || flag_resr) sm_readout <= SM_TRL0;
end
SM_PCAM1:
begin
flag_pkam <= 1;
set_rsr <= 1;
sm_readout <= SM_PCAM2;
end
SM_PCAM2:
begin
set_rsr <= 0;
sm_readout <= SM_TRL0;
end
SM_TRL0:
if (trl_start) sm_readout <= SM_TRL1;
SM_TRL1:
sm_readout <= SM_TRL2;
SM_TRL2:
sm_readout <= SM_TRL3;
SM_TRL3:
begin
flag_pkam <= 0;
sm_readout <= SM_IDLE;
end
default: sm_readout <= SM_IDLE;
endcase
end
end
always @(*)
begin
if (sm_readout == SM_HDR1)
daq_data <= {8'ha0, queue_trigger_counter};
else if (sm_readout == SM_HDR2)
daq_data <= {8'h80, 4'b0000, queue_trg_pos};
else if (sm_readout == SM_TRL1)
daq_data <= {8'he0, ~queue_tok, queue_flags[0],
queue_flags[1], 1'b0, queue_flags[3], queue_flags[3], queue_flags[2], queue_flags[4]};
else if (sm_readout == SM_TRL2)
daq_data <= {8'hc0, queue_flags[5], flag_pkam, 2'b00, queue_size};
else daq_data <= 16'd0;
end
soft_tbm_queue #(18) stack
(
.clk(clk),
.sync(sync),
.reset(reset),
.write(trg_pass),
.read(queue_read),
.clear(queue_clear),
.clear_token(queue_clear_token),
.empty(queue_empty),
.full(queue_full),
.size(queue_size),
.din({flags, trg_pos, trigger_counter, 1'b1}),
.dout({queue_flags, queue_trg_pos, queue_trigger_counter, queue_tok})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 53e4, mod = 998244353; int n, nn, L, A, B, ans, fac[N], inv[N], a[N], b[N], c[N], R[N]; int C(int a, int b) { return 1ll * fac[a] * inv[b] % mod * inv[a - b] % mod; } int qpow(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % mod; a = 1ll * a * a % mod, b >>= 1; } return ret; } void init(int n) { nn = 1, L = 0; while (nn <= 2 * n) nn <<= 1, ++L; for (int i = 1; i < nn; ++i) R[i] = (R[i >> 1] >> 1) | ((i & 1) << L - 1); } void NTT(int* a, int tp) { for (int i = 0; i < nn; ++i) if (i < R[i]) swap(a[i], a[R[i]]); for (int i = 1; i < nn; i <<= 1) { int wn = qpow(3, tp * (mod / (i * 2)) + mod - 1); for (int j = 0; j < nn; j += i * 2) for (int k = 0, w = 1; k < i; ++k, w = 1ll * w * wn % mod) { int x = a[j + k], y = 1ll * w * a[j + k + i] % mod; a[j + k] = (x + y) % mod; a[j + k + i] = (x - y + mod) % mod; } } if (tp == 1) return; int invn = qpow(nn, mod - 2); for (int i = 0; i < nn; ++i) a[i] = 1ll * a[i] * invn % mod; } void solve(int n) { if (n == 1) { a[1] = 1; return; } if (n & 1) { solve(n - 1); for (int i = n - 1; ~i; --i) a[i + 1] = (a[i + 1] + a[i]) % mod, a[i] = 1ll * (n - 1) * a[i] % mod; return; } int l = n / 2; solve(l), init(l); for (int i = 0; i < nn; ++i) b[i] = c[i] = 0; int tmp = 1; for (int i = 0; i <= l; ++i) b[i] = 1ll * a[i] * fac[i] % mod, c[i] = 1ll * tmp * inv[i] % mod, tmp = 1ll * tmp * l % mod; reverse(b, b + l + 1); NTT(b, 1), NTT(c, 1); for (int i = 0; i < nn; ++i) b[i] = 1ll * b[i] * c[i] % mod; NTT(b, -1); reverse(b, b + l + 1); for (int i = 0; i <= l; ++i) b[i] = 1ll * inv[i] * b[i] % mod; for (int i = l + 1; i < nn; ++i) b[i] = 0; init(n); NTT(a, 1), NTT(b, 1); for (int i = 0; i < nn; ++i) a[i] = 1ll * a[i] * b[i] % mod; NTT(a, -1); } int main() { scanf( %d%d%d , &n, &A, &B); if (n == 1) { if (A == 1 && B == 1) puts( 1 ); else puts( 0 ); return 0; } if (A < 1 || B < 1 || A + B > n + 1 || A + B == 2) { puts( 0 ); return 0; } fac[0] = inv[0] = 1; for (int i = 1; i <= n; ++i) fac[i] = 1ll * fac[i - 1] * i % mod; inv[n] = qpow(fac[n], mod - 2); for (int i = n; i; --i) inv[i - 1] = 1ll * inv[i] * i % mod; solve(n - 1); ans = 1ll * a[A + B - 2] * C(A + B - 2, A - 1) % mod; printf( %d , ans); }
|
/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the ability to resolve resolve tri-state drivers onto a single
* signal. Use multiple continuous assignments to a wire to create
* multiple drivers, and use the ?: operator to tri-state the driven
* value based on the sel value.
*/
module main;
wire [1:0] out;
reg [1:0] sel = 2'bzz;
reg [1:0] v0 = 0;
reg [1:0] v1 = 1;
reg [1:0] v2 = 2;
reg [1:0] v3 = 3;
assign out = (sel == 2'b00)? v0 : 2'bz;
assign out = (sel == 2'b01)? v1 : 2'bz;
assign out = (sel == 2'b10)? v2 : 2'bz;
assign out = (sel == 2'b11)? v3 : 2'bz;
initial begin
#1 if (out !== 2'bxx) begin
$display("FAILED -- sel==%b, out==%b", sel, out);
$finish;
end
sel = 0;
#1 if (out !== 2'b00) begin
$display("FAILED -- sel==%b, out==%b, v0==%b", sel, out, v0);
$finish;
end
sel = 1;
#1 if (out !== 2'b01) begin
$display("FAILED -- sel==%b, out==%b", sel, out);
$finish;
end
sel = 2;
#1 if (out !== 2'b10) begin
$display("FAILED -- sel==%b, out==%b", sel, out);
$finish;
end
sel = 3;
#1 if (out !== 2'b11) begin
$display("FAILED -- sel==%b, out==%b", sel, out);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module transmision (input enable,
input clk_in,
input reset,
input wire [7:0] din,
output busy,
output reg done,
output reg tx);
parameter count = 8;
initial begin
tx <= 1'b1;
done=0;
end
parameter STATE_IDLE = 2'b00;
parameter STATE_START = 2'b01;
parameter STATE_DATA = 2'b10;
parameter STATE_STOP = 2'b11;
reg [8:0] data = 8'b11111111;
reg [3:0] bitpos = 0;
reg [1:0] state = STATE_IDLE;
reg [31:0] counter=0;
always @(posedge clk_in) begin
if (reset)
tx <= 1'b1;
else begin
case (state)
STATE_IDLE: begin
done<=0;
tx <= 1'b1;
if (enable)begin
state <= STATE_START;
data <= {1'h01,din};
bitpos <= 0;
end
end
STATE_START: begin
tx <= 1'b0;
state <= STATE_DATA;
end
STATE_DATA: begin
if(bitpos <= count)begin
counter <= counter +1;
if (counter==5208) begin
tx<=data[bitpos];
bitpos <= bitpos + 1;
counter<=0;
if (bitpos==count)
state<=STATE_STOP;
end
end
end
STATE_STOP: begin
tx <= 1'b1;
done<=1;
state <= STATE_IDLE;
end
default: begin
tx <= 1'b1;
state <= STATE_IDLE;
end
endcase
end
end
assign busy = (state != STATE_IDLE);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:37:19 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); if (n == 1 || n == 2) printf( 1 n ); else if (n == 3) printf( 2 n ); else { if (n % 2 == 1) printf( %d n , (n - 1) / 2 + 1); else printf( %d n , n / 2); } } return 0; }
|
#include <bits/stdc++.h> long long a[1001]; using namespace std; int main() { long long n, cnt = 0; cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 0) { cnt++; } if (n == 1) { if (a[i] == 0) { cout << NO ; return 0; } else { cout << YES ; return 0; } } } if (cnt >= 0 && cnt != 1) { cout << NO ; return 0; } else { cout << YES ; return 0; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; long long sum = 0, cyl = 0; long long k = (n / m); for (int i = 1; i <= 10; ++i) { cyl += (m * i) % 10; } sum = (k / 10) * cyl; cyl = 0; for (int i = 1; i <= k % 10; ++i) { cyl += m * (i) % 10; } cout << sum + cyl << endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:55 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/bram_1024_0_stub.v
// Design : bram_1024_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_1024_0(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void pre() {} void solve() {} int p[100]; int vis[109]; int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); pre(); int n; cin >> n; for (int i = 0; i < (n); ++i) { cin >> p[i]; vis[p[i]] = 1; } vector<pair<int, int> > v; for (int i = 0; i < (n); ++i) if (p[i]) p[i] = p[i] % 2 + 2; v.push_back(make_pair(p[0], 1)); for (int i = 1; i <= (n - 1); ++i) { if (p[i] == p[i - 1]) v.back().second++; else v.push_back(make_pair(p[i], 1)); } if ((int)(v).size() == 1) { if (p[0] == 0) { if (n == 1) cout << 0; else cout << 1; } else cout << 0; return 0; } vector<int> cnt[2]; int fns = 0; for (int i = 0; i < ((int)(v).size()); ++i) { if (v[i].first == 0) { if (i == 0) ; else if (i == (int)(v).size() - 1) ; else if (v[i - 1].first % 2 == v[i + 1].first % 2) cnt[v[i - 1].first % 2].push_back(v[i].second); else fns++; } else if (i != (int)(v).size() - 1 && v[i + 1].first != 0 && v[i].first != v[i + 1].first) { fns++; } } int val[2]; val[0] = val[1] = 0; for (int i = 1; i <= (n); ++i) if (!vis[i]) val[i % 2]++; sort(cnt[0].begin(), cnt[0].end()); sort(cnt[1].begin(), cnt[1].end()); reverse(cnt[0].begin(), cnt[0].end()); reverse(cnt[1].begin(), cnt[1].end()); int gns = n; int st[2]; st[0] = val[0], st[1] = val[1]; vector<int> gg1 = cnt[0], gg2 = cnt[1]; int cns = fns; for (int q = 0; q < (4); ++q) { val[0] = st[0]; val[1] = st[1]; cnt[0] = gg1; cnt[1] = gg2; fns = cns; if (v[(int)(v).size() - 1].first == 0) { if (q & 2) { if (val[v[(int)(v).size() - 2].first % 2] >= v[(int)(v).size() - 1].second) { val[v[(int)(v).size() - 2].first % 2] -= v[(int)(v).size() - 1].second; } else fns++; } else fns++; } if (v[0].first == 0) { if (q & 1) { if (val[v[1].first % 2] >= v[0].second) { val[v[1].first % 2] -= v[0].second; } else fns++; } else fns++; } while ((int)(cnt[1]).size() && cnt[1].back() <= val[1]) { val[1] -= cnt[1].back(); cnt[1].pop_back(); } while ((int)(cnt[0]).size() && cnt[0].back() <= val[0]) { val[0] -= cnt[0].back(); cnt[0].pop_back(); } gns = min(gns, fns + 2 * ((int)(cnt[0]).size() + (int)(cnt[1]).size())); } cout << gns; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define FAST ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #define PB(x, v) x.push_back(v); #define M_P(a, b) make_pair(a, b) #define pll pair<ll, ll> #define ll long long int #define mll map<ll, ll> #define vl vector<ll> #define fa(x, v) for(auto x: v) #define fr(i, a, b, step) for(auto i= a;i <=b; i+=step) #define TEST Int test; cin >> test; while(test--) #define FTEST Int TesT; cin >> TesT; for(Int test = 1; test<=TesT; test++) /**So..a**/ #define B_ begin() #define E_ end() #define all(a) a.begin(), a.end() #define rall(a) a.rbegin(), a.rend() #define NL_ n #define F first #define S second #define FF first.first #define FS first.second #define SF second.first #define SS second.second #include <iomanip> #define __lcm(a, b) (a/__gcd(a, b)*b) #define PI acos(-1) #define EXP 10e-6 ll prime(ll a,ll b){ ll ans=0; return ans; } int main() { ll n,m,k,i,j,sum=0,cnt=0,x; string s,ss,str,st; bool sign=1,ok=true,cheak=1; ll t,tc; ll a,b,c; ll ans=0; ok=1; sum=0; ll fac=1; cin>>t; while(t--) { cnt=0; ok=1;sign=0; int first=0; int p=0; int fst=0,scnd=0; cin>>n>>k; int mid=(n+1)/2; vector<ll>vv,v; for(i=1;i<=mid;i++){ vv.push_back(i); } for(i=mid+1;i<=n;i++){ v.push_back(i); } /* for(auto i:vv)cout<<i<< ; cout<<endl; for(auto i:v)cout<<i<< ; cout<<endl; */ if(k==0){ for(i=1;i<=n;i++)cout<<i<< ; cout<<endl; continue; } if((k+k+1) > n)cout<<-1<<endl; else { for(i=1;i<=n;i++) { if(ok){ cout<<vv[first++]<< ; ok=0; sign=1; fst++; continue; } if(sign){ ok=1; sign=0; cout<<v[p++]<< ; scnd++; cnt++; if(cnt==k)break; } } for(i=fst;i<vv.size();i++)cout<<vv[i]<< ; for(i=scnd;i<v.size();i++)cout<<v[i]<< ; cout<<endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; int main() { int a, b; cin >> a >> b; long long S = 0; for (int e = 1; e < b; e++) { long long s1 = ((long long)a * (a + 1) / 2) % INF; long long s2 = (s1 * b) % INF; s2 = (s2 + a) % INF; S = (S + ((s2 * e) % INF)) % INF; } cout << S; return 0; }
|
// part of NeoGS project (c) 2008-2013 NedoPC
// dma sequencer
/*
input interface of every DMA end-user
clocks: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
reqN _______/```````````\______________/`````````````````\______________/``````````````````
ackN ________________/``\_____________________________/``\____________________/``\__/``\__/
doneN _________________________/``\_____________________________/``\______________/``\__/``\
rnwN -------/```````````\--------------\_________________/--------------/````````\_____/```
adrwdN -------< read addr >--------------< write addr&data >--------------< rdaddr X wra X rd
rdN -------------------------<dd>-----------------------------------------------<dd>------
sequencing algorithm is round-robin with fixed initial prioritizing when multiple requests appear simultaneously while
everything was idle
*/
module dma_sequencer(
input wire clk,
input wire rst_n,
// dma requests connection
//
input wire req0,
input wire req1,
input wire req2,
input wire req3,
input wire [21:0] addr0,
input wire [21:0] addr1,
input wire [21:0] addr2,
input wire [21:0] addr3,
input wire rnw0,
input wire rnw1,
input wire rnw2,
input wire rnw3,
input wire [7:0] wd0,
input wire [7:0] wd1,
input wire [7:0] wd2,
input wire [7:0] wd3,
output wire ack0,
output wire ack1,
output wire ack2,
output wire ack3,
output wire end0,
output wire end1,
output wire end2,
output wire end3,
// dma controller connection
output wire dma_req,
output wire [21:0] dma_addr,
output wire dma_rnw,
output wire [7:0] dma_wd,
input wire dma_ack,
input wire dma_end
);
localparam DEVNUM = 4;
wire [DEVNUM-1:0] reqs;
wire [21:0] addrs [0:DEVNUM-1];
wire [DEVNUM-1:0] rnws;
wire [7:0] wds [0:DEVNUM-1];
wire [DEVNUM-1:0] acks;
wire [DEVNUM-1:0] ends;
// aggregate signals for brewity
assign reqs[DEVNUM-1:0] = {req3,req2,req1,req0};
assign addrs[0] = addr0;
assign addrs[1] = addr1;
assign addrs[2] = addr2;
assign addrs[3] = addr3;
assign rnws[DEVNUM-1:0] = {rnw3,rnw2,rnw1,rnw0};
assign wds[0] = wd0;
assign wds[1] = wd1;
assign wds[2] = wd2;
assign wds[3] = wd3;
assign {ack3,ack2,ack1,ack0} = acks[DEVNUM-1:0];
assign {end3,end2,end1,end0} = ends[DEVNUM-1:0];
reg [DEVNUM-1:0] cur_input_mux; // which current input is muxed to the DMA (input=req,ack,addr,wd)
reg [DEVNUM-1:0] cur_output_mux; // which current output is muxed to the DMA (output=end)
wire [DEVNUM-1:0] next_input_mux;
reg busy;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
busy = 1'b0;
else // posedge clk
begin
if( !busy )
busy <= |reqs;
else // busy
busy <= dma_req;
end
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
cur_input_mux = {DEVNUM{1'b0}}; // to remove static priority selection after idle -- have here 'd1!
end
else // posedge clk
begin
if( (!busy) || dma_ack ) // idle or dma acknoledges data receive
begin
cur_input_mux <= next_input_mux;
end
end
end
rr_arbiter #( .DEVNUM(DEVNUM) ) rr_arbiter(
.reqs(reqs),
.prev( cur_input_mux),
.next(next_input_mux)
);
// output mux should follow input after dma_ack
//
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
cur_output_mux = {DEVNUM{1'b0}};
end
else // posedge clk
begin
if( dma_ack )
cur_output_mux <= cur_input_mux;
end
end
// actual muxing of input data
//
wor int_dma_req; // wor is to do easily decoded AND-OR muxes
wor [20:0] int_dma_addr; //
wand int_dma_rnw; // this is WAND to have it 1 in idle
wor [7:0] int_dma_wd; //
//
genvar i;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : mux_dma_inputs
assign int_dma_req = cur_input_mux[i] & reqs[i]; // wired OR happens!
assign int_dma_addr = {21{cur_input_mux[i]}} & addrs[i]; //
assign int_dma_rnw = (~cur_input_mux[i]) | rnws[i]; // wired AND...
assign int_dma_wd = {8{cur_input_mux[i]}} & wds[i]; //
end
endgenerate
//
// output data to dma controller
//
assign dma_req = int_dma_req;
assign dma_addr = int_dma_addr;
assign dma_rnw = int_dma_rnw;
assign dma_wd = int_dma_wd;
// actual de-muxing of output data from dma controller
//
assign acks = cur_input_mux & {DEVNUM{dma_ack}};
assign ends = cur_output_mux & {DEVNUM{dma_end}};
endmodule
// round-robin arbiter
module rr_arbiter(
/*input wire [DEVNUM-1:0]*/ reqs,
/*input wire [DEVNUM-1:0]*/ prev,
/*output wire [DEVNUM-1:0]*/ next
);
parameter DEVNUM=4;
input wire [DEVNUM-1:0] reqs;
input wire [DEVNUM-1:0] prev;
output wire [DEVNUM-1:0] next;
genvar i;
// arbitration if there was previous actives
//
wire [DEVNUM-1:0] loop;
wire [DEVNUM-1:0] next_arb;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : gen_forwarders
if( i==0 )
rr_fwd forwarder( .prev(prev[i]),
.req(reqs[i]),
.next(next_arb[i]),
.loop_in(loop[DEVNUM-1]),
.loop_out(loop[i]) );
else
rr_fwd forwarder( .prev(prev[i]),
.req(reqs[i]),
.next(next_arb[i]),
.loop_in(loop[i-1]),
.loop_out(loop[i]) );
end
endgenerate
// arbitration if there was no actives prior to requests
//
wire [DEVNUM-1:0] next_empty;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : pri_enc
if( i==0 )
begin : pri_zero
assign next_empty[0] = reqs[0];
end
else
begin : pri_nonzero
assign next_empty[i] = reqs[i] & ( ~|reqs[i-1:0] );
end
end
endgenerate
// select between prev-busy and prev-free cases
assign next = ( prev ) ? next_arb : next_empty;
endmodule
// round-robin request forwarder (1 bit)
module rr_fwd(
input wire prev, // who was arbitrated last time (one-hot)
input wire req, // who are requesting
output reg next, // who will be next
input wire loop_in, // for internal arbitration
output reg loop_out //
);
always @*
begin
if( prev )
begin
loop_out = 1'b1;
end
else //!prev
begin
loop_out = req ? 1'b0 : loop_in;
end
end
always @*
begin
next = req ? loop_in : 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$PKG$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; constexpr long long MOD = 1e9 + 7; struct { int val, lazy; } tree[4 * 1000010]; int bal(int p) { return tree[p].val + tree[p].lazy; } void ins(int S, int val, int L = 1, int R = 1000000, int p = 1) { if (S < L || R < 1) return; if (1 <= L && R <= S) { tree[p].lazy += val; return; } tree[2 * p].lazy += tree[p].lazy; tree[2 * p + 1].lazy += tree[p].lazy; tree[p].lazy = 0; int M = (L + R) / 2; ins(S, val, L, M, 2 * p); ins(S, val, M + 1, R, 2 * p + 1); tree[p].val = max(bal(2 * p), bal(2 * p + 1)); } int query(int L = 1, int R = 1000000, int p = 1) { if (L == R) { return bal(p) > 0 ? L : -1; } int M = (L + R) / 2; tree[2 * p].lazy += tree[p].lazy; tree[2 * p + 1].lazy += tree[p].lazy; tree[p].val += tree[p].lazy; tree[p].lazy = 0; if (bal(2 * p + 1) > 0) return query(M + 1, R, 2 * p + 1); return query(L, M, 2 * p); } int main() { int n, m; scanf( %d%d , &n, &m); vector<int> a[2]; for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); a[0].push_back(x); ins(x, 1); } for (int i = 0; i < m; ++i) { int x; scanf( %d , &x); a[1].push_back(x); ins(x, -1); } int q; scanf( %d , &q); while (q--) { int idx, i, x; scanf( %d%d%d , &idx, &i, &x); --i; --idx; if (idx == 0) { ins(a[idx][i], -1); ins(x, 1); } else { ins(a[idx][i], 1); ins(x, -1); } a[idx][i] = x; printf( %d n , query()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; constexpr static int MAXN = 1e6; int main() { int k, a, b; cin >> k >> a >> b; if (a > b) swap(a, b); int x = a / k; int y = b / k; if (x == 0 && y == 0) { cout << -1 << endl; return 0; } if (x == 0 && b % k > 0) { cout << -1 << endl; return 0; } cout << x + y << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int M = 55; const int K = 200010; const int LIT = 2500; const int INF = 1 << 30; const int dir[6][2] = {{2, 0}, {-2, 0}, {1, 1}, {-1, 1}, {1, -1}, {-1, -1}}; bool check(long long x, long long y, long long n) { long long dist = x * x + 3 * y * y; long long cmp = 4 * n * n; return dist <= cmp; } bool inside(long long x, long long y, long long n) { for (int j = 0; j < 6; j++) { long long xx = x + dir[j][0]; long long yy = y + dir[j][1]; if (!check(xx, yy, n)) return 0; } return 1; } void solve(int n) { long long x = 0, y = 0; long long res = 1; while (1) { y += 2; if (!inside(x, y, n)) break; res += 2; } while (y >= 0) { x += 3, y++; while (y >= 0) { if (inside(x, y, n)) { res += (y + 1) * 2; break; } y -= 2; } } cout << res << endl; } int main() { int n; while (cin >> n) { solve(n); } }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/KEEPER.v,v 1.5 2007/05/23 21:43:39 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Weak Keeper
// /___/ /\ Filename : KEEPER.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module KEEPER (O);
inout O;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
reg in;
always @(O)
if (O)
in <= 1;
else
in <= 0;
buf (pull1, pull0) B1 (O, in);
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; string vow = aeiou ; long long month[] = {-1, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; const long long dxhorse[] = {-2, -2, -1, -1, 1, 1, 2, 2}; const long long dyhorse[] = {1, -1, 2, -2, 2, -2, 1, -1}; const long long dx4[] = {-1, 0, 1, 0}; const long long dy4[] = {0, 1, 0, -1}; const long long dx8[] = {-1, -1, -1, 0, 0, 1, 1, 1}; const long long dy8[] = {-1, 0, 1, -1, 1, -1, 0, 1}; const long double pie = 3.1415926535897932384626; const long long special_prime = 982451653l; const long long mod = 1e9 + 7; const long long inf = 2e18; template <class T> istream &operator>>(istream &in, vector<T> &a) { for (auto &i : a) cin >> i; return in; } template <class T> ostream &operator<<(ostream &out, const vector<T> &a) { for (auto &i : a) cout << i << ; return out; } template <class T, class U> ostream &operator<<(ostream &out, const map<T, U> &a) { for (auto &i : a) cout << ( << i.first << , << i.second << ) n ; return out; } template <class T, class U> ostream &operator<<(ostream &out, const unordered_map<T, U> &a) { for (auto &i : a) cout << ( << i.first << , << i.second << ) n ; return out; } long long GCD(long long a, long long b) { if (!b) return a; return GCD(b, a % b); } long long LCM(long long a, long long b) { return (a * b) / GCD(a, b); } bool comp(long long a, long long b) { return a > b; } void sieve(vector<long long> &prime) { prime[0] = false; prime[1] = false; for (long long p = 2; p * p <= 99999; p++) { if (prime[p] == true) { for (long long i = p * p; i <= 99999; i += p) prime[i] = false; } } } void solve() { long long n, g, b; cin >> n >> g >> b; long long d = n / 2 + n % 2; if (d % g) cout << max(n, (d / g) * (g + b) + d % g) << n ; else cout << max((d / g) * (g + b) - b, n) << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; cout << setprecision(15) << fixed; for (long long i = 1; i <= t; i++) solve(); }
|
// Copyright (c) 2013-2015, Intel Corporation
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
module spl_pt_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
// port 0, read/write
input wire we0,
input wire re0,
input wire [ADDR_WIDTH-1:0] addr0,
input wire [DATA_WIDTH-1:0] din0,
output reg [DATA_WIDTH-1:0] dout0,
// port 1, read only
input wire re1,
input wire [ADDR_WIDTH-1:0] addr1,
output reg [DATA_WIDTH-1:0] dout1
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "AUTO, no_rw_check" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we0)
mem[addr0] <= din0;
if (re0)
dout0 <= mem[addr0];
if (re1)
dout1 <= mem[addr1];
end
endmodule
|
/*****************************************************************************
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
-------------------------------------------------------------------------------
-- Entity: mig_interface_model
-- File: mig_interface_model.v
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a interface model for Xilinx Virtex-7 MIG used on eval board
-- VC707 and KC705.
--
-------------------------------------------------------------------------------
*****************************************************************************/
`timescale 1ps/1ps
module mig_interface_model
(
// user interface signals
input [27:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output wire [511:0] app_rd_data,
output wire app_rd_data_end,
output wire app_rd_data_valid,
output wire app_rdy,
output wire app_wdf_rdy,
output reg ui_clk,
output reg ui_clk_sync_rst,
output reg init_calib_complete,
input sys_rst
);
parameter AddressSize = 28 - 12;
parameter WordSize = 512;
parameter MEM_SIZE = (1<<AddressSize);
reg app_rd_data_end_r;
reg app_rd_data_valid_r;
reg app_rdy_r;
reg app_wdf_rdy_r;
reg app_en_r;
reg app_wdf_wren_r;
reg app_wdf_end_r;
reg [27:0] app_addr_r;
reg [27:0] app_addr_r1;
reg [27:0] app_addr_r2;
reg [511:0] mask;
reg [WordSize-1:0] Mem [0:MEM_SIZE];
integer k;
wire [511:0] app_rd_data_hi_data;
wire [511:0] app_rd_data_hi;
wire [511:0] app_rd_data_lo;
wire test;
assign #100 app_rd_data_end = app_rd_data_end_r;
assign #100 app_rdy = app_rdy_r;
assign #100 app_wdf_rdy = app_wdf_rdy_r;
assign app_rd_data_valid = app_rd_data_valid_r;
// assign app_rd_data_lo = Mem[(app_addr_r >> 4) + 0];
// assign app_rd_data_hi = Mem[(app_addr_r >> 4) + 1];
// assign app_rd_data_hi_data = {app_rd_data_hi[255:0],app_rd_data_lo[511:256]};
// assign test = app_addr_r[3];
// assign #100 app_rd_data = test ? app_rd_data_hi_data : app_rd_data_lo;
assign #100 app_rd_data = Mem[app_addr_r >> 3];
// Clear memory
initial
begin
for (k = 0; k < MEM_SIZE ; k = k + 1)
begin
Mem[k] = 512'd0;
end
end
initial
begin
app_rd_data_valid_r = 1'b0;
app_rd_data_end_r = 1'b0;
app_rdy_r = 1'b1;
app_wdf_rdy_r = 1'b1;
init_calib_complete = 1'b0;
ui_clk_sync_rst = 1'b0;
ui_clk = 1'b0;
end
// Generate clocks
always
begin
forever begin
#5000;
ui_clk = ~ui_clk;
end
end
// Release reset and calibration
initial
begin
#10000;
$display("Reset release of simulation time is %d",$time);
@(posedge ui_clk) ui_clk_sync_rst = 1'b1;
#1000;
$display("Calibration release of simulation time is %d",$time);
@(posedge ui_clk) init_calib_complete = 1'b1;
end
// Write Process
always@(posedge app_wdf_wren)
begin
#100;
for (k = 0; k < 511 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
end
// Read Process
always@(posedge app_en)
begin
#100;
if (app_cmd == 3'd1) begin
app_addr_r1 = app_addr;
#10000;
app_addr_r2 = app_addr;
#40000;
app_addr_r = app_addr_r1;
#100;
app_rd_data_valid_r = 1'b1;
#10000;
app_addr_r = app_addr_r2;
#10000;
app_rd_data_valid_r = 1'b0;
#10000;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const int inf = (1 << 30) - 1; const long long inf64 = ((long long)1 << 62) - 1; const long double pi = 3.1415926535897932384626433832795; template <class T> T sqr(T x) { return x * x; } template <class T> T abs(T x) { return x < 0 ? -x : x; } const int MAXN = 310000; int a[MAXN], ind[MAXN], ind_cut[MAXN]; long long sum[MAXN]; bool comp(int ind1, int ind2) { return ((a[ind1] < a[ind2]) || (a[ind1] == a[ind2] && ind1 < ind2)); } int main() { int n; cin >> n; sum[0] = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); sum[i + 1] = (a[i] > 0 ? sum[i] + a[i] : sum[i]); ind[i] = i; } sort(ind, ind + n, comp); int i = 0; int ind_l, ind_r; long long max_sum = -2 * inf; ind[n] = n; a[n] = inf; while (i < n) { int j = i; while (a[ind[j + 1]] == a[ind[i]]) j++; long long temp = sum[ind[j]] - sum[ind[i] + 1] + 2 * a[ind[i]]; if (j > i && temp > max_sum) { max_sum = temp; ind_l = ind[i]; ind_r = ind[j]; } i = j + 1; } int num = 0; for (int i = 0; i < ind_l; ++i) { ind_cut[num] = i + 1; num++; } for (int i = ind_l + 1; i < ind_r; ++i) { if (a[i] < 0) { ind_cut[num] = i + 1; num++; } } for (int i = ind_r + 1; i < n; ++i) { ind_cut[num] = i + 1; num++; } cout << max_sum << << num << endl; for (int i = 0; i < num; ++i) { cout << ind_cut[i] << ; } cout << endl; return 0; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.