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#include <bits/stdc++.h> using namespace std; const int INF = 1000000001; const long double EPS = 1e-9; const int MOD = 1000000007; const long long LLINF = 1000000000000000001; const int maxn = 350000; int n, k; int result[maxn]; int cost[maxn]; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> cost[i]; set<pair<int, int>, greater<pair<int, int> > > s; for (int i = 1; i <= k; i++) s.insert(make_pair(cost[i], i)); for (int i = k + 1; i <= n; i++) { s.insert(make_pair(cost[i], i)); result[s.begin()->second] = i; s.erase(s.begin()); } for (int i = n + 1; i <= n + k; i++) { result[s.begin()->second] = i; s.erase(s.begin()); } long long sumCost = 0; for (int i = 1; i <= n; i++) sumCost += (long long)(result[i] - i) * cost[i]; cout << sumCost << n ; for (int i = 1; i <= n; i++) cout << result[i] << ; cout << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a > b) swap(a, b); if (a == 0) return b; return gcd(b % a, a); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t, i; cin >> t; while (t--) { long long n; cin >> n; long long arr[n]; for (i = 0; i < n; i++) { cin >> arr[i]; } long long sum = 0; for (i = 0; i < n; i++) { if (i % 2 && arr[i] > 0) arr[i] *= -1; else if (i % 2 == 0 && arr[i] < 0) arr[i] *= -1; } for (i = 0; i < n; i++) { cout << arr[i] << ; } cout << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:14 08/24/2011
// Design Name:
// Module Name: q15_mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmult #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
output [N-1:0] o_result,
output reg ovr
);
// The underlying assumption, here, is that both fixed-point values are of the same length (N,Q)
// Because of this, the results will be of length N+N = 2N bits....
// This also simplifies the hand-back of results, as the binimal point
// will always be in the same location...
reg [2*N-1:0] r_result; // Multiplication by 2 values of N bits requires a
// register that is N+N = 2N deep...
reg [N-1:0] r_RetVal;
//--------------------------------------------------------------------------------
assign o_result = r_RetVal; // Only handing back the same number of bits as we received...
// with fixed point in same location...
//---------------------------------------------------------------------------------
always @(i_multiplicand, i_multiplier) begin // Do the multiply any time the inputs change
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; // Removing the sign bits from the multiply - that
// would introduce *big* errors
end
// This always block will throw a warning, as it uses a & b, but only acts on changes in result...
always @(r_result) begin // Any time the result changes, we need to recompute the sign bit,
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // which is the XOR of the input sign bits... (you do the truth table...)
r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; // And we also need to push the proper N bits of result up to
// the calling entity...
if (r_result[2*N-2:N-1+Q] > 0) // And finally, we need to check for an overflow
ovr <= 1'b1;
else
ovr <= 1'b0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
module some_module (
input [3:0] i_clks
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge i_clks[3]) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (i_clks[3])
some_other_state <= 0;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
.i_clks (i_clks)
);
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
/*AUTOARG*/
// Inputs
clk /*verilator clocker*/,
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
input clk;
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk),
.i_clk2 (clk2),
.i_data (data_in)
);
// initial begin
// $write("*-* All Finished *-*\n");
// $finish;
// end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> v(n); for (auto &x : v) { scanf( %d , &x); } sort(v.begin(), v.end()); int pos = 0, cnt = 0; for (int x : v) { while (pos < n) { if (v[pos] > x) { pos++; cnt++; break; } pos++; } } printf( %d n , cnt); return 1 == 0; }
|
#include <bits/stdc++.h> using namespace std; bool checktwo(long long int n){if(n==0){return false;}else{return (ceil(log2(n)) == floor(log2(n)));}} long long int powerof2lte(long long int n){int p = (long long int)log2(n);return (long long int)pow(2, p);} long long int numdigits(long long int n){return floor(log10(n)) + 1; } int main() { long long int n; cin>>n; cout<<2 - (n*n)<< n ; }
|
#include <bits/stdc++.h> const int INF_INT = 0x3f3f3f3f; const long long INF_LL = 0x7f7f7f7f; const int MOD = 1e9 + 7; const double eps = 1e-10; const double pi = acos(-1); using namespace std; const int N = 200200; int n, m, q; int u[N], v[N]; struct Query { int l, r, s, t, id; Query(int l, int r, int s, int t, int id) : l(l), r(r), s(s), t(t), id(id) {} Query() {} bool operator<(const Query& rhs) const { return l > rhs.l; } }; vector<Query> qs; int dp[1010][1010]; int ans[N]; int main(int argc, char const* argv[]) { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) scanf( %d%d , &u[i], &v[i]); for (int i = 1; i <= q; i++) { int l, r, s, t; scanf( %d%d , &l, &r); scanf( %d%d , &s, &t); qs.emplace_back(l, r, s, t, i); } sort(qs.begin(), qs.end()); memset((dp), (INF_INT), sizeof(dp)); for (int i = 1; i <= n; i++) dp[i][i] = 0; int cnt = 0; for (int i = m; i >= 1; i--) { dp[u[i]][v[i]] = dp[v[i]][u[i]] = i; for (int j = 1; j <= n; j++) { if (j != u[i]) dp[v[i]][j] = min(dp[v[i]][j], dp[u[i]][j]); if (j != v[i]) dp[u[i]][j] = min(dp[u[i]][j], dp[v[i]][j]); } while (cnt < qs.size() && qs[cnt].l >= i) { ans[qs[cnt].id] = dp[qs[cnt].s][qs[cnt].t] <= qs[cnt].r; cnt++; } } for (int i = 1; i <= q; i++) puts(ans[i] ? Yes : No ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_TB_V
`define SKY130_FD_SC_LP__A311O_TB_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A2BB2OI_PP_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, a, b; cin >> n >> m >> a >> b; long long cost = 0; if (m > n) m = n; if (m * a <= b) cost = n * a; else { cost = (n / m) * b; n = n % m; if (n > 0) { if ((n)*a <= b) cost += n * a; else cost += b; } } cout << cost; return 0; }
|
module conware #(
parameter DWIDTH = 32,
parameter WIDTH = 4,
parameter HEIGHT = 1
)(
clk,
rstn,
// Color conversion signals
alive_color,
dead_color,
// Input AXI stream ports
S_AXIS_TVALID,
S_AXIS_TREADY,
S_AXIS_TDATA,
S_AXIS_TLAST,
// Output AXI stream ports
M_AXIS_TVALID,
M_AXIS_TREADY,
M_AXIS_TDATA,
M_AXIS_TLAST
);
input clk;
input rstn;
input [DWIDTH-1:0] alive_color;
input [DWIDTH-1:0] dead_color;
input [DWIDTH-1:0] S_AXIS_TDATA;
input S_AXIS_TVALID;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output [DWIDTH-1:0] M_AXIS_TDATA;
output M_AXIS_TVALID;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
wire [WIDTH*HEIGHT-1:0] in_states;
wire [WIDTH*HEIGHT-1:0] out_states;
// Signals to handle internal handshake between in-buffer and out-buffer
wire pvalid;
wire pready;
axis2buffer #(DWIDTH, WIDTH, HEIGHT) a2b(
.clk(clk),
.rstn(rstn),
.alive_color(alive_color),
.dead_color(dead_color),
.S_AXIS_TVALID(S_AXIS_TVALID),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TLAST(S_AXIS_TLAST),
.out_data(in_states),
.out_valid(pvalid),
.out_ready(pready)
);
shredder_array #(WIDTH) shredders(
.in_data(in_states),
.out_data(out_states)
);
buffer2axis #(DWIDTH, WIDTH, HEIGHT) b2a(
.clk(clk),
.rstn(rstn),
.alive_color(alive_color),
.dead_color(dead_color),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(M_AXIS_TLAST),
.in_data(out_states),
.in_valid(pvalid),
.in_ready(pready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; class strocks { public: string strocksguy() {} }; int main() { strocks strocks; iostream::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; string s, d; unordered_map<string, string> master; for (long long i = 0; i < m; i++) { cin >> s >> d; if (s.size() > d.size()) { master.insert(make_pair(s, d)); } else master.insert(make_pair(d, s)); } for (long long i = 0; i < n; i++) { cin >> s; if (master.find(s) != master.end()) cout << master.at(s) << ; else cout << s << ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; void printVector(vector<string> &v) { for (auto x : v) cout << x << n ; } void printVector(vector<int> &v) { for (auto x : v) cout << x << ; cout << n ; } int main() { cin.tie(0); cout.tie(0); ios::sync_with_stdio(0); int t; t = 1; while (t--) { int n, k, x; cin >> n >> k >> x; vector<int> freq(1024, 0); vector<int> upd(1024, 0); vector<int> calc(1024); for (int i = 0; i < 1024; i++) { calc[i] = i xor x; } for (int i = 0; i < n; i++) { int a; cin >> a; freq[a]++; } for (int i = 0; i < k; i++) { int sum = 0; for (int j = 0; j < 1024; j++) { int s = freq[j]; if (sum % 2 == 0) s++; s /= 2; upd[calc[j]] += s; sum += freq[j]; freq[j] -= s; } for (int j = 0; j < 1024; j++) { freq[j] += upd[j]; upd[j] = 0; } } int mn, mx; for (int j = 0; j < 1024; j++) { if (freq[j] > 0) { mn = j; break; } } for (int j = 1023; j >= 0; j--) { if (freq[j] > 0) { mx = j; break; } } cout << mx << << mn << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_BLACKBOX_V
/**
* udp_dff$PS_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PG (
Q ,
D ,
CLK ,
SET ,
VPWR,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_BLACKBOX_V
|
module DRAMReader(
//AXI port
input wire ACLK,
input wire ARESETN,
output reg [31:0] M_AXI_ARADDR,
input wire M_AXI_ARREADY,
output wire M_AXI_ARVALID,
input wire [63:0] M_AXI_RDATA,
output wire M_AXI_RREADY,
input wire [1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
input wire M_AXI_RLAST,
output wire [3:0] M_AXI_ARLEN,
output wire [1:0] M_AXI_ARSIZE,
output wire [1:0] M_AXI_ARBURST,
//Control config
input wire CONFIG_VALID,
output wire CONFIG_READY,
input wire [31:0] CONFIG_START_ADDR,
input wire [31:0] CONFIG_NBYTES,
//RAM port
input wire DATA_READY_DOWNSTREAM,
output wire DATA_VALID,
output wire [63:0] DATA
);
assign M_AXI_ARLEN = 4'b1111;
assign M_AXI_ARSIZE = 2'b11;
assign M_AXI_ARBURST = 2'b01;
parameter IDLE = 0, RWAIT = 1;
//ADDR logic
reg [31:0] a_count;
reg a_state;
assign M_AXI_ARVALID = (a_state == RWAIT);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
a_state <= IDLE;
M_AXI_ARADDR <= 0;
a_count <= 0;
end else case(a_state)
IDLE: begin
if(CONFIG_VALID) begin
M_AXI_ARADDR <= CONFIG_START_ADDR;
a_count <= CONFIG_NBYTES[31:7];
a_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_ARREADY == 1) begin
if(a_count - 1 == 0)
a_state <= IDLE;
a_count <= a_count - 1;
M_AXI_ARADDR <= M_AXI_ARADDR + 128; // Bursts are 128 bytes long
end
end
endcase
end
//READ logic
reg [31:0] b_count;
reg r_state;
assign M_AXI_RREADY = (r_state == RWAIT) && DATA_READY_DOWNSTREAM;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
r_state <= IDLE;
b_count <= 0;
end else case(r_state)
IDLE: begin
if(CONFIG_VALID) begin
b_count <= {CONFIG_NBYTES[31:7],7'b0}; // round to nearest 128 bytes
r_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_RVALID && DATA_READY_DOWNSTREAM) begin
//use M_AXI_RDATA
if(b_count - 8 == 0)
r_state <= IDLE;
b_count <= b_count - 8; // each valid cycle the bus provides 8 bytes
end
end
endcase
end
assign DATA = M_AXI_RDATA;
assign DATA_VALID = M_AXI_RVALID && (r_state == RWAIT);
assign CONFIG_READY = (r_state == IDLE) && (a_state == IDLE);
endmodule // DRAMReader
|
`timescale 1ns/100ps
module Combiner(
input clk,
input signed [15:0] din,
//input mode,
input integ,
input bypass,
//input [9:0] gateEnd,
//(* equivalent_register_removal = "no" *) output reg signed [15:0] dout = 16'h0000
output signed [15:0] dout
);
`include "bits_to_fit.v"
//parameter real CLK_FREQ = 192e6; // SiS digitisers - 192 MHz
parameter real CLK_FREQ = 357e6; // FONT5A board - 357 MHz
parameter real SUB_PULSE_LENGTH = 280e-9; // Factor 4 - 280 ns sub-pulse length
//localparam integer COMB_FACT = 4; // Factor 4 combination
localparam integer SUB_PULSE_CNT_SIZE = bits_to_fit(CLK_FREQ * SUB_PULSE_LENGTH);
//localparam SUB_PULSE_CNT_SIZE = $clog2(CLK_FREQ * SUB_PULSE_LENGTH + 1); //NB: Icarus verilog understand the clog2 system CUF but not user functions!!!
//localparam [SUB_PULSE_CNT_SIZE-1:0] SUB_PULSE_CNT = CLK_FREQ * SUB_PULSE_LENGTH;
//reg [SUB_PULSE_CNT_SIZE-1:0] subPulseCtr = {SUB_PULSE_CNT_SIZE{1'b0}};
//parameter SRL_SIZE = 64;
localparam [SUB_PULSE_CNT_SIZE-1:0] SRL_SIZE = (CLK_FREQ * SUB_PULSE_LENGTH);
reg signed [17:0] dsh [0:SRL_SIZE-1]; // 18-bits necessary for Factor 4 combination //
integer i, n;
initial for (i=0; i < SRL_SIZE; i=i+1) dsh[i] = 18'h00000;
//MUXY for uncombined beam
wire signed [17:0] din_mux = (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1];
always @(posedge clk) begin
/* if (intergrating) begin //ACC/CLR !!
dsh[0] <= din + dsh[SRL_SIZE-1];
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1];
end else begin
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= 20'h0; // not synthesisible, must shift-in the zero
dout <= dsh[SRL_SIZE-1]; */
//Begin combiner unit
/*
dout <= (bypass) ? din : dsh[SRL_SIZE-1];
dsh[0] <= (integ) ? din + dsh[SRL_SIZE-1] : 20'h0; //control (integ) must be set to correct sample range
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; */
//End combiner
//NO THIS iS WRONG, output needs to be din + dsh
//dout <= (bypass) ? din : din + dsh[SRL_SIZE-1];
dsh[0] <= (integ) ? din_mux : 18'h00000; // MUXY to clear SR when not interleaving
//dsh[0] <= (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1]; //MUXY for uncombined beam
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; // Implement Shift Rgegister
//dout <= dsh[0][17:2]; // Bit-select top 16 bits and present on output
end
assign dout = dsh[1][17:2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { list<unsigned long long int> blind; list<unsigned long long int>::iterator bite, tempite; unsigned long long int total, l, maxarea = 0, sum, i; cin >> total >> l; for (i = 0; i < total; ++i) { cin >> sum; if (sum >= l) blind.push_back(sum); } sum = 1; while (sum != 0) { sum = 0; for (bite = blind.begin(); bite != blind.end();) { if (*bite < l) { tempite = bite; ++bite; blind.erase(tempite); } else { sum += *bite / l; ++bite; } } if (maxarea < l * sum) maxarea = l * sum; ++l; } cout << maxarea; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename X, typename Y> static inline void xmin(X &x, Y y) { if (y < x) x = y; } template <typename X, typename Y> static inline void xmax(X &x, Y y) { if (x < y) x = y; } long long pw(long long x, long long y, long long md) { if (!y) return 1; if (y & 1) return (x * pw(x, y - 1, md)) % md; long long tmp = pw(x, y / 2, md); return (tmp * tmp) % md; } int n, a[200001], sm[200001], seg[524288]; void ins(int x, int v, int s = 1, int e = n, int i = 1) { seg[i] += v; int md = (s + e) / 2; if (s == e) return; if (x > md) ins(x, v, md + 1, e, 2 * i + 1); else ins(x, v, s, md, 2 * i); } int que(int x, int s = 1, int e = n, int i = 1) { if (s > x) return 0; if (e <= x) return seg[i]; int md = (s + e) / 2; return que(x, s, md, 2 * i) + que(x, md + 1, e, 2 * i + 1); } int elt(int x, int s = 1, int e = n, int i = 1) { if (s == e) return s; int md = (s + e) / 2; return seg[2 * i] >= x ? elt(x, s, md, 2 * i) : elt(x - seg[2 * i], md + 1, e, 2 * i + 1); } void solve() { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i], ins(a[i] + 1, 1); for (int i = 1; i <= n; ++i) ins(a[i] + 1, -1), sm[i] = que(a[i] + 1); for (int i = 1; i <= n; ++i) cin >> a[i], ins(a[i] + 1, 1); for (int i = 1; i <= n; ++i) ins(a[i] + 1, -1), sm[i] += que(a[i] + 1); for (int i = n; i >= 1; --i) if (sm[i] > n - i) sm[i] -= n - i + 1, ++sm[i - 1]; for (int i = 1; i <= n; ++i) ins(i, 1); for (int i = 1; i <= n; ++i) { sm[i] = elt(sm[i] + 1); ins(sm[i], -1); } for (int i = 1; i <= n; ++i) cout << sm[i] - 1 << ; } signed main() { ios::sync_with_stdio(0); cin.tie(0); int TESTS = 1; while (TESTS--) solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O41AI_BEHAVIORAL_PP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long long int INF = 3e16; const int N = 200010; int n; int ask(vector<int> v) { printf( ? ); for (int i = 0; i < n; i++) printf( %d , v[i]); printf( n ); fflush(stdout); int ans; scanf( %d , &ans); return ans; } int main() { scanf( %d , &n); int pivo = -1; for (int i = 1; i < n; i++) { vector<int> tmp(n); tmp[n - 1] = 1; for (int j = 0; j < n - 1; j++) { tmp[j] = 1 + i; } int k = ask(tmp); if (k == 0) { pivo = i; break; } } if (pivo == -1) pivo = n; vector<int> ans(n + 1); ans[n] = pivo; for (int i = 1; i <= n; i++) { if (i == pivo) continue; vector<int> tmp(n); tmp[n - 1] = (n + 1) - pivo; for (int j = 0; j < n - 1; j++) { tmp[j] = (n + 1) - i; } int k = ask(tmp); ans[k] = i; } printf( ! ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); fflush(stdout); return 0; }
|
/************************************************************************
dataGeneration.v
Data generation module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email:
************************************************************************/
module dataGenerator (
input nReset,
input clock,
input [9:0] adc_databus,
input testModeFlag,
// Outputs
output [9:0] dataOut
);
// Register to store test and ADC data values
reg [9:0] adcData;
reg [9:0] testData;
wire [9:0] adc_databusRead;
// If we are in test-mode use test data,
// otherwise use the actual ADC data
assign dataOut = testModeFlag ? testData : adcData;
// Read the ADC data and generate the test data on the
// negative edge of the clock
//
// Note: The test data is a repeating pattern of incrementing
// values from 0 to 1023.
always @ (posedge clock, negedge nReset) begin
if (!nReset) begin
adcData <= 10'd0;
testData <= 10'd0;
end else begin
// Read the ADC data
adcData <= adc_databus;
// Test mode data generation
testData <= testData + 10'd1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000006; const long long int M = 935172938408392767LL; vector<long long int> kub[N]; long long int kra[N]; long long int maska[N]; int deg[N]; int main() { int n, m, a, b; long long int wynik = 0; scanf( %d%d , &n, &m); kra[1] = 1; for (int i = 2; i <= n; i++) kra[i] = (kra[i - 1] * 2) % M; for (int i = 0; i < m; i++) { scanf( %d%d , &a, &b); maska[a] += kra[b]; maska[b] += kra[a]; maska[a] %= M; maska[b] %= M; deg[a]++; deg[b]++; } for (int i = 1; i <= n; i++) { kub[deg[i]].push_back(maska[i]); kub[deg[i]].push_back((maska[i] + kra[i]) % M); } for (int i = 0; i <= n; i++) { sort(kub[i].begin(), kub[i].end()); a = 1; for (int j = 1; j < kub[i].size(); j++) { if (kub[i][j - 1] == kub[i][j]) a++; else { wynik += ((a - 1) * (long long)a) / 2; a = 1; } } wynik += ((a - 1) * (long long)a) / 2; } printf( %I64d n , wynik); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[m], b[m]; for (int i = 0; i < m; i++) { cin >> a[i]; b[i] = a[i]; } int min = 0; for (int i = 0; i < n; i++) { int t1 = INT_MAX; int loc = -1; for (int j = 0; j < m; j++) { if (a[j] < t1 && a[j] > 0) { t1 = a[j]; loc = j; } } a[loc] -= 1; min += t1; } int max = 0; for (int i = 0; i < n; i++) { int t = INT_MIN; int loc = -1; for (int j = 0; j < m; j++) { if (b[j] > t && b[j] > 0) { t = b[j]; loc = j; } } max += t; b[loc] -= 1; } cout << max << << min << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> int main() { int t = 1, i, j, n; long long int p, q, temp, arr[90]; for (j = 0; j < t; j++) { scanf( %lld %lld , &p, &q); scanf( %d , &n); for (i = 0; i < n; i++) scanf( %lld , &arr[i]); for (i = 0; i < n; i++) { if (p / q < arr[i]) { printf( NO n ); break; } p = p - (q * arr[i]); if (p == 0 && i != n - 1) { printf( NO n ); break; } if (i != n - 1) { temp = p; p = q; q = temp; } } if (p == 0 && i == n) printf( YES n ); else if (i == n) printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDLXTP_SYMBOL_V
/**
* sdlxtp: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; cin >> t; while (t--) { int n, m, i, x = 0, y, z; cin >> n; string s[n + 1]; for (int i = 0; i < n; i++) cin >> s[i]; vector<pair<int, int>> v; if (s[0][1] == s[1][0]) { if (s[n - 1][n - 2] == s[0][1]) { v.push_back({n, n - 1}); } if (s[n - 2][n - 1] == s[0][1]) { v.push_back({n - 1, n}); } } else if (s[n - 1][n - 2] == s[n - 2][n - 1]) { if (s[n - 1][n - 2] == s[0][1]) { v.push_back({1, 2}); } if (s[n - 2][n - 1] == s[1][0]) { v.push_back({2, 1}); } } else { if (s[0][1] != 0 ) { v.push_back({1, 2}); } if (s[1][0] != 0 ) { v.push_back({2, 1}); } if (s[n - 2][n - 1] != 1 ) { v.push_back({n - 1, n}); } if (s[n - 1][n - 2] != 1 ) { v.push_back({n, n - 1}); } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i].first << << v[i].second << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_TB_V
`define SKY130_FD_SC_HVL__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_TB_V
|
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapslowadt7410.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [7:0] I2C_ReadCount_s;
wire [15:0] PeriodCounterPresetH_s;
wire [15:0] PeriodCounterPresetL_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [15:0] WaitCounterPresetH_s;
wire [15:0] WaitCounterPresetL_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetHEnable_s;
wire ParamPeriodCounterPresetLEnable_s;
wire ParamThresholdEnable_s;
wire ParamWaitCounterPresetHEnable_s;
wire ParamWaitCounterPresetLEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 7 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
SlowADT7410 SlowADT7410_0 (
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_o(I2C_DataIn_o),
.I2C_Data_i(I2C_DataOut_i),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_s),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPresetH_i(PeriodCounterPresetH_s),
.PeriodCounterPresetL_i(PeriodCounterPresetL_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s),
.WaitCounterPresetH_i(WaitCounterPresetH_s),
.WaitCounterPresetL_i(WaitCounterPresetL_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_F100_400_n_o = 1'b1;
assign I2C_ReadCount_o = I2C_ReadCount_s[3:0];
assign Outputs_o[0] = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_DataIn_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SPI_ReadNext_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign SPI_Write_o = 1'b0;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetH (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetH_s),
.Enable_i(ParamPeriodCounterPresetHEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetL (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetL_s),
.Enable_i(ParamPeriodCounterPresetLEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_WaitCounterPresetH (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(WaitCounterPresetH_s),
.Enable_i(ParamWaitCounterPresetHEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_WaitCounterPresetL (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(WaitCounterPresetL_s),
.Enable_i(ParamWaitCounterPresetLEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetHEnable_s = TODO: implement;
/* Address $03 */
assign ParamPeriodCounterPresetLEnable_s = TODO: implement;
/* Address $04 */
assign ParamThresholdEnable_s = TODO: implement;
/* Address $05 */
assign ParamWaitCounterPresetHEnable_s = TODO: implement;
/* Address $06 */
assign ParamWaitCounterPresetLEnable_s = TODO: implement;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: cpu_dma_queue_regs.v
// Project: NF2.1
// Description: Register module for the CPU DMA queue
//
///////////////////////////////////////////////////////////////////////////////
module cpu_dma_queue_regs
#(
parameter TX_WATCHDOG_TIMEOUT = 125000
)
(
// Interface to "main" module
input tx_timeout,
// Register interface
input reg_req,
input reg_rd_wr_L,
input [`MAC_GRP_REG_ADDR_WIDTH-1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_wr_data,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data,
output reg reg_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// -------- Internal parameters --------------
localparam NUM_REGS_USED = 'h2; /* don't forget to update this when adding regs */
localparam REG_FILE_ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
wire [REG_FILE_ADDR_WIDTH-1:0] addr;
wire addr_good;
wire new_reg_req;
reg reg_req_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data_nxt;
reg [31:0] tx_timeout_cnt;
// ---------- Logic ----------
assign addr = reg_addr[REG_FILE_ADDR_WIDTH-1:0];
assign addr_good = (reg_addr[`CPU_QUEUE_REG_ADDR_WIDTH-1:REG_FILE_ADDR_WIDTH] == 'h0 && addr < NUM_REGS_USED);
assign new_reg_req = reg_req && !reg_req_d1;
// Update the tx timeout counter
always @(posedge clk) begin
if (reset) begin
tx_timeout_cnt <= 'h0;
end
else begin
if (tx_timeout)
tx_timeout_cnt <= tx_timeout_cnt + 'h1;
end
end
// Work out the data to return from a register request
always @*
begin
case (addr)
'h0: reg_rd_data_nxt = tx_timeout_cnt;
default: reg_rd_data_nxt = 'h dead_beef;
endcase
end
// Handle register requests
always @(posedge clk) begin
reg_req_d1 <= reg_req;
if( reset ) begin
reg_rd_data <= 0;
reg_ack <= 0;
end
else begin
// Register access logic
if(new_reg_req) begin // read request
if(addr_good) begin
reg_rd_data <= reg_rd_data_nxt;
end
else begin
reg_rd_data <= 32'hdead_beef;
end
end
// requests complete after one cycle
reg_ack <= new_reg_req;
end // else: !if( reset )
end // always @ (posedge clk)
endmodule // cpu_dma_queue_regs
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__maj3 (
VPWR,
VGND,
X ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
// Local signals
wire csi_opt_296, and0_out ;
wire csi_opt_296, and1_out ;
wire or0_out ;
wire or1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; void my_dbg() { cout << endl; } template <typename Arg, typename... Args> void my_dbg(Arg A, Args... B) { cout << << A; my_dbg(B...); } using ll = long long; using vi = vector<int>; using vl = vector<ll>; using pii = pair<int, int>; const int inf = INT_MAX; const int ninf = INT_MIN; const int mod = 1e9 + 7; const int maxN = 2e5 + 2; void solve() { int n, m; scanf( %d , &n); scanf( %d , &m); vector<pii> a(m); for (int i = (int)(0); i < (int)(m); i++) { scanf( %d , &a[i].first); scanf( %d , &a[i].second); } sort(a.begin(), a.end(), [&](pii a, pii b) { return a.second < b.second; }); ll sum = 0, ans = 0; multiset<int> ms; for (int i = (int)(0); i < (int)(m); i++) { while ((int)ms.size() and (*ms.begin() < a[i].second or (int) ms.size() >= n)) { sum -= *ms.begin(); ms.erase(ms.begin()); } sum += a[i].first; ll cur = sum; ll rem = n - (int)ms.size() - 1; cur += rem * a[i].second; ans = max(ans, cur); ms.insert(a[i].first); } printf( %lld n , ans); } int main() { int t = 1; scanf( %d , &t); while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; void bug() { cout << << endl; } template <class T> void bug(T a) { cout << a << ; } template <class T> void bug(T* a, int n) { for (int i = 0; i < (n); i++) bug(a[i]); } int n, m; vector<pair<pair<int, int>, bool> > e; int ans = 1000000000; vector<int> vs; int fa[111111], size[111111]; int find(int u) { if (fa[u] == u) return u; else return fa[u] = find(fa[u]); } void merge(int u, int v) { u = find(u); v = find(v); if (u == v) return; if (size[u] > size[v]) { size[u] += size[v]; fa[v] = u; } else { size[v] += size[u]; fa[u] = v; } } vector<int> g[111111]; int vis[111111]; void go(bool b) { for (int i = 0; i < (n); i++) g[i].clear(); memset(vis, -1, sizeof(vis)); for (int i = 0; i < (n); i++) { fa[i] = i; size[i] = 1; } for (int i = 0; i < (m); i++) { int u = e[i].first.first; int v = e[i].first.second; bool bb = e[i].second; if (bb == b) { merge(u, v); } } for (int i = 0; i < (m); i++) { int u = e[i].first.first; int v = e[i].first.second; bool bb = e[i].second; if (bb != b) { u = find(u); v = find(v); g[u].push_back(v); g[v].push_back(u); } } int ret = 0; vector<int> vv; for (int i = 0; i < (n); i++) if (find(i) == i && vis[i] == -1) { queue<int> q; q.push(i); vis[i] = 0; int zero = size[i], one = 0; vector<int> zs, os; zs.push_back(i); while (q.size() > 0) { int u = q.front(); q.pop(); for (int v : g[u]) { if (vis[v] != -1) { if (vis[v] != (1 - vis[u])) return; } else { vis[v] = (1 - vis[u]); if (vis[v] == 0) { zero += size[v]; zs.push_back(v); } else { one += size[v]; os.push_back(v); } q.push(v); } } } if (zero < one) { ret += zero; for (int i = 0; i < (zs.size()); i++) vv.push_back(zs[i]); } else { ret += one; for (int i = 0; i < (os.size()); i++) vv.push_back(os[i]); } } if (ans > ret) { ans = ret; set<int> s; for (int i = 0; i < (vv.size()); i++) s.insert(vv[i]); vs.clear(); for (int i = 0; i < (n); i++) if (s.find(find(i)) != s.end()) vs.push_back(i); } } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < (m); i++) { int u, v; char c; cin >> u >> v >> c; u--; v--; bool b = (c == B ); e.push_back(make_pair(make_pair(u, v), b)); } go(0); go(1); if (ans == 1000000000) cout << -1 << endl; else { cout << ans << endl; for (int i = 0; i < (vs.size()); i++) { cout << vs[i] + 1 << ; } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1000; int from[MAXN + 5]; void Gauss(int n, int d, double a[][MAXN + 5], double *Ans) { for (int i = 1; i <= n; i++) from[i] = i; for (int i = 1; i <= n; i++) { if (!a[i][i]) for (int j = i + 1; j <= min(n, i + d); j++) if (a[i][j]) { for (int k = max(1, i - d); k <= min(n, i + d); k++) swap(a[k][i], a[k][j]); swap(from[i], from[j]); break; } for (int j = i + 1; j <= min(n, i + 2 * d); j++) { double div = a[j][i] / a[i][i]; for (int k = i; k <= min(n, i + d); k++) a[j][k] -= a[i][k] * div; a[j][n + 1] -= a[i][n + 1] * div; } } for (int i = n; i >= 1; i--) { Ans[from[i]] = a[i][n + 1]; for (int j = i + 1; j <= min(i + d, n); j++) Ans[from[i]] -= Ans[from[j]] * a[i][j]; Ans[from[i]] /= a[i][i]; } } int n, m, x, y; double a[MAXN + 5][MAXN + 5], Ans[MAXN + 5][MAXN + 5]; int main() { scanf( %d %d %d %d , &n, &m, &x, &y); if (m == 1) { printf( %.4f n , 2.0 * (n - x)); return 0; } for (int i = n - 1; i >= 1; i--) { a[1][1] = 2.0 / 3; a[1][2] = -1.0 / 3; a[1][m + 1] = 1.0 / 3 * Ans[i + 1][1] + 1; for (int j = 2; j <= m - 1; j++) { a[j][j - 1] = -1.0 / 4; a[j][j] = 3.0 / 4; a[j][j + 1] = -1.0 / 4; a[j][m + 1] = 1.0 / 4 * Ans[i + 1][j] + 1; } a[m][m - 1] = -1.0 / 3; a[m][m] = 2.0 / 3; a[m][m + 1] = 1.0 / 3 * Ans[i + 1][m] + 1; Gauss(m, 1, a, Ans[i]); } printf( %.4f n , Ans[x][y]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; string s, s1 = , s2 = ; cin >> n >> s; reverse(s.begin(), s.end()); for (int i = 0; i < s.size(); ++i) { if (i % 2 == 0) s1 += s[i]; else s2 += s[i]; } reverse(s1.begin(), s1.end()); cout << s2 << s1; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 50; const int inf = 0x3f3f3f3f; int n, mod; long long ans; int head[maxn], nxt[maxn << 1], to[maxn << 1], cost[maxn << 1], edge_tot; void add_edge(int u, int v, int c) { nxt[++edge_tot] = head[u]; head[u] = edge_tot; to[edge_tot] = v; cost[edge_tot] = c; } void change(long long &x, int mod) { x = (x % mod + mod) % mod; } void ext_gcd(long long a, long long b, long long &d, long long &x, long long &y) { if (!b) { d = a; x = 1; y = 0; } else { ext_gcd(b, a % b, d, y, x); y -= x * (a / b); } } long long fac[maxn], inv[maxn]; void pre() { fac[0] = 1; for (int i = 1; i < maxn; i++) fac[i] = fac[i - 1] * 10 % mod; for (int i = 0; i < maxn; i++) { long long a = fac[i], b = mod; long long d, x, y; ext_gcd(a, b, d, x, y); change(x, mod); inv[i] = x; } } int root; bool vis[maxn]; int siz[maxn], mxson[maxn]; void ndc_init() { mxson[0] = inf; } void get_root(int u, int f, int sum) { siz[u] = 1; mxson[u] = 0; for (int i = head[u]; i; i = nxt[i]) { int v = to[i]; if (vis[v] || v == f) continue; get_root(v, u, sum); siz[u] += siz[v]; if (mxson[u] < siz[v]) mxson[u] = siz[v]; } if (mxson[u] < sum - siz[u]) mxson[u] = sum - siz[u]; if (mxson[u] < mxson[root]) root = u; } map<long long, int> mp; void add1(int u, int f, register long long sum, int dep, int op) { mp[sum] += op; for (int i = head[u]; i; i = nxt[i]) { int v = to[i]; if (vis[v] || v == f) continue; add1(v, u, (sum + fac[dep] * cost[i] % mod) % mod, dep + 1, op); } } void calc(int u, int f, register long long sum, int dep) { if (!sum) ans++; long long fd = -inv[dep] * sum; change(fd, mod); if (mp.count(fd)) ans += mp[fd]; for (int i = head[u]; i; i = nxt[i]) { int v = to[i]; if (vis[v] || v == f) continue; calc(v, u, (sum * 10 + cost[i]) % mod, dep + 1); } } void solve(int u = 1, int sum = n) { root = 0; get_root(u, 0, sum); vis[root] = 1; for (int i = head[root]; i; i = nxt[i]) { int v = to[i]; if (vis[v]) continue; add1(v, root, cost[i] % mod, 1, 1); } if (mp.count(0)) ans += mp[0]; for (int i = head[root]; i; i = nxt[i]) { int v = to[i]; if (vis[v]) continue; add1(v, root, cost[i] % mod, 1, -1); calc(v, root, cost[i] % mod, 1); add1(v, root, cost[i] % mod, 1, 1); } mp.clear(); int root_sz = siz[root]; for (int i = head[root]; i; i = nxt[i]) { int v = to[i]; if (vis[v]) continue; solve(v, siz[v]); } } int main() { ans = 0; scanf( %d%d , &n, &mod); for (int i = 1; i < n; i++) { int u, v, c; scanf( %d%d%d , &u, &v, &c); u++, v++; add_edge(u, v, c); add_edge(v, u, c); } pre(); ndc_init(); solve(); printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> const double pi = acos(-1); const int MOD = 1e9 + 7; const int INF = 1e9 + 7; const int MAXN = 1e6 + 5; const double eps = 1e-9; using namespace std; int main() { for (int i = 0; i < 9; i++) printf( %d ? ?<>%d n , i, i + 1); printf( 9 ? ?>> ? ?0 n ? ?<>1 n ); for (int i = 0; i <= 9; i++) printf( ?%d>>%d ? n , i, i); printf( ?>> ? ? n>> ? n ); return 0; }
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#include <bits/stdc++.h> using namespace std; inline int ri() { int x; scanf( %d , &x); return x; } template <typename T> inline bool smax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <typename T> inline bool smin(T &a, T b) { if (a > b) { a = b; return true; } return false; } const int maxn = 30005; int n, mod, m = 0; int a[maxn], id[maxn]; int fib[maxn]; struct seg { int l, r, d, off; int x0, x1; seg *ls, *rs; seg(int l_, int r_) : l(l_), r(r_), d(0), off(0), ls(NULL), rs(NULL), x0(0), x1(0) { if (l < r) { int mid = (l + r) >> 1; ls = new seg(l, mid); rs = new seg(mid + 1, r); } } inline void shift(int x) { off += x; d += x; if (x > 0) { int tmp = (x0 * fib[x - 1] + x1 * fib[x]) % mod; x1 = (x0 * fib[x] + x1 * fib[x + 1]) % mod; x0 = tmp; } else if (x < 0) { x = -x; if (x % 2 == 0) { int tmp = (x0 * fib[x + 1] - x1 * fib[x]); x1 = (x1 * fib[x - 1] - x0 * fib[x]); x0 = tmp; } else { int tmp = (x1 * fib[x] - x0 * fib[x + 1]); x1 = (x0 * fib[x] - x1 * fib[x - 1]); x0 = tmp; } x0 %= mod; if (x0 < 0) x0 += mod; x1 %= mod; if (x1 < 0) x1 += mod; } } inline void down() { if (d == 0) return; if (ls) ls->shift(d); if (rs) rs->shift(d); d = 0; } void add(int pos, int x) { if (l == r) { x0 = (x0 + fib[off] * x) % mod; x1 = (x1 + fib[off + 1] * x) % mod; return; } down(); int mid = (l + r) >> 1; if (mid < pos) { rs->add(pos, x); } else { ls->add(pos, x); } x0 = (ls->x0 + rs->x0); x1 = (ls->x1 + rs->x1); if (x0 >= mod) x0 -= mod; if (x1 >= mod) x1 -= mod; off = ls->off; } void move(int x, int lo, int hi) { if (x == 0) return; if (lo <= l && r <= hi) { shift(x); return; } down(); int mid = (l + r) >> 1; if (lo <= mid) ls->move(x, lo, hi); if (hi > mid) rs->move(x, lo, hi); x0 = (ls->x0 + rs->x0); x1 = (ls->x1 + rs->x1); if (x0 >= mod) x0 -= mod; if (x1 >= mod) x1 -= mod; off = ls->off; } } * tree; struct query { int id, l, r; } q[30000]; int res[30000]; int cnt[maxn]; inline void insert(int x) { if ((++cnt[id[x]]) == 1) { tree->move(1, id[x], m); tree->add(id[x], a[x] % mod); } } inline void remove(int x) { if ((--cnt[id[x]]) == 0) { tree->add(id[x], -a[x] % mod); tree->move(-1, id[x], m); } } int main() { scanf( %d%d , &n, &mod); vector<pair<int, int> > v; for (int i = 0; i < (n); i++) { scanf( %d , a + i); v.push_back(pair<int, int>(a[i], i)); } sort(v.begin(), v.end()); id[v[0].second] = 0; for (int i = (1); i < (v.size()); i++) if (v[i].first != v[i - 1].first) { id[v[i].second] = ++m; } else { id[v[i].second] = m; } fib[1] = fib[2] = 1; for (int i = (3); i < (maxn); i++) fib[i] = (fib[i - 1] + fib[i - 2]) % mod; int Q = ri(); for (int i = 0; i < (Q); i++) { q[i].id = i; scanf( %d%d , &q[i].l, &q[i].r); q[i].l--; q[i].r--; } const int sqr = 300; sort(q, q + Q, [](query a, query b) { return a.l / sqr == b.l / sqr ? (((a.l / sqr) & 1) ? a.r > b.r : a.r < b.r) : a.l / sqr < b.l / sqr; }); int L = q[0].l, R = q[0].l - 1; tree = new seg(0, m); for (int i = 0; i < (Q); i++) { while (R < q[i].r) insert(++R); while (L > q[i].l) insert(--L); while (R > q[i].r) remove(R--); while (L < q[i].l) remove(L++); res[q[i].id] = tree->x0; } for (int i = 0; i < (Q); i++) printf( %d n , (res[i] % mod + mod) % mod); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; vector<long long> presum(maxn, 0); int main() { int last = 0; for (long long i = 1; i < maxn; ++i) { presum[i] = presum[i - 1] + min(i, 9LL); if (i >= 10 && i < 100) { presum[i] = presum[i] + (2LL * (i - 9LL)); } else if (i >= 100 && i < 1000) { presum[i] = presum[i] + (2LL * 90LL) + (3LL * (i - 99LL)); } else if (i >= 1000 && i < 10000) { presum[i] = presum[i] + (2LL * 90LL) + (3LL * 900LL) + (4LL * (i - 999LL)); } else if (i >= 10000 && i < 100000) { presum[i] = presum[i] + (2LL * 90LL) + (3LL * 900LL) + (4LL * 9000LL) + (5LL * (i - 9999LL)); } else if (i >= 100000 && i < 1000000) { presum[i] = presum[i] + (2LL * 90LL) + (3LL * 900LL) + (4LL * 9000LL) + (5LL * 90000LL) + (6LL * (i - 99999LL)); } else if (i >= 1000000 && i < 10000000) { presum[i] = presum[i] + (2LL * 90LL) + (3LL * 900LL) + (4LL * 9000LL) + (5LL * 90000LL) + (6LL * 900000LL) + (7LL * (i - 999999LL)); } } int q; cin >> q; while (q--) { long long k; cin >> k; int it = lower_bound(presum.begin(), presum.end(), k) - presum.begin(); string aux = ; for (int i = 1; i <= it; ++i) { aux += to_string(i); } cout << aux[k - (presum[it - 1] + 1)] << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = INT_MAX; int n; struct node { long double x, y; } a[100010]; bool check(long double xx) { long double l, r; l = -1e19, r = 1e19; for (int i = 0; i < n; ++i) { if (a[i].y >= xx * 2 || l > r) return false; l = max(l, a[i].x - sqrt(2 * a[i].y * xx - a[i].y * a[i].y)); r = min(r, a[i].x + sqrt(2 * a[i].y * xx - a[i].y * a[i].y)); } return l <= r; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %lf%lf , &a[i].x, &a[i].y); for (int i = 0; i < n; ++i) if (a[i].y * a[n - 1].y < 0) { printf( -1 ); return 0; } else a[i].y = (a[i].y > 0) ? a[i].y : -a[i].y; long double l = 0, r = 1e19, mid; for (int i = 0; i <= 100; i++) { mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } printf( %.10Lf , mid); }
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#include <bits/stdc++.h> using namespace std; const unsigned long long hash1 = 201326611; const unsigned long long hash2 = 50331653; const int N = 200000 + 10; const int M = 20; vector<int> g[N]; int n, vis[N]; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; int u, v; for (int i = 1; i < n; i++) { cin >> u >> v; vis[u]++; vis[v]++; } int flag = 0; for (int i = 1; i <= n; i++) { if (vis[i] == 2) flag = 1; } if (flag) cout << NO << endl; else cout << YES << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; map<int, string> mapa; int main() { mapa[0] = zero ; mapa[1] = one ; mapa[2] = two ; mapa[3] = three ; mapa[4] = four ; mapa[5] = five ; mapa[6] = six ; mapa[7] = seven ; mapa[8] = eight ; mapa[9] = nine ; mapa[10] = ten ; mapa[11] = eleven ; mapa[12] = twelve ; mapa[13] = thirteen ; mapa[14] = fourteen ; mapa[15] = fifteen ; mapa[16] = sixteen ; mapa[17] = seventeen ; mapa[18] = eighteen ; mapa[19] = nineteen ; mapa[20] = twenty ; mapa[30] = thirty ; mapa[40] = forty ; mapa[50] = fifty ; mapa[60] = sixty ; mapa[70] = seventy ; mapa[80] = eighty ; mapa[90] = ninety ; int num; cin >> num; if (num <= 19) { cout << mapa[num] << endl; } else if (num % 10 == 0) { cout << mapa[num] << endl; } else { int aux = (num / 10) * 10; int rest = num % 10; cout << mapa[aux] << - << mapa[rest] << endl; } return 0; }
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#include <bits/stdc++.h> const int oo = 0x3f3f3f3f, mod = 1e9 + 7; using namespace std; int dx[]{1, -1, 0, 0, 1, 1, -1, -1}; int dy[]{0, 0, 1, -1, 1, -1, 1, -1}; long long OO = (1LL * oo * oo); void K_K() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { K_K(); long long n, mx = 0, mxidx = 0; cin >> n; map<long long, long long> mp; vector<long long> v(n + 2); vector<pair<long long, pair<long long, long long>>> ans; for (int i = 1; i <= n; i++) { cin >> v[i], mp[v[i]]++; if (mp[v[i]] > mx) mxidx = i, mx = mp[v[i]]; } for (int i = mxidx - 1; i > 0; i--) { if (v[i] > v[i + 1]) { v[i] -= abs(v[i] - v[i + 1]); ans.push_back({2, {i, i + 1}}); } else if (v[i] < v[i + 1]) { ans.push_back({1, {i, i + 1}}); v[i] += abs(v[i] - v[i + 1]); } } for (int i = mxidx + 1; i <= n; i++) { if (v[i] > v[i - 1]) { v[i] -= abs(v[i] - v[i - 1]); ans.push_back({2, {i, i - 1}}); } else if (v[i] < v[i - 1]) { ans.push_back({1, {i, i - 1}}); v[i] += abs(v[i] - v[i - 1]); } } cout << (int)(ans.size()) << n ; for (int i = 0; i < (int)(ans.size()); i++) cout << ans[i].first << << ans[i].second.first << << ans[i].second.second << n ; }
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/**
* $Id: red_pitaya_daisy_test.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya daisy chain communication module. Testing module.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Testing serial connection module.
*
*
* ----------< CFG
* |
* /----------\
* RX ----------> | COMPARE | -----> STATUS
* \----------/
* ^
* PARALLEL |
* |
* /-----------\
* TX <---------- | GENERATE |
* \-----------/
*
*
* In order to test serial link over multiple board this module was made. Every
* 32 cycles it sends semi-random numbers to transmitter.If retured value is the
* same (non zero) then it increase successful counter. If value is different it
* increases error counter. Both counters can be reseted by SW.
*
*/
module red_pitaya_daisy_test
(
// transmit ports
input tx_clk_i , //!< transmitter clock
input tx_rstn_i , //!< transmitter reset - active low
input tx_rdy_i , //!< transmitter ready
output tx_dv_o , //!< transmitter data valid
output [ 16-1: 0] tx_dat_o , //!< transmitter data
// receive ports
input rx_clk_i , //!< receiver clock
input rx_rstn_i , //!< receiver reset - active low
input rx_dv_i , //!< receiver data valid
input [ 16-1: 0] rx_dat_i , //!< receiver data
input stat_clr_i , //!< status clear
output [ 32-1: 0] stat_err_o , //!< status error counter
output [ 32-1: 0] stat_dat_o //!< status success counter
);
//---------------------------------------------------------------------------------
//
// generate random numbers
wire [32-1: 0] rand_temp ;
reg [32-1: 0] rand_work ;
reg [32-1: 0] rand_dat ;
assign rand_temp = rand_work ^ (32'h84C11DB6 & {32{rand_work[0]}}) ; // x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
always @(posedge tx_clk_i) begin
if (tx_rstn_i == 1'b0) begin
rand_work <= 32'h01010101 ; // starting seed
rand_dat <= 32'h0 ;
end
else begin
rand_work <= {rand_work[0], rand_temp[31:1]};
rand_dat <= rand_work ;
end
end
//---------------------------------------------------------------------------------
//
// Transmitter
reg [ 5-1: 0] tx_dv_cnt ;
reg [16-1: 0] tx_dat ;
always @(posedge tx_clk_i) begin
if (tx_rstn_i == 1'b0) begin
tx_dv_cnt <= 5'h0 ;
tx_dat <= 16'h0 ;
end
else begin
tx_dv_cnt <= tx_dv_cnt + 5'h1 ;
if ( (tx_dv_cnt[4:2] == 3'h7) && tx_rdy_i ) // every 32 cycles (when ready)
tx_dat <= rand_dat[15:0] ;
end
end
assign tx_dv_o = (tx_dv_cnt[4:2] == 3'h7) && tx_rdy_i;
assign tx_dat_o = rand_dat[15:0] ;
//---------------------------------------------------------------------------------
//
// Receiver and verifier
reg [32-1: 0] rx_err_cnt ;
reg [32-1: 0] rx_dat_cnt ;
reg rx_dv ;
reg [16-1: 0] rx_dat ;
always @(posedge rx_clk_i) begin
if (rx_rstn_i == 1'b0) begin
rx_err_cnt <= 32'h0 ;
rx_dat_cnt <= 32'h0 ;
rx_dv <= 1'b0 ;
rx_dat <= 16'h0 ;
end
else begin
rx_dv <= rx_dv_i ;
rx_dat <= rx_dat_i ;
// counting errors
if ( rx_dv && (rx_dat != tx_dat) && (rx_dat != 16'h0))
rx_err_cnt <= rx_err_cnt + 32'h1 ;
else if (stat_clr_i)
rx_err_cnt <= 32'h0 ;
// counting successfull transfer
if ( rx_dv && (rx_dat == tx_dat) && (rx_dat != 16'h0))
rx_dat_cnt <= rx_dat_cnt + 32'h1 ;
else if (stat_clr_i)
rx_dat_cnt <= 32'h0 ;
end
end
assign stat_err_o = rx_err_cnt ;
assign stat_dat_o = rx_dat_cnt ;
endmodule
|
// sram_0.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module sram_0 (
input wire iCLK, // clk.clk
inout wire [15:0] SRAM_DQ, // avalon_slave_0_export.export
output wire [17:0] SRAM_ADDR, // .export
output wire SRAM_UB_N, // .export
output wire SRAM_LB_N, // .export
output wire SRAM_WE_N, // .export
output wire SRAM_CE_N, // .export
output wire SRAM_OE_N, // .export
input wire [15:0] iDATA, // avalon_slave_0.writedata
output wire [15:0] oDATA, // .readdata
input wire [17:0] iADDR, // .address
input wire iWE_N, // .write_n
input wire iOE_N, // .read_n
input wire iCE_N, // .chipselect_n
input wire [1:0] iBE_N, // .byteenable_n
input wire iRST_N // reset_n.reset_n
);
SRAM_16Bit_512K sram_0 (
.iCLK (iCLK), // clk.clk
.SRAM_DQ (SRAM_DQ), // avalon_slave_0_export.export
.SRAM_ADDR (SRAM_ADDR), // .export
.SRAM_UB_N (SRAM_UB_N), // .export
.SRAM_LB_N (SRAM_LB_N), // .export
.SRAM_WE_N (SRAM_WE_N), // .export
.SRAM_CE_N (SRAM_CE_N), // .export
.SRAM_OE_N (SRAM_OE_N), // .export
.iDATA (iDATA), // avalon_slave_0.writedata
.oDATA (oDATA), // .readdata
.iADDR (iADDR), // .address
.iWE_N (iWE_N), // .write_n
.iOE_N (iOE_N), // .read_n
.iCE_N (iCE_N), // .chipselect_n
.iBE_N (iBE_N), // .byteenable_n
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vll = vector<ll>; using vii = vector<int>; using pii = pair<int, int>; template <typename T = vii> using vec = vector<T>; const ll INF = 1e18, MOD = 998244353; const int MAX = 1e6; ll ft[MAX + 1]; void cf() { ft[0] = 1; for (int i = 1; i <= MAX; i++) { ft[i] = (i * ft[i - 1]) % MOD; } } int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); cf(); int n; cin >> n; unordered_map<int, int> cnt; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; u--, v--; cnt[u]++; cnt[v]++; } ll res = 1; for (auto p : cnt) { (res *= ft[p.second]) %= MOD; } cout << (n * res) % MOD << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O2111A_FUNCTIONAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_FUNCTIONAL_V
|
// test_pg.v
`timescale 1ns / 1ps
module test_pg;
reg clk = 0;
reg sync = 0;
reg reset = 1;
reg trigger = 0;
wire [4:0]signal;
// avalon interface
reg write_data = 0;
reg write_ctrl = 0;
reg read_ctrl = 0;
reg [7:0]address;
reg [31:0]writedata;
wire [31:0]readdata;
reg [1:0]byteenable = 2'b11;
task automatic pgwrite_data(input [7:0]a, input [15:0]d);
begin
@(posedge clk)
begin
#5;
write_data <= 1;
write_ctrl <= 0;
read_ctrl <= 0;
address <= a;
writedata <= {16'd0, d};
end
end
endtask
task automatic pgwrite_ctrl(input [7:0]a, input [31:0]d);
begin
@(posedge clk)
begin
#5;
write_data <= 0;
write_ctrl <= 1;
read_ctrl <= 0;
address <= a;
writedata <= d;
end
end
endtask
task automatic pgend();
begin
@(posedge clk)
begin
#5;
write_data <= 0;
write_ctrl <= 0;
read_ctrl <= 0;
address <= 8'dx;
writedata <= 32'dx;
end
end
endtask
always #10 clk <= ~clk;
integer n = 0;
always @(posedge clk)
begin
n <= n + 1;
sync <= !sync;
end
initial
begin
#25 reset = 0;
#20;
pgwrite_data( 0, { 5'b01000, 8'd1 } );
pgwrite_data( 1, { 5'b00100, 8'd2 } );
pgwrite_data( 2, { 5'b00010, 8'd3 } );
pgwrite_data( 3, { 5'b10001, 8'd4 } );
pgwrite_data( 4, { 5'b01111, 8'd1 } );
pgwrite_data( 5, { 5'b00100, 8'd1 } );
pgwrite_data( 6, { 5'b00010, 8'd5 } );
pgwrite_data( 7, { 5'b00001, 8'd0 } ); // stop
pgend();
pgwrite_ctrl( 1, 40); // period
pgwrite_ctrl( 0, {24'd0, 8'b10000000}); // loop
pgend();
#160 trigger = 1;
#40 trigger = 0;
#80 pgwrite_ctrl(0, {24'd0, 8'b10000001}); // start
pgend();
@(negedge pg.running);
#100 $stop(2);
end
patterngenerator pg
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
.avs_ctrl_address(address[0]),
.avs_ctrl_read(read_ctrl),
.avs_ctrl_readdata(readdata),
.avs_ctrl_write(write_ctrl),
.avs_ctrl_writedata(writedata),
.avs_data_address(address),
.avs_data_write(write_data),
.avs_data_byteenable(byteenable),
.avs_data_writedata(writedata[15:0]),
.clkena(sync),
.trigger(trigger),
.pgout(signal)
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// TX side of flow control -- when other side sends PAUSE, we wait
module flow_ctrl_tx
(input rst,
input tx_clk,
//host processor
input tx_pause_en,
// From MAC_rx_ctrl
input [15:0] pause_quanta,
input pause_quanta_val,
// MAC_tx_ctrl
output pause_apply,
input paused);
// ******************************************************************************
// Inhibit our TX from transmitting because they sent us a PAUSE frame
// ******************************************************************************
// Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
// as big as 16 bits, so 22 bits are needed for the counter
reg [15+6:0] pause_quanta_counter;
reg pqval_d1, pqval_d2;
always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
always @(posedge tx_clk) pqval_d2 <= pqval_d1;
always @ (posedge tx_clk or posedge rst)
if (rst)
pause_quanta_counter <= 0;
else if (pqval_d1 & ~pqval_d2)
pause_quanta_counter <= {pause_quanta, 6'b0};
else if((pause_quanta_counter!=0) & paused)
pause_quanta_counter <= pause_quanta_counter - 1;
assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
endmodule // flow_ctrl
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; if (n > 2) cout << n - 2 << endl; else if (n <= 2) cout << n + 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long k; cin >> k; getchar(); char s[1000001]; cin >> s; int a[strlen(s)]; long long sum = 0; for (int i = 0; i < strlen(s); i++) { sum += s[i] - 48; a[i] = s[i] - 48; } k = k - sum; sort(a, a + strlen(s)); int c = 0; for (int i = 0; i < strlen(s); i++) { if (k > 0) { k -= (9 - a[i]); c++; } else break; } cout << c << endl; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench UART Decoder ////
//// ////
//// Description ////
//// ORPSoC Testbench UART output decoder ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - jb, ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
`timescale 1ns/1ns
module uart_decoder(clk, uart_tx);
input clk;
input uart_tx;
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
// Something to trigger the task
always @(posedge clk)
uart_decoder;
task uart_decoder;
reg [7:0] tx_byte;
begin
while (uart_tx !== 1'b1)
@(uart_tx);
// Wait for start bit
while (uart_tx !== 1'b0)
@(uart_tx);
#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
tx_byte[0] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[1] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[2] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[3] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[4] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[5] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[6] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[7] = uart_tx;
#uart_baudrate_period_ns;
//Check for stop bit
if (uart_tx !== 1'b1)
begin
// Wait for return to idle
while (uart_tx !== 1'b1)
@(uart_tx);
end
// display the char
$write("%c", tx_byte);
end
endtask // user_uart_read_byte
endmodule // uart_decoder
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 4; int n, k, b[N], vis[N]; long long l, dp[N], temp[N]; const long long mod = 1e9 + 7; struct node { friend bool operator<(node x, node y) { if (x.a == y.a) return x.pos < y.pos; return x.a < y.a; } int a, pos; }; node po[N]; int main() { cin >> n >> l >> k; for (int i = 0; i < n; i++) { scanf( %d , &po[i].a); po[i].pos = i; } sort(po, po + n); po[n].a = po[n - 1].a + 10; for (int i = n - 1; i >= 0; i--) { if (po[i].a == po[i + 1].a) vis[i] = vis[i + 1]; else vis[i] = i; b[po[i].pos] = i; } for (int i = 0; i < n; i++) { dp[i] = 1; } long long ans = l, sum, fn = (long long)n; ans %= mod; for (int i = 2; i <= k; i++) { temp[0] = dp[0]; for (int j = 1; j < n; j++) { temp[j] = temp[j - 1] + dp[j]; temp[j] %= mod; } sum = 0; for (int j = 0; j < n; j++) { dp[j] = temp[vis[j]]; sum += dp[j]; sum %= mod; } if (l % fn == 0) { if (i <= l / fn) { ans += ((l / fn - i + 1) % mod) * sum; ans %= mod; } } else { if (i <= l / fn) { ans += ((l / fn - i + 1) % mod) * sum; ans %= mod; sum = 0; for (int j = 0; j < l % fn; j++) { sum += dp[b[j]]; sum %= mod; } ans += sum; ans %= mod; } else if (i == l / fn + 1) { sum = 0; for (int j = 0; j < l % fn; j++) { sum += dp[b[j]]; sum %= mod; } ans += sum; ans %= mod; } } } cout << ans % mod << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; for (int i = 0; i < a; i++) { int c = 0; int j; cin >> j; int f = j % 10; if (j > 1) f = (f - 1) * 10; if (j > 1000) { f = f + 10; } else if (j > 100) { f = f + 6; } else if (j > 10) { f = f + 3; } else if (j > 1 && j < 10) { f = f + 1; } cout << f << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long i, j, k, l, n, m; long long t; cin >> t; while (t--) { cin >> n >> m; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (i == 1 && j == 1) cout << B ; else if (i == 1 && j >= 2) cout << W ; else cout << B ; } cout << n ; } } }
|
#include <bits/stdc++.h> using namespace std; const long long e = 1e5 + 110; bool zs[e]; long long num[e]; void sai() { for (long long i = 2; i <= e - 99; i++) { if (zs[i]) continue; for (long long j = i + i; j <= e - 99; j += i) { zs[j] = true; } } for (long long tot = 0, i = 2; i <= e - 99; i++) { if (!zs[i]) tot++, num[tot] = i; } } struct fengjie { long long v, t; } f[e]; long long cnf = 0; void fj(long long x) { long long tmp = x; for (long long i = 2; i <= x; i++) { long long cnt = 0; while (tmp % i == 0) { tmp /= i; cnt++; } if (cnt == 0) continue; cnf++; f[cnf].v = i, f[cnf].t = cnt; } return; } long long ksm(long long a, long long z) { long long ret = 1; if (z == 0) return 1; while (z != 1) { if (z % 2 == 1) { ret *= a; a *= a; } else { a *= a; } z /= 2; } return a * ret; } fengjie an[e]; signed main() { long long n; cin >> n; sai(); fj(n); long long ans = 1, g = 0, cna = 0, minn; for (long long i = cnf; i > 0; i--) { for (long long j = 1; j <= f[i].t; j++) { if (cna == 0) { g++; ans *= ksm(num[g], f[i].v - 1); an[++cna].v = num[g]; an[cna].t = f[i].v - 1; continue; } long long pl = -1; minn = ans * ksm(num[g + 1], f[i].v - 1); for (long long l = 1; l <= cna; l++) { long long ct = f[i].v * (an[l].t + 1) - 1; long long tmp = ans / ksm(an[l].v, an[l].t); tmp *= ksm(an[l].v, ct); if (tmp < ans or ksm(an[l].v, ct) < an[l].v) continue; if (tmp < minn) { pl = l; minn = tmp; } } if (pl == -1) { g++; ans *= ksm(num[g], f[i].v - 1); an[++cna].v = num[g]; an[cna].t = f[i].v - 1; } if (pl != -1) { long long tmp = ans / ksm(an[pl].v, an[pl].t); long long ct = f[i].v * (an[pl].t + 1) - 1; ans = tmp * ksm(an[pl].v, ct); } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[(1 << 20) + 4], n; long long store[21][2], INV = 0; long long query(int l, int r, int no) { return (A + r + 1 - upper_bound(A + l, A + r + 1, no)); } void gen(int de, int l, int r) { if (!de) return; gen(de - 1, l, (l + r) / 2); gen(de - 1, (l + r) / 2 + 1, r); int a = l, b = (l + r) / 2, c = r; for (int i = a; i <= b; i++) { long long nos = query(b + 1, c, A[i]); store[de][1] += nos; } for (int i = b + 1; i <= c; i++) { long long nos = query(a, b, A[i]); store[de][0] += nos; } sort(A + l, A + r + 1); } int main() { cin >> n; for (int i = 1; i <= (1 << n); i++) cin >> A[i]; gen(n, 1, (1 << n)); for (int de = n; de > 0; de--) INV += store[de][0]; int m; cin >> m; while (m--) { int de; cin >> de; while (de != 0) { INV -= store[de][0]; INV += store[de][1]; swap(store[de][0], store[de][1]); de--; } printf( %lld n , INV); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_4_V
`define SKY130_FD_SC_HD__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_4_V
|
#include <bits/stdc++.h> using namespace std; bool isprime(unsigned long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (unsigned long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } long long int exp(long long int value, long long int power) { long long int result = 1; while (power > 0) { if (power & 1LL) { result *= value; result %= 1000000007; } value *= value; value %= 1000000007; power /= 2LL; } return result; } long long int lcm(long long n1, long long n2) { long long max = (n1 > n2) ? n1 : n2; do { if (max % n1 == 0 && max % n2 == 0) { return max; } else ++max; } while (true); } int isprime(long long n) { if (n <= 3) return 1; if (n % 2 == 0 || n % 3 == 0) return 0; for (long long i = 5; i * i <= n; i += 6) { if (n % i == 0 || n % (i + 2) == 0) return 0; } return 1; } long long a[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int f, cnt, len, p, q, r, t, i, j, k, l, n, m, x, y, z, b, c, s; cin >> n; n -= 10; x = 0; if (n == 1) x = 4; if (n == 2) x = 4; if (n == 3) x = 4; if (n == 4) x = 4; if (n == 5) x = 4; if (n == 6) x = 4; if (n == 7) x = 4; if (n == 8) x = 4; if (n == 9) x = 4; if (n == 10) x = 15; if (n == 11) x = 4; cout << x; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 1e3; long long all[MAXN]; struct node { node *child[2]; node() { child[0] = child[1] = NULL; } }; node *root; deque<short> binary(long long x) { deque<short> ans; while (x) { ans.push_front(x % 2); x /= 2; } while (ans.size() < 50) ans.push_front(0); return ans; } void add(long long x) { deque<short> a = binary(x); node *C = root; while (a.size()) { if (C->child[a[0]] == NULL) C->child[a[0]] = new node; C = C->child[a[0]]; a.pop_front(); } } long long query(long long x) { deque<short> a = binary(x); long long ans = 0; node *C = root; while (a.size()) { if (C->child[1 - a[0]] != NULL) { C = C->child[1 - a[0]]; ans *= 2; ans += 1; } else { C = C->child[a[0]]; ans *= 2; } a.pop_front(); } return ans; } int main() { root = new node; int n; cin >> n; long long xorall = 0; for (int i = 1; i <= n; ++i) { cin >> all[i]; xorall ^= all[i]; } long long maxgot = 0; int ai = 0, bi = 0; long long total = 0; add(total); for (int i = 1; i <= n; ++i) { total ^= all[i]; add(total); maxgot = max(maxgot, query(total ^ xorall)); } cout << fixed << maxgot << endl; return 0; }
|
module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 2) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 3) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUFKAPWR_FUNCTIONAL_PP_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__bufkapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long MOD = 1e9 + 7; template <class T> inline void chmax(T &a, const T &b) { if ((a) < (b)) (a) = (b); } template <class T> inline void chmin(T &a, const T &b) { if ((a) > (b)) (a) = (b); } template <typename T> using PQ = priority_queue<T, vector<T>, greater<T>>; struct Fast { Fast() { std::cin.tie(0); ios::sync_with_stdio(false); } } fast; long long query() { long long n; cin >> n; vector<long long> x(n); vector<long long> y(n); vector<long long> L(n); vector<long long> U(n); vector<long long> R(n); vector<long long> D(n); long long l = -1e5; long long r = 1e5; long long d = -1e5; long long u = 1e5; for (long long i = (long long)(0); i < (long long)(n); ++i) { cin >> x[i] >> y[i] >> L[i] >> U[i] >> R[i] >> D[i]; if (L[i] == 1 && R[i] == 1) { } if (L[i] == 0 && R[i] == 1) { chmax(l, x[i]); } if (L[i] == 1 && R[i] == 0) { chmin(r, x[i]); } if (L[i] == 0 && R[i] == 0) { chmax(l, x[i]); chmin(r, x[i]); } if (D[i] == 1 && U[i] == 1) { } if (D[i] == 0 && U[i] == 1) { chmax(d, y[i]); } if (D[i] == 1 && U[i] == 0) { chmin(u, y[i]); } if (D[i] == 0 && U[i] == 0) { chmax(d, y[i]); chmin(u, y[i]); } } 42; 42; if (l <= r && d <= u) { 42; printf( 1 %lld %lld n , l, d); } else { printf( 0 n ); } return 0; } long long solve() { long long Q; cin >> Q; for (long long q = (long long)(0); q < (long long)(Q); ++q) { query(); } return 0; } signed main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string num1, num2, num3; int i, j, k, l, m, n, last, flag = 0; cin >> num1; num2 = num1; num3 = num1; l = num1.length(); last = num1.at(l - 1) - 48; for (i = 0; i < l - 1; i++) { m = num2.at(i) - 48; if (m % 2 == 0 && m < last) { swap(num2.at(i), num2.at(l - 1)); flag = 1; cout << num2 << endl; return 0; } } if (flag == 0) { for (i = l - 2; i >= 0; i--) { m = num3.at(i); if (m % 2 == 0 && last < m) { swap(num3.at(i), num3.at(l - 1)); cout << num3 << endl; return 0; } } } cout << -1 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_4_V
`define SKY130_FD_SC_HDLL__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_4_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: audio_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; vector<string> vec[1003], v; bool mat[26][26], flag, ok[26], vis[26], run[26]; int ind[26]; inline bool func(int x, int y) { vector<int> vs, vt; for (int i = 0; i < v[x].size(); i++) vs.push_back(v[x][i]); for (int i = 0; i < v[y].size(); i++) vt.push_back(v[y][i]); reverse(vs.begin(), vs.end()); reverse(vt.begin(), vt.end()); while (!vs.empty() && !vt.empty()) { if (vt.back() != vs.back()) return mat[vs.back() - a ][vt.back() - a ] = 1; else vs.pop_back(), vt.pop_back(); } if (!vs.empty()) return 0; else return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); flag = 1; string str; int n, k, p; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> p; for (int j = 0; j < k; j++) { cin >> str, vec[p].emplace_back(str); for (int l = 0; l < str.size(); l++) ok[str[l] - a ] = 1; } } for (int i = 0; i < n; i++) for (int j = 0; j < k; j++) v.emplace_back(vec[i][j]); for (int i = 0; i < v.size() - 1 && flag; i++) flag = func(i, i + 1); for (int i = 0; i < 26; i++) for (int j = 0; j < 26; j++) ind[j] += mat[i][j]; int cnt = 0, tot = 0; for (int i = 0; i < 26; i++) tot += ok[i]; queue<int> q; for (int i = 0; i < 26; i++) if (ok[i] && !ind[i]) q.push(i); vector<int> res; while (!q.empty() && flag) { int x = q.front(); q.pop(); res.push_back(x); for (int i = 0; i < 26; i++) if (mat[x][i]) { ind[i]--; if (!ind[i]) q.push(i); } } if (flag && res.size() == tot) { for (int i = 0; i < res.size(); i++) cout << (char)(res[i] + a ); cout << n ; } else cout << IMPOSSIBLE n ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:44 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_lmb_bram_0/system_lmb_bram_0_stub.v
// Design : system_lmb_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module system_lmb_bram_0(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int b[2] = {1, -1}; int n, m, f[105][55][205][2], ans; char a[200]; int main() { scanf( %s , a); scanf( %d , &n); f[0][0][0][0] = 1; m = strlen(a); for (int i = (0); i <= (m - 1); i++) for (int j = (0); j <= (n); j++) for (int k = (0); k <= (2 * i); k++) for (int c = (0); c <= (1); c++) if (f[i][j][k][c]) { f[i + 1][j + (a[i] != T )][k + 1][c ^ 1] = 1; f[i + 1][j + (a[i] != F )][k + 1 + b[c]][c] = 1; } for (int j = (0); j <= (n); j++) if (((n - j) & 1) == 0) for (int c = (0); c <= (1); c++) for (int k = (0); k <= (2 * m); k++) if (f[m][j][k][c]) ans = max(ans, abs(k - m)); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ceiling(long long a, long long b) { if (a % b != 0) { return (a / b) + 1; } else return (a / b); } void solve() { long long n, k; cin >> n >> k; long long a[n * k]; for (long long i = 0; i < n * k; i++) { cin >> a[i]; } sort(a, a + n * k); long long cnt = 0; long long cnt1 = 0; long long i = n * k - 1 - (n / 2); while (cnt1 < k and i >= 0) { cnt1++; cnt += a[i]; i -= (n / 2) + 1; } cout << cnt << endl; return; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long tc; cin >> tc; while (tc--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_gtp_cpllpd_ovrd.v
// Version : 3.2
`timescale 1ns / 1ps
module PCIeGen2x8If128_gtp_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2)
begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Tomasz Kryjak
//
// Create Date: 11:29:28 10/28/2013
// Design Name:
// Module Name: tb_filter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_hdmi(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
wire [7:0] lut_blue;
wire [7:0] lut_red;
wire [7:0] lut_green;
BINARYZACJA lut_r (
.a(rx_red), // input [7 : 0] a
.clk(rx_pclk), // input clk
.qspo(lut_red) // output [7 : 0] qspo
);
BINARYZACJA lut_g (
.a(rx_green), // input [7 : 0] a
.clk(rx_pclk), // input clk
.qspo(lut_green) // output [7 : 0] qspo
);
BINARYZACJA lut_b (
.a(rx_blue), // input [7 : 0] a
.clk(rx_pclk), // input clk
.qspo(lut_blue) // output [7 : 0] qspo
);
reg lut_de = 0;
reg lut_hsync = 0;
reg lut_vsync = 0;
always @(posedge rx_pclk)
begin
lut_de <= rx_de;
lut_hsync <= rx_hsync;
lut_vsync <= rx_vsync;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = lut_de;
assign tx_hsync = lut_hsync;
assign tx_vsync = lut_vsync;
assign tx_blue = lut_blue & lut_green & lut_red;
assign tx_green = lut_blue & lut_green & lut_red;
assign tx_red = lut_blue & lut_green & lut_red;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_4_V
`define SKY130_FD_SC_HD__O311AI_4_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; cout << a + b; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_2_V
`define SKY130_FD_SC_HDLL__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_LP_V
`define SKY130_FD_SC_LP__OR2B_LP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_lp (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_lp (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_LP_V
|
#include <bits/stdc++.h> using namespace std; struct point { int x, y; } a[5], b[5]; int ans; int dis(int i, int j) { int res = (a[i].x - a[j].x) * (a[i].x - a[j].x); return res + (a[i].y - a[j].y) * (a[i].y - a[j].y); } int ok() { map<int, int> mp; for (int i = 1; i < 4; i++) for (int j = i + 1; j <= 4; j++) mp[dis(i, j)]++; if (mp.size() != 2) return 0; int t; for (auto tmp : mp) { if (tmp.first == 0) return 0; t = tmp.second; } if (t == 4 || t == 2) return 1; return 0; } void Rotate(int p) { int x = a[p].x - b[p].x, y = a[p].y - b[p].y; a[p].x = -y + b[p].x; a[p].y = x + b[p].y; } void dfs(int p, int step) { if (p == 5) { if (ok()) ans = min(ans, step); return; } dfs(p + 1, step); for (int i = 1; i < 4; i++) { Rotate(p); dfs(p + 1, step + i); } Rotate(p); } int main() { int T; cin >> T; while (T--) { ans = 100; for (int i = 1; i <= 4; i++) cin >> a[i].x >> a[i].y >> b[i].x >> b[i].y; dfs(1, 0); if (ans == 100) puts( -1 ); else cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long int det(long long int a, long long int b, int bit) { if (!bit) { if (a & 1) return a; if (b & 1) return b; return a; } if (a & (1ll << bit)) return det(a, b, bit - 1); if (!(b & (1ll << bit))) return det(a, b, bit - 1); if ((b & ((1ll << (bit + 1)) - 1)) == ((1ll << (bit + 1)) - 1)) return b; return ((a & (~((1ll << bit) - 1))) | ((1ll << bit) - 1)); } int main() { int n = 0; cin >> n; long long int a = 0, b = 0; while (n--) { cin >> a >> b; cout << det(a, b, 60) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; cout << n % 2; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_tagmem #(
parameter depth = 2,
parameter width = 2
) (
input sys_clk,
/* Primary port (read-write) */
input [depth-1:0] a,
input we,
input [width-1:0] di,
output [width-1:0] do,
/* Secondary port (read-only) */
input [depth-1:0] a2,
output [width-1:0] do2
);
reg [width-1:0] tags[0:(1 << depth)-1];
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
a_r <= a;
a2_r <= a2;
end
always @(posedge sys_clk) begin
if(we)
tags[a] <= di;
end
assign do = tags[a_r];
assign do2 = tags[a2_r];
// synthesis translate_off
integer i;
initial begin
for(i=0;i<(1 << depth);i=i+1)
tags[i] = 0;
end
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> #pragma GCC diagnostic ignored -Wunused-result #pragma GCC diagnostic ignored -Wsign-compare using namespace std; void solve(); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int test_case = 1; cin >> test_case; while (test_case--) { solve(); } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; } void solve() { int n, m, t; vector<int> arr; bool odd = false; bool zero = false; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> t; if (t == 0) { zero = true; } if (t < 0) { odd = !odd; arr.push_back(-t); } else { arr.push_back(t); } } } sort(arr.begin(), arr.end()); int sum = 0; for (int i = 0; i < arr.size(); i++) { sum += arr[i]; } if (zero) { cout << sum << endl; } else { if (odd) { sum -= 2 * arr[0]; cout << sum << endl; } else { cout << sum << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k = 0, c = -1, x, z; cin >> n; while (true) { c += 1; x = pow(10, c); z = 9 * x; if (n - z > 0) { n -= z; k += (z * (c + 1)); } else { n *= (c + 1); k += n; break; } } cout << k; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 3; struct node { int nonzero, val; void merge(node &n1, node &n2, int range) { if (val) nonzero = range; else nonzero = n1.nonzero + n2.nonzero; } void update(int x) { val += x; } } tree[7 * MAX]; void update(int root, int l, int r, int u, int v, int val) { if (u <= l and v >= r) { tree[root].update(val); tree[root].merge(tree[2 * root], tree[2 * root + 1], r - l + 1); return; } int mid = (l + r) / 2; if (u <= mid) update(2 * root, l, mid, u, v, val); if (v > mid) update(2 * root + 1, mid + 1, r, u, v, val); tree[root].merge(tree[2 * root], tree[2 * root + 1], r - l + 1); } vector<int> G[MAX], intervals[MAX]; int st[MAX], en[MAX], Time = 0, ans[MAX], n, m; void dfs(int x, int par) { st[x] = ++Time; for (int i = 0; i < G[x].size(); i++) if (G[x][i] != par) dfs(G[x][i], x); en[x] = Time; } void dfs2(int x, int par) { if (intervals[x].size()) intervals[x].push_back(x); for (int i = 0; i < intervals[x].size(); i++) update(1, 1, n, st[intervals[x][i]], en[intervals[x][i]], 1); ans[x] = max(0, tree[1].nonzero - 1); for (int i = 0; i < G[x].size(); i++) if (G[x][i] != par) dfs2(G[x][i], x); for (int i = 0; i < intervals[x].size(); i++) update(1, 1, n, st[intervals[x][i]], en[intervals[x][i]], -1); } int main() { scanf( %d , &n); ; scanf( %d , &m); ; memset(tree, 0, sizeof tree); for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d , &a); ; scanf( %d , &b); ; G[a].push_back(b); G[b].push_back(a); } dfs(1, -1); while (m--) { int a, b; scanf( %d , &a); ; scanf( %d , &b); ; intervals[a].push_back(b); intervals[b].push_back(a); } dfs2(1, -1); for (int i = 1; i < n + 1; i++) printf( %d , ans[i]); cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { double n, k, m, l, a, b, f, d; cin >> n >> k; long long kek = n; double cnt1 = 0, cnt2 = 0; while (kek % 2 == 0) { kek /= 2; cnt1++; } kek = n; while (kek % 5 == 0) { kek /= 5; cnt2++; } cout.precision(0); cout << fixed; cnt1 = max(0.0, k - cnt1); cnt2 = max(0.0, k - cnt2); cout << n * pow(2, cnt1) * pow(5, cnt2); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Sep 27 18:05:24 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/dbg_ila/dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module dbg_ila(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const long double INF = 2e30; struct node { int id; long double da, db, len; node(int _id = 0, long double _da = 0, long double _db = 0, long double _len = 0) { id = _id; da = _da; db = _db; len = _len; } }; node a[maxn]; int n; double ax, ay, bx, by, tx, ty; double x[maxn], y[maxn]; long double len[maxn], da[maxn], db[maxn]; bool cmpb(node a, node b) { long double ans1 = a.db - a.len; long double ans2 = b.db - b.len; return ans1 < ans2; } bool cmpa(node a, node b) { long double ans1 = a.da - a.len; long double ans2 = b.da - b.len; return ans1 < ans2; } void solve() { long double sum = 0; for (int i = 0; i < n; i++) { a[i].id = i; long double dx, dy; dx = ax - x[i]; dy = ay - y[i]; a[i].da = sqrt(dx * dx + dy * dy); dx = bx - x[i]; dy = by - y[i]; a[i].db = sqrt(dx * dx + dy * dy); dx = tx - x[i]; dy = ty - y[i]; a[i].len = sqrt(dx * dx + dy * dy); sum += a[i].len * 2; len[i] = a[i].len; da[i] = a[i].da; db[i] = a[i].db; } long double ans = INF; sort(a, a + n, cmpb); for (int i = 0; i < n; i++) { if (n > 1) { int id = a[0].id; if (i == id) { id = a[1].id; } long double tmp = sum - len[i] + da[i] - len[id] + db[id]; ans = min(ans, tmp); } long double tmp = sum - len[i] + da[i]; ans = min(ans, tmp); } sort(a, a + n, cmpa); for (int i = 0; i < n; i++) { if (n > 1) { int id = a[0].id; if (i == id) { id = a[1].id; } long double tmp = sum - len[i] + db[i] - len[id] + da[id]; ans = min(ans, tmp); } long double tmp = sum - len[i] + db[i]; ans = min(ans, tmp); } printf( %.14f n , (double)ans); } int main() { while (scanf( %lf%lf%lf%lf%lf%lf , &ax, &ay, &bx, &by, &tx, &ty) != EOF) { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lf%lf , &x[i], &y[i]); } solve(); } return 0; }
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
MatchTemplateBin
:Function
Match a binary from template for binary images.
It will give the first output after 1 cycle while in_enable enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module MatchTemplateBin(
clk,
rst_n,
template,
in_enable,
in_data,
out_ready,
out_data);
/*
::description
This module's working mode.
::range
0 for Pipeline, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
The width(and height) of window.
::range
2 - 15
*/
parameter[3 : 0] window_width = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Reset, active low.
*/
input[window_width * window_width - 1 : 0] template;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [window_width * window_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output out_data;
reg reg_out_data;
reg reg_out_ready;
generate
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_out_ready <= 0;
end else begin
reg_out_ready <= 1;
end
end
assign out_ready = reg_out_ready;
if(work_mode == 0) begin
always @(posedge clk)
reg_out_data <= in_data == template ? 1 : 0;
end else begin
always @(posedge in_enable)
reg_out_data <= in_data == template ? 1 : 0;
end
assign out_data = out_ready ? reg_out_data : 0;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i; int a, b, c, d; vector<long long> v; long long ans; void add(int a, int b) { ans += a - b; v.push_back(a + b); } void add_stack() { if (a + b >= c + d) { add(a, b); add(c, d); return; } if (a > d) add(a - d, d - a); if (b > c) add(c - b, b - c); } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d%d%d , &a, &b, &c, &d); add_stack(); } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long sgn = 1; for (auto e : v) { ans += sgn * e; sgn *= -1; } printf( %lld , ans / 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int mod = 1e9 + 7; long long a[N], n, mx, cnt; vector<int> v, e; long long ans = 1; long long pw(long long a, long long b) { if (b == 0) return 1; long long res = pw(a, b / 2); res = res * res % mod; if (b % 2) res = res * a % mod; return res; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]), mx = max(mx, a[i]); sort(a, a + n); for (int i = 2; i <= mx; i++) { v.clear(); e.clear(); for (int j = 1; j * j <= i; j++) { if (i % j == 0) { v.push_back(j); if (j * j != i) e.push_back(i / j); } } for (int j = (int)e.size() - 1; j >= 0; j--) v.push_back(e[j]); int now = 0; long long sum = 1, sum2 = 1; for (int j = 1; j < (int)v.size(); j++) { int to = lower_bound(a + now, a + n, v[j]) - a; sum = sum * pw(j, to - now) % mod; now = to; } sum = sum * pw((int)v.size(), n - now) % mod; now = 0; for (int j = 1; j < v.size() - 1; j++) { int to = lower_bound(a + now, a + n, v[j]) - a; sum2 = sum2 * pw(j, to - now) % mod; now = to; } sum2 = sum2 * pw((int)v.size() - 1, n - now) % mod; ans = (ans + sum) % mod; ans = (ans + mod - sum2) % mod; } ans = (ans + mod) % mod; printf( %lld n , ans); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:36 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: sym_gen.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// SYM_GEN
//
//
// Description: The SYM_GEN module is a symbol generator for 2-byte Aurora Lanes.
// Its inputs request the transmission of specific symbols, and its
// outputs drive the GTP interface to fulfil those requests.
//
// All generation request inputs must be asserted exclusively
// except for the GEN_K, GEN_R and GEN_A signals from the Global
// Logic, and the GEN_PAD and TX_PE_DATA_V signals from TX_LL.
//
// GEN_K, GEN_R and GEN_A can be asserted anytime, but they are
// ignored when other signals are being asserted. This allows the
// idle generator in the Global Logic to run continuosly without
// feedback, but requires the TX_LL and Lane Init SM modules to
// be quiescent during Channel Bonding and Verification.
//
// The GEN_PAD signal is only valid while the TX_PE_DATA_V signal
// is asserted. This allows padding to be specified for the LSB of
// the data transmission. GEN_PAD must not be asserted when
// TX_PE_DATA_V is not asserted - this will generate errors.
//
//
`timescale 1 ns / 10 ps
module aurora_201_SYM_GEN
(
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
// Lane Init SM Interface
GEN_K_FSM,
GEN_SP_DATA,
GEN_SPA_DATA,
// GTP Interface
TX_CHAR_IS_K,
TX_DATA,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// TX_LL Interface // See description for info about GEN_PAD and TX_PE_DATA_V.
input GEN_SCP; // Generate SCP.
input GEN_ECP; // Generate ECP.
input GEN_PAD; // Replace LSB with Pad character.
input [0:15] TX_PE_DATA; // Data. Transmitted when TX_PE_DATA_V is asserted.
input TX_PE_DATA_V; // Transmit data.
input GEN_CC; // Generate Clock Correction symbols.
// Global Logic Interface // See description for info about GEN_K,GEN_R and GEN_A.
input GEN_A; // Generate A character for MSBYTE
input [0:1] GEN_K; // Generate K character for selected bytes.
input [0:1] GEN_R; // Generate R character for selected bytes.
input [0:1] GEN_V; // Generate Ver data character on selected bytes.
// Lane Init SM Interface
input GEN_K_FSM; // Generate K character on byte 0.
input [0:1] GEN_SP_DATA; // Generate SP data character on selected bytes.
input [0:1] GEN_SPA_DATA; // Generate SPA data character on selected bytes.
// GTP Interface
output [1:0] TX_CHAR_IS_K; // Transmit TX_DATA as a control character.
output [15:0] TX_DATA; // Data to GTP for transmission to channel partner.
// System Interface
input USER_CLK; // Clock for all non-GTP Aurora Logic.
//**************************External Register Declarations****************************
reg [15:0] TX_DATA;
reg [1:0] TX_CHAR_IS_K;
//**************************Internal Register Declarations****************************
// Slack registers. Allow slack for routing delay and automatic retiming.
reg gen_scp_r;
reg gen_ecp_r;
reg gen_pad_r;
reg [0:15] tx_pe_data_r;
reg tx_pe_data_v_r;
reg gen_cc_r;
reg gen_a_r;
reg [0:1] gen_k_r;
reg [0:1] gen_r_r;
reg [0:1] gen_v_r;
reg gen_k_fsm_r;
reg [0:1] gen_sp_data_r;
reg [0:1] gen_spa_data_r;
//*********************************Wire Declarations**********************************
wire [0:1] idle_c;
//*********************************Main Body of Code**********************************
// Register all inputs with the slack registers.
always @(posedge USER_CLK)
begin
gen_scp_r <= `DLY GEN_SCP;
gen_ecp_r <= `DLY GEN_ECP;
gen_pad_r <= `DLY GEN_PAD;
tx_pe_data_r <= `DLY TX_PE_DATA;
tx_pe_data_v_r <= `DLY TX_PE_DATA_V;
gen_cc_r <= `DLY GEN_CC;
gen_a_r <= `DLY GEN_A;
gen_k_r <= `DLY GEN_K;
gen_r_r <= `DLY GEN_R;
gen_v_r <= `DLY GEN_V;
gen_k_fsm_r <= `DLY GEN_K_FSM;
gen_sp_data_r <= `DLY GEN_SP_DATA;
gen_spa_data_r <= `DLY GEN_SPA_DATA;
end
// When none of the msb non_idle inputs are asserted, allow idle characters.
assign idle_c[0] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_k_fsm_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
// Generate data for MSB. Note that all inputs must be asserted exclusively, except
// for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
// are asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[15:8] <= `DLY 8'h5c; // K28.2(SCP)
if(gen_ecp_r) TX_DATA[15:8] <= `DLY 8'hfd; // K29.7(ECP)
if(tx_pe_data_v_r) TX_DATA[15:8] <= `DLY tx_pe_data_r[0:7]; // DATA
if(gen_cc_r) TX_DATA[15:8] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[0] & gen_a_r) TX_DATA[15:8] <= `DLY 8'h7c; // K28.3(A)
if(idle_c[0] & gen_k_r[0]) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[0] & gen_r_r[0]) TX_DATA[15:8] <= `DLY 8'h1c; // K28.0(R)
if(gen_k_fsm_r) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(gen_sp_data_r[0]) TX_DATA[15:8] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[0]) TX_DATA[15:8] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[0]) TX_DATA[15:8] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for MSB.
always @(posedge USER_CLK)
TX_CHAR_IS_K[1] <= `DLY !( tx_pe_data_v_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
// When none of the msb non_idle inputs are asserted, allow idle characters. Note that
// because gen_pad is only valid with the data valid signal, we only look at the data
// valid signal.
assign idle_c[1] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
// Generate data for LSB. Note that all inputs must be asserted exclusively except for
// the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD can be asserted
// at the same time as TX_DATA_VALID. This will override TX_DATA and replace the
// lsb user data with a PAD character. The GEN_K and GEN_R inputs are ignored
// if any other input is asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[7:0] <= `DLY 8'hfb; // K27.7(SCP)
if(gen_ecp_r) TX_DATA[7:0] <= `DLY 8'hfe; // K30.7(ECP)
if(tx_pe_data_v_r & gen_pad_r) TX_DATA[7:0] <= `DLY 8'h9c; // K28.4(PAD)
if(tx_pe_data_v_r & !gen_pad_r) TX_DATA[7:0] <= `DLY tx_pe_data_r[8:15]; // DATA
if(gen_cc_r) TX_DATA[7:0] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[1] & gen_k_r[1]) TX_DATA[7:0] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[1] & gen_r_r[1]) TX_DATA[7:0] <= `DLY 8'h1c; // K28.0(R)
if(gen_sp_data_r[1]) TX_DATA[7:0] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[1]) TX_DATA[7:0] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[1]) TX_DATA[7:0] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for LSB.
always @(posedge USER_CLK)
TX_CHAR_IS_K[0] <= `DLY !( tx_pe_data_v_r & !gen_pad_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
endmodule
|
`timescale 1ns / 1ps
module top
(
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output ddr3_ck_p,
output ddr3_ck_n,
output ddr3_cke,
output ddr3_cs_n,
output [7:0] ddr3_dm,
output ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
//output tg_compare_error,
//output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
// Wire declarations
(* MARK_DEBUG="true" *) wire app_rdy;
(* MARK_DEBUG="true" *) wire app_wdf_rdy;
(* MARK_DEBUG="true" *) wire [511:0] app_rd_data;
(* MARK_DEBUG="true" *) wire app_rd_data_valid;
(* MARK_DEBUG="true" *) wire [27:0] app_addr;
(* MARK_DEBUG="true" *) wire [2:0] app_cmd;
(* MARK_DEBUG="true" *) wire app_en;
(* MARK_DEBUG="true" *) wire [511:0] app_wdf_data;
(* MARK_DEBUG="true" *) wire app_wdf_end;
// (* MARK_DEBUG="true" *) wire [63:0] app_wdf_mask;
(* MARK_DEBUG="true" *) wire app_wdf_wren;
(* MARK_DEBUG="true" *) wire init_calib_complete;
(* MARK_DEBUG="true" *) wire rst;
reg [27:0] app_addr_a;
reg [2:0] app_cmd_a;
reg app_en_a;
reg [511:0] app_wdf_data_a;
reg app_wdf_end_a;
// reg [63:0] app_wdf_mask_a;
reg app_wdf_wren_a;
parameter START = 4'b0001;
parameter SWRITE = 4'b0010;
parameter SREAD = 4'b0100;
parameter SSTOP = 4'b1000;
(* MARK_DEBUG="true" *) reg[3:0] cstate;
always @(posedge clk or posedge sys_rst)
begin
if(sys_rst) cstate <= START;
else begin
case(cstate)
START:begin
if(init_calib_complete)
begin
if((app_wdf_rdy)&&(!app_rdy))
begin
app_en_a <= 1'b1; app_cmd_a <= 3'b000;
cstate <= SWRITE;
end
end
else cstate <= START;
end
SWRITE: begin
if((app_rdy)&&(app_wdf_rdy))
begin
app_wdf_wren_a <= 1'b1; app_wdf_end_a <= 1'b1;
app_addr_a <= 7'h0000000;
app_wdf_data_a <= 128'h508050ff;
cstate <= SREAD;
end
else if((!app_rdy) && (app_wdf_rdy))
begin
app_wdf_wren_a <= 1'b0; app_wdf_end_a <= 1'b0;
cstate <= SWRITE;
end
else
cstate <= START;
end
SREAD: begin
if(app_rdy )
begin
app_en_a <= 1'b1; app_cmd_a <= 3'b001;
app_addr_a <= 7'h0000f00;
cstate <= SSTOP;
end
else cstate <= SREAD;
end
SSTOP: cstate <= START;
default: cstate <= START;
endcase
end
end
assign app_addr = app_addr_a;
assign app_cmd = app_cmd_a;
assign app_en = app_en_a;
assign app_wdf = app_wdf_data_a;
assign app_wdf_end = app_wdf_end_a;
//assign app_wdf_mask = app_wdf_mask_a;
assign app_wdf_wren = app_wdf_wren_a;
assign rst = sys_rst;
//---------- mig instance
mig_7series_0 u_mig_7series_0 (
// Memory interface ports
.ddr3_addr (ddr3_addr), // output [13:0] ddr3_addr
.ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba
.ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n
.ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n
.ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p
.ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke
.ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n
.ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n
.ddr3_we_n (ddr3_we_n), // output ddr3_we_n
.ddr3_dq (ddr3_dq), // inout [63:0] ddr3_dq
.ddr3_dqs_n (ddr3_dqs_n), // inout [7:0] ddr3_dqs_n
.ddr3_dqs_p (ddr3_dqs_p), // inout [7:0] ddr3_dqs_p
.init_calib_complete (init_calib_complete), // output init_calib_complete
.ddr3_cs_n (ddr3_cs_n), // output [0:0] ddr3_cs_n
.ddr3_dm (ddr3_dm), // output [7:0] ddr3_dm
.ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt
// Application interface ports
.app_addr (app_addr), // input [27:0] app_addr
.app_cmd (app_cmd), // input [2:0] app_cmd
.app_en (app_en), // input app_en
.app_wdf_data (app_wdf_data), // input [511:0] app_wdf_data
.app_wdf_end (app_wdf_end), // input app_wdf_end
.app_wdf_wren (app_wdf_wren), // input app_wdf_wren
.app_rd_data (app_rd_data), // output [511:0] app_rd_data
.app_rd_data_valid (app_rd_data_valid),//output
.app_rd_data_end (), // output app_rd_data_end
.app_rdy (app_rdy), // output app_rdy
.app_wdf_rdy (app_wdf_rdy), // output app_wdf_rdy
.app_sr_req (1'b0), // input app_sr_req
.app_ref_req (1'b0), // input app_ref_req
.app_zq_req (1'b0), // input app_zq_req
.app_sr_active (), // output app_sr_active
.app_ref_ack (), // output app_ref_ack
.app_zq_ack (), // output app_zq_ack
.ui_clk (clk), // output ui_clk
.ui_clk_sync_rst (), // output ui_clk_sync_rst
.app_wdf_mask (16'h0000000000000000), // input [63:0] app_wdf_mask
// System Clock Ports
.sys_clk_p (sys_clk_p), // input sys_clk_p
.sys_clk_n (sys_clk_n), // input sys_clk_n
.sys_rst (sys_rst) // input sys_rst
);
endmodule
|
#include <bits/stdc++.h> const int M = 1000005; long long f[M]; int A[M]; int n; int Min(int a, int b) { return a < b ? a : b; } int Max(int a, int b) { return a < b ? b : a; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , A + i); long long ans = 0; A[0] = 1; for (int i = 1; i <= n; ++i) { (ans += A[i] - 1) %= 1000000007; (ans += f[i - 1] * (Min(A[i], A[i - 1]) - 1)) %= 1000000007; (f[i] += Min(A[i], A[i + 1]) - 1) %= 1000000007; (f[i] += Max(0, Min(Min(A[i], A[i - 1]), A[i + 1]) - 1) * f[i - 1]) %= 1000000007; } printf( %lld n , (ans + 1000000007) % 1000000007); return 0; }
|
//
// Copyright (c) 2002 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic expression assign with add
//
//
module adder (q,a,b );
input a,b;
output [1:0] q;
assign q = a + b;
endmodule
module test ;
reg d;
wire [1:0] q;
adder u_add (.q(q),.a(d),.b(d));
(* ivl_synthesis_off *)
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
d = 0;
# 1;
if (q !== 2'b0)
begin
$display("FAILED - Q isn't 0 ");
$finish;
end
#1 ;
d = 1;
# 1;
if (q !== 2'b10)
begin
$display("FAILED - Q isn't 2 ");
$finish;
end
$display("PASSED");
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../common/fpga_regs_common.v"
`include "../common/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2));
bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_2 : io_2_oe
<= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_3 : io_3_oe
<= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:42 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, t[200100], ll, rr, sum; double inv, res, f[200100], g[200100]; inline double calc(long long l, long long r) { while (ll > l) { --ll; inv += 1.0 / t[ll]; sum += t[ll]; res += inv * t[ll]; } while (rr < r) { ++rr; inv += 1.0 / t[rr]; sum += t[rr]; res += 1.0 * sum / t[rr]; } while (ll < l) { res -= inv * t[ll]; sum -= t[ll]; inv -= 1.0 / t[ll]; ll++; } while (rr > r) { res -= 1.0 * sum / t[rr]; sum -= t[rr]; inv -= 1.0 / t[rr]; rr--; } return res; } inline void func(long long l, long long r, long long L, long long R) { if (l > r || L > R) return; register long long mid = (l + r) >> 1; register long long mp; register double mn = 9e18; for (register long long i = L; i <= R; i++) if (f[i] + calc(i + 1, mid) < mn) mn = f[i] + calc(i + 1, mid), mp = i; g[mid] = mn; func(l, mid - 1, L, mp), func(mid + 1, r, mp, R); } inline void read(long long &x) { x = 0; register char c = getchar(); while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); } signed main() { read(n), read(m); for (register long long i = 1; i <= n; i++) read(t[i]), inv += 1.0 / t[i], sum += t[i], res += 1.0 * sum / t[i], f[i] = res; ll = 1, rr = n; while (--m) func(1, n, 0, n - 1), memcpy(f, g, sizeof(g)); printf( %lf n , f[n]); return 0; }
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