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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 4; void solve() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; float min = 4.5 * n; int mn = (int)min; if (min - mn > 0) mn++; int sum = 0; for (int i = 0; i < n; i++) sum += arr[i]; int req = mn - sum; if (req <= 0) { cout << 0 << endl; return; } sort(arr, arr + n); int ans = 0, i = 0; while (req > 0) { req -= 5 - arr[i]; i++; ans++; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int RNG = 1000003; const int RNGT = RNG * 4; const int MOD1 = 1e9 + 7; const int MOD2 = 1e9 + 87; const double pi = 2 * acos(0.0); inline int _Int() { int x; scanf( %d , &x); return x; } inline long long _LLi() { long long x; scanf( %lld , &x); return x; } void pruts() { puts( -1 ); exit(EXIT_SUCCESS); } int dirX[] = {1, 0, -1, 0, 1, -1, 1, -1}; int dirY[] = {0, 1, 0, -1, 1, -1, -1, 1}; int rX[] = {1, 1, 2, 2, -1, -1, -2, -2}; int rY[] = {2, -2, 1, -1, 2, -2, 1, -1}; template <class T> T tri_Area(T x1, T y1, T x2, T y2, T x3, T y3) { return abs(x1 * (y2 - y3) - y1 * (x2 - x3) + (x2 * y3 - x3 * y2)); }; template <class T> T Distance(T x1, T y1, T x2, T y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); }; template <class T> T bigMod(T n, T p, T m) { if (p == 0) return 1; if (p & 1) return (n * bigMod(n, p - 1, m)) % m; T x = bigMod(n, p / 2, m); return (x * x) % m; }; int Case; int sset(int N, int pos) { return N = N | (1 << pos); } bool check(int N, int pos) { return (bool)(N & (1 << pos)); } int reset(int N, int pos) { return N = N & ~(1 << pos); } int A[RNG], n, m, flag; string str[600]; void Hunger() { n = _Int(); m = _Int(); for (int i = 0; i < n; i++) cin >> str[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (str[i][j] == W ) { int x = i + 1; if (x < n && x >= 0) { if (str[x][j] == . ) str[x][j] = D ; if (str[x][j] == S ) { cout << No << endl; return; } } x = i - 1; if (x < n && x >= 0) { if (str[x][j] == . ) str[x][j] = D ; if (str[x][j] == S ) { cout << No << endl; return; } } x = j + 1; if (x < m && x >= 0) { if (str[i][x] == . ) str[i][x] = D ; if (str[i][x] == S ) { cout << No << endl; return; } } x = j - 1; if (x < m && x >= 0) { if (str[i][x] == . ) str[i][x] = D ; if (str[i][x] == S ) { cout << No << endl; return; } } } } } cout << Yes << endl; for (int i = 0; i < n; i++) cout << str[i] << endl; } int main() { Hunger(); return 0; }
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/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LFSR PRBS generator
*/
module lfsr_prbs_gen #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// Initial state
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}},
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// bit-reverse input and output
parameter REVERSE = 0,
// invert output
parameter INVERT = 1,
// width of data output
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire clk,
input wire rst,
input wire enable,
output wire [DATA_WIDTH-1:0] data_out
);
/*
Fully parametrizable combinatorial parallel LFSR PRBS module. Implements an unrolled LFSR
next state computation.
Ports:
clk
Clock input
rst
Reset input, set state to LFSR_INIT
enable
Generate new output data
data_out
LFSR output (DATA_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_INIT
Initial state of LFSR. Defaults to all 1s.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR output. Shifts MSB first by default, set REVERSE for LSB first.
INVERT
Bitwise invert PRBS output.
DATA_WIDTH
Specify width of output data bus.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT;
reg [DATA_WIDTH-1:0] output_reg = 0;
wire [DATA_WIDTH-1:0] lfsr_data;
wire [LFSR_WIDTH-1:0] lfsr_state;
assign data_out = output_reg;
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(0),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
lfsr_inst (
.data_in({DATA_WIDTH{1'b0}}),
.state_in(state_reg),
.data_out(lfsr_data),
.state_out(lfsr_state)
);
always @* begin
if (INVERT) begin
output_reg <= ~lfsr_data;
end else begin
output_reg <= lfsr_data;
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= LFSR_INIT;
end else begin
if (enable) begin
state_reg <= lfsr_state;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b, h[20], f[20][20][20][20], g[20][20][20][20][5]; void update(int &f1, int f2, int p[5], int i, int j, int k, int l, int w) { if (f2 < f1) { f1 = f2; p[0] = w; p[1] = i; p[2] = j; p[3] = k; p[4] = l; } } int main() { cin >> n >> a >> b; memset(h, 0, sizeof h); for (int i = 0; i < n; i++) { scanf( %d , h + i); h[i]++; } memset(f, 0x3f, sizeof f); f[1][h[0]][h[1]][h[2]] = 0; memset(g, 0xff, sizeof g); for (int i = 1; i < n; i++) { for (int j = 16; j >= 0; j--) { for (int k = 16; k >= 0; k--) for (int l = 16; l >= 0; l--) { if (j == 0) update(f[i + 1][k][l][h[i + 2]], f[i][j][k][l], g[i + 1][k][l][h[i + 2]], g[i][j][k][l][1], g[i][j][k][l][2], g[i][j][k][l][3], g[i][j][k][l][4], g[i][j][k][l][0]); if (i != n - 1) { int j1 = j - b > 0 ? j - b : 0, k1 = k - a > 0 ? k - a : 0, l1 = l - b > 0 ? l - b : 0; if (j <= b) update(f[i + 1][k1][l1][h[i + 2]], f[i][j][k][l] + 1, g[i + 1][k1][l1][h[i + 2]], i, j, k, l, i); update(f[i][j1][k1][l1], f[i][j][k][l] + 1, g[i][j1][k1][l1], i, j, k, l, i); } if (i != 1) { int j1 = j - a > 0 ? j - a : 0, k1 = k - b > 0 ? k - b : 0; if (j <= a) update(f[i + 1][k1][l][h[i + 2]], f[i][j][k][l] + 1, g[i + 1][k1][l][h[i + 2]], i, j, k, l, i - 1); update(f[i][j1][k1][l], f[i][j][k][l] + 1, g[i][j1][k1][l], i, j, k, l, i - 1); } } } } cout << f[n - 1][0][0][0] << endl; int i = n - 1, j = 0, k = 0, l = 0; while (i != -1) { if (g[i][j][k][l][0] == -1) break; printf( %d , g[i][j][k][l][0] + 1); int i1 = g[i][j][k][l][1], j1 = g[i][j][k][l][2], k1 = g[i][j][k][l][3], l1 = g[i][j][k][l][4]; i = i1, j = j1, k = k1, l = l1; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_2_V
`define SKY130_FD_SC_MS__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_2_V
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sd_mgr (
input wire clk_50,
input wire reset_n,
input wire bram_rd_sd_clk,
input wire [6:0] bram_rd_sd_addr,
input wire bram_rd_sd_wren,
input wire [31:0] bram_rd_sd_data,
output wire [31:0] bram_rd_sd_q,
input wire bram_rd_ext_clk,
input wire [6:0] bram_rd_ext_addr,
input wire bram_rd_ext_wren,
input wire [31:0] bram_rd_ext_data,
output wire [31:0] bram_rd_ext_q,
input wire bram_wr_sd_clk,
input wire [6:0] bram_wr_sd_addr,
input wire bram_wr_sd_wren,
input wire [31:0] bram_wr_sd_data,
output wire [31:0] bram_wr_sd_q,
input wire bram_wr_ext_clk,
input wire [6:0] bram_wr_ext_addr,
input wire bram_wr_ext_wren,
input wire [31:0] bram_wr_ext_data,
output wire [31:0] bram_wr_ext_q,
input wire link_read_act,
output reg link_read_go,
input wire [31:0] link_read_addr,
input wire [31:0] link_read_num,
input wire link_read_stop,
input wire link_write_act,
output reg link_write_done,
input wire [31:0] link_write_addr,
input wire [31:0] link_write_num,
output reg ext_read_act,
input wire ext_read_go,
output reg [31:0] ext_read_addr,
output reg [31:0] ext_read_num,
output reg ext_read_stop,
output reg ext_write_act,
input wire ext_write_done,
output reg [31:0] ext_write_addr,
output reg [31:0] ext_write_num
);
reg [31:0] link_read_addr_latch;
reg [15:0] dc;
reg [4:0] state;
parameter [4:0] ST_RESET = 'd0,
ST_IDLE = 'd4,
ST_BREAD_0 = 'd5,
ST_BREAD_1 = 'd6,
ST_BREAD_2 = 'd7,
ST_BREAD_3 = 'd8,
ST_BREAD_4 = 'd9,
ST_BREAD_5 = 'd10,
ST_BWRITE_0 = 'd13,
ST_BWRITE_1 = 'd14,
ST_BWRITE_2 = 'd15,
ST_BWRITE_3 = 'd16,
ST_BWRITE_4 = 'd17,
ST_BWRITE_5 = 'd18,
ST_LAST = 'd31;
wire reset_s;
wire ext_read_go_s, ext_read_go_r;
wire ext_write_done_s, ext_write_done_r;
synch_3 a(reset_n, reset_s, clk_50);
synch_3 b(ext_read_go, ext_read_go_s, clk_50, ext_read_go_r);
synch_3 c(ext_write_done, ext_write_done_s, clk_50, ext_write_done_r);
always @(posedge clk_50) begin
// free running counter
dc <= dc + 1'b1;
link_write_done <= 0;
case(state)
ST_RESET: begin
ext_read_act <= 0;
ext_read_stop <= 0;
ext_write_act <= 0;
sel_rd_sd <= 0;
sel_rd_ext <= 0;
buf_rd_a_full <= 0;
buf_rd_b_full <= 0;
sel_wr_sd <= 0;
sel_wr_ext <= 0;
link_read_go <= 0;
state <= ST_IDLE;
end
ST_IDLE: begin
dc <= 0;
if(link_read_act) begin
ext_read_addr <= link_read_addr;
link_read_addr_latch <= link_read_addr;
//ext_read_num <= link_read_num;
ext_read_stop <= 0;
state <= ST_BREAD_0;
end else
if(link_write_act) begin
ext_write_addr <= link_write_addr;
//ext_write_num <= link_write_num;
state <= ST_BWRITE_0;
end
end
ST_BREAD_0: begin
// 1. check if desired block was already cached in the next read slot
// 2. if it is, immediately let the SD have it, otherwise stall until it's ready
// 3. then start another read to preload the next block in the sequence
if( (sel_rd_sd ? {buf_rd_b_block, buf_rd_b_full} :
{buf_rd_a_block, buf_rd_a_full}) == {ext_read_addr, 1'b1} ) begin
// selected buffer has the data already
link_read_go <= 1;
// swap wishbone pointer to the next slot
sel_rd_ext <= ~sel_rd_ext;
state <= ST_BREAD_3;
end else begin
// not in next buffer
state <= ST_BREAD_1;
end
dc <= 0;
end
ST_BREAD_1: begin
// load block if one is not cached
case(sel_rd_ext)
0: buf_rd_a_block <= link_read_addr_latch;
1: buf_rd_b_block <= link_read_addr_latch;
endcase
// signal to external (wishbone) to start a block read
ext_read_act <= 1;
if(ext_read_go_r ) begin
ext_read_act <= 0;
ext_read_stop <= 1;
// tell link to start pushing data to SD
link_read_go <= 1;
case(sel_rd_ext)
0: buf_rd_a_full <= 1;
1: buf_rd_b_full <= 1;
endcase
// swap wishbone pointer to the next slot
sel_rd_ext <= ~sel_rd_ext;
state <= ST_BREAD_2;
end
end
ST_BREAD_2: begin
if(~ext_read_go) begin
ext_read_stop <= 0;
state <= ST_BREAD_3;
end
dc <= 0;
end
ST_BREAD_3: begin
// preload next block
case(sel_rd_ext)
0: buf_rd_a_block <= link_read_addr_latch + 1;
1: buf_rd_b_block <= link_read_addr_latch + 1;
endcase
// signal to external (wishbone) to start a block read
ext_read_addr <= link_read_addr_latch + 1;
ext_read_act <= 1;
if(ext_read_go_r) begin
// data is valid
ext_read_act <= 0;
ext_read_stop <= 1;
case(sel_rd_ext)
0: buf_rd_a_full <= 1;
1: buf_rd_b_full <= 1;
endcase
state <= ST_BREAD_4;
end
end
ST_BREAD_4: begin
if(~ext_read_go) begin
ext_read_stop <= 0;
state <= ST_BREAD_5;
end
end
ST_BREAD_5: begin
// wait for SD to stop sending
if(link_read_stop) begin
// finished, or interrupted
case(sel_rd_sd)
0: buf_rd_a_full <= 0;
1: buf_rd_b_full <= 0;
endcase
link_read_go <= 0;
state <= ST_IDLE;
// swap buffers
sel_rd_sd <= ~sel_rd_sd;
end
end
ST_BWRITE_0: begin
// 1. immediately flush loaded data to wishbone ext
// 2. accept new data from SD after swapping buffers
// 3. stall done until WB write is finished
// signal to external (wishbone) to start a block write
ext_write_act <= 1;
if(~ext_write_done) begin
// wait for done to fall to be able to detect the rising/risen edge later
sel_wr_sd <= ~sel_wr_sd;
state <= ST_BWRITE_1;
end
end
ST_BWRITE_1: begin
// tell SD we can accept another block
link_write_done <= 1;
// SD may dump another load, we won't service it until the FSM returns to idle and notices
if(~link_write_act) begin
state <= ST_BWRITE_2;
end else
if(ext_write_done) begin
// external has written the buffer, tell link
sel_wr_ext <= ~sel_wr_ext;
ext_write_act <= 0;
state <= ST_BWRITE_3;
end
end
ST_BWRITE_2: begin
if(ext_write_done) begin
// external has written the buffer, tell link
sel_wr_ext <= ~sel_wr_ext;
ext_write_act <= 0;
state <= ST_BWRITE_3;
end
end
ST_BWRITE_3: begin
// invalidate read cache
buf_rd_a_full <= 0;
buf_rd_b_full <= 0;
state <= ST_IDLE;
end
endcase
if(~reset_s) begin
state <= ST_RESET;
end
end
reg sel_rd_sd;
reg sel_rd_ext;
reg buf_rd_a_full;
reg buf_rd_b_full;
reg [31:0] buf_rd_a_block;
reg [31:0] buf_rd_b_block;
// address two sector buffers inside the bram
wire [7:0] bram_rd_sd_addr_sel = (sel_rd_sd ? bram_rd_sd_addr + 8'd128 : bram_rd_sd_addr) /* synthesis keep */;
wire [7:0] bram_rd_ext_addr_sel = (sel_rd_ext ? bram_rd_ext_addr + 8'd128 : bram_rd_ext_addr) /* synthesis keep */;
// 512 byte bram (2 x 128 x 32bit word)
sd_bram_block_dp #(32, 8) isdb1 (
.a_clk ( bram_rd_sd_clk ),
.a_wr ( bram_rd_sd_wren ),
.a_addr ( bram_rd_sd_addr_sel ),
.a_din ( bram_rd_sd_data ),
.a_dout ( bram_rd_sd_q ),
.b_clk ( bram_rd_ext_clk ),
.b_wr ( bram_rd_ext_wren ),
.b_addr ( bram_rd_ext_addr_sel ),
.b_din ( bram_rd_ext_data ),
.b_dout ( bram_rd_ext_q )
);
reg sel_wr_sd;
reg sel_wr_ext;
// address two sector buffers inside the bram
wire [7:0] bram_wr_sd_addr_sel = (sel_wr_sd ? bram_wr_sd_addr + 8'd128 : bram_wr_sd_addr) /* synthesis keep */;
wire [7:0] bram_wr_ext_addr_sel = (sel_wr_ext ? bram_wr_ext_addr + 8'd128 : bram_wr_ext_addr) /* synthesis keep */;
// 512 byte bram (2 x 128 x 32bit word)
sd_bram_block_dp #(32, 8) isdb2 (
.a_clk ( bram_wr_sd_clk ),
.a_wr ( bram_wr_sd_wren ),
.a_addr ( bram_wr_sd_addr_sel ),
.a_din ( bram_wr_sd_data ),
.a_dout ( bram_wr_sd_q ),
.b_clk ( bram_wr_ext_clk ),
.b_wr ( bram_wr_ext_wren ),
.b_addr ( bram_wr_ext_addr_sel ),
.b_din ( bram_wr_ext_data ),
.b_dout ( bram_wr_ext_q )
);
endmodule
|
//Componentes varios
//Banco de registros de dos salidas y una entrada
module regfile(input wire clk,
input wire we3, //se�al de habilitaci�n de escritura
input wire [3:0] ra1, ra2, wa3, //direcciones de regs leidos y reg a escribir
input wire [7:0] wd3, //dato a escribir
output wire [7:0] rd1, rd2); //datos leidos
reg [7:0] regb[0:15]; //memoria de 16 registros de 8 bits de ancho
// El registro 0 siempre es cero
// se leen dos reg combinacionalmente
// y la escritura del tercero ocurre en flanco de subida del reloj
always @(posedge clk)
if (we3) regb[wa3] <= wd3;
assign rd1 = (ra1 != 0) ? regb[ra1] : 8'b00000000;
assign rd2 = (ra2 != 0) ? regb[ra2] : 8'b00000000;
endmodule
//modulo sumador
module sum(input wire [9:0] a, b,
output wire [9:0] y);
assign y = a + b;
endmodule
//modulo de registro para modelar el PC, cambia en cada flanco de subida de reloj o de reset
module registro #(parameter WIDTH = 8)
(input wire clk, reset,
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
module retorno_reg #(parameter WIDTH = 10)
(input wire swe, reset,
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge swe, posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
// module retorno_reg #(parameter WIDTH = 10)
// (input wire push, pop, reset,
// input wire [WIDTH-1:0] d,
// output reg [WIDTH-1:0] q);
// always @(posedge swe, posedge reset)
// if (reset) q <= 0;
// else q <= d;
// endmodule
//modulo multiplexor, cos s=1 sale d1, s=0 sale d0
module mux1 #(parameter WIDTH = 10)
(input wire [WIDTH-1:0] d0, d1,
input wire s,
output wire [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
//modulo multiplexor, cos s=1 sale d1, s=0 sale d0
module mux2 #(parameter WIDTH = 8)
(input wire [WIDTH-1:0] d0, d1,
input wire s,
output wire [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
/// ENTRADA/SALIDA
//modulo de registro activable de E/S
module reg_e #(parameter WIDTH = 8)
(input wire clk, reset, rwe,
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
//$display("******: %d", d);
always @(posedge clk, posedge reset)
// always @(*)
if (reset) q <= 0;
else if (rwe) q <= d;
endmodule
//modulo multiplexor de entrada 4-1 al MicroC
module mux_in #(parameter WIDTH = 8)
(input wire [WIDTH-1:0] d0, d1, d2, d3,
input wire [1:0] s,
output wire [WIDTH-1:0] y);
reg [7:0] aux;
always @(d0,d1,d2,d3,s)
begin
case (s)
2'b00: aux = d0;
2'b01: aux = d1;
2'b10: aux = d2;
2'b11: aux = d3;
default: aux = 8'bxxxxxxxx; //desconocido en cualquier otro caso (x � z), por si se modifica el c�digo
endcase
end
assign y = aux;
endmodule
//modulo multiplexor de entrada 2-4 del MicroC
module mux_out #(parameter WIDTH = 8)
(input wire [WIDTH-1:0] e0, e1,
input wire s, enable,
input wire [1:0] reg_,
output reg [WIDTH-1:0] d0, d1, d2, d3 );
// wire [7:0] aux;
// assign aux = s ? e1 : e0;
// always @(reg_,aux)
// always @(posedge enable)
// begin
// if (enable)
// begin
// case (reg_)
// 2'b00: d0 = (s) ? e1 : e0;
// 2'b01: d1 = (s) ? e1 : e0;
// 2'b10: d2 = (s) ? e1 : e0;
// 2'b11: d3 = (s) ? e1 : e0;
// endcase
// end
// end
wire [7:0] aux;
assign aux = s ? e1 : e0;
always @(reg_,aux)
begin
case (reg_)
2'b00: d0 = aux;
2'b01: d1 = aux;
2'b10: d2 = aux;
2'b11: d3 = aux;
//default: d0 = 'bx; d1 = 'bx; d2 = 'bx; d3 = 'bx;//desconocido en cualquier otro caso (x � z), por si se modifica el c�digo
endcase
end
endmodule
|
/**
* Copyright 2014 Kevin Townsend
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module std_fifo(rst, clk, push, pop, d, q, full, empty, count, almost_empty, almost_full);
parameter WIDTH = 8;
parameter DEPTH = 6;
parameter DEPTH_ADDR_WIDTH = log2(DEPTH-1);
parameter ALMOST_EMPTY_COUNT = 1;
parameter ALMOST_FULL_COUNT = 1;
input rst;
input clk;
input push;
input pop;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output full;
output empty;
output [DEPTH_ADDR_WIDTH:0]count;
output almost_empty;
output almost_full;
reg [WIDTH-1:0] r_q;
reg [DEPTH_ADDR_WIDTH:0] r_end;
reg [DEPTH_ADDR_WIDTH:0] r_beg;
reg [WIDTH-1:0] ram [DEPTH-1:0];
always @(posedge clk) begin
if(rst) begin
r_end <= 0;
r_beg <= 0;
end else begin
r_q <= ram[r_end[DEPTH_ADDR_WIDTH-1:0]];
if(pop)
r_end <= r_end + 1;
if(push) begin
r_beg <= r_beg + 1;
ram[r_beg[DEPTH_ADDR_WIDTH-1:0]] <= d;
end
end
end
assign q = r_q;
assign empty = (r_end == r_beg);
assign full = (r_end[DEPTH_ADDR_WIDTH-1:0] == r_beg[DEPTH_ADDR_WIDTH-1:0]) && (r_end[DEPTH_ADDR_WIDTH] != r_beg[DEPTH_ADDR_WIDTH]);
assign count = r_beg - r_end;
assign almost_empty = (count < (1+ALMOST_EMPTY_COUNT));
assign almost_full = (count > (DEPTH-1-ALMOST_FULL_COUNT));
always @(posedge clk) begin
if(full && push) begin
$display("ERROR: %d Overflow at %m", $time);
$finish;
end
if(empty && pop) begin
$display("ERROR: %d underflow at %m", $time);
$finish;
end
end
`include "log2.vh"
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); long long a[100001]; long long y = 0; long long thissum = 0, maxsum = 0; int count = 1; for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); y += a[i]; } thissum = a[0]; maxsum = a[0]; int temp = 1; for (int i = 1; i < n; i++) { if (thissum > 0) { thissum += a[i]; temp++; } else { thissum = a[i]; temp = 1; } if (thissum > maxsum) { maxsum = thissum; count = temp; } } int flag; if (y > maxsum) { flag = 1; } else { if (y == maxsum && count == n) { maxsum = maxsum - min(a[0], a[n - 1]); if (y > maxsum) { flag = 1; } else { flag = 0; } } else { flag = 0; } } if (flag == 1) { printf( YES n ); } else { printf( NO n ); } } return 0; }
|
module parser(
input clk,
input reset,
input ip_src_valid,
input [130:0] ip_src,
input cdp2um_data_valid,
input [138:0] cdp2um_data,
output um2cdp_tx_enable,
output um2cdp_path,
output pkt_ctl_valid, //contorl
output [138:0] pkt_ctl,
input [7:0] pkt_ctl_usedw,
output pkt_metadata_cut_out_valid,
output [359:0] pkt_metadata_cut_out,
output [138:0] pkt_cut_data,
output pkt_cut_data_valid,
input [7:0] pkt_cut_data_usedw,
output pkt_metadata_nocut_out_valid,
output [359:0] pkt_metadata_nocut_out,
output [138:0] pkt_nocut_data,
output pkt_nocut_data_valid,
input [7:0] pkt_nocut_data_usedw);
wire buf_addr_full;
wire pkt_head_valid;
wire [138:0] pkt_head;
wire pkt_payload_valid;
wire [138:0] pkt_payload;
wire pkt_metadata_valid;
wire [359:0] pkt_metadata; //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
parser_h parser_h(
.ip_src_valid (ip_src_valid),
.ip_src (ip_src),
.clk (clk),
.reset (reset),
.buf_addr_full (buf_addr_full),
.cdp2um_data_valid (cdp2um_data_valid),
.cdp2um_data (cdp2um_data),
.um2cdp_tx_enable (um2cdp_tx_enable),
.um2cdp_path (um2cdp_path),
.pkt_head_valid (pkt_head_valid),
.pkt_head (pkt_head),
.pkt_payload_valid (pkt_payload_valid),
.pkt_payload (pkt_payload),
.pkt_metadata_valid (pkt_metadata_valid),
.pkt_metadata (pkt_metadata)); //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
parse_pkt_disp parse_pkt_disp(
.clk (clk),
.reset (reset),
.pkt_head_valid (pkt_head_valid),
.pkt_head (pkt_head),
.pkt_payload_valid (pkt_payload_valid),
.pkt_payload (pkt_payload),
.pkt_metadata_valid (pkt_metadata_valid),
.pkt_metadata (pkt_metadata), //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
.pkt_ctl_valid (pkt_ctl_valid), //contorl
.pkt_ctl (pkt_ctl),
.pkt_ctl_usedw (pkt_ctl_usedw),
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw),
.buf_addr_full (buf_addr_full));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__MUX4_PP_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux4 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
input A2 ,
input A3 ,
output X ,
//# {{control|Control Signals}}
input S0 ,
input S1 ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ii = pair<int, int>; using vi = vector<int>; using vb = vector<bool>; using vvi = vector<vi>; using vii = vector<ii>; using vvii = vector<vii>; const int INF = 2000000000; const ll LLINF = 9000000000000000000; struct T { ld mat[2][2]; ld dx = 0, dy = 0; T() { for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) mat[i][j] = i == j; } T(const T &o) { for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) mat[i][j] = o.mat[i][j]; dx = o.dx; dy = o.dy; } }; T op(T l, T r) { T m; m.mat[0][0] = l.mat[0][0] * r.mat[0][0] + l.mat[0][1] * r.mat[1][0]; m.mat[0][1] = l.mat[0][0] * r.mat[0][1] + l.mat[0][1] * r.mat[1][1]; m.mat[1][0] = l.mat[1][0] * r.mat[0][0] + l.mat[1][1] * r.mat[1][0]; m.mat[1][1] = l.mat[1][0] * r.mat[0][1] + l.mat[1][1] * r.mat[1][1]; m.dx = l.mat[0][0] * r.dx + l.mat[0][1] * r.dy + l.dx; m.dy = l.mat[1][0] * r.dx + l.mat[1][1] * r.dy + l.dy; return m; } T ident; struct SegmentTree { struct Node { T val; int l, r; Node(T _val, int _l, int _r) : val(_val), l(_l), r(_r){}; }; int n; vector<Node> tree; SegmentTree(int p, vector<T> &init) : n(1 << p) { tree.assign(2 * n, Node(ident, 0, n - 1)); for (int j = 1; j < n; ++j) { int m = (tree[j].l + tree[j].r) / 2; tree[2 * j].l = tree[j].l; tree[2 * j].r = m; tree[2 * j + 1].l = m + 1; tree[2 * j + 1].r = tree[j].r; } for (int j = 2 * n - 1; j > 0; --j) { if (j >= n) tree[j].val = init[j - n]; else tree[j].val = op(tree[2 * j].val, tree[2 * j + 1].val); } } void update(int i, T val) { for (tree[i + n].val = val, i = (i + n) / 2; i > 0; i /= 2) tree[i].val = op(tree[2 * i].val, tree[2 * i + 1].val); } T query(int l, int r) { T lhs, rhs; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) lhs = op(lhs, tree[l++].val); if (!(r & 1)) rhs = op(tree[r--].val, rhs); } return op(l == r ? op(lhs, tree[l].val) : lhs, rhs); } }; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; int p = 1; while ((1 << p) < 2 * n) ++p; vector<T> init(1 << p, T()); for (int i = 0; i < n; ++i) { init[2 * i + 1].dx = 1; } SegmentTree st(p, init); vector<ld> curdeg(n, 0.0); while (m--) { int x, y, z; cin >> x >> y >> z; --y; if (x == 1) { T cur = st.query(2 * y + 1, 2 * y + 1); cur.dx += z; st.update(2 * y + 1, cur); } else { curdeg[y] -= ld(z) / 180.0 * 3.14159265358979323846; T m; m.mat[0][0] = m.mat[1][1] = cos(curdeg[y]); m.mat[1][0] = sin(curdeg[y]); m.mat[0][1] = -m.mat[1][0]; st.update(2 * y, m); } T f = st.query(0, 2 * n - 1); printf( %.7lf %.7lf n , double(f.dx), double(f.dy)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long n, k; cin >> n >> k; unsigned long long r = 1, l = 0, num = n, mid; for (int i = 0; i < n; i++) { r <<= 1; } mid = (l + r) >> 1; while (mid != k) { --num; if (mid > k) r = mid; else l = mid; mid = (l + r) >> 1; } cout << num; return 0; }
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:51:15 2016
/////////////////////////////////////////////////////////////
module LOAGDA_St_N16_M4_P4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_24_CI, intadd_24_n4, intadd_24_n3, intadd_24_n2, intadd_25_CI,
intadd_25_n3, intadd_25_n2, intadd_25_n1, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47;
CMPR32X2TS intadd_24_U5 ( .A(in1[12]), .B(in2[12]), .C(intadd_24_CI), .CO(
intadd_24_n4), .S(res[12]) );
CMPR32X2TS intadd_24_U4 ( .A(in1[13]), .B(in2[13]), .C(intadd_24_n4), .CO(
intadd_24_n3), .S(res[13]) );
CMPR32X2TS intadd_24_U3 ( .A(in1[14]), .B(in2[14]), .C(intadd_24_n3), .CO(
intadd_24_n2), .S(res[14]) );
CMPR32X2TS intadd_24_U2 ( .A(in1[15]), .B(in2[15]), .C(intadd_24_n2), .CO(
res[16]), .S(res[15]) );
CMPR32X2TS intadd_25_U3 ( .A(in2[9]), .B(in1[9]), .C(intadd_25_n3), .CO(
intadd_25_n2), .S(res[9]) );
ADDFX1TS intadd_25_U4 ( .A(in1[8]), .B(in2[8]), .CI(intadd_25_CI), .CO(
intadd_25_n3), .S(res[8]) );
ADDFX1TS intadd_25_U2 ( .A(in2[10]), .B(in1[10]), .CI(intadd_25_n2), .CO(
intadd_25_n1), .S(res[10]) );
AO22X1TS U39 ( .A0(in1[7]), .A1(in2[7]), .B0(n37), .B1(n32), .Y(intadd_25_CI) );
XOR2X1TS U40 ( .A(intadd_25_n1), .B(n29), .Y(res[11]) );
NOR2X2TS U41 ( .A(in2[6]), .B(in1[6]), .Y(n47) );
NAND3XLTS U42 ( .A(res[1]), .B(res[2]), .C(n33), .Y(n34) );
AO22XLTS U43 ( .A0(in1[1]), .A1(in2[1]), .B0(in1[0]), .B1(in2[0]), .Y(n33)
);
XOR2XLTS U44 ( .A(n47), .B(n46), .Y(res[6]) );
OAI2BB2XLTS U45 ( .B0(n47), .B1(n31), .A0N(in2[6]), .A1N(in1[6]), .Y(n32) );
XOR2XLTS U46 ( .A(in2[11]), .B(in1[11]), .Y(n29) );
OAI31X1TS U47 ( .A0(n47), .A1(n37), .A2(n46), .B0(n36), .Y(res[7]) );
OAI21X2TS U48 ( .A0(in1[5]), .A1(in2[5]), .B0(n45), .Y(n46) );
OAI2BB2X1TS U49 ( .B0(n39), .B1(n38), .A0N(in2[10]), .A1N(in1[10]), .Y(n41)
);
AOI2BB1X2TS U50 ( .A0N(in1[4]), .A1N(in2[4]), .B0(n42), .Y(n45) );
OR2X1TS U51 ( .A(in1[7]), .B(in2[7]), .Y(n37) );
OR2X1TS U52 ( .A(in1[5]), .B(in2[5]), .Y(n44) );
AND3X1TS U53 ( .A(in1[4]), .B(in2[4]), .C(n44), .Y(n30) );
AOI21X1TS U54 ( .A0(in2[5]), .A1(in1[5]), .B0(n30), .Y(n31) );
OR2X1TS U55 ( .A(in1[0]), .B(in2[0]), .Y(res[0]) );
OR2X1TS U56 ( .A(in1[1]), .B(in2[1]), .Y(res[1]) );
OR2X1TS U57 ( .A(in2[2]), .B(in1[2]), .Y(res[2]) );
OR2X1TS U58 ( .A(in1[3]), .B(in2[3]), .Y(res[3]) );
AOI22X1TS U59 ( .A0(in1[3]), .A1(in2[3]), .B0(in2[2]), .B1(in1[2]), .Y(n35)
);
OAI2BB1X1TS U60 ( .A0N(n35), .A1N(n34), .B0(res[3]), .Y(n42) );
OAI21XLTS U61 ( .A0(n47), .A1(n46), .B0(n37), .Y(n36) );
AOI22X1TS U62 ( .A0(in2[9]), .A1(in1[9]), .B0(in1[8]), .B1(in2[8]), .Y(n39)
);
OAI22X1TS U63 ( .A0(in2[10]), .A1(in1[10]), .B0(in2[9]), .B1(in1[9]), .Y(n38) );
OAI21XLTS U64 ( .A0(n41), .A1(in1[11]), .B0(in2[11]), .Y(n40) );
OAI2BB1X1TS U65 ( .A0N(in1[11]), .A1N(n41), .B0(n40), .Y(intadd_24_CI) );
NOR2XLTS U66 ( .A(in1[4]), .B(in2[4]), .Y(n43) );
AOI21X1TS U67 ( .A0(n43), .A1(n42), .B0(n45), .Y(res[4]) );
OA21XLTS U68 ( .A0(n45), .A1(n44), .B0(n46), .Y(res[5]) );
initial $sdf_annotate("LOAGDA_St_N16_M4_P4_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; int ucln(int k, int l) { int t; while (l > 0) { t = l; l = k % l; k = t; } return (k); } int main() { int x, y, m, n, a, b; cin >> n >> m >> x >> y >> a >> b; int u = ucln(a, b); a /= u; b /= u; int na, nb; if ((n / a) < (m / b)) { na = a * (n / a); nb = b * (n / a); } else { na = a * (m / b); nb = b * (m / b); } int x1, x2, y1, y2; x2 = x + na / 2; x1 = x2 - na; if (x1 < 0) { x2 -= x1; x1 = 0; } if (x2 > n) { x1 -= (x2 - n); x2 = n; } y2 = y + nb / 2; y1 = y2 - nb; if (y1 < 0) { y2 -= y1; y1 = 0; } if (y2 > m) { y1 -= (y2 - m); y2 = m; } cout << x1 << << y1 << << x2 << << y2; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[1005], b[1005]; int main() { bool same = 1; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , a + i, b + i); same &= a[i] == b[i]; } if (!same) { puts( rated ); return 0; } for (int i = 2; i <= n; ++i) { if (a[i] > a[i - 1]) { puts( unrated ); return 0; } } puts( maybe ); return 0; }
|
module autoreset_equal_extra ();
always_ff @(posedge csclk) begin
if( ~srst_n | !val_tx_to_csi ) begin
csi.cmd <= ncbo_cmd_t'('0);
// vvvvvv fifo.data.cb_req.req.cmd = '0; should not be below
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
csi.src <= 1'h0;
csi.wr <= 1'h0;
// End of automatics
end
else begin
if (fifo.sot) begin
csi.src <= fifo.src;
csi.wr <= (fifo.data.cb_req.req.cmd == ncb_defs::NCBO_RSVD_LMTST
| fifo.data.cb_req.req.cmd == ncb_defs::NCBO_IOBST
);
csi.cmd <= fifo.data.cb_req.req.cmd;
end
end
end
always_ff @(posedge csclk) begin
if (~srst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sdp__x2p.bval <= 1'h0;
sdp__x2p.err <= 1'h0;
// End of automatics
end
else begin
sdp__x2p.err <= (x2p_fifo_rdat.err & x2p_fifo_pop_d3_sk)
? x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_RCVERR
: x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_NONE;
sdp__x2p.bval <= x2p_fifo_rdat.bval & {4{x2p_fifo_pop_d3_sk}};
//FOO::bar <= 1; // Legal, though not typically used in RTL
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, c; cin >> a >> c; vector<long long> aa; while (a) { aa.push_back(a % 3); a /= 3; } vector<long long> cc; while (c) { cc.push_back(c % 3); c /= 3; } long long i = 0, j = 0; vector<long long> res; while (i < aa.size() && j < cc.size()) { res.push_back((cc[j] - aa[i] + 3) % 3); i++; j++; } while (i < aa.size()) { res.push_back((3 - aa[i]) % 3); i++; } while (j < cc.size()) { res.push_back(cc[j] % 3); j++; } long long p = 1; long long ans = 0; for (int i = 0; i < res.size(); i++) { ans += (res[i] * (p)); p *= 3; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; const int mod = 1e9 + 7; const long long inf = 1e18; const double PI = acos(-1); const double eps = 1e-8; long long qkmod(long long base, long long cnt) { long long res = 1; while (cnt) { if (cnt & 1) res = res * base % mod; base = base * base % mod; cnt >>= 1; } return res; } int a[maxn]; int main() { int T; scanf( %d , &T); int n, p; while (T--) { scanf( %d %d , &n, &p); for (int i = 0; i < n; i++) cin >> a[i]; if (p == 1) { printf(n & 1 ? 1 n : 0 n ); continue; } sort(a, a + n); long long res = 0, sum = 0, pre = 1e6 + 7; bool flag = false; int i = n - 1, j = n - 1; while (~i) { int k = a[i--]; int d = pre - k; pre = k; res = res * qkmod(p, d) % mod; for (int i = 0; i < min(20, d); i++) { sum *= p; if (sum > maxn) flag = true; } while (~j && a[j] == k) { j--; if (flag || sum > 0) { sum--; res += mod - 1; } else { sum++; res++; } } res %= mod; } printf( %d n , (res * qkmod(p, pre)) % mod); } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; long long a[N]; long long p[N]; long long size[N]; long long n; long long root(long long v) { if (v != p[v]) { return p[v] = root(p[v]); } return v; } void fix(long long v, long long x) { if (v == n + 1) return; p[v] = v + 1; long long r = root(p[v]); p[v] = r; if (size[r] + x <= a[r]) { size[r] += x; return; } else { long long excess = size[r] + x - a[r]; size[r] = a[r]; fix(r, excess); } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; p[i] = i; size[i] = 0; } p[n + 1] = n + 1; long long q; cin >> q; while (q--) { long long type, x, k; cin >> type; if (type == 1) { cin >> k >> x; if (size[k] + x <= a[k]) { size[k] += x; } else { long long excess = size[k] + x - a[k]; size[k] = a[k]; if (k == n) continue; fix(k, excess); } } else { cin >> k; cout << size[k] << n ; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, sum1 = 0, Min = 0, sum = 0; cin >> x; int p; vector<int> v; for (int j = 0; j < x; j++) { cin >> p; sum += p; v.push_back(p); } sort(v.begin(), v.end()); int s = v.size(); sum1 = 0; for (int i = s - 1; i >= 0; i--) { sum = sum - v[i]; sum1 = sum1 + v[i]; ++Min; if (sum1 > sum) break; } cout << Min; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 30, Mod = 1e9 + 7; const long long SQ = 330; const long long LOG = 20; long long n, q, Par[LOG][N], a[N], H[N], St[N], Fn[N], Lazy[N << 2], T, Fen[N], Seg[N << 2], root = 1; vector<long long> G[N]; void DFS(long long v = 1, long long par = 0) { St[v] = T++; Par[0][v] = par; for (int i = 1; i < LOG; i++) Par[i][v] = Par[i - 1][Par[i - 1][v]]; for (auto u : G[v]) { if (u == par) continue; H[u] = H[v] + 1; DFS(u, v); } Fn[v] = T; } void Shift(int id, int b, int e) { long long val = Lazy[id]; Seg[(id << 1)] += (((b + e) >> 1) - b) * val; Seg[((id << 1) | 1)] += (e - ((b + e) >> 1)) * val; Lazy[(id << 1)] += val; Lazy[((id << 1) | 1)] += val; Lazy[id] = 0; } void Add(int l, int r, long long val = 0, int id = 1, int b = 0, int e = n) { if (r <= b || e <= l) return; if (l <= b && e <= r) { Seg[id] += val * (e - b); Lazy[id] += val; return; } Shift(id, b, e); Add(l, r, val, (id << 1), b, ((b + e) >> 1)); Add(l, r, val, ((id << 1) | 1), ((b + e) >> 1), e); Seg[id] = Seg[(id << 1)] + Seg[((id << 1) | 1)]; } long long Get(int l, int r, int id = 1, int b = 0, int e = n) { if (r <= b || e <= l) return 0; if (l <= b && e <= r) return Seg[id]; Shift(id, b, e); return Get(l, r, (id << 1), b, ((b + e) >> 1)) + Get(l, r, ((id << 1) | 1), ((b + e) >> 1), e); } bool is_par(long long v, long long u) { return St[v] <= St[u] && Fn[u] <= Fn[v]; } long long Up(long long v, long long h) { for (int i = LOG - 1; ~i; i--) if (h & (1 << i)) v = Par[i][v]; return v; } long long LLCA(long long v, long long u) { if (H[v] < H[u]) swap(v, u); v = Up(v, H[v] - H[u]); if (v == u) return v; for (int i = LOG - 1; ~i; i--) { if (Par[i][v] ^ Par[i][u]) { v = Par[i][v]; u = Par[i][u]; } } return Par[0][v]; } long long LCA(long long v, long long u) { if (is_par(root, v) && is_par(root, u)) return LLCA(v, u); if (is_par(root, v) && !is_par(root, u)) return root; if (is_par(root, u) && !is_par(root, v)) return root; long long l = LLCA(v, u); if (is_par(v, u)) { long long x = LLCA(u, root); if (is_par(v, x)) return x; return v; } if (is_par(u, v)) { long long x = LLCA(v, root); if (is_par(u, x)) return x; return u; } if (is_par(l, root)) { long long f = LLCA(v, root); long long f2 = LLCA(u, root); if (H[f2] > H[f]) { return f2; } return f; } return l; } void Inp() { cin >> n >> q; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 0; i < n - 1; i++) { long long v, u; cin >> v >> u; G[v].push_back(u); G[u].push_back(v); } DFS(1, 0); for (int i = 1; i <= n; i++) { Add(St[i], St[i] + 1, a[i]); } } void Add_Sub(long long v, long long val) { if (v == root) { Add(0, n, val); return; } if (is_par(root, v)) { Add(St[v], Fn[v], val); return; } if (is_par(v, root)) { long long dif = H[root] - H[v] - 1; long long rr = Up(root, dif); Add(0, n, val); Add(St[rr], Fn[rr], -val); return; } Add(St[v], Fn[v], val); } long long Get_Sub(long long v) { if (v == root) return Get(0, n); if (is_par(root, v)) { return Get(St[v], Fn[v]); } if (is_par(v, root)) { long long dif = H[root] - H[v] - 1; long long rr = Up(root, dif); return Get(0, n) - Get(St[rr], Fn[rr]); } return Get(St[v], Fn[v]); } int main() { ios::sync_with_stdio(0), cin.tie(0); Inp(); while (q--) { long long t; cin >> t; if (t == 1) { long long v; cin >> v; root = v; } if (t == 2) { long long v, u, x; cin >> v >> u >> x; long long l = LCA(v, u); Add_Sub(l, x); } if (t == 3) { long long v; cin >> v; cout << Get_Sub(v) << n ; } } }
|
#include <bits/stdc++.h> using namespace std; struct block { int x, y; inline bool operator<(const block &cpr) const { if (x != cpr.x) return x < cpr.x; return y < cpr.y; } inline bool operator==(const block &cpr) const { return ((x == cpr.x) && (y == cpr.y)); } }; struct nblock { int x, y, id; inline bool operator<(const nblock &cpr) const { if (y != cpr.y) return y < cpr.y; return x < cpr.x; } }; block bl[100005]; nblock nbl[100005]; int vis[100005]; int n, m; queue<int> pq; int mov[8][2]{ 1, 1, 1, 0, 1, -1, 0, -1, 0, 1, -1, 1, -1, 0, -1, -1, }; int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d%d , &bl[i].x, &bl[i].y); sort(bl + 1, bl + 1 + m); for (int i = 1; i <= m; i++) { nbl[i].x = bl[i].x; nbl[i].y = bl[i].y; nbl[i].id = i; } sort(nbl + 1, nbl + 1 + m); for (int i = 1; i <= m; i++) if (bl[i].x == n || bl[i].y == 1) { vis[i] = 1; pq.push(i); } while (pq.size()) { block cur; int cid; cid = pq.front(); cur = bl[cid]; pq.pop(); if (cur.x > 1) { block nw; nw = cur; nw.x--; int top, bot, tr; top = m; bot = 1; while (top > bot) { tr = (top + bot + 1) / 2; if (bl[tr] < nw) bot = tr; else top = tr - 1; } if (bl[top].x == nw.x) if (bl[top].y < nw.y) if (vis[top] == 0) { vis[top] = 1; pq.push(top); } } if (cur.y < n) { nblock nw; nw.x = cur.x; nw.y = cur.y + 1; int top, bot, tr; top = m; bot = 1; while (top > bot) { tr = (top + bot) / 2; if (nw < nbl[tr]) top = tr; else bot = tr + 1; } if (nbl[top].y == nw.y) if (nbl[top].x > nw.x) if (vis[nbl[top].id] == 0) { vis[nbl[top].id] = 1; pq.push(nbl[top].id); } } for (int dr = 0; dr < 8; dr++) { block nw; nw = cur; nw.x += mov[dr][0]; nw.y += mov[dr][1]; int top, bot, tr; top = m; bot = 1; while (top > bot) { tr = (top + bot + 1) / 2; if (nw < bl[tr]) top = tr - 1; else bot = tr; } if (nw == bl[top]) if (vis[top] == 0) { vis[top] = 1; pq.push(top); } } } for (int i = 1; i <= m; i++) if (vis[i] == 1) if (bl[i].x == 1 || bl[i].y == n) { printf( -1 n ); return 0; } printf( %d n , 2 * (n - 1)); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pli = pair<ll, int>; const int INF = 0x3f3f3f3f, N = 3e3 + 5; const ll LINF = 1e18 + 5; int n; vector<int> G[N]; int sz[N][N], f[N][N]; ll dp[N][N], maxn; void dfs(int u, int fa, int rt) { sz[rt][u] = 1; f[rt][u] = fa; for (int v : G[u]) { if (v == fa) continue; dfs(v, u, rt); sz[rt][u] += sz[rt][v]; } } ll solve(int u, int v) { if (~dp[u][v]) return dp[u][v]; if (u == v) return dp[u][v] = 0; return dp[u][v] = max(solve(f[v][u], v), solve(u, f[u][v])) + 1ll * sz[u][v] * sz[v][u]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= n; i++) dfs(i, 0, i); memset(dp, -1, sizeof(dp)); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) maxn = max(maxn, solve(i, j)); cout << maxn; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter BUFTYPE = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out_p;
output tx_data_out_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire tx_data_oddr_s;
wire tx_data_odelay_s;
// delay controller
generate
if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// transmit data interface, oddr -> odelay -> obuf
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_tx_data_oddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (tx_clk),
.D1 (tx_data_p),
.D2 (tx_data_n),
.Q (tx_data_oddr_s));
generate
if ((IODELAY_ENABLE == 1) && (BUFTYPE == SERIES7)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
ODELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("ODATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.ODELAY_TYPE ("VAR_LOAD"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_tx_data_odelay (
.CE (1'b0),
.CLKIN (1'b0),
.INC (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.ODATAIN (tx_data_oddr_s),
.DATAOUT (tx_data_odelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
assign up_drdata = 5'd0;
assign tx_data_odelay_s = tx_data_oddr_s;
end
endgenerate
OBUFDS i_tx_data_obuf (
.I (tx_data_odelay_s),
.O (tx_data_out_p),
.OB (tx_data_out_n));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> inline bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long N, K; cin >> N >> K; if (K == 1) { cout << N << n ; return 0; } string be, en; cin >> be >> en; long long ans = 0, cur = 1; for (int i = 0; i < N; ++i) { cur *= 2LL; if (be[i] == b ) --cur; if (en[i] == a ) --cur; uin(cur, K); ans += cur; } cout << ans << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_1_V
`define SKY130_FD_SC_LP__A2111O_1_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_1_V
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic IDDR module
*/
module iddr #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q1,
output wire [WIDTH-1:0] q2
);
/*
Provides a consistent input DDR flip flop across multiple FPGA families
_____ _____ _____ _____ ____
clk ____/ \_____/ \_____/ \_____/ \_____/
_ _____ _____ _____ _____ _____ _____ _____ _____ _____ _
d _X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7__X_D8__X_
_______ ___________ ___________ ___________ ___________ _
q1 _______X___________X____D0_____X____D2_____X____D4_____X_
_______ ___________ ___________ ___________ ___________ _
q2 _______X___________X____D1_____X____D3_____X____D5_____X_
*/
genvar n;
generate
if (TARGET == "XILINX") begin
for (n = 0; n < WIDTH; n = n + 1) begin : iddr
if (IODDR_STYLE == "IODDR") begin
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.SRTYPE("ASYNC")
)
iddr_inst (
.Q1(q1[n]),
.Q2(q2[n]),
.C(clk),
.CE(1'b1),
.D(d[n]),
.R(1'b0),
.S(1'b0)
);
end else if (IODDR_STYLE == "IODDR2") begin
IDDR2 #(
.DDR_ALIGNMENT("C0")
)
iddr_inst (
.Q0(q1[n]),
.Q1(q2[n]),
.C0(clk),
.C1(~clk),
.CE(1'b1),
.D(d[n]),
.R(1'b0),
.S(1'b0)
);
end
end
end else if (TARGET == "ALTERA") begin
wire [WIDTH-1:0] q1_int;
reg [WIDTH-1:0] q1_delay;
altddio_in #(
.WIDTH(WIDTH),
.POWER_UP_HIGH("OFF")
)
altddio_in_inst (
.aset(1'b0),
.datain(d),
.inclocken(1'b1),
.inclock(clk),
.aclr(1'b0),
.dataout_h(q1_int),
.dataout_l(q2)
);
always @(posedge clk) begin
q1_delay <= q1_int;
end
assign q1 = q1_delay;
end else begin
reg [WIDTH-1:0] d_reg_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] d_reg_2 = {WIDTH{1'b0}};
reg [WIDTH-1:0] q_reg_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] q_reg_2 = {WIDTH{1'b0}};
always @(posedge clk) begin
d_reg_1 <= d;
end
always @(negedge clk) begin
d_reg_2 <= d;
end
always @(posedge clk) begin
q_reg_1 <= d_reg_1;
q_reg_2 <= d_reg_2;
end
assign q1 = q_reg_1;
assign q2 = q_reg_2;
end
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; string convertTostr(int x) { stringstream ss; ss << x; string st; st = ss.str(); return st; } unsigned long long convertToint(string y) { unsigned long long num; stringstream ss(y); ss >> num; return num; } unsigned long long fpow(unsigned long long b, unsigned long long p, unsigned long long m) { if (p == 0) return 1; if (p == 1) return b % m; unsigned long long res = fpow(b, p / 2, m) % m; res = (res * res) % m; if (p % 2 != 0) res = (res * (b % m)) % m; return res; } int main() { std::cin.tie(0); std::ios::sync_with_stdio(false); int n; cin >> n; vector<pair<int, int> > vec; int x, y; for (int i = 0; i < n; i++) { cin >> x >> y; vec.push_back(make_pair(x, y)); } int cnt = 0; for (int i = 0; i < n - 2; i++) { int curX = vec[i].first, curY = vec[i].second; int nX = vec[i + 1].first, nY = vec[i + 1].second; int aX = vec[i + 2].first, aY = vec[i + 2].second; if ((nX > curX && aY > nY) || (nX < curX && aY < nY) || (nY > curY && aX < nX) || (nY < curY && aX > nX)) cnt++; } cout << cnt; return 0; }
|
module globalbranchpredictor(clk,pcsrcd,pcsrcd2,pcd,pcbranchd,pcbranchd2,originalpc,pcnext,clrbp);
input clk;
input [1:0] pcsrcd,pcsrcd2;
input [63:0] originalpc;
input [31:0] pcbranchd,pcbranchd2, pcd;
output reg [31:0] pcnext;
output reg clrbp;
reg [71:0] branchtargetbuffer[127:0];
reg [31:0] pcstorage;
reg [1:0] global;
//66 bits, first 32 bits address, next 32 bits predicted address, 2 bits T/NT
integer i;
reg foundflag, pcdfoundflag; // foundflag for Prediction, pcdfoundflag for mispredictions
initial begin
global = 2'b00;
for (i=0; i<128; i=i+1) begin
branchtargetbuffer[i] = 72'bx;
end
end
integer j=0;
integer count=0;
integer recorder;
always @(negedge clk) begin
// IF Stage
foundflag = 1'b0;
pcdfoundflag = 1'b0;
for (i=0; i<128; i=i+1) begin
if (pcd==branchtargetbuffer[i][71:40]) begin
pcdfoundflag = 1'b1;
recorder = i;
end
if (originalpc[63:32]==branchtargetbuffer[i][71:40] ) begin
case(global)
2'b00: begin
if (!branchtargetbuffer[i][7]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b01: begin
if (!branchtargetbuffer[i][5]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b10: begin
if (!branchtargetbuffer[i][3]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b11: begin
if (!branchtargetbuffer[i][1]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
endcase
foundflag = 1'b1;
recorder = i;
end
else if (originalpc[31:0]==branchtargetbuffer[i][71:40] ) begin
case(global)
2'b00: begin
if (!branchtargetbuffer[i][7]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b01: begin
if (!branchtargetbuffer[i][5]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b10: begin
if (!branchtargetbuffer[i][3]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b11: begin
if (!branchtargetbuffer[i][1]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
endcase
foundflag = 1'b1;
recorder = i;
end
end
// ID and EX Stages
// found? - Yes
if (foundflag) begin
clrbp = 1'b0;
// Update the existing buffer to a higher taken
case(global)
2'b00: begin
global = 2'b00;
case(branchtargetbuffer[recorder][7:6])
2'b00: branchtargetbuffer[recorder][7:6] = 2'b00;
2'b01: branchtargetbuffer[recorder][7:6] = 2'b00;
2'b10: branchtargetbuffer[recorder][7:6] = 2'b01;
2'b11: branchtargetbuffer[recorder][7:6] = 2'b10;
endcase
end
2'b01: begin
global = 2'b00;
case(branchtargetbuffer[recorder][5:4])
2'b00: branchtargetbuffer[recorder][5:4] = 2'b00;
2'b01: branchtargetbuffer[recorder][5:4] = 2'b00;
2'b10: branchtargetbuffer[recorder][5:4] = 2'b01;
2'b11: branchtargetbuffer[recorder][5:4] = 2'b10;
endcase
end
2'b10: begin
global = 2'b01;
case(branchtargetbuffer[recorder][3:2])
2'b00: branchtargetbuffer[recorder][3:2] = 2'b00;
2'b01: branchtargetbuffer[recorder][3:2] = 2'b00;
2'b10: branchtargetbuffer[recorder][3:2] = 2'b01;
2'b11: branchtargetbuffer[recorder][3:2] = 2'b10;
endcase
end
2'b11: begin
global = 2'b10;
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b10;
endcase
end
endcase
end
// Misprediction
else if (!pcsrcd[0] && pcdfoundflag) begin
// Put back old count and issue a clr signal to pipefd
clrbp = 1'b1;
pcnext = pcstorage;
// Update the existing buffer to a lower taken
case(global)
2'b00: begin
global = 2'b01;
case(branchtargetbuffer[recorder][7:6])
2'b00: branchtargetbuffer[recorder][7:6] = 2'b01;
2'b01: branchtargetbuffer[recorder][7:6] = 2'b10;
2'b10: branchtargetbuffer[recorder][7:6] = 2'b11;
2'b11: branchtargetbuffer[recorder][7:6] = 2'b11;
endcase
end
2'b01: begin
global = 2'b11;
case(branchtargetbuffer[recorder][5:4])
2'b00: branchtargetbuffer[recorder][5:4] = 2'b01;
2'b01: branchtargetbuffer[recorder][5:4] = 2'b10;
2'b10: branchtargetbuffer[recorder][5:4] = 2'b11;
2'b11: branchtargetbuffer[recorder][5:4] = 2'b11;
endcase
end
2'b10: begin
global = 2'b01;
case(branchtargetbuffer[recorder][3:2])
2'b00: branchtargetbuffer[recorder][3:2] = 2'b01;
2'b01: branchtargetbuffer[recorder][3:2] = 2'b10;
2'b10: branchtargetbuffer[recorder][3:2] = 2'b11;
2'b11: branchtargetbuffer[recorder][3:2] = 2'b11;
endcase
end
2'b11: begin
global = 2'b11;
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b10;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b11;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b11;
endcase
end
endcase
end
//found? - No
else begin
if (pcsrcd[0]) begin//branch taken
// Write into buffer at next available spot
branchtargetbuffer[count][7:0] = 8'b0;
branchtargetbuffer[count][39:8] = pcbranchd;
branchtargetbuffer[count][71:40] = pcd;
pcnext = pcbranchd;
clrbp = 1'b0;
count = count + 1;
if (count > 127)
count = 0;
case(global)
2'b00: global=2'b00;
2'b01: global=2'b10;
2'b10: global=2'b00;
2'b11: global=2'b10;
endcase
end
else if (pcsrcd2[0]) begin//branch taken
// Write into buffer at next available spot
branchtargetbuffer[count][7:0] = 8'b0;
branchtargetbuffer[count][39:8] = pcbranchd2;
branchtargetbuffer[count][71:40] = pcd;
pcnext = pcbranchd2;
clrbp = 1'b0;
count = count + 1;
if (count > 127)
count = 0;
case(global)
2'b00: global=2'b00;
2'b01: global=2'b10;
2'b10: global=2'b00;
2'b11: global=2'b10;
endcase
end
else begin//branch not taken
clrbp = 1'b0;
pcnext = originalpc[63:32];
case(global)
2'b00: global=2'b01;
2'b01: global=2'b11;
2'b10: global=2'b01;
2'b11: global=2'b11;
endcase
end
end
end
endmodule
|
module mutex_buffer #
(
parameter integer C_BUFF_NUM = 4
) (
input wire clk,
input wire resetn,
output wire wr_done,
input wire w_sof,
output reg [C_BUFF_NUM-1:0] w_bmp,
input wire r0_sof,
output reg [C_BUFF_NUM-1:0] r0_bmp,
input wire r1_sof,
output reg [C_BUFF_NUM-1:0] r1_bmp
);
assign wr_done = w_sof;
reg [C_BUFF_NUM-1:0] last_bmp;
/// reader 0
always @(posedge clk) begin
if (resetn == 0) begin
r0_bmp <= 0;
end
else if (r0_sof) begin
if (w_sof) begin
r0_bmp <= w_bmp;
end
else begin
r0_bmp <= last_bmp;
end
end
end
/// reader 1 (same as reader 0)
always @(posedge clk) begin
if (resetn == 0) begin
r1_bmp <= 0;
end
else if (r1_sof) begin
if (w_sof) begin
r1_bmp <= w_bmp;
end
else begin
r1_bmp <= last_bmp;
end
end
end
/// last done (ready for read)
always @(posedge clk) begin
if (resetn == 0) begin
last_bmp <= 4'b0001;
end
else if (w_sof) begin
last_bmp <= w_bmp;
end
end
always @(posedge clk) begin
if (resetn == 0) begin
w_bmp <= 4'b0010;
end
else if (w_sof) begin
casez (w_bmp | r0_bmp | r1_bmp)
4'b???0: begin
w_bmp <= 4'b0001;
end
4'b??01: begin
w_bmp <= 4'b0010;
end
4'b?011: begin
w_bmp <= 4'b0100;
end
4'b0111: begin
w_bmp <= 4'b1000;
end
default: begin
w_bmp <= 4'b0010;
end
endcase
end
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more than 1 asserted bits");
end
end
end
assign fire_2state_1 = !zoh_test_expr;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_all_zeros covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == {width{1'b0}}) && (prev_test_expr != {width{1'b0}}));
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int n, m, sum = 0, a = 101; int main() { cin >> n; while (n--) { cin >> m; sum += m; if (m & 1 && m < a) a = m; } if (sum & 1) cout << sum << endl; else { if (a == 101) cout << 0 << endl; else cout << sum - a << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, i = 0, j = 0; cin >> a >> b >> c >> d; while (a != 0) { a = a - 1; i++; } while (b != 0) { b = b - 1; j++; } if (j >= i) cout << Second ; else cout << First ; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; const int mod = 1000000007; const int inf = 2012345678; const long long infl = 9012345678901234567; const double pi = 3.1415926535897932384626433832795; struct rat { long long a, b; rat(long long _a = 0, long long _b = 1) { if (_b < 0) _a = -_a, _b = -_b; a = _a; b = _b; } bool operator<(const rat& ot) const { return a * ot.b < ot.a * b; } rat operator-() const { return rat(-a, b); } bool operator==(const rat& ot) const { return a * ot.b == ot.a * b; } }; const int N = 100000; const int LG = 17; vector<int> adj[N]; int rnk[N], up[N], anc[N][LG], down[N], hvc[N], cnt[N]; void dfs0(int u) { cnt[u] = 1; hvc[u] = -1; for (auto& x : adj[u]) { if (x == anc[u][0]) continue; rnk[x] = rnk[u] + 1; anc[x][0] = u; dfs0(x); cnt[u] += cnt[x]; if (hvc[u] == -1 || cnt[x] > cnt[hvc[u]]) hvc[u] = x; } } void dfs1(int u, bool hv) { if (hv) up[u] = u; else up[u] = up[anc[u][0]]; if (hvc[u] == -1) { down[u] = u; } else { dfs1(hvc[u], false); down[u] = down[hvc[u]]; } for (auto& x : adj[u]) { if (x == anc[u][0] || x == hvc[u]) continue; dfs1(x, true); } } int lca(int u, int v) { if (rnk[u] < rnk[v]) swap(u, v); int d = rnk[u] - rnk[v]; for (int i = 0; i < (LG); i++) if (d & (1 << i)) u = anc[u][i]; if (u == v) return u; for (int i = LG - 1; i >= 0; i--) if (anc[u][i] != anc[v][i]) u = anc[u][i], v = anc[v][i]; return anc[u][0]; } struct Query { int X, Y; int s, c; Query() {} Query(int a, int b, int x, int y) : X(a), Y(b), s(x), c(y) {} }; vector<Query> qs[N]; double ans = 1e12; int chk[N]; void solve(int u) { priority_queue<tuple<rat, int, int, int> > pq; auto cmp = [&](int i, int j) -> bool { if (rat(qs[u][i].X, qs[u][i].c) < rat(qs[u][j].X, qs[u][j].c)) { return rat((long long)qs[u][i].c * qs[u][j].X, qs[u][j].c) < qs[u][j].s - qs[u][i].s + qs[u][i].X; } else { return rat(qs[u][i].s - qs[u][j].s + qs[u][j].X, 1) < rat((long long)qs[u][i].X * qs[u][j].c, qs[u][i].c); } }; set<int, decltype(cmp)> st(cmp); int sz = qs[u].size(); for (int i = 0; i < (sz); i++) { pq.push(make_tuple(rat(-qs[u][i].X, qs[u][i].c), 2, i, 0)); pq.push(make_tuple(rat(-qs[u][i].Y, qs[u][i].c), 1, i, 0)); chk[i] = 0; } while (!pq.empty()) { auto T = pq.top(); pq.pop(); int tp = get<1>(T); rat time = -get<0>(T); if (tp == 1) { int i = get<2>(T); chk[i] = 0; auto it = st.find(i); it = st.erase(it); auto it2 = it; if (it != st.begin()) { it2--; if (it != st.end()) { int i = *it; int j = *it2; if (qs[u][i].c != qs[u][j].c) { rat ntime = rat(qs[u][i].X - qs[u][j].X - qs[u][i].s + qs[u][j].s, qs[u][i].c - qs[u][j].c); if (!(ntime < time)) { pq.push(make_tuple(-ntime, 3, i, j)); } } } } } else if (tp == 2) { int i = get<2>(T); chk[i] = 1; auto P = st.insert(i); if (!P.second) { ans = min(ans, (double)time.a / time.b); return; } auto it2 = P.first; auto it = it2; if (it != st.begin()) { it2--; int j = *it2; if (qs[u][i].c != qs[u][j].c) { rat ntime = rat(qs[u][i].X - qs[u][j].X - qs[u][i].s + qs[u][j].s, qs[u][i].c - qs[u][j].c); if (!(ntime < time)) { pq.push(make_tuple(-ntime, 3, i, j)); } } } it2 = it; it2++; if (it2 != st.end()) { int j = *it2; if (qs[u][i].c != qs[u][j].c) { rat ntime = rat(qs[u][i].X - qs[u][j].X - qs[u][i].s + qs[u][j].s, qs[u][i].c - qs[u][j].c); if (!(ntime < time)) { pq.push(make_tuple(-ntime, 3, i, j)); } } } } else { int u = get<2>(T); int v = get<3>(T); if (!chk[u] || !chk[v]) continue; ans = min(ans, (double)time.a / time.b); return; } } } int main() { freopen( input.txt , r , stdin); int n, m; scanf( %d%d , &(n), &(m)); for (int i = 0; i < (n - 1); i++) { int a, b; scanf( %d%d , &(a), &(b)); a--; b--; adj[a].push_back(b); adj[b].push_back(a); } anc[0][0] = -1; dfs0(0); dfs1(0, true); for (int j = 1; j <= (LG - 1); j++) for (int i = 0; i < (n); i++) { int a = anc[i][j - 1]; if (a == -1) anc[i][j] = -1; else anc[i][j] = anc[a][j - 1]; } for (int i = 0; i < (m); i++) { int t, c, u, v; scanf( %d%d , &(t), &(c)); scanf( %d%d , &(u), &(v)); u--; v--; bool good = false; int L = lca(u, v); int ou = u; while (up[u] != up[L]) { int uu = up[u]; qs[uu].emplace_back(-(c * t + rnk[ou] - rnk[u]), -(c * t + rnk[ou] - rnk[uu] + 1), rnk[u], -c); u = anc[uu][0]; } if (u != L) { qs[up[u]].emplace_back(-(c * t + rnk[ou] - rnk[u]), -(c * t + rnk[ou] - rnk[L]), rnk[u], -c); good = true; } int d = rnk[ou] - rnk[L]; while (up[v] != up[L]) { int vv = up[v]; qs[vv].emplace_back(t * c + rnk[vv] - 1 - rnk[L] + d, t * c + rnk[v] - rnk[L] + d, rnk[vv] - 1, c); v = anc[vv][0]; } if (v != L) { good = true; qs[up[v]].emplace_back(t * c + d, t * c + rnk[v] - rnk[L] + d, rnk[L], c); } if (!good) { qs[up[L]].emplace_back(t * c + d, t * c + d, rnk[L], c); } } for (int i = 0; i < (n); i++) { if (up[i] == i) { solve(i); } } if (ans > 1e11) { puts( -1 ); } else printf( %.15f n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, ans[110]; int main() { scanf( %d , &n); for (int i = n; i > 0; i--) { printf( ? ); for (int j = 1; j < n; j++) printf( 1 ); printf( %d n , i); fflush(stdout); int k; scanf( %d , &k); if (k) { ans[n] = n - i + 1; ans[k] = n; break; } } if (!ans[n]) ans[n] = n; for (int i = ans[n] + 1; i <= n; i++) { printf( ? ); for (int j = 1; j < n; j++) printf( 1 ); printf( %d n , i - ans[n] + 1); fflush(stdout); int k; scanf( %d , &k); ans[k] = i; } for (int i = 1; i < ans[n]; i++) { printf( ? ); for (int j = 1; j < n; j++) printf( %d , ans[n] - i + 1); printf( 1 n ); fflush(stdout); int k; scanf( %d , &k); ans[k] = i; } printf( ! ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); puts( ); }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 10; const long long INF = numeric_limits<long long>::max(); enum { EVEN, ODD }; int A[MAXN]; long long dp[2][MAXN]; int main() { int N; cin >> N; for (int i = 1; i <= N; ++i) cin >> A[i]; dp[ODD][1] = dp[EVEN][1] = dp[ODD][2] = -INF; dp[EVEN][2] = abs(A[2] - A[1]); long long ans = dp[EVEN][2]; for (int i = 3; i <= N; ++i) { dp[ODD][i] = dp[EVEN][i - 1] - abs(A[i] - A[i - 1]); dp[EVEN][i] = max(dp[ODD][i - 1] + abs(A[i] - A[i - 1]), abs(A[i] - A[i - 1]) * 1ll); ans = max(ans, max(dp[ODD][i], dp[EVEN][i])); } cout << ans << endl; return 0; }
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: id_ex
// File: id_ex.v
// Author: Lei Silei
// E-mail:
// Description: ID/EX½×¶ÎµÄ¼Ä´æÆ÷
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module id_ex(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//´ÓÒëÂë½×¶Î´«µÝµÄÐÅÏ¢
input wire[`AluOpBus] id_aluop,
input wire[`AluSelBus] id_alusel,
input wire[`RegBus] id_reg1,
input wire[`RegBus] id_reg2,
input wire[`RegAddrBus] id_wd,
input wire id_wreg,
input wire[`RegBus] id_link_address,
input wire id_is_in_delayslot,
input wire next_inst_in_delayslot_i,
input wire[`RegBus] id_inst,
input wire[`RegBus] id_current_inst_address,
input wire[31:0] id_excepttype,
//´«µÝµ½Ö´Ðн׶εÄÐÅÏ¢
output reg[`AluOpBus] ex_aluop,
output reg[`AluSelBus] ex_alusel,
output reg[`RegBus] ex_reg1,
output reg[`RegBus] ex_reg2,
output reg[`RegAddrBus] ex_wd,
output reg ex_wreg,
output reg[`RegBus] ex_link_address,
output reg ex_is_in_delayslot,
output reg is_in_delayslot_o,
output reg[`RegBus] ex_inst,
output reg[31:0] ex_excepttype,
output reg[`RegBus] ex_current_inst_address
);
always @ (posedge clk) begin
if (rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
is_in_delayslot_o <= `NotInDelaySlot;
ex_inst <= `ZeroWord;
ex_excepttype <= `ZeroWord;
ex_current_inst_address <= `ZeroWord;
end else if(flush == 1'b1 ) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_excepttype <= `ZeroWord;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
ex_current_inst_address <= `ZeroWord;
is_in_delayslot_o <= `NotInDelaySlot;
end else if(stall[2] == `Stop && stall[3] == `NoStop) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_is_in_delayslot <= `NotInDelaySlot;
ex_inst <= `ZeroWord;
ex_excepttype <= `ZeroWord;
ex_current_inst_address <= `ZeroWord;
end else if(stall[2] == `NoStop) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_link_address <= id_link_address;
ex_is_in_delayslot <= id_is_in_delayslot;
is_in_delayslot_o <= next_inst_in_delayslot_i;
ex_inst <= id_inst;
ex_excepttype <= id_excepttype;
ex_current_inst_address <= id_current_inst_address;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long int; string s, t; int mp[28], tempMap[28]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int i, j, len1, len2, can = -1; cin >> s >> t; len1 = (int)s.size(), len2 = (int)t.size(); for (i = 0; i < len1; i++) { mp[s[i] - a ]++; } int rng = min(len1, len2) - 1; if (len1 > len2) rng++; for (i = 0; i < rng; i++) { if (mp[t[i] - a ]) { mp[t[i] - a ]--; for (j = 0; j < 26; j++) { tempMap[j] = mp[j]; } bool flag = false; if (i == len2 - 1) { if (len1 > len2 && i == rng - 1) flag = true, can = i; } else { for (j = t[i + 1] - a + 1; j < 26; j++) { if (mp[j]) { flag = true; break; } } if (flag) can = i; } } else { break; } } memset(mp, 0, sizeof mp); for (i = 0; i < len1; i++) mp[s[i] - a ]++; if (can == -1) { int found = -1; for (i = t[0] - a + 1; i < 26; i++) { if (mp[i]) { found = i; break; } } if (found == -1) cout << -1 << endl; else { cout << (char)(found + a ); mp[found]--; for (i = 0; i < 26; i++) { for (j = 0; j < mp[i]; j++) { cout << (char)(i + a ); } } cout << endl; } } else { for (i = 0; i <= can; i++) { cout << t[i]; mp[t[i] - a ]--; } if (len1 > len2 && can == len2 - 1) { for (i = 0; i < 26; i++) { for (j = 0; j < mp[i]; j++) { cout << (char)(i + a ); } } cout << endl; } else { for (i = t[can + 1] - a + 1; i < 26; i++) { if (mp[i]) { cout << (char)(i + a ); mp[i]--; break; } } for (i = 0; i < 26; i++) { for (j = 0; j < mp[i]; j++) { cout << (char)(i + a ); } } cout << endl; } } return 0; }
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module top
(
input clk
/* synthesis loc="27" pullmode="none" */,
input rx
/* synthesis loc="73" */,
input [7:0] pin
/* synthesis loc="10, 9, 6, 5, 4, 3, 2, 1" */,
output tx
/* synthesis loc="74" */,
output [7:0] led
/* synthesis loc="107, 106, 105, 104, 100, 99, 98, 97" */,
output x2en
/* synthesis loc="32" */,
output [7:0] pout
/* synthesis loc="96, 95, 94, 93, 92, 91, 86, 85" */,
output clk_sample
/* synthesis loc="14" */
);
parameter ENABLE = 1'b1;
parameter DISABLE = 1'b0;
parameter STATE_RCV_REG = 2'b0;
parameter STATE_RCV_VAL = 2'b1;
parameter REG_LED = 7'h0;
parameter REG_MEMADR_RD_LO = 7'h1;
parameter REG_MEMADR_RD_HI = 7'h2;
parameter REG_MEMADR_WR_LO = 7'h3;
parameter REG_MEMADR_WR_HI = 7'h4;
parameter REG_MEM = 7'h5;
parameter REG_STATUS = 7'h6;
parameter REG_TRIG_EN = 7'h7;
parameter REG_TRIG_VAL = 7'h8;
parameter REG_CLKDIV_LO = 7'h9;
parameter REG_CLKDIV_HI = 7'hA;
reg rst = ENABLE;
reg transmit = DISABLE;
reg [7:0] tx_byte;
reg [6:0] register;
reg [7:0] value;
reg [2:0] state = 2'b0;
reg [7:0] r_led = 8'b0;
reg [13:0] memadr_rd = 13'h0;
reg [13:0] memadr_wr = 13'h0;
reg memwe = DISABLE;
reg [7:0] memdata_in;
wire [7:0] memdata_out;
reg [7:0] memcnt_rd = 10'h0;
reg [7:0] trig_en = 8'h0;
reg [7:0] trig_val = 8'h0;
reg [15:0] clkdiv = 16'h1;
/**
* Status register bits:
*
* Bit Direction Function
* 0 WR Write 1 to start sampling, is set to 0 after sampling started
* 1 R 1 if sampling is in progress, 0 no sampling in progress
* 2 WR Trigger enable
* 3
* 4
* 5
* 6
* 7
*/
reg [7:0] status = 8'b0;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire rcv_error;
wire clk_96M;
wire clk_48M;
wire clk_24M;
wire clk_1M;
// pll
pll pll1 (
clk,
clk_96M,
clk_48M,
clk_24M,
clk_1M
);
reg clk_sample_rst = DISABLE;
// wire clk_sample;
clkdiv div1 (
clk_sample_rst,
clk_96M,
clkdiv,
clk_sample
);
// DP ram
ram ram1 (
memadr_wr[13:0] - 1'b1,
memadr_rd[13:0],
memdata_in[7:0],
memwe,
clk_96M,
ENABLE,
rst,
clk_96M,
ENABLE,
memdata_out[7:0]
);
// uart 115200 baud (12 MHz * 1000 * 1000 / (115200 * 4))
// uart #(26) uart1 (
uart #(26) uart1 (
clk_96M, // The master clock for this module
rst, // Synchronous reset.
rx, // Incoming serial line
tx, // Outgoing serial line
transmit, // Signal to transmit
tx_byte, // Byte to transmit
received, // Indicated that a byte has been received.
rx_byte, // Byte received
is_receiving, // Low when receive line is idle.
is_transmitting, // Low when transmit line is idle.
recv_error // Indicates error in receiving packet.
);
////
// communication loop
////
always @(posedge clk_96M) begin
if(rst) begin
rst <= DISABLE;
end
else if(received) begin
case(state)
STATE_RCV_REG:
begin
register[6:0] = rx_byte[6:0];
// check if bit 7 is 0, this means read access
if(rx_byte[7] == 0) begin
////
// handle register command
////
case(register)
REG_STATUS : tx_byte[7:0] = status[7:0];
REG_LED : tx_byte[7:0] = r_led[7:0];
REG_MEMADR_RD_LO : tx_byte[7:0] = memadr_rd[7:0];
REG_MEMADR_RD_HI : tx_byte[7:0] = memadr_rd[13:8];
REG_MEMADR_WR_LO : tx_byte[7:0] = memadr_wr[7:0];
REG_MEMADR_WR_HI : tx_byte[7:0] = memadr_wr[13:8];
REG_MEM : state <= STATE_RCV_VAL; // this takes the number of bytes as a parameter
REG_TRIG_EN : tx_byte[7:0] = trig_en[7:0];
REG_TRIG_VAL : tx_byte[7:0] = trig_val[7:0];
REG_CLKDIV_LO : tx_byte[7:0] = clkdiv[7:0];
REG_CLKDIV_HI : tx_byte[7:0] = clkdiv[15:8];
default : tx_byte[7:0] = 8'hff;
endcase
// for single read access, begin data transfer
if(register != REG_MEM) begin
transmit <= ENABLE;
end
end
else begin
// write access always takes a parameter
state <= STATE_RCV_VAL;
end
end
STATE_RCV_VAL:
begin
value[7:0] = rx_byte[7:0];
////
// handle parameter
////
case(register)
REG_STATUS :
begin
status[0] = value[0]; // start sampling
status[2] = value[2]; // enable trigger
end
REG_LED : r_led[7:0] = value[7:0];
REG_MEMADR_RD_LO : memadr_rd[7:0] = value[7:0];
REG_MEMADR_RD_HI : memadr_rd[13:8] = value[5:0];
REG_MEM : memcnt_rd[7:0] = value[7:0];
REG_TRIG_EN : trig_en[7:0] = value[7:0];
REG_TRIG_VAL : trig_val[7:0] = value[7:0];
REG_CLKDIV_LO : clkdiv[7:0] = value[7:0];
REG_CLKDIV_HI : clkdiv[15:8] = value[7:0];
endcase
// reset sample clk
if(register == REG_CLKDIV_LO || register == REG_CLKDIV_HI) begin
clk_sample_rst = ENABLE;
end
// ready to receive next command
state <= STATE_RCV_REG;
end
endcase
end
else if(is_transmitting) begin
transmit <= DISABLE;
end
else if(!transmit && memcnt_rd) begin
// send the requested bytes from memory until count is zero
tx_byte[7:0] = memdata_out[7:0];
memadr_rd = memadr_rd + 1;
memcnt_rd = memcnt_rd - 1;
transmit <= ENABLE;
end
else if(status[1] && status[0]) begin
status[0] = 1'b0;
end
else begin
// enable sample clk in case it was disabled
clk_sample_rst = DISABLE;
end
end
////
// sampling loop
////
always @(posedge clk_sample) begin
// stop writing to memory
memwe = DISABLE;
// start sampling is requesetd but sampling not started
if(status[0] && !status[1] &&
// check trigger if enabled
(!status[2] || (status[2] && (pin[7:0] & trig_en[7:0]) == trig_val[7:0])))
begin
memadr_wr = 14'h00; // start writing samples to address 0
status[1] = ENABLE; // sampling started
end
// sampling already in progress
else if(status[1]) begin
memdata_in[7:0] = pin[7:0]; // put sample to memory
memadr_wr = memadr_wr + 1; // auto advance to next address
memwe = ENABLE; // write to memory
// when address is 0 again, whole sample memory is written - done sampling
if(!memadr_wr) begin
status[1] = DISABLE;
end
end
end
reg [7:0] r_pout = 8'h0;
// create some test data on the output
always @(posedge clk_24M) begin
r_pout <= r_pout + 1;
end
assign x2en = 1'b1;
assign led[7:0] = ~r_led[7:0];
assign pout = r_pout;
endmodule
|
module crc_ccitt
#(parameter INIT = 16'hffff)
(input clk, input rst, input [7:0] d, input dv, output [15:0] crc);
wire [15:0] next_crc;
wire [15:0] crc_d = (rst ? INIT : next_crc);
r #(16) crc_r(.c(clk), .rst(1'b0), .en(dv | rst), .d(crc_d), .q(crc));
assign next_crc[0] = crc[8] ^ crc[12] ^ d[0] ^ d[4];
assign next_crc[1] = crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[2] = crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[3] = crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[4] = crc[12] ^ d[4];
assign next_crc[5] = crc[8] ^ crc[12] ^ crc[13] ^ d[0] ^ d[4] ^ d[5];
assign next_crc[6] = crc[9] ^ crc[13] ^ crc[14] ^ d[1] ^ d[5] ^ d[6];
assign next_crc[7] = crc[10] ^ crc[14] ^ crc[15] ^ d[2] ^ d[6] ^ d[7];
assign next_crc[8] = crc[0] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[9] = crc[1] ^ crc[12] ^ d[4];
assign next_crc[10] = crc[2] ^ crc[13] ^ d[5];
assign next_crc[11] = crc[3] ^ crc[14] ^ d[6];
assign next_crc[12] = crc[4] ^ crc[8] ^ crc[12] ^ crc[15] ^ d[0] ^ d[4] ^ d[7];
assign next_crc[13] = crc[5] ^ crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[14] = crc[6] ^ crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[15] = crc[7] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
endmodule
|
// $Id: c_xor_nto1.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// n-input bitwise XOR
module c_xor_nto1
(data_in, data_out);
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:bit_positions
wire [0:num_ports-1] data;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:input_ports
assign data[j] = data_in[j*width+i];
end
assign data_out[i] = ^data;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long far(long long x, long long y) { return x * x + y * y; } vector<long long> val; vector<long long> dsu; vector<long long> rang; long long pred(long long a) { if (a == dsu[a]) { return a; } else { long long to = pred(dsu[a]); if (to != dsu[a]) { val[a] *= val[dsu[a]]; } dsu[a] = to; return to; } } void unite(long long a, long long b) { a = pred(a); b = pred(b); if (a != b) { if (rang[a] < rang[b]) { swap(a, b); } if (val[a] == -1) { val[b] *= -1; } dsu[b] = a; if (rang[a] == rang[b]) { rang[a]++; } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; val.resize(n); dsu.resize(n); rang.resize(n); vector<pair<long long, long long> > x(n); vector<long long> type(n, 1); long long stx = 0, sty = 0; for (long long i = 0; i < n; i++) { cin >> x[i].first >> x[i].second; } long long p = 1e6; p = p * p; vector<long long> ind(n); for (long long i = 0; i < n; i++) { ind[i] = i; dsu[i] = i; rang[i] = 1; val[i] = 1; } for (long long i = 0; i < n - 2; i++) { for (long long j = i + 0; j < min(n, 3 + i); j++) { for (long long d = j + 1; d < min(n, 3 + i); d++) { if (far(x[j].first + x[d].first, x[j].second + x[d].second) <= p) { unite(ind[j], ind[d]); x[d].first += x[j].first; x[d].second += x[j].second; if (j != i) { x[i + 1] = x[i]; ind[i + 1] = ind[i]; } j = 3 + i; break; } else if (far(x[j].first - x[d].first, x[j].second - x[d].second) <= p) { val[pred(ind[d])] *= -1; unite(ind[j], ind[d]); x[d].first = x[j].first - x[d].first; x[d].second = x[j].second - x[d].second; if (j != i) { x[i + 1] = x[i]; ind[i + 1] = ind[i]; } j = 3 + i; break; } } } } long long p1 = 1.5e6; p1 = p1 * p1; if (n > 1) { if (far(x[n - 2].first + x[n - 1].first, x[n - 2].second + x[n - 1].second) <= p1) { unite(ind[n - 2], ind[n - 1]); } else { val[pred(ind[n - 1])] *= -1; unite(ind[n - 2], ind[n - 1]); } } for (long long i = 0; i < n; i++) { long long t = pred(i); if (t != i) { cout << val[t] * val[i] << ; } else { cout << val[i] << ; } } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: async_fifo_fwft.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An asynchronous capable parameterized FIFO. As with all
// first word fall through FIFOs, the RD_DATA will be valid when RD_EMPTY is
// low. Asserting RD_EN will consume the current RD_DATA value and cause the
// next value (if it exists) to appear on RD_DATA on the following cycle. Be sure
// to check if RD_EMPTY is low each cycle to determine if RD_DATA is valid.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module async_fifo_fwft #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "functions.vh"
reg [C_WIDTH-1:0] rData=0;
reg [C_WIDTH-1:0] rCache=0;
reg [1:0] rCount=0;
reg rFifoDataValid=0;
reg rDataValid=0;
reg rCacheValid=0;
wire [C_WIDTH-1:0] wData;
wire wEmpty;
wire wRen = RD_EN || (rCount < 2'd2);
assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;
// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will
// determine the memory option).
async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.WR_FULL(WR_FULL),
.RD_EN(wRen),
.RD_DATA(wData),
.RD_EMPTY(wEmpty)
);
always @ (posedge RD_CLK) begin
if (RD_RST) begin
rCount <= #1 0;
rDataValid <= #1 0;
rCacheValid <= #1 0;
rFifoDataValid <= #1 0;
end
else begin
// Keep track of the count
rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);
// Signals when wData from FIFO is valid
rFifoDataValid <= #1 (wRen & !wEmpty);
// Keep rData up to date
if (rFifoDataValid) begin
if (RD_EN | !rDataValid) begin
rData <= #1 wData;
rDataValid <= #1 1'd1;
rCacheValid <= #1 1'd0;
end
else begin
rCacheValid <= #1 1'd1;
end
rCache <= #1 wData;
end
else begin
if (RD_EN | !rDataValid) begin
rData <= #1 rCache;
rDataValid <= #1 rCacheValid;
rCacheValid <= #1 1'd0;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_TB_V
`define SKY130_FD_SC_LS__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_TB_V
|
#include <bits/stdc++.h> using namespace std; int now[5 * 100010], after[5 * 100010], mx[5 * 100010]; int lft[5 * 100010], rgt[5 * 100010], vi[5 * 100010], timer = 0, comp = 0; long long Add[5 * 100010]; vector<int> g[5 * 100010]; stack<int> stk; inline void dfs(int c, int p) { vi[c] = 1; now[c] = after[c] = ++timer; stk.push(c); for (auto x : g[c]) { if (x != p) { if (!vi[x]) { dfs(x, c); now[c] = min(now[c], now[x]); } else now[c] = min(now[c], now[x]); } } if (now[c] == after[c]) { lft[comp] = rgt[comp] = c; while (1) { int node = stk.top(); lft[comp] = min(lft[comp], node); rgt[comp] = max(rgt[comp], node); if (node == c) break; stk.pop(); } stk.pop(); comp++; } } int main() { int n, m; scanf( %d , &n); ; scanf( %d , &m); ; memset(vi, 0, sizeof(vi)); ; for (int x = 1; x <= m; x++) { int u, v; scanf( %d , &u); ; scanf( %d , &v); ; g[u].emplace_back(v); g[v].emplace_back(u); } for (int x = 1; x <= n; x++) if (!vi[x]) dfs(x, 0); for (int x = 1; x <= n; x++) mx[x] = n; for (int x = 0; x < comp; x++) if (lft[x] != rgt[x]) mx[lft[x]] = rgt[x] - 1; for (int x = n - 1; x >= 1; x--) mx[x] = min(mx[x + 1], mx[x]); for (int x = 1; x <= n; x++) Add[x] = Add[x - 1] + mx[x] - x + 1; int q; scanf( %d , &q); ; while (q--) { int from, to; scanf( %d , &from); ; scanf( %d , &to); ; int l = from - 1, r = to + 1, chk = from; while (l + 1 < r) { int m = l + r >> 1; if (mx[m] > to) r = m; else chk = max(chk, m), l = m; } chk = l; printf( %lld n , Add[chk] - Add[from - 1] + 1LL * (to - chk) * (to - chk + 1LL) / 2); } }
|
#include <bits/stdc++.h> using namespace std; string s; int n; int oddb, evenb, oddr, evenr; int main() { cin >> n; cin >> s; int ans = 0; for (int i = 0; i < n; i++) { if (i % 2 == 0) { if (s[i] == b ) evenb++; else if (s[i] == r ) evenr++; } else if (i % 2 == 1) { if (s[i] == r ) oddr++; else if (s[i] == b ) oddb++; } } ans = min(max(oddr, evenb), max(oddb, evenr)); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct ww { long double x, y; } a[100010]; int i, j, k, n, m, xx, yy; long double LU[100010], RU[100010], LD[100010], RD[100010]; inline bool judge(long double len) { int i, j; j = 0; for (i = 1; i <= n; i++) { for (; a[j + 1].x + len < a[i].x; j++) ; if (max(LU[j], RU[i + 1]) - min(LD[j], RD[i + 1]) <= len) return 1; } return 0; } inline bool cc1(const ww &a, const ww &b) { return a.x < b.x; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &xx, &yy); a[i].x = yy - xx, a[i].y = xx + yy; } sort(a + 1, a + n + 1, cc1); LD[0] = RD[n + 1] = 1e10; LU[0] = RU[n + 1] = -1e10; for (i = 1; i <= n; i++) LD[i] = min(LD[i - 1], a[i].y), LU[i] = max(LU[i - 1], a[i].y); for (i = n; i; i--) RD[i] = min(RD[i + 1], a[i].y), RU[i] = max(RU[i + 1], a[i].y); long double l = 0, r = 1e10, mid; for (; l + 1e-7 < r;) { mid = (l + r) / 2; if (judge(mid)) r = mid; else l = mid; } double an = r; printf( %.10lf n , an / 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long c[2000], d[2000]; long long u[2000], b[2000]; int main() { long long n, m, d; long long lpl = 0; cin >> n >> m >> d; for (int i = 0; i < m; i++) { cin >> c[i]; lpl += c[i]; } if (lpl == n) { cout << YES << endl; for (int i = 0; i < m; i++) { for (int j = 0; j < c[i]; j++) { cout << i + 1 << ; } } cout << endl; return 0; } long long st = 0; long long flag = 0; for (int i = 0; i < m; i++) { long long op = c[i]; op = n - (lpl - op) - 1; long long to = st + d; long long ss = op - c[i] + 1; if (to > ss) { u[i] = ss; st = ss + c[i] - 1; } if (to <= ss) { u[i] = to; st = to + c[i] - 1; } lpl -= c[i]; } if (st + d > n) { cout << YES << endl; for (int i = 0; i < m; i++) { for (int j = u[i]; j < u[i] + c[i]; j++) { b[j] = i + 1; } } for (int i = 1; i <= n; i++) { cout << b[i] << ; } cout << endl; } else { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 == 1) { cout << 0; return 0; } n = n / 2; if (n % 2 == 0) cout << n / 2 - 1; else cout << n / 2; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_2_V
`define SKY130_FD_SC_HDLL__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int tc, i, j, k, cs = 1, m, n, ans; { scanf( %d%d , &m, &n); if (n > m) swap(m, n); if (n == 1) ans = m; else if (n == 2) { ans = (m / 4) * 4; if (m % 4 == 1) ans += 2; else if (m % 4 == 2) ans += 4; else if (m % 4 == 3) ans += 4; } else { ans = ((m + 1) / 2) * ((n + 1) / 2); ans += (m / 2) * (n / 2); } printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_4_V
`define SKY130_FD_SC_HD__XNOR3_4_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_4_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> T ModInv(T b, T m) { return BigMod(b, m - 2, m); } template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> T POW(T B, T printf) { if (printf == 0) return 1; if (printf & 1) return B * POW(B, printf - 1); else return (POW(B, printf / 2) * POW(B, printf / 2)); } template <typename T> T Bigmod(T b, T p, T m) { if (p == 0) return 1; else if (!(p & 1)) return (Bigmod(b, p / 2, m) * Bigmod(b, p / 2, m)) % m; else return ((b % m) * Bigmod(b, p - 1, m)) % m; } template <typename T> T Dis(T x1, T y1, T x2, T y2) { return sqrt((x1 - x2 * x1 - x2) + (y1 - y2 * y1 - y2)); } template <typename T> T Angle(T x1, T y1, T x2, T y2) { return atan(double(y1 - y2) / double(x1 - x2)); } template <typename T> T DIFF(T a, T b) { T d = a - b; if (d < 0) return -d; else return d; } template <typename T> T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <typename T> T euclide(T a, T b, T &x, T &y) { if (a < 0) { T d = euclide(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = euclide(a, -b, x, y); y = -y; return d; } if (b == 0) { x = 1; y = 0; return a; } else { T d = euclide(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <typename T> void ia(T a[], int n) { for (int i = 0; i < n; i++) cin >> a[i]; } template <typename T> void pa(T a[], int n) { for (int i = 0; i < n - 1; i++) cout << a[i] << ; cout << a[n - 1] << endl; } template <typename T> long long int isLeft(T a, T b, T c) { return (a.x - b.x) * (b.y - c.y) - (b.x - c.x) * (a.y - b.y); } int Set(int N, int pos) { return N = N | (1 << pos); } int Reset(int N, int pos) { return N = N & ~(1 << pos); } bool Check(int N, int pos) { return (bool)(N & (1 << pos)); } template <class T, class first> inline T togglebit(T a, first i) { T t = 1; return (a ^ (t << i)); } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } int cdigittoint(char ch) { return ch - 0 ; } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } double DEG(double x) { return (180.0 * x) / (2.0 * acos(0.0)); } double RAD(double x) { return (x * (double)2.0 * acos(0.0)) / (180.0); } int vis[5000007]; long long int sum[5000007]; void Sieve() { vis[2] = 2; for (int i = 3; i < 5000007; i += 2) { if (!vis[i]) { vis[i] = i; for (int j = 3 * i; j < 5000007; j += i + i) vis[j] = i; } vis[i + 1] = 2; } } void Factor(int n) { int x = n; while (n != 1) { int p = vis[n]; while (n % p == 0) { sum[x]++; n /= p; } } } int main() { Sieve(); for (int i = 2; i < 5000007; i++) Factor(i), sum[i] += sum[i - 1]; int(t); scanf( %d , &t); while (t--) { int x, y; scanf( %d%d , &x, &y); printf( %lld n , sum[x] - sum[y]); } return 0; }
|
`timescale 1 ns / 1 ns
`define LATENCY_TIMEOUT 24'h1
`include "project_include.v"
module fx3_bus_out_path #(
parameter ADDRESS_WIDTH = 8 //256 32-bit values to align with
//largest packet size
)(
input clk,
input rst,
//Control
output reg o_out_path_ready, //Status Strobe detected, lock in count
input i_out_path_enable, //A buffer is available to write to
output o_out_path_busy, //Outpath is busy writing data out
output reg o_out_path_finished,//Outpath is finished writing data out
input i_dma_buf_ready, //A buffer is ready to write to
output reg o_dma_buf_finished, //A buffer has been filled or finished
//Packet size
input [23:0] i_packet_size,
input i_status_rdy_stb,
input [31:0] i_read_size,
//FX3 Interface
output reg o_write_enable,
output reg o_packet_end,
output [31:0] o_data,
//FIFO in path
output [1:0] o_rpath_ready,
input [1:0] i_rpath_activate,
output [23:0] o_rpath_size,
input [31:0] i_rpath_data,
input i_rpath_strobe
);
//Local Parameters
localparam IDLE = 4'h0;
localparam WAIT_FOR_READY = 4'h1;
localparam WRITE_TO_HOST = 4'h2;
localparam LATENCY_HOLD = 4'h3;
//Registers/Wires
reg [3:0] state;
reg [23:0] r_packet_count;
reg [32:0] r_data_out_size;
reg [31:0] r_data_out_count;
//Ping Pong FIFO
reg r_out_strobe;
wire w_out_ready;
reg r_out_activate;
wire [23:0] w_out_size;
wire [31:0] w_out_data;
reg [23:0] r_ppfifo_count;
reg [23:0] r_latency_count;
//Submodules
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH )
)pp_out(
.reset (rst ),
//Write Side
.write_clock (clk ),
.write_ready (o_rpath_ready ),
.write_activate (i_rpath_activate ),
.write_fifo_size (o_rpath_size ),
.write_strobe (i_rpath_strobe ),
.write_data (i_rpath_data ),
//Read Side
.read_clock (clk ),
.read_strobe (r_out_strobe ),
.read_ready (w_out_ready ),
.read_activate (r_out_activate ),
.read_count (w_out_size ),
// .read_data (w_out_data )
.read_data (o_data )
);
//Asynchronous Logic
assign o_out_path_busy = ((state != IDLE) && !o_out_path_finished);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
r_ppfifo_count <= 0;
r_out_strobe <= 0;
r_packet_count <= 0;
o_write_enable <= 0;
o_packet_end <= 0;
r_data_out_count <= 0;
r_data_out_size <= 0;
r_latency_count <= 0;
r_out_activate <= 0;
//Controller Interface
o_out_path_ready <= 0;
o_out_path_finished <= 0;
o_dma_buf_finished <= 0;
end
else begin
//Strobes
r_out_strobe <= 0;
o_write_enable <= 0;
o_packet_end <= 0;
//Controller Interface
o_out_path_finished <= 0;
if (i_out_path_enable) begin
o_out_path_ready <= 0;
end
if (i_out_path_enable && !o_out_path_busy) begin
o_out_path_finished <= 1;
end
//Ping Pong FIFO Interface
if (w_out_ready && !r_out_activate) begin
r_ppfifo_count <= 0;
r_out_activate <= 1;
end
else if (r_out_activate && (r_ppfifo_count >= w_out_size)) begin
//$display ("fx3_bus_out_path: Ping Pong FIFO Finished");
r_ppfifo_count <= 0;
r_out_activate <= 0;
end
//State Machine
case (state)
IDLE: begin
r_packet_count <= 0;
r_data_out_size <= 0;
o_out_path_ready <= 0;
if (i_status_rdy_stb) begin
o_out_path_ready <= 1;
r_data_out_size <= i_read_size + `STATUS_LENGTH;
r_data_out_count <= 0;
//data to send
//Account for 1 clock cycle delay upon write start
state <= WAIT_FOR_READY;
end
end
WAIT_FOR_READY: begin
if (i_dma_buf_ready && r_out_activate) begin
//$display ("fx3_bus_out_path: Write to host");
r_packet_count <= 0;
state <= WRITE_TO_HOST;
end
end
WRITE_TO_HOST: begin
if (r_data_out_count < r_data_out_size) begin
if (r_packet_count < i_packet_size) begin
if (r_out_activate && (r_ppfifo_count < w_out_size)) begin
o_write_enable <= 1;
r_out_strobe <= 1;
r_data_out_count <= r_data_out_count + 1;
r_packet_count <= r_packet_count + 1;
r_ppfifo_count <= r_ppfifo_count + 1;
if ((r_packet_count != i_packet_size - 1) &&
(r_data_out_count == r_data_out_size - 1)) begin
o_packet_end <= 1;
end
end
end
else begin
//$display ("fx3_bus_out_path: Packet Sent to FX3");
r_latency_count <= 0;
state <= LATENCY_HOLD;
o_dma_buf_finished <= 1;
end
end
else begin
o_out_path_finished <= 1;
r_out_activate <= 0;
if (!i_out_path_enable) begin
$display ("fx3_bus_out_path: Sent all data");
state <= IDLE;
end
end
//Don't write a packet larger than the packet size
//If we reached packet size go to an IDLE state
//Check if we have reached the end of this FIFO (NOTE: this shouldn't
//happen, this should be aligned with the output size
end
LATENCY_HOLD: begin
o_dma_buf_finished <= 1;
if (r_latency_count < `LATENCY_TIMEOUT) begin
r_latency_count <= r_latency_count + 1;
end
else begin
if (!i_dma_buf_ready) begin
//Wait for the controller to deassert the dma ready signal to
//continue
state <= WAIT_FOR_READY;
o_dma_buf_finished <= 0;
end
end
end
endcase
end
end
endmodule
|
`include "../network_params.h"
// A module to shift in pixels from the video stream and output a ready signal
module window_ctrl (
input clock,
input reset,
// x/y coordinates of the buffer, will be constants to start but may
// eventually change to look at different parts of the image
input [`SCREEN_X_BITWIDTH:0] buffer_x_pos,
input [`SCREEN_Y_BITWIDTH:0] buffer_y_pos,
// video stream in
input [`SCREEN_X_BITWIDTH:0] screen_x, // the x coordinate of the current pixel input
input [`SCREEN_Y_BITWIDTH:0] screen_y, // the y coordinate of the current pixel input
// input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
// window/ buffer control signals
output reg shift_up,
output reg shift_left,
// mult_adder tree ready signal to indicate valid data
// will strobe once when data is ready
output reg buffer_rdy
);
// wire declarations
// reg declarations
// shift left control
always@(posedge clock or negedge reset) begin
if(reset == 1'b0) begin
shift_left <= 1'd0;
end else if( screen_x >= buffer_x_pos &&
screen_x < buffer_x_pos + `SCREEN_X_WIDTH'd`BUFFER_W &&
screen_y >= buffer_y_pos &&
screen_y < buffer_y_pos + `SCREEN_Y_WIDTH'd`BUFFER_H
)
shift_left <= 1'd1;
else
shift_left <= 1'd0;
end // always
// shift up control
always@(posedge clock or negedge reset) begin
if(reset == 1'b0) begin
shift_up <= 1'd0;
end else if (screen_x == buffer_x_pos + `SCREEN_X_WIDTH'd`BUFFER_W &&
screen_y >= buffer_y_pos &&
screen_y < buffer_y_pos + `SCREEN_Y_WIDTH'd`BUFFER_H - 1
)
shift_up <= 1'd1;
else
shift_up <= 1'd0;
end // always
// buffer ready control
always@(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
buffer_rdy <= 1'b0;
end else if( screen_x == buffer_x_pos + `SCREEN_X_WIDTH'd`BUFFER_W &&
screen_y == buffer_y_pos + `SCREEN_Y_WIDTH'd`BUFFER_H)
// the buffer is full
buffer_rdy <= 1'b1;
else
buffer_rdy <= 1'b0;
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, x, len, dir, t, y; bool fin; pair<int, int> a[210000]; int loc[210000]; int binary_right(int x, int t) { int l = x, r = n, mid; while (l < r) { mid = (l + r + 1) / 2; if (a[mid].first <= t) l = mid; else r = mid - 1; } return l; } int binary_left(int x, int t) { int l = 1, r = x, mid; while (l < r) { mid = (l + r) / 2; if (a[mid].first >= t) r = mid; else l = mid + 1; } return l; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) loc[a[i].second] = i; for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &len); x = loc[x]; dir = 1; fin = 0; while (!fin) { t = a[x].first + dir * len; if (dir == 1) { y = binary_right(x, t); if (binary_left(y, a[y].first - (len - a[y].first + a[x].first)) == x) { if (y == x) fin = 1; else len %= 2 * (a[y].first - a[x].first); } else { dir = -1; len -= (a[y].first - a[x].first); x = y; } } else { y = binary_left(x, t); if (binary_right(y, a[y].first + (len - a[x].first + a[y].first)) == x) { if (y == x) fin = 1; else len %= 2 * (a[x].first - a[y].first); } else { dir = 1; len -= (a[x].first - a[y].first); x = y; } } } printf( %d n , a[x].second); } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int alpha[26], kitta = 0; for (int i = 0; i < 26; i++) alpha[i] = 0; for (int i = 0; i < s.length(); i++) { alpha[s[i] - a ]++; if (alpha[s[i] - a ] == 1) kitta++; } if (kitta > 4 || kitta < 2) { cout << No ; return 0; } for (int i = 0; i < s.length(); i++) { if (alpha[s[i] - a ] > 1) { kitta++; alpha[s[i] - a ] = 1; } } if (kitta > 3) cout << Yes ; else cout << No ; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: eight_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module eight_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/eight_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/eight_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL eight_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d, e, f; cin >> a >> b; c = a / 2; if (b < c || (a == 1 && b != 0)) cout << -1; else if (a == 1 && b == 0) cout << 1; else if (b % c == 0) { e = b / c; if (b / c != 1) { for (int i = 0; i < a; i++) { cout << e << ; e += (b / c); } } else { for (int i = 0; i < a; i++) { cout << e << ; e += 1; } } } else { f = b / c; e = b / c + b % c; cout << e << << 2 * e << << f << ; if (b / c != 1) { for (int i = 3; i < a; i++) { if (b / c + f != 2 * e && b / c + f != e) cout << (b / c) + f << ; else { f += b / c; cout << b / c + f << ; } f += (b / c); } } else { for (int i = 3; i < a; i++) { cout << (e * e + 1) + f << ; f += 1; } } } return 0; }
|
module fifo_top
#(
parameter DEPTH = 32,
WIDTH = 32,
ADDR = 5
)
(
input wire write, wreset_b, wclk, read, rreset_b, rclk,
input wire [WIDTH-1:0] wdata,
output wire [WIDTH-1:0] rdata,
output wire rempty, wfull
);
// function to convert from gray to binary
function [ADDR:0] G2B_Fn;
input [ADDR:0] gray;
reg [ADDR:0] binary;
integer i;
begin
binary[ADDR] = gray [ADDR];
for (i=ADDR-1;i >= 0;i=i-1)
binary[i] = (binary[i+1] ^ gray[i]);
G2B_Fn = binary;
end
endfunction
// declare connecting wires
wire [ADDR:0] wptr_b,wptr_g, // binary and gray signals from write pointer
rptr_b,rptr_g; // binary and gray signals from read pointer
reg [ADDR:0] g2b_wd_op, // function G2B_Fn output in the write domain
g2b_rd_op; // function G2B_Fn output in the read domain
wire [ADDR:0] g2b_wd_ip, // function G2B_Fn input in the write domain
g2b_rd_ip; // function G2B_Fn input in the read domain
//assign intermediate wires
always @(g2b_wd_ip or g2b_rd_ip)
begin
g2b_wd_op = G2B_Fn(g2b_wd_ip);
g2b_rd_op = G2B_Fn(g2b_rd_ip);
end
// instantiate write pointer
pointer wptr(
.clk(wclk),
.reset_b(wreset_b),
.op(write),
.fifo_status(wfull),
.gray(wptr_g),
.binary(wptr_b)
);
//instantiate read pointer
pointer rptr(
.clk(rclk),
.reset_b(rreset_b),
.op(read),
.fifo_status(rempty),
.gray(rptr_g),
.binary(rptr_b)
);
//instantiate memory module
memory m1(
.clk(wclk),
.reset_b(wreset_b),
.write(write),
.wfull(wfull),
.waddr(wptr_b[ADDR-1:0]),
.raddr(rptr_b[ADDR-1:0]),
.wdata(wdata),
.rdata(rdata)
);
//instantiate read->write synchronizer
sync_r2w syncr2w(
.clk(wclk),
.reset_b(wreset_b),
.rptr(rptr_g),
.rptr_wr(g2b_wd_ip)
);
//instantiate write->read synchronizer
sync_w2r syncw2r(
.clk(rclk),
.reset_b(rreset_b),
.wptr(wptr_g),
.wptr_rd(g2b_rd_ip)
);
//instantiate write domain comparator
compare_wr cmp_wr(
.rptr(g2b_wd_op),
.wptr(wptr_b),
.full(wfull)
);
//instantiate write domain comparator
compare_rd cmp_rd(
.rptr(rptr_b),
.wptr(g2b_rd_op),
.empty(rempty)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 7; long long n, m, a[maxn], b[maxn]; vector<long long> vt[100]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 1; i <= n; i++) { cin >> b[i]; long long gau = b[i]; long long dem = 0; while (gau > 0) { gau >>= 1; dem++; } vt[--dem].push_back(b[i]); } bool d = true; long long gau = 0; for (long long i = 1; i <= n; i++) { if (!d) return cout << No , 0; d = false; for (long long j = 0; j <= 61; j++) { if (((gau >> j) & 1) != 0 || vt[j].empty()) continue; gau ^= vt[j].back(); a[i] = vt[j].back(); vt[j].pop_back(); d = true; break; } } if (!d) return cout << No , 0; cout << Yes << n ; for (long long i = 1; i <= n; i += 1) cout << a[i] << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int n, dp, q, c, b; string ans = ; void update(int &x) { if (x == 0) x = 1; else x = 0; } int main() { scanf( %d , &n); int a[n][n]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) scanf( %d , &a[i][j]); } for (int i = 0; i < n; i++) dp = (dp + a[i][i]) % 2; scanf( %d , &q); while (q--) { scanf( %d , &b); if (b == 3) { printf( %d , dp); } else { scanf( %d , &c); update(dp); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int s = 0; s = n * (n); s = s + (n - 1) * (n - 1); cout << s; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using ull = unsigned long long int; bool odd(ll num) { return ((num & 1) == 1); } bool even(ll num) { return ((num & 1) == 0); } ll sum(ll n) { return ((n * (n + 1)) / 2); } ll ceil(ll a, ll b) { return ((a + (b - 1)) / b); } void InputOutput() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } ll calculation(vector<ll> &v, ll k) { ll dis, cnt, len, index; dis = cnt = 0; len = (ll)v.size(); len -= k; index = len - 1; for (ll i = len - 1; i >= 0; i--) { cnt++; if (cnt == k) { dis += (v[index] * 2); cnt = 0; index = i - 1; } } if (cnt) dis += (v[index] * 2); return dis; } void solve() { ll n, k; cin >> n >> k; vector<ll> pos, neg; ll temp, dis; for (ll i = 0; i < n; i++) { cin >> temp; if (temp < 0) neg.push_back(abs(temp)); else if (temp > 0) pos.push_back(temp); } if (pos.empty() and neg.empty()) { cout << 0 << n ; return; } sort(pos.begin(), pos.end()); sort(neg.begin(), neg.end()); dis = 0; dis += calculation(pos, k); dis += calculation(neg, k); if (pos.empty()) dis += neg.back(); else if (neg.empty()) dis += pos.back(); else { if (pos.back() < neg.back()) { dis += (pos.back() * 2); dis += neg.back(); } else { dis += (neg.back() * 2); dis += pos.back(); } } cout << dis << n ; } int main() { InputOutput(); int t = 1; cin >> t; for (int test_case = 1; test_case <= t; test_case++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int from[101], to[101], p; int main() { int n, m, x, y; cin >> n >> m; memset(to, -1, sizeof to); for (int i = 1; i <= n; i++) { cin >> x >> y; for (int j = x; j <= y; j++) to[j] = max(to[j], y); } int now = 0; for (; now <= m;) { if (to[now] == -1 || to[now] == now) break; if (now == m || (now <= m and to[now] >= m)) { cout << YES ; return 0; } now = to[now]; } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const long long _INF = 0x7ffffffffffffffll; const double EPS = 1e-9; const double PI = acos(-1.0); template <class T, class INT> inline T pow(T x, INT y) { T res(1); for (T tt(x); y; y /= 2) { if (y & 1) res *= tt; tt *= tt; } return res; } template <class T, class INT> inline T pow(T x, INT y, T p) { T res(1); for (T tt(x); y; y /= 2) { if (y & 1) res = res * tt % p; tt = tt * tt % p; } return res; } int toInt(string s) { int x = 0; istringstream sin(s); sin >> x; return x; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class INT> inline INT gcd(INT x, INT y) { return y ? gcd(y, x % y) : x; } template <class INT> inline int calc_bits(INT x) { return x ? (x & 1) + calc_bits(x >> 1) : 0; } const int MAXN = 1000 + 10; int n, m, cnt, r[MAXN], c[MAXN], u[MAXN], d[MAXN]; string a[MAXN]; double ans; inline long long calc(int x, int n) { return (n - x) * (n - x - 1) / 2 + (x + 1) * x / 2; } int main(int argc, char* argv[]) { cin >> n >> m; for (int i = 0; i < (n); ++i) cin >> a[i]; cnt = n * m; memset(r, 255, sizeof(r)), memset(c, 255, sizeof(c)); for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) if (a[i][j] == X ) r[i] = j, c[j] = i, --cnt; for (int i = 0; i < (n); ++i) { u[i] = r[i]; d[i] = m - r[i] - 1; if (r[i] != -1) { if (i && r[i - 1] != -1 && r[i - 1] < r[i]) u[i] += u[i - 1]; if (i && r[i - 1] != -1 && r[i - 1] > r[i]) d[i] += d[i - 1]; } } for (int i = (n - 1); i > (-1); --i) if (r[i] != -1) { if (i < n - 1 && r[i + 1] != -1 && r[i + 1] < r[i]) u[i] += u[i + 1]; if (i < n - 1 && r[i + 1] != -1 && r[i + 1] > r[i]) d[i] += d[i + 1]; } for (int i = 0; i < (m); ++i) ans += n * n * calc(i, m); for (int i = 0; i < (n); ++i) for (int j = 0; j < (n); ++j) { ans += (r[i] == -1 ? m : m - 1) * (r[j] == -1 ? m : m - 1) * abs(i - j); if (i == j && r[i] != -1) ans += 2 * (u[i] * (m - r[i] - 1) + d[i] * r[i]); if (r[i] != -1) ans -= calc(r[i], m); if (r[j] != -1) ans -= calc(r[j], m); if (r[i] != -1 && r[j] != -1) ans += abs(r[i] - r[j]); } for (int i = 0; i < (m); ++i) { u[i] = c[i]; d[i] = n - c[i] - 1; if (c[i] != -1) { if (i && c[i - 1] != -1 && c[i - 1] < c[i]) u[i] += u[i - 1]; if (i && c[i - 1] != -1 && c[i - 1] > c[i]) d[i] += d[i - 1]; } } for (int i = (m - 1); i > (-1); --i) if (c[i] != -1) { if (i < m - 1 && c[i + 1] != -1 && c[i + 1] < c[i]) u[i] += u[i + 1]; if (i < m - 1 && c[i + 1] != -1 && c[i + 1] > c[i]) d[i] += d[i + 1]; } for (int i = 0; i < (m); ++i) if (c[i] != -1) ans += 2 * (u[i] * (n - c[i] - 1) + d[i] * c[i]); cout << setprecision(8) << fixed << ans / cnt / cnt << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, t; int n; int a[100005]; int b[100005]; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(a, a + n); int cnt = 0; for (i = 0; i < n; i++) { if (a[i] != b[i]) cnt++; } if (cnt == 0 || cnt == 2) printf( YES n ); else printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int parent[300005], maxLen[300005]; int findRoot(int u) { int root = u; while (parent[root] != root) { root = parent[root]; } while (parent[u] != root) { int y = parent[u]; parent[u] = root; u = y; } return root; } void unionNum(int u, int v) { int ru = findRoot(u), rv = findRoot(v); if (ru == rv) return; if (maxLen[ru] > maxLen[rv]) { parent[rv] = ru; maxLen[ru] = max(maxLen[ru], maxLen[ru] / 2 + maxLen[rv] / 2 + maxLen[ru] % 2 + maxLen[rv] % 2 + 1); } else { swap(ru, rv); parent[rv] = ru; maxLen[ru] = max(maxLen[ru], maxLen[ru] / 2 + maxLen[rv] / 2 + maxLen[ru] % 2 + maxLen[rv] % 2 + 1); } } int visited[300005] = {0}; bool nVis(int &i, int n) { while (i <= n && visited[i] == 1) i++; if (i <= n) return true; return false; } void dfs(int node, vector<int> child[]) { map<int, int> v1, v2, d1, d2; stack<int> myStack; myStack.push(node); v1[node] = 1; d1[node] = 0; visited[node] = 1; while (!myStack.empty()) { int y = myStack.top(); myStack.pop(); for (size_t i = 0; i < child[y].size(); i++) { if (v1[child[y][i]] == 0) { v1[child[y][i]] = 1; d1[child[y][i]] = d1[y] + 1; myStack.push(child[y][i]); visited[child[y][i]] = 1; } } } for (map<int, int>::iterator it = d1.begin(); it != d1.end(); it++) { if (d1[node] < it->second) { node = it->first; } } myStack.push(node); d2[node] = 0; v2[node] = 1; while (!myStack.empty()) { int y = myStack.top(); myStack.pop(); parent[y] = node; for (size_t i = 0; i < child[y].size(); i++) { if (v2[child[y][i]] == 0) { v2[child[y][i]] = 1; d2[child[y][i]] = d2[y] + 1; maxLen[node] = max(maxLen[node], d2[child[y][i]]); myStack.push(child[y][i]); } } } } int main() { int n, m, q, a, b; scanf( %d%d%d , &n, &m, &q); for (int i = 0; i <= n; i++) { parent[i] = i; maxLen[i] = 0; } vector<int> child[n + 1]; for (int i = 0; i < m; i++) { scanf( %d%d , &a, &b); child[a].push_back(b); child[b].push_back(a); } int i = 1; while (nVis(i, n)) { dfs(i, child); } while (q--) { int type; scanf( %d , &type); if (type == 1) { scanf( %d , &a); printf( %d n , maxLen[findRoot(a)]); } else { scanf( %d%d , &a, &b); unionNum(a, b); } } }
|
//`define ENABLE_ADC
//`define ENABLE_AUD
//`define ENABLE_CLOCK2
//`define ENABLE_CLOCK3
//`define ENABLE_CLOCK4
`define ENABLE_CLOCK
//`define ENABLE_DRAM
//`define ENABLE_FAN
`define ENABLE_FPGA
`define ENABLE_GPIO
`define ENABLE_HEX
//`define ENABLE_HPS
//`define ENABLE_IRDA
`define ENABLE_KEY
`define ENABLE_LEDR
//`define ENABLE_PS2
//`define ENABLE_TD
//`define ENABLE_VGA
`define ENABLE_SW
module de1_soc(
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
`endif
`ifdef ENABLE_SW
input [9:0] SW
`endif
);
// wires & inputs
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule
|
#include <bits/stdc++.h> using namespace std; deque<int> A, B; long long p, i, j, k, n, m, aux; long long fact(int a) { long long f = 1; int i; for (int i = (int)(1); i <= (int)(a); ++i) f *= i; return f; } int main(void) { cin >> p; cin >> n; for (int i = (int)(1); i <= (int)(n); ++i) { cin >> aux; A.push_back(aux); } cin >> n; for (int i = (int)(1); i <= (int)(n); ++i) { cin >> aux; B.push_back(aux); } long long step(0); long long stari = fact(p + 1); while (step <= stari) { if (A.empty()) return cout << step << << 2, 0; if (B.empty()) return cout << step << << 1, 0; ++step; int x = A.front(); A.pop_front(); int y = B.front(); B.pop_front(); if (x < y) { B.push_back(x); B.push_back(y); } else { A.push_back(y); A.push_back(x); } } cout << -1 ; return 0; }
|
module execute(clk, signe,signe2, rse,rse2, rte,rte2, rde,rde2,signimme,signimme2,mux1after,mux1after2,mux2after,mux2after2,resultw,resultw2,aluoutm,aluoutm2,
alucontrole,alucontrole2,alusrce,alusrce2,multsele,multsele2,regdste,regdste2,forwardae,forwardae2,forwardbe,forwardbe2,writerege,writerege2,
solutione,solutione2,writedatae,writedatae2,multready,multready2);
input clk, alusrce,alusrce2, regdste,regdste2, signe,signe2, multsele,multsele2;
input [4:0] rse,rse2, rte, rte2,rde,rde2;
input [31:0] signimme,signimme2, mux1after,mux1after2, mux2after,mux2after2, resultw,resultw2, aluoutm,aluoutm2;
input [2:0] alucontrole,alucontrole2;
input [2:0] forwardae,forwardae2, forwardbe,forwardbe2;
output [4:0] writerege,writerege2;
output [31:0] solutione,solutione2, writedatae,writedatae2;
output multready,multready2;
wire [31:0] srcae,srcae2,srcbe,srcbe2, aluoute,aluoute2, LSB,LSB2;
wire zero,zero2;
wire [63:0] product,product2;
assign LSB = product[31:0];
assign LSB2 = product2[31:0];
mux2 #(5) mux2execute(rte,rde,regdste,writerege);
mux5 #(32) mux3alu1(mux1after,resultw,aluoutm,aluoutm2,resultw2,forwardae,srcae);
mux5 #(32) mux3alu2(mux2after,resultw,aluoutm,aluoutm2,resultw2,forwardbe,writedatae);
mux2 #(32) mux2alu(writedatae,signimme,alusrce,srcbe);
alu alu(srcae, srcbe, signe, alucontrole, aluoute, zero);
multiplier mult(clk, signe, multsele, srcae, srcbe, product, multready);
mux2 #(32) multalu(aluoute, LSB, multsele, solutione);
mux2 #(5) mux2execute2(rte2,rde2,regdste2,writerege2);
mux6 #(32) mux3alu1_2(mux1after2,resultw2,aluoutm2,solutione,aluoutm,resultw,forwardae2,srcae2);
mux6 #(32) mux3alu2_2(mux2after2,resultw2,aluoutm2,solutione,aluoutm,resultw,forwardbe2,writedatae2);
mux2 #(32) mux2alu2(writedatae2,signimme2,alusrce2,srcbe2);
alu alu2(srcae2, srcbe2, signe2, alucontrole2, aluoute2, zero2);
multiplier mult2(clk, signe2, multsele2, srcae2, srcbe2, product2, multready2);
mux2 #(32) multalu2(aluoute2, LSB2, multsele2, solutione2);
endmodule
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long &a) { a %= 1000000007; (a < 0) && (a += 1000000007); } inline long long modMul(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a * b) % 1000000007; } inline long long modAdd(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a + b) % 1000000007; } inline long long modSub(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { normal(a); return modPow(a, 1000000007 - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; int n, a[15][15], num[15][15], cur[105], dp[2][5][5][105], lagbe[2][5][105]; vector<int> vt[5][105]; int knightx[] = {-2, -2, +2, +2, -1, -1, +1, +1}; int knighty[] = {-1, +1, -1, +1, +2, -2, +2, -2}; void valid(int ro, int col) { for (int i = 0; i < 8; i++) { int tmp = ro + knightx[i]; int tpp = col + knighty[i]; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[1][num[ro][col]].push_back(num[tmp][tpp]); } for (int i = 1; i <= 10; i++) { int tmp = ro + i; int tpp = col + i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[2][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro - i; tpp = col - i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[2][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro + i; tpp = col - i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[2][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro - i; tpp = col + i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[2][num[ro][col]].push_back(num[tmp][tpp]); } for (int i = 1; i <= 10; i++) { int tmp = ro + i; int tpp = col; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[3][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro - i; tpp = col; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[3][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro; tpp = col + i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[3][num[ro][col]].push_back(num[tmp][tpp]); tmp = ro; tpp = col - i; if (tmp > 0 && tmp <= n && tpp > 0 && tpp <= n) vt[3][num[ro][col]].push_back(num[tmp][tpp]); } } bool one(int beg, int fin, int ro, int col, int &mov, int &change) { if (ro == col) { change++; return true; } if (beg != fin) return false; for (int i = 0; i < vt[beg][ro].size(); i++) if (vt[beg][ro][i] == col) { mov++; return true; } return false; } bool berkoro(int num, int beg, int fin, int ro, int col, int &mov, int &change) { int res = 0, val1 = 0, val2 = 0; if (num == 1) return one(beg, fin, ro, col, mov, change); for (int i = 0, tmp; !res && i < vt[beg][ro].size(); i++) { tmp = vt[beg][ro][i]; val1 = 1, val2 = 0; res |= berkoro(num - 1, beg, fin, tmp, col, val1, val2); } for (int i = 1; !res && i <= 3; i++) { if (beg == i) continue; val2 = 1, val1 = 0; res |= berkoro(num - 1, i, fin, ro, col, val1, val2); } if (res) mov += val1, change += val2; return res; } void process(int beg, int fin, int ro, int col, int &mov, int &change) { for (int i = 1; i <= 4; i++) { mov = 0, change = 0; if (berkoro(i, beg, fin, ro, col, mov, change)) return; } } void process(int mark, int pos, int &mov, int &change) { int &ret1 = lagbe[0][mark][pos]; int &ret2 = lagbe[1][mark][pos]; if (ret1 != -1) { mov += ret1; change += ret2; return; } if (pos == n * n) return; int val1 = 0, val2 = 0, res1 = 1e9, res2 = 1e9; if (pos == 1) { for (int i = 1; i <= 3; i++) for (int j = 1; j <= 3; j++) { val1 = dp[0][i][j][pos], val2 = dp[1][i][j][pos]; process(j, pos + 1, val1, val2); if (val1 + val2 < res1 + res2) res1 = val1, res2 = val2; else if (val1 + val2 == res1 + res2 && val2 < res2) res1 = val1, res2 = val2; } } else { for (int i = 1; i <= 3; i++) { val1 = dp[0][mark][i][pos], val2 = dp[1][mark][i][pos]; process(i, pos + 1, val1, val2); if (val1 + val2 < res1 + res2) res1 = val1, res2 = val2; else if (val1 + val2 == res1 + res2 && val2 < res2) res1 = val1, res2 = val2; } } mov += res1, change += res2; ret1 = res1, ret2 = res2; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 1, cnt = 1; i <= n; i++) for (int j = 1; j <= n; j++) { cin >> a[i][j]; num[i][j] = cnt; cur[a[i][j]] = cnt; cnt++; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) valid(i, j); for (int i = 1; i < n * n; i++) { for (int k = 1; k <= 3; k++) for (int l = 1; l <= 3; l++) process(k, l, cur[i], cur[i + 1], dp[0][k][l][i], dp[1][k][l][i]); } memset(lagbe, -1, sizeof(lagbe)); int mov = 0, change = 0; process(0, 1, mov, change); cout << mov + change << << change << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long int> v1, v2; vector<char> v4; string s1, s2, s3; long long int visited[2000005]; set<char> st; set<long long int>::iterator it; int main() { long long int a, b, c, d, e, f, i, j, k, cnt1 = 0, cnt2 = 0, sum1 = 0, sum2 = 0, first, chk1 = 0, chk2 = 0, T; cin >> a >> b; char xx; long long int indx, chk = 0; cin >> s1; s2 = s1; for (i = 0; i < a; i++) { if (visited[i] == 0) { v1.push_back(i); for (j = i; j < a; j += b) { visited[j] = 1; s1[j] = s1[i]; } } } for (i = 0; i < a; i++) { if (s1[i] > s2[i]) { chk = 1; for (j = 0; j < v1.size(); j++) { if (v1[j] > i) { for (int k = v1[j]; k < a; k += b) { s1[k] = 0 ; } } } break; } else if (s1[i] == s2[i]) cnt1++; else { first = i; break; } } if (cnt1 == a) chk = 1; if (chk == 0) { long long int x = upper_bound(v1.begin(), v1.end(), first) - v1.begin(); x--; xx = s1[v1[x]]; if (xx == 9 ) { for (i = x - 1; i >= 0; i--) { if (s1[v1[i]] != 9 ) { xx = s1[v1[i]] + 1; for (j = v1[i]; j < a; j += b) { s1[j] = xx; } for (j = i + 1; j < v1.size(); j++) { if (s1[v1[j]] != 0 ) { for (int k = v1[j]; k < a; k += b) { s1[k] = 0 ; } } } break; } } } else { for (i = v1[x]; i < a; i += b) { s1[i] = xx + 1; } } } cout << s1.size() << endl; cout << s1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, x = 0; cin >> n >> m >> k; if (n + m - 2 < k) { cout << -1; return 0; } if (m > n) swap(m, n); if (k < m) x = n * (m / (k + 1)); if (k < n) x = max(x, m * (n / (k + 1))); if (k >= n) x = m / (k - n + 2); cout << x; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int q; scanf( %d , &q); while (q--) { int l, r, d; scanf( %d %d %d , &l, &r, &d); if (d < l) printf( %d n , d); else if (d > r) printf( %d n , d); else { int res = r - d; res = res % d; printf( %d n , r + d - res); } } }
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#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-8; const int N = 1e5 + 10; int n, q; int sgn(long double x) { return x < -EPS ? -1 : x > EPS; } struct Point { Point() {} long double x, y; Point(long double x, long double y) : x(x), y(y) {} void read() { cin >> x >> y; } Point operator-(const Point& p) { return Point(x - p.x, y - p.y); } long double operator*(const Point& p) { return x * p.x + y * p.y; } long double operator^(const Point& p) { return x * p.y - y * p.x; } long double length() { return hypotl(x, y); } } poly[N]; using Vec = Point; long double getIntersection(Point p, Vec v, Point q, Vec w) { return (w ^ (p - q)) / (v ^ w); } long double work(Point p, Vec v) { long double ret = 0; vector<pair<long double, int> > pos; for (int i = 1; i <= n; i++) { int s1 = sgn(v ^ (poly[i] - p)); int s2 = sgn(v ^ (poly[i + 1] - p)); if (s1 == s2) continue; long double o = getIntersection(p, v, poly[i], poly[i + 1] - poly[i]); if (s1 > s2) pos.push_back({o, s1 && s2 ? 2 : 1}); else pos.push_back({o, s1 && s2 ? -2 : -1}); } sort(pos.begin(), pos.end()); int flag = 0; for (int i = 0; i + 1 < pos.size(); i++) { flag += pos[i].second; if (flag) ret += pos[i + 1].first - pos[i].first; } return ret * v.length(); } int main() { ios ::sync_with_stdio(false); cin >> n >> q; for (int i = 1; i <= n; i++) poly[i].read(); poly[n + 1] = poly[1]; while (q--) { Point a, b; a.read(); b.read(); cout << fixed << setprecision(20) << work(a, b - a) << endl; } return 0; }
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// Simple Register file model by Ali Jahanian
// Students should not used reg_bank as a descrete moule. It is recommended to use the internal part of the code inside mips_core module.
// In this model, only writing to register bank is synchronized with clock and reading is not synchonized with clock.
// For any problem, contact
module regfile(clk, raddr1, dout1, raddr2, dout2, wr, waddr, din, ram1, ram2, ram3);
input clk;
input wr;
input [4:0] raddr1, raddr2, waddr;
input [31:0] din;
output reg[31:0] dout1, dout2;
output wire[31:0] ram1;
output wire[31:0] ram2;
output wire[31:0] ram3;
reg [31:0] ram [0:31];
assign ram1 = ram[5'b00001];
assign ram2 = ram[5'b00010];
assign ram3 = ram[5'b00011];
// Start of internal part
always @(posedge clk)
begin
//ram[5'b00001] = 32'd3;
//ram[5'b00010] = 32'd5;
if (wr == 1'b1)
begin
ram[waddr] = din;
end
end
always @(negedge clk)
begin
dout1 <= (raddr1 == 5'b0) ? 32'b0 : ram[raddr1];
dout2 <= (raddr2 == 5'b0) ? 32'b0 : ram[raddr2];
end
// End of internal part
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = (int)5e3 + 10; const int MOD = (int)1e9 + 7; long long dp[1111][1111]; int num[1111], k; int mark[1111]; long long dfs(int pos, int x, int flag) { if (pos == 0) return mark[x] == k - 1 && (x != 0); if (dp[pos][x] != -1 && !flag) { return dp[pos][x]; } long long ans = 0; int ed = flag ? num[pos] : 1; for (int i = 0; i <= ed; i++) { ans += dfs(pos - 1, x + i, flag && i == ed); ans %= MOD; } if (!flag) dp[pos][x] = ans; return ans; } char str[1111]; long long solve() { memset(dp, -1, sizeof(dp)); int len = 0, l = strlen(str + 1); for (int i = l; i >= 1; i--) { num[++len] = str[i] - 0 ; } if (k == 0) return 1; if (k == 1) return len - 1; return dfs(len, 0, 1); } int work(int x) { int re = 0; while (x) { re++; x -= x & (-x); } return re; } void init() { mark[1] = 0; for (int i = 2; i <= 1000; i++) mark[i] = mark[work(i)] + 1; } int main() { init(); scanf( %s , str + 1); scanf( %d , &k); printf( %lld n , solve()); return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <typename T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <typename T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <typename T> inline void println(T first) { print(first), putchar( n ); } template <typename T> inline void printsp(T first) { print(first), putchar( ); } template <class T, class T1> inline void print(T first, T1 second) { printsp(first), println(second); } template <class T, class T1, class T2> inline void print(T first, T1 second, T2 z) { printsp(first), printsp(second), println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int first[1555], second[1555]; int ans[1555], sz[1555]; vector<int> adj[1555]; void dfs(int u, int fa = -1) { sz[u] = 1; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == fa) continue; dfs(v, u); sz[u] += sz[v]; } } long double alp[1555][1555]; int id0; bool cmp(int u, int v) { return alp[u][id0] + 1e-14 < alp[v][id0]; } int id[1555]; void solve(int u, int fa, int *id, int n) { if (n == 1) { ans[id[0]] = u; return; } for (int i = 1; i < n; i++) { if (second[id[i]] < second[id[0]]) swap(id[0], id[i]); } ans[id[0]] = u; id0 = id[0]; sort(id + 1, id + n, cmp); int st = 1; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == fa) continue; solve(v, u, id + st, sz[v]); st += sz[v]; } } int main() { srand(time(NULL)); int n; gn(n); for (int i = 1; i < n; i++) { int u, v; gn(u, v); u--; v--; adj[u].push_back(v); adj[v].push_back(u); } int u = rand() % n; dfs(u); for (int i = 0; i < n; i++) gn(first[i], second[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) if (i != j) alp[i][j] = atan2l(second[j] - second[i], first[j] - first[i]); } for (int i = 0; i < n; i++) id[i] = i; solve(u, -1, id, n); for (int i = 0; i < n; i++) printsp(ans[i] + 1); return 0; }
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//date:2016/3/14
//engineer :ZhaiShaoMin
// module function :unite all four ring_node together
module whole_system(//input
clk,
rst
);
input clk;
input rst;
wire en_local_req_1; // to previous node refer to below notes
wire en_local_rep_1;
wire en_pass_req_1; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_1; // refer to notes below
wire [3:0] used_slots_pass_req_1;
wire [3:0] used_slots_pass_rep_1;
wire [15:0] flit_out_1;
wire [1:0] ctrl_out_1;
wire [1:0] dest_fifo_out_1;
wire en_local_req_2; // to previous node refer to below notes
wire en_local_rep_2;
wire en_pass_req_2; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_2; // refer to notes below
wire [3:0] used_slots_pass_req_2;
wire [3:0] used_slots_pass_rep_2;
wire [15:0] flit_out_2;
wire [1:0] ctrl_out_2;
wire [1:0] dest_fifo_out_2;
wire en_local_req_3; // to previous node refer to below notes
wire en_local_rep_3;
wire en_pass_req_3; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_3; // refer to notes below
wire [3:0] used_slots_pass_req_3;
wire [3:0] used_slots_pass_rep_3;
wire [15:0] flit_out_3;
wire [1:0] ctrl_out_3;
wire [1:0] dest_fifo_out_3;
wire en_local_req_4; // to previous node refer to below notes
wire en_local_rep_4;
wire en_pass_req_4; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep_4; // refer to notes below
wire [3:0] used_slots_pass_req_4;
wire [3:0] used_slots_pass_rep_4;
wire [15:0] flit_out_4;
wire [1:0] ctrl_out_4;
wire [1:0] dest_fifo_out_4;
// instance of node1
ring_node node1(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_4), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_4),
.dest_fifo_in(dest_fifo_out_4),
.en_local_req_in(en_local_req_4),
.en_local_rep_in(en_local_rep_4),
.en_pass_req_in(en_pass_req_4),
.en_pass_rep_in(en_pass_rep_4),
.used_slots_pass_req_in(used_slots_pass_req_4),
.used_slots_pass_rep_in(used_slots_pass_rep_4),
//output
.en_local_req(en_local_req_1), // to previous node refer to below notes
.en_local_rep(en_local_rep_1),
.en_pass_req(en_pass_req_1), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_1), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_1),
.used_slots_pass_rep(used_slots_pass_rep_1),
.flit_out(flit_out_1),
.ctrl_out(ctrl_out_1),
.dest_fifo_out(dest_fifo_out_1)
);
// instance of node2
ring_node node2(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_1), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_1),
.dest_fifo_in(dest_fifo_out_1),
.en_local_req_in(en_local_req_1),
.en_local_rep_in(en_local_rep_1),
.en_pass_req_in(en_pass_req_1),
.en_pass_rep_in(en_pass_rep_1),
.used_slots_pass_req_in(used_slots_pass_req_1),
.used_slots_pass_rep_in(used_slots_pass_rep_1),
//output
.en_local_req(en_local_req_2), // to previous node refer to below notes
.en_local_rep(en_local_rep_2),
.en_pass_req(en_pass_req_2), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_2), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_2),
.used_slots_pass_rep(used_slots_pass_rep_2),
.flit_out(flit_out_2),
.ctrl_out(ctrl_out_2),
.dest_fifo_out(dest_fifo_out_2)
);
// instance of node3
ring_node node3(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_2), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_2),
.dest_fifo_in(dest_fifo_out_2),
.en_local_req_in(en_local_req_2),
.en_local_rep_in(en_local_rep_2),
.en_pass_req_in(en_pass_req_2),
.en_pass_rep_in(en_pass_rep_2),
.used_slots_pass_req_in(used_slots_pass_req_2),
.used_slots_pass_rep_in(used_slots_pass_rep_2),
//output
.en_local_req(en_local_req_3), // to previous node refer to below notes
.en_local_rep(en_local_rep_3),
.en_pass_req(en_pass_req_3), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_3), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_3),
.used_slots_pass_rep(used_slots_pass_rep_3),
.flit_out(flit_out_3),
.ctrl_out(ctrl_out_3),
.dest_fifo_out(dest_fifo_out_3)
);
// instance of node4
ring_node node4(//input
.clk(clk),
.rst(rst),
.ctrl_in(ctrl_out_3), //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
.flit_in(flit_out_3),
.dest_fifo_in(dest_fifo_out_3),
.en_local_req_in(en_local_req_3),
.en_local_rep_in(en_local_rep_3),
.en_pass_req_in(en_pass_req_3),
.en_pass_rep_in(en_pass_rep_3),
.used_slots_pass_req_in(used_slots_pass_req_3),
.used_slots_pass_rep_in(used_slots_pass_rep_3),
//output
.en_local_req(en_local_req_4), // to previous node refer to below notes
.en_local_rep(en_local_rep_4),
.en_pass_req(en_pass_req_4), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep_4), // refer to notes below
.used_slots_pass_req(used_slots_pass_req_4),
.used_slots_pass_rep(used_slots_pass_rep_4),
.flit_out(flit_out_4),
.ctrl_out(ctrl_out_4),
.dest_fifo_out(dest_fifo_out_4)
);
endmodule
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#include <bits/stdc++.h> using namespace std; #pragma GCC optimize -O3 bool prime(long long int n) { if (n == 1) return false; if (n == 2 || n == 3) return true; long long int k = sqrt(n) + 1; for (long long int i = 2; i < k; i++) { if (n % i == 0) return false; } return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int x; cin >> x; long long int b[x]; for (long long int i = 0; i < x; i++) { cin >> b[i]; } long long int y; cin >> y; long long int g[y]; for (long long int i = 0; i < y; i++) { cin >> g[i]; } sort(b, b + x); sort(g, g + y); long long int ans = 0; for (long long int i = 0; i < x; i++) { for (long long int j = 0; j < y; j++) { long long int val = abs(b[i] - g[j]); if (val <= 1) { g[j] = 99999; ans++; break; ; } } } cout << ans; cout << endl; ; ; return 0; }
|
//
// GPIO controller for picorv32
//
// Little endian.
// Increasing numeric significance with increasing memory addresses known as "little-endian".
//
`include "inc/timescale.vh"
module gpio (
// Bus interface
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
// gpio interface
output reg [31:0] gpio
);
reg [7:0] q;
reg rdy;
always @(posedge clk) begin
if (!resetn) begin
rdy <= 0;
q <= 0;
gpio <= 0;
end else if (mem_valid & enable) begin
if (mem_wstrb[0])
gpio[7:0] <= mem_wdata[7:0];
if (mem_wstrb[1])
gpio[15:8] <= mem_wdata[15:8];
if (mem_wstrb[2])
gpio[23:16] <= mem_wdata[23:16];
if (mem_wstrb[3])
gpio[31:24] <= mem_wdata[31:24];
rdy <= 1;
end else begin
rdy <= 0;
end
q <= gpio;
end
// Wire-OR'ed bus outputs.
assign mem_rdata = enable ? q : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Multiplication Module for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 64-bit Booth signed or unsigned multiply and //
// multiply-accumulate supported. It takes about 38 clock //
// cycles to complete an operation. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
// bit 0 go, bit 1 accumulate
// Command:
// 4'b01 : MUL - 32 bit multiplication
// 4'b11 : MLA - 32 bit multiply and accumulate
//
// 34-bit Booth adder
// The adder needs to be 34 bit to deal with signed and unsigned 32-bit
// multiplication inputs. This adds 1 extra bit. Then to deal with the
// case of two max negative numbers another bit is required.
//
module a23_multiply (
input i_clk,
input i_fetch_stall,
input [31:0] i_a_in, // Rds
input [31:0] i_b_in, // Rm
input [1:0] i_function,
input i_execute,
output [31:0] o_out,
output [1:0] o_flags, // [1] = N, [0] = Z
output reg o_done = 'd0 // goes high 2 cycles before completion
);
wire enable;
wire accumulate;
wire [33:0] multiplier;
wire [33:0] multiplier_bar;
wire [33:0] sum;
wire [33:0] sum34_b;
reg [5:0] count = 'd0;
reg [5:0] count_nxt;
reg [67:0] product = 'd0;
reg [67:0] product_nxt;
reg [1:0] flags_nxt;
wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
assign enable = i_function[0];
assign accumulate = i_function[1];
assign multiplier = { 2'd0, i_a_in} ;
assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ;
assign sum34_b = product[1:0] == 2'b01 ? multiplier :
product[1:0] == 2'b10 ? multiplier_bar :
34'd0 ;
// Use DSP modules from Xilinx Spartan6 FPGA devices
`ifdef XILINX_FPGA
// -----------------------------------
// 34-bit adder - booth multiplication
// -----------------------------------
`ifdef XILINX_SPARTAN6_FPGA
xs6_addsub_n #(.WIDTH(34))
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_addsub_n #(.WIDTH(34))
`endif
u_xx_addsub_34_sum (
.i_a ( product[67:34] ),
.i_b ( sum34_b ),
.i_cin ( 1'd0 ),
.i_sub ( 1'd0 ),
.o_sum ( sum ),
.o_co ( )
);
// ------------------------------------
// 33-bit adder - accumulate operations
// ------------------------------------
`ifdef XILINX_SPARTAN6_FPGA
xs6_addsub_n #(.WIDTH(33))
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_addsub_n #(.WIDTH(33))
`endif
u_xx_addsub_33_acc1 (
.i_a ( {1'd0, product[32:1]} ),
.i_b ( {1'd0, i_a_in} ),
.i_cin ( 1'd0 ),
.i_sub ( 1'd0 ),
.o_sum ( sum_acc1 ),
.o_co ( )
);
`else
// -----------------------------------
// 34-bit adder - booth multiplication
// -----------------------------------
assign sum = product[67:34] + sum34_b;
// ------------------------------------
// 33-bit adder - accumulate operations
// ------------------------------------
assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
`endif
always @*
begin
// Defaults
count_nxt = count;
product_nxt = product;
// update Negative and Zero flags
// Use registered value of product so this adds an extra cycle
// but this avoids having the 64-bit zero comparator on the
// main adder path
flags_nxt = { product[32], product[32:1] == 32'd0 };
if ( count == 6'd0 )
product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ;
else if ( count <= 6'd33 )
product_nxt = { sum[33], sum, product[33:1]} ;
else if ( count == 6'd34 && accumulate )
begin
// Note that bit 0 is not part of the product. It is used during the booth
// multiplication algorithm
product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
end
// Multiplication state counter
if (count == 6'd0) // start
count_nxt = enable ? 6'd1 : 6'd0;
else if ((count == 6'd34 && !accumulate) || // MUL
(count == 6'd35 && accumulate) ) // MLA
count_nxt = 6'd0;
else
count_nxt = count + 1'd1;
end
always @ ( posedge i_clk )
if ( !i_fetch_stall )
begin
count <= i_execute ? count_nxt : count;
product <= i_execute ? product_nxt : product;
o_done <= i_execute ? count == 6'd31 : o_done;
end
// Outputs
assign o_out = product[32:1];
assign o_flags = flags_nxt;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 101000; int fa[maxn], sz[maxn], c[maxn]; int fd(int f) { return fa[f] == f ? f : fa[f] = fd(fa[f]); } int n, m, f[maxn]; bool isok(int x) { while (x) { int d = x % 10; if (d != 4 && d != 7) return false; x /= 10; } return true; } void bp(int v, int w) { for (int i = n; i >= v; --i) f[i] = min(f[i], f[i - v] + w); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) fa[i] = i; for (int i = 1; i <= m; ++i) { int u, v; scanf( %d%d , &u, &v); fa[fd(u)] = fd(v); } for (int i = 1; i <= n; ++i) sz[fd(i)]++; for (int i = 1; i <= n; ++i) c[sz[i]]++, f[i] = 1e9; for (int i = 1; i <= n; ++i) if (c[i]) { for (int s = 1; s <= c[i]; s <<= 1) bp(s * i, s), c[i] -= s; bp(c[i] * i, c[i]); } int ans = 1e9; for (int i = 1; i <= n; ++i) if (isok(i)) ans = min(ans, f[i]); printf( %d n , ans == 1e9 ? -1 : ans - 1); return 0; }
|
module pass_through(
clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [1:0]current_state;
parameter idle=2'b0,
transmit=2'b01,
discard=2'b10;
always@(posedge clk or negedge reset)
if(!reset)
begin
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
current_state<=idle;
end
else
begin
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
discard:
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
end//end defult;
endcase
end
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
fifo_256_139 fifo_256_1393(
.aclr(!reset),
.clock(clk),
.data(in_pkt),
.rdreq(in_pkt_rdreq),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.usedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
fifo_64_1 fifo_64_13(
.aclr(!reset),
.clock(clk),
.data(in_valid),
.rdreq(in_valid_rdreq),
.wrreq(in_valid_wrreq),
.empty(in_valid_empty),
.q(in_valid_q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n = 10; const int ms = 100; int grid[ms][ms]; const int inf = 1e9; int f[ms]; double dp[ms]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed << setprecision(8); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> grid[i][j]; } i++; for (int j = n - 1; j >= 0; j--) { cin >> grid[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (grid[i][j] % 2 == 0) { f[i * 10 + j] = i * 10 + j - grid[i][j] * 10; } else { f[i * 10 + j] = i * 10 + (n - j - 1) - grid[i][j] * 10; } } i++; for (int j = n - 1; j >= 0; j--) { if (grid[i][j] % 2 == 0) { f[i * 10 + j] = i * 10 + j - grid[i][j] * 10; } else { f[i * 10 + j] = i * 10 + (n - j - 1) - grid[i][j] * 10; } } } dp[0] = 0.0; for (int i = 1; i < ms; i++) { double sum = 1; double tam = min(i, 6); for (int d = 1; d <= tam; d++) { sum += 1.0 / 6.0 * min(dp[i - d], dp[f[i - d]]); } dp[i] = (6.0 / tam) * sum; } cout << dp[99] << n ; }
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long int fast_expo(long long int base, long long int to) { long long int res = 1; while (to) { if (to & 1) { res *= base; } base *= base; to /= 2; } return res; } long long int to_bin[50]; int main() { ios::sync_with_stdio(false); cin.tie(0); long long int h, n; cin >> h >> n; long long int temp = n - 1; for (long long int i = 0; i < h; i++) { to_bin[h - i - 1] = temp % 2; temp /= 2; } long long int ans = 0; if (to_bin[0] == 1) { ans += fast_expo(2, h); } else { ans += 1; } for (long long int i = 1; i < h; i += 1) { if (to_bin[i] == to_bin[i - 1]) { ans += fast_expo(2, h - i); } else { ans += 1; } } cout << ans; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/23/07 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module OBUFT (O, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
input I, T;
bufif0 T1 (O, I, T);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, aa[8] = {-1, 0, 1, -1, 2, -1, -1, -1}, bb[8] = {-1, -1, -1, 2, -1, 1, 0, -1}; int T, n, i, j; long long l, r, m, a[N], b[N], c[N], x, y, z, mn[8], u[4], d[4]; inline bool ckk(long long p, long long q, long long r) { for (x = q + r - 4 >> 1; x <= q + r + 4 >> 1; ++x) for (y = r + p - 4 >> 1; y <= r + p + 4 >> 1; ++y) for (z = p + q - 4 >> 1; z <= p + q + 4 >> 1; ++z) if (d[0] <= -x + y + z && -x + y + z <= u[0] && d[1] <= x - y + z && x - y + z <= u[1] && d[2] <= x + y - z && x + y - z <= u[2] && d[3] <= x + y + z && x + y + z <= u[3]) return 1; return 0; } inline bool ck(long long D) { for (i = 0; i < 8; ++i) mn[i] = 8e18; for (i = 1; i <= n; ++i) for (j = 0; j < 8; ++j) mn[j] = min(mn[j], D + (j & 1 ? -a[i] : a[i]) + (j & 2 ? -b[i] : b[i]) + (j & 4 ? -c[i] : c[i])); u[3] = mn[0]; d[3] = -mn[7]; for (i = 1; i < 7; ++i) { if (aa[i] != -1) u[aa[i]] = mn[i]; if (bb[i] != -1) d[bb[i]] = -mn[i]; } for (i = 0; i < 4; ++i) if (u[i] < d[i]) return 0; x = 27; y = 26; z = 59; if (53 <= D && D < 70) ++D, --D; for (i = 0; i < 16; ++i) { long long p, q, r, s; p = i & 1 ? u[0] : d[0]; q = i & 2 ? u[1] : d[1]; r = i & 4 ? u[2] : d[2]; s = i & 8 ? u[3] : d[3]; s = p + q + r; if (d[3] <= s && s <= u[3] && ckk(p, q, r)) return 1; p = i & 1 ? u[0] : d[0]; q = i & 2 ? u[1] : d[1]; r = i & 4 ? u[2] : d[2]; s = i & 8 ? u[3] : d[3]; r = s - p - q; if (d[2] <= r && r <= u[2] && ckk(p, q, r)) return 1; if (i == 0) ++i, --i; p = i & 1 ? u[0] : d[0]; q = i & 2 ? u[1] : d[1]; r = i & 4 ? u[2] : d[2]; s = i & 8 ? u[3] : d[3]; q = s - p - r; if (d[1] <= q && q <= u[1] && ckk(p, q, r)) return 1; p = i & 1 ? u[0] : d[0]; q = i & 2 ? u[1] : d[1]; r = i & 4 ? u[2] : d[2]; s = i & 8 ? u[3] : d[3]; p = s - q - r; if (d[0] <= p && p <= u[0] && ckk(p, q, r)) return 1; } return 0; } int main() { scanf( %d , &T); for (; T--;) { l = r = 0; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %lld%lld%lld , a + i, b + i, c + i), r = max(r, abs(a[i]) + abs(b[i]) + abs(c[i])); for (; l < r;) { m = l + r >> 1; if (ck(m)) r = m; else l = m + 1; } ck(l); printf( %lld %lld %lld n , x, y, z); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int lg = 22; const long long int N = 2e5 + 5; const long long int INF = 1e18; const long long int mod = 1e9 + 7; const double PI = 3.14159265358979323846; template <typename T> T power(T x, T y, long long int m) { T ans = 1; while (y > 0) { if (y & 1LL) ans = (ans * x) % m; y >>= 1LL; x = (x * x) % m; } return ans % m; } inline long long int mul(long long int a, long long int b, long long int p) { return (a * 1ll * b) % p; } inline long long int sub(long long int a, long long int b, long long int p) { long long int c = a - b; if (c < 0) c += p; return c; } inline long long int add(long long int a, long long int b, long long int p) { long long int c = a + b; if (c > p) c -= p; return c; } long long int mark[N]; long long int n, q, a[N], minidx[N], maxidx[N]; int main() { long long int ans = 0; cin >> n >> q; for (long long int i = 1; i <= n; i++) { cin >> a[i]; if (minidx[a[i]] == 0) { minidx[a[i]] = i; } maxidx[a[i]] = i; } for (long long int i = 1; i <= n; i++) { long long int maxcnt = 0, cnt = 0; long long int maxi = maxidx[a[i]]; if (mark[i]) { continue; } map<long long int, long long int> xfreq; for (long long int j = i; j <= maxi; j++) { cnt++; mark[j] = 1; xfreq[a[j]]++; maxcnt = max(maxcnt, xfreq[a[j]]); maxi = max(maxi, maxidx[a[j]]); } ans += (cnt - maxcnt); } cout << ans << endl; }
|
// $Id: c_wf_alloc.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic wavefront allocator
module c_wf_alloc
(clk, reset, update, req, gnt);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// select implementation variant
parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
// try to recover from errors
parameter error_recovery = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// update arbitration priorities
input update;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
generate
case(wf_alloc_type)
`WF_ALLOC_TYPE_MUX:
begin
c_wf_alloc_mux
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_mux
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_REP:
begin
c_wf_alloc_rep
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_rep
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_DPA:
begin
c_wf_alloc_dpa
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_dpa
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_ROT:
begin
c_wf_alloc_rot
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_rot
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_LOOP:
begin
c_wf_alloc_loop
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_loop
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
endcase
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; int m; cin >> n >> m; int c[m], a[n]; int i, j, k; for (i = 0; i < n; i++) { a[i] = 0; } for (i = 0; i < m; i++) { cin >> c[i]; a[c[i] - 1]++; } k = a[0]; for (i = 0; i < n; i++) { if (k > a[i]) { k = a[i]; } } cout << k; return 0; }
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#include <bits/stdc++.h> using namespace std; const int BUFFER_SIZE = 1 << 20; char rb[BUFFER_SIZE], *rp = rb, *rt = rb; inline char read_char() { return rp == rt ? (rt = rb + fread(rb, 1, BUFFER_SIZE, stdin), rp = rb, *rp++) : *rp++; } inline int read_int() { int x = 0; char ch = read_char(), flag = 0; while (ch != - && (ch < 0 || ch > 9 )) { ch = read_char(); } if (ch == - ) { flag = 1; ch = read_char(); } for (x = 0; ch >= 0 && ch <= 9 ; ch = read_char()) { x = x * 10 + (ch - 0 ); } return flag ? -x : x; } const int MAX_N = 200000 + 5; int N, n[2], siz[MAX_N]; int ey[MAX_N << 1], enext[MAX_N << 1], elast[MAX_N]; void dp(int u, int fa, int dep) { n[dep & 1]++; siz[u] = 1; for (int j = elast[u]; j; j = enext[j]) { int v = ey[j]; if (v != fa) { dp(v, u, dep ^ 1); siz[u] += siz[v]; } } } int main() { N = read_int(); for (int i = 1, j = 1; i < N; i++) { int x = read_int(); int y = read_int(); ey[j] = y; enext[j] = elast[x]; elast[x] = j++; ey[j] = x; enext[j] = elast[y]; elast[y] = j++; } dp(1, 0, 0); long long ans = 0; for (int i = 1; i <= N; i++) { ans += 1ll * siz[i] * (N - siz[i]); } ans += 1ll * n[0] * n[1]; printf( %lld n , ans >> 1); return 0; }
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#include <bits/stdc++.h> using namespace std; long long sum(long long n) { return (n * (n - 1)) / 2; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int arr[n + 1]; for (int i = 0; i < n; i++) cin >> arr[i]; pair<int, int> b[n + 1]; for (int i = 0; i < n; i++) { cin >> b[i].first; b[i].second = i; } sort(b, b + n); sort(arr, arr + n, greater<int>()); long long a[n + 1]; for (int i = 0; i < n; i++) { a[b[i].second] = arr[i]; } for (int i = 0; i < n; i++) cout << a[i] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = (int)3 * 1e5 + 21; const double eps = (double)1e-8; const int mod = (int)1000000007; int a[maxn], b[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, x; memset((a), 0, sizeof(a)); ; memset((b), 0, sizeof(b)); ; cin >> n >> x; long long ans = 0; for (int i = (0); i < (n); i++) { cin >> a[i]; ans += b[a[i] ^ x]; b[a[i]]++; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; const long long N = 101000; struct p { long long x, y; } a[N]; long long n, m; long long pro(p o, p b, p c) { return (b.x - o.x) * (c.y - o.y) - (c.x - o.x) * (b.y - o.y); } int main() { scanf( %I64d , &n); for (long long i = 1; i <= n; i++) scanf( %I64d%I64d , &a[i].x, &a[i].y); scanf( %I64d , &m); for (long long i = 1; i <= m; i++) { p b; scanf( %I64d%I64d , &b.x, &b.y); if (pro(a[1], a[2], b) >= 0 || pro(a[1], a[n], b) <= 0) { puts( NO ); return 0; } long long l = 2, r = n; while (l < r) { long long mid = (l + r) / 2; if (pro(a[1], a[mid], b) >= 0) r = mid; else l = mid + 1; } if (pro(a[l], a[l - 1], b) <= 0) { puts( NO ); return 0; } } puts( YES ); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb8to1 (
//# {{data|Data Signals}}
input [7:0] D,
output Z,
//# {{control|Control Signals}}
input [7:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
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