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#include <bits/stdc++.h> using namespace std; const int N = 1E5 + 9; vector<int> g[N]; int tin[N]; int tout[N]; int sz[N]; int tt; int toys[N]; bool root[N]; void dfs(int v) { tin[v] = tt++; sz[v] = 1; for (auto i : g[v]) { dfs(i); sz[v] += sz[i]; } tout[v] = tt++; } bool parent(int v, int p) { return (tin[v] > tin[p] && tout[v] < tout[p]); } int main() { int n, m, k, q; cin >> n >> m >> k >> q; for (int i = 1; i <= n; i++) root[i] = true; for (int i = 1; i <= k; i++) { int v, t; cin >> v >> t; if (toys[t] == 0) { toys[t] = v; continue; } g[toys[t]].push_back(v); root[v] = false; toys[t] = v; } for (int i = 1; i <= n; i++) if (root[i]) dfs(i); for (int i = 1; i <= q; i++) { int v, t; cin >> v >> t; if (toys[t] == 0) { cout << 0 << endl; continue; } if (parent(toys[t], v)) { cout << sz[v] << endl; continue; } cout << 0 << endl; } return 0; }
|
module testbench();
reg tb_clk;
reg SCK;
reg MOSI;
reg SSEL;
wire MISO;
wire [7:0] MSG;
spi_slave spi1(.CLK(tb_clk),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting testbench!!!!");
tb_clk <= 0;
repeat (10*100) begin
#1;
tb_clk <= 1;
#1;
tb_clk <= 0;
end
$display("finished OK!");
$finish;
end
reg [15:0] msg;
initial
begin
SSEL <= 1;
SCK <= 0;
MOSI <= 0;
msg <= 16'b1110001101010101;
#100;
SSEL <= 0;
repeat (16) begin
#10;
MOSI <= msg[15];
msg <= msg << 1;
SCK <= 1;
#10;
SCK <= 0;
end
SSEL <= 1;
end
reg a, b;
wand WA;
assign WA = a;
assign WA = b;
initial begin
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
#100;
a <= 1'bz;
#100;
b <= 1;
#100;
b <= 1'bz;
#100;
a <= 0;
#100;
a <= 1'bz;
#100;
b <= 0;
#100;
b <= 1'bz;
#100;
a <= 0;
b <= 0;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
b <= 1;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 0;
b <= 1;
#100;
a <= 1'bz;
b <= 1'bz;
#100;
a <= 1;
b <= 0;
#100;
a <= 1'bz;
b <= 1'bz;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_memory_sync (reset, enable, start_addr, end_addr, r_clock, ren, raddr, rdata,
w_clock, wen, waddr, wdata, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter data_width = 1;
parameter addr_width = 1;
parameter mem_size = 2;
parameter addr_check = 1;
parameter init_check = 1;
parameter conflict_check = 0;
parameter pass_thru = 0;
parameter one_read_check = 0;
parameter one_write_check = 0;
parameter value_check = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter wen_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter ren_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input ren, wen, r_clock, w_clock;
input [addr_width-1 : 0] start_addr;
input [addr_width-1 : 0] end_addr;
input [addr_width-1 : 0] raddr;
input [data_width-1 : 0] rdata;
input [addr_width-1 : 0] waddr;
input [data_width-1 : 0] wdata;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_MEMORY_SYNC";
`ifdef OVL_EVERYTHING_OFF
// No logic if ASSERT & COVER both OFF
`else
// latch based gated clock
wire rd_gclk, wr_gclk;
reg rd_clken, wr_clken;
always @ (r_clock or enable) begin
if (r_clock == 1'b0)
rd_clken <= enable;
end
always @ (w_clock or enable) begin
if (w_clock == 1'b0)
wr_clken <= enable;
end
assign rd_gclk = (gating_type == `OVL_GATE_CLOCK) ? r_clock & rd_clken : r_clock;
assign wr_gclk = (gating_type == `OVL_GATE_CLOCK) ? w_clock & wr_clken : w_clock;
// clk (programmable edge)
wire rd_clk, wr_clk;
assign rd_clk = (ren_edge == `OVL_POSEDGE) ? rd_gclk : ~rd_gclk;
assign wr_clk = (wen_edge == `OVL_POSEDGE) ? wr_gclk : ~wr_gclk;
// reset_n (programmable polarity & optional gating)
wire reset_n;
assign reset_n = (gating_type == `OVL_GATE_RESET) ? ((reset_polarity == `OVL_ACTIVE_LOW) ? reset & enable : ~reset & enable)
: ((reset_polarity == `OVL_ACTIVE_LOW) ? reset : ~reset);
`endif
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_memory_sync_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_memory_sync
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:51:59 09/23/2013
// Design Name:
// Module Name: Main_Module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Main_Module(clock, reset, write_data_selector, led_write, led_read, led_success, led_fail,
addr, dato,clock2,estado,mem_data,WE);
/**ENTRADAS Y SALIDAS*/
input clock, reset;
input [1:0] write_data_selector;
output wire clock2, led_write, led_read, led_success, led_fail, WE;
output wire [3:0] estado, mem_data;
output wire [6:0] addr, dato;
/**VARIABLES DEL PROGRAMA*/
//Variables que obtienen los resultados del debounce
wire [1:0] write_data_selector_sync;
wire reset_sync;
//Clock a 1Hz
wire div_clock;
//Valor por escribirse y leer en la memoria.
wire [3:0] write_value, read_value, data;
//Senales de la maquina de estados
wire enable_cuenta, write_value_reg_en, read_value_reg_en;
//Direccion de la memoria
wire [3:0] mem_address;
//Divisor de reloj
Clock_Divider mod_divisor(
.clock(clock),
.reset(reset_sync),
.clock_out(div_clock)
);
//Debounce para limpiar las sennales
Debounce mod_debounce(
.clock(clock),
.reset(reset),
.div_clock(div_clock),
.write_data_selector(write_data_selector),
.reset_sync(reset_sync),
.write_data_selector_sync(write_data_selector_sync)
);
//Maquina de estados
FSM mod_fsm(
.div_clock(div_clock),
.reset(reset_sync),
.enable_cuenta(enable_cuenta),
.write_enable(WE),
.write_value_reg_en(write_value_reg_en),
.read_value_reg_en(read_value_reg_en),
.led_write(led_write),
.led_read(led_read),
.estado(estado)
);
assign clock2 = div_clock;
//Contador que lleva la direccion de memoria
Contador mod_contador(
.enable_cuenta(enable_cuenta),
.reset(reset_sync),
.mem_address(mem_address)
);
//Asigna los valores para los 7 segmentos
assign addr = mem_address;
//Selector del dato a escribir
Data_Parameters mod_data(
.clock(clock),
.reset(reset_sync),
.mem_address(mem_address),
.write_value_reg_en(write_value_reg_en),
.write_data_selector(write_data_selector_sync),
.write_value(write_value)
);
//Buffer que deja pasar o envia info a la memoria
Buffer mod_buffer(
.WE(WE),
.write_value(write_value),
.read_value(read_value),
.data(data)
);
//Se guarda el dato para los 7 segmentos
assign dato = data;
Memoria mod_memoria(
.WE(WE),
.ADDR(mem_address),
.DATA(data),
.mem_data(mem_data)
);
//Comparador del valor escrito y el leido
Comparador mod_compara(
.clock(clock),
.reset(reset_sync),
.write_value(write_value),
.read_value(read_value),
.read_value_reg_en(read_value_reg_en),
.led_success(led_success),
.led_fail(led_fail)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long double pi = 3.141592653589793238; set<long long>::iterator it; multiset<long long>::iterator itr; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long t; t = 1; while (t--) { long long n; cin >> n; long long m, a, b; cin >> m >> a >> b; long long r = n % m; cout << min(b * (r), a * (m - r)) << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; void qr(int &x) { scanf( %d , &x); } int n, sz[N], f[N], root, c[N]; long long k, mn, mx; struct edge { int y, next; } a[N * 2]; int len, last[N]; void ins(int x, int y) { a[++len] = (edge){y, last[x]}; last[x] = len; } void dfs1(int x, int fa) { sz[x] = f[x] = 1; for (int k = last[x], y; k; k = a[k].next) { y = a[k].y; if (y ^ fa) { dfs1(y, x); sz[x] += sz[y]; mn += sz[y] & 1; mx += min(sz[y], n - sz[y]); f[x] = max(f[x], sz[y]); } } f[x] = max(f[x], n - sz[x]); } void dfs2(int x, int fa) { sz[x] = 1; for (int k = last[x], y; k; k = a[k].next) { y = a[k].y; if (y ^ fa) { dfs2(y, x); sz[x] += sz[y]; } } c[sz[x]]++; } vector<int> d[N]; int son[N], tot, A[N], B[N]; void dfs3(int x, int fa) { sz[x] = 1; for (int k = last[x], y; k; k = a[k].next) if ((y = a[k].y) ^ fa) dfs3(y, x), sz[x] += c[y]; int C = (sz[x] - c[x]) >> 1, st = 1, ed; son[tot = 1] = x; d[x].push_back(x); for (int k = last[x], y; k; k = a[k].next) if ((y = a[k].y) ^ fa) son[++tot] = y; ed = tot; for (int i = 1; i <= C; i++) { while (d[son[st]].empty()) st++; A[i] = d[son[st]].back(); d[son[st]].pop_back(); while (d[son[ed]].empty()) ed--; B[i] = d[son[ed]].back(); d[son[ed]].pop_back(); } for (int i = 1; i <= C; i++) printf( %d %d n , A[i], B[C - i + 1]); for (int i = 2; i <= tot; i++) { if (d[son[i]].size() > d[x].size()) swap(d[x], d[son[i]]); for (int j : d[son[i]]) d[x].push_back(j); } } int main() { qr(n); scanf( %lld , &k); for (int i = 1, x, y; i < n; i++) qr(x), qr(y), ins(x, y), ins(y, x); dfs1(1, 0); if (!(mn <= k && k <= mx) || (k - mn) % 2 == 1) puts( NO ), exit(0); root = 1; for (int i = 2; i <= n; i++) if (f[i] < f[root]) root = i; dfs2(root, 0); int p = n - 1; for (; p > 1; p--) if (mx - c[p] * 2 >= k) { mx -= c[p] * 2; c[p - 2] += c[p]; } else break; for (int i = 1; i <= n; i++) c[i] = min(sz[i], p - (p + sz[i]) % 2); c[root] = 0; for (int i = 1; i <= n; i++) if (c[i] == p && mx > k) { mx -= 2; c[i] -= 2; } puts( YES ); dfs3(root, 0); return 0; }
|
`timescale 1ns / 1ps
module mux_32to1_2b_tb;
// Inputs
reg [63:0] data_in;
reg [4:0] ctrl_sel;
// Outputs
wire [1:0] data_out;
// Variables
integer i = 0;
// Instantiate the Unit Under Test (UUT)
mux_32to1_2b uut (
.data_in(data_in),
.ctrl_sel(ctrl_sel),
.data_out(data_out)
);
task expect;
input [1:0] exp_out;
if (data_out !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d ctrl_sel=%b, data_out=%b",
$time, ctrl_sel, data_out);
$display("data_out should be %b", exp_out);
$finish;
end
else begin
$display("At time %0d ctrl_sel=%b, data_out=%b",
$time, ctrl_sel, data_out);
end
endtask
initial begin
// Initialize 32 Inputs with repetition of 2'b00, 2'b01, 2'b10, 2'b11
for( i=0; i<32; i = i+1)
begin
data_in[i*2+:2] = i%4;
end
// Check if mux produces expected output
// for each of the 32 select signal values
for( i=0; i<32; i = i+1)
begin
ctrl_sel = i;
#10 expect(i%4);
end
$display("TEST PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } int getid(string s) { int len = ((int)(s).size()), id = 0; if (len > 19) return -1; for (int j = 0; j < len; j++) id = id * 2 + s[j] - 0 ; return id + (1 << len) - 2; } int n, m, u, v; char s[110]; string t; struct blk { string bg, ed; bitset<1048576> S; bool full; void add(string s) { int m = ((int)(s).size()); for (int j = 0; j < m; j++) for (int k = j; k < m; k++) { string f = s.substr(j, k - j + 1); int id = getid(f); if (id == -1) continue; S[id] = 1; } } void simply() { if (((int)(bg).size()) > 20) { bg = bg.substr(0, 20); full = 0; } if (((int)(ed).size()) > 20) { ed = ed.substr(((int)(ed).size()) - 20, 20); full = 0; } } int query() { for (int i = 20 - 1; i >= 1; i--) { int d = (1 << i) - 2, val = 1; for (int j = 0; j < (1 << i); j++) { if (!S[d + j]) { val = 0; break; } } if (val) return i; } return 0; } } b[210]; void gao(int p, int u, int v) { b[p].S = b[u].S | b[v].S; if (b[u].full) b[p].bg = b[u].bg + b[v].bg, b[p].full = 1; else b[p].bg = b[u].bg; if (b[v].full) b[p].ed = b[u].ed + b[v].ed, b[p].full = 1; else b[p].ed = b[v].ed; b[p].add(b[u].ed + b[v].bg); b[p].simply(); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , s); t = s; b[i].add(t); b[i].bg = t; b[i].ed = t; b[i].full = 1; b[i].simply(); } scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); gao(n + i, u - 1, v - 1); printf( %d n , b[n + i].query()); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e9 + 1; int a[201][201]; int cnt[10][10]; int calc(int x, int y) { if (x * 2 > y) return 500; else if (x * 4 > y) return 1000; else if (x * 8 > y) return 1500; else if (x * 16 > y) return 2000; else if (x * 32 > y) return 2500; else return 3000; } int use[10]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < 5; j++) { cin >> a[i][j]; } } for (int k = 0; k < 5; k++) { if (a[0][k] == -1) use[k] = 0; else if (a[1][k] == -1 || (a[1][k] != -1 && a[1][k] > a[0][k])) use[k] = -1; else use[k] = 1; } for (int t = 0; t < 50000; t++) { int sc1 = 0, sc0 = 0; for (int i = 0; i < 5; i++) { long long x = 0, y = 0; for (int j = 0; j < n; j++) { if (a[j][i] != -1) x++; } if (use[i] == 1) x += t; y = n + t; if (a[0][i] != -1) { sc0 += calc(x, y) * (250 - a[0][i]); } if (a[1][i] != -1) { sc1 += calc(x, y) * (250 - a[1][i]); } } if (sc0 > sc1) { cout << t << endl; return 0; } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[500000]; bool visited[500000]; int n; unordered_map<int, int> m, p; vector<pair<int, int> > v; void check(int u) { visited[u] = true; for (auto v : g[u]) { if (!visited[v]) check(v); } } int main() { cin >> n; set<int> s; for (int i = 0; i < n; i++) { int a, b; cin >> a >> b; m[a] = b; v.push_back({a, 0}); v.push_back({b, 1}); p[a] = i; p[b] = i; } sort(v.begin(), v.end()); int count = 0; for (int i = 0; i < v.size(); i++) { if (v[i].second == 0) { for (auto ele : s) { if (ele < m[v[i].first]) { count++; g[p[v[i].first]].push_back(p[ele]); g[p[ele]].push_back(p[v[i].first]); } else break; } if (count > n - 1) { break; } s.insert(m[v[i].first]); } else { s.erase(v[i].first); } } if (count == n - 1) { check(0); int i; for (i = 0; i < n; i++) { if (!visited[i]) break; } if (i == n) cout << YES << endl; else cout << NO << endl; } else cout << NO << endl; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* GMII PHY interface
*/
module gmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2"
)
(
input wire clk,
input wire rst,
/*
* GMII interface to MAC
*/
output wire mac_gmii_rx_clk,
output wire mac_gmii_rx_rst,
output wire [7:0] mac_gmii_rxd,
output wire mac_gmii_rx_dv,
output wire mac_gmii_rx_er,
output wire mac_gmii_tx_clk,
output wire mac_gmii_tx_rst,
input wire [7:0] mac_gmii_txd,
input wire mac_gmii_tx_en,
input wire mac_gmii_tx_er,
/*
* GMII interface to PHY
*/
input wire phy_gmii_rx_clk,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
input wire phy_mii_tx_clk,
output wire phy_gmii_tx_clk,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
/*
* Control
*/
input wire mii_select
);
ssio_sdr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(10)
)
rx_ssio_sdr_inst (
.input_clk(phy_gmii_rx_clk),
.input_d({phy_gmii_rxd, phy_gmii_rx_dv, phy_gmii_rx_er}),
.output_clk(mac_gmii_rx_clk),
.output_q({mac_gmii_rxd, mac_gmii_rx_dv, mac_gmii_rx_er})
);
ssio_sdr_out #
(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(10)
)
tx_ssio_sdr_inst (
.clk(mac_gmii_tx_clk),
.input_d({mac_gmii_txd, mac_gmii_tx_en, mac_gmii_tx_er}),
.output_clk(phy_gmii_tx_clk),
.output_q({phy_gmii_txd, phy_gmii_tx_en, phy_gmii_tx_er})
);
generate
if (TARGET == "XILINX") begin
BUFGMUX
gmii_bufgmux_inst (
.I0(clk),
.I1(phy_mii_tx_clk),
.S(mii_select),
.O(mac_gmii_tx_clk)
);
end else begin
assign mac_gmii_tx_clk = mii_select ? phy_mii_tx_clk : clk;
end
endgenerate
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_gmii_tx_rst = tx_rst_reg[0];
always @(posedge mac_gmii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_gmii_rx_rst = rx_rst_reg[0];
always @(posedge mac_gmii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 30000; long long t, n, a[N], l, r; bool possible() { if (l > r) return 1; long long o = a[l - 1]; a[l - 1] = 0; for (long long i = l; i <= r; i++) { long long v = max(a[i - 1], a[i] - o); if (v > a[r + 1]) return 0; o = a[i] - v; a[i] = v; } return 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; l = 1; r = n - 2; for (; l < n && a[l - 1] >= a[l]; l++) ; for (; r >= 0 && a[r] <= a[r + 1]; r--) ; cout << (possible() ? YES n : NO n ); } }
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Implicit Arguments id [[A]].
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Open Local Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Implicit Arguments prod_curry [[A] [B] [C]].
Implicit Arguments prod_uncurry [[A] [B] [C]].
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_2_V
`define SKY130_FD_SC_MS__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_2_V
|
#include <bits/stdc++.h> using namespace std; bool secdes(const pair<long long, long long>& a, const pair<long long, long long>& b) { if (a.second == b.second) { return a.first > b.first; } else { return a.second > b.second; } } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; long long ind = -1; long long l = s.length(), f = 0; for (long long i = l - 1; i >= 0; i--) { long long k = s[i] - 48; if (k % 2 == 0) { f += 1; if (f == 1) { ind = i; } if (s[l - 1] - 48 > k) { ind = i; } } } if (f == 0) cout << -1; else { swap(s[ind], s[l - 1]); cout << s; } }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_reg_map.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
/*** WA for CR # 695818 ***/
`ifdef XILINX_SIMULATOR
`define XSIM_ISIM
`endif
`ifdef XILINX_ISIM
`define XSIM_ISIM
`endif
module processing_system7_bfm_v2_0_reg_map();
`include "processing_system7_bfm_v2_0_local_params.v"
/* Register definitions */
`include "processing_system7_bfm_v2_0_reg_params.v"
parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB
`ifdef XSIM_ISIM
reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
parameter addr_offset_bits = 26;
`else
reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space
parameter addr_offset_bits = 27;
`endif
/* preload reset_values from file */
task automatic pre_load_rst_values;
input dummy;
begin
`include "processing_system7_bfm_v2_0_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
end
endtask
/* writes the reset data into the reg memory */
task automatic set_reset_data;
input [addr_width-1:0] address;
input [data_width-1:0] data;
reg [addr_width-1:0] addr;
begin
addr = address >> 2;
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* writes the data into the reg memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* get the read data from reg mem */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
endcase
`else
data = reg_mem[addr[addr_offset_bits-1:0]];
`endif
end
endtask
/* read chunk of registers */
task read_reg_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
if(no_of_bytes < mem_width ) begin
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - mem_width;
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
initial
begin
pre_load_rst_values(1);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int p[3500]; int n; cin >> n; bool b = 1; int j = 1; for (int i = 1; i <= n; i++) { cin >> p[i]; } sort(p + 1, p + n + 1); for (int i = 1; i <= n; i++) { if (p[i] != j) { cout << j; return 0; } else { j++; } } cout << p[n] + 1; return 0; }
|
`timescale 1ns / 1ps
module AssembledLogicAnalyzer(input CLK, input RXD_START, input [7:0] RXD, input TXD_DONE, input [15:0] DATA_IN, output TXD_ENABLE,
output [15:0] TXD);
wire RST, WE;
wire [9:0] ADDR;
wire [15:0] RAM_DATA;
wire [15:0] DATA;
wire [9:0] READ_ADDR;
wire SEL;
wire [31:0] TRIG_DATA;
wire TRIG_FORCE, TRIG_UPDATE;
ADDR_SEQUENCER seq(
.CLK(CLK),
.RST(RST),
.WE(WE),
.ADDR(ADDR)
);
OUTPUT_MUX multiplexor(
.SEL(SEL),
.TRIGGERED(TRIGGERED),
.RAM_DATA(RAM_DATA),
.DATA(TXD)
);
RAM_2_PORTS RAM(
.CLK(CLK),
.WE(WE),
.WRITE_ADDR(ADDR),
.READ_ADDR(READ_ADDR),
.DATA_IN(DATA_IN),
.DATA_OUT(RAM_DATA)
);
TRIGGER_DETECTOR trig_det(
.CLK(CLK),
.DATA_IN(DATA_IN),
.TRIG_DATA(TRIG_DATA),
.TRIG_UPDATE(TRIG_UPDATE),
.TRIG_FORCE(TRIG_FORCE),
.RST(RST),
.TRIGGERED(TRIGGERED)
);
INSTRUCTION_DECODER dec(
.CLK(CLK),
.RXD(RXD),
.RXD_START(RXD_START),
.TXD_DONE(TXD_DONE),
.TXD_ENABLE(TXD_ENABLE),
.MUX_SEL(SEL),
.RAM_ADDR(READ_ADDR),
.TRIG_DATA(TRIG_DATA),
.TRIG_UPDATE(TRIG_UPDATE),
.TRIG_FORCE(TRIG_FORCE)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) return a; else return b; } long long min(long long a, long long b) { if (a < b) return a; else return b; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long n; cin >> n; string s = ; long long i = 0; while (i < n) { if (i < n) { s += a ; i++; } if (i < n) { s += a ; i++; } if (i < n) { s += b ; i++; } if (i < n) { s += b ; i++; } } cout << s << n ; }
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is Gary
// It is the equivalent of Gary in a real Amiga
// Gary handles the address decoding and cpu/chip bus multiplexing
// Gary handles kickstart area and bootrom overlay
// Gary handles CIA e clock synchronization
//
// 20-12-2005 - started coding
// 21-12-2005 - done more coding
// 25-12-2005 - changed blitter nasty handling
// 15-01-2006 - fixed sensitivity list
// 12-11-2006 - debugging for new Minimig rev1.0 board
// 17-11-2006 - removed debugging and added decode for $C0000 ram
// ----------
// JB:
// 2008-10-06 - added decoders for IDE and GAYLE register range
// 2008-10-15 - signal name change cpuok -> dbr
// 2009-05-23 - better timing model for CIA interface
// 2009-05-24 - clean-up & renaming
// 2009-05-25 - ram, cpu and custom chips bus multiplexer
// 2009-09-01 - fixed sel_kick
// 2010-08-15 - clean-up
//
// SB:
// 2010-10-18 - added special memory config like in A500 Rev.6 with 512kb + 512kb of memory
//
// AMR:
// 2012-03-23 - Added select for Akiko
module gary
(
input [23:1] cpu_address_in, //cpu address bus input
input [20:1] dma_address_in, //agnus dma memory address input
output [18:1] ram_address_out, //ram address bus output
input [15:0] cpu_data_out,
output [15:0] cpu_data_in,
input [15:0] custom_data_out,
output [15:0] custom_data_in,
input [15:0] ram_data_out,
output [15:0] ram_data_in,
input a1k,
input cpu_rd, //cpu read
input cpu_hwr, //cpu high write
input cpu_lwr, //cpu low write
input cpu_hlt,
input ovl, //overlay kickstart rom over chipram
input dbr, //Agns takes the bus
input dbwe, //Agnus does a write cycle
output dbs, //data bus slow down
output xbs, //cross bridge select, active dbr prevents access
input [3:0] memory_config, //selected memory configuration
input ecs, // ECS chipset enable
input hdc_ena, //enables hdd interface
output ram_rd, //bus read
output ram_hwr, //bus high write
output ram_lwr, //bus low write
output sel_reg, //select chip register bank
output reg [3:0] sel_chip, //select chip memory
output reg [2:0] sel_slow, //select slowfast memory ($C0000)
output reg sel_kick, //select kickstart rom
output sel_cia, //select CIA space
output sel_cia_a, //select cia A
output sel_cia_b, //select cia B
output sel_rtc, //select $DCxxxx
output sel_ide, //select $DAxxxx
output sel_gayle //select $DExxxx
);
wire [2:0] t_sel_slow;
wire sel_xram;
wire sel_bank_1; // $200000-$3FFFFF
//--------------------------------------------------------------------------------------
assign ram_data_in = dbr ? custom_data_out : cpu_data_out;
assign custom_data_in = dbr ? ram_data_out : cpu_rd ? 16'hFFFF : cpu_data_out;
assign cpu_data_in = dbr ? 16'h00_00 : custom_data_out | ram_data_out | {16{sel_bank_1}};
//read write control signals
assign ram_rd = dbr ? ~dbwe : cpu_rd;
assign ram_hwr = dbr ? dbwe : cpu_hwr;
assign ram_lwr = dbr ? dbwe : cpu_lwr;
//--------------------------------------------------------------------------------------
// ram address multiplexer (512KB bank)
assign ram_address_out = dbr ? dma_address_in[18:1] : cpu_address_in[18:1];
//--------------------------------------------------------------------------------------
//chipram, kickstart and bootrom address decode
always @(*)
begin
if (dbr)//agnus only accesses chipram
begin
sel_chip[0] = ~dma_address_in[20] & ~dma_address_in[19];
sel_chip[1] = ~dma_address_in[20] & dma_address_in[19];
sel_chip[2] = dma_address_in[20] & ~dma_address_in[19];
sel_chip[3] = dma_address_in[20] & dma_address_in[19];
sel_slow[0] = ( ecs && memory_config==4'b0100 && dma_address_in[20:19]==2'b01) ? 1'b1 : 1'b0;
sel_slow[1] = 1'b0;
sel_slow[2] = 1'b0;
sel_kick = 1'b0;
end
else
begin
sel_chip[0] = cpu_address_in[23:19]==5'b0000_0 && !ovl ? 1'b1 : 1'b0;
sel_chip[1] = cpu_address_in[23:19]==5'b0000_1 ? 1'b1 : 1'b0;
sel_chip[2] = cpu_address_in[23:19]==5'b0001_0 ? 1'b1 : 1'b0;
sel_chip[3] = cpu_address_in[23:19]==5'b0001_1 ? 1'b1 : 1'b0;
sel_slow[0] = t_sel_slow[0];
sel_slow[1] = t_sel_slow[1];
sel_slow[2] = t_sel_slow[2];
/* TODO better solution required for loading kickstart - don-t rely on !boot && ovl, address should be 0xf80000, add another signal from osd! (cpu_rd || boot || osd_write) */
sel_kick = (cpu_address_in[23:19]==5'b1111_1 && (cpu_rd || cpu_hlt)) || (cpu_rd && ovl && cpu_address_in[23:19]==5'b0000_0) ? 1'b1 : 1'b0; //$F80000 - $FFFFF
end
end
assign t_sel_slow[0] = cpu_address_in[23:19]==5'b1100_0 ? 1'b1 : 1'b0; //$C00000 - $C7FFFF
assign t_sel_slow[1] = cpu_address_in[23:19]==5'b1100_1 ? 1'b1 : 1'b0; //$C80000 - $CFFFFF
assign t_sel_slow[2] = cpu_address_in[23:19]==5'b1101_0 ? 1'b1 : 1'b0; //$D00000 - $D7FFFF
// 512kb extra rom area at $e0 and $f0 write able only at a1k chipset mode
//assign t_sel_slow[2] = (cpu_address_in[23:19]==5'b1110_0 || cpu_address_in[23:19]==5'b1111_0) && (a1k | cpu_rd) ? 1'b1 : 1'b0; //$E00000 - $E7FFFF & $F00000 - $F7FFFF
assign sel_xram = ((t_sel_slow[0] & (memory_config[2] | memory_config[3]))
| (t_sel_slow[1] & memory_config[3])
| (t_sel_slow[2] & memory_config[2] & memory_config[3]));
assign sel_ide = hdc_ena && cpu_address_in[23:16]==8'b1101_1010 ? 1'b1 : 1'b0; //IDE registers at $DA0000 - $DAFFFF
assign sel_gayle = hdc_ena && cpu_address_in[23:12]==12'b1101_1110_0001 ? 1'b1 : 1'b0; //GAYLE registers at $DE1000 - $DE1FFF
assign sel_rtc = (cpu_address_in[23:16]==8'b1101_1100) ? 1'b1 : 1'b0; //RTC registers at $DC0000 - $DCFFFF
assign sel_reg = cpu_address_in[23:21]==3'b110 ? ~(sel_xram | sel_rtc | sel_ide | sel_gayle) : 1'b0; //chip registers at $DF0000 - $DFFFFF
assign sel_cia = cpu_address_in[23:20]==4'b1011 ? 1'b1 : 1'b0;
//cia a address decode
assign sel_cia_a = sel_cia & ~cpu_address_in[12];
//cia b address decode
assign sel_cia_b = sel_cia & ~cpu_address_in[13];
assign sel_bank_1 = cpu_address_in[23:21]==3'b001 ? 1'b1 : 1'b0;
//data bus slow down
assign dbs = cpu_address_in[23:21]==3'b000 || cpu_address_in[23:20]==4'b1100 || cpu_address_in[23:19]==5'b1101_0 || cpu_address_in[23:16]==8'b1101_1111 ? 1'b1 : 1'b0;
assign xbs = ~(sel_cia | sel_gayle | sel_ide);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; long long a[300100], sum[300100]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); for (int i = n - 1; i >= 0; i--) sum[i] = sum[i + 1] + a[i]; long long ans = sum[0]; sort(sum + 1, sum + n); for (int i = 0; i < k - 1; i++) ans += sum[n - 1 - i]; printf( %lld , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_1_V
`define SKY130_FD_SC_HS__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfstp_1 (
CLK ,
D ,
Q ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfstp_1 (
CLK ,
D ,
Q ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_l2_buf2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_l2_buf2(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_buf, dram_scbuf_ecc_r2_buf,
scbuf_dram_wr_data_r5_buf, scbuf_dram_data_vld_r5_buf,
scbuf_dram_data_mecc_r5_buf, sctag_dram_rd_req_buf,
sctag_dram_rd_dummy_req_buf, sctag_dram_rd_req_id_buf,
sctag_dram_addr_buf, sctag_dram_wr_req_buf, dram_sctag_rd_ack_buf,
dram_sctag_wr_ack_buf, dram_sctag_chunk_id_r0_buf,
dram_sctag_data_vld_r0_buf, dram_sctag_rd_req_id_r0_buf,
dram_sctag_secc_err_r2_buf, dram_sctag_mecc_err_r2_buf,
dram_sctag_scb_mecc_err_buf, dram_sctag_scb_secc_err_buf,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_buf;
output [27:0] dram_scbuf_ecc_r2_buf;
// scbuf to dram TOp
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// BOTTOM
output [63:0] scbuf_dram_wr_data_r5_buf;
output scbuf_dram_data_vld_r5_buf;
output scbuf_dram_data_mecc_r5_buf;
// sctag_dramsctag signals INputs
// @ the TOp.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
// sctag_dram BOTTOM
output sctag_dram_rd_req_buf;
output sctag_dram_rd_dummy_req_buf;
output [2:0] sctag_dram_rd_req_id_buf;
output [39:5] sctag_dram_addr_buf;
output sctag_dram_wr_req_buf;
// Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
// outputs BOTTOM
output dram_sctag_rd_ack_buf;
output dram_sctag_wr_ack_buf;
output [1:0] dram_sctag_chunk_id_r0_buf;
output dram_sctag_data_vld_r0_buf;
output [2:0] dram_sctag_rd_req_id_r0_buf;
output dram_sctag_secc_err_r2_buf ;
output dram_sctag_mecc_err_r2_buf ;
output dram_sctag_scb_mecc_err_buf;
output dram_sctag_scb_secc_err_buf;
// The placement of pins on the top and bottom should be identical to
// the placement of the data column of pins in dram_l2_buf1.v
assign dram_scbuf_data_r2_buf = dram_scbuf_data_r2 ;
assign dram_scbuf_ecc_r2_buf = dram_scbuf_ecc_r2 ;
assign scbuf_dram_wr_data_r5_buf = scbuf_dram_wr_data_r5 ;
assign scbuf_dram_data_vld_r5_buf = scbuf_dram_data_vld_r5 ;
assign scbuf_dram_data_mecc_r5_buf = scbuf_dram_data_mecc_r5 ;
assign dram_sctag_rd_ack_buf = dram_sctag_rd_ack ;
assign dram_sctag_wr_ack_buf = dram_sctag_wr_ack ;
assign dram_sctag_chunk_id_r0_buf = dram_sctag_chunk_id_r0 ;
assign dram_sctag_data_vld_r0_buf = dram_sctag_data_vld_r0;
assign dram_sctag_rd_req_id_r0_buf = dram_sctag_rd_req_id_r0;
assign dram_sctag_secc_err_r2_buf = dram_sctag_secc_err_r2;
assign dram_sctag_mecc_err_r2_buf = dram_sctag_mecc_err_r2;
assign dram_sctag_scb_mecc_err_buf = dram_sctag_scb_mecc_err;
assign dram_sctag_scb_secc_err_buf = dram_sctag_scb_secc_err;
assign sctag_dram_rd_req_buf = sctag_dram_rd_req ;
assign sctag_dram_rd_dummy_req_buf = sctag_dram_rd_dummy_req ;
assign sctag_dram_rd_req_id_buf = sctag_dram_rd_req_id ;
assign sctag_dram_addr_buf = sctag_dram_addr ;
assign sctag_dram_wr_req_buf = sctag_dram_wr_req ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, MOD = 1e9 + 7; const int n_ = 1e5 + 1000; const long double PI = acos(-1.0); long long gcd(long long a, long long b) { return (a ? gcd(b % a, a) : b); } long long power(long long a, long long n) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; } n >>= 1; a *= a; } return p; } long long power(long long a, long long n, long long mod) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; p %= mod; } n >>= 1; a *= a; a %= mod; } return p % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, h; cin >> n >> h; int res = 0; for (int(i) = 0; (i) < (n); (i)++) { int a; cin >> a; if (a > h) res += 2; else res++; } cout << res << endl; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; void _print(long long int t) { cerr << t; } void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } long long int mod1 = 1e9 + 7; long long int INF = 1e9 + 5; long long int mod = 998244353; void solve(long long int test_case) { string s; cin >> s; long long int n = s.size(); long long int take = n / 2; string ans, rev; long long int i = 0, j = n - 1; while (j >= i && take > 0) { if (j > i && s[i] == s[j]) { ans.push_back(s[i]); rev.push_back(s[i]); i++; j--; take -= 2; } else if (j - 1 > i && s[i] == s[j - 1]) { ans.push_back(s[i]); rev.push_back(s[i]); j -= 2; i++; take -= 2; } else if (j > i + 1 && s[i + 1] == s[j]) { ans.push_back(s[j]); rev.push_back(s[j]); j--; i += 2; take -= 2; } else if (j - 1 > i + 1 && s[j - 1] == s[i + 1]) { ans.push_back(s[j - 1]); rev.push_back(s[j - 1]); j -= 2; i += 2; take -= 2; } else { ans.push_back(s[i]); i++; take--; break; } } reverse(rev.begin(), rev.end()); ans += rev; if (take > 0 || ans.size() < n / 2) { cout << IMPOSSIBLE n ; } else { cout << ans; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int t = 1; long long int i = 1ll; while (t--) { solve(i); i++; } }
|
`include "datapath/alu.v"
`include "datapath/comp.v"
`include "datapath/CoProcessor0RF.v"
`include "datapath/dm.v"
`include "datapath/ext.v"
`include "datapath/im.v"
`include "datapath/mux.v"
`include "datapath/npc.v"
`include "datapath/pc.v"
`include "datapath/rf.v"
`include "control/ctrl.v"
module mips (clk, rst);
input clk;
input rst;
// Wires.
wire [31:0] pc_next;
wire [31:0] pc_cur;
wire [31:0] ins;
wire [31:0] ext_imm;
wire [31:0] routa;
wire [31:0] routb;
wire [31:0] rin;
wire [31:0] aluSrcA_mux_out;
wire [31:0] aluSrcB_mux_out;
wire [31:0] alu_out;
wire [31:0] return_addr;
wire [31:0] dm_out;
wire [4:0] rWin;
wire [31:0] cop_out;
wire [31:0] npc_out;
wire [31:0] expiaddr;
wire [31:0] jiaddr;
// Control signals.
wire [3:0] aluCtr;
wire compare;
wire branch;
wire jump;
wire [1:0] regDst;
wire [1:0] aluSrcA;
wire [1:0] aluSrcB;
wire [1:0] regWr;
wire [1:0] memWr;
wire [1:0] immExt;
wire [1:0] memtoReg;
wire [1:0] copWr;
wire [1:0] byteExt;
wire [1:0] iaddrtoNPC;
wire [4:0] manInput_raddr;
wire [31:0] manInput_shf;
pc pc(
.clk(clk),
.rst(rst),
.niaddr(pc_next),
.iaddr(pc_cur)
);
npc npc(
.iaddr(pc_cur),
.branch(branch),
.jump(jump),
.ins(ins),
.jiaddr(jiaddr),
.imm16(ins[15:0]),
.imm26(ins[25:0]),
.riaddr(npc_out),
.niaddr(pc_next)
);
im_4k im(
.iaddr(pc_cur[11:2]),
.ins(ins)
);
ext immExt_ext(
.din(ins[15:0]),
.extOp(immExt),
.dout(ext_imm)
);
mux #(32) aluSrcA_mux(
.a(routa),
.b({{27{1'b0}}, ins[10:6]}),// Shift.
.c(manInput_shf),
.ctrl_s(aluSrcA),
.dout(aluSrcA_mux_out)
);
mux #(32) aluSrcB_mux(
.a(routb),
.b(ext_imm),
.ctrl_s(aluSrcB),
.dout(aluSrcB_mux_out)
);
mux #(5) regDst_mux(
.a(ins[20:16]),// rt.
.b(ins[15:11]),// rd.
.c(manInput_raddr),
.ctrl_s(regDst),
.dout(rWin)
);
regFile rf(
.busW(rin),
.clk(clk),
.wE(regWr),
.rW(rWin),
.rA(ins[25:21]),
.rB(ins[20:16]),
.busA(routa),
.busB(routb)
);
alu alu(
.ALUop(aluCtr),
.a(aluSrcA_mux_out),
.b(aluSrcB_mux_out),
.result(alu_out),
.clk(clk)
);
dm_4k dm(
.addr(alu_out[11:0]),
.din(routb),
.byteExt(byteExt),
.wEn(memWr),
.clk(clk),
.dout(dm_out)
);
mux #(32) memtoReg_mux(
.a(alu_out),
.b(dm_out),
.c(cop_out),
.d(npc_out),
.ctrl_s(memtoReg),
.dout(rin)
);
ctrl ctrl(
.ins(ins),
.compare(compare),
.jump(jump),
.regDst(regDst),
.aluSrcA(aluSrcA),
.aluSrcB(aluSrcB),
.aluCtr(aluCtr),
.regWr(regWr),
.memWr(memWr),
.immExt(immExt),
.memtoReg(memtoReg),
.copWr(copWr),
.byteExt(byteExt),
.manInput_raddr(manInput_raddr),
.manInput_shf(manInput_shf),
.iaddrtoNPC(iaddrtoNPC)
);
comp comp(
.dinA(aluSrcA_mux_out),
.dinB(aluSrcB_mux_out),
.ins(ins),
.compare(compare),
.branch(branch)
);
CoProcessor0RF CoP0(
.clk(clk),
.din(aluSrcB_mux_out),
.wEn(copWr),
.regNum(ins[15:11]),
.sel(ins[2:0]),
.dout(cop_out),
.npc_out(npc_out),
.expiaddr(expiaddr),
.ins(ins)
);
mux #(32) iaddrtoNPC_mux(
.a(aluSrcA_mux_out),
.b(expiaddr),
.ctrl_s(iaddrtoNPC),
.dout(jiaddr)
);
endmodule // MIPS main program;
|
#include <bits/stdc++.h> using namespace std; int nbPairs[5001][5001]; const int MOD = 1e9 + 7; int main() { char s[5001], t[5001]; scanf( %s%s , &s, &t); int ss = strlen(s), st = strlen(t); for (int is = ss - 1; is >= 0; is--) for (int it = st - 1; it >= 0; it--) { if (s[is] == t[it]) nbPairs[is][it] += 1 + nbPairs[is + 1][it + 1]; nbPairs[is][it] += nbPairs[is][it + 1]; nbPairs[is][it] %= MOD; } int a = 0; for (int i = 0; i < ss; i++) { a += nbPairs[i][0]; a %= MOD; } printf( %d n , a); return 0; }
|
#include <bits/stdc++.h> using namespace std; void reverseQueue(queue<long long int>& q) { if (q.empty()) return; long long int data = q.front(); q.pop(); reverseQueue(q); q.push(data); } int main() { ios_base::sync_with_stdio(0); int n, k; cin >> n >> k; vector<long long int> friends; queue<long long int> q; map<long long int, int> check; for (int i = 0, temp; i < n; i++) { cin >> temp; friends.emplace_back(temp); if (i < k) { if (check.find(friends[i]) == check.end() || check[friends[i]] == 0) { q.push(temp); check[temp] = 1; } } } for (int i = k; i < n; i++) { if (check.find(friends[i]) == check.end() || check[friends[i]] == 0) { if (q.size() == k) { check[q.front()] = 0; q.pop(); } q.push(friends[i]); check[friends[i]] = 1; } } reverseQueue(q); cout << q.size() << endl; while (!q.empty()) { cout << q.front() << ; q.pop(); } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 300010; vector<long long> arr[MAXN]; vector<pair<long long, long long>> holdqs[MAXN]; bool visited[MAXN]; long long answer[MAXN]; long long temp[MAXN]; long long n; void dfs(long long curr, long long par, long long level, long long ans) { for (auto x : holdqs[curr]) { long long lb = level; long long rb = level + 1 + x.first; temp[lb] += x.second; if (rb <= n) { temp[rb] -= x.second; } } ans += temp[level]; answer[curr] = ans; for (auto x : arr[curr]) { if (x != par) { dfs(x, curr, level + 1, ans); } } for (auto x : holdqs[curr]) { long long lb = level; long long rb = level + 1 + x.first; temp[lb] -= x.second; if (rb <= n) { temp[rb] += x.second; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (long long i = 1; i < n; i++) { long long x, y; cin >> x >> y; arr[x].push_back(y); arr[y].push_back(x); } long long q; cin >> q; while (q--) { long long v, d, x; cin >> v >> d >> x; holdqs[v].push_back(make_pair(d, x)); } dfs(1, 1, 1, 0); for (long long i = 1; i <= n; i++) { std::cout << answer[i] << endl; } }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Update history:
*
* date: 04/08 '13
* modified content: add external interrupt
* modified by: Ye-sheng Kuo <>
*
* date: 11/08 '13
* modified content: add power gating macro
* modified by: Ye-sheng Kuo <>
* --------------------------------------------------------------------------
* IMPORTANT: Don't change blocking statement to non-blocking, it causes
* simulation problems!!
* --------------------------------------------------------------------------
* */
`timescale 1ns/1ps
`include "include/mbus_def.v"
module mbus_wire_ctrl(
input RESETn,
input DOUT_FROM_BUS,
input CLKOUT_FROM_BUS,
`ifdef POWER_GATING
input DIN,
input CLKIN,
input RELEASE_ISO_FROM_SLEEP_CTRL,
input EXTERNAL_INT,
`endif
output reg DOUT,
output reg CLKOUT
);
`ifdef POWER_GATING
always @ *
begin
if (~RESETn)
CLKOUT <= `SD 1'b1;
else if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
CLKOUT <= `SD CLKIN;
else
CLKOUT <= `SD CLKOUT_FROM_BUS;
if (~RESETn)
DOUT <= `SD 1'b1;
else if (EXTERNAL_INT)
DOUT <= `SD 0;
else
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
DOUT <= `SD DIN;
else
DOUT <= `SD DOUT_FROM_BUS;
end
end
`else
always @ *
begin
if (~RESETn)
CLKOUT <= `SD 1'b1;
else
CLKOUT <= `SD CLKOUT_FROM_BUS;
if (~RESETn)
DOUT <= `SD 1'b1;
else
DOUT <= `SD DOUT_FROM_BUS;
end
`endif
endmodule // mbus_wire_ctrl_wresetn
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:06:28 09/07/2015
// Design Name:
// Module Name: Ninth_Phase_M
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ninth_Phase_M
//SINGLE PRECISION PARAMETERS
# (parameter W_Exp = 8)
//DOUBLE PRECISION PARAMETERS
/* # (parameter W_Exp = 11) */
(
input wire clk, //system clock
input wire rst, //module's reset signal
input wire load_a, //load signals for registers
input wire load_b,
input wire [W_Exp-1:0] Exp_X, //Exponents of the operands
input wire [W_Exp-1:0] Exp_Y,
output wire [W_Exp:0] Exp_Add, //Result of the add function
output wire underflow_f //underflow flag
);
wire [W_Exp:0] U_Limit;
wire [W_Exp:0] Exp_Add_Verif;
wire underflow_exp_reg;
add_sub_carry_out #(.W(W_Exp)) EXP_Add_Reg (
.op_mode(1'b0),
.Data_A(Exp_X),
.Data_B(Exp_Y),
.Data_S(Exp_Add_Verif)
);
RegisterMult #(.W(W_Exp+1)) ExpAdd_Register ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_a),
.D(Exp_Add_Verif),
.Q(Exp_Add)
);
Comparator_Less #(.W(W_Exp+1)) Exp_unflow_Comparator (
.Data_A(Exp_Add),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) ExpUnderflow_Register ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_b),
.D(underflow_exp_reg),
.Q(underflow_f)
);
generate
if (W_Exp == 8)
assign U_Limit = 9'd127;
else
assign U_Limit = 12'd1023;
endgenerate
endmodule
|
`timescale 1ns / 1ps
module text_editor_keyboard_controller(
input sys_Clk,
input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
reg [1:0] state;
localparam
I = 2'b00,
BAT = 2'b01,
DATA = 2'b10,
UNK = 2'bXX;
wire [7:0] received_data;
wire received_data_en;
reg [7:0] previous_word;
reg send_command;
reg [7:0] the_command;
wire command_sent;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
PS2_Controller PS2_Keyboard_Controller(
// Inputs
.CLOCK_50(PS2_Clk),
.reset(Reset),
.the_command(the_command),
.send_command(send_command),
// Bidirectionals
.PS2_CLK(PS2KeyboardClk), // PS2 Clock
.PS2_DAT(PS2KeyboardData), // PS2 Data
// Outputs
.command_was_sent(command_sent),
.error_communication_timed_out( ),
.received_data(received_data),
.received_data_en(received_data_en) // If 1 - new data has been received
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
always @ (posedge sys_Clk, posedge Reset) begin: STATE_MACHINE
if(Reset) begin
state <= I;
previous_word <= 8'hXX;
send_command <= 1'bX;
the_command <= 8'hXX;
KeyData <= 8'hXX;
end else
case(state)
I: begin
state <= BAT;
KeyData <= 8'h00;
previous_word <= 8'h00;
KeyReleased <= 1'b0;
send_command <= 1'b1;
the_command <= 8'hFF; // RESET KEYBOARD
end
BAT: begin
if (command_sent) begin
send_command <= 1'b0;
end
case (received_data)
8'hAA: begin // SUCCESSFUL POST
state <= DATA;
end
8'hFC: begin
send_command <= 1'b1; // TRY TO POST AGAIN
end
default: begin
end
endcase
end
DATA: begin
if (command_sent) begin
send_command <= 1'b0;
end
if (KeyReleased) begin
KeyReleased <= 1'b0;
end
if (received_data_en) begin
previous_word <= received_data;
case(received_data)
8'hF0: begin
// Key Released
end
8'hFA: begin
// Acknowledge
end
8'hAA: begin
// Self Test Passed
end
8'hEE: begin
// Echo Response
end
8'hFE: begin
// Resend Request
end
8'h00: begin
// Error
end
8'hFF: begin
// Error
end
8'h12: begin
// Shift
end
8'h59: begin
// Shift
end
8'h58: begin
// Caps
end
8'h0D: begin
// Tab
end
8'h14: begin
// Ctrl
end
8'h11: begin
// Alt
end
8'hE0: begin
// Extra
end
8'h5A: begin
// Enter
end
default: begin
if (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE
KeyData <= received_data;
KeyReleased <= 1'b1;
end
end
endcase
end
end
default:
state <= UNK;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_0_V
`define SKY130_FD_SC_LP__O221A_0_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_0 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_0 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_0_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int ans[100100]; struct by { int l, r, id, i, num; } a[100100 * 2]; bool cmp(by a, by b) { if (a.r != b.r) return a.r < b.r; return a.id < b.id; } struct byy { int i, l; byy() {} byy(int i, int l) : i(i), l(l) {} bool operator<(const byy &rhs) const { if (l != rhs.l) return l < rhs.l; return i < rhs.i; } }; set<byy> s; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i].l, &a[i].r); a[i].i = i; a[i].id = 0; } scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &a[i + n].l, &a[i + n].r, &a[i + n].num); a[i + n].i = i; a[i + n].id = 1; } sort(a + 1, a + m + n + 1, cmp); int cnt = 0; for (int i = 1; i <= m + n; i++) { if (!a[i].id) s.insert(byy(a[i].i, a[i].l)); else { while (s.size() && a[i].num--) { set<byy>::iterator p = s.lower_bound(byy(0, a[i].l)); if (p == s.end()) break; byy now = *p; s.erase(p); ans[now.i] = a[i].i; cnt++; } } } if (cnt == n) { printf( YES n ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); } else printf( NO n ); return 0; }
|
#include<bits/stdc++.h> using namespace std; int main() { int n,i,j,cnt,ara2[20000],m; string ss; cin>>m; for(i=0;i<m;i++) { cin>>n; cin>>ss; if((ss[0]== 2 )&&(ss[n-1]== 0 )&&(ss[n-2]== 2 )&&(ss[n-3]== 0 )) { cout<< Yes <<endl; } else if((ss[0]== 2 )&&(ss[n-1]== 0 )&&(ss[n-2]== 2 )&&(ss[1]== 0 )) { cout<< Yes <<endl; } else if((ss[0]== 2 )&&(ss[1]== 0 )&&(ss[2]== 2 )&&(ss[n-1]== 0 )) { cout<< Yes <<endl; } else if((ss[0]== 2 )&&(ss[1]== 0 )&&(ss[2]== 2 )&&(ss[3]== 0 )) { cout<< Yes <<endl; } else if((ss[n-1]== 0 )&&(ss[n-2]== 2 )&&(ss[n-3]== 0 )&&(ss[n-4]== 2 )) { cout<< Yes <<endl; } else { cout<< No <<endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<int, int> A; for (int i = 0; i < n; i++) { int x; cin >> x; A[x]++; } int mx = 0; for (auto x : A) { if (x.second > mx) mx = x.second; } cout << mx; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/);
reg [5:0] addr;
parameter BANKS = 6;
parameter ROWS = 8;
wire [2:0] bank;
wire [2:0] row;
integer a;
integer used[BANKS][ROWS];
// Test loop
initial begin
for (a = 0; a < BANKS*ROWS; ++a) begin
addr[5:0] = a[5:0];
hash (addr, bank, row);
used [bank][row] ++;
if (used [bank][row] > 1) begin
$write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row);
end
end
$write("*-* All Finished *-*\n");
$finish;
end
task hash (input [5:0] addr,
output [2:0] bank,
output [2:0] row);
reg [1:0] third;
reg [1:0] fourth;
third = {addr[5], addr[4]};
fourth = {addr[3] ^ addr[1],
addr[2] ^ addr[0]};
case (third)
2'h0:
case (fourth)
2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end
2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end
2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end
2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end
endcase
2'h1:
case (fourth)
2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end
2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end
2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end
2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end
endcase
2'h2:
case (fourth)
2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end
2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end
2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end
2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end
endcase
2'h3: $stop;
endcase
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 2100; int a[N][N], b[N][N], d[N][N]; int c[N], n, tag = -1, res[N]; void print() { cout << -1; exit(0); } int cnt = 0; void solve(int id, int T) { if (T) { for (int i = 1; i <= n; i++) { if (i == tag) continue; if (d[i][id] != c[i]) res[i]++; } } else { for (int i = 1; i <= n; i++) { if (i == tag) continue; if (d[i][id] != 0) res[i]++; } } } int main() { std::ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; char ch; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> ch, a[i][j] = ch - 0 ; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> ch, b[i][j] = ch - 0 ; for (int i = 1; i <= n; i++) cin >> ch, c[i] = ch - 0 ; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) d[i][j] = a[i][j] ^ b[i][j]; for (int i = 1; i <= n; i++) if (c[i]) tag = i; if (tag == -1) { bool f = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (d[i][j]) f = 1; if (f) print(); } for (int i = 1; i <= n; i++) if (d[tag][i]) cnt++; for (int i = 1; i <= n; i++) solve(i, d[tag][i]); for (int i = 1; i <= n; i++) { if (res[i]) { cnt++; for (int j = 1; j <= n; j++) d[i][j] ^= c[j]; } } for (int j = 1; j <= n; j++) { int C = 0; bool f = 0; for (int i = 1; i <= n; i++) { if ((d[i][j] && c[i] == 0) || (!d[i][j] && c[i])) f = 1; if (d[i][j]) C++; } if (C && f) print(); } cout << cnt << n ; for (int i = 1; i <= n; i++) if (res[i]) cout << row << i - 1 << n ; for (int i = 1; i <= n; i++) if (d[tag][i]) cout << col << i - 1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { string s; cin >> s; long long n = s.size(); long long sum = 0; for (long long i = 0; i < n; i++) { sum += s[i] - 0 ; } string a = s; for (long long i = n - 2; i >= 0; i--) { if (s[i] != 0 ) { string p = s; p[i] = p[i] - 1; for (long long j = i + 1; j < n; j++) { p[j] = 9 ; } long long su = 0; for (long long i = 0; i < n; i++) { su += p[i] - 0 ; } if (su > sum) { sum = su; a = p; } } } long long f = 0; for (long long i = 0; i < a.size(); i++) { if (a[i] != 0 ) { f = 1; cout << a[i]; } if (a[i] == 0 && f == 1) { cout << a[i]; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; int mark = 1; for (int i = 1; i < s.size(); i++) { if (s[i] != s[i - 1]) { mark = -1; break; } } if (mark == 1) { cout << s; for (int i = 1; i < k; i++) { cout << s[0]; } return 0; } for (int i = s.size() - 1; i >= 1; i--) { string t1 = s.substr(0, i); string t2 = s.substr(s.size() - i, i); if (t1 == t2) { int len = s.size() - i; string ost = s.substr(i, len); string ans = s; for (int j = 1; j < k; j++) { ans += ost; } int kol = 0; for (int j = 0; j + s.size() <= ans.size(); j++) { string mr = ans.substr(j, s.size()); if (mr == s) { kol++; if (kol == k) { string prt = ans.substr(0, j + s.size()); cout << prt << endl; return 0; } } } } } for (int i = 1; i <= k; i++) { cout << s; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_1_V
`define SKY130_FD_SC_HVL__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_1_V
|
#include <bits/stdc++.h> using namespace std; char _buf[100000], *_op(_buf), *_ed(_buf); inline int getint() { int _s = 0, _f = 1; char _ch = (_op == _ed && (_ed = (_op = _buf) + fread(_buf, 1, 100000, stdin), _op == _ed) ? EOF : *_op++); while (!( 0 <= _ch && _ch <= 9 )) (_ch == - ) && (_f = -1), _ch = (_op == _ed && (_ed = (_op = _buf) + fread(_buf, 1, 100000, stdin), _op == _ed) ? EOF : *_op++); while (( 0 <= _ch && _ch <= 9 )) _s = _s * 10 + _ch - 48, _ch = (_op == _ed && (_ed = (_op = _buf) + fread(_buf, 1, 100000, stdin), _op == _ed) ? EOF : *_op++); return _s * _f; } const int N = 2e5 + 1, mod = 1e9 + 7; inline void check(int& x) { x -= mod, x += x >> 31 & mod; } inline void cmax(int& x, int y) { if (x - y >> 31) x = y; } inline void cmin(int& x, int y) { if (y - x >> 31) x = y; } int n, m, ans; int Sx, Sy, Fx, Fy; int X[N], Y[N], tag[N]; int idx[N], idy[N], posx[N], posy[N]; inline int dis(int x, int y, int p) { return min(abs(X[p] - x), abs(Y[p] - y)); } priority_queue<pair<int, int> > q; inline void input() { n = getint(), m = getint(); Sx = getint(), Sy = getint(), Fx = getint(), Fy = getint(); for (int i = 1; i <= m; i++) X[i] = getint(), Y[i] = getint(); ans = abs(Fx - Sx) + abs(Fy - Sy); for (int i = 1; i <= m; i++) q.push(pair<int, int>(-dis(Sx, Sy, i), i)); } inline int cmpx(int x, int y) { return X[x] < X[y]; } inline int cmpy(int x, int y) { return Y[x] < Y[y]; } inline void init() { for (int i = 1; i <= m; i++) idx[i] = i; sort(idx + 1, idx + 1 + m, cmpx); for (int i = 1; i <= m; i++) posx[idx[i]] = i; for (int i = 1; i <= m; i++) idy[i] = i; sort(idy + 1, idy + 1 + m, cmpy); for (int i = 1; i <= m; i++) posy[idy[i]] = i; } inline void work() { for (int u, w, v; !q.empty();) { w = -q.top().first, u = q.top().second, q.pop(); if (tag[u]) continue; tag[u] = 1, ans = min(0ll + ans, 0ll + w + abs(X[u] - Fx) + abs(Y[u] - Fy)); if ((v = idx[posx[u] - 1]) && !tag[v]) q.push(pair<int, int>(-w - X[u] + X[v], v)); if ((v = idx[posx[u] + 1]) && !tag[v]) q.push(pair<int, int>(-w - X[v] + X[u], v)); if ((v = idy[posy[u] - 1]) && !tag[v]) q.push(pair<int, int>(-w - Y[u] + Y[v], v)); if ((v = idy[posy[u] + 1]) && !tag[v]) q.push(pair<int, int>(-w - Y[v] + Y[u], v)); } cout << ans << n ; } int main() { input(); init(); work(); return 0; }
|
#include <bits/stdc++.h> const int MAX = 1000010; const long long MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const long long LLINF = 0x3f3f3f3f3f3f3f3f; const long double EPS = 1e-6; const long double PI = acos(-1.0); using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, x, y; cin >> n; cout << YES n ; for (int i = 0; i < n; i++) { cin >> x >> y; cin >> x >> y; if (x & 1) { if (y & 1) cout << 1 << n ; else cout << 2 << n ; } else { if (y & 1) cout << 3 << n ; else cout << 4 << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, t, x, y, ed, pt, bcc, done, cnt, cycl; int qd[400005], qn[400005], l[400005], v[400005], w[400005], vv[400005], d[400005], AP[400005], p[400005], vis[400005]; int col[400005], par[400005], L[400005], C[400005], cc[400005], vc[400005], pp[400005]; vector<int> P; void bd(int x, int y) { qd[++ed] = y, qn[ed] = l[x], l[x] = ed; } void dfs(int x, int y) { int c = 0; v[x] = w[x] = ++t; p[x] = y; for (int i = l[x]; i; i = qn[i]) if (!v[qd[i]]) { dfs(qd[i], x); w[x] = min(w[x], w[qd[i]]); ++c; if ((y >= 0 && w[qd[i]] >= v[x]) || (y < 0 && c > 1)) AP[x] = 1; } else if (qd[i] != y) w[x] = min(w[x], v[qd[i]]); } void color(int x, int y) { vis[x] = 1; for (int i = l[x]; i; i = qn[i]) { if (col[i ^ 1]) continue; if (p[x] == -1 || (AP[x] && w[qd[i]] >= v[x])) { col[i] = col[i ^ 1] = ++bcc; color(qd[i], bcc); } else { col[i] = col[i ^ 1] = y; if (!vis[qd[i]]) color(qd[i], y); } } } void cyc(int x, int p) { vv[x] = 1; par[x] = p; for (int i = (l[x]); i; i = qn[i]) if (qd[i] != p) { if (!vv[qd[i]]) cyc(qd[i], x); else if (vv[qd[i]] == 1 && !cycl) { int t = x; while (1) { C[cycl++] = t; cc[t] = 1; if (t == qd[i]) break; t = par[t]; } } } vv[x] = 2; } void shoot(int x, int p) { if (done) return; vc[x] = 1; pp[x] = p; for (int i = (l[x]); i; i = qn[i]) if (!vc[qd[i]] && !done) { if (p == -1 && cc[qd[i]]) continue; if (cc[qd[i]]) { done = 1; pp[qd[i]] = x; pt = qd[i]; } else shoot(qd[i], x); } } void print() { printf( %d , P.size()); for (int i = (0); i < (P.size()); i++) printf( %d , P[i]); puts( ); } void doit(int y, int j) { P.clear(); for (int k = y; k != j; k = (k + 1 == cycl ? 0 : k + 1)) P.push_back(C[k] + 1); P.push_back(C[j] + 1); print(); P.clear(); for (int k = y; k != j; k = (k == 0 ? cycl - 1 : k - 1)) P.push_back(C[k] + 1); P.push_back(C[j] + 1); print(); } struct edge { int x, y, c; bool operator<(edge const &T) const { return c < T.c; } }; edge E[400005]; int main() { scanf( %d%d , &n, &m); ed = 1; for (int i = (0); i < (m); i++) { scanf( %d%d , &x, &y), --x, --y; bd(x, y), bd(y, x); } for (int i = (0); i < (n); i++) if (!v[i]) dfs(i, -1); for (int i = (0); i < (n); i++) if (!vis[i]) color(i, -1); memset(l, 0, sizeof(l)); for (int i = (2); i <= (ed); i++) { E[i - 2].x = qd[i]; E[i - 2].y = qd[i ^ 1]; E[i - 2].c = col[i]; } int Edges = ed - 1; sort(E, E + Edges); int ptr = 0; for (int bb = (1); bb <= (bcc); bb++) { ed = cnt = 0; while (ptr < Edges && E[ptr].c == bb) { bd(E[ptr].x, E[ptr].y); ++d[E[ptr].x]; L[cnt++] = E[ptr].x; ++ptr; } if (cnt < 4) goto AFTER; cycl = 0; cyc(L[0], -1); for (int j = (0); j < (cycl); j++) if (d[C[j]] > 2) { for (int k = (l[C[j]]); k; k = qn[k]) { int y = qd[k]; if (!cc[y]) continue; if (y == C[(j + 1) % cycl] || y == C[(j + cycl - 1) % cycl]) continue; puts( YES ); printf( 2 %d %d n , y + 1, C[j] + 1); int ty = y; for (int k = (0); k < (cycl); k++) if (C[k] == ty) y = k; doit(y, j); return 0; } done = 0; shoot(C[j], -1); if (done) { puts( YES ); for (int k = (0); k < (cycl); k++) if (C[k] == pt) y = k; doit(y, j); P.clear(); while (1) { P.push_back(pt + 1); if (pt == C[j]) break; pt = pp[pt]; } print(); return 0; } } AFTER: for (int i = (0); i < (cnt); i++) vv[L[i]] = vc[L[i]] = cc[L[i]] = l[L[i]] = d[L[i]] = 0; } puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int a; string type; node() {} node(int x, const char *s) { a = x; type = s; } }; map<string, node> h; char str[100]; int main() { int n; scanf( %d , &n); char a[100], b[100]; int x, y; h[ void ] = node(0, void ); for (int i = 1; i <= n; i++) { scanf( %s , str); if (strcmp(str, typedef ) == 0) { scanf( %s %s , a, b); x = y = 0; int j = 0; while (a[j] == & ) j++, x++; j = strlen(a) - 1; while (a[j] == * ) j--, y++; a[j + 1] = 0; node tmp; if (h.find(a + x) == h.end()) { tmp = node(0, errtype ); } else tmp = h[a + x]; x -= y; tmp.a += x; if (tmp.a > 0) { tmp.type = errtype ; } h[b] = tmp; } else { scanf( %s , a); x = y = 0; int j = 0; while (a[j] == & ) j++, x++; j = strlen(a) - 1; while (a[j] == * ) j--, y++; a[j + 1] = 0; node t; if (h.find(a + x) == h.end()) { t = node(0, errtype ); } else t = h[a + x]; x -= y; t.a += x; if (t.a > 0) { cout << errtype << endl; } else { cout << t.type; if (t.type != errtype ) { for (int i = 1; i <= -t.a; i++) putchar( * ); } puts( ); } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__mux2 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_20_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (u_mux_20_out_X , A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_20_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_FUNCTIONAL_PP_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int W, H; while (cin >> W >> H) { vector<pair<int, int>> pset; for (int dy = 0; dy < (int)(2); ++dy) for (int dx = 0; dx < (int)(2); ++dx) { if (dx <= W && dy <= H) pset.push_back(pair<int, int>(dx, dy)); } for (int dy = 0; dy < (int)(2); ++dy) for (int dx = 0; dx < (int)(2); ++dx) { if (dx <= W && H - dy >= 0) pset.push_back(pair<int, int>(dx, H - dy)); } for (int dy = 0; dy < (int)(2); ++dy) for (int dx = 0; dx < (int)(2); ++dx) { if (W - dx >= 0 && dy <= H) pset.push_back(pair<int, int>(W - dx, dy)); } for (int dy = 0; dy < (int)(2); ++dy) for (int dx = 0; dx < (int)(2); ++dx) { if (W - dx >= 0 && H - dy >= 0) pset.push_back(pair<int, int>(W - dx, H - dy)); } sort(pset.begin(), pset.end()); pset.erase(unique(pset.begin(), pset.end()), pset.end()); vector<pair<double, vector<pair<int, int>>>> ans; for (int comb = (1 << 4) - 1; comb < (1 << pset.size());) { vector<pair<int, int>> ps; for (int i = 0; i < (int)(pset.size()); ++i) if (comb >> i & 1) { ps.push_back(pset[i]); } sort(ps.begin(), ps.end()); do { double len = 0; for (int i = 0; i < (int)(3); ++i) { len += hypot(ps[i].first - ps[i + 1].first, ps[i].second - ps[i + 1].second); } ans.push_back(make_pair(len, ps)); } while (next_permutation(ps.begin(), ps.end())); int x = comb & -comb, y = comb + x; comb = ((comb & ~y) / x >> 1) | y; } sort(ans.begin(), ans.end()); vector<pair<int, int>> ps = ans.back().second; for (int i = 0; i < (int)(4); ++i) { cout << ps[i].first << << ps[i].second << endl; } } return 0; }
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_const;
// Inputs
reg clk;
reg [5:0] addr;
// Outputs
wire [1007:0] out;
wire effective;
reg [1007:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const_ uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
initial begin
// Initialize Inputs
addr = 0; clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {6'b000101, 1002'd0};
#(`P); check;
addr = 8; w_out = {6'b001001, 1002'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 1002'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:37:25 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
// opedTop.v - Top Level Verilog wrapper for NETFPGA10G "OPED" component
// Copyright (c) 2010 Atomic Rules LLC, ALL RIGHTS RESERVED
// 2010-10-31 ssiegel Creation with WCI::AXI only
// 2010-11-02 ssiegel Made debug a 32b vector
// 2010-11-22 ssiegel Minor noodling
module opedTop(
// Outward-Facing Direct Connection to PCIe pads...
input wire pcie_clk_p, // PCIe Clock +
input wire pcie_clk_n, // PCIe Clock -
input wire pcie_reset_n, // PCIe Reset (active low)
output wire [7:0] pcie_txp, // PCIe lanes...
output wire [7:0] pcie_txn,
input wire [7:0] pcie_rxp,
input wire [7:0] pcie_rxn,
output wire [31:0] debug // Debug Port Bitfields...
// debug[31:3] reserved // For future use, will read as '0'
// debug[2] oped_egress // True when TL data is making egress to PCIe from OPED
// debug[1] oped_ingress // True when TL data is making ingress from PCIe to OPED
// debug[0] oped_linkp // True when the PCIe link-layer is established with OPED
//TODO: AXI ports to be added...
/*
// Inward-Facing OPED signals, clock, resets for AXI ports...
output wire oped_clk125, // OPED Clock Output (nominaly 125 MHz)
output wire oped_reset, // OPED Reset (active high)
// WCI::AXI AXI4-Lite Master WCIM0...
output wire wcim0_awvalid, // (AW) Write Address Channel...
input wire wcim0_awready,
output wire [31:0] wcim0_awaddr,
output wire [ 2:0] wcim0_awprot,
output wire wcim0_wvalid, // (W) Write Data Channel...
input wire wcim0_wready,
output wire [31:0] wcim0_wdata,
output wire [ 3:0] wcim0_wstrb,
input wire wcim0_bvalid, // (B) Write Response Channel...
output wire wcim0_bready,
output wire [ 1:0] wcim0_bresp,
output wire wcim0_arvalid, // (AR) Read Address Channel...
input wire wcim0_arready,
output wire [31:0] wcim0_araddr,
output wire [ 2:0] wcim0_arprot,
input wire wcim0_rvalid, // (R) Read Response Channel..
output wire wcim0_rready,
output wire [31:0] wcim0_rdata,
output wire [ 1:0] wcim0_rresp,
// WSI::AXI AXI4-Stream Master 0 WSI-M0...
output wire wsim0_tvalid, // (T) Stream Channel...
input wire wsim0_tready,
output wire [255:0] wsim0_tdata, // 32B (256b) Message Data
output wire [ 31:0] wsim0_tstrb,
output wire wsim0_tlast,
// WSI::AXI AXI4-Stream Master Info Channel 0 WSI-M0ic...
output wire wsim0ic_tvalid, // (T) Stream Channel...
input wire wsim0ic_tready,
output wire [ 15:0] wsim0ic_tdata, // 4B (16b) Stream Info Channel
output wire [ 3:0] wsim0ic_tstrb,
output wire wsim0ic_tlast,
// WSI::AXI AXI4-Stream Slave 1 WSI-S0...
input wire wsis0_tvalid, // (T) Stream Channel...
output wire wsis0_tready,
input wire [255:0] wsis0_tdata, // 32B (256b) Message Data
input wire [ 31:0] wsis0_tstrb,
input wire wsis0_tlast,
// WSI::AXI AXI4-Stream Slave Info Channel 1 WSI-S0ic...
input wire wsis0ic_tvalid, // (T) Stream Channel...
output wire wsis0ic_tready,
input wire [ 15:0] wsis0ic_tdata, // 4B (16b) Stream Info Channel
input wire [ 3:0] wsis0ic_tstrb,
input wire wsis0ic_tlast
*/
);
// The implementation of module opedTop follows. This may be made opaque,
// black-boxed, etc, and should be of no concern to the average NETFPGA-10G user.
// The purpose is to provide some ligweight "impedence-matching" between the
// BSV compiler-generated mkOPED implementation.
//
// Core Team: Shep owns this interface contract from this point down...
wire unused_1;
// Instance and connect mkOPED...
mkOPED moped(
.pcie_clk_p (pcie_clk_p),
.pcie_clk_n (pcie_clk_n),
.pcie_reset_n (pcie_reset_n),
.pcie_rxp_i (pcie_rxp),
.pcie_rxn_i (pcie_rxn),
.pcie_txp (pcie_txp),
.pcie_txn (pcie_txn),
.debug (debug),
.trnClk (oped_clk125),
.CLK_GATE_trnClk (unused_1)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_0_2 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { stringstream ss; string x, s1, s2, s3; long long int a1 = 0, a2 = 0, a3 = 0, sum = -1, q = 0; cin >> x; int z = x.size(); for (int i = 1; i < (z - 1); i++) { for (int j = 1; j < (z - i); j++) { q = 0; stringstream ss1, ss2, ss3; s1 = x.substr(0, i); s2 = x.substr(i, j); s3 = x.substr((i + j), (z - i - j)); if ((s1[0] == 0 && s1.size() > 1) || (s2[0] == 0 && s2.size() > 1) || (s3[0] == 0 && s3.size() > 1)) continue; { ss1 << s1; ss1 >> a1; ss1.clear(); ss2 << s2; ss2 >> a2; ss2.clear(); ss3 << s3; ss3 >> a3; ss3.clear(); if (a1 > 1000000 || a2 > 1000000 || a3 > 1000000) continue; q = a1 + a2 + a3; if (q > sum) sum = q; } } } cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; long long dp[511][511]; long long tol[511]; int main() { int n, k, i, j, p; scanf( %d%d , &n, &k); for (i = 1; i <= n; ++i) dp[0][i] = 1; for (i = 1; i <= n; ++i) { for (j = 1; j <= n; ++j) { for (p = max(i - j, 0); p <= i - 1; ++p) { dp[i][j] = dp[i][j] + dp[p][j]; dp[i][j] %= mod; } } } for (i = 1; i <= n; ++i) { tol[i] = dp[n][i] - dp[n][i - 1]; } long long ans = 0; for (i = 1; i <= n; ++i) { for (j = 1; j <= n; ++j) { if (i * j < k) { ans += tol[i] * tol[j]; ans %= mod; } } } ans *= 2; cout << (ans % mod + mod) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bitset<4096> f[100020]; int a[13][100005], b[100005][13], now; bool cmp(int x, int y) { return a[x][now] == a[y][now] ? x > y : a[x][now] > a[y][now]; } int main() { int n, q, k, cnt, op, x, y; scanf( %d%d%d , &n, &k, &q); cnt = k; for (int i = 1; i <= k; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]), b[j][i] = i; for (int i = 1; i <= n; i++) now = i, sort(b[i] + 1, b[i] + k + 1, cmp); for (int i = 1; i <= k; i++) for (int j = 0; j < (1 << k); j++) if (j & (1 << (i - 1))) f[i][j] = 1; while (q--) { scanf( %d%d%d , &op, &x, &y); if (op == 1) cnt++, f[cnt] = f[x] | f[y]; else if (op == 2) cnt++, f[cnt] = f[x] & f[y]; else for (int i = 1, t = 0; i <= k; i++) { t |= (1 << (b[y][i] - 1)); if (f[x][t]) { printf( %d n , a[b[y][i]][y]); break; } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> status(26); vector<vector<int> > adjList(200000); vector<string> names(100); vector<int> ts; vector<int> processing(26); void dfs(int u, bool &valid) { status[u] = 1; processing[u] = true; for (int j = 0; j < adjList[u].size(); j++) { int v = adjList[u][j]; if (processing[v] == true) { valid = false; return; } if (status[v] == 0) { dfs(v, valid); } } processing[u] = false; ts.push_back(u); } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> names[i]; } for (int i = 0; i < 26; i++) { status[i] = 0; processing[i] = false; } for (int i = 0; i < n - 1; i++) { int c1 = -1; int c2 = -1; for (int j = 0; j < names[i].size() && j < names[i + 1].size(); j++) { if (names[i][j] != names[i + 1][j]) { c1 = names[i][j]; c2 = names[i + 1][j]; adjList[(c1 - a )].push_back(c2 - a ); break; } } if (c1 == -1 && c2 == -1 && names[i].size() > names[i + 1].size()) { cout << Impossible << endl; return 0; } } for (int i = 0; i < 26; i++) { if (status[i] == 0) { bool valid = true; dfs(i, valid); if (!valid) { cout << Impossible << endl; return 0; } } } for (int i = ts.size() - 1; i >= 0; i--) { cout << (char)( a + ts[i]); } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long C[4003 + 2][4003 + 2]; void pascal() { for (int i = 0; i < 4003; ++i) C[i][i] = C[i][0] = 1; for (int i = 2; i < 4003; ++i) { for (int j = 1; j < i; ++j) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % 1000000007LL; } } long long pd[4003 + 2]; long long spd[4003]; long long proc(int N) { pd[1] = 1; pd[2] = 3; pd[3] = 10; if (N < 4) return pd[N]; spd[1] = 1; spd[2] = 4; spd[3] = 14; for (int n = 4; n <= N; n++) { for (int i = 2; i < n; i++) { pd[n] = (pd[n] + (spd[i - 1] * C[n][i]) % 1000000007LL) % 1000000007LL; } for (int i = 0; i < n; i++) { pd[n] = (pd[n] + C[n][i]) % 1000000007LL; } spd[n] = (spd[n - 1] + pd[n]) % 1000000007LL; } return pd[N]; } int main() { pascal(); int n; scanf( %d , &n); printf( %lld n , proc(n)); }
|
module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
//input wire clk_ddr3_100_p,
input wire fpga_reset_n,
//QSPI
output wire qspi_clk,
inout wire[3:0] qspi_io,
output wire qspi_csn,
//ddr3
//output wire [13:0] mem_a,
//output wire [2:0] mem_ba,
//inout wire [0:0] mem_ck,
//inout wire [0:0] mem_ck_n,
//output wire [0:0] mem_cke,
//output wire [0:0] mem_cs_n,
//output wire [0:0] mem_dm,
//output wire [0:0] mem_ras_n,
//output wire [0:0] mem_cas_n,
//output wire [0:0] mem_we_n,
//output wire mem_reset_n,
///inout wire [7:0] mem_dq,
//inout wire [0:0] mem_dqs,
//inout wire [0:0] mem_dqs_n,
//output wire [0:0] mem_odt,
//i2c
inout wire i2c_sda,
inout wire i2c_scl,
//spi
input wire spi_miso,
output wire spi_mosi,
output wire spi_sclk,
output wire spi_ssn,
//16550 UART
input wire uart_rx,
output wire uart_tx,
output wire [4:0] user_led
);
//Heart-beat counter
reg [25:0] heart_beat_cnt;
//DDR3 interface assignments
//wire local_init_done;
//wire local_cal_success;
//wire local_cal_fail;
//i2c interface
wire i2c_serial_sda_in ;
wire i2c_serial_scl_in ;
wire i2c_serial_sda_oe ;
wire i2c_serial_scl_oe ;
assign i2c_serial_scl_in = i2c_scl;
assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
assign i2c_serial_sda_in = i2c_sda;
assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
//assign system_resetn = fpga_reset_n & local_init_done;
// SoC sub-system module
ghrd_10m50da ghrd_10m50da_inst (
.clk_clk (clk_50),
//.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
.reset_reset_n (fpga_reset_n),
//.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
.ext_flash_qspi_pins_data (qspi_io),
.ext_flash_qspi_pins_dclk (qspi_clk),
.ext_flash_qspi_pins_ncs (qspi_csn),
//.memory_mem_a (mem_a[12:0] ), // memory.mem_a
//.memory_mem_ba (mem_ba ), // .mem_ba
//.memory_mem_ck (mem_ck ), // .mem_ck
//.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
//.memory_mem_cke (mem_cke ), // .mem_cke
//.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
//.memory_mem_dm (mem_dm ), // .mem_dm
//.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
//.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
//.memory_mem_we_n (mem_we_n ), // .mem_we_n
//.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
//.memory_mem_dq (mem_dq ), // .mem_dq
//.memory_mem_dqs (mem_dqs ), // .mem_dqs
//.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
//.memory_mem_odt (mem_odt ), // .mem_odt
//.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
//.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
//.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
//i2c
.i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
.i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
.i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
.i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
//spi
.spi_0_external_MISO (spi_miso), // spi_0_external.MISO
.spi_0_external_MOSI (spi_mosi), // .MOSI
.spi_0_external_SCLK (spi_sclk), // .SCLK
.spi_0_external_SS_n (spi_ssn), // .SS_n
//pio
.led_external_connection_export (user_led[3:0]),
//16550 UART
.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
);
//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
//assign mem_a[13] = 1'b0;
//Heart beat by 50MHz clock
always @(posedge clk_50 or negedge fpga_reset_n)
if (!fpga_reset_n)
heart_beat_cnt <= 26'h0; //0x3FFFFFF
else
heart_beat_cnt <= heart_beat_cnt + 1'b1;
assign user_led[4] = heart_beat_cnt[25];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct inf { long long t, w; }; struct djk { long long n, v; bool operator>(const djk &i) const { return v < i.v; } bool operator<(const djk &i) const { return v > i.v; } } n; struct edge { long long n1, n2, t; bool operator<(const edge &i) const { return t < i.t; } }; long long nodes, edges, n1, n2, weight, nn, totes, p1, p2, ports; long long isp[100005], cp[100005], pd[100005], rnk[100005], head[100005]; edge elist[100005]; vector<inf> nlist[100005]; priority_queue<djk> viser; long long ufind(long long n) { if (head[n] != n) head[n] = ufind(head[n]); return head[n]; } void uni(long long n1, long long n2) { p1 = ufind(n1); p2 = ufind(n2); if (rnk[p1] > rnk[p2]) head[p1] = p2; else if (rnk[p2] > rnk[p1]) head[p2] = p1; else head[p1] = p2, rnk[p1]++; } int main() { scanf( %I64d%I64d , &nodes, &edges); for (int i = 1; i <= nodes; i++) pd[i] = -1, head[i] = i, rnk[i] = 1; for (int i = 1; i <= edges; i++) { scanf( %I64d%I64d%I64d , &n1, &n2, &weight); nlist[n1].push_back({n2, weight}); nlist[n2].push_back({n1, weight}); elist[i] = {n1, n2, weight}; } scanf( %I64d , &ports); for (int i = 1; i <= ports; i++) { scanf( %I64d , &n1); isp[n1] = 1; viser.push({n1, 0}); pd[n1] = 0; cp[n1] = n1; } while (!viser.empty()) { n = viser.top(); viser.pop(); if (pd[n.n] > n.v) continue; for (int i = 0; i < nlist[n.n].size(); i++) { nn = nlist[n.n][i].t; if (pd[nn] == -1 || pd[nn] > nlist[n.n][i].w + pd[n.n]) { pd[nn] = nlist[n.n][i].w + pd[n.n]; cp[nn] = cp[n.n]; viser.push({nn, pd[nn]}); } } } for (int i = 1; i <= edges; i++) elist[i].t += pd[elist[i].n1] + pd[elist[i].n2]; sort(elist + 1, elist + 1 + edges); for (int i = 1; i <= edges; i++) { if (ufind(cp[elist[i].n1]) != ufind(cp[elist[i].n2])) { uni(cp[elist[i].n1], cp[elist[i].n2]); totes += elist[i].t; } } if (!isp[1] && pd[1] != -1) totes += pd[1]; printf( %I64d n , totes); return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[20][20], ans[20]; int n, m; bool isValid() { for (int i = 2; i <= n; i++) { int c = 0; for (int j = 1; j <= m; j++) c += (ans[j] != a[i][j]); if (c > 1) return false; } return true; } void fun() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> (a[i] + 1); for (int i = 1; i <= m; i++) ans[i] = a[1][i]; ans[m + 1] = 0 ; if (isValid()) cout << (ans + 1) << n ; else { bool isGood = false; for (int i = 1; i <= m && !isGood; i++) { for (char c = a ; c <= z && !isGood; c++) { if (c != a[1][i]) { ans[i] = c; if (isValid()) { cout << (ans + 1) << n ; isGood = true; } } } ans[i] = a[1][i]; } if (!isGood) cout << -1 n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { fun(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 1000000; int n; char s[MAXN + 1]; int pac[MAXN], npac; int ast[MAXN], nast; int prvpac[MAXN], prvast[MAXN]; int mxpos[MAXN]; bool canrgt[MAXN]; int calcmxpos(int i, int t) { int x = i - t >= 0 ? prvast[i - t] : -1; if (x == -1) return prvpac[i] == -1 ? i : max(i, prvpac[i] + t); if (prvpac[i] == -1 || prvpac[i] <= x) return canrgt[x] ? i : -1; if (prvpac[prvpac[i]] != -1 && prvpac[prvpac[i]] > x) return mxpos[prvpac[prvpac[i]]] != -1 ? max(i, prvpac[i] + t) : -1; return canrgt[x] ? max(i, prvpac[i] + t) : mxpos[prvpac[i]] != -1 ? i : -1; } bool calccanrgt(int x, int t) { int i = prvpac[x]; if (i == -1 || x - i > t) return false; int y = prvast[i]; return mxpos[i] != -1 && mxpos[i] >= x || y == -1 || (prvpac[i] != -1 && prvpac[i] > y && mxpos[prvpac[i]] != -1) || canrgt[y]; } bool canall(int t) { for (int i = (0); i < (n); ++i) { if (s[i] == P ) { mxpos[i] = calcmxpos(i, t); } if (s[i] == * ) { canrgt[i] = calccanrgt(i, t); } } int idx = max(pac[npac - 1], ast[nast - 1]); if (s[idx] == P ) return mxpos[idx] != -1; else if (s[idx] == * ) return canrgt[idx]; else { assert(false); return false; } } pair<int, int> solve() { npac = nast = 0; for (int i = (0); i < (n); ++i) { prvast[i] = nast == 0 ? -1 : ast[nast - 1]; prvpac[i] = npac == 0 ? -1 : pac[npac - 1]; if (s[i] == P ) pac[npac++] = i; else if (s[i] == * ) ast[nast++] = i; } assert(npac > 0 && nast > 0); if (npac == 1) { int nleft = 0, tleft = 0, nright = 0, tright = 0; for (int i = (0); i < (nast); ++i) if (ast[i] < pac[0]) { ++nleft; tleft = max(tleft, pac[0] - ast[i]); } else { ++nright; tright = max(tright, ast[i] - pac[0]); } if (nleft > nright || nleft == nright && tleft <= tright) return make_pair(nleft, tleft); else return make_pair(nright, tright); } int l = 0, r = n - 1; while (l + 1 < r) { int m = l + (r - l) / 2; if (canall(m)) r = m; else l = m; } return make_pair(nast, r); } void run() { scanf( %d , &n); scanf( %s , s); pair<int, int> ans = solve(); printf( %d %d n , ans.first, ans.second); } int main() { run(); return 0; }
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; int n, m, Q, a[300006][2], fa[300006], dep[300006], siz[300006], b[300006], D; bool vis[300006]; map<int, int> mp[300006]; vector<int> v[300006], s[300006]; const double pi = acos(-1.0); void df5(int te, int la) { vis[te] = 1; siz[te] = 1; for (int i = 0; i < v[te].size(); i++) { int j = v[te][i]; if (j == la) continue; if (vis[j]) continue; dep[j] = dep[te] + 1; fa[j] = te; df5(j, te); siz[te] += siz[j]; } } inline double getde(int x, int y) { double ret = atan2(1.0 * a[y][1] - a[x][1], 1.0 * a[y][0] - a[x][0]); if (ret < 0) ret += 2.0 * pi; return ret; } inline bool cmp(int x, int y) { return getde(D, x) < getde(D, y); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); v[x].push_back(y), v[y].push_back(x); } for (int i = 1; i <= n; i++) scanf( %d%d , &a[i][0], &a[i][1]); df5(1, 1); for (int i = 1; i <= n; i++) { D = i; sort(v[i].begin(), v[i].end(), cmp); for (int j = 0; j < v[i].size(); j++) mp[i][v[i][j]] = j; if (!v[i].empty()) { if (v[i][0] == fa[i]) s[i].push_back(-siz[i]); else if (fa[v[i][0]] == i) s[i].push_back(siz[v[i][0]]); else s[i].push_back(0); } for (int j = 1; j < v[i].size(); j++) { int x = v[i][j], la = s[i][j - 1]; if (x == fa[i]) s[i].push_back(la - siz[i]); else if (fa[x] == i) s[i].push_back(la + siz[x]); else s[i].push_back(la); } } scanf( %d , &Q); while (Q--) { int k; scanf( %d , &k); bool hv1 = false; for (int i = 1; i <= k; i++) scanf( %d , &b[i]); for (int i = 1; i <= k; i++) if (b[i] == 1) { hv1 = true; break; } long long sum = 0; bool flag = false; for (int i = 1; i <= k; i++) { int ii = i % k + 1; sum += (1ll * (a[b[i]][0] - a[b[ii]][0]) * a[b[i]][1] - 1ll * a[b[i]][0] * (a[b[i]][1] - a[b[ii]][1])); } if (sum > 0) flag = true; long long ans = 0; if (!flag) { for (int i = 2, j = k; i < j; i++, j--) swap(b[i], b[j]); } for (int i = 1; i <= k; i++) { int la = i - 1; if (!la) la = k; int nx = i % k + 1; int ts1 = mp[b[i]][b[la]], ts2 = mp[b[i]][b[nx]], tt = ((int)v[b[i]].size()) - 1; if (ts1 >= ts2) { if (ts1) ans += s[b[i]][ts1]; if (ts2) ans -= s[b[i]][ts2 - 1]; } else { ans += s[b[i]][ts1]; if (ts2) ans += s[b[i]][tt] - s[b[i]][ts2 - 1]; } } ans += k; if (ans <= 0) ans += n; printf( %lld n , ans); } }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; template <typename... T> void rd(T&... args) { ((cin >> args), ...); } template <typename... T> void wr(T... args) { ((cout << args << ), ...); cout << endl; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tt; cin >> tt; while (tt--) { int n; cin >> n; vector<int> a(n), l(n); for (auto& i : a) cin >> i; for (auto& i : l) cin >> i; vector<int> tmp; for (int i = 0; i < n; i++) { if (!l[i]) { tmp.push_back(a[i]); } } sort(tmp.begin(), tmp.end()); for (int i = 0; i < n; i++) { if (l[i]) cout << a[i] << ; else { cout << tmp.back() << ; tmp.pop_back(); } } cout << n ; } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 01:41:24 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_100 CLK" *) input clk_100;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_50 CLK" *) output clk_50;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_25 CLK" *) output clk_25;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_12_5 CLK" *) output clk_12_5;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_6_25 CLK" *) output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
(* ORIG_REF_NAME = "vga_pll" *)
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`include "defs.v"
// Bundling CPU and ICache together
module toycpu(
input clk, // clock
input rst, // reset
// Memory bus
input [31:0] bus_data_in, // bus data in
input bus_data_in_ready, // bus data ready
input bus_data_ack, // acknowledge write op
output bus_data_wr, // request data write
output bus_data_rd, // request data read
output [31:0] bus_data_address, // output data address
output [31:0] bus_data_out, // data to be written
// CPU signals
input irq, // IRQ requested
input [3:0] irqn, // IRQ number
output irq_ack, // Interrupt acknowledged and processed
output irq_busy, // Busy doing current interrupt (maintain your fifo outside!)
output [31:0] debug_reg_out,
input [3:0] debug_reg_num,
input debug,
input step,
output step_ack,
input stall
);
wire [31:0] ic_addr;
wire [31:0] ic_data_out;
wire [31:0] ic_bus_data_address;
wire [31:0] ic_data_in;
wire [31:0] data_in;
wire [31:0] data_out;
wire [31:0] data_address;
wire ic_rq;
wire ic_data_out_valid;
wire data_ack;
wire data_wr;
wire data_rd;
wire data_in_ready;
wire ic_data_in_ready;
wire ic_data_rd;
wire [31:0] stack_real_addr_a;
wire [31:0] stack_real_addr_b;
wire stack_wr_a;
wire [31:0] stack_datain_a;
wire [31:0] stack_data_a;
wire [31:0] stack_data_b;
toycpu_core core1(.clk(clk),
.rst(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out(ic_data_out),
.ic_data_out_valid(ic_data_out_valid),
.data_in(data_in),
.data_in_ready(data_in_ready),
.data_ack(data_ack),
.data_wr(data_wr),
.data_rd(data_rd),
.data_address(data_address),
.data_out(data_out),
.irq(irq),
.irqn(irqn),
.irq_ack(irq_ack),
.irq_busy(irq_busy),
.debug_reg_out(debug_reg_out),
.debug_reg_num(debug_reg_num),
.debug(debug),
.step(step),
.step_ack(step_ack),
.stall(stall),
.stack_real_addr_a(stack_real_addr_a),
.stack_real_addr_b(stack_real_addr_b),
.stack_data_a(stack_data_a),
.stack_data_b(stack_data_b),
.stack_wr_a(stack_wr_a),
.stack_datain_a(stack_datain_a)
);
toyblockram stack ( .clk(clk),
.addr_a(stack_real_addr_a),
.data_a(stack_data_a),
.datain_a(stack_datain_a),
.wr_a(stack_wr_a),
.addr_b(stack_real_addr_b),
.data_b(stack_data_b)
);
toy_icache cache1 (.clk(clk),
.reset(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out_valid(ic_data_out_valid),
.ic_data_out(ic_data_out),
.data_in(ic_data_in),
.data_in_ready(ic_data_in_ready),
.data_rd(ic_data_rd),
.data_address(ic_bus_data_address));
wire grant_ic;
wire grant_lsu;
reg ic_rq_cnt;
reg lsu_rq_cnt;
wire gnt2;
wire gnt3;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(ic_rq_cnt),
.req1(lsu_rq_cnt),
.req2(0),
.req3(0),
.gnt0(grant_ic),
.gnt1(grant_lsu),
.gnt2(gnt2),
.gnt3(gnt3)
);
always @(posedge clk)
if(!rst) begin
ic_rq_cnt <= 0;
lsu_rq_cnt <= 0;
end else begin
if (ic_data_rd) ic_rq_cnt <= 1;
else if (grant_ic && !bus_data_in_ready) ic_rq_cnt <= 0;
if (data_rd|data_wr) lsu_rq_cnt <= 1;
else if (grant_lsu && !bus_data_in_ready && !bus_data_ack)
lsu_rq_cnt <= 0;
end
assign ic_data_in_ready = grant_ic?bus_data_in_ready:0;
assign data_in_ready = grant_lsu?bus_data_in_ready:0;
assign ic_data_in = grant_ic?bus_data_in:0;
assign data_in = grant_lsu?bus_data_in:0;
// Memory bus combinational logic
assign bus_data_address = grant_ic?ic_bus_data_address:data_address;
assign bus_data_wr = grant_lsu?data_wr:0;
assign bus_data_rd = grant_ic?ic_data_rd:grant_lsu?data_rd:0;
assign bus_data_out = grant_lsu?data_out:0;
assign data_ack = grant_lsu?bus_data_ack:0;
endmodule // toycpu
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// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_atomics_arb_stall
#(
// Configuration
parameter integer STALL_CYCLES = 6
)
(
input logic clock,
input logic resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
/******************
* Local Variables *
******************/
reg shift_register [0:STALL_CYCLES-1];
wire atomic;
wire stall;
integer t;
/******************
* Local Variables *
******************/
assign out_intf.req.request = ( in_intf.req.request & ~stall ); // mask request
assign out_intf.req.read = ( in_intf.req.read & ~stall ); // mask read
assign out_intf.req.write = ( in_intf.req.write & ~stall ); // mask write
assign out_intf.req.writedata = in_intf.req.writedata;
assign out_intf.req.burstcount = in_intf.req.burstcount;
assign out_intf.req.address = in_intf.req.address;
assign out_intf.req.byteenable = in_intf.req.byteenable;
assign out_intf.req.id = in_intf.req.id;
assign in_intf.stall = ( out_intf.stall | stall );
/*****************
* Detect Atomic *
******************/
assign atomic = ( out_intf.req.request == 1'b1 &&
out_intf.req.read == 1'b1 &&
out_intf.req.writedata[0:0] == 1'b1 ) ? 1'b1 : 1'b0;
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
shift_register[0] <= 1'b0;
end
else begin
shift_register[0] <= atomic;
end
end
/*****************
* Shift Register *
******************/
always@(posedge clock or negedge resetn)
begin
for (t=1; t< STALL_CYCLES; t=t+1)
begin
if ( !resetn ) begin
shift_register[t] <= 1'b0;
end
else begin
shift_register[t] <= shift_register[t-1];
end
end
end
/***************
* Detect Stall *
***************/
assign stall = ( shift_register[STALL_CYCLES-1] == 1'b1 );
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { string p, h; int w = 0; cin >> p >> h; sort(p.begin(), p.end()); if (h.size() >= p.size()) { for (int i = 0; i < (h.size() - p.size() + 1); i++) { string sub = h.substr(i, p.size()); sort(sub.begin(), sub.end()); if (sub == p) { w = 1; break; } } if (w == 1) cout << YES << endl; else cout << NO << endl; } else cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> int n, k, pos[1000005]; char s[1000005]; struct ac_automaton { int ch[1000005][26], fail[1000005], arr[1000005], cnt[1000005], totc; int fir[1000005], nxt[1000005], to[1000005], tot, in[1000005], out[1000005], block; void line(int x, int y) { nxt[++tot] = fir[x]; fir[x] = tot; to[tot] = y; } void update(int x, int d) { for (int i = x; i <= block; i += i & (-i)) arr[i] += d; } int getsum(int x) { int s = 0; for (int i = x; i; i -= i & (-i)) s += arr[i]; return s; } void insert(char *s, int k) { int r = 0, v; for (int i = 0; s[i]; i++) { v = s[i] - a ; if (!ch[r][v]) ch[r][v] = ++totc; r = ch[r][v]; } pos[k] = r; } int Q[1000005], head, tail; void build() { Q[head = 0] = 0, tail = 1; int r, c; while (head < tail) { r = Q[head++]; for (int i = 0; i < 26; i++) if (c = ch[r][i]) { Q[tail++] = c; fail[c] = r ? ch[fail[r]][i] : 0; } else ch[r][i] = ch[fail[r]][i]; } for (int i = 1; i <= totc; i++) line(fail[i], i); } void dfs(int u) { in[u] = ++block; for (int i = fir[u]; i; i = nxt[i]) dfs(to[i]); out[u] = block; } void modify(int x, int d) { if (cnt[x] == d) return; cnt[x] = d; update(in[x], d); update(out[x] + 1, -d); } int find(char *s) { int r = 0, v, ans = 0; for (int i = 0; s[i]; i++) { v = s[i] - a ; r = ch[r][v]; ans += getsum(in[r]); } return ans; } } A; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= k; i++) scanf( %s , s), A.insert(s, i); A.build(); A.dfs(0); for (int i = 1; i <= k; i++) A.modify(pos[i], 1); int x; char c; for (int i = 1; i <= n; i++) { getchar(), c = getchar(); if (c == ? ) scanf( %s , s), printf( %d n , A.find(s)); else scanf( %d , &x), A.modify(pos[x], c == + ? 1 : -1); } }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; vector<pair<int, int> > arr(n); for (int i = 0; i < n; i++) cin >> arr[i].first; for (int i = 0; i < n; i++) cin >> arr[i].second; sort(arr.begin(), arr.end()); long long int cost = 1e18; long long int prev = 0; for (int i = n - 1; i >= 0; i--) { cost = min(cost, max((long long int)arr[i].first, prev)); prev += arr[i].second; } cost = min(cost, prev); cout << cost << endl; } }
|
// DESCRIPTION: Verilator: Test generate index usage.
//
// The code illustrates a problem in Verilator's handling of constant
// expressions inside generate indexes.
//
// This is a regression test against issue 517.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
`define START 8
`define SIZE 4
`define END (`START + `SIZE)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [`END-1:0] y;
wire [`END-1:0] x;
foo foo_i (.y (y),
.x (x),
.clk (clk));
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module foo(output wire [`END-1:0] y,
input wire [`END-1:0] x,
input wire clk);
function peek_bar;
peek_bar = bar_inst[`START].i_bar.r; // this is ok
peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not.
endfunction
genvar g;
generate
for (g = `START; g < `END; g = g + 1) begin: bar_inst
bar i_bar(.x (x[g]),
.y (y[g]),
.clk (clk));
end
endgenerate
endmodule : foo
module bar(output wire y,
input wire x,
input wire clk);
reg r = 0;
assign y = r;
always @(posedge clk) begin
r = x ? ~x : y;
end
endmodule : bar
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> int dx[] = {-1, -1, -1, 0, 0, 0, 1, 1, 1}; int dy[] = {-1, 0, 1, -1, 0, 1, -1, 0, 1}; using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } long long to_int(string s) { long long ans = 0; for (int i = 0; i < s.size(); i++) { ans = ans * 10 + (s[i] - 48); } return ans; } int l[100001]; int r[100001]; int a[100001]; int main() { fast(); int d1, d2, d3, ans = 0; cin >> d1 >> d2 >> d3; if (d2 < d1) swap(d2, d1); ans += d1; ans += min(d3, d1 + d2); ans += min(d2, d3 + d1); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1000100; struct node { int w, flag; int a, b; int id; long long num; } a[M]; int n, pos[M], m, s[M]; bool cmp(const node &x, const node &y) { if (x.w == y.w) return x.flag > y.flag; return x.w < y.w; } int fa[M]; bool cmp1(const node &x, const node &y) { return x.id < y.id; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &a[i].w, &a[i].flag); a[i].id = i; } sort(a + 1, a + 1 + m, cmp); for (int i = 1; i <= n; i++) fa[i] = i; int k = 1; for (int i = 1; i <= m; i++) if (a[i].flag) { a[i].a = k; pos[k] = i; a[i].num = (long long)(k - 1) * k / 2 + 1; a[i].b = ++k; } bool flag = 0; for (int i = 1; i <= m; i++) if (a[i].flag) if (a[i].num < (long long)i) { flag = 1; break; } if (flag) { printf( -1 n ); return 0; } pos[n] = m + 1; int h = 3, s1 = 1; for (int i = 1; i < n; i++) { for (int j = pos[i] + 1; j < pos[i + 1];) { a[j].a = s1; a[j].b = h; s1++; if (s1 == h - 1) { s1 = 1; h++; } j++; } } if (flag) { printf( -1 n ); return 0; } sort(a + 1, a + 1 + m, cmp1); for (int i = 1; i <= m; i++) printf( %d %d n , a[i].a, a[i].b); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct _ { _() { ios_base::sync_with_stdio(0); } } _; template <class A, class B> ostream &operator<<(ostream &o, pair<A, B> t) { o << ( << t.first << , << t.second << ) ; return o; } template <class T> string tostring(T first, int len = 0, char c = 0 ) { stringstream ss; ss << first; string r = ss.str(); if (r.length() < len) r = string(len - r.length(), c) + r; return r; } template <class T> void PV(T a, T b, int n = 0, int w = 0, string s = ) { int c = 0; while (a != b) { cout << tostring(*a++, w, ); if (a != b && (n == 0 || ++c % n)) cout << s; else cout << endl; } } template <class T> inline bool chmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <class T> inline bool chmax(T &a, T b) { return a < b ? a = b, 1 : 0; } const long long linf = 0x3f3f3f3f3f3f3f3fLL; const int inf = 0x3f3f3f3f; const int mod = int(1e9) + 7; const int N = 111111; vector<int> prime; bool isp[N]; vector<int> oddPrime; void generatePrime(int n = 1000000) { memset(isp, 1, sizeof(isp)); ; isp[0] = isp[1] = 0; for (int i = 2; i <= n; i++) { if (!isp[i]) continue; prime.push_back(i); for (int j = i + i; j <= n; j += i) { isp[j] = 0; } } } int cnt[10000]; long long cc; inline int isPrime(int *a, int n) { int r = 0; for (int i = 0; i < n; i++) r = 10 * r + a[i]; return isp[r]; } int D[5][5], n, res; void dfs(int r, int c) { if (n <= 4 && r == n - 1) { res++; return; } if (n == 5 && r == n - 2) { res += cnt[D[3][0] * 1000 + D[3][1] * 100 + D[3][2] * 10 + D[3][4]]; return; } for (int i = 0; i < 10; i++) { D[r][c] = D[c][r] = i; if (c == n - 2) { if (isPrime(D[r], n)) dfs(r + 1, r + 1); } else { dfs(r, c + 1); } if (D[r][n - 1] == 2) break; } } int main() { generatePrime(100000); for (int i : prime) { int t = i; int ok = 1; while (t > 0) { if (t % 10 != 2 && t % 2 == 0) ok = 0; t /= 10; } if (ok) oddPrime.push_back(i); int j = i / 100 * 10 + i % 10; cnt[j]++; } int T; cin >> T; while (T--) { int first; cin >> first; string s = tostring(first); n = s.length(); res = 0; for (int second : oddPrime) { if (tostring(second).size() > n) continue; for (int i = 0; i < n; i++) D[0][i] = D[i][0] = s[i] - 0 ; string os = tostring(second, n); if (os[0] != s[n - 1]) continue; int ok = 1; for (int i = 0; i < n; i++) { int t = os[i] - 0 ; D[i][n - 1] = D[n - 1][i] = t; if (t % 2 == 0 && D[0][i] != 0) ok = 0; } if (ok) dfs(1, 1); } cout << res << endl; } cerr << [ 0 -> clock() : << 1e3 * (clock() - 0) / CLOCKS_PER_SEC << ms] n ; ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a; cin >> n >> m; a = n % m; for (int i = 1; i <= m; i++) { if (a > 0) { cout << n / m + 1 << ; a--; } else { cout << n / m << ; } } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_gray_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_gray_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_gray_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_gray_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; priority_queue<long long> Q[3]; int K[4], T[5]; int n; void gao() { int i, j; for (i = 0; i < 3; ++i) { for (j = 0; j < K[i]; ++j) Q[i].push(-1); } long long ans = 0; while (n--) { int ti; scanf( %d , &ti); long long now_min = Q[0].top(); now_min = min(now_min, -ti + 0LL); Q[0].pop(); now_min -= T[0]; Q[0].push(now_min); long long tmp = Q[1].top(); Q[1].pop(); now_min = min(now_min, tmp); now_min -= T[1]; Q[1].push(now_min); tmp = Q[2].top(); Q[2].pop(); now_min = min(now_min, tmp); now_min -= T[2]; Q[2].push(now_min); ans = max(ans, -now_min - ti); } cout << ans << endl; } int main() { int i, j; for (i = 0; i < 3; ++i) cin >> K[i]; for (i = 0; i < 3; ++i) cin >> T[i]; cin >> n; for (i = 0; i < 3; ++i) K[i] = min(K[i], n); gao(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2015; const int inf = 1 << 29; int n, h, a[maxn], l[maxn], r[maxn]; double p, dp[maxn][maxn][2][2]; int main() { cin >> n >> h >> p; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = 0; i < n; i++) { int lb = i - 1; for (; lb >= 0 && a[lb + 1] - a[lb] < h; lb--) ; l[i] = lb; int rb = i + 1; for (; rb < n && a[rb] - a[rb - 1] < h; rb++) ; r[i] = rb; } for (int len = 1; len <= n; len++) { for (int leftFall = 0; leftFall < 2; leftFall++) { for (int rightFall = 0; rightFall < 2; rightFall++) { for (int start = 0; start + len - 1 < n; start++) { int end = start + len - 1; if (leftFall == 0) { int tmp = -inf; if (start > 0) { tmp = a[start - 1]; } dp[start][end][leftFall][rightFall] += 0.5 * p * (min(h, a[start] - tmp) + dp[start + 1][end][0][rightFall]); } else { int tmp = -inf; if (start > 0) { tmp = a[start - 1] + h; } dp[start][end][leftFall][rightFall] += 0.5 * p * (min(h, a[start] - tmp) + dp[start + 1][end][0][rightFall]); } if (rightFall == 1) { int tmp = inf; if (end < n - 1) { tmp = a[end + 1]; } dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * (min(h, tmp - a[end]) + dp[start][end - 1][leftFall][1]); } else { int tmp = inf; if (end < n - 1) { tmp = a[end + 1] - h; } dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * (min(h, tmp - a[end]) + dp[start][end - 1][leftFall][1]); } if (end < r[start]) { dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * (a[end] - a[start]); if (rightFall == 1) { int tmp = inf; if (end < n - 1) { tmp = a[end + 1]; } dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * min(h, tmp - a[end]); } else { int tmp = inf; if (end < n - 1) { tmp = a[end + 1] - h; } dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * min(h, tmp - a[end]); } } else { dp[start][end][leftFall][rightFall] += 0.5 * (1 - p) * (a[r[start] - 1] - a[start] + h + dp[r[start]][end][1][rightFall]); } if (l[end] < start) { dp[start][end][leftFall][rightFall] += 0.5 * p * (a[end] - a[start]); if (leftFall == 0) { int tmp = -inf; if (start > 0) { tmp = a[start - 1]; } dp[start][end][leftFall][rightFall] += 0.5 * p * min(h, a[start] - tmp); } else { int tmp = -inf; if (start > 0) { tmp = a[start - 1] + h; } dp[start][end][leftFall][rightFall] += 0.5 * p * min(h, a[start] - tmp); } } else { dp[start][end][leftFall][rightFall] += 0.5 * p * (a[end] - a[l[end] + 1] + h + dp[start][l[end]][leftFall][0]); } } } } } cout << setprecision(9) << fixed << dp[0][n - 1][0][0] << n ; return 0; }
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n,
input rx_n,
input rx_p,
output tx_n,
output tx_p,
input ibufds_gte2_i,
input ibufds_gte2_ib
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
GTPE2_CHANNEL GTPE2_CHANNEL (
.GTPRXP(rx_p),
.GTPRXN(rx_n),
.GTPTXP(tx_p),
.GTPTXN(tx_n)
);
(* keep *)
IBUFDS_GTE2 IBUFDS_GTE2 (
.I (ibufds_gte2_i),
.IB(ibufds_gte2_ib)
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ba.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char *name, Arg1 &&arg1) { cerr << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char *names, Arg1 &&arg1, Args &&...args) { const char *comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } using ll = long long; using P = pair<int, int>; using vi = vector<int>; const char nl = n ; const int inf = 2e9; const ll INF = (ll)2e18; const ll mod = 1e9 + 7; const int N = 2e6 + 15; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, x; cin >> n; vi a(n), pos(n + 1); vi bucket(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) { cin >> x; pos[x] = i; } for (int i = 0; i < n; ++i) { if (pos[a[i]] <= i) { bucket[i - pos[a[i]]]++; } else { bucket[i + n - pos[a[i]]]++; } } int ans = 0; for (int i = 0; i < n; ++i) { ans = max(ans, bucket[i]); } cout << ans << nl; return 0; }
|
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
module bm_functional_test(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
counter
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [7:0] counter;
reg [`B2TS-1:0] out0;
reg [`B2TS-1:0] out1;
wire [`B2TS-1:0] temp1;
wire [`B2TS-1:0] temp2;
wire [`B2TS-1:0] temp3;
wire [`B2TS-1:0] temp4;
reg [7:0]counter;
always @(posedge clock or negedge reset_n)
begin
if (~reset_n)
begin
counter <= 0;
out1<= 0;
out0<= 0;
end
else
begin
case (counter)
8'b00000000: out0 <= a_in & b_in;
8'b00000001: out0 <= a_in | b_in;
8'b00000010: out0 <= a_in ^ b_in;
8'b00000011: out0 <= a_in * b_in;
8'b00000100: out0 <= a_in + b_in;
8'b00000101: out0 <= a_in - b_in;
8'b00000110: out0 <= temp1;
8'b00000111: out0 <= temp2;
8'b00001000: out0 <= temp3;
8'b00001001: out0 <= temp4;
8'b00001010: out0 <= temp1 ? temp2 : temp3;
default: out0 <= 8'b11001101;
endcase
if (counter <= 8'b00001111)
begin
out1 <= 1;
end
else
begin
out1 <= 0;
end
if (counter == 8'b11111111)
counter <= 0;
else
counter <= counter + 1;
end
end
assign temp1 = c_in * d_in;
assign temp2 = c_in + d_in;
assign temp3 = c_in - d_in;
assign temp4 = ~c_in & d_in;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a211o (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rng_64(chrono::steady_clock::now().time_since_epoch().count()); const double PI = 2 * acos(0.0); const string DIGITS = 0123456789 ; const string ALPH = abcdefghijklmnopqrstuvwxyz ; istream &operator>>(istream &in, pair<int, int> &a) { in >> a.first >> a.second; return in; } ostream &operator<<(ostream &out, pair<int, int> &a) { out << a.first << << a.second; return out; } istream &operator>>(istream &in, pair<double, double> &a) { in >> a.first >> a.second; return in; } ostream &operator<<(ostream &out, pair<double, double> &a) { out << a.first << << a.second; return out; } template <class T0, class T1> inline ostream &operator<<(ostream &out, pair<T0, T1> &a) { return out << { << a.first << , << a.second << } ; } template <class T0, class T1, class T2> inline ostream &operator<<(ostream &out, tuple<T0, T1, T2> &a) { return out << { << get<0>(a) << , << get<1>(a) << , << get<2>(a) << } ; } template <class T0, class T1, class T2, class T3> inline ostream &operator<<(ostream &out, tuple<T0, T1, T2, T3> &a) { return out << { << get<0>(a) << , << get<1>(a) << , << get<2>(a) << , << get<3>(a) << } ; } template <class T> inline ostream &operator<<(ostream &out, vector<T> &a) { out << [ ; for (int i = 0; i < int(a.size()); ++i) out << a[i] << vector<string>{ , , ] }[i + 1 == a.size()]; return out; } void print(int n, int k, vector<tuple<int, int, int, int> > kek) { ofstream cout( output.txt ); cout << n << << k << n ; for (auto p : kek) { int r, x, y, z; tie(r, x, y, z) = p; cout << x << << y << << z << << r << n ; } cout.close(); exit(0); } void smain(); signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << setprecision(12) << fixed; smain(); } const int M1 = 1000000093, p1 = 27162; const int M2 = 1000000087, p2 = 241; const double pi = atan2(1, 0) * 2, EPS = 1e-9; const int pw = 10, N = 2e5 + 10, oo = 1e9 + 100, B = 1000, M = 998244353; const int NN = 1e4; const int RND = 37542135; template <class KEY, class VAL, int N> struct HashTable { pair<KEY, VAL> hmap[NN]; HashTable(KEY a, KEY b) { for (int i = 0; i < int(NN); ++i) hmap[i] = {a, b}; } int has1(KEY v) { return (v ^ RND) % NN; } int h1(KEY v, int i) { return (has1(v) + i) % NN; } int find(KEY v) { int pos, i = 0; do { pos = h1(v, i); if (hmap[pos].first == v) return pos; i++; } while (hmap[pos].first != -1 && i != NN); assert(i != NN); return pos; } VAL get(KEY key) { int pos = find(key); return hmap[pos].second; } void set(KEY key, VAL val) { int lol = find(key); hmap[lol] = {key, val}; } }; vector<int> vertices1[N]; vector<int> vertices2[N]; vector<int> bvertices[N]; int used[N], used2[N], TIMER = 1; long long trans(long long a, long long b) { return (a << 18) | b; } void dfs(int v, int col) { used[v] = col; for (int u : vertices2[v]) { if (!used[u]) dfs(u, col); } } void dfs2(int v) { used2[v] = TIMER; for (int u : bvertices[v]) { if (used2[u] != TIMER) dfs2(u); } } void smain() { int n, m; cin >> n >> m; vector<tuple<int, int, int> > quer(m); for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; quer[i] = make_tuple(a, b, c); } int last = 0; vector<int> vertex; vertex.reserve(4 * B); vector<pair<int, int> > edges; edges.reserve(B); for (int i = 0; i <= n; ++i) bvertices[i].reserve(B / 10); for (int i = 0; i < m; i += B) { vertex.clear(); HashTable<long long, int, NN> abused(-1, 0); for (int i = 0; i <= n; ++i) { bvertices[i].clear(); vertices2[i].clear(); vertices2[i].reserve(((int)((vertices1[i]).size()))); } for (int j = i; j < min(m, i + B); ++j) { int a, b, c; tie(a, b, c) = quer[j]; if (a == 1) { if (b > c) swap(b, c); abused.set(trans(b, c), 1); vertex.push_back(b); vertex.push_back(c); b++, c++; if (b == n + 1) b = 1; if (c == n + 1) c = 1; if (b > c) swap(b, c); vertex.push_back(b); vertex.push_back(c); abused.set(trans(b, c), 1); } else { vertex.push_back(b); vertex.push_back(c); b++, c++; if (b == n + 1) b = 1; if (c == n + 1) c = 1; vertex.push_back(b); vertex.push_back(c); } } for (int v = 1; v <= n; ++v) for (int &u : vertices1[v]) if (!abused.get(trans(min(v, u), max(v, u)))) { vertices2[v].push_back(u); } int col = 1; fill(used, used + N, 0); for (auto &v : vertex) if (!used[v]) dfs(v, col++); edges.clear(); for (int v = 1; v <= n; ++v) for (int &u : vertices1[v]) if (abused.get(trans(v, u))) { if (used[u] != used[v]) { bvertices[used[v]].push_back(used[u]); bvertices[used[u]].push_back(used[v]); } edges.push_back(make_pair(min(v, u), (max(v, u)))); } for (int j = i; j < min(m, i + B); ++j) { int a, b, c; tie(a, b, c) = quer[j]; if (last) b++, c++; if (b == n + 1) b = 1; if (c == n + 1) c = 1; if (b > c) swap(b, c); if (a == 1) { if (find(edges.begin(), edges.end(), make_pair(b, (c))) != edges.end()) { edges.erase(find(edges.begin(), edges.end(), make_pair(b, (c)))); if (used[b] != used[c]) { bvertices[used[b]].erase(find(bvertices[used[b]].begin(), bvertices[used[b]].end(), used[c])); bvertices[used[c]].erase(find(bvertices[used[c]].begin(), bvertices[used[c]].end(), used[b])); } } else { edges.push_back(make_pair(b, (c))); if (used[b] != used[c]) { bvertices[used[b]].push_back(used[c]); bvertices[used[c]].push_back(used[b]); } } } else { if (used[b] == used[c]) { cout << 1 ; last = 1; } else { dfs2(used[b]); if (used2[used[c]] == TIMER) { cout << 1 ; last = 1; } else { cout << 0 ; last = 0; } TIMER++; } } } for (int i = 1; i <= n; ++i) vertices1[i] = vertices2[i]; for (auto &p : edges) { vertices1[p.first].push_back(p.second); vertices1[p.second].push_back(p.first); } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char arr1[n][m]; char arr2[m][n]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char a; cin >> a; arr1[i][j] = a; arr2[j][i] = a; } } string ans = ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (count(arr1[i], arr1[i] + m, arr1[i][j]) == 1 && count(arr2[j], arr2[j] + n, arr1[i][j]) == 1) { ans += string(1, arr1[i][j]); } } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; bool endline = false; template <class T> istream& operator>>(istream& inp, vector<T>& v) { for (auto& it : v) inp >> it; return inp; } template <class T> ostream& operator<<(ostream& out, vector<T>& v) { for (auto& it : v) out << it << (endline ? n : ); return out; } template <class T, class U> istream& operator>>(istream& inp, pair<T, U>& v) { inp >> v.first >> v.second; return inp; } template <class T, class U> ostream& operator<<(ostream& out, pair<T, U>& v) { out << v.first << << v.second; return out; } const int mod1 = 998244353, mod = 1e9 + 7; const int MAXN = 1e6 + 6, MAXM = 5e5 + 5; const int inf = 2e9; const long long linf = 1e18; long long n, m, a[5050]; void Solve() { cin >> n >> m; long long tmp = 0, i; for (i = 1; i <= n; i++) { if (tmp + (i - 1) / 2 < m) { a[i] = i; tmp += (i - 1) / 2; } else { long long gap = m - tmp; if (gap == 0) { a[i] = i; } else { a[i] = a[i - 1] + a[i - 2 * gap]; } tmp += gap; i++; break; } } if (tmp < m) { cout << -1; return; } for (; i <= n; i++) { a[i] = 1e8 + i * i; } for (i = 1; i <= n; i++) { cout << a[i] << ; } } signed main() { if (fopen( .inp , r )) { freopen( .inp , r , stdin); freopen( .out , w , stdout); }; std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long TC = 1; while (TC--) Solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 5; int N, M, K; int A[MAXN]; long long P, H; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; for (int i = 1; i <= N; i++) { cin >> P; A[i] = A[i - 1] + __builtin_popcountll(P); M = 0; for (int j = i - 1; j >= 0; j--) { if (A[i] - A[j] >= 118) { break; } M = max(M, A[j + 1] - A[j]); if ((A[i] - A[j]) & 1) { continue; } if (A[i] - A[j] < 2 * M) { H--; } } if (A[i] & 1) { H += K; K++; } else { H += i - K; } } cout << H << n ; return 0; }
|
#include <bits/stdc++.h> bool V[11][11]; int T[11][11]; int R = 0, C = 0, N = 0, K = 0, t1 = 0, t2 = 0; int W = 0; int main() { scanf( %d%d%d%d , &R, &C, &N, &K); for (int i = 1; i <= N; i++) { scanf( %d%d , &t1, &t2); V[t1][t2] = true; } for (int i = 1; i <= R; i++) for (int j = 1; j <= C; j++) { T[i][j] = T[i - 1][j] + T[i][j - 1] - T[i - 1][j - 1]; if (V[i][j]) T[i][j]++; } for (int i = 1; i <= R; i++) for (int j = 1; j <= C; j++) for (int k = i; k <= R; k++) for (int l = j; l <= C; l++) { if (T[k][l] - T[i - 1][l] - T[k][j - 1] + T[i - 1][j - 1] >= K) W++; } printf( %d n , W); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long lv[100001], lf[100001], par[100001], n; vector<long long> con[100001], cld[100001]; long long get_leaf(long long id) { if (cld[id].size() == 0) { lf[1]++; return 1; } long long x = 0, i; for (i = 0; i <= cld[id].size() - 1; i++) { x += get_leaf(cld[id][i]); } lf[x]++; return x; } int main() { ios_base::sync_with_stdio(0); long long int i, j, x, y, m, cnt = 0, k, g, flg, t, l, r, md; cin >> n; for (i = 2; i <= n; i++) { cin >> x; con[x].push_back(i); con[i].push_back(x); } queue<long long> q; q.push(1); while (!q.empty()) { x = q.front(); q.pop(); if (con[x].size() == 0) continue; for (i = 0; i <= con[x].size() - 1; i++) { y = con[x][i]; if (par[y] || y == 1) continue; par[y] = x; cld[x].push_back(y); q.push(y); } } x = get_leaf(1); for (i = 2; i <= n; i++) { lf[i] += lf[i - 1]; } for (i = 1; i <= n; i++) { l = 0; r = n; while (r - l > 1) { md = (l + r) / 2; if (lf[md] < i) l = md; else r = md; } cout << r << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { double x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; double vmax, t0, vx, vy, wx, wy; cin >> vmax >> t0 >> vx >> vy >> wx >> wy; double dx = (x2 - x1); double dy = (y2 - y1); double l = 0, r = 1e16; double ans = 1e16; for (int i = 0; i < 200; i++) { double t = (l + r) / 2; double xx = vx * (t0 < t ? t0 : t); double yy = vy * (t0 < t ? t0 : t); if (t > t0) { xx += wx * (t - t0); yy += wy * (t - t0); } if ((xx - dx) * (xx - dx) + (yy - dy) * (yy - dy) > vmax * vmax * t * t) l = t; else { r = t; ans = t; } } printf( %.12f n , ans); }
|
#include <bits/stdc++.h> using namespace std; int N; char S[1010]; int E[1010], F[1010][2]; int main() { scanf( %d , &N); scanf( %s , S); memset(E, 0, sizeof(E)); for (int i = 0; i < N; i++) { E[i + 1] = S[i] - 0 ; F[i + 1][0] = F[i + 1][1] = 0x3f3f3f3f; } F[0][0] = F[0][1] = 0; for (int i = 1; i <= N; i++) for (int j = 0; j < 2; j++) { if (E[i] == j) { F[i][j] = min(F[i][j], F[i - 1][1 - j]); } else if (E[i] == 1 - j) { F[i][j] = min(F[i][j], F[i - 1][E[i]] + 1); } if (i - 2 >= 0) { if (E[i] == E[i - 1]) { F[i][j] = min(F[i][j], F[i - 2][j] + 1); } else if (E[i] != E[i - 1]) { if (E[i] == j) F[i][j] = min(F[i][j], F[i - 2][j]); else if (E[i] != j) F[i][j] = min(F[i][j], F[i - 2][j] + 2); } } } int ans = min(F[N][0], F[N][1]); if (ans == 0x3f3f3f3f) ans = -1; cout << ans << endl; return 0; }
|
// ----------------------------------------------------------------------------
// Module: porf_gen.v
// Project: MOS 6502 Processor
// Author: George Castillo <>
// Date: 09 July 2017
//
// Description: Synchronous reset module which synchronizes the assertion (and
// most importantly) the deassertion of a reset signal. The reset signal
// generated by this module is an implementation of high-performance local reset
// suggested by Xilinx in WP272.
//
// This circuit was designed using Xilinx primitives to specifically control
// the placement and implementation details. The number of flip-flops in the
// chain determines the minimum duration of the reset pulse that will be issued
// to the localized network.
// ----------------------------------------------------------------------------
module porf_gen
#(
parameter N = 4
)
(
input async_reset,
input clk,
input clk_enable,
output sync_reset
);
wire d_1;
wire [N:1] q;
assign sync_reset = q[N];
assign d_1 = 1'b0;
// The first flop in the sequence needs D tied to ground
FDPE #(
.INIT(1'b0)
) FDPE_INITIAL (
.D(d_1),
.Q(q[1]),
.C(clk),
.CE(clk_enable),
.PRE(async_reset)
);
// All the rest of these flops have the same wiring pattern. If you wanted to
// tap off the second to last flop, you would alter the loop to stop at N-1.
genvar i;
for (i=2; i<=N; i=i+1) begin: generate_flops
FDPE #(
.INIT(1'b0)
) u_FDPE (
.D(q[i-1]),
.Q(q[i]),
.C(clk),
.CE(clk_enable),
.PRE(async_reset)
);
end
endmodule // porf_gen
|
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