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/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module runs through the 16x2 Character LCD initialization *
* commands for the DE2 Board. *
* *
******************************************************************************/
module altera_up_character_lcd_initialization (
// Inputs
clk,
reset,
initialize_LCD_display,
command_was_sent,
// Bidirectionals
// Outputs
done_initialization,
send_command,
the_command
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b1;
// Timing info for waiting for power up
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter W15 = 20; // Counter width required for 15ms
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for waiting between commands
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_5MS = 250000;
parameter W5 = 18; // Counter width required for 5ms
parameter COUNTER_INCREMENT_FOR_5MS = 18'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input initialize_LCD_display;
input command_was_sent;
// Bidirectionals
// Outputs
output done_initialization;
output send_command;
output reg [ 8: 0] the_command;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam LCD_INIT_STATE_0_WAIT_POWER_UP = 2'h0,
LCD_INIT_STATE_1_SEND_COMMAND = 2'h1,
LCD_INIT_STATE_2_CHECK_DONE = 2'h2,
LCD_INIT_STATE_3_DONE = 2'h3;
localparam AUTO_INIT_LENGTH = 4'h8;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [ 8: 0] command_rom;
// Internal Registers
reg [W15: 1] waiting_power_up;
reg [W5: 1] waiting_to_send;
reg [ 3: 0] command_counter;
// State Machine Registers
reg [ 1: 0] ns_lcd_initialize;
reg [ 1: 0] s_lcd_initialize;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_initialize <= LCD_INIT_STATE_0_WAIT_POWER_UP;
else
s_lcd_initialize <= ns_lcd_initialize;
end
always @(*)
begin
// Defaults
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
case (s_lcd_initialize)
LCD_INIT_STATE_0_WAIT_POWER_UP:
begin
if ((waiting_power_up == CLOCK_CYCLES_FOR_15MS) &
(initialize_LCD_display))
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
LCD_INIT_STATE_1_SEND_COMMAND:
begin
if (command_was_sent)
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
end
LCD_INIT_STATE_2_CHECK_DONE:
begin
if (command_counter == AUTO_INIT_LENGTH)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else if (waiting_to_send == CLOCK_CYCLES_FOR_5MS)
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
end
LCD_INIT_STATE_3_DONE:
begin
if (initialize_LCD_display)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
default:
begin
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
the_command <= 9'h000;
else
the_command <= command_rom;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
waiting_power_up <= {W15{1'b0}};
else if ((s_lcd_initialize == LCD_INIT_STATE_0_WAIT_POWER_UP) &&
(waiting_power_up != CLOCK_CYCLES_FOR_15MS))
waiting_power_up <= waiting_power_up + COUNTER_INCREMENT_FOR_15MS;
end
always @(posedge clk)
begin
if (reset)
waiting_to_send <= {W5{1'b0}};
else if (s_lcd_initialize == LCD_INIT_STATE_2_CHECK_DONE)
begin
if (waiting_to_send != CLOCK_CYCLES_FOR_5MS)
waiting_to_send <= waiting_to_send + COUNTER_INCREMENT_FOR_5MS;
end
else
waiting_to_send <= {W5{1'b0}};
end
always @(posedge clk)
begin
if (reset)
command_counter <= 4'h0;
else if (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND)
begin
if (command_was_sent)
command_counter <= command_counter + 4'h1;
end
else if (s_lcd_initialize == LCD_INIT_STATE_3_DONE)
command_counter <= 4'h5;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign send_command = (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND);
assign done_initialization = (s_lcd_initialize == LCD_INIT_STATE_3_DONE);
// Internal Assignments
always @(*)
begin
case (command_counter)
0 : command_rom <= 9'h030;
1 : command_rom <= 9'h030;
2 : command_rom <= 9'h030;
3 : command_rom <= 9'h03C;
4 : command_rom <= 9'h008;
5 : command_rom <= 9'h001;
6 : command_rom <= 9'h006;
7 : command_rom <= {7'h03, CURSOR_ON, BLINKING_ON};
default : command_rom <= 9'h000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> sorted; vector<set<int> > v; set<int> solve(int lf, int rg) { if (lf == rg) { return v[lf]; } int md = (lf + rg) >> 1; set<int> x = solve(lf, md); set<int> y = solve(md + 1, rg); for (int val : y) { v[md + 1].insert(val); } for (int val : x) { v[md].insert(val); } if ((int)(x).size() < (int)(y).size()) { for (int val : x) { v[md + 1].insert(val); y.insert(val); } return y; } else { for (int val : y) { v[md].insert(val); x.insert(val); } return x; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; vector<pair<int, int> > a(n); for (int i = 0; i < n; ++i) { int x, y; cin >> x >> y; sorted.push_back(x); a[i] = {x, y}; } sort((sorted).begin(), (sorted).end()); sorted.resize(unique((sorted).begin(), (sorted).end()) - sorted.begin()); v.resize((int)(sorted).size()); for (int i = 0; i < n; ++i) { a[i].first = lower_bound((sorted).begin(), (sorted).end(), a[i].first) - sorted.begin(); v[a[i].first].insert(a[i].second); } solve(0, (int)(v).size() - 1); vector<pair<int, int> > ans; for (int i = 0; i < (int)(v).size(); ++i) { for (int y : v[i]) { ans.push_back({sorted[i], y}); } } cout << (int)(ans).size() << n ; for (int i = 0; i < (int)(ans).size(); ++i) { cout << ans[i].first << << ans[i].second << n ; } }
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream& operator<<(ostream& os, const pair<A, B>& x) { return os << ( << x.first << , << x.second << ) ; } vector<int> E[505][505]; long long dp[505][505], W[505][505]; vector<pair<int, int>> verts[505][505], hors[505][505]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); vector<int> C(k); for (int i = 0; i < k; ++i) { int r, c, d, t; scanf( %d%d%d%d%d , &r, &c, &d, &t, &C[i]); vector<bool> has(4); if (r + c >= t && (r + c - t) % 4 == 0) has[0] = true; if (r + c >= t && (r + c - t) % 4 == 1) has[1] = true; if (r + c + d >= t && (r + c + d - t) % 4 == 2) has[2] = true; if (r + c + d >= t && (r + c + d - t) % 4 == 3) has[3] = true; int tot = has[0] + has[1] + has[2] + has[3]; assert(tot <= 2); if (!tot) continue; if (has[0] && has[2]) verts[r][c].emplace_back(r + d, C[i]); else if (has[0] && has[3]) hors[r][c].emplace_back(c + d, C[i]); else if (has[1] && has[2]) hors[r + d][c - d].emplace_back(c, C[i]); if (has[0]) W[r][c] += C[i]; if (has[1]) W[r + d][c - d] += C[i]; if (has[2]) W[r + d][c] += C[i]; if (has[3]) W[r][c + d] += C[i]; } for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { if (!i && !j) continue; long long val = LLONG_MAX; long long cost = 0; for (int k = j; k >= 0; --k) { cost += W[i][k]; for (auto& x : hors[i][k]) { if (x.first <= j) cost -= x.second; } if (k < j) val = min(val, dp[i][k] + cost - W[i][k]); } cost = 0; for (int k = i; k >= 0; --k) { cost += W[k][j]; for (auto& x : verts[k][j]) { if (x.first <= i) cost -= x.second; } if (k < i) val = min(val, dp[k][j] + cost - W[k][j]); } dp[i][j] = val; } printf( %lld n , dp[n - 1][m - 1]); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000000000000ll; long long x[6], y[6]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> x[i] >> y[i]; if (n == 1) { cout << -1 << endl; return 0; } if (n == 2) { if (x[0] == x[1] || y[0] == y[1]) { cout << -1 << endl; return 0; } long long s = (abs(x[0] - x[1]) * abs(y[0] - y[1])); cout << s << endl; return 0; } long long X = 0, Y = 0; for (int i = 1; i < n; i++) { X = max(X, abs(x[0] - x[i])); Y = max(Y, abs(y[0] - y[i])); } cout << X * Y << endl; }
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#include <bits/stdc++.h> using namespace std; map<int, int> glosy; map<pair<int, int>, int> parki; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = (0); i < (n); i++) { int a, b; scanf( %d%d , &a, &b); if (a > b) swap(a, b); if (glosy.find(a) != glosy.end()) glosy[a]++; else glosy.insert(make_pair(a, 1)); if (glosy.find(b) != glosy.end()) glosy[b]++; else glosy.insert(make_pair(b, 1)); if (parki.find(make_pair(a, b)) != parki.end()) parki[make_pair(a, b)]++; else parki.insert(make_pair(make_pair(a, b), 1)); } if (m == 0) { cout << (n * 1LL * (n - 1LL)) / 2LL << endl; return 0; } long long int res = 0LL; vector<int> v; for (map<int, int>::iterator it = glosy.begin(); it != glosy.end(); it++) v.push_back(it->second); int jeszcze = n - v.size(); sort(v.begin(), v.end()); int k = v.size(); for (int i = (0); i < (k); i++) { vector<int>::iterator it2 = lower_bound(v.begin(), v.end(), m - v[i]); int ile = (v.end() - it2); if (v[i] + v[i] >= m) ile--; if (v[i] >= m) ile += 2 * jeszcze; res += ile * 1LL; } res = res / 2; for (map<pair<int, int>, int>::iterator it = parki.begin(); it != parki.end(); it++) { pair<int, int> para = it->first; int a = para.first; int b = para.second; int x = glosy[a] + glosy[b] - it->second; if (x < m && ((glosy[a] + glosy[b]) >= m)) res--; } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = int(5e3); const int MOD = int(1e9 + 7); const int oo = INT_MAX; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, d, h; while (cin >> n >> d >> h) { if (2 * h < d) { cout << -1 << n ; continue; } vector<pair<int, int> > edges; for (int i = 2; i <= h + 1; i++) { if (i > n) continue; edges.push_back({i - 1, i}); } for (int i = h + 2; i <= d + 1; i++) { if (i > n) continue; if (i == h + 2) edges.push_back({1, i}); else edges.push_back({i - 1, i}); } int id = d + 2, node = -1; if (h < d) node = 1; else if (h == d && h != 1) node = 2; if (node != -1) { while (id <= n) { edges.push_back({node, id}); id++; } } if (int(edges.size()) == n - 1) for (auto& e : edges) cout << e.first << << e.second << n ; else cout << -1 << n ; } return 0; }
|
/////////////////////////////
//LAB01 29/05 - Atividade 1//
/////////////////////////////
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR
);
// Ligacoes na placa
//{SW[17],SW[16],SW[15],SW[14],SW[13],SW[12],SW[11],SW[10],SW[9],SW[8],SW[7],SW[6],SW[5],SW[4],SW[3],SW[2],SW[1],SW[0]}
//{DA[2], DA[1], DA[0], AA[2], AA[1], AA[0], BA[2], BA[1], BA[0],MB, FS[3],FS[2],FS[1],FS[0],MD[2],RW, D_in, CONST_in}
parameter WORD_WIDTH = 16;
wire [WORD_WIDTH-1:0] B2HEXA_in, B2HEXB_in;
// Conversores Binario->7 Segmentos Hexadecimal
Decoder_Binary2HexSevenSegments B2HEXA(HEX0, B2HEXA_in);
Decoder_Binary2HexSevenSegments B2HEXB(HEX1, B2HEXB_in);
// Leds da Placa ligados ao barramento para monitoramento da atividade
assign LEDR[7:0] = {B2HEXA_in, B2HEXB_in};
// Instancia do Datapath
Datapath DP(
.FLAG_out(LEDR[17:13]),
.A_bus(B2HEXA_in),
.D_bus(B2HEXB_in),
.D_in({WORD_WIDTH{SW[1]}}),
.CNTRL_in(SW[17:2]),
.CONST_in({{(WORD_WIDTH-3){1'b0}},SW[1:0]}),
.CLK(KEY[3]),
);
defparam DP.WORD_WIDTH = WORD_WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef struct { int i; int j; } AXIS; AXIS D[] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; bool DFS(char maze[][505], AXIS S, int &k, int &n, int &m) { maze[S.i][S.j] = * ; for (int i = 0; i < 4; i++) { AXIS next; next.i = S.i + D[i].i; next.j = S.j + D[i].j; if (maze[next.i][next.j] == . && 0 <= next.i && next.i < n && 0 <= next.j && next.j < m && DFS(maze, next, k, n, m)) { maze[next.i][next.j] = X ; k--; } if (!k) return 0; } return 1; } int main() { int n, m, k; char maze[505][505]; AXIS start = {-1, -1}; cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> maze[i][j]; if (start.i < 0 && maze[i][j] == . ) { start.i = i; start.j = j; } } } DFS(maze, start, k, n, m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (maze[i][j] == * ) { cout << . ; } else { cout << maze[i][j]; } } cout << endl; } return 0; }
|
module cbus_tb;
`define ch1in_freq 0
`define ch2in_freq 1
`define ch3in_freq 2
`define ch4in_freq 3
`define ch1out_freq 4
`define ch2out_freq 5
`define ch3out_freq 6
`define ch4out_freq 7
`define rates 8
`define misc 9
task send_config_word;
input [7:0] addr;
input [31:0] data;
integer i;
begin
#10 serenable = 1;
for(i=7;i>=0;i=i-1)
begin
#10 serdata = addr[i];
#10 serclk = 0;
#10 serclk = 1;
#10 serclk = 0;
end
for(i=31;i>=0;i=i-1)
begin
#10 serdata = data[i];
#10 serclk = 0;
#10 serclk = 1;
#10 serclk = 0;
end
#10 serenable = 0;
// #10 serclk = 1;
// #10 serclk = 0;
end
endtask // send_config_word
initial $dumpfile("cbus_tb.vcd");
initial $dumpvars(0,cbus_tb);
initial reset = 1;
initial #500 reset = 0;
reg serclk, serdata, serenable, reset;
wire SDO;
control_bus control_bus
( .serial_clock(serclk),
.serial_data_in(serdata),
.enable(serenable),
.reset(reset),
.serial_data_out(SDO) );
initial
begin
#1000 send_config_word(8'd1,32'hDEAD_BEEF);
#1000 send_config_word(8'd3,32'hDDEE_FF01);
#1000 send_config_word(8'd19,32'hFFFF_FFFF);
#1000 send_config_word(8'd23,32'h1234_FEDC);
#1000 send_config_word(8'h80,32'h0);
#1000 send_config_word(8'h81,32'h0);
#1000 send_config_word(8'h82,32'h0);
#1000 reset = 1;
#1 $finish;
end
endmodule // cbus_tb
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:35:22 10/10/2013
// Design Name:
// Module Name: mod_fsm_bola
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm_bola(clk,start_bola, bussy_bola, perdio, bola_x, bola_y, speed, barra_y);
//Se definen las variables
input clk, start_bola;
input [4:0] speed;
output bussy_bola, perdio;
output [10:0] bola_x;
output [9:0] bola_y, barra_y;
reg comenzar;
reg [2:0] state, direccion_x, direccion_y;;
//Se definen los estados
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
parameter STATE_3 = 3;
initial
begin
comenzar <= 0;
perdio <= 0;
end
always@(posedge clk)
begin
case(state)
STATE_0:
begin
if (start_bola)
begin
comenzar <= 1;
state <= STATE_1;
end
end
STATE_1:
begin
bola_x <= bola_x + direccion_x*speed;
bola_y <= bola_y + direccion_y*speed;
state <= STATE_2;
end
STATE_2:
begin
if (bola_x >= 623)
begin
bola_x <= 623;
direccion_x <= direccion_x*-1;
end
if (bola_y >= 463)
begin
bola_y <= 463;
direccion_y <= direccion_y*-1;
end
if (bola_y < 0)
begin
bola_y <= 0;
direccion_y <= direccion_y*-1;
end
state <= STATE_3;
end
STATE_3:
begin
if (bola_x <= 23)//suponiendo que "barra_x + 16 = 32", es decir, que barra_x = 16
begin
if ((bola_y >= barra_y) && (bola_y <= barra_y +50))
begin
bola_x <= 32;//suponiendo que barra_x = 16
direccion_x <= direccion_x*-1;
end
end
else
begin
perdio <= 1;
end
end
endcase
end
//Se asignan los valores de salida
assign bussy_bola = ((state == STATE_0)||(state == STATE_1)||(state == STATE_2))&&(comenzar == 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_TB_V
`define SKY130_FD_SC_LS__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ls__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_TB_V
|
#include <bits/stdc++.h> using namespace std; bool valid(long long num, long long den) { if (den == 0) { return num == 0; } else { return (num % den) == 0; } } long long gcd(long long a, long long b) { if (b == 0) { return a; } else { return gcd(b, a % b); } } bool valid(long long a, long long b, long long c) { if (a == 0 && b == 0) { return c == 0; } if (a < 0) { a = -a; } if (b < 0) { b = -b; } return c % gcd(a, b) == 0; } int main() { long long ax, ay, bx, by, cx, cy; cin >> ax >> ay >> bx >> by >> cx >> cy; long long a_x = -ay, a_y = ax; long long c_x = -cy, c_y = cx; for (long long a = -1; a <= 1; ++a) { for (long long a_ = -1; a_ <= 1; ++a_) { if (abs(a) + abs(a_) == 1) { long long X = bx - a * ax - a_ * a_x; long long Y = by - a * ay - a_ * a_y; long long num1 = X * c_y - Y * c_x; long long den1 = cx * c_y - cy * c_x; long long num2 = X * cy - Y * cx; long long den2 = c_x * cy - c_y * cx; bool ok; if (den1 != 0 && den2 != 0) { ok = (num1 % den1) == 0 && (num2 % den2) == 0; } else { if (cx == 0 && c_x == 0) { ok = X == 0 && valid(cy, c_y, Y); } else if (cy == 0 && c_y == 0) { ok = Y == 0 && valid(cx, c_x, X); } else { if (cx == 0) { ok = (X % c_x) == 0 && (Y % c_y) == 0 && X / c_x == Y / c_y; } else if (c_x == 0) { ok = (X % cx) == 0 && (Y % cy) == 0 && X / cx == Y / cy; } else { ok = valid(cx, c_x, X) && X * cy == Y * cx; } } } if (ok) { cout << YES << endl; return 0; } } } } cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = 1000000000; const double H = sqrt(3.0) * 0.5; const double eps = 1e-6; int main() { double r; scanf( %lf , &r); int i; long long ans = 0; for (i = 0; i <= r; i++) { double x = 1.5 * i + 1.0; if (x > r) break; double y = sqrt(r * r - x * x); int k; if (i % 2) k = (floor(y / H + eps) + 1) / 2; else k = floor(y / H + eps) / 2 + 1; x = 1.5 * i + 0.5; y = sqrt(r * r - x * x); if (i % 2) k = 2 * min(k, (int)floor(y / H + eps) / 2); else k = 2 * min(k, ((int)floor(y / H + eps) + 1) / 2) - 1; ans += i ? 2 * k : k; } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_SYMBOL_V
`define SKY130_FD_SC_LP__DLYGATE4S18_SYMBOL_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s18 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; long long fact[200001], invfact[200001]; int n50 = 0, n100 = 0, k = 0; struct node { int l[2], r[2], b; }; long long nways[51][51][51][51][2], shortest[51][51][51][51][2]; queue<node> q; long long pmod(long long base, long long p) { if (p == 0) return 1LL; long long ret = pmod(base, p / 2); ret = (ret * ret) % MOD; if (p % 2 == 1) ret = (ret * base) % MOD; return ret; } long long invEuler(long long x) { return pmod(x, MOD - 2); } long long nCr(long long n, long long r) { long long ret = 1; ret *= fact[n]; ret = (ret * invfact[r]) % MOD; ret = (ret * invfact[n - r]) % MOD; return ret; } void bfs() { memset(nways, 0, sizeof(nways)); memset(shortest, -1, sizeof(shortest)); nways[n50][n100][0][0][0] = 1; shortest[n50][n100][0][0][0] = 0; node temp; temp.l[0] = n50; temp.l[1] = n100; temp.r[0] = 0; temp.r[1] = 0; temp.b = 0; q.push(temp); while (!q.empty()) { temp = q.front(); q.pop(); int l0, l1, r0, r1, b; l0 = temp.l[0]; l1 = temp.l[1]; r0 = temp.r[0]; r1 = temp.r[1]; b = temp.b; if (b == 0) { for (int i = 0; i <= l0; ++i) { for (int j = 0; j <= l1; ++j) { if (50 * i + 100 * j > k || (!i && !j)) continue; int _l0 = l0 - i, _l1 = l1 - j, _r0 = r0 + i, _r1 = r1 + j, _b = !b; if (shortest[_l0][_l1][_r0][_r1][_b] == -1 || shortest[_l0][_l1][_r0][_r1][_b] > shortest[l0][l1][r0][r1][b] + 1) { shortest[_l0][_l1][_r0][_r1][_b] = 1 + shortest[l0][l1][r0][r1][b]; nways[_l0][_l1][_r0][_r1][_b] = (((nCr(l0, i) * nCr(l1, j)) % MOD) * nways[l0][l1][r0][r1][b]) % MOD; temp.l[0] = _l0; temp.l[1] = _l1; temp.r[0] = _r0; temp.r[1] = _r1; temp.b = _b; q.push(temp); } else if (shortest[_l0][_l1][_r0][_r1][_b] == shortest[l0][l1][r0][r1][b] + 1) nways[_l0][_l1][_r0][_r1][_b] = (nways[_l0][_l1][_r0][_r1][_b] + (((nCr(l0, i) * nCr(l1, j)) % MOD) * nways[l0][l1][r0][r1][b]) % MOD) % MOD; } } } else { for (int i = 0; i <= r0; ++i) { for (int j = 0; j <= r1; ++j) { if (50 * i + 100 * j > k || (!i && !j)) continue; int _l0 = l0 + i, _l1 = l1 + j, _r0 = r0 - i, _r1 = r1 - j, _b = !b; if (shortest[_l0][_l1][_r0][_r1][_b] == -1 || shortest[_l0][_l1][_r0][_r1][_b] > shortest[l0][l1][r0][r1][b] + 1) { shortest[_l0][_l1][_r0][_r1][_b] = 1 + shortest[l0][l1][r0][r1][b]; nways[_l0][_l1][_r0][_r1][_b] = (((nCr(r0, i) * nCr(r1, j)) % MOD) * nways[l0][l1][r0][r1][b]) % MOD; temp.l[0] = _l0; temp.l[1] = _l1; temp.r[0] = _r0; temp.r[1] = _r1; temp.b = _b; q.push(temp); } else if (shortest[_l0][_l1][_r0][_r1][_b] == shortest[l0][l1][r0][r1][b] + 1) nways[_l0][_l1][_r0][_r1][_b] = (nways[_l0][_l1][_r0][_r1][_b] + (((nCr(r0, i) * nCr(r1, j)) % MOD) * nways[l0][l1][r0][r1][b]) % MOD) % MOD; } } } } } int main() { int n, in; fact[0] = 1; fact[1] = 1; invfact[0] = invEuler(1); invfact[1] = invfact[0]; for (int i = 2; i < 200001; ++i) { fact[i] = (fact[i - 1] * i) % MOD; invfact[i] = invEuler(fact[i]); } scanf( %d %d , &n, &k); for (int i = 0; i < n; ++i) { scanf( %d , &in); if (in == 50) n50++; else n100++; } bfs(); cout << shortest[0][0][n50][n100][1] << endl << nways[0][0][n50][n100][1]; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005, inf = 2e9, n = 100000; struct seg { int fl[N << 2], m1[N << 2], m2[N << 2], sz[N << 2], tg[N << 2], c[N << 2]; long long tr[N << 2]; void build(int k, int l, int r) { fl[k] = 0; m1[k] = inf; m2[k] = 0; sz[k] = r - l + 1; tr[k] = 1ll * inf * sz[k]; tg[k] = 0; c[k] = r - l + 1; if (l == r) return; int mid = l + r >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); } void pu(int k) { if (m1[k << 1] == m1[k << 1 | 1]) { m1[k] = m1[k << 1]; m2[k] = max(m2[k << 1], m2[k << 1 | 1]); c[k] = c[k << 1] + c[k << 1 | 1]; } else if (m1[k << 1] > m1[k << 1 | 1]) { m1[k] = m1[k << 1]; m2[k] = max(m2[k << 1], m1[k << 1 | 1]); c[k] = c[k << 1]; } else { m1[k] = m1[k << 1 | 1]; m2[k] = max(m1[k << 1], m2[k << 1 | 1]); c[k] = c[k << 1 | 1]; } tr[k] = tr[k << 1] + tr[k << 1 | 1]; fl[k] = (fl[k << 1] & fl[k << 1 | 1]); } void pd(int k) { if (tg[k]) { if (m1[k << 1] == m1[k << 1 | 1]) { m1[k << 1] += tg[k]; tg[k << 1] += tg[k]; tr[k << 1] += 1ll * tg[k] * c[k << 1]; fl[k << 1] = 1; m1[k << 1 | 1] += tg[k]; tg[k << 1 | 1] += tg[k]; tr[k << 1 | 1] += 1ll * tg[k] * c[k << 1 | 1]; fl[k << 1 | 1] = 1; } else if (m1[k << 1] > m1[k << 1 | 1]) { m1[k << 1] += tg[k]; tg[k << 1] += tg[k]; tr[k << 1] += 1ll * tg[k] * c[k << 1]; fl[k << 1] = 1; } else { m1[k << 1 | 1] += tg[k]; tg[k << 1 | 1] += tg[k]; tr[k << 1 | 1] += 1ll * tg[k] * c[k << 1 | 1]; fl[k << 1 | 1] = 1; } tg[k] = 0; } } void upd(int k, int l, int r, int a, int b, int v) { if (v >= m1[k]) return; if (l == a && r == b) { if (v > m2[k]) { int d = v - m1[k]; m1[k] += d; tg[k] += d; tr[k] += 1ll * d * c[k]; fl[k] = 1; return; } pd(k); int mid = l + r >> 1; upd(k << 1, l, mid, a, mid, v); upd(k << 1 | 1, mid + 1, r, mid + 1, b, v); pu(k); } pd(k); int mid = l + r >> 1; if (b <= mid) upd(k << 1, l, mid, a, b, v); else if (a > mid) upd(k << 1 | 1, mid + 1, r, a, b, v); else upd(k << 1, l, mid, a, mid, v), upd(k << 1 | 1, mid + 1, r, mid + 1, b, v); pu(k); } } t1, t2; int q; long long ask(int k, int l, int r, int a, int b) { if (t1.tr[k] == 1ll * inf * t1.sz[k] || t2.tr[k] == 1ll * inf * t2.sz[k]) return 0; if (l == a && r == b) { if (t1.fl[k] && t2.fl[k]) return t1.tr[k] + t2.tr[k]; t1.pd(k), t2.pd(k); int mid = l + r >> 1; return ask(k << 1, l, mid, a, mid) + ask(k << 1 | 1, mid + 1, r, mid + 1, b); } t1.pd(k), t2.pd(k); int mid = l + r >> 1; if (b <= mid) return ask(k << 1, l, mid, a, b); else if (a > mid) return ask(k << 1 | 1, mid + 1, r, a, b); else return ask(k << 1, l, mid, a, mid) + ask(k << 1 | 1, mid + 1, r, mid + 1, b); } int main() { t1.build(1, 1, n); t2.build(1, 1, n); scanf( %d , &q); while (q--) { int t, l, r, v; scanf( %d%d%d , &t, &l, &r); r--; if (t == 1) { scanf( %d , &v); if (v > 0) t1.upd(1, 1, n, l, r, v); else t2.upd(1, 1, n, l, r, -v); } else printf( %lld n , ask(1, 1, n, l, r)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = (long long)(1e6) + 322; const long long MAXN = (long long)(1e7) + 100; const long long inf = (long long)(3e18) + 322; const long long mod = (long long)(1e9) + 7; const double eps = 1e-6; inline void upd(long long &mn, long long x, long long y, long long z) { mn = min(mn, (x - y) * (x - y) + (y - z) * (y - z) + (z - x) * (z - x)); } void solve() { long long mn = inf; long long n1, n2, n3; vector<long long> v[4]; cin >> n1 >> n2 >> n3; for (long long i = 1; i <= n1; ++i) { long long x; cin >> x; v[0].push_back(x); } sort((v[0]).begin(), (v[0]).end()); for (long long i = 1; i <= n2; ++i) { long long x; cin >> x; v[1].push_back(x); } sort((v[1]).begin(), (v[1]).end()); for (long long i = 1; i <= n3; ++i) { long long x; cin >> x; v[2].push_back(x); } sort((v[2]).begin(), (v[2]).end()); vector<long long> ids; for (long long i = 0; i < 3; ++i) { ids.push_back(i); } do { for (long long i = 0; i < (long long)(v[ids[0]].size()); ++i) { long long x = v[ids[0]][i]; auto z = lower_bound((v[ids[2]]).begin(), (v[ids[2]]).end(), x); if (z == v[ids[2]].end()) continue; auto y = lower_bound((v[ids[1]]).begin(), (v[ids[1]]).end(), (x + *z) / 2); if (y != v[ids[1]].end()) upd(mn, x, *y, *z); if (y != v[ids[1]].begin()) { auto y2 = --lower_bound((v[ids[1]]).begin(), (v[ids[1]]).end(), (x + *z) / 2); upd(mn, x, *y2, *z); } } } while (next_permutation((ids).begin(), (ids).end())); cout << mn << n ; } signed main() { ios_base ::sync_with_stdio(false); cin.tie(0); long long test; cin >> test; for (long long tt = 1; tt <= test; ++tt) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; string s[3003], t[3003]; long long hhs[3003][3003], hht[3003][3003], pp[3003], hhts[3003], hhtt[3003]; pair<int, int> cseg[3003]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); pp[0] = 1; for (int i = 1; i < 3003; ++i) pp[i] = pp[i - 1] * 47017 % mod; int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> s[i]; for (int i = 1; i <= n; ++i) cin >> t[i]; if (0) { for (int i = 1; i <= n; ++i) cout << s[i] << endl << t[i] << endl << endl; } string ts, tt; for (int i = 1; i <= n; ++i) { int L = 1e9, R = 0; for (int j = 0; j < int(s[i].size()); ++j) { if (s[i][j] != t[i][j]) L = min(L, j), R = max(R, j); } cseg[i] = {L, R}; if (L < 1e9) { string cs = s[i].substr(L, R - L + 1); string ct = t[i].substr(L, R - L + 1); if (ts == ) ts = cs, tt = ct; else { if (ts != cs || tt != ct) exit((cout << NO << endl, 0)); else ; } } } while (1) { bool lexp = 1; char lsamp = 0; char tsamp = 0; for (int i = 1; i <= n; ++i) { if (cseg[i].first == 1e9) continue; if (cseg[i].first == 0) { if (0) { cout << l can not expand at i= << i << endl; } lexp = 0; break; } if (lsamp) { if (s[i][cseg[i].first - 1] != lsamp || t[i][cseg[i].first - 1] != tsamp) { lexp = 0; if (0) { cout << l can not expand at i= << i << endl; } break; } else ; } else { lsamp = s[i][cseg[i].first - 1]; tsamp = t[i][cseg[i].first - 1]; } } if (!lexp) break; ts = string(1, lsamp) + ts; tt = string(1, tsamp) + tt; for (int i = 1; i <= n; ++i) { if (cseg[i].first == 1e9) continue; --cseg[i].first; } } while (1) { bool rexp = 1; char samp = 0; char tamp = 0; for (int i = 1; i <= n; ++i) { if (cseg[i].first == 1e9) continue; if (cseg[i].second == int(s[i].size()) - 1) { rexp = 0; break; } if (samp) { if (s[i][cseg[i].second + 1] != samp || t[i][cseg[i].second + 1] != tamp) { rexp = 0; break; } else ; } else { samp = s[i][cseg[i].second + 1]; tamp = t[i][cseg[i].second + 1]; } } if (!rexp) break; ts += samp; tt += samp; for (int i = 1; i <= n; ++i) { if (cseg[i].first == 1e9) continue; ++cseg[i].second; } } for (int i = 1; i <= n; ++i) { for (int j = 0; j < int(s[i].size()); ++j) { if (j) hhs[i][j] = (hhs[i][j - 1] + s[i][j] * pp[j]) % mod; else hhs[i][j] = s[i][j]; if (j) hht[i][j] = (hht[i][j - 1] + t[i][j] * pp[j]) % mod; else hht[i][j] = t[i][j]; } } for (int j = 0; j < int(ts.size()); ++j) { if (j) hhts[j] = (hhts[j - 1] + ts[j] * pp[j]) % mod; else hhts[j] = ts[j]; if (j) hhtt[j] = (hhtt[j - 1] + tt[j] * pp[j]) % mod; else hhtt[j] = tt[j]; } for (int i = 1; i <= n; ++i) { for (int j = 0; j + int(ts.size()) - 1 < int(s[i].size()); ++j) { if (((hhs[i][j + int(ts.size()) - 1] - ((j) ? hhs[i][(j)-1] : 0ll) + mod) * pp[3001 - (j + int(ts.size()) - 1)] % mod) == ((hhts[int(ts.size()) - 1] - ((0) ? hhts[(0) - 1] : 0ll) + mod) * pp[3001 - (int(ts.size()) - 1)] % mod)) { if (cseg[i].first != j) { cout << NO << endl; exit(0); } else break; } } } cout << YES << endl << ts << endl << tt << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m, Magic, md, pd; int a[99], b[99], cnt[99], row[99], col[99]; int t[99][99]; void giveans() { printf( %d n , Magic); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) printf( %d%c , t[i][j], n [j + 1 == n]); exit(0); } void dfs2(int, int); void dfs(int x, int y) { if (x == n) { if (row[n - 1] == Magic && md == Magic && pd == Magic) giveans(); } else if (x == 2 && y == 0) dfs(x, y + 1); else if (x == 2 && y == 3) dfs(x + 1, 0); else if (x == n - 1) { int tmp, tmp1, tmp2; if (y == 0) tmp = lower_bound(b, b + m, Magic - pd) - b; else tmp = lower_bound(b, b + m, Magic - col[y]) - b; if ((y == 0 && b[tmp] != Magic - pd) || (y != 0 && b[tmp] != Magic - col[y])) return; if (!cnt[tmp]) return; cnt[tmp]--; t[x][y] = b[tmp]; if (y == n - 1) md += b[tmp]; if (!y) pd += b[tmp]; row[x] += b[tmp]; col[y] += b[tmp]; bool ok = 1, need = 0; if (y == 0 && ok) { tmp1 = lower_bound(b, b + m, Magic - col[0]) - b; if (b[tmp1] != Magic - col[0] || !cnt[tmp1]) ok = 0; else { cnt[tmp1]--; col[0] += b[tmp1]; row[2] += b[tmp1]; t[2][0] = b[tmp1]; tmp2 = lower_bound(b, b + m, Magic - row[2]) - b; if (b[tmp2] != Magic - row[2] || !cnt[tmp2]) { ok = 0; col[0] -= b[tmp1]; row[2] -= b[tmp1]; cnt[tmp1]++; } else { cnt[tmp2]--; t[2][3] = b[tmp2]; col[3] += b[tmp2]; row[2] += b[tmp2]; need = 1; } } } if (ok) { if (y == n - 1) dfs(x + 1, 0); else dfs(x, y + 1); } if (need) { cnt[tmp1]++; col[0] -= b[tmp1]; row[2] -= b[tmp1]; cnt[tmp2]++; col[3] -= b[tmp2]; row[2] -= b[tmp2]; } if (!y) pd -= b[tmp]; if (y == n - 1) md -= b[tmp]; col[y] -= b[tmp]; row[x] -= b[tmp]; cnt[tmp]++; } else if (y == n - 1) { int tmp = lower_bound(b, b + m, Magic - row[x]) - b; if (b[tmp] != Magic - row[x]) return; if (!cnt[tmp]) return; cnt[tmp]--; t[x][y] = b[tmp]; if (!x) pd += b[tmp]; col[y] += b[tmp]; row[x] += b[tmp]; dfs(x + 1, 0); col[y] -= b[tmp]; row[x] -= b[tmp]; if (!x) pd -= b[tmp]; cnt[tmp]++; } else { for (int i = 0; i < m; i++) if (cnt[i]) { cnt[i]--; t[x][y] = b[i]; row[x] += b[i]; col[y] += b[i]; if (x == y) md += b[i]; if (x + y == n - 1) pd += b[i]; dfs(x, y + 1); if (x + y == n - 1) pd -= b[i]; if (x == y) md -= b[i]; col[y] -= b[i]; row[x] -= b[i]; cnt[i]++; } } } int main() { srand(13451); scanf( %d , &n); srand(rand() * 10 + rand() + n); for (int i = 0; i < n * n; i++) scanf( %d , a + i), Magic += a[i], b[i] = a[i]; if (n == 1) { printf( %d n%d n , a[0], a[0]); return 0; } sort(b, b + n * n); m = unique(b, b + n * n) - b; b[m] = 1000000000; for (int i = 0; i < n * n; i++) cnt[lower_bound(b, b + m, a[i]) - b]++; Magic /= n; if (n < 4) dfs2(0, 0); int p[200]; for (int i = 0; i < m; i++) p[i] = i; random_shuffle(p, p + m); for (int i = 0; i < m; i++) { cnt[i]--; t[0][0] = b[i]; row[0] += b[i]; col[0] += b[i]; md += b[i]; dfs(0, 1); row[0] -= b[i]; col[0] -= b[i]; md -= b[i]; cnt[i]++; } return 0; } void dfs2(int x, int y) { if (x == n) { if (row[n - 1] == Magic && md == Magic && pd == Magic) giveans(); } else if (x == n - 1) { int tmp = lower_bound(b, b + m, Magic - col[y]) - b; if (b[tmp] != Magic - col[y]) return; if (!cnt[tmp]) return; cnt[tmp]--; t[x][y] = b[tmp]; if (y == n - 1) md += b[tmp]; if (!y) pd += b[tmp]; row[x] += b[tmp]; if (pd == Magic) { if (y == n - 1) dfs2(x + 1, 0); else dfs2(x, y + 1); } if (!y) pd -= b[tmp]; if (y == n - 1) md -= b[tmp]; row[x] -= b[tmp]; cnt[tmp]++; } else if (y == n - 1) { int tmp = lower_bound(b, b + m, Magic - row[x]) - b; if (b[tmp] != Magic - row[x]) return; if (!cnt[tmp]) return; cnt[tmp]--; t[x][y] = b[tmp]; if (!x) pd += b[tmp]; col[y] += b[tmp]; dfs2(x + 1, 0); col[y] -= b[tmp]; if (!x) pd -= b[tmp]; cnt[tmp]++; } else { for (int i = 0; i < m; i++) if (cnt[i]) { cnt[i]--; t[x][y] = b[i]; row[x] += b[i]; col[y] += b[i]; if (x == y) md += b[i]; if (x + y == n - 1) pd += b[i]; dfs2(x, y + 1); if (x + y == n - 1) pd -= b[i]; if (x == y) md -= b[i]; col[y] -= b[i]; row[x] -= b[i]; cnt[i]++; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
|
//wb_artemis_ddr3.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_artemis_ddr3
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x06
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x03
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/03/11
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:0x8000000
*/
`timescale 1 ns/1 ps
module wb_artemis_ddr3 (
input clk,
input rst,
//DDR3 Control Signals
output ddr3_cmd_clk,
output ddr3_cmd_en,
output [2:0] ddr3_cmd_instr,
output [5:0] ddr3_cmd_bl,
output [29:0] ddr3_cmd_byte_addr,
input ddr3_cmd_empty,
input ddr3_cmd_full,
output ddr3_wr_clk,
output ddr3_wr_en,
output [3:0] ddr3_wr_mask,
output [31:0] ddr3_wr_data,
input ddr3_wr_full,
input ddr3_wr_empty,
input [6:0] ddr3_wr_count,
input ddr3_wr_underrun,
input ddr3_wr_error,
output ddr3_rd_clk,
output ddr3_rd_en,
input [31:0] ddr3_rd_data,
input ddr3_rd_full,
input ddr3_rd_empty,
input [6:0] ddr3_rd_count,
input ddr3_rd_overflow,
input ddr3_rd_error,
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
//Registers/Wires
reg write_en;
reg read_en;
wire [27:0] ddr3_cmd_word_addr;
reg if_write_strobe;
wire [1:0] if_write_ready;
reg [1:0] if_write_activate;
wire [23:0] if_write_fifo_size;
wire if_starved;
reg of_read_strobe;
wire of_read_ready;
reg of_read_activate;
wire [23:0] of_read_size;
wire [31:0] of_read_data;
reg [23:0] write_count;
reg [23:0] read_count;
//Submodules
ddr3_controller dc(
.clk (clk ),
.rst (rst ),
.write_address (i_wbs_adr[27:0] ),
.write_en (write_en ),
.read_address (i_wbs_adr[27:0] ),
.read_en (read_en ),
.if_write_strobe (if_write_strobe ),
.if_write_data (i_wbs_dat ),
//.if_write_data (32'h01234567 ),
.if_write_ready (if_write_ready ),
.if_write_activate (if_write_activate ),
.if_write_fifo_size (if_write_fifo_size ),
.if_starved (if_starved ),
.of_read_strobe (of_read_strobe ),
.of_read_ready (of_read_ready ),
.of_read_activate (of_read_activate ),
.of_read_size (of_read_size ),
.of_read_data (of_read_data ),
.cmd_en (ddr3_cmd_en ),
.cmd_instr (ddr3_cmd_instr ),
.cmd_bl (ddr3_cmd_bl ),
.cmd_word_addr (ddr3_cmd_word_addr ),
.cmd_empty (ddr3_cmd_empty ),
.cmd_full (ddr3_cmd_full ),
.wr_en (ddr3_wr_en ),
.wr_mask (ddr3_wr_mask ),
.wr_data (ddr3_wr_data ),
.wr_full (ddr3_wr_full ),
.wr_empty (ddr3_wr_empty ),
.wr_count (ddr3_wr_count ),
.wr_underrun (ddr3_wr_underrun ),
.wr_error (ddr3_wr_error ),
.rd_en (ddr3_rd_en ),
.rd_data (ddr3_rd_data ),
.rd_full (ddr3_rd_full ),
.rd_empty (ddr3_rd_empty ),
.rd_count (ddr3_rd_count ),
.rd_overflow (ddr3_rd_overflow ),
.rd_error (ddr3_rd_error )
);
//Asynchronous Logic
assign ddr3_cmd_clk = clk;
assign ddr3_wr_clk = clk;
assign ddr3_rd_clk = clk;
assign ddr3_cmd_byte_addr = {ddr3_cmd_word_addr, 2'b0};
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
write_en <= 0;
read_en <= 0;
if_write_strobe <= 0;
if_write_activate <= 0;
of_read_strobe <= 0;
of_read_activate <= 0;
write_count <= 0;
read_count <= 0;
end
else begin
//Deasserts Strobes
if_write_strobe <= 0;
of_read_strobe <= 0;
//Get a Ping Pong FIFO Writer
if ((if_write_ready > 0) && (if_write_activate == 0)) begin
write_count <= 0;
if (if_write_ready[0]) begin
if_write_activate[0] <= 1;
end
else begin
if_write_activate[1] <= 1;
end
end
//Get the Ping Pong FIFO Reader
if (of_read_ready && !of_read_activate) begin
read_count <= 0;
of_read_activate <= 1;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
//A transaction has starting
if (i_wbs_cyc) begin
if (i_wbs_we) begin
write_en <= 1;
end
else begin
read_en <= 1;
end
end
else begin
write_en <= 0;
read_en <= 0;
//A transaction has ended
//Close any FIFO that is open
if_write_activate <= 0;
of_read_activate <= 0;
end
if ((if_write_activate > 0) && (write_count > 0)&& (if_write_ready > 0)) begin
//Other side is idle, give it something to do
if_write_activate <= 0;
end
//Strobe
else if (i_wbs_stb && i_wbs_cyc && !o_wbs_ack) begin
//master is requesting something
if (write_en) begin
//write request
if (if_write_activate > 0) begin
if (write_count < if_write_fifo_size) begin
if_write_strobe <= 1;
o_wbs_ack <= 1;
write_count <= write_count + 24'h1;
end
else begin
if_write_activate <= 0;
end
end
end
else begin
//read request
if (of_read_activate) begin
if (read_count < of_read_size) begin
read_count <= read_count + 1;
o_wbs_dat <= of_read_data;
o_wbs_ack <= 1;
of_read_strobe <= 1;
end
else begin
of_read_activate <= 0;
end
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int& n) { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + ch - 0 , ch = getchar(); n = x * f; } int outputarray[20]; inline void write(int k) { int num = 0; if (k < 0) putchar( - ), k = -k; do { outputarray[++num] = k % 10, k /= 10; } while (k); while (num) putchar(outputarray[num--] + 0 ); puts( ); } const int N = 50; int n, m, sg[N][N][N][N][2]; char s[N][N]; int dfs(int x0, int x2, int y0, int y2, int type) { if (sg[x0][x2][y0][y2][type] >= 0) return sg[x0][x2][y0][y2][type]; int a[N * N]; memset(a, 0, sizeof(a)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (((i + j) & 1) == type) { int x = i + j, y = i - j + m; if (x >= x0 && x < x2 && y >= y0 && y < y2) { int tmp = 0; if (s[i][j] == L ) tmp = dfs(x0, x, y0, y2, type) ^ dfs(x + 1, x2, y0, y2, type); if (s[i][j] == R ) tmp = dfs(x0, x2, y0, y, type) ^ dfs(x0, x2, y + 1, y2, type); if (s[i][j] == X ) tmp = dfs(x0, x, y0, y, type) ^ dfs(x0, x, y + 1, y2, type) ^ dfs(x + 1, x2, y0, y, type) ^ dfs(x + 1, x2, y + 1, y2, type); a[tmp] = 1; } } while (a[++sg[x0][x2][y0][y2][type]]) ; return sg[x0][x2][y0][y2][type]; } int main() { memset(sg, -1, sizeof(sg)); read(n), read(m); for (int i = 0; i < n; i++) scanf( %s , s[i]); if (dfs(0, n + m, 0, n + m, 0) ^ dfs(0, n + m, 0, n + m, 1)) puts( WIN ); else puts( LOSE ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long modPow(long long a, long long b); long long modInv(long long a); void solve() { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long dp[n + 1][n + 1]; memset(dp, 0, sizeof(dp)); long long ans = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < i - 1; j++) { dp[a[j]][a[i - 1]]++; } for (long long j = i + 1; j < n; j++) { ans += dp[a[i]][a[j]]; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long test = 1; cin >> test; while (test--) solve(); } long long modPow(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 0) { long long x = a * a; x %= 1000000007; return modPow(x, b / 2); } return (a * modPow(a, b - 1)) % 1000000007; } long long modInv(long long a) { return modPow(a, 1000000007 - 2); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:50:01 07/20/2013
// Design Name:
// Module Name: sha256
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module karray(
input wire [5:0] idx, output reg [31:0] k
);
always @(*) begin
case (idx)
6'b000000: k = 32'h428a2f98;
6'b000001: k = 32'h71374491;
6'b000010: k = 32'hb5c0fbcf;
6'b000011: k = 32'he9b5dba5;
6'b000100: k = 32'h3956c25b;
6'b000101: k = 32'h59f111f1;
6'b000110: k = 32'h923f82a4;
6'b000111: k = 32'hab1c5ed5;
6'b001000: k = 32'hd807aa98;
6'b001001: k = 32'h12835b01;
6'b001010: k = 32'h243185be;
6'b001011: k = 32'h550c7dc3;
6'b001100: k = 32'h72be5d74;
6'b001101: k = 32'h80deb1fe;
6'b001110: k = 32'h9bdc06a7;
6'b001111: k = 32'hc19bf174;
6'b010000: k = 32'he49b69c1;
6'b010001: k = 32'hefbe4786;
6'b010010: k = 32'h0fc19dc6;
6'b010011: k = 32'h240ca1cc;
6'b010100: k = 32'h2de92c6f;
6'b010101: k = 32'h4a7484aa;
6'b010110: k = 32'h5cb0a9dc;
6'b010111: k = 32'h76f988da;
6'b011000: k = 32'h983e5152;
6'b011001: k = 32'ha831c66d;
6'b011010: k = 32'hb00327c8;
6'b011011: k = 32'hbf597fc7;
6'b011100: k = 32'hc6e00bf3;
6'b011101: k = 32'hd5a79147;
6'b011110: k = 32'h06ca6351;
6'b011111: k = 32'h14292967;
6'b100000: k = 32'h27b70a85;
6'b100001: k = 32'h2e1b2138;
6'b100010: k = 32'h4d2c6dfc;
6'b100011: k = 32'h53380d13;
6'b100100: k = 32'h650a7354;
6'b100101: k = 32'h766a0abb;
6'b100110: k = 32'h81c2c92e;
6'b100111: k = 32'h92722c85;
6'b101000: k = 32'ha2bfe8a1;
6'b101001: k = 32'ha81a664b;
6'b101010: k = 32'hc24b8b70;
6'b101011: k = 32'hc76c51a3;
6'b101100: k = 32'hd192e819;
6'b101101: k = 32'hd6990624;
6'b101110: k = 32'hf40e3585;
6'b101111: k = 32'h106aa070;
6'b110000: k = 32'h19a4c116;
6'b110001: k = 32'h1e376c08;
6'b110010: k = 32'h2748774c;
6'b110011: k = 32'h34b0bcb5;
6'b110100: k = 32'h391c0cb3;
6'b110101: k = 32'h4ed8aa4a;
6'b110110: k = 32'h5b9cca4f;
6'b110111: k = 32'h682e6ff3;
6'b111000: k = 32'h748f82ee;
6'b111001: k = 32'h78a5636f;
6'b111010: k = 32'h84c87814;
6'b111011: k = 32'h8cc70208;
6'b111100: k = 32'h90befffa;
6'b111101: k = 32'ha4506ceb;
6'b111110: k = 32'hbef9a3f7;
6'b111111: k = 32'hc67178f2;
endcase
end
endmodule
module sha256_chunk(
input wire clk, input wire [511:0] data, input wire [255:0] V_in, output wire [255:0] hash
);
/*
design choices:
select parts of data via shifter or by muxing
use hash output as temp storage
*/
function [31:0] rotate (input [31:0] data, input [4:0] shift);
// from http://stackoverflow.com/questions//defining-a-rightrotate-function-with-non-fixed-rotation-length/#
reg [63:0] tmp;
begin
tmp = {data, data} >> shift;
rotate = tmp[31:0];
end
endfunction
function [31:0] flipbytes (input [31:0] data);
flipbytes = {data[7:0], data[15:8], data[23:16], data[31:24]};
endfunction
// State:
reg [255:0] V;
reg [31:0] R[7:0]; // R[0] through R[7] represent a through h
reg [31:0] w[15:0];
// round computation
// nw and nR are the computation of w and R for the next round.
reg [31:0] nw, nR[7:0], s0, s1, S1, ch, temp1, S0, maj, temp2;
wire [31:0] k;
karray karray(.idx(roundnum), .k(k));
// On round i, we calculate nw=w[i+16].
assign hash[31:0] = V[31:0] + nR[0];
assign hash[63:32] = V[63:32] + nR[1];
assign hash[95:64] = V[95:64] + nR[2];
assign hash[127:96] = V[127:96] + nR[3];
assign hash[159:128] = V[159:128] + nR[4];
assign hash[191:160] = V[191:160] + nR[5];
assign hash[223:192] = V[223:192] + nR[6];
assign hash[255:224] = V[255:224] + nR[7];
reg [5:0] roundnum = 0;
always @(*) begin
s0 = rotate(w[1], 7) ^ rotate(w[1], 18) ^ (w[1] >> 3);
s1 = rotate(w[14], 17) ^ rotate(w[14], 19) ^ (w[14] >> 10);
nw = w[0] + s0 + w[9] + s1;
S1 = rotate(R[4], 6) ^ rotate(R[4], 11) ^ rotate(R[4], 25);
ch = (R[4] & R[5]) ^ ((~R[4]) & R[6]);
temp1 = R[7] + S1 + ch + k + w[0];
S0 = rotate(R[0], 2) ^ rotate(R[0], 13) ^ rotate(R[0], 22);
maj = (R[0] & R[1]) ^ (R[0] & R[2]) ^ (R[1] & R[2]);
temp2 = S0 + maj;
nR[7] = R[6];
nR[6] = R[5];
nR[5] = R[4];
nR[4] = R[3] + temp1;
nR[3] = R[2];
nR[2] = R[1];
nR[1] = R[0];
nR[0] = temp1 + temp2;
end
always @(posedge clk) begin
if (roundnum == 6'b111111) begin
V <= V_in;
R[0] <= V_in[31:0];
R[1] <= V_in[63:32];
R[2] <= V_in[95:64];
R[3] <= V_in[127:96];
R[4] <= V_in[159:128];
R[5] <= V_in[191:160];
R[6] <= V_in[223:192];
R[7] <= V_in[255:224];
w[0] <= flipbytes(data[31:0]);
w[1] <= flipbytes(data[63:32]);
w[2] <= flipbytes(data[95:64]);
w[3] <= flipbytes(data[127:96]);
w[4] <= flipbytes(data[159:128]);
w[5] <= flipbytes(data[191:160]);
w[6] <= flipbytes(data[223:192]);
w[7] <= flipbytes(data[255:224]);
w[8] <= flipbytes(data[287:256]);
w[9] <= flipbytes(data[319:288]);
w[10] <= flipbytes(data[351:320]);
w[11] <= flipbytes(data[383:352]);
w[12] <= flipbytes(data[415:384]);
w[13] <= flipbytes(data[447:416]);
w[14] <= flipbytes(data[479:448]);
w[15] <= flipbytes(data[511:480]);
end else begin
R[0] <= nR[0];
R[1] <= nR[1];
R[2] <= nR[2];
R[3] <= nR[3];
R[4] <= nR[4];
R[5] <= nR[5];
R[6] <= nR[6];
R[7] <= nR[7];
w[0] <= w[1];
w[1] <= w[2];
w[2] <= w[3];
w[3] <= w[4];
w[4] <= w[5];
w[5] <= w[6];
w[6] <= w[7];
w[7] <= w[8];
w[8] <= w[9];
w[9] <= w[10];
w[10] <= w[11];
w[11] <= w[12];
w[12] <= w[13];
w[13] <= w[14];
w[14] <= w[15];
w[15] <= nw;
end
roundnum <= roundnum + 1'b1;
end
endmodule
|
/*
* Copyright (c) 2000 Philips Semiconductors
*
* This source code is free software; you can redistribute it
* Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 1ns / 10ps
`celldefine
module MULT_8x8_f (P, A, B);
parameter
NA = 8,
NB = 8,
NP = 16,
PX = 16'bx;
input [NA-1:0] A;
input [NB-1:0] B;
output [NP-1:0] P;
reg [NA-1:0] A_sign;
reg [NB-1:0] B_sign;
reg [NP-1:0] P_sign;
reg Sign;
wire [NA-1:0] AI;
wire [NB-1:0] BI;
// SDF constraint: set of buffers to allow the MIPDs annotation
buf a0 (AI[0], A[0]);
buf a1 (AI[1], A[1]);
buf a2 (AI[2], A[2]);
buf a3 (AI[3], A[3]);
buf a4 (AI[4], A[4]);
buf a5 (AI[5], A[5]);
buf a6 (AI[6], A[6]);
buf a7 (AI[7], A[7]);
buf b0 (BI[0], B[0]);
buf b1 (BI[1], B[1]);
buf b2 (BI[2], B[2]);
buf b3 (BI[3], B[3]);
buf b4 (BI[4], B[4]);
buf b5 (BI[5], B[5]);
buf b6 (BI[6], B[6]);
buf b7 (BI[7], B[7]);
reg change_in;
wire change_out;
initial change_in = 0;
buf #(0.01) bc (change_out, change_in);
wire [NP-1:0] PI;
// SDF constraint: P_sign cannot be used to drive directly buffers
assign PI = P_sign;
// SDF constraint: set of buffers to allow the output acceleration
buf p0 (P[0], PI[0]);
buf p1 (P[1], PI[1]);
buf p2 (P[2], PI[2]);
buf p3 (P[3], PI[3]);
buf p4 (P[4], PI[4]);
buf p5 (P[5], PI[5]);
buf p6 (P[6], PI[6]);
buf p7 (P[7], PI[7]);
buf p8 (P[8], PI[8]);
buf p9 (P[9], PI[9]);
buf p10 (P[10], PI[10]);
buf p11 (P[11], PI[11]);
buf p12 (P[12], PI[12]);
buf p13 (P[13], PI[13]);
buf p14 (P[14], PI[14]);
buf p15 (P[15], PI[15]);
specify
specparam
th = 0.940,
td = 4.930;
// Pin-to-pin delay
(A, B *> P) = (td, td, th, 0, th, 0);
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using LL = long long; using ULL = unsigned long long; using namespace std; long long n, m; vector<long long> a; vector<pair<long long, long long> > vec; signed main() { ios::sync_with_stdio(false), cin.tie(NULL); cin >> n; a.resize(n, 0); vec.resize(n, {0, 0}); for (long long i = (0); i < (n); i++) cin >> a[i]; for (long long i = (0); i < (n); i++) vec[i].first = a[i], vec[i].second = n - i; sort(vec.rbegin(), vec.rend()); cin >> m; for (long long i = (0); i < (m); i++) { long long k, pos; cin >> k >> pos; vector<pair<long long, long long> > tmp; tmp.resize(k, {0, 0}); for (long long i = (0); i < (k); i++) tmp[i].first = n - vec[i].second, tmp[i].second = vec[i].first; sort(tmp.begin(), tmp.end()); cout << tmp[pos - 1].second << n ; } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module wasca_rs232_0 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 10; // Baud counter width
parameter BAUD_TICK_COUNT = 1006;
parameter HALF_BAUD_TICK_COUNT = 503;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [ 7: 0] read_available;
wire read_data_valid;
wire [(DW-1):0] read_data;
wire parity_error;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DW-1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (chipselect)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
read_data_valid,
5'h00,
parity_error,
1'b0,
read_data[(DW - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset)
read_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset)
write_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (&(read_available[6:5]) | read_available[7]);
end
always @(posedge clk)
begin
if (reset)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset)
data_to_uart <= 'h0;
else
data_to_uart <= writedata[(DW - 1):0];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign parity_error = 1'b0;
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data_valid (read_data_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (data_to_uart),
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4_PP_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
module HammingDecoderTest;
reg [6:0] ReceivedHammingCode;
wire [3:0] DecodedWord;
wire [3:0] DecodedWord2;
HammingDecoder DUT1 (ReceivedHammingCode, DecodedWord);
NewHammingDecoder DUT2 (ReceivedHammingCode, DecodedWord2);
wire [2:0] syndrome = DUT1.syndrome;
initial begin
ReceivedHammingCode = 7'b0000000; #5; //0
ReceivedHammingCode = 7'b0001011; #5; //1
ReceivedHammingCode = 7'b0010101; #5; //2
ReceivedHammingCode = 7'b0011110; #5; //3
ReceivedHammingCode = 7'b0100110; #5; //4
ReceivedHammingCode = 7'b0101101; #5; //5
ReceivedHammingCode = 7'b0110011; #5; //6
ReceivedHammingCode = 7'b0111000; #5; //7
ReceivedHammingCode = 7'b1000111; #5; //8
ReceivedHammingCode = 7'b1001100; #5; //9
ReceivedHammingCode = 7'b1010010; #5; //10
ReceivedHammingCode = 7'b1011001; #5; //11
ReceivedHammingCode = 7'b1100001; #5; //12
ReceivedHammingCode = 7'b1101010; #7; //13
ReceivedHammingCode = 7'b1110100; #7; //14
ReceivedHammingCode = 7'b1111111; #10; //15
ReceivedHammingCode = 7'b1010100; #7; //14 bit 6 in error
$monitor ("Number 14 with bit 6 in error.");
ReceivedHammingCode = 7'b1001111; #7; //8 bit 3 in error
ReceivedHammingCode = 7'b0011111; #7; //3 bit 0 in error
ReceivedHammingCode = 7'b0111100; #7; //7 bit 2 in error
ReceivedHammingCode = 7'b0001101; #7; //5 bit 5 in error
ReceivedHammingCode = 7'b0100101; #7; //5 bit 3 in error
ReceivedHammingCode = 7'b0101111; #7; //5 bit 1 in error
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; set<int> s[300000]; int ans[300000]; bool vis[300000]; int nr[500000]; int main() { int n, m; scanf( %d %d , &n, &m); priority_queue<pair<int, int> > pq; for (int i = 0; i <= 2 * m; i++) nr[i] = -1; for (int i = 0; i < n; i++) { int k, x; scanf( %d , &k); while (k--) { scanf( %d , &x); nr[x + m] = i; s[i].insert(x); } pq.push(make_pair(-s[i].size(), i)); } while (!pq.empty()) { int k = pq.top().second; pq.pop(); if (vis[k]) continue; vis[k] = true; if (s[k].empty()) { puts( NO ); return 0; } int x = *s[k].begin(); if (x > 0) ans[x] = 1; if (nr[m - x] != -1) { s[nr[m - x]].erase(-x); pq.push(make_pair(-s[nr[m - x]].size(), nr[m - x])); } } puts( YES ); for (int i = 1; i <= m; i++) printf( %d , ans[i]); puts( ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_4_V
`define SKY130_FD_SC_HDLL__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_4_V
|
#include <bits/stdc++.h> using namespace std; struct point { int x, y; point(){}; point(int xx, int yy) { x = xx; y = yy; } point friend operator+(point a, point b) { return point(a.x + b.x, a.y + b.y); } point friend operator-(point a, point b) { return point(a.x - b.x, a.y - b.y); } long long friend operator*(point a, point b) { return (long long)a.x * b.y - (long long)a.y * b.x; } } a[5050], s[5050]; int n, tot; long long S; bool cmp(point a, point b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } void put(point a) { printf( %d %d n , a.x, a.y); } long long area(int i, int j, int k) { return abs((s[j] - s[i]) * (s[k] - s[i])); } int main() { scanf( %d%I64d , &n, &S); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].x, &a[i].y); sort(a + 1, a + 1 + n, cmp); for (int i = 1; i <= n; i++) { while (tot > 1 && (a[i] - s[tot - 1]) * (s[tot] - s[tot - 1]) <= 0) tot--; s[++tot] = a[i]; } int k = tot; for (int i = n - 1; i > 0; i--) { while (tot > k && (a[i] - s[tot - 1]) * (s[tot] - s[tot - 1]) <= 0) tot--; s[++tot] = a[i]; } tot--; S = 0; int ii, jj, kk; for (int i = 1; i < tot - 1; i++) { int tmp = i + 2; for (int j = i + 1; j <= tot; j++) { while (tmp < tot && area(i, j, tmp + 1) > area(i, j, tmp)) tmp++; if (area(i, j, tmp) > S) { S = area(i, j, tmp); ii = i; jj = j; kk = tmp; } } } put(s[ii] + s[jj] - s[kk]); put(s[jj] + s[kk] - s[ii]); put(s[kk] + s[ii] - s[jj]); return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const double PI = 4 * atan(1); const int INF = 0x3f3f3f3f; const ll LINF = 0x3f3f3f3f3f3f3f3f; const int MOD = 1e9 + 7; const int MAX_N = 2e6 + 10; int n; int a[MAX_N], b[MAX_N], p[MAX_N]; void solve() { for (int i = 1; i <= n; ++i) { p[b[i]] = i; } if (p[1]) { int i = 2; for (; p[i] == p[1] + i - 1; ++i) ; if (p[i - 1] == n) { int j; for (j = i; j <= n && p[j] <= j - i; ++j) ; if (j > n) { cout << n - i + 1 << n ; return; } } } int ans = 0; for (int i = 1; i <= n; ++i) ans = max(ans, p[i] - i + 1 + n); cout << ans << n ; } int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) cin >> b[i]; solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 220000; const long long MOD = 1e9 + 7; int n; int was[MAXN * 2]; vector<int> beds[MAXN * 2]; int go[MAXN * 2]; int tm1; long long dfs1(int v) { was[v] = 1; long long ans = 1; for (int u : beds[v]) ans = (ans + dfs1(u)) % MOD; return ans; } int dfs2(int v) { was[v] = tm1; if (was[go[v]] == tm1) { return 1; } if (was[go[v]]) return 0; return dfs2(go[v]); } int main() { scanf( %d , &n); for (int i = 0; i < 2 * n; ++i) go[i] = -1; for (int i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); --x, --y; go[x] = y; beds[y].push_back(x); } long long ans = 1; for (int i = 0; i < 2 * n; ++i) { if (go[i] == -1) ans = (ans * dfs1(i)) % MOD; else if (go[i] == i) { was[i] = 1; } } tm1 = 1; for (int i = 0; i < 2 * n; ++i) { if (was[i]) continue; ++tm1; if (dfs2(i)) ans = (ans * 2) % MOD; } cout << ans << n ; return 0; }
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#include <bits/stdc++.h> template <typename T> T gcd(T a, T b) { if (!b) return a; return gcd(b, a % b); } template <typename T> T lcm(T a, T b) { return a * b / gcd(a, b); } template <typename T> void chmin(T& a, T b) { a = (a > b) ? b : a; } template <typename T> void chmax(T& a, T b) { a = (a < b) ? b : a; } int in() { int x; scanf( %d , &x); return x; } using namespace std; const int MAXN = 502; int N, M; int P[MAXN][MAXN]; vector<int> G[MAXN], GA[MAXN]; vector<int> comp; bool vis[MAXN]; int color[MAXN]; void dfs(int x) { vis[x] = true; for (int i = 0; i < (int)GA[x].size(); i++) { int u = G[x][i]; if (!vis[u]) { dfs(u); } } } bool dfs_color(int node, int c) { if (color[node] != 0) { if (color[node] == c) { return true; } else { return false; } } color[node] = c; for (int i = 0; i < (int)GA[node].size(); i++) { if (!dfs_color(GA[node][i], -c)) { return false; } } return true; } int main(void) { cin >> N >> M; string S(N, b ); for (int i = 0; i < M; i++) { int A, B; cin >> A >> B; A -= 1; B -= 1; P[A][B] = 1; P[B][A] = 1; G[A].push_back(B); G[B].push_back(A); } bool valid = true; for (int i = 0; i < N; i++) { for (int j = i; j < N; j++) { if (i != j && !P[i][j]) { GA[i].push_back(j); GA[j].push_back(i); } } } for (int i = 0; i < N; i++) { if (!vis[i] && GA[i].size() > 0) { comp.push_back(i); } } for (int i = 0; i < (int)comp.size(); i++) { if (color[comp[i]] == 0 && !dfs_color(comp[i], 1)) { valid = false; } } for (int i = 0; i < N; i++) { if (color[i] == -1) { S[i] = a ; } if (color[i] == 1) { S[i] = c ; } } for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { if (i != j) { if (P[i][j] && abs(S[i] - S[j]) > 1) { valid = false; } if (!P[i][j] && abs(S[i] - S[j]) <= 1) { valid = false; } } } } if (valid) { cout << Yes n << S << n ; } else { cout << No n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename S> ostream &operator<<(ostream &os, const pair<T, S> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename C, typename T = decay<decltype(*begin(declval<C>()))>, typename enable_if<!is_same<C, string>::value>::type * = nullptr> ostream &operator<<(ostream &os, const C &c) { bool f = true; os << [ ; for (const auto &x : c) { if (!f) os << , ; f = false; os << x; } return os << ] ; } template <typename T> void debug(string s, T x) { cerr << s << = << x << n ; } template <typename T, typename... Args> void debug(string s, T x, Args... args) { cerr << s.substr(0, s.find( , )) << = << x << | ; debug(s.substr(s.find( , ) + 2), args...); } int a[200000]; bool isMountain[200000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; int ret = 0, cnt = 0; for (int i = 0; i < n; i++) isMountain[i] = (i > 0 && i < n - 1 && a[i] > a[i - 1] && a[i] > a[i + 1]); for (int i = 1; i < k - 1; i++) cnt += isMountain[i]; ret = cnt; int l = 0; for (int i = k; i < n; i++) { cnt -= isMountain[i - (k - 1)]; cnt += isMountain[i - 1]; if (cnt > ret) { ret = cnt; l = i - k + 1; } } cout << ret + 1 << << l + 1 << n ; } return 0; }
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module maquina_4_estados(clock_50mhz, clock_1hz, segmentos, anodo,estado);
input clock_50mhz; //entrada de oscilacion del cristal externo
output clock_1hz; //clock 1 segundo
output reg [6:0] segmentos = 7'b3F; //apagar segmentos
output reg anodo = 0; //encender display1
output reg [1:0] estado = 0; //estado inicial para conectar 2 leds, 00, 01, 10, 11, 00 y se repite
reg [25:0] cuenta_para_1hz = 0; //inicializacion de la variable que servira para generar la salida de 1hz
parameter [6:0] cero = 0; //falta definir constante
parameter [6:0] uno = 0; //falta definir parameter
parameter [6:0] dos = 0; // falta definir parameter
parameter [6:0] tres = 0; //falta definir parameter
always @(posedge clock_50mhz)
begin
cuenta_para_1hz = cuenta_para_1hz + 1;
if(cuenta_para_1hz == 25_000_000)
begin
clock_1hz = ~clock_1hz; //genera la señal de oscialcion, esta señal empezo en 0, valor inicial
cuenta_para_1hz = 0; // resetea el contador
end
always @(posedge clock_1hz)
begin
case(estado)
0: estado <= 1;
1: estado <= 2;
2: estado <= 3;
3: estado <= 4;
endcase
end
always @(estado)
begin
case(estado)
0: segmentos = cero;
1: segmentos = uno;
2: segmentos = dos;
3: segmentos = tres;
endcase
end
endmodule
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:55:15 05/29/2015
// Design Name:
// Module Name: UART_IP
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_IP(
// UART USB ports
input sys_clk, // 27 MHZ on SP605
output CTS,// I am ready to receive data (active low)
input RTS, // USB Clear to send (active low)
output TX, // Output to USB
input RX, // Input to USB
// FPGA
output [7:0] TxD_par,
output TxD_ready,
input [7:0] RxD_par,
input RxD_start
);
wire BaudTick;
wire Baud16Tick;
assign CTS = ~NCTS;
// Generate baud clock 115200
BaudGen baudgen(
.sys_clk(sys_clk),
.BaudTick(BaudTick)
);
Baud16Gen baud16gen(
.sys_clk(sys_clk),
.Baud16Tick(Baud16Tick)
);
// Transmit data to USB
UART_TX uart_tx(
.RxD_par(RxD_par), // 8 bit data Input from FPGA
.RxD_start(RxD_start), // start input from FPGA
.RTS(~RTS), // USB clear to send
.sys_clk(sys_clk),
.BaudTick(BaudTick),
.TxD_ser(TX)
);
// Receive data from USB
UART_RX uart_rx (
.RxD_ser(RX),
.CTS(NCTS), // I am clear to receive
.sys_clk(sys_clk),
.Baud16Tick(Baud16Tick),
.TxD_par(TxD_par), //8 bit Output data to fpga
.TxD_ready(TxD_ready) // Ready data to FPGA
);
endmodule
|
`include "DC_define.v"
`include "logfunc.h"
`include "scmemc.vh"
module DC_top_bank_tag
//#(parameter Width=36, Size =256, Forward=0, REQ_BITS=7)
//tag 10+counter 2+states 3 =15//29 bits virtual adress
(
input clk
,input reset
,input req_valid
,input write
,input ack_retry
,input [35:0] req_data
,input [14:0] req_tag
,input[4:0] index
,input[2:0] bank_sel
,input row_even_odd
,output ack_valid
,output req_retry_from_top
,output [35:0] ack_data_from_top
//****************************************,output [2:0] ack_req_to_L2 //3 bit ack req to L2
,output miss
,output hit
,output[2:0] way
,output [14:0] output_data_tag
,output tag_retry
,input coretodc_ld_valid
,output coretodc_ld_retry
,input [4:0] coretodc_ld_req
//---------------------------
// 7 bit store Req,atomic,checkpoint
,input coretodc_std_valid
,output coretodc_std_retry
,input [6:0] coretodc_std
//3 bit DC->L2 Req
,output l1tol2_req_valid
,input l1tol2_req_retry
,output [2:0] l1tol2_req
//5 bit L2 -> DC ACK
,input l2tol1_snack_valid
,input [4:0] l2tol1_snack
// 3 bit Displacement
,output l1tol2_disp_valid
,output [2:0] l1tol2_disp //command out displacement
);
logic [2:0] way_no, way_from_tag;
logic hit_tag, miss_tag,ack_valid;
logic write_musk_reset,req_retry_to_1_tagcheck,req_retry;
logic [35:0] ack_data;
logic [14:0] ack_data_to_1_tagcheck;
DC_1_tagcheck
#(.Width(15), .Size(256))
tagcheck0 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.write (write)//we=0 for read
,.ack_retry (ack_retry)
,.req_tag (req_tag)
,.index (index)
,.ack_valid (ack_valid)
,. req_retry_to_1_tagcheck (req_retry_to_1_tagcheck)
,.ack_data_to_1_tagcheck( ack_data_to_1_tagcheck)
,.miss( miss_tag)
,.hit(hit_tag)
,.way (way_from_tag)
,.coretodc_ld_valid (coretodc_ld_valid)
,.coretodc_ld_retry (coretodc_ld_retry)
,.coretodc_ld_req (coretodc_ld_req)
,.coretodc_std_valid (coretodc_std_valid)
,.coretodc_std_retry (coretodc_std_retry)
,.coretodc_std (coretodc_std)
,.l1tol2_req_valid(l1tol2_req_valid)
,.l1tol2_req_retry(l1tol2_req_retry)
,.l1tol2_req(l1tol2_req)
,.l2tol1_snack_valid (l2tol1_snack_valid)
,.l2tol1_snack (l2tol1_snack)
,.l1tol2_disp_valid (l1tol2_disp_valid)
,.l1tol2_disp (l1tol2_disp)
);
DC_8_databanks #(.Width(36),.Size(512))
databanks_8
(
.clk(clk)
,.reset(reset)
,.req_valid(req_valid)
,.write(write)
,.bank_sel(bank_sel)
,.ack_retry(ack_retry)
,.way(way_no)
,.row_even_odd(row_even_odd)
,.req_Index(index)
,.req_data(req_data)//32 bit data+4 bit valid bit
,.Load_req(coretodc_ld_req)
,.Load_req_valid(coretodc_ld_valid)
,.Load_req_retry(coretodc_ld_retry)
,.STD_req(coretodc_std)
,.STD_req_valid(coretodc_std_valid)
,.STD_req_retry(coretodc_std_retry)
,.write_musk_reset(write_musk_reset) //when Invalidate
,.ack_valid(ack_valid)
,.req_retry(req_retry)
,.ack_data(ack_data) //36 bit
);
always_comb begin
if(hit_tag) begin
way_no=way_from_tag;
hit=hit_tag;
way=way_no;
ack_data_from_top=ack_data;
req_retry_from_top=req_retry;
output_data_tag=ack_data_to_1_tagcheck;
end
end
always_comb begin
if(miss_tag) begin
miss=miss_tag;
end
end
always_comb begin
if(reset) begin
write_musk_reset=0;
end
end
always_comb begin
tag_retry=req_retry_to_1_tagcheck;
end
endmodule
|
// $Id: c_matrix_arbiter.v 1625 2009-10-29 00:15:03Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic matrix arbiter
module c_matrix_arbiter
(clk, reset, update, req, gnt);
`include "c_constants.v"
// number of inputs ports
parameter num_ports = 32;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// update port priorities
input update;
// request vector
input [0:num_ports-1] req;
// grant vector
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
generate
if(num_ports > 1)
begin
// port priority matrix
wire [0:num_ports*num_ports-1] prio;
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
// lower triangle has inverted values of transposed upper
// triangle
genvar col;
for(col = 0; col < row; col = col + 1)
begin:cols
assign prio[row*num_ports+col] = ~prio[col*num_ports+row];
end
// diagonal has all ones
assign prio[row*num_ports+row] = 1'b1;
// upper triangle has actual registers
if(row < num_ports-1)
begin
wire [(row+1):num_ports-1] prio_s, prio_q;
assign prio_s
= update ?
(prio_q | gnt[(row+1):num_ports-1]) &
~{(num_ports-row-1){gnt[row]}} :
prio_q;
c_dff
#(.width(num_ports-row-1),
.offset(row+1),
.reset_type(reset_type),
.reset_value({(num_ports-row-1){1'b1}}))
prioq
(.clk(clk),
.reset(reset),
.d(prio_s),
.q(prio_q));
assign prio[row*num_ports+row+1:(row+1)*num_ports-1]
= prio_q;
end
// grant requests if we have priority over all other requestors
assign gnt[row]
= req[row] &
(&(prio[row*num_ports:(row+1)*num_ports-1] | ~req));
end
end
else
assign gnt = req;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } template <typename T> inline bool smin(T &a, const T &b) { return a > b ? a = b : a; } template <typename T> inline bool smax(T &a, const T &b) { return a < b ? a = b : a; } const int N = (int)1 << 15, mod = (int)998244353; int a[N], b[N], dp[N]; int pw(int a, int b) { return b != 0 ? (long long)pw((long long)a * a % mod, b >> 1) * (b & 1 ? a : 1) % mod : 1; } void NTT(int a[], int lg, bool inverse) { int N = 1 << lg; for (int i = 0; i < N; ++i) { int rev = 0; for (int j = 0; j < lg; ++j) if (i >> j & 1) rev |= 1 << (lg - j - 1); if (rev > i) swap(a[rev], a[i]); } for (int len = 2; len <= N; len <<= 1) { int wn = pw(3, (mod - 1) / len); if (inverse) wn = pw(wn, mod - 2); for (int j = 0; j < N; j += len) { int w = 1; for (int first = j, second = j + len / 2; second < j + len; ++first, ++second) { int u = a[first], v = (long long)a[second] * w % mod; a[first] = u + v; a[second] = u - v + mod; while (a[first] >= mod) a[first] -= mod; while (a[second] >= mod) a[second] -= mod; w = (long long)w * wn % mod; } } } if (inverse) { int div = pw(N, mod - 2); for (int i = 0; i < N; ++i) a[i] = (long long)a[i] * div % mod; } } int res[17][N], tmpa[17][N], tmpb[17][N]; void solve(int b, int e, int a[N], int d = 0) { if (b + 1 == e) { res[d][0] = 1; res[d][1] = a[b]; return; } int m = b + e >> 1; solve(b, m, a, d + 1); for (int j = 0; j <= (m - b); ++j) tmpa[d][j] = res[d + 1][j], res[d + 1][j] = 0; solve(m, e, a, d + 1); for (int j = 0; j <= (e - m); ++j) tmpb[d][j] = res[d + 1][j], res[d + 1][j] = 0; int lg = 0; while ((1 << lg) <= e - b) ++lg; NTT(tmpa[d], lg, false); NTT(tmpb[d], lg, false); for (int j = 0; j < (1 << lg); ++j) res[d][j] = (long long)tmpa[d][j] * tmpb[d][j] % mod, tmpa[d][j] = tmpb[d][j] = 0; NTT(res[d], lg, true); } int32_t main() { int n, k; cin >> n >> k; for (int j = 0; j < n; ++j) cin >> a[j]; int qm; cin >> qm; while (qm--) { int c; cin >> c; if (c == 1) { int q, p, d; cin >> q >> p >> d; --p; for (int j = 0; j < n; ++j) b[j] = q - a[j]; b[p] = q - d; } else { int q, l, r, d; cin >> q >> l >> r >> d; --l; for (int j = 0; j < n; ++j) b[j] = q - a[j]; for (int j = l; j < r; ++j) b[j] -= d; } for (int j = 0; j < n; ++j) b[j] = (b[j] % mod + mod) % mod; memset(res, 0, sizeof res); solve(0, n, b); cout << res[0][k] << n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = numeric_limits<int>::max(); const long long LINF = numeric_limits<long long>::max() / 2; const double DINF = numeric_limits<double>::max(); const int ITER = 3000; const double EPS = 1e-9; const int MAXN = 1005; struct addr { int x, y; addr(){}; addr(int a, int b) { x = a; y = b; } }; struct cell { addr top, bot, left, right; addr cur; cell(){}; }; cell a[MAXN][MAXN]; int val[MAXN][MAXN]; int getVal(addr cur) { return val[cur.x][cur.y]; } cell moveLeft(cell x) { x = a[x.left.x][x.left.y]; return x; } cell moveRight(cell x) { x = a[x.right.x][x.right.y]; return x; } cell moveTop(cell x) { x = a[x.top.x][x.top.y]; return x; } cell moveBot(cell x) { x = a[x.bot.x][x.bot.y]; return x; } string strad(addr x) { stringstream ss; ss << ( << x.x << , << x.y << ) ; return ss.str(); } void solve() { int n, m, q; cin >> n >> m >> q; for (int i = 0; i < MAXN; ++i) { for (int j = 0; j < MAXN; ++j) { a[i][j].cur.x = i; a[i][j].cur.y = j; if (i > 0) a[i][j].top = addr(i - 1, j); if (i < MAXN - 1) a[i][j].bot = addr(i + 1, j); if (j < MAXN - 1) a[i][j].right = addr(i, j + 1); if (j > 0) a[i][j].left = addr(i, j - 1); } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> val[i][j]; } } cout << endl; cell it = a[0][0]; while (q--) { int x, y, c, d, h, w; cin >> x >> y >> c >> d >> h >> w; cell first = a[0][0]; cell second = a[0][0]; for (int i = 0; i < x; ++i) first = moveBot(first); for (int i = 0; i < y; ++i) first = moveRight(first); for (int i = 0; i < c; ++i) second = moveBot(second); for (int i = 0; i < d; ++i) second = moveRight(second); for (int i = 0; i < w; ++i) { addr ftop = first.top; addr stop = second.top; a[ftop.x][ftop.y].bot = second.cur; a[stop.x][stop.y].bot = first.cur; a[first.cur.x][first.cur.y].top = stop; a[second.cur.x][second.cur.y].top = ftop; if (i < w - 1) { first = moveRight(first); second = moveRight(second); } } for (int i = 0; i < h; ++i) { addr fright = first.right; addr sright = second.right; a[fright.x][fright.y].left = second.cur; a[sright.x][sright.y].left = first.cur; a[first.cur.x][first.cur.y].right = sright; a[second.cur.x][second.cur.y].right = fright; if (i < h - 1) { first = moveBot(first); second = moveBot(second); } } for (int i = 0; i < w; ++i) { addr fbot = first.bot; addr sbot = second.bot; a[fbot.x][fbot.y].top = second.cur; a[sbot.x][sbot.y].top = first.cur; a[first.cur.x][first.cur.y].bot = sbot; a[second.cur.x][second.cur.y].bot = fbot; if (i < w - 1) { first = moveLeft(first); second = moveLeft(second); } } for (int i = 0; i < h; ++i) { addr sleft = second.left; addr fleft = first.left; a[fleft.x][fleft.y].right = second.cur; a[sleft.x][sleft.y].right = first.cur; a[first.cur.x][first.cur.y].left = sleft; a[second.cur.x][second.cur.y].left = fleft; if (i < h - 1) { first = moveTop(first); second = moveTop(second); } } } it = a[0][0]; it = moveRight(it); it = moveBot(it); for (int i = 0; i < n; ++i) { cell col = it; for (int j = 0; j < m; ++j) { cout << getVal(col.cur) << ; col = moveRight(col); } it = moveBot(it); cout << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, k, ans; int a[500101], b[500101], fl[500101]; int q[500101], qn; void solve() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= k; i++) { scanf( %d , &b[i]); fl[b[i]] = 1; } int fl2 = 0; for (int i = 2; i <= k; i++) if (a[b[i]] <= a[b[i - 1]] || a[b[i]] - a[b[i - 1]] < b[i] - b[i - 1]) { fl2 = 1; break; } if (fl2) { printf( -1 n ); return; } for (int i = 1; i <= n; i++) a[i] -= i; q[0] = -1000000007; int last = 0; for (int i = 1; i <= n; i++) { if (a[i] >= q[qn]) { q[++qn] = a[i]; if (fl[i]) last = qn; } else { int p = upper_bound(q + 1, q + 1 + qn, a[i]) - q; if (p > last) { q[p] = a[i]; if (fl[i]) last = qn = p; } } } printf( %d n , n - qn); } int main() { int T = 1; while (T--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T t) { return t < 0 ? -t : t; } const long long modn = 1000000007; inline long long mod(long long x) { return x % modn; } const int MAXN = 100010, INF = 0x3f3f3f3f; int n, m, deg, s[MAXN], p[MAXN]; int main() { scanf( %d , &n); for (int a = 0; a < n; a++) { scanf( %d , &s[a]); p[s[a]] = a; } int ult = -1, cnt = 0, res = 0; for (int a = 1; a <= n; a++) { if (p[a] > ult) { cnt++; ult = p[a]; res = max(cnt, res); } else { cnt = 1; ult = p[a]; } } printf( %d n , n - res); return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module m26_rx_core
#(
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTYFIER = 0
)(
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR
);
localparam VERSION = 1;
//output format #ID (as parameter IDENTYFIER + 1 frame start + 16 bit data)
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN;
reg CONF_TIMESTAMP_HEADER;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_TIMESTAMP_HEADER <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2) begin
CONF_EN <= BUS_DATA_IN[0];
CONF_TIMESTAMP_HEADER <= BUS_DATA_IN[1];
end
end
end
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {6'b0, CONF_TIMESTAMP_HEADER, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_reset_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(CLK_RX), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC;
wire CONF_EN_SYNC;
assign CONF_EN_SYNC = CONF_EN;
wire MKD_RX_IO;
IDDR IDDR_inst_mkd (
.Q1(),
.Q2(MKD_RX_IO),
.C(CLK_RX),
.CE(1'b1),
.D(MKD_RX),
.R(1'b0),
.S(1'b0)
);
wire [1:0] DATA_RX_IO;
IDDR IDDR_inst_rx0 (
.Q1(),
.Q2(DATA_RX_IO[0]),
.C(CLK_RX),
.CE(1'b1),
.D(DATA_RX[0]),
.R(1'b0),
.S(1'b0)
);
IDDR IDDR_inst_rx1 (
.Q1(),
.Q2(DATA_RX_IO[1]),
.C(CLK_RX),
.CE(1'b1),
.D(DATA_RX[1]),
.R(1'b0),
.S(1'b0)
);
reg [4:0] MKD_DLY;
always@(posedge CLK_RX)
MKD_DLY[4:0] <= {MKD_DLY[3:0], MKD_RX_IO};
reg [4:0] DATA1_DLY;
always@(posedge CLK_RX)
DATA1_DLY[4:0] <= {DATA1_DLY[3:0], DATA_RX_IO[1]};
reg [4:0] DATA0_DLY;
always@(posedge CLK_RX)
DATA0_DLY[4:0] <= {DATA0_DLY[3:0], DATA_RX_IO[0]};
wire [1:0] WRITE;
wire FRAME_START, FRAME_START1;
wire [15:0] DATA [1:0];
m26_rx_ch m26_rx_ch0(
.RST(RST_SYNC), .CLK_RX(CLK_RX), .MKD_RX(MKD_DLY[0]), .DATA_RX(DATA0_DLY[0]),
.WRITE(WRITE[0]), .FRAME_START(FRAME_START), .DATA(DATA[0])
);
m26_rx_ch m26_rx_ch1(
.RST(RST_SYNC), .CLK_RX(CLK_RX), .MKD_RX(MKD_DLY[4]), .DATA_RX(DATA1_DLY[4]),
.WRITE(WRITE[1]), .FRAME_START(FRAME_START1), .DATA(DATA[1])
);
//ila_0 ila(
// .clk(CLK_RX),
// .probe0({FRAME_START, WRITE, DATA[1], DATA[0]})
//);
reg [31:0] TIMESTAMP_save;
always@(posedge CLK_RX)
if(FRAME_START)
TIMESTAMP_save <= TIMESTAMP;
wire [17:0] cdc_data;
wire fifo_full, cdc_fifo_empty;
wire cdc_fifo_write;
reg data_lost_flag;
reg [15:0] data_field;
always@(*) begin
if(CONF_TIMESTAMP_HEADER & (WRITE[0] && FRAME_START))
data_field = TIMESTAMP[15:0];
else if(CONF_TIMESTAMP_HEADER & (WRITE[1] && FRAME_START1))
data_field = TIMESTAMP_save[31:16];
else if(WRITE[0])
data_field = DATA[0];
else
data_field = DATA[1];
end
assign cdc_data[17] = data_lost_flag;
assign cdc_data[16] = FRAME_START;
assign cdc_data[15:0] = data_field;
assign cdc_fifo_write = |WRITE & CONF_EN_SYNC;
wire wfull;
always@(posedge CLK_RX) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
always@(posedge CLK_RX) begin
if(RST_SYNC)
data_lost_flag <= 0;
else if (cdc_fifo_write) begin
if(wfull)
data_lost_flag <= 1;
else
data_lost_flag <= 0;
end
end
wire [17:0] cdc_data_out;
cdc_syncfifo #(.DSIZE(18), .ASIZE(3)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data),
.winc(cdc_fifo_write), .wclk(CLK_RX), .wrst(RST_SYNC),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(RST)
);
gerneric_fifo #(.DATA_SIZE(18), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[17:0]), .size()
);
assign FIFO_DATA[19:18] = 0;
assign FIFO_DATA[23:20] = IDENTYFIER[3:0];
assign FIFO_DATA[31:24] = HEADER[7:0];
assign LOST_ERROR = LOST_DATA_CNT != 0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
*--------------------------------------------------------------------------------
*/
//`timescale 1ps/1ps
module LAG_test_random ();
parameter CLOCK_PERIOD = 10_000;
localparam global_links_num = find_max_global_link_num(links);
flit_t flit_in[network_x-1:0][network_y-1:0];
flit_t flit_out[network_x-1:0][network_y-1:0][global_links_num-1:0];
logic [router_num_pls_on_entry-1:0] input_full_flag [network_x-1:0][network_y-1:0];
logic [global_links_num-1:0] cntrl_in [network_x-1:0][network_y-1:0];
integer rec_count [network_x-1:0][network_y-1:0];
integer flits_sent [network_x-1:0][network_y-1:0];
sim_stats_t stats [network_x-1:0][network_y-1:0];
real av_lat[network_x-1:0][network_y-1:0];
integer link_util [network_x-1:0][network_y-1:0][router_radix-1:0][global_links_num-1:0];
real link_util_ [network_x-1:0][network_y-1:0][router_radix-1:0][global_links_num-1:0];
genvar x,y;
integer i,j,k,l;
integer sys_time, total_packets, total_hops, min_latency, max_latency, total_latency;
integer min_hops, max_hops;
integer total_rec_count;
integer total_send_count;
integer lat_freq[100:0];
logic clk, rst_n;
integer s;
// clock generator
initial begin
clk=0;
end
always #(CLOCK_PERIOD/2) clk = ~clk;
always@(posedge clk) begin
if (!rst_n) begin
sys_time=0;
end else begin
sys_time++;
end
end
// ########################
// Network
// ########################
LAG_mesh_network #(.XS(network_x),
.YS(network_y),
.NP(router_radix),
.global_links_num(global_links_num),
.links(links)
) network
(flit_in, flit_out,
input_full_flag,
cntrl_in, link_util,
clk, rst_n
);
// ########################
// Traffic Sources
// ########################
generate
for (x=0; x<network_x; x++) begin:xl
for (y=0; y<network_y; y++) begin:yl
LAG_random_traffic_source #(.np(router_num_pls_on_entry),
.destinations(destinations[x][y]),
.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.packet_length(sim_packet_length)
)
traf_src (.flit_out(flit_in[x][y]),
.flits_sent_o(flits_sent[x][y]),
.network_ready(~input_full_flag[x][y]),
.clk, .rst_n
);
end
end
endgenerate
// ########################
// Traffic Sinks
// ########################
generate
for (x=0; x<network_x; x++) begin:xl2
for (y=0; y<network_y; y++) begin:yl2
LAG_traffic_sink #(.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y), .global_links_num(global_links_num),
.local_links_num(links[x][y][`TILE][OUT]), .warmup_packets(sim_warmup_packets), .measurement_packets(sim_measurement_packets)
)
traf_sink (.flit_in(flit_out[x][y]),
.cntrl_out(cntrl_in[x][y]),
.rec_count(rec_count[x][y]),
.stats(stats[x][y]),
.clk, .rst_n);
end
end
endgenerate
//
// All measurement packets must be received before we end the simulation
// (this includes a drain phase)
//
always@(posedge clk) begin
total_rec_count = 0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
if(rec_count[i][j] != -1)
total_rec_count = total_rec_count+rec_count[i][j];
end
end
if ( rst_n /* if not reset */ && ((total_rec_count - sim_warmup_packets)%(sim_measurement_packets/20)) == 0 )
$display ("%1d: %1.2f%% complete", sys_time, $itor(total_rec_count*100)/$itor(sim_measurement_packets) );
end
initial begin
$display ("******************************************");
$display ("* NoC with LAG - Predefined Traffic Test *");
$display ("******************************************");
total_hops=0;
total_latency=0;
total_send_count=0;
link_util_[i][j][k][l] = '0;
//
// reset
//
rst_n=0;
// reset
#(CLOCK_PERIOD*20);
rst_n=1;
$display ("-- Reset Complete");
$display ("-- Entering warmup phase (%1d packets per node)", sim_warmup_packets);
`ifdef DUMPTRACE
$dumpfile ("/tmp/trace.vcd");
$dumpvars;
`endif
// #################################################################
// wait for all traffic sinks to rec. all measurement packets
// #################################################################
wait (total_rec_count > sim_measurement_packets);
$display ("** Simulation End **\n");
//calculating utilization of links
for (i=0; i<network_x; i++)
for (j=0; j<network_y; j++)
for (k=0; k<router_radix; k++)
for (l=0; l<global_links_num; l++)
link_util_[i][j][k][l] = $itor(link_util[i][j][k][l]) / $itor(sys_time);
//calculating the blocking rate of each input link of each router
total_packets = sim_measurement_packets;
min_latency=stats[0][0].min_latency;
max_latency=stats[0][0].max_latency;
min_hops=stats[0][0].min_hops;
max_hops=stats[0][0].max_hops;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
av_lat[i][j] = $itor(stats[i][j].total_latency)/$itor(rec_count[i][j]);
total_latency = total_latency + stats[i][j].total_latency;
total_hops=total_hops+stats[i][j].total_hops;
min_latency = min(min_latency, stats[i][j].min_latency);
max_latency = max(max_latency, stats[i][j].max_latency);
min_hops = min(min_hops, stats[i][j].min_hops);
max_hops = max(max_hops, stats[i][j].max_hops);
end
end
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
total_send_count += flits_sent[i][j] / sim_packet_length;
end
end
for (k=0; k<=100; k++) lat_freq[k]=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
for (k=0; k<=100; k++) begin
lat_freq[k]=lat_freq[k]+stats[i][j].lat_freq[k];
end
end
end
$display ("***********************************************************************************");
$display ("-- Channel Latency = %1d", 0);
$display ("***********************************************************************************");
$display ("-- Packet Length = %1d", sim_packet_length);
$display ("-- Average Latency = %1.2f (cycles)", $itor(total_latency)/$itor(total_packets));
$display ("-- Min. Latency = %1d, Max. Latency = %1d", min_latency, max_latency);
$display ("-- Average no. of hops taken by packet = %1.2f hops (min=%1d, max=%1d)",
$itor(total_hops)/$itor(total_packets), min_hops, max_hops);
$display ("***********************************************************************************");
$display ("\n");
$display ("Average Latencies for packets rec'd at nodes [x,y] and (no. of packets received)");
for (j=0; j<network_y;j++) begin
for (i=0; i<network_x; i++)
if (rec_count[i][j] != -1)
$write ("%1.2f (%1d)\t", av_lat[i][j], rec_count[i][j]);
else
$write ("0.00 (0)\t");
$display ("");
end
$display ("");
$display ("Flits/cycle sent at each node:");
for (j=0; j<network_y; j++) begin
for (i=0; i<network_x; i++) begin
$write ("%1.2f\t", $itor(flits_sent[i][j])/$itor(sys_time));
end
$display ("");
end
$display ("");
$display ("Flits/cycle received at each node: (should approx. injection rate)");
for (j=0; j<network_y; j++) begin
for (i=0; i<network_x; i++) begin
$write ("%1.2f\t", $itor(stats[i][j].flit_count)/$itor(stats[i][j].measure_end-stats[i][j].measure_start));
end
$display ("");
end
$display ("");
$display ("Latencies for packet flows (in clock cycles)");
$display("----------------------------------------------------------");
for (j=0; j<network_y; j++) // destination y
for (i=0; i<network_x; i++) // destination x
for (l=0; l<network_y; l++) // source y
for (k=0; k<network_x; k++) // source x
if(stats[i][j].flows_latencies[k][l][0]) begin
$display ("(%1d, %1d) -> (%1d, %1d): min = %1d; av = %1d; max = %1d;",
k, l, i, j, stats[i][j].flows_latencies[k][l][3],
stats[i][j].flows_latencies[k][l][1] / stats[i][j].flows_latencies[k][l][2],
stats[i][j].flows_latencies[k][l][4]);
$display("----------------------------------------------------------");
end
$display ("\n");
$display ("Distribution of packet latencies: ");
$display ("Latency : Frequency (as percentage of total)");
$display ("-------------------");
for (k=0; k<100; k++) begin
$display ("%1d %1.2f", k, $itor(lat_freq[k]*100)/$itor(total_packets));
end
$display ("100+ %1.2f", $itor(lat_freq[k]*100)/$itor(total_packets));
$finish;
end
endmodule // LAG_test_random
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "wasca_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2560,
the_altsyncram.numwords_a = 2560,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_SYMBOL_V
/**
* udp_dff$P_pp$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int computeXOR(long long int n) { if (n % 4 == 0) return n; if (n % 4 == 1) return 1; if (n % 4 == 2) return n + 1; return 0; } void solve() { vector<long long int> v; map<long long int, long long int> mp; long long int e, i, j, l, m, x, y, z, r, k, n; cin >> n >> m; x = computeXOR(n - 1); r = x ^ n; if (x == m) cout << n << endl; else if (r == m) cout << n + 2 << endl; else cout << n + 1 << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T = 1; cin >> T; while (T--) solve(); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_top.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
`include "spi_defines.v"
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = reg_ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[`SPI_CTRL_CHAR_LEN];
assign lsb = reg_ctrl[`SPI_CTRL_LSB];
assign ie = reg_ctrl[`SPI_CTRL_IE];
assign ass = reg_ctrl[`SPI_CTRL_ASS];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {`SPI_SS_NB{tip & ass}}) | (reg_ss & {`SPI_SS_NB{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
`timescale 1ns/10ps
/*
功能：逻辑分析仪触发器
输入：nrst-0复位
clk-时钟
din-数据输入
level_sel-触发电平选择，0低电平，1高电平
level_mask-电平触发掩码，1为不关心
edge_sel-边沿触发通道选择,0~7
edge_mask-边沿触发掩码，1为不关心
输出：trig_out-1成功触发
修改：eleqian 2016-01-22
*/
module la_trig(nrst, clk, din, level_sel, level_mask, edge_sel, edge_mask, trig_out);
input nrst;
input clk;
input [7:0] din;
input [7:0] level_sel;
input [7:0] level_mask;
input [2:0] edge_sel;
input edge_mask;
output trig_out;
reg d_last;
wire d_sel;
wire d_edge;
wire m_edge;
wire [7:0] d_level;
wire [7:0] m_level;
wire s_level;
// 选择单个信号检测边沿
assign d_sel = din[edge_sel];
// 延迟一个clk以检测边沿
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
d_last <= 1'b0;
end else begin
d_last <= d_sel;
end
end
// 边沿检测
assign d_edge = d_last ^ d_sel;
// 边沿掩码
assign m_edge = d_edge | edge_mask;
// 电平选择
assign d_level = ~(din ^ level_sel);
// 电平掩码
assign m_level = d_level | level_mask;
// 各电平为与
assign trig_out = &m_level & m_edge;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, x, y; int main() { cin >> a >> b; if (a > b) { x = b; y = (a - b) / 2; } else { x = a; y = (b - a) / 2; } cout << x << << y; }
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// BlockRAM
ram
#(
.block_count(128) // 1MB
)
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
// CPU
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE("ENABLED"),
.ENABLE_DCACHE("ENABLED"),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
#include <bits/stdc++.h> inline int read() { int f = 1, x = 0; char ch = getchar(); while (!(ch >= 0 && ch <= 9 )) { if (ch == - ) f *= -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return f * x; } int dx[8] = {1, 1, -1, -1, 2, 2, -2, -2}; int dy[8] = {2, -2, 2, -2, 1, -1, 1, -1}; struct Point { int x, y, c, fa; friend bool operator==(Point a, Point b) { return (a.x == b.x && a.y == b.y); } } w[2], b[2], other, list[4][1000 * 1000 + 1]; void readother() { std::cin >> other.x >> other.y; } bool check(Point a, Point b) { int x = abs(a.x - b.x), y = abs(a.y - b.y); if (x <= 2 && y <= 2 && x + y == 3) { printf( %d %d n , b.x, b.y); return true; } return false; } int otherx, othery; bool bk = false; void printlist(int k, Point a) { if (a.fa == -1 || bk == true) return; if (a.fa != 1) printlist(k, list[k][a.fa]); if (check(a, other) == true) bk = true; if (bk == true) return; printf( %d %d n , a.x, a.y); readother(); } int n, m, head, tail, v[4][1000 + 1][1000 + 1]; void closer(int k, Point st, Point ed) { Point a, b; head = tail = 1; memset(v[k], 0, sizeof(v[k])); v[k][st.x][st.y] = head; list[k][head] = st, list[k][head].c = 0, list[k][head].fa = -1; if (st == ed) return; while (head <= tail) { a = list[k][head]; for (int i = 0; i < 8; i++) { b = a, b.x += dx[i], b.y += dy[i], b.c++; if (b.x < 1 || b.y < 1 || b.x > n || b.y > m || v[k][b.x][b.y] != 0) continue; tail++; v[k][b.x][b.y] = tail; b.fa = head; list[k][tail] = b; if (b == ed) return; } head++; } } void printlast(int k) { Point a; if (k == 0) { a = b[0]; if (check(a, other) == false) { a = b[0], a.x -= 1, a.y += 2; printf( %d %d n , a.x, a.y), readother(); } else return; if (check(a, other) == false) { a = b[0], a.x -= 3, a.y += 1; printf( %d %d n , a.x, a.y), readother(); } else return; if (check(a, other) == false) { a = b[0], a.x -= 1; printf( %d %d n , a.x, a.y), readother(); } else return; } else { a = w[0]; if (check(a, other) == false) { a = w[0], a.x += 1, a.y += 2; printf( %d %d n , a.x, a.y), readother(); } else return; if (check(a, other) == false) { a = w[0], a.x += 3, a.y += 1; printf( %d %d n , a.x, a.y), readother(); } else return; if (check(a, other) == false) { a = w[0], a.x += 1; printf( %d %d n , a.x, a.y), readother(); } else return; } } bool choose; int main() { n = read(), m = read(), w[1].x = read(), w[1].y = read(), b[1].x = read(), b[1].y = read(); w[0].x = n / 2, w[0].y = m / 2, b[0].x = n / 2 + 1, b[0].y = m / 2; closer(0, w[1], w[0]), closer(1, b[1], b[0]); closer(2, w[1], b[0]); closer(3, b[1], w[0]); if ((w[1].x + w[1].y) % 2 != (b[1].x + b[1].y) % 2) { if (list[0][v[0][w[0].x][w[0].y]].c <= list[1][v[1][b[0].x][b[0].y]].c) printf( WHITE n ), other = b[1], printlist(0, list[0][v[0][w[0].x][w[0].y]]); else if (list[2][v[2][b[0].x][b[0].y]].c >= list[1][v[1][b[0].x][b[0].y]].c + 2) printf( BLACK n ), readother(), printlist(1, list[1][v[1][b[0].x][b[0].y]]); else printf( WHITE n ), other = b[1], printlist(2, list[2][v[2][b[0].x][b[0].y]]), printlast(0); } else { if (list[1][v[1][b[0].x][b[0].y]].c < list[0][v[0][w[0].x][w[0].y]].c) printf( BLACK n ), readother(), printlist(1, list[1][v[1][b[0].x][b[0].y]]); else if (list[3][v[3][w[0].x][w[0].y]].c > list[0][v[0][w[0].x][w[0].y]].c) printf( WHITE n ), other = b[1], printlist(0, list[0][v[0][w[0].x][w[0].y]]); else printf( BLACK n ), readother(), printlist(3, list[3][v[3][w[0].x][w[0].y]]), printlast(1); } }
|
// Verilog netlist generated by Workcraft 3
module VME (d, lds, dtack, dsr, dsw, ldtack);
input dsr, dsw, ldtack;
output d, lds, dtack;
wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;
NAND3BX1 U1 (.Y(U1_ON), .AN(OUT_BUBBLE3_ON), .B(ldtack), .C(dsr));
// This inverter should have a short delay
INVX1 IN_BUBBLE3 (.Y(IN_BUBBLE3_ON), .A(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE5 (.Y(IN_BUBBLE5_ON), .A(ldtack));
OAI221X1 U7 (.Y(U7_ON), .A0(IN_BUBBLE3_ON), .A1(d), .B0(IN_BUBBLE5_ON), .B1(OUT_BUBBLE3_ON), .C0(dsw));
NAND2X1 U8 (.Y(d), .A(U7_ON), .B(U1_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE10 (.Y(IN_BUBBLE10_ON), .A(OUT_BUBBLE3_ON));
INVX1 OUT_BUBBLE1 (.Y(OUT_BUBBLE1_ON), .A(U14_ON));
OAI221X1 U14 (.Y(U14_ON), .A0(d), .A1(dsr), .B0(dsr), .B1(OUT_BUBBLE2_ON), .C0(IN_BUBBLE10_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE16 (.Y(IN_BUBBLE16_ON), .A(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE18 (.Y(IN_BUBBLE18_ON), .A(dsw));
OAI31X1 U20 (.Y(U20_ON), .A0(IN_BUBBLE18_ON), .A1(IN_BUBBLE16_ON), .A2(d), .B0(OUT_BUBBLE3_ON));
C2 U21 (.Q(lds), .A(U20_ON), .B(OUT_BUBBLE1_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE23 (.Y(IN_BUBBLE23_ON), .A(OUT_BUBBLE3_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE25 (.Y(IN_BUBBLE25_ON), .A(OUT_BUBBLE2_ON));
AOI221X1 U26 (.Y(dtack), .A0(IN_BUBBLE23_ON), .A1(dsw), .B0(d), .B1(OUT_BUBBLE3_ON), .C0(IN_BUBBLE25_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE28 (.Y(IN_BUBBLE28_ON), .A(OUT_BUBBLE3_ON));
INVX1 OUT_BUBBLE2 (.Y(OUT_BUBBLE2_ON), .A(U31_ON));
OAI222X1 U31 (.Y(U31_ON), .A0(IN_BUBBLE28_ON), .A1(dsw), .B0(OUT_BUBBLE2_ON), .B1(d), .C0(d), .C1(lds));
// This inverter should have a short delay
INVX1 IN_BUBBLE33 (.Y(IN_BUBBLE33_ON), .A(d));
INVX1 OUT_BUBBLE3 (.Y(OUT_BUBBLE3_ON), .A(U36_ON));
AOI32X1 U36 (.Y(U36_ON), .A0(IN_BUBBLE33_ON), .A1(ldtack), .A2(OUT_BUBBLE2_ON), .B0(ldtack), .B1(OUT_BUBBLE3_ON));
// signal values at the initial state:
// IN_BUBBLE10_ON IN_BUBBLE16_ON IN_BUBBLE18_ON IN_BUBBLE23_ON IN_BUBBLE25_ON IN_BUBBLE28_ON IN_BUBBLE33_ON IN_BUBBLE3_ON IN_BUBBLE5_ON !OUT_BUBBLE1_ON !OUT_BUBBLE2_ON !OUT_BUBBLE3_ON U14_ON U1_ON U20_ON U31_ON U36_ON U7_ON !d !dsr !dsw !dtack !lds !ldtack
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_BLACKBOX_V
`define SKY130_FD_SC_HS__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: input_arbiter.v 5240 2009-03-14 01:50:42Z grg $
//
// Module: input_arbiter.v
// Project: NF2.1
// Description: Goes round-robin around the input queues and services one pkt
// out of each (if available). Note that this is unfair for queues
// that always receive small packets since they pile up!
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module input_arbiter
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter STAGE_NUMBER = 2,
parameter NUM_QUEUES = 8
)
(// --- data path interface
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
// interface to rx queues
input [DATA_WIDTH-1:0] in_data_0,
input [CTRL_WIDTH-1:0] in_ctrl_0,
input in_wr_0,
output in_rdy_0,
input [DATA_WIDTH-1:0] in_data_1,
input [CTRL_WIDTH-1:0] in_ctrl_1,
input in_wr_1,
output in_rdy_1,
input [DATA_WIDTH-1:0] in_data_2,
input [CTRL_WIDTH-1:0] in_ctrl_2,
input in_wr_2,
output in_rdy_2,
input [DATA_WIDTH-1:0] in_data_3,
input [CTRL_WIDTH-1:0] in_ctrl_3,
input in_wr_3,
output in_rdy_3,
input [DATA_WIDTH-1:0] in_data_4,
input [CTRL_WIDTH-1:0] in_ctrl_4,
input in_wr_4,
output in_rdy_4,
input [DATA_WIDTH-1:0] in_data_5,
input [CTRL_WIDTH-1:0] in_ctrl_5,
input in_wr_5,
output in_rdy_5,
input [DATA_WIDTH-1:0] in_data_6,
input [CTRL_WIDTH-1:0] in_ctrl_6,
input in_wr_6,
output in_rdy_6,
input [DATA_WIDTH-1:0] in_data_7,
input [CTRL_WIDTH-1:0] in_ctrl_7,
input in_wr_7,
output in_rdy_7,
/**** not used
// --- Interface to SATA
input [DATA_WIDTH-1:0] in_data_5,
input [CTRL_WIDTH-1:0] in_ctrl_5,
input in_wr_5,
output in_rdy_5,
// --- Interface to the loopback queue
input [DATA_WIDTH-1:0] in_data_6,
input [CTRL_WIDTH-1:0] in_ctrl_6,
input in_wr_6,
output in_rdy_6,
// --- Interface to a user queue
input [DATA_WIDTH-1:0] in_data_7,
input [CTRL_WIDTH-1:0] in_ctrl_7,
input in_wr_7,
output in_rdy_7,
*****/
// --- Register interface
/*input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,*/
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------ Internal Params --------
localparam NUM_QUEUES_WIDTH = log2(NUM_QUEUES);
localparam NUM_STATES = 1;
localparam IDLE = 0;
localparam WR_PKT = 1;
// ------------- Regs/ wires -----------
wire [NUM_QUEUES-1:0] nearly_full;
wire [NUM_QUEUES-1:0] empty;
wire [DATA_WIDTH-1:0] in_data [NUM_QUEUES-1:0];
wire [CTRL_WIDTH-1:0] in_ctrl [NUM_QUEUES-1:0];
wire [NUM_QUEUES-1:0] in_wr;
wire [CTRL_WIDTH-1:0] fifo_out_ctrl[NUM_QUEUES-1:0];
wire [DATA_WIDTH-1:0] fifo_out_data[NUM_QUEUES-1:0];
reg [NUM_QUEUES-1:0] rd_en;
wire [NUM_QUEUES_WIDTH-1:0] cur_queue_plus1;
reg [NUM_QUEUES_WIDTH-1:0] cur_queue;
reg [NUM_QUEUES_WIDTH-1:0] cur_queue_next;
reg [NUM_STATES-1:0] state;
reg [NUM_STATES-1:0] state_next;
reg [CTRL_WIDTH-1:0] fifo_out_ctrl_prev;
reg [CTRL_WIDTH-1:0] fifo_out_ctrl_prev_next;
wire [CTRL_WIDTH-1:0] fifo_out_ctrl_sel;
wire [DATA_WIDTH-1:0] fifo_out_data_sel;
reg [DATA_WIDTH-1:0] out_data_next;
reg [CTRL_WIDTH-1:0] out_ctrl_next;
reg out_wr_next;
reg eop;
// ------------ Modules -------------
generate
genvar i;
for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues
small_fifo
#( .WIDTH(DATA_WIDTH+CTRL_WIDTH),
.MAX_DEPTH_BITS(2))
in_arb_fifo
(// Outputs
.dout ({fifo_out_ctrl[i], fifo_out_data[i]}),
.full (),
.nearly_full (nearly_full[i]),
.prog_full (),
.empty (empty[i]),
// Inputs
.din ({in_ctrl[i], in_data[i]}),
.wr_en (in_wr[i]),
.rd_en (rd_en[i]),
.reset (reset),
.clk (clk));
end // block: in_arb_queues
endgenerate
/*in_arb_regs
#(
.DATA_WIDTH(DATA_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
) in_arb_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
.state (state),
.out_wr (out_wr),
.out_ctrl (out_ctrl),
.out_data (out_data),
.out_rdy (out_rdy),
.eop (eop),
.clk (clk),
.reset (reset)
);*/
// ------------- Logic ------------
assign in_data[0] = in_data_0;
assign in_ctrl[0] = in_ctrl_0;
assign in_wr[0] = in_wr_0;
assign in_rdy_0 = !nearly_full[0];
assign in_data[1] = in_data_1;
assign in_ctrl[1] = in_ctrl_1;
assign in_wr[1] = in_wr_1;
assign in_rdy_1 = !nearly_full[1];
assign in_data[2] = in_data_2;
assign in_ctrl[2] = in_ctrl_2;
assign in_wr[2] = in_wr_2;
assign in_rdy_2 = !nearly_full[2];
assign in_data[3] = in_data_3;
assign in_ctrl[3] = in_ctrl_3;
assign in_wr[3] = in_wr_3;
assign in_rdy_3 = !nearly_full[3];
assign in_data[4] = in_data_4;
assign in_ctrl[4] = in_ctrl_4;
assign in_wr[4] = in_wr_4;
assign in_rdy_4 = !nearly_full[4];
assign in_data[5] = in_data_5;
assign in_ctrl[5] = in_ctrl_5;
assign in_wr[5] = in_wr_5;
assign in_rdy_5 = !nearly_full[5];
assign in_data[6] = in_data_6;
assign in_ctrl[6] = in_ctrl_6;
assign in_wr[6] = in_wr_6;
assign in_rdy_6 = !nearly_full[6];
assign in_data[7] = in_data_7;
assign in_ctrl[7] = in_ctrl_7;
assign in_wr[7] = in_wr_7;
assign in_rdy_7 = !nearly_full[7];
/* disable regs for this module */
assign cur_queue_plus1 = (cur_queue == NUM_QUEUES-1) ? 0 : cur_queue + 1;
assign fifo_out_ctrl_sel = fifo_out_ctrl[cur_queue];
assign fifo_out_data_sel = fifo_out_data[cur_queue];
always @(*) begin
state_next = state;
cur_queue_next = cur_queue;
fifo_out_ctrl_prev_next = fifo_out_ctrl_prev;
out_wr_next = 0;
out_ctrl_next = fifo_out_ctrl_sel;
out_data_next = fifo_out_data_sel;
rd_en = 0;
eop = 0;
case(state)
/* cycle between input queues until one is not empty */
IDLE: begin
if(!empty[cur_queue] && out_rdy) begin
state_next = WR_PKT;
rd_en[cur_queue] = 1;
fifo_out_ctrl_prev_next = STAGE_NUMBER;
end
if(empty[cur_queue] && out_rdy) begin
cur_queue_next = cur_queue_plus1;
end
end
/* wait until eop */
WR_PKT: begin
/* if this is the last word then write it and get out */
if(out_rdy & |fifo_out_ctrl_sel & (fifo_out_ctrl_prev==0) ) begin
out_wr_next = 1;
state_next = IDLE;
cur_queue_next = cur_queue_plus1;
eop = 1;
end
/* otherwise read and write as usual */
else if (out_rdy & !empty[cur_queue]) begin
fifo_out_ctrl_prev_next = fifo_out_ctrl_sel;
out_wr_next = 1;
rd_en[cur_queue] = 1;
end
end // case: WR_PKT
endcase // case(state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
state <= IDLE;
cur_queue <= 0;
fifo_out_ctrl_prev <= 1;
out_wr <= 0;
out_ctrl <= 1;
out_data <= 0;
end
else begin
state <= state_next;
cur_queue <= cur_queue_next;
fifo_out_ctrl_prev <= fifo_out_ctrl_prev_next;
out_wr <= out_wr_next;
out_ctrl <= out_ctrl_next;
out_data <= out_data_next;
end
end
endmodule // input_arbiter
// Local Variables:
// verilog-library-directories:(".")
// End:
|
#include <bits/stdc++.h> using namespace std; map<long, long> cmap; map<long, long>::iterator it; bool visit[200005]; long c[200005]; vector<long> graph[200005]; long res = 0, mac, counter; void DFS(long node); int main(void) { long long n, m, k, i, l, r, j; cin >> n >> m >> k; memset(visit, false, sizeof(visit)); for (i = 1; i <= n; i++) cin >> c[i]; for (i = 1; i <= m; i++) { cin >> l >> r; graph[l].push_back(r); graph[r].push_back(l); } for (i = 1; i <= n; i++) { if (!visit[i]) { mac = 0; counter = 0; DFS(i); for (it = cmap.begin(); it != cmap.end(); it++) { mac = max(mac, it->second); } res += counter - mac; cmap.clear(); } } cout << res; return 0; } void DFS(long node) { visit[node] = true; counter++; cmap[c[node]]++; long j, i; for (i = 0; i < graph[node].size(); i++) { j = graph[node][i]; if (!visit[j]) DFS(j); } }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module jtag_master #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire JTAG_CLK,
output wire TCK, // TCK
input wire TDO, // TDO
output wire TDI, // TDI
output wire TMS, // TMS
output wire SEN,
output wire SLD
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
// Module to map basil bus address to jtag_spi_core internal address
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
jtag_master_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES)
) i_jtag_master_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.JTAG_CLK(JTAG_CLK),
.TCK(TCK),
.TDO(TDO),
.TDI(TDI),
.TMS(TMS),
.SEN(SEN),
.SLD(SLD)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_1_V
`define SKY130_FD_SC_HVL__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; int ans; scanf( %d%d%d , &a, &b, &c); ans = (a - b) * c; if (!(ans % b)) ans /= b; else { ans /= b; ans += 1; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n << ; for (int i = 1; i < n; i++) { cout << i << ; } }
|
#include <bits/stdc++.h> int main() { int n, m; scanf( %d %d , &n, &m); char a[1005][1005]; for (int k = 0; k < n; k++) { scanf( %s , a[k]); } char b[1005][1005] = {0}; for (int x = 1; x < n - 1; x++) { for (int y = 1; y < m - 1; y++) { if (a[x - 1][y] == # && a[x - 1][y - 1] == # && a[x - 1][y + 1] == # ) { if (a[x][y + 1] == # && a[x][y - 1] == # && a[x + 1][y - 1] == # && a[x + 1][y] == # && a[x + 1][y + 1] == # ) b[x][y] = 2 ; } } } for (int x = 1; x < n - 1; x++) { for (int y = 1; y < m - 1; y++) { if (b[x][y] == 2 ) { a[x - 1][y] = . ; a[x - 1][y - 1] = . ; a[x - 1][y + 1] = . ; a[x][y - 1] = . ; a[x][y + 1] = . ; a[x + 1][y] = . ; a[x + 1][y - 1] = . ; a[x + 1][y + 1] = . ; } } } int book = 1; for (int k = 0; k < n; k++) { for (int y = 0; y < m; y++) { if (a[k][y] == # ) book = 0; if (book == 0) break; } } if (book == 1) printf( YES ); else printf( NO ); }
|
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output wire OUT;
(* force_downto *)
output wire[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = 0;
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
if (DIRECTION == "UP") begin
if (WIDTH < 2) begin
initial begin
$display("ERROR: \$__COUNT_ must be at least 2 bits wide (bug in extract_counter pass?).");
$finish;
end
end
// FIXME: Max width?
assign OUT = POUT == COUNT_TO;
if (HAS_CE) begin
genvar i;
for (i = 0; i < WIDTH; i++) begin: countbits
// each bit = (cur & !reset) ^ (all prev & !reset)
wire xor_to_mc_bitn;
FDCP #(
.INIT(0)
) bitn_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bitn),
.PRE(0),
.Q(POUT[i])
);
wire orterm_to_xor_bitn;
wire pterm0_to_or_bitn;
wire pterm1_to_or_bitn;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bitn_xor (
.IN_ORTERM(orterm_to_xor_bitn),
.IN_PTC(pterm1_to_or_bitn),
.OUT(xor_to_mc_bitn)
);
ORTERM #(
.WIDTH(1)
) bitn_or (
.IN(pterm0_to_or_bitn),
.OUT(orterm_to_xor_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(1)
) bitn_pterm0 (
.IN(POUT[i]),
.IN_B(OUT),
.OUT(pterm0_to_or_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(i + 1)
) bitn_pterm1 (
.IN({POUT[i-1:0], CE}),
.IN_B(OUT),
.OUT(pterm1_to_or_bitn)
);
end
end else begin
// Bit0 is special; toggle unless reset
// cur reset out
// 0 0 1
// 0 1 0
// 1 0 0
// 1 1 0
wire xor_to_mc_bit0;
FDCP #(
.INIT(0)
) bit0_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bit0),
.PRE(0),
.Q(POUT[0])
);
wire pterm_to_xor_bit0;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bit0_xor (
.IN_PTC(pterm_to_xor_bit0),
.OUT(xor_to_mc_bit0)
);
ANDTERM #(
.COMP_INP(2),
.TRUE_INP(0)
) bit0_pterm (
.IN(),
.IN_B({POUT[0], OUT}),
.OUT(pterm_to_xor_bit0)
);
genvar i;
for (i = 1; i < WIDTH; i++) begin: countbits
// each bit = (cur & !reset) ^ (all prev & !reset)
wire xor_to_mc_bitn;
FDCP #(
.INIT(0)
) bitn_ff (
.C(CLK),
.CLR(0),
.D(xor_to_mc_bitn),
.PRE(0),
.Q(POUT[i])
);
wire orterm_to_xor_bitn;
wire pterm0_to_or_bitn;
wire pterm1_to_or_bitn;
MACROCELL_XOR #(
.INVERT_OUT(0)
) bitn_xor (
.IN_ORTERM(orterm_to_xor_bitn),
.IN_PTC(pterm1_to_or_bitn),
.OUT(xor_to_mc_bitn)
);
ORTERM #(
.WIDTH(1)
) bitn_or (
.IN(pterm0_to_or_bitn),
.OUT(orterm_to_xor_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(1)
) bitn_pterm0 (
.IN(POUT[i]),
.IN_B(OUT),
.OUT(pterm0_to_or_bitn)
);
ANDTERM #(
.COMP_INP(1),
.TRUE_INP(i)
) bitn_pterm1 (
.IN(POUT[i-1:0]),
.IN_B(OUT),
.OUT(pterm1_to_or_bitn)
);
end
end
end
// FIXME: down counters
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; long long ans[2200], MOD = 1000003; long long dp[2200][2200], inv[2200], fac[2200], ifac[2200]; void init_math(int N) { inv[1] = 1LL; for (int i = 2; i <= N; i++) inv[i] = (MOD - ((MOD / i) * inv[MOD % i]) % MOD); fac[0] = 1LL; ifac[0] = 1LL; for (int i = 1; i <= N; i++) { fac[i] = (fac[i - 1] * (long long)(i)) % MOD; ifac[i] = (ifac[i - 1] * inv[i]) % MOD; } } int st[2200], stc, r, len, ms, t[2200], tc; int main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); init_math(2000); cin >> s; len = s.size(); ans[1] = 1; for (int i = 1; i <= 2000; i++) ans[i + 1] = inv[i + 1] * fac[i * 2] % MOD * ifac[i] % MOD * ifac[i] % MOD; tc = 0; bool isn = 0, ist; for (int i = 0; i < len; i++) { ist = 0; if (s[i] <= 9 && s[i] >= 0 ) isn = 1; else { if (isn) { t[tc++] = 0; isn = 0; } if (i == 0 || !(s[i - 1] <= 9 && s[i - 1] >= 0 )) { if (s[i] == * || s[i] == / ) { cout << 0 << endl; return 0; } t[tc++] = 1; } else ist = 1; } } if (isn) t[tc++] = 0; if (t[tc - 1] == 1 || ist) { cout << 0 << endl; return 0; } stc = 0; for (int i = 0; i < tc; i++) { if (t[i] == 0) st[stc]++; else stc++; } if (stc == 0) { cout << ans[tc] << endl; return 0; } dp[stc + 1][0] = 1; for (int i = stc; i >= 0; i--) { r = st[i]; if (i) { ms += r; for (int j = 1; j <= ms; j++) for (int k = max(r - j, 0); k <= ms - j; k++) { dp[i][k + 1] += (dp[i + 1][k + j - r] * ans[j]) % MOD; if (dp[i][k + 1] >= MOD) dp[i][k + 1] -= MOD; } } else { for (int j = 0; j <= ms; j++) { dp[i][j + r] += dp[i + 1][j]; if (dp[i][j + r] >= MOD) dp[i][j + r] -= MOD; } } } long long res = 0; for (int i = 1; i <= tc; i++) { res += (dp[0][i] * ans[i]) % MOD; if (res >= MOD) res -= MOD; } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a, d, t, v; double tim[200000]; double jisuan(double a, double vmax, double s) { double t = (vmax) / a; if (0.5 * a * t * t > s) return sqrt(s * 2 / a); else return t + (s - 0.5 * a * t * t) / vmax; } int main() { scanf( %d%d%d , &n, &a, &d); scanf( %d%d , &t, &v); tim[1] = t + jisuan(a, v, d); for (int i = 2; i <= n; ++i) { scanf( %d%d , &t, &v); tim[i] = t + jisuan(a, v, d); if (tim[i] < tim[i - 1]) tim[i] = tim[i - 1]; } for (int i = 1; i <= n; ++i) printf( %.10lf n , tim[i]); return 0; }
|
// file: testclk_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module testclk_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 3.906*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (3.906*2*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (3.906*2*4*1000/8.000);
time prev_rise4;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", /period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
testclk_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int v[1100]; int pd[1100][1 << 8]; int qtd1, qtd2; int vis[1100][1 << 8]; int inv[1100]; vector<int> pos[10]; bool check(int mask) { for (int i = 0; i < 8; ++i) { if (mask & (1 << i)) continue; if (qtd1) return false; } return true; } int f(int x, int mask) { if (x >= n) { if (check(mask)) return 0; else return -0x3F3F3F3F; } int &p = pd[x][mask]; if (vis[x][mask] < qtd2) { vis[x][mask] = qtd2; p = f(x + 1, mask); if (!(mask & (1 << v[x]))) { int fim, qtd; qtd = pos[v[x]].size() - inv[x]; if (qtd1 && qtd >= qtd1) { fim = pos[v[x]][inv[x] + qtd1 - 1] + 1; p = max(p, f(fim, mask | (1 << v[x])) + qtd1); } qtd = pos[v[x]].size() - inv[x]; if (qtd >= qtd2) { fim = pos[v[x]][inv[x] + qtd2 - 1] + 1; p = max(p, f(fim, mask | (1 << v[x])) + qtd2); } } } return p; } int main() { int ans = 1; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &v[i]); v[i]--; inv[i] = (int)pos[v[i]].size(); pos[v[i]].push_back(i); } for (int i = 0; i < n; ++i) { qtd1 = i, qtd2 = i + 1; ans = max(ans, f(0, 0)); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200010], b[200010]; int n, m; inline bool isprime(int x) { for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } unsigned long long hashseed; unsigned long long h1[200010], h2[200010], t[200010]; inline void prehash() { for (int i = 1; i < n; i++) h1[i] = h1[i - 1] * hashseed + (unsigned long long)b[i]; for (int i = n - 1; i; i--) h2[i] = h2[i + 1] * hashseed + (unsigned long long)b[i]; t[0] = 1; for (int i = 1; i <= n; i++) t[i] = t[i - 1] * hashseed; } inline unsigned long long q1(int l, int r) { return h1[r] - h1[l - 1] * t[r - l + 1]; } inline unsigned long long q2(int l, int r) { return h2[l] - h2[r + 1] * t[r - l + 1]; } inline bool check(int l, int r) { return q1(l, r) == q2(l, r); } set<int> ans; int main() { srand(time(NULL)); hashseed = rand() * rand(); while (!isprime(hashseed)) hashseed++; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i < n; i++) b[i] = a[i + 1] - a[i]; prehash(); bool flag; for (int i = 1; i <= n; i++) { flag = 1; if (i != 1 && !check(1, i - 1)) flag = 0; if (i != n) { if (a[1] + a[i] + m != a[i + 1] + a[n]) flag = 0; if (i != n - 1 && !check(i + 1, n - 1)) flag = 0; } if (flag) ans.insert((a[1] + a[i]) % m); } cout << ans.size() << endl; for (set<int>::iterator it = ans.begin(); it != ans.end(); it++) printf( %d , *it); }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)(1e9 + 7); const int inf = (int)INFINITY; const long long INF = (long long)INFINITY; const int MAX = (int)(2e5 + 5); const int maxn = 2e5 + 5; int n, m, k, p[maxn], path[maxn]; vector<int> in[maxn], out[maxn]; int maxa, mina; set<pair<long long, long long> > st; void dijkstra() { while (st.size()) { pair<long long, long long> x = *st.begin(); st.erase(x); int i = x.second; for (auto A : in[i]) { if (path[i] + 1 < path[A]) { st.erase(pair<long long, long long>(path[A], A)); path[A] = path[i] + 1; st.insert(pair<long long, long long>(path[A], A)); } } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (long long i = 0; i < (m); ++i) { int u, v; cin >> u >> v; out[u].push_back(v); in[v].push_back(u); } cin >> k; for (int i = 1; i <= k; ++i) cin >> p[i]; memset(path, 63, sizeof path); path[p[k]] = 0; st.insert(pair<long long, long long>(0, p[k])); dijkstra(); for (int i = 2; i <= k; ++i) { if (path[p[i]] != path[p[i - 1]] - 1) { ++mina; ++maxa; } else { int e = 0; for (auto A : out[p[i - 1]]) if (A != p[i] && path[A] == path[p[i]]) e = 1; maxa += e; } } cout << mina << << maxa; return 0; }
|
/* An 8 clock of latency shift-register FIFO. (8bit queue)
*
* This really is an 8 bit circular array with a write pointer that moves but
* it will always read from position zero. Reading empty values will
* return zero.
*
* Created by David Tran
* Version 0.1.0.0
* Last Modified:04-24-2014
*/
module shift_fifo (
readMode, // Specifies if we want to read from the FIFO
writeMode, // Specifies if we want to write form the FIFO
inputBit, // The input bit to write to the shift-register
outputBit, // The output bit to read from the shift-register
clk, // Clock input
rst // Reset input
);
input readMode, writeMode, clk, rst;
input inputBit;
output outputBit;
reg outputBit;
reg [7:0] curData; // This contains the full queue.
reg [2:0] topPtr; // This is the current write pointer (top) of the queue.
always @(posedge clk or posedge rst)
if (rst) begin
topPtr <= 3'h0;
curData <= 8'h00;
end else begin
if (readMode) begin
{curData, outputBit} <= {1'b0, curData}; // Read out "zeroth" bit
topPtr <= topPtr - 1; // Change pointer location
end else if (writeMode) begin
curData[topPtr] <= inputBit; // Write in new bit
topPtr <= topPtr + 1; // Change pointer location
end
end
endmodule
|
#include <bits/stdc++.h> int N; int T[20000 + 10]; int Cnt[20000 + 10]; int Ans; int main() { scanf( %d , &N); for (int i = 0; i < N; i++) scanf( %d , &T[i]); Ans = -1000000000; for (int i = 1; i <= N; i++) if (N % i == 0 && N / i >= 3) { for (int j = 0; j < i; j++) Cnt[j] = 0; for (int j = 0; j < N; j++) Cnt[j % i] += T[j]; for (int j = 0; j < i; j++) if (Cnt[j] > Ans) Ans = Cnt[j]; } printf( %d n , Ans); return 0; }
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
#include <bits/stdc++.h> const int N = 1000000; int n; char str[N + 10]; int cdog = 0, fdog = 0, ldog = 0, cbone = 0, fbone = 0, lbone = 0; int cntd[N + 10], cntb[N + 10]; int nxtd[N + 10], nxtb[N + 10]; int lstd[N + 10], lstb[N + 10]; int tp1[N + 10], tp2[N + 10][2]; bool dp[N + 10]; bool chk(int x) { memset(dp, 0, sizeof(dp)); dp[0] = true; for (int i = n; i >= 0; --i) { if (str[i] != P ) continue; int nd = lstd[std::min(i + x, n)]; if (nd > i) tp1[i] = tp1[nd]; else tp1[i] = i + x; } for (int i = n; i >= 0; --i) { if (str[i] != P ) continue; int nd = lstd[std::min(i + x, n)], bd = nxtd[i + 1]; if (!bd) tp2[i][0] = n + 1, tp2[i][1] = 0; else if (nd == bd) tp2[i][0] = bd - x, tp2[i][1] = i + x; else tp2[i][0] = bd - x, tp2[i][1] = tp1[nd]; } for (int i = 0; i < n; ++i) { if (!dp[i]) continue; int nd = nxtd[i + 1]; int nb = nxtb[i + 1]; if (nd == 0 || nb == 0) break; if (nb < nd) { if (nb >= nd - x) { dp[nd] = true; } if (nb >= tp2[nd][0]) { dp[std::min(tp2[nd][1], n)] = true; } } else { dp[std::min(tp1[nd], n)] = true; } } int lst = 0; for (int i = n; i >= 0; --i) if (dp[i]) { lst = i; break; } return lst >= lbone; } int main() { scanf( %d , &n); scanf( %s , str + 1); for (int i = 1; i <= n; ++i) if (str[i] == P ) { ++cdog; if (fdog == 0) fdog = i; ldog = i; cntd[i] = cntd[i - 1] + 1; cntb[i] = cntb[i - 1]; } else if (str[i] == * ) { ++cbone; if (fbone == 0) fbone = i; lbone = i; cntd[i] = cntd[i - 1]; cntb[i] = cntb[i - 1] + 1; } else { cntd[i] = cntd[i - 1]; cntb[i] = cntb[i - 1]; } if (cdog == 1) { if (cntb[ldog] > cbone - cntb[ldog]) { printf( %d %d n , cntb[ldog], ldog - fbone); } else { printf( %d %d n , cbone - cntb[ldog], lbone - ldog); } return 0; } printf( %d , cbone); for (int i = n; i >= 0; --i) { if (str[i] == P ) nxtd[i] = i; else nxtd[i] = nxtd[i + 1]; if (str[i] == * ) nxtb[i] = i; else nxtb[i] = nxtb[i + 1]; } for (int i = 1; i <= n; ++i) { if (str[i] == P ) lstd[i] = i; else lstd[i] = lstd[i - 1]; if (str[i] == * ) lstb[i] = i; else lstb[i] = lstb[i - 1]; } int l = 1, r = n, ans = 0; while (l <= r) { int mid = (l + r) >> 1; if (chk(mid)) { ans = mid, r = mid - 1; } else { l = mid + 1; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> int inp() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int sum = 0; while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum; } int n, x[200010]; long long ans[200010], sum[200010]; void solve(int a, int b) { if (a == b) return; if (a > b) std::swap(a, b); sum[1] += b - a; sum[a] -= b - a; sum[b + 1] += b - a; sum[a + 1] += (b - a - 1); sum[b] -= (b - a - 1); ans[a] += b - 1; ans[b] += a; } int main() { n = inp(); int m = inp(); for (int i = 1; i <= m; i++) x[i] = inp(); for (int i = 1; i < m; i++) solve(x[i], x[i + 1]); long long tot = 0; for (int i = 1; i <= n; i++) { tot += sum[i]; printf( %lld , tot + ans[i]); } putchar( n ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_4_V
`define SKY130_FD_SC_MS__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_4_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = (int)2e5 + 100; const int mod = (int)1e9 + 7; int cnt[MAX_N]; inline int mul(int x, int y) { return (long long)x * y % mod; } inline int powMod(int x, int n) { int ret = 1; while (n > 0) { if (n & 1) ret = mul(ret, x); x = mul(x, x); n >>= 1; } return ret; } int main() { int m; scanf( %d , &m); memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < m; ++i) { int p; scanf( %d , &p); ++cnt[p]; } vector<int> toMul; for (int i = 0; i < MAX_N; ++i) if (cnt[i] > 0) { toMul.push_back(cnt[i] + 1); } bool perfectSq = true; for (int i = 0; i < toMul.size(); ++i) { if (toMul[i] % 2 == 0) { toMul[i] /= 2; perfectSq = false; break; } } int p1 = 1; for (int i = 0; i < toMul.size(); ++i) { p1 = (long long)p1 * toMul[i] % (mod - 1); } if (!perfectSq) { int num = 1; for (int i = 0; i < MAX_N; ++i) if (cnt[i] > 0) { num = mul(num, powMod(i, cnt[i])); } printf( %d n , powMod(num, p1)); } else { int root = 1; for (int i = 0; i < MAX_N; ++i) if (cnt[i] > 0) { root = mul(root, powMod(i, cnt[i] / 2)); } printf( %d n , powMod(root, p1)); } return 0; }
|
// See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output [7:0] count,
input clk,
input reset,
input start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output clk,
output reset,
output start,
input [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] count; // From submod0 of autoinst_interface_sub.v
my_svi my_svi_noport; // To/From submod0 of autoinst_interface_sub.v
my_svi my_svi_noport_upper_decl;// To/From submod0 of autoinst_interface_sub.v
// End of automatics
autoinst_interface_sub submod0 (.*);
endmodule
|
// soc_design_mm_interconnect_0_avalon_st_adapter_008.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter_008 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_008_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: completer_pkt_gen
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Completer Packet Generator module. This block creates the header
// info for completer packets- it also passes along the data source and
// address info for the TRN state machine block to request the data from
// the egress data presenter.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module completer_pkt_gen(
input clk,
input rst,
//interface from RX Engine
input [6:0] bar_hit, //denotes which base address was hit
input comp_req, //gets asserted when the rx engine recevies a MemRd request
input [31:0] MEM_addr, //needed to fetch data from egress_data_presenter
input [15:0] MEM_req_id,//needed for completion header
input [15:0] comp_id, //needed for completion header
input [7:0] MEM_tag, //neede for completion header
//interface to completion header fifo
output reg comp_fifo_wren,
output reg [63:0] comp_fifo_data
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
//parameters used to define fixed header fields
localparam rsvd = 1'b0;
localparam fmt = 2'b10; //always with data
localparam CplD = 5'b01010; //completer
localparam TC = 3'b000;
localparam TD = 1'b0;
localparam EP = 1'b0;
localparam ATTR = 2'b00;
localparam Length = 10'b0000000001; //length is always one DWORD
localparam ByteCount = 12'b000000000100; //BC is always one DWORD
localparam BCM = 1'b0;
reg [3:0] state;
reg [6:0] bar_hit_reg;
reg [26:0] MEM_addr_reg;
reg [15:0] MEM_req_id_reg;
reg [15:0] comp_id_reg;
reg [7:0] MEM_tag_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if there is a memory read request then latch the header information
//needed to create the completion TLP header
always@(posedge clk)begin
if(comp_req)begin
bar_hit_reg <= bar_hit;
MEM_addr_reg[26:0] <= MEM_addr[26:0];
MEM_req_id_reg <= MEM_req_id;
comp_id_reg <= comp_id;
MEM_tag_reg <= MEM_tag;
end
end
// State machine
// Builds headers for completion TLP headers
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
if(comp_req)
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin //create first 64-bit completion TLP header
//NOTE: bar_hit_reg[6:0],MEM_addr_reg[26:2] are not part of completion TLP
//header but are used by tx_trn_sm module to fetch data from the
//egress_data_presenter
comp_fifo_data <= {bar_hit_reg[6:0],MEM_addr_reg[26:2],
rsvd,fmt,CplD,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,Length};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= HEAD2;
end
HEAD2 : begin //create second 64-bit completion TLP header
comp_fifo_data <= {comp_id_reg[15:0],3'b000, BCM,ByteCount,
MEM_req_id_reg[15:0],MEM_tag_reg[7:0],rsvd,
MEM_addr_reg[6:0]};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= IDLE;
end
default : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mo[10]; int main() { int n; scanf( %d , &n); int a[n + 1]; for (int i = int(0); i <= int(n - 1); i++) { scanf( %d , a + i); } sort(a, a + n); a[0] = 1; for (int i = int(1); i <= int(n - 1); i++) { if (a[i] > a[i - 1]) a[i] = a[i - 1] + 1; else a[i] = a[i - 1]; } printf( %d n , a[n - 1] + 1); }
|
#include <bits/stdc++.h> using namespace std; int n, m, d[200], g[200][200], dp[200][200], ans[200]; int cnt, st[200], ed[200]; bool flag[200]; void dfs1(int u) { flag[u] = true; st[u] = ++cnt; for (int i = 1; i <= n; i++) if (g[u][i] == 1 && !flag[i]) dfs1(i); ed[u] = ++cnt; } void dfs2(int u) { flag[u] = true; for (int i = 1; i <= n; i++) if (i ^ u) dp[u][i] = d[g[u][i]]; dp[u][u] = m; for (int i = 1; i <= n; i++) if (g[u][i] == 1 && !flag[i]) { dfs2(i); for (int j = 1; j <= n; j++) if (st[i] <= st[j] && ed[j] <= ed[i]) dp[u][j] += dp[i][j]; else dp[u][j] += min(dp[i][j], dp[i][dp[i][0]]); } dp[u][0] = u; for (int i = 1; i <= n; i++) if (st[u] <= st[i] && ed[i] <= ed[u] && dp[u][i] < dp[u][dp[u][0]]) dp[u][0] = i; } void dfs3(int u) { flag[u] = true; for (int i = 1; i <= n; i++) if (g[u][i] == 1 && !flag[i]) { if (st[i] <= st[ans[u]] && ed[ans[u]] <= ed[i]) ans[i] = ans[u]; else if (dp[i][ans[u]] < dp[i][dp[i][0]]) ans[i] = ans[u]; else ans[i] = dp[i][0]; dfs3(i); } } void solve() { for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) g[i][j] = min(g[i][j], g[i][k] + g[k][j]); memset(flag, false, sizeof(flag)); cnt = 0; dfs1(1); memset(flag, false, sizeof(flag)); dfs2(1); ans[1] = dp[1][0]; memset(flag, false, sizeof(flag)); dfs3(1); printf( %d n , dp[1][dp[1][0]]); for (int i = 1; i <= n; i++) printf( %d%c , ans[i], i < n ? : n ); } int main() { int u, v; while (scanf( %d%d , &n, &m) == 2) { for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) g[i][j] = 1000000000; for (int i = 1; i < n; i++) scanf( %d , d + i); for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); g[u][v] = g[v][u] = 1; } solve(); } return 0; }
|
#include <bits/stdc++.h> inline int getint() { register char ch; while (!isdigit(ch = getchar())) ; register int x = ch ^ 0 ; while (isdigit(ch = getchar())) x = (((x << 2) + x) << 1) + (ch ^ 0 ); return x; } const int N = 101, K = 41, mod = 1e9 + 7; int k, f[N][K], tmp[K]; std::forward_list<int> e[N]; inline void add_edge(const int &u, const int &v) { e[u].push_front(v); e[v].push_front(u); } void dfs(const int &x, const int &par) { f[x][0] = f[x][k + 1] = 1; for (int &y : e[x]) { if (y == par) continue; dfs(y, x); std::fill(&tmp[0], &tmp[k * 2] + 1, 0); for (register int i = 0; i <= k * 2; i++) { for (register int j = 0; j <= k * 2; j++) { (tmp[i + j <= k * 2 ? std::min(i, j + 1) : std::max(i, j + 1)] += (long long)f[x][i] * f[y][j] % mod) %= mod; } } std::copy(&tmp[0], &tmp[k * 2] + 1, f[x]); } } int main() { const int n = getint(); k = getint(); for (register int i = 1; i < n; i++) { add_edge(getint(), getint()); } dfs(1, 0); int ans = 0; for (register int i = 0; i <= k; i++) { (ans += f[1][i]) %= mod; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> int main() { int tab[2000], i, max = 0, posmax = 0, index = -1, n; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &tab[i]); if (tab[i] > max) { max = tab[i]; posmax = i + 1; } } while (max-- && index == -1) for (i = 0; i < n; i++) if (tab[i] == max) { index = i; break; } printf( %d %d , posmax, tab[index]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; long long x[1000005], r, cur[1000005]; long long len; bool check(long long cnt) { long long res = 0, s = 0; for (int i = (1); i < (n + 1); i++) cur[i] = 0; for (int i = (1); i < (r + 1); i++) s += x[i]; for (int i = 1; i <= n; i++) { s += x[i + r]; if (i > r) { s = s - x[i - r - 1] - cur[i - r - 1]; } if (s < cnt) { long long d = cnt - s; res += d; cur[i + r] += d; s += d; if (res > k) return 0; } } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> r >> k; for (int i = 1; i <= n; i++) { cin >> x[i]; } long long l = 0, r = 2e18, mid, ans = 0; while (l <= r) { mid = (l + r) >> 1ll; if (check(mid)) { l = mid + 1; ans = max(ans, mid); } else { r = mid - 1; } } cout << ans; return 0; }
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
(* whitebox *)
module CBLOCK (
I,
O,
CIN,
COUT
);
input wire [3:0] I;
(* carry="C" *)
input wire CIN;
(* DELAY_MATRIX_I="30e-12 30e-12 30e-12 30e-12" *)
(* DELAY_CONST_CIN="30e-12" *)
output wire O;
(* carry="C" *)
(* DELAY_MATRIX_I="30e-12 30e-12 30e-12 30e-12" *)
(* DELAY_CONST_CIN="30e-12" *)
output wire COUT;
wire [4:0] internal_sum;
assign internal_sum = I + CIN;
assign O = internal_sum[4];
assign COUT = internal_sum[3];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; const long long inf = 1e18 + 9; int n, m, k, q; vector<pair<int, int> > g[maxn]; pair<long long, pair<int, int> > edges[maxn]; pair<int, int> query[maxn]; struct data { int id; long long val; bool operator<(const data& other) const { return val > other.val; } }; long long d[maxn]; int lab[maxn]; int low[maxn], high[maxn]; vector<int> vec[maxn]; void read_input() { cin >> n >> m >> k >> q; for (int i = 1; i <= m; ++i) { int u, v, w; cin >> u >> v >> w; edges[i] = make_pair(w, pair<int, int>(u, v)); g[u].push_back(pair<int, int>(v, w)); g[v].push_back(pair<int, int>(u, w)); } for (int i = 1; i <= q; ++i) { int u, v; cin >> u >> v; query[i] = pair<int, int>(u, v); } } void dijkstra() { priority_queue<data> pq; fill(d + 1, d + n + 1, inf); for (int i = 1; i <= k; ++i) { d[i] = 0; pq.push({i, 0}); } while (!pq.empty()) { data tp = pq.top(); pq.pop(); if (tp.val != d[tp.id]) continue; int u = tp.id; for (auto& to : g[u]) { int v = to.first, w = to.second; if (d[v] > d[u] + w) { d[v] = d[u] + w; pq.push({v, d[v]}); } } } } int find_set(int u) { return lab[u] < 0 ? u : lab[u] = find_set(lab[u]); } void union_sets(int u, int v) { if (lab[u] < lab[v]) swap(u, v); lab[v] += lab[u]; lab[u] = v; } void solve() { dijkstra(); for (int i = 1; i <= m; ++i) { int u = edges[i].second.first, v = edges[i].second.second; edges[i].first += d[u] + d[v]; } sort(edges + 1, edges + m + 1); for (int i = 1; i <= q; ++i) { low[i] = 1; high[i] = m; } while (true) { bool stop = true; for (int i = 1; i <= q; ++i) if (low[i] <= high[i]) { stop = false; int mid = (low[i] + high[i]) / 2; vec[mid].push_back(i); } if (stop) break; fill(lab + 1, lab + n + 1, -1); for (int i = 1; i <= m; ++i) { int u = edges[i].second.first, v = edges[i].second.second; u = find_set(u); v = find_set(v); if (u != v) union_sets(u, v); while ((int)vec[i].size()) { int id = vec[i].back(); vec[i].pop_back(); if (find_set(query[id].first) == find_set(query[id].second)) high[id] = i - 1; else low[id] = i + 1; } } } for (int i = 1; i <= q; ++i) cout << edges[low[i]].first << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); read_input(); solve(); }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module altera_up_altpll (
// Inputs
refclk,
reset,
// Bidirectional
// Outputs
outclk0,
outclk1,
outclk2,
locked
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter OUTCLK0_MULT = 1;
parameter OUTCLK0_DIV = 1;
parameter OUTCLK1_MULT = 1;
parameter OUTCLK1_DIV = 1;
parameter OUTCLK2_MULT = 1;
parameter OUTCLK2_DIV = 1;
parameter PHASE_SHIFT = 0;
parameter DEVICE_FAMILY = "Cyclone IV";
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input refclk;
input reset;
// Bidirectionals
// Outputs
output outclk0;
output outclk1;
output outclk2;
output locked;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll PLL_for_DE_Series_Boards (
// Inputs
.inclk ({1'b0, refclk}),
// Outputs
.clk ({outclk2, outclk1, outclk0}),
.locked (locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
PLL_for_DE_Series_Boards.clk0_divide_by = OUTCLK0_DIV,
PLL_for_DE_Series_Boards.clk0_duty_cycle = 50,
PLL_for_DE_Series_Boards.clk0_multiply_by = OUTCLK0_MULT,
PLL_for_DE_Series_Boards.clk0_phase_shift = "0",
PLL_for_DE_Series_Boards.clk1_divide_by = OUTCLK1_DIV,
PLL_for_DE_Series_Boards.clk1_duty_cycle = 50,
PLL_for_DE_Series_Boards.clk1_multiply_by = OUTCLK1_MULT,
PLL_for_DE_Series_Boards.clk1_phase_shift = PHASE_SHIFT,
PLL_for_DE_Series_Boards.clk2_divide_by = OUTCLK2_DIV,
PLL_for_DE_Series_Boards.clk2_duty_cycle = 50,
PLL_for_DE_Series_Boards.clk2_multiply_by = OUTCLK2_MULT,
PLL_for_DE_Series_Boards.clk2_phase_shift = "0",
PLL_for_DE_Series_Boards.compensate_clock = "CLK0",
PLL_for_DE_Series_Boards.gate_lock_signal = "NO",
PLL_for_DE_Series_Boards.inclk0_input_frequency = 20000,
PLL_for_DE_Series_Boards.intended_device_family = DEVICE_FAMILY,
PLL_for_DE_Series_Boards.invalid_lock_multiplier = 5,
PLL_for_DE_Series_Boards.lpm_type = "altpll",
PLL_for_DE_Series_Boards.operation_mode = "NORMAL",
PLL_for_DE_Series_Boards.pll_type = "FAST",
PLL_for_DE_Series_Boards.port_activeclock = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_areset = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkbad0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkbad1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkloss = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkswitch = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_fbin = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_inclk0 = "PORT_USED",
PLL_for_DE_Series_Boards.port_inclk1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_locked = "PORT_USED",
PLL_for_DE_Series_Boards.port_pfdena = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_pllena = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scanaclr = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scanclk = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scandata = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scandataout = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scandone = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scanread = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_scanwrite = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clk0 = "PORT_USED",
PLL_for_DE_Series_Boards.port_clk1 = "PORT_USED",
PLL_for_DE_Series_Boards.port_clk2 = "PORT_USED",
PLL_for_DE_Series_Boards.port_clk3 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clk4 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clk5 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena2 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena3 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena4 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_clkena5 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_enable0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_enable1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclk0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclk1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclk2 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclk3 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclkena0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclkena1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclkena2 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_extclkena3 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_sclkout0 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.port_sclkout1 = "PORT_UNUSED",
PLL_for_DE_Series_Boards.valid_lock_multiplier = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(long long first) { return first ? 8 * sizeof(long long) - __builtin_clzll(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; class DPowerTree { public: int N; vector<vector<int>> E; vector<long long> C; vector<int> Omit; vector<bool> Take; vector<pair<long long, long long>> Ans; pair<long long, long long> solve(int u, int p) { if (E[u].size() == 1 && u != 0) { return Ans[u] = {0, C[u]}; }; long long a = 0, b = 0; for (int v : E[u]) { if (v != p) { auto s = solve(v, u); a = min(a + s.second, b + s.first); b += s.second; } } return Ans[u] = {a, min(b, a + C[u])}; } void collect(int u, int p, bool allPaths, vector<int>& Ret) { long long diff = Ans[u].second - Ans[u].first; if (allPaths && C[u] <= diff) Ret.push_back(u + 1); int worst = -1; int cnt = 0; for (int v : E[u]) { if (v != p) { int myDiff = Ans[v].second - Ans[v].first; if (myDiff > worst) { worst = myDiff; cnt = 0; } cnt += myDiff == worst; } } for (int v : E[u]) { if (v != p) { int myDiff = Ans[v].second - Ans[v].first; collect(v, u, myDiff < worst || cnt > 1 || (worst <= C[u] && allPaths), Ret); } } } void solve(istream& cin, ostream& cout) { cin >> N; C.resize(N); cin >> C; E.resize(N); Ans.resize(N); for (int i = 0; i < N - 1; ++i) { int u, v; cin >> u >> v; --u; --v; E[u].push_back(v); E[v].push_back(u); } auto s = solve(0, -1); vector<int> X; collect(0, -1, true, X); sort(X.begin(), X.end()); cout << s.second << << X.size() << endl; cout << X; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); DPowerTree solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_4_V
`define SKY130_FD_SC_HD__NAND2B_4_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_FUNCTIONAL_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^16 + x^15 + x^2 + 1
// * data width: 64
//
// Info :
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC16_D64(
nextCRC16_D64,
Data,
crc
);
output reg [15:0] nextCRC16_D64;
input wire [63:0] Data;
input wire [15:0] crc;
reg [63:0] d;
reg [15:0] c;
reg [15:0] newcrc;
always @ (*)
begin
d = Data;
c = crc;
newcrc[0] = d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[12] ^ c[13] ^ c[14] ^ c[15];
newcrc[1] = d[63] ^ d[62] ^ d[61] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[13] ^ c[14] ^ c[15];
newcrc[2] = d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[46] ^ d[42] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[16] ^ d[14] ^ d[1] ^ d[0] ^ c[8] ^ c[9] ^ c[12] ^ c[13];
newcrc[3] = d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[47] ^ d[43] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[17] ^ d[15] ^ d[2] ^ d[1] ^ c[9] ^ c[10] ^ c[13] ^ c[14];
newcrc[4] = d[63] ^ d[62] ^ d[59] ^ d[58] ^ d[48] ^ d[44] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[18] ^ d[16] ^ d[3] ^ d[2] ^ c[0] ^ c[10] ^ c[11] ^ c[14] ^ c[15];
newcrc[5] = d[63] ^ d[60] ^ d[59] ^ d[49] ^ d[45] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[19] ^ d[17] ^ d[4] ^ d[3] ^ c[1] ^ c[11] ^ c[12] ^ c[15];
newcrc[6] = d[61] ^ d[60] ^ d[50] ^ d[46] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[20] ^ d[18] ^ d[5] ^ d[4] ^ c[2] ^ c[12] ^ c[13];
newcrc[7] = d[62] ^ d[61] ^ d[51] ^ d[47] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[21] ^ d[19] ^ d[6] ^ d[5] ^ c[3] ^ c[13] ^ c[14];
newcrc[8] = d[63] ^ d[62] ^ d[52] ^ d[48] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[22] ^ d[20] ^ d[7] ^ d[6] ^ c[0] ^ c[4] ^ c[14] ^ c[15];
newcrc[9] = d[63] ^ d[53] ^ d[49] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[23] ^ d[21] ^ d[8] ^ d[7] ^ c[1] ^ c[5] ^ c[15];
newcrc[10] = d[54] ^ d[50] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[24] ^ d[22] ^ d[9] ^ d[8] ^ c[2] ^ c[6];
newcrc[11] = d[55] ^ d[51] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[25] ^ d[23] ^ d[10] ^ d[9] ^ c[3] ^ c[7];
newcrc[12] = d[56] ^ d[52] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[26] ^ d[24] ^ d[11] ^ d[10] ^ c[4] ^ c[8];
newcrc[13] = d[57] ^ d[53] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[27] ^ d[25] ^ d[12] ^ d[11] ^ c[5] ^ c[9];
newcrc[14] = d[58] ^ d[54] ^ d[43] ^ d[42] ^ d[41] ^ d[40] ^ d[28] ^ d[26] ^ d[13] ^ d[12] ^ c[6] ^ c[10];
newcrc[15] = d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[44] ^ d[42] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[11] ^ c[12] ^ c[13] ^ c[14] ^ c[15];
nextCRC16_D64 = newcrc;
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module mbus_layer_wrapper
(
input CLKIN,
input RESETn,
input DIN,
output CLKOUT,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH-1:0] RX_ADDR,
output [`DATA_WIDTH-1:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK,
output [3:0] debug
);
parameter ADDRESS = 20'h12345;
wire w_n0lc0_clk_out;
wire w_n0lc0;
wire ext_int_to_wire;
wire ext_int_to_bus;
wire clr_ext_int;
wire clr_busy;
wire [`DYNA_WIDTH-1:0] rf_addr_out_to_node;
wire [`DYNA_WIDTH-1:0] rf_addr_in_from_node;
wire rf_addr_valid;
wire rf_addr_write;
wire rf_addr_rstn;
mbus_node#(.ADDRESS(ADDRESS)) n0
(
.CLKIN (CLKIN),
.CLKOUT (w_n0lc0_clk_out),
.RESETn (RESETn),
.DIN (DIN),
.DOUT (w_n0lc0),
.TX_ADDR (TX_ADDR),
.TX_DATA (TX_DATA),
.TX_REQ (TX_REQ),
.TX_ACK (TX_ACK),
.TX_PEND (TX_PEND),
.TX_PRIORITY (TX_PRIORITY),
.RX_ADDR (RX_ADDR),
.RX_DATA (RX_DATA),
.RX_REQ (RX_REQ),
.RX_ACK (RX_ACK),
.RX_BROADCAST (RX_BROADCAST),
.RX_FAIL (RX_FAIL),
.RX_PEND (RX_PEND),
.rx_snoop(1'b0),
.TX_SUCC (TX_SUCC),
.TX_FAIL (TX_FAIL),
.TX_RESP_ACK (TX_RESP_ACK),
.MBC_RESET (),
.SLEEP_REQUEST_TO_SLEEP_CTRL(),
.LRC_SLEEP (),
.LRC_CLKENB (),
.LRC_RESET (),
.LRC_ISOLATE (),
.EXTERNAL_INT (ext_int_to_bus),
.CLR_EXT_INT (clr_ext_int),
.CLR_BUSY (clr_busy),
.ASSIGNED_ADDR_IN (rf_addr_out_to_node),
.ASSIGNED_ADDR_OUT (rf_addr_in_from_node),
.ASSIGNED_ADDR_VALID (rf_addr_valid),
.ASSIGNED_ADDR_WRITE (rf_addr_write),
.ASSIGNED_ADDR_INVALIDn (rf_addr_rstn),
.debug(debug)
);
mbus_wire_ctrl lc0
(
.RESETn(RESETn),
.DIN(DIN),
.CLKIN(CLKIN),
.RELEASE_ISO_FROM_SLEEP_CTRL(1'b0),
.DOUT_FROM_BUS(w_n0lc0),
.CLKOUT_FROM_BUS(w_n0lc0_clk_out),
.DOUT(DOUT),
.CLKOUT(CLKOUT),
.EXTERNAL_INT(ext_int_to_wire)
);
mbus_addr_rf rf0
(
.RESETn (RESETn),
.RELEASE_ISO_FROM_SLEEP_CTRL (1'b0),
.ADDR_OUT (rf_addr_out_to_node),
.ADDR_IN (rf_addr_in_from_node),
.ADDR_VALID (rf_addr_valid),
.ADDR_WR_EN (rf_addr_write),
.ADDR_CLRn (rf_addr_rstn)
);
// always on interrupt controller
mbus_int_ctrl mic0
(
.CLKIN (CLKIN),
.RESETn (RESETn),
.MBC_ISOLATE (1'b0),
.SC_CLR_BUSY (1'b0),
.MBUS_CLR_BUSY (clr_busy),
.REQ_INT (1'b0),
.MBC_SLEEP (1'b0),
.LRC_SLEEP (1'b0),
.EXTERNAL_INT_TO_WIRE (ext_int_to_wire),
.EXTERNAL_INT_TO_BUS (ext_int_to_bus),
.CLR_EXT_INT (clr_ext_int)
);
endmodule // mbus_layer_wrapper
|
#include <bits/stdc++.h> using namespace std; void Read(int &n) { int sign = 1; n = 0; char c; do { c = getchar(); } while (!isdigit(c) && c != - ); if (c == - ) { c = getchar(); sign = -1; } do { n = n * 10 + c - 48; c = getchar(); } while (isdigit(c)); n *= sign; } void Read(long long &n) { int sign = 1; n = 0; char c; do { c = getchar(); } while (!isdigit(c) && c != - ); if (c == - ) { c = getchar(); sign = -1; } do { n = n * 10ll + c - 48; c = getchar(); } while (isdigit(c)); n *= sign; } void Write(int n) { if (n == 0) { putchar( 0 ); return; } else if (n < 0) putchar( - ), n = -n; char C[30]; int d = 0; while (n) { C[++d] = (n % 10) + 48; n /= 10; } for (int i = d; i >= 1; --i) putchar(C[i]); } void Write(long long n) { if (n == 0) { putchar( 0 ); return; } else if (n < 0) putchar( - ), n = -n; char C[30]; int d = 0; while (n) { C[++d] = (n % 10ll) + 48; n /= 10ll; } for (int i = d; i >= 1; --i) putchar(C[i]); } const int maxn = 1e4 + 5; const long long INFL = 0x3f3f3f3f3f3f3f3f; int n, c; long long f[maxn], g[maxn]; int p[maxn], s[maxn]; int main() { scanf( %d%d , &n, &c); for (int i = 0; i < n; ++i) scanf( %d , &p[i]); for (int i = 0; i < n; ++i) scanf( %d , &s[i]); memset(f, INFL, sizeof f); f[0] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j <= i; ++j) g[j] = f[j], f[j] = INFL; for (int j = 0; j <= i; ++j) { f[j + 1] = min(g[j] + s[i], f[j + 1]); f[j] = min(f[j], g[j] + p[i] + (long long)j * c); } } long long ans = INFL; for (int i = 0; i <= n; ++i) ans = min(ans, f[i]); printf( %I64d , ans); return 0; }
|
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