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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:29:20 10/26/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
input clk,
input reset,
input rx,
input fsm,
output [2:0] Led,
output tx
);
`define TXreg 3'b001
`define controltx 3'b011
`define RXreg 3'b101
`define controlrx 3'b111
`define NOTREADY 3'b000
`define WAITRX 3'b001
`define TRANS 3'b010
`define PASSTX 3'b011
`define CHECKTX 3'b100
`define PASSTX1 3'b101
`define STOP 3'b111
`define RXREADY dout[1]
reg wr_tx, rd_tx, wr_rx, rd_rx, rx_sel, tx_sel, finished, dadd, clr;
reg [7:0] data;
wire [7:0] ready, dout_tx;
wire [8:0] dout_rx;
reg [2:0] addr_rx, addr_tx;
reg [2:0] nstate, pstate, dout;
reg [1:0] trans;
assign ready = 8'b00000001;
uart_tx #(.PERIOD(8'h1A)) out(
.clk (clk),
.reset (reset),
.wren (wr_tx),
.rden (rd_tx),
.din (data),
.dout (dout_tx),
.txout (tx),
.addr (addr_tx));
uart_rx #(.PERIOD(8'h1A)) in(
.clk (clk),
.reset (reset),
.wren (wr_rx),
.rden (rd_rx),
.din (ready),
.dout (dout_rx),
.rxin (rx),
.addr (addr_rx));
// adder
always @(posedge clk or posedge reset) begin
if(reset)
data <= 8'b11111111;
else begin
if(rx_sel)
data <= dout_rx + 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if(reset)
dout = dout_rx[2:0];
else begin
if(dadd)
dout = dout_tx[2:0];
else
dout = dout_rx[2:0];
end
end
assign Led[0] = dout[0];
assign Led[1] = dout[1];
assign Led[2] = data[2];
always @* begin
addr_rx = `controlrx;
case(rx_sel)
1'b1:
addr_rx = `RXreg;
endcase
end
always @* begin
if(tx_sel)
addr_tx = `TXreg;
else
addr_tx = `controltx;
end
//trans clock
always @(posedge clk or posedge reset) begin
if(reset)
trans <= 2'b00;
else begin
trans <= trans + 1;
if(clr)
trans <= 2'b00;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `NOTREADY;
else
pstate <= nstate;
end
// fsm
always @* begin
wr_tx = 0; wr_rx = 0;
rd_tx = 0; rd_tx = 0;
rx_sel = 0; tx_sel = 0;
finished = 0; clr = 0;
nstate = pstate;
case (pstate)
`NOTREADY: begin
wr_rx = 1;
nstate = `WAITRX;
end
`WAITRX: begin
rd_rx = 1;
if(`RXREADY) begin
nstate = `TRANS;
clr = 1;
end
end
`TRANS: begin
if(trans == 2'b11) begin
rd_rx = 1;
rx_sel = 1;
nstate = `PASSTX;
end
end
`PASSTX: begin
rd_rx = 1;
rx_sel = 1;
nstate = `PASSTX1;
end
`PASSTX1: begin
wr_tx = 1;
tx_sel = 1;
nstate = `STOP;
end
`STOP: begin
nstate = `STOP;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a, b, n; long long mod = 1000000007; vector<long long> factorial(1000005); bool excellent(long long z) { while (z != 0) { if (z % 10 != a && z % 10 != b) return false; z /= 10; } return true; } long long pow(long long a, long long p) { if (p == 0) return 1; if (p % 2 == 1) return (a * pow(a, p - 1)) % mod; long long v = pow(a, p >> 1); return (v * v) % mod; } int calc(int n, int m) { return (factorial[n] * (pow(factorial[m], mod - 2) % mod) % mod * (pow(factorial[n - m], mod - 2) % mod) % mod); } int main() { cin >> a >> b >> n; factorial[1] = 1; for (int i = 2; i <= n; i++) factorial[i] = (factorial[i - 1] * i) % mod; long long count = 0; for (int i = 0; i <= n; i++) { if (excellent(a * i + b * (n - i))) { if (n - i != 0 && i != 0) { count += calc(n, i); count = count % mod; } else count++; } } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5010; struct Edge { int v, u, f, r, c; Edge() {} Edge(int v, int u, int f, int c, int r) : v(v), u(u), f(f), c(c), r(r) {} }; const int inf = 1e9; const int C = 4000; int n, m, k, nflow, s, t, parent[N], number[N], a[N], b[N]; int dist[N], pl[N]; vector<Edge> g[N]; queue<pair<int, int> > q; vector<int> ga, gb; void addEdge(int a, int b, int u, int c) { g[a].push_back(Edge(b, u, 0, c, g[b].size())); g[b].push_back(Edge(a, 0, 0, -c, g[a].size() - 1)); } int MinCostFlow() { int flow = 0; int cost = 0; while (true) { for (int i = 1; i <= nflow; i++) dist[i] = inf; dist[s] = 0; q.push(make_pair(0, s)); while (!q.empty()) { int v = (q.front()).second; int d = -(q.front()).first; q.pop(); if (dist[v] != d) continue; if (d == inf) break; for (int i = 0; i < g[v].size(); i++) if (g[v][i].f < g[v][i].u && dist[g[v][i].v] > d + g[v][i].c) { dist[g[v][i].v] = d + g[v][i].c; q.push(make_pair(-dist[g[v][i].v], g[v][i].v)); number[g[v][i].v] = i; parent[g[v][i].v] = v; } } if (dist[t] == inf) break; int v = t, addflow = 1e9; while (v != s) { int u = parent[v]; addflow = min(addflow, g[u][number[v]].u - g[u][number[v]].f); v = u; } v = t; while (v != s) { int u = parent[v]; cost += addflow * g[u][number[v]].c; g[u][number[v]].f += addflow; g[v][g[u][number[v]].r].f -= addflow; v = u; } flow += addflow; } return cost; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); s = n + 3; t = n + 4; for (int i = 1; i <= n; i++) { addEdge(n + 1, i, 1, -a[i]); addEdge(n + 2, i, 1, -b[i]); } addEdge(s, n + 1, m, 0); addEdge(s, n + 2, k, 0); for (int i = 1; i <= n; i++) { addEdge(i, t, 1, 0); } nflow = n + 4; int ans = -MinCostFlow(); cout << ans << endl; for (int j = 0; j < g[n + 1].size(); j++) { int v = g[n + 1][j].v; if (v >= 1 && v <= n && g[n + 1][j].f == 1) { ga.push_back(v); } } for (int j = 0; j < g[n + 2].size(); j++) { int v = g[n + 2][j].v; if (v >= 1 && v <= n && g[n + 2][j].f == 1) { gb.push_back(v); } } for (int i = 0; i < ga.size(); i++) cout << ga[i] << ; cout << endl; for (int i = 0; i < gb.size(); i++) cout << gb[i] << ; cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_lp__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int BIN[30], P[1000005], vis[1000005]; int _bin(int n) { int i, now; for (i = 0; BIN[i] <= n; i++) now = BIN[i]; return BIN[i]; } int main() { int i, j, n, k, now, t; long long ans = 0; for (i = 1, BIN[0] = 1; i < 30; i++) BIN[i] = BIN[i - 1] * 2; for (scanf( %d , &n), i = n; i; i--) if (vis[i] == 0) { now = _bin(i); t = (now - 1) ^ i; ans += t + i + t + i; P[i] = t, P[t] = i; vis[t] = 1; } for (i = 0, printf( %I64d n , ans); i <= n; i++) printf( %d%c , P[i], i == n ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const bool MULTI_TESTCASES = 0; struct Query { int l, r, id; }; void solve() { int n, k; cin >> n >> k; vector<int> t(n + 1); for (int i = 1; i < n + 1; ++i) { cin >> t[i]; if (t[i] == 2) t[i] = -1; } vector<ll> a(n + 1); for (int i = 1; i < n + 1; ++i) { cin >> a[i]; a[i] *= t[i]; a[i] += a[i - 1]; } map<ll, int> comp; for (int i = 0; i < n + 1; ++i) { comp[a[i]] = comp[a[i] - k] = comp[a[i] + k] = 0; } int z = 0; for (auto &kv : comp) kv.second = z++; vector<int> a1(n + 1), a2(n + 1), a3(n + 1); for (int i = 0; i < n + 1; ++i) { a1[i] = comp[a[i]]; a2[i] = comp[a[i] - k]; a3[i] = comp[a[i] + k]; } int q; cin >> q; vector<Query> qs(q); for (int i = 0; i < q; ++i) { cin >> qs[i].l >> qs[i].r; --qs[i].l; qs[i].id = i; } int sqrtn = sqrt(n + 1); sort(qs.begin(), qs.end(), [&](const Query &q1, const Query &q2) { return make_pair(q1.l / sqrtn, q1.r) < make_pair(q2.l / sqrtn, q2.r); }); int l = 0, r = -1; ll cur = 0; vector<ll> ans(q), oc(z); for (auto &query : qs) { while (l > query.l) { --l; cur += oc[a3[l]]; oc[a1[l]]++; } while (l < query.l) { oc[a1[l]]--; cur -= oc[a3[l]]; ++l; } while (r < query.r) { ++r; cur += oc[a2[r]]; oc[a1[r]]++; } while (r > query.r) { oc[a1[r]]--; cur -= oc[a2[r]]; --r; } ans[query.id] = cur; } for (auto x : ans) { cout << x << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int testcases = 1; if (MULTI_TESTCASES) cin >> testcases; while (testcases--) solve(); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:00:03 05/22/2014
// Design Name:
// Module Name: cpu_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_top(
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec,
output wire [5:0] initype,
output wire [3:0] node,
output wire [7:0] segment
);
wire clock;
wire memclock;
wire resetn;
wire [31:0] dpdata;
reg [15:0] digit,count=0;
wire [7:0] pc;
wire [31:0] inst;
wire [31:0] ealu;
wire [31:0] malu;
wire [31:0] walu;
wire [7:0] bpc,jpc,npc,dpc4,epc4,pc4;
wire [31:0] ins,da,db,ea,eb,dimm,eimm; wire [31:0] mb,mmo,wmo,wdi;
wire [4:0] drn,ern0,ern,mrn,wrn,dsa,esa;
wire [3:0] daluc,ealuc;
wire [1:0] pcsource;
wire wpcir;
wire dwreg,dm2reg,dwmem,daluimm,dshift,djal;//id stage
wire ewreg,em2reg,ewmem,ealuimm,eshift,ejal;//exe stage
wire mwreg,mm2reg,mwmem;//mem stage
wire wwreg,wm2reg;//wb stage
pbdebounce p0(clk,stp,clock);
assign memclock=clk;
pbdebounce p1(clk,rst,resetn);
always @(posedge clock) count=count+1;
pipepc prog_cnt(npc,wpcir,clock,resetn,pc);
pipeif if_stage(pcsource,pc,bpc,da,jpc,npc,pc4,ins);
pipeir inst_reg(pc4,ins,wpcir,clock,resetn,dpc4,inst);
pipeid id_stage(mwreg,mrn,ern,ewreg,em2reg,mm2reg,dpc4,inst,wrn,wdi,ealu,malu,mmo,wwreg,clock,resetn,bpc,jpc,pcsource,wpcir,dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dsa,regselect,dpdata);
pipedereg de_reg(dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dpc4,dsa,clock,resetn,ewreg,em2reg,ewmem,ealuc,ealuimm,ea,eb,eimm,ern0,eshift,ejal,epc4,esa);
pipeexe exe_stage(ealuc,ealuimm,ea,eb,eimm,esa,eshift,ern0,epc4,ejal,ern,ealu);
pipeemreg em_reg(ewreg,em2reg,ewmem,ealu,eb,ern,clock,resetn,mwreg,mm2reg,mwmem,malu,mb,mrn);
pipemem mem_stage(mwmem,malu,mb,clock,memclock,mmo);
pipemwreg mw_reg(mwreg,mm2reg,mmo,malu,mrn,clock,resetn,wwreg,wm2reg,wmo,walu,wrn);
mux2x32 wb_stage(walu,wmo,wm2reg,wdi);
display dp(clk,digit,node,segment);
always @* begin
case (dptype)
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<={8'b0,pc[7:0]};
2'b11:digit<=count;
endcase
end
assign exec=clock;
assign initype=inst[31:26];
endmodule
|
/*
--VGA Timing
--Horizontal :
-- ______________ _____________
-- | | |
--_______________| VIDEO |_______________| VIDEO (next line)
--___________ _____________________ ______________________
-- |_| |_|
-- B <-C-><----D----><-E->
-- <------------A--------->
--The Unit used below are pixels;
-- B->Sync_cycle :H_sync_cycle
-- C->Back_porch :hori_back
-- D->Visable Area
-- E->Front porch :hori_front
-- A->horizontal line total length :hori_line
--Vertical :
-- ______________ _____________
-- | | |
--______________| VIDEO |_______________| VIDEO (next frame)
--
--__________ _____________________ ______________________
-- |_| |_|
-- P <-Q-><----R----><-S->
-- <-----------O---------->
--The Unit used below are horizontal lines;
-- P->Sync_cycle :V_sync_cycle
-- Q->Back_porch :vert_back
-- R->Visable Area
-- S->Front porch :vert_front
-- O->vertical line total length :vert_line
*/
module vsg
(
input wire rst,
input wire clk,
output reg blank_n,
output reg hs,
output reg vs
);
// 640x480 visible resolution
parameter hori_line = 800;
parameter hori_back = 144;
parameter hori_front = 16;
parameter vert_line = 525;
parameter vert_back = 34;
parameter vert_front = 11;
parameter H_sync_cycle = 96;
parameter V_sync_cycle = 2;
reg [10:0] h_cnt;
reg [9:0] v_cnt;
wire c_hd, c_vd, c_blank_n;
wire h_valid, v_valid;
always @ (negedge clk, posedge rst) begin
if (rst) begin
h_cnt <= 0;
v_cnt <= 0;
end
else begin
if (h_cnt == hori_line - 1) begin
h_cnt <= 0;
if (v_cnt == vert_line - 1)
v_cnt <= 0;
else
v_cnt <= v_cnt + 1;
end
else
h_cnt <= h_cnt + 1;
end
end
assign c_hd = (h_cnt < H_sync_cycle) ? 0 : 1;
assign c_vd = (v_cnt < V_sync_cycle) ? 0 : 1;
assign h_valid = (h_cnt < (hori_line-hori_front) && h_cnt >= hori_back) ? 1 : 0;
assign v_valid = (v_cnt < (vert_line-vert_front) && v_cnt >= vert_back) ? 1 : 0;
assign c_blank_n = h_valid && v_valid;
always @ (negedge clk) begin
hs <= c_hd;
vs <= c_vd;
blank_n <= c_blank_n;
end
endmodule
|
// Jagadeesh Vasudevamurthy nes_top_X99.v
// Please do not remove the header
// Char array passed is as follows
//--------------------------------------
//0:000000 01101101
//1:000001 00100010
//2:000010 00000010
//3:000011 01000010
//4:000100 10000001
//5:000101 10100000
//6:000110 10100000
//7:000111 01100000
//8:001000 01000100
//9:001001 00001000
//10:001010 00001000
//11:001011 00000100
//12:001100 00000101
//13:001101 00000000
//14:001110 00000000
//15:001111 00000000
//16:010000 10110110
//17:010001 00001111
//18:010010 00100111
//19:010011 10000011
//20:010100 10100010
//21:010101 11100001
//22:010110 11000100
//23:010111 11001000
//24:011000 10001100
//25:011001 00010000
//26:011010 00010100
//27:011011 00010000
//28:011100 00010010
//29:011101 00000000
//30:011110 00000000
//31:011111 00000000
//32:100000 11111111
//33:100001 00110111
//34:100010 01010011
//35:100011 10110011
//36:100100 11101111
//37:100101 11101110
//38:100110 11101101
//39:100111 11110000
//40:101000 11110100
//41:101001 10011000
//42:101010 01011001
//43:101011 01011110
//44:101100 00011111
//45:101101 00000000
//46:101110 00000000
//47:101111 00000000
//48:110000 11111111
//49:110001 10111111
//50:110010 11011011
//51:110011 11011011
//52:110100 11111011
//53:110101 11111011
//54:110110 11110110
//55:110111 11111010
//56:111000 11111110
//57:111001 11111110
//58:111010 10111110
//59:111011 10111111
//60:111100 10011111
//61:111101 00000000
//62:111110 00000000
//63:111111 00000000
// default NOT given
// Parallel mux
//--------------------------------------
// PLA starts now
module nes_top_X99(a,o);
input[5:0] a;
output reg[7:0] o;
always @(a)
begin
case(a)
6'b000000: o = 8'b01101101;
6'b000001: o = 8'b00100010;
6'b000010: o = 8'b00000010;
6'b000011: o = 8'b01000010;
6'b000100: o = 8'b10000001;
6'b000101: o = 8'b10100000;
6'b000110: o = 8'b10100000;
6'b000111: o = 8'b01100000;
6'b001000: o = 8'b01000100;
6'b001001: o = 8'b00001000;
6'b001010: o = 8'b00001000;
6'b001011: o = 8'b00000100;
6'b001100: o = 8'b00000101;
6'b001101: o = 8'b00000000;
6'b001110: o = 8'b00000000;
6'b001111: o = 8'b00000000;
6'b010000: o = 8'b10110110;
6'b010001: o = 8'b00001111;
6'b010010: o = 8'b00100111;
6'b010011: o = 8'b10000011;
6'b010100: o = 8'b10100010;
6'b010101: o = 8'b11100001;
6'b010110: o = 8'b11000100;
6'b010111: o = 8'b11001000;
6'b011000: o = 8'b10001100;
6'b011001: o = 8'b00010000;
6'b011010: o = 8'b00010100;
6'b011011: o = 8'b00010000;
6'b011100: o = 8'b00010010;
6'b011101: o = 8'b00000000;
6'b011110: o = 8'b00000000;
6'b011111: o = 8'b00000000;
6'b100000: o = 8'b11111111;
6'b100001: o = 8'b00110111;
6'b100010: o = 8'b01010011;
6'b100011: o = 8'b10110011;
6'b100100: o = 8'b11101111;
6'b100101: o = 8'b11101110;
6'b100110: o = 8'b11101101;
6'b100111: o = 8'b11110000;
6'b101000: o = 8'b11110100;
6'b101001: o = 8'b10011000;
6'b101010: o = 8'b01011001;
6'b101011: o = 8'b01011110;
6'b101100: o = 8'b00011111;
6'b101101: o = 8'b00000000;
6'b101110: o = 8'b00000000;
6'b101111: o = 8'b00000000;
6'b110000: o = 8'b11111111;
6'b110001: o = 8'b10111111;
6'b110010: o = 8'b11011011;
6'b110011: o = 8'b11011011;
6'b110100: o = 8'b11111011;
6'b110101: o = 8'b11111011;
6'b110110: o = 8'b11110110;
6'b110111: o = 8'b11111010;
6'b111000: o = 8'b11111110;
6'b111001: o = 8'b11111110;
6'b111010: o = 8'b10111110;
6'b111011: o = 8'b10111111;
6'b111100: o = 8'b10011111;
6'b111101: o = 8'b00000000;
6'b111110: o = 8'b00000000;
6'b111111: o = 8'b00000000;
// defaults of ALL_0 and ALL_X are never routine to input pla. ALL_X,ALL_1 are expanded by me. Output never has default
// Parallel mux
endcase
end
endmodule
|
`timescale 1 ps / 1 ps
module system_top_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fmc_imageon_hdmii_clk,
fmc_imageon_hdmii_data,
fmc_imageon_iic_rst_b,
fmc_imageon_iic_scl_io,
fmc_imageon_iic_sda_io,
hdmio_int_b,
hdmio_clk,
hdmio_data,
hdmio_de,
hdmio_hsync,
hdmio_vsync,
video_clk_n,
video_clk_p);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input fmc_imageon_hdmii_clk;
input [15:0]fmc_imageon_hdmii_data;
output fmc_imageon_iic_rst_b;
inout fmc_imageon_iic_scl_io;
inout fmc_imageon_iic_sda_io;
input hdmio_int_b;
output hdmio_clk;
output [15:0]hdmio_data;
output hdmio_de;
output hdmio_hsync;
output hdmio_vsync;
input video_clk_n;
input video_clk_p;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire fmc_imageon_hdmii_clk;
wire [15:0]fmc_imageon_hdmii_data;
wire fmc_imageon_iic_rst_b;
wire fmc_imageon_iic_scl_i;
wire fmc_imageon_iic_scl_io;
wire fmc_imageon_iic_scl_o;
wire fmc_imageon_iic_scl_t;
wire fmc_imageon_iic_sda_i;
wire fmc_imageon_iic_sda_io;
wire fmc_imageon_iic_sda_o;
wire fmc_imageon_iic_sda_t;
wire hdmio_int_b;
wire hdmio_clk;
wire [15:0]hdmio_data;
wire hdmio_de;
wire hdmio_hsync;
wire hdmio_vsync;
wire video_clk_n;
wire video_clk_p;
wire video_clk;
wire video_clk_sys;
IBUFDS ibufds_i
(.I(video_clk_p),
.IB(video_clk_n),
.O(video_clk));
BUFG bufg_i
(.I(video_clk),
.O(video_clk_sys));
IOBUF fmc_imageon_iic_scl_iobuf
(.I(fmc_imageon_iic_scl_o),
.IO(fmc_imageon_iic_scl_io),
.O(fmc_imageon_iic_scl_i),
.T(fmc_imageon_iic_scl_t));
IOBUF fmc_imageon_iic_sda_iobuf
(.I(fmc_imageon_iic_sda_o),
.IO(fmc_imageon_iic_sda_io),
.O(fmc_imageon_iic_sda_i),
.T(fmc_imageon_iic_sda_t));
system_top system_top_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.fmc_imageon_hdmii_clk(fmc_imageon_hdmii_clk),
.fmc_imageon_hdmii_data(fmc_imageon_hdmii_data),
.fmc_imageon_iic_rst_b(fmc_imageon_iic_rst_b),
.fmc_imageon_iic_scl_i(fmc_imageon_iic_scl_i),
.fmc_imageon_iic_scl_o(fmc_imageon_iic_scl_o),
.fmc_imageon_iic_scl_t(fmc_imageon_iic_scl_t),
.fmc_imageon_iic_sda_i(fmc_imageon_iic_sda_i),
.fmc_imageon_iic_sda_o(fmc_imageon_iic_sda_o),
.fmc_imageon_iic_sda_t(fmc_imageon_iic_sda_t),
.hdmio_int_b(hdmio_int_b),
.hdmio_clk(hdmio_clk),
.hdmio_data(hdmio_data),
.hdmio_de(hdmio_de),
.hdmio_hsync(hdmio_hsync),
.hdmio_vsync(hdmio_vsync),
.video_clk(video_clk_sys));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_PP_SYMBOL_V
|
module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
oDIN,
oCS_n,
oSCLK,
iDOUT,
oADC_12_bit_channel_0,
oADC_12_bit_channel_1,
oADC_12_bit_channel_2,
oADC_12_bit_channel_3,
oADC_12_bit_channel_4,
oADC_12_bit_channel_5,
oADC_12_bit_channel_6,
oADC_12_bit_channel_7
);
input iRST;
input iCLK;
input iCLK_n;
input iGO;
output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;
output reg [11:0] oADC_12_bit_channel_0;
output reg [11:0] oADC_12_bit_channel_1;
output reg [11:0] oADC_12_bit_channel_2;
output reg [11:0] oADC_12_bit_channel_3;
output reg [11:0] oADC_12_bit_channel_4;
output reg [11:0] oADC_12_bit_channel_5;
output reg [11:0] oADC_12_bit_channel_6;
output reg [11:0] oADC_12_bit_channel_7;
reg [2:0] channel;
reg data;
reg go_en;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [31:0] adc_counter;
assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
always@( iCLK )//posedge iGO or posedge iRST)
begin
if(iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end
always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end
always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)
data <= channel[2];
else if (cont == 3)
data <= channel[1];
else if (cont == 4)
data <= channel[0];
else
data <= 0;
end
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
end
else
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
begin
if ( adc_counter < 32'd20 )
begin
adc_counter <= adc_counter + 1'b1;
end
else
begin
if (channel == 3'd0)
oADC_12_bit_channel_0 <= adc_data;
else if (channel == 3'd1)
oADC_12_bit_channel_1 <= adc_data;
else if (channel == 3'd2)
oADC_12_bit_channel_2 <= adc_data;
else if (channel == 3'd3)
oADC_12_bit_channel_3 <= adc_data;
else if (channel == 3'd4)
oADC_12_bit_channel_4 <= adc_data;
else if (channel == 3'd5)
oADC_12_bit_channel_5 <= adc_data;
else if (channel == 3'd6)
oADC_12_bit_channel_6 <= adc_data;
else if (channel == 3'd7)
oADC_12_bit_channel_7 <= adc_data;
adc_counter <= 32'd0;
channel <= channel + 1'b1;
end
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
wire toggle_up;
alpha a1 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
alpha a2 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle_up (toggle_up));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
reg [1:0] memory[121:110];
reg [1023:0] largeish;
// CHECK_COVER_MISSING(-1)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
if (cyc==4) begin
toggle <= '0;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module alpha (/*AUTOARG*/
// Outputs
toggle_up,
// Inputs
clk, toggle, cyc_copy
);
// t.a1 and t.a2 collapse to a count of 2
input clk;
input toggle;
// CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2)
input [7:0] cyc_copy;
// CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22)
// CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10)
// CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4)
// CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2)
// CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0)
// CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0)
// CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0)
// CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0)
reg toggle_internal;
// CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2)
output reg toggle_up;
// CHECK_COVER(-1,"top.v.a*",4)
// 2 edges * (t.a1 and t.a2)
always @ (posedge clk) begin
toggle_internal <= toggle;
toggle_up <= toggle;
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle_up
);
input clk;
input toggle_up;
// CHECK_COVER(-1,"top.v.b1","toggle_up",2)
/* verilator public_module */
always @ (posedge clk) begin
if (0 && toggle_up) begin end
end
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
// verilator coverage_off
input clk;
// CHECK_COVER_MISSING(-1)
// verilator coverage_on
input toggle;
// CHECK_COVER(-1,"top.v.o1","toggle",2)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 3e3 + 100; const long long inf = 0x3f3f3f3f; const long long iinf = 1 << 30; const long long linf = 2e18; const long long mod = 998244353; const double eps = 1e-7; template <class T = long long> T chmin(T &a, T b) { return a = min(a, b); } template <class T = long long> T chmax(T &a, T b) { return a = max(a, b); } template <class T = long long> inline void red(T &x) { x -= mod, x += x >> 31 & mod; } template <class T = long long> T read() { T f = 1, a = 0; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { a = (a << 3) + (a << 1) + ch - 0 ; ch = getchar(); } return a * f; } long long n, m, ans; char s[maxn], t[maxn]; long long f[maxn][maxn]; signed main() { scanf( %s %s , s + 1, t + 1); long long n = strlen(s + 1), m = strlen(t + 1); for (long long i = (1); i <= (n); ++i) f[i][i] = 2 * (i > m || s[1] == t[i]); for (long long i = (2); i <= (n); ++i) for (long long l = (1); l <= (n - i + 1); ++l) { long long r = l + i - 1; if (l > m || s[i] == t[l]) red(f[l][r] += f[l + 1][r]); if (r > m || s[i] == t[r]) red(f[l][r] += f[l][r - 1]); } for (long long i = (m); i <= (n); ++i) red(ans += f[1][i]); printf( %lld n , ans); return 0; }
|
// DSP48E1 - 7 Series DSP48E1 User Guide UG479 (v1.9) September 27, 2016
`ifndef PB_TYPE
`include "alu/alu.sim.v"
`include "alumode_mux/alumode_mux.sim.v"
`include "carryinsel_logic/carryinsel_logic.sim.v"
`include "carryinsel_mux/carryinsel_mux.sim.v"
`include "creg_mux/creg_mux.sim.v"
`include "dual_ad_preadder/dual_ad_preadder.sim.v"
`include "dual_b_reg/dual_b_reg.sim.v"
`include "inmode_mux/inmode_mux.sim.v"
`include "mult25x18/mult25x18.sim.v"
`include "mult_mux/mult_mux.sim.v"
`include "nreg/nreg.sim.v"
`include "opmode_mux/opmode_mux.sim.v"
`include "xmux/dsp48_xmux.sim.v"
`include "ymux/dsp48_ymux.sim.v"
`include "zmux/dsp48_zmux.sim.v"
`endif
// Figure 2-1: 7 Series FPGA DSP48E1 Slice
module DSP48E1(
A, B, C, D,
OPMODE,ALUMODE, CARRYIN, CARRYINSEL, INMODE,
CEA1, CEA2, CEB1, CEB2, CEC, CED, CEM, CEP, CEAD,
CEALUMODE, CECTRL, CECARRYIN, CEINMODE,
RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCTRL, RSTALLCARRYIN, RSTALUMODE, RSTINMODE,
CLK,
ACIN, BCIN, PCIN, CARRYCASCIN, MULTSIGNIN,
ACOUT, BCOUT, PCOUT, P, CARRYOUT, CARRYCASCOUT, MULTSIGNOUT, PATTERNDETECT, PATTERNBDETECT, OVERFLOW, UNDERFLOW
);
// Main inputs
input wire [29:0] A;
input wire [17:0] B;
input wire [47:0] C;
input wire [24:0] D;
input wire [6:0] OPMODE;
input wire [3:0] ALUMODE;
input wire CARRYIN;
input wire [2:0] CARRYINSEL;
input wire [4:0] INMODE;
// Clock enable for registers
input wire CEA1;
input wire CEA2;
input wire CEB1;
input wire CEB2;
input wire CEC;
input wire CED;
input wire CEM;
input wire CEP;
input wire CEAD;
input wire CEALUMODE;
input wire CECTRL;
input wire CECARRYIN;
input wire CEINMODE;
// Reset for registers
input wire RSTA;
input wire RSTB;
input wire RSTC;
input wire RSTD;
input wire RSTM;
input wire RSTP;
input wire RSTCTRL;
input wire RSTALLCARRYIN;
input wire RSTALUMODE;
input wire RSTINMODE;
// clock for all registers and flip-flops
input wire CLK;
// Interslice connections
input wire [29:0] ACIN;
input wire [17:0] BCIN;
input wire [47:0] PCIN;
input wire CARRYCASCIN;
input wire MULTSIGNIN;
output wire [29:0] ACOUT;
output wire [17:0] BCOUT;
output wire [47:0] PCOUT;
output wire [47:0] P;
// main outputs
output wire [3:0] CARRYOUT;
output wire CARRYCASCOUT;
output wire MULTSIGNOUT;
output wire PATTERNDETECT;
output wire PATTERNBDETECT;
output wire OVERFLOW;
output wire UNDERFLOW;
// wires for concatenating A and B registers to XMUX input
wire [47:0] XMUX_CAT;
wire [29:0] XMUX_A_CAT;
wire [17:0] XMUX_B_CAT;
// wires for multiplier inputs
wire [24:0] AMULT;
wire [17:0] BMULT;
`ifndef PB_TYPE
parameter ACASCREG = 1;
parameter ADREG = 1;
parameter ALUMODEREG = 1;
parameter AREG = 1;
parameter BCASCREG = 1;
parameter BREG = 1;
parameter CARRYINREG = 1;
parameter CARRYINSELREG = 1;
parameter CREG = 1;
parameter DREG = 1;
parameter INMODEREG = 1;
parameter MREG = 1;
parameter OPMODEREG = 1;
parameter PREG = 1;
parameter A_INPUT = "DIRECT";
parameter B_INPUT = "DIRECT";
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
parameter USE_SIMD = "ONE48";
parameter AUTORESET_PATDET = "NO_RESET";
parameter MASK = 001111111111111111111111111111111111111111111111;
parameter PATTERN = 000000000000000000000000000000000000000000000000;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter USE_PATTERN_DETECT = "NO_PATDET";
// Figure 2-10 OPMODE, ALUMODE, CARRYINSEL
wire [6:0] OPMODE_REG;
wire [6:0] OPMODE_MUX_OUT;
NREG #(.NBITS(7)) opmode_reg (.D(OPMODE), .Q(OPMODE_REG), .CE(CECTRL), .CLK(CLK), .RESET(RSTCTRL));
OPMODE_MUX #(.S(OPMODEREG)) opmode_mux (.BYPASS(OPMODE), .REG(OPMODE_REG), .O(OPMODE_MUX_OUT));
// ALUMODE register
wire [3:0] ALUMODE_REG;
wire [3:0] ALUMODE_MUX_OUT;
NREG #(.NBITS(4)) alu_reg (.D(ALUMODE), .Q(ALUMODE_REG), .CE(CEALUMODE), .CLK(CLK), .RESET(RSTALUMODE));
ALUMODE_MUX #(.S(ALUMODEREG)) alumode_mux (.BYPASS(ALUMODE), .REG(ALUMODE_REG), .O(ALUMODE_MUX_OUT));
wire [2:0] CARRYINSEL_REG;
wire [2:0] CARRYINSEL_MUX_OUT;
NREG #(.NBITS(3)) carryinsel_reg (.D(CARRYINSEL), .Q(CARRYINSEL_REG), .CE(CECTRL), .CLK(CLK), .RESET(RSTCTRL));
CARRYINSEL_MUX #(.S(CARRYINSELREG)) carryseling_mux (.BYPASS(CARRYSELIN), .REG(CARRYINSEL_REG), .O(CARRYINSEL_MUX_OUT));
wire CIN;
CARRYINSEL_LOGIC #(.MREG(MREG), .CARRYINREG(CARRYINREG)) carryinsel_logic (.CARRYIN(CARRYIN), .CARRYCASCIN(CARRYCASCIN), .CARRYCASCOUT(CARRYCASCOUT), .A(A), .B(B), .P(P), .PCIN(PCIN), .CARRYINSEL(CARRYINSEL), .CIN(CIN),
.RSTALLCARRYIN(RSTALLCARRYIN), .CECARRYIN(CECARRYIN), .CEM(CEM), .CLK(CLK));
// INMODE register and bypass mux
wire [4:0] INMODE_REG;
wire [4:0] INMODE_MUX_OUT;
NREG #(.NBITS(5)) inmode_reg (.D(INMODE), .Q(INMODE_REG), .CE(CEINMODE), .CLK(CLK), .RESET(RSTINMODE));
INMODE_MUX #(.S(INMODEREG)) inmode_mux(.BYPASS(INMODE), .REG(INMODE_REG), .O(INMODE_MUX_OUT));
// input register blocks for A, B, D
DUAL_AD_PREADDER dual_ad_preadder (.A(A), .ACIN(ACIN), .D(D), .INMODE(INMODE_MUX_OUT),
.ACOUT(ACOUT), .XMUX(XMUX_A_CAT), .AMULT(AMULT),
.CEA1(CEA1), .CEA2(CEA2), .RSTA(RSTA), .CED(CED), .CEAD(CEAD), .RSTD(RSTD), .CLK(CLK));
DUAL_B_REG dualb_reg (.B(B), .BCIN(BCIN), .INMODE(INMODE_MUX_OUT),
.BCOUT(BCOUT), .XMUX(XMUX_B_CAT), .BMULT(BMULT),
.CEB1(CEB1), .CEB2(CEB2), .RSTB(RSTB), .CLK(CLK));
// concatenate for XMUX
assign XMUX_CAT = {XMUX_A_CAT, XMUX_B_CAT};
// Multiplier output
wire [85:0] MULT_OUT;
wire [85:0] MULT_REG;
wire [85:0] MULT_MUX_OUT;
// 25bit by 18bit multiplier
MULT25X18 mult25x18 (.A(AMULT), .B(BMULT), .OUT(MULT_OUT));
NREG #(.NBITS(86)) mult_reg (.D(MULT_OUT), .Q(MULT_REG), .CLK(CLK), .CE(CEM), .RESET(RSTM));
MULT_MUX #(.S(MREG)) mult_mux (.BYPASS(MULT_OUT), .REG(MULT_REG), .O(MULT_MUX_OUT));
// Figure 2-9
wire [47:0] C_REG;
wire [47:0] CMUX_OUT;
NREG #(.NBITS(48)) creg (.D(C), .Q(C_REG), .CLK(CLK), .CE(CEC), .RESET(RSTC));
CREG_MUX #(.S(CREG)) creg_mux (.BYPASS(C), .REG(C_REG), .O(CMUX_OUT));
// signals from muxes to ALU unit
wire [47:0] X;
wire [47:0] Y;
wire [47:0] Z;
// TODO(elmsfu): take in full OPMODE to check for undefined behaviors
// See table 2-7 for X mux selection
DSP48_XMUX dsp48_xmux (.ZEROS(48'h000000000000), .M({5'b00000, MULT_MUX_OUT[85:43]}), .P(P), .AB_CAT(XMUX_CAT), .S(OPMODE_MUX_OUT[1:0]), .O(X));
// See table 2-8 for Y mux selection
DSP48_YMUX dsp48_ymux (.ZEROS(48'h000000000000), .M({5'b00000, MULT_MUX_OUT[42:0]}), .ONES(48'hFFFFFFFFFFFF), .C(CMUX_OUT), .S(OPMODE_MUX_OUT[3:2]), .O(Y));
// See table 2-9 for Z mux selection
// Note: Z mux actually has 7 inputs but 2 and 4 are both P
DSP48_ZMUX dsp48_zmux (.ZEROS(48'h000000000000), .PCIN(PCIN), .P(P), .C(CMUX_OUT), .P2(P), .PCIN_UPSHIFT({ {17{PCIN[47]}}, PCIN[47:17]}), .P_UPSHIFT({ {17{P[47]}}, P[47:17]}), .S(OPMODE_MUX_OUT[6:4]), .O(Z));
// See table 2-10 for 3 input behavior
// See table 2-13 for 2 input behavior
ALU alu (.X(X), .Y(Y), .Z(Z), .ALUMODE(ALUMODE_MUX_OUT), .CARRYIN(CIN), .MULTSIGNIN(MULTSIGNIN), .OUT(P), .CARRYOUT(CARRYOUT), .MULTSIGNOUT(MULTSIGNOUT));
assign PCOUT = P;
`endif // `ifndef PB_TYPE
endmodule // DSP48E1
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } } int fr[100005], to[100005 << 1], ne[100005 << 1], x[100005]; int a[100005], b[100005], l, r; int n, m; int flag; int c, d, e; inline void dfs(int w) { for (int u = fr[w]; u; u = ne[u]) if (!x[to[u]]) { x[to[u]] = 3 - x[w]; dfs(to[u]); } else if (x[w] == x[to[u]]) flag = 1; } int main() { read(n); read(m); for (int i = 1; i <= m; ++i) { read(c); read(d); to[++e] = d; ne[e] = fr[c]; fr[c] = e; to[++e] = c; ne[e] = fr[d]; fr[d] = e; } flag = 0; for (int i = 1; i <= n; ++i) if (!x[i]) { x[i] = 1; dfs(i); } if (flag) printf( -1 n ); else { for (int i = 1; i <= n; ++i) if (x[i] == 1) a[++l] = i; else b[++r] = i; printf( %d n , l); for (int i = 1; i <= l; ++i) printf( %d%c , a[i], i < l ? : n ); printf( %d n , r); for (int i = 1; i <= r; ++i) printf( %d%c , b[i], i < r ? : n ); } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module time_sender
(input clk, input rst,
input [63:0] vita_time,
input send_sync,
output reg exp_time_out);
reg [7:0] datain;
reg k;
wire [9:0] dataout;
reg [9:0] dataout_reg;
reg disp_reg;
wire disp, new_word;
reg [4:0] state;
reg [3:0] bit_count;
encode_8b10b encode_8b10b
(.datain({k,datain}),.dispin(disp_reg),
.dataout(dataout),.dispout(disp));
always @(posedge clk)
if(rst)
disp_reg <= 0;
else if(new_word)
disp_reg <= disp;
always @(posedge clk)
if(rst)
dataout_reg <= 0;
else if(new_word)
dataout_reg <= dataout;
else
dataout_reg <= {1'b0,dataout_reg[9:1]};
always @(posedge clk)
exp_time_out <= dataout_reg[0];
assign new_word = (bit_count == 9);
always @(posedge clk)
if(rst)
bit_count <= 0;
else if(new_word | send_sync)
bit_count <= 0;
else
bit_count <= bit_count + 1;
localparam SEND_IDLE = 0;
localparam SEND_HEAD = 1;
localparam SEND_T0 = 2;
localparam SEND_T1 = 3;
localparam SEND_T2 = 4;
localparam SEND_T3 = 5;
localparam SEND_T4 = 6;
localparam SEND_T5 = 7;
localparam SEND_T6 = 8;
localparam SEND_T7 = 9;
localparam SEND_TAIL = 10;
localparam COMMA = 8'hBC;
localparam HEAD = 8'h3C;
localparam TAIL = 8'hF7;
reg [63:0] vita_time_reg;
always @(posedge clk)
if(rst)
vita_time_reg <= 0;
else if(send_sync)
vita_time_reg <= vita_time;
always @(posedge clk)
if(rst)
begin
{k,datain} <= 0;
state <= SEND_IDLE;
end
else
if(send_sync)
state <= SEND_HEAD;
else if(new_word)
case(state)
SEND_IDLE :
{k,datain} <= {1'b1,COMMA};
SEND_HEAD :
begin
{k,datain} <= {1'b1, HEAD};
state <= SEND_T0;
end
SEND_T0 :
begin
{k,datain} <= {1'b0, vita_time_reg[63:56] };
state <= SEND_T1;
end
SEND_T1 :
begin
{k,datain} <= {1'b0, vita_time_reg[55:48]};
state <= SEND_T2;
end
SEND_T2 :
begin
{k,datain} <= {1'b0, vita_time_reg[47:40]};
state <= SEND_T3;
end
SEND_T3 :
begin
{k,datain} <= {1'b0, vita_time_reg[39:32]};
state <= SEND_T4;
end
SEND_T4 :
begin
{k,datain} <= {1'b0, vita_time_reg[31:24]};
state <= SEND_T5;
end
SEND_T5 :
begin
{k,datain} <= {1'b0, vita_time_reg[23:16]};
state <= SEND_T6;
end
SEND_T6 :
begin
{k,datain} <= {1'b0, vita_time_reg[15:8]};
state <= SEND_T7;
end
SEND_T7 :
begin
{k,datain} <= {1'b0, vita_time_reg[7:0]};
state <= SEND_TAIL;
end
SEND_TAIL :
begin
{k,datain} <= {1'b1, TAIL};
state <= SEND_IDLE;
end
default :
state <= SEND_IDLE;
endcase // case(state)
endmodule // time_sender
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : alu.v
// KEYWORDS : arithmetic, logic, alu, dlx
// -----------------------------------------------------------------------------
// PURPOSE : Provide logical and arithmetical opperations.
// -----------------------------------------------------------------------------
module alu
#(
parameter DATA_WIDTH = 'd32,
parameter OPCODE_WIDTH = 6,
parameter FUNCTION_WIDTH = 6,
parameter PC_WIDTH = 'd32,
parameter FLAGS_WIDTH = 4
)
(
input clk,
input rst_n,
input en,
input [DATA_WIDTH-1:0] alu_data_a_in, // Input data from register file port A
input [DATA_WIDTH-1:0] alu_data_b_in, // Input data from register file port A
input [OPCODE_WIDTH-1:0] alu_opcode_in, // Instruction opcode
input [FUNCTION_WIDTH-1:0] alu_function_in, // Instruction function
input [PC_WIDTH-1:0] pc_in,
output reg alu_branch_result_out,
output [DATA_WIDTH-1:0] alu_data_out, // ALU output result data
output [DATA_WIDTH-1:0] hi_data_out
);
reg [DATA_WIDTH:0] alu_result_reg;
reg [DATA_WIDTH-1:0] hi_result_reg;
reg flag_over_underflow;
reg flag_above;
reg flag_equal;
reg flag_error;
reg [FLAGS_WIDTH-1:0] flags_reg;
`include "opcodes.v"
wire [DATA_WIDTH-1:0] sum_result;
wire [DATA_WIDTH-1:0] sub_result;
wire [DATA_WIDTH-1:0] and_result;
wire [DATA_WIDTH-1:0] or_result;
wire [2*DATA_WIDTH-1:0] mult_result;
wire [DATA_WIDTH-1:0] div_result;
wire [DATA_WIDTH-1:0] mod_result;
assign sum_result = alu_data_a_in + alu_data_b_in;
assign sub_result = alu_data_a_in - alu_data_b_in;
assign and_result = alu_data_a_in & alu_data_b_in;
assign or_result = alu_data_a_in | alu_data_b_in;
assign zero_cmp = alu_data_a_in == {DATA_WIDTH{1'b0}};
assign mult_result = alu_data_a_in*alu_data_b_in;
assign div_result = alu_data_a_in/alu_data_b_in;
assign mod_result = alu_data_a_in%alu_data_b_in;
assign alu_data_out = alu_result_reg;
assign hi_data_out = hi_result_reg;
always@(*)
begin
alu_result_reg = {DATA_WIDTH{1'b0}};
hi_result_reg = {DATA_WIDTH{1'b0}};
if(alu_opcode_in == R_TYPE_OPCODE)begin
case (alu_function_in)
ADD_FUNCTION :
alu_result_reg = sum_result;
SUB_FUNCTION, CMP_FUNCTION :
alu_result_reg = sub_result;
AND_FUNCTION :
alu_result_reg = and_result;
OR_FUNCTION :
alu_result_reg = or_result;
MULT_FUNCTION : begin
alu_result_reg = mult_result[15:0];
hi_result_reg = mult_result[31:16];
end
DIV_FUNCTION : begin
alu_result_reg = div_result[15:0];
hi_result_reg = mod_result[31:16];
end
// CMP_FUNCTION :
// alu_result_reg = alu_data_a_in - alu_data_b_in;
NOT_FUNCTION :
alu_result_reg = ~alu_data_b_in;
JALR_FUNCTION :
alu_result_reg = pc_in;
default :
alu_result_reg = {DATA_WIDTH{1'b0}};
endcase
end
else begin
case (alu_opcode_in)
ADDI_OPCODE,LW_OPCODE,SW_OPCODE:
alu_result_reg = sum_result;
SUBI_OPCODE :
alu_result_reg = sub_result;
ANDI_OPCODE :
alu_result_reg = and_result;
ORI_OPCODE :
alu_result_reg = or_result;
// JAL_OPCODE, JALR_OPCODE, CALL_OPCODE :
JAL_OPCODE, CALL_OPCODE :
alu_result_reg = pc_in;
default :
alu_result_reg = {DATA_WIDTH{1'b0}};
endcase
end
end
always@(*) begin
case (alu_opcode_in)
BEQZ_OPCODE :
alu_branch_result_out = zero_cmp;
BNEZ_OPCODE :
alu_branch_result_out = ~zero_cmp;
BRFL_OPCODE :
alu_branch_result_out = flags_reg == alu_data_b_in[3:0];
default :
alu_branch_result_out = {DATA_WIDTH{1'b0}};
endcase
end
// ---------------------------------------------------------
// Flag Setup
// ---------------------------------------------------------
always@(*)
begin
flag_over_underflow = 1'b0;
flag_above = 1'b0;
flag_equal = 1'b0;
flag_error = 1'b0;
if(alu_opcode_in == R_TYPE_OPCODE) begin
case (alu_function_in)
ADD_FUNCTION,SUB_FUNCTION,MULT_FUNCTION,DIV_FUNCTION :
begin
// Test overflow for arithmetic functions
if(alu_data_a_in[DATA_WIDTH-1] == alu_data_b_in[DATA_WIDTH-1] && alu_result_reg[DATA_WIDTH-1] != alu_data_a_in[DATA_WIDTH-1]) begin
flag_over_underflow = 1'b1;
end
if(alu_opcode_in == DIV_FUNCTION) begin
if(alu_data_b_in == {DATA_WIDTH{1'b0}}) begin
flag_error = 1'b1;
end
end
end
CMP_FUNCTION :
begin
if(alu_result_reg == {DATA_WIDTH{1'b0}}) begin
flag_equal = 1'b1;
end
// Missing tests if operators have different signals
if(alu_data_a_in > alu_data_b_in && alu_data_a_in[15] == alu_data_b_in[15]) begin
flag_above = 1'b1;
end
end
default :
flag_error = 1'b1;
endcase
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
flags_reg <= {FLAGS_WIDTH{1'b0}};
end else if(en)
flags_reg <= {flag_over_underflow,flag_above,flag_equal,flag_error};
end
endmodule
|
`timescale 1ns / 1ps
/*
* Spartan3AN_PicoBlaze_Leds.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/07/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : XC3S700AN - 4FGG484
* Board : Spartan-3AN Starter Kit.
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 19/06/2015.
*/
//////////////////////////////////////////////////////////////////////////////////
module Spartan3AN_PicoBlaze_Leds(
//////////// CLOCK //////////
CLK_50M,
//////////// LED //////////
LED
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter PORTA_ID = 8'h00;
//=======================================================
// PORT declarations
//=======================================================
input wire CLK_50M;
output wire [7:0] LED;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [7:0] portA;
//=======================================================
// Structural coding
//=======================================================
//******************************************************************//
// Instantiate PicoBlaze and the Program ROM. //
//******************************************************************//
wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire write_strobe;
wire read_strobe;
wire interrupt;
wire reset;
kcpsm3 kcpsm3_inst (
.address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(),
.reset(reset),
.clk(CLK_50M));
picocode picocode_inst (
.address(address),
.instruction(instruction),
.clk(CLK_50M));
PicoBlaze_OutReg #(.LOCAL_PORT_ID(PORTA_ID)) portA_inst(
.clk(CLK_50M),
.reset(reset),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.new_out_port(portA));
//=======================================================
// Connections & assigns
//=======================================================
//******************************************************************//
// Input PicoBlaze Interface. //
//******************************************************************//
assign in_port = 8'h00;
assign interrupt = 1'b0;
assign reset = 1'b0;
//******************************************************************//
// Output PicoBlaze Interface. //
//******************************************************************//
assign LED = portA;
endmodule
|
module sevenseg
(
input wire clk,
input wire rstn,
input wire [7:0] display_0,
input wire [7:0] display_1,
input wire [7:0] display_2,
input wire [7:0] display_3,
input wire [1:0] decplace,
output reg [7:0] seg,
output reg [3:0] an
);
// CHARACTERS Hgfedcba
localparam NUM_0 = 8'b11000000;
localparam NUM_1 = 8'b11111001;
localparam NUM_2 = 8'b10100100;
localparam NUM_3 = 8'b10110000;
localparam NUM_4 = 8'b10011001;
localparam NUM_5 = 8'b10010010;
localparam NUM_6 = 8'b10000010;
localparam NUM_7 = 8'b11111000;
localparam NUM_8 = 8'b10000000;
localparam NUM_9 = 8'b10010000;
localparam CHAR_A = 8'b10001000;
localparam CHAR_B = 8'b10000011;
localparam CHAR_C = 8'b11000110;
localparam CHAR_D = 8'b10100001;
localparam CHAR_E = 8'b10000110;
localparam CHAR_F = 8'b10001110;
localparam CHAR_G = 8'b10000010; // 6
localparam CHAR_H = 8'b10001001;
localparam CHAR_K = 8'b10001111;
localparam CHAR_L = 8'b11000111;
localparam CHAR_o = 8'b10100011;
localparam CHAR_S = 8'b10010010; // 5
localparam CHAR_T = 8'b11111000; // 7
localparam CHAR_P = 8'b10001100;
localparam SPACE = 8'b11111111;
localparam HYPHEN = 8'b10111111;
localparam UNDERLINE = 8'b11110111;
localparam OVERRLINE = 8'b11111110;
reg [16:0] cnt;
reg [7:0] digit;
// Anode
always @(cnt[16:15]) begin
case (cnt[16:15])
2'b11: an <= 4'b1110;
2'b10: an <= 4'b1101;
2'b01: an <= 4'b1011;
default: an <= 4'b0111;
endcase
end
// Cathode
always @(cnt[16:15] or display_0 or display_1 or display_2 or display_3) begin
case (cnt[16:15])
2'b00: digit <= display_0;
2'b01: digit <= display_1;
2'b10: digit <= display_2;
default: digit <= display_3;
endcase
// TODO: Add missing/required characters here
case (digit)
8'h20: seg <= SPACE;
8'h2d: seg <= HYPHEN;
//
8'h30: seg <= NUM_0;
8'h31: seg <= NUM_1;
8'h32: seg <= NUM_2;
8'h33: seg <= NUM_3;
8'h34: seg <= NUM_4;
8'h35: seg <= NUM_5;
8'h36: seg <= NUM_6;
8'h37: seg <= NUM_7;
8'h38: seg <= NUM_8;
8'h39: seg <= NUM_9;
//
8'h41: seg <= CHAR_A;
8'h43: seg <= CHAR_C;
8'h45: seg <= CHAR_E;
8'h47: seg <= CHAR_G;
8'h48: seg <= CHAR_H;
8'h4b: seg <= CHAR_K;
8'h4c: seg <= CHAR_L;
8'h50: seg <= CHAR_P;
8'h53: seg <= CHAR_S;
//
8'h5f: seg <= UNDERLINE;
//
8'h6f: seg <= CHAR_o;
default: seg <= OVERRLINE;
endcase
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 0;
end
else
cnt <= cnt + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 2e5 + 5; vector<int> v(MX); struct Q { int t, l, r; }; vector<Q> qs(MX); int n, q, m, p; int main() { cin >> n >> q >> m; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i <= q; i++) cin >> qs[i].t >> qs[i].l >> qs[i].r; while (m--) { cin >> p; for (int i = q; i > 0; i--) { if (p < qs[i].l || p > qs[i].r) continue; if (qs[i].t == 1) { p--; if (p < qs[i].l) p = qs[i].r; } else p = qs[i].r - (p - qs[i].l); } cout << v[p] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { set<int> s; long long int n, m, k, a; cin >> n >> m; while (n--) { cin >> k; while (k--) { cin >> a; s.insert(a); } } if (s.size() == m) { cout << YES << n ; } else { cout << NO << n ; } return 0; }
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int n, s[1000006], top, a[1000006]; int solve(int n, int mul) { if (n == 1) return s[++top] = mul; if (n == 2) return s[++top] = mul, s[++top] = mul * 2; if (n == 3) return s[++top] = mul, s[++top] = mul, s[++top] = mul * 3; for (int i = 1; i <= (n - n / 2); i++) s[++top] = mul; for (int i = 1; i <= n / 2; i++) a[i] = a[i * 2] / 2; solve(n / 2, mul << 1); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) a[i] = i; solve(n, 1); for (int i = 1; i <= n; i++) printf( %d , s[i]); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, a, b; cin >> a >> b >> n; if (n % 2 == 0) cout << (n / 2) * (a - b) << endl; else cout << ((n / 2) * (a - b)) + a << endl; } return 0; }
|
// Module m_2to1_8bit_mux is a dual 2 to 1 multiplexer. When w_channel is HIGH,
// w_bus_mux_in_1 bus is selected. When w_channel is LOW, w_bus_mux_in_0 bus is selected.
module m_2to1_8bit_mux (w_bus_mux_out, w_bus_mux_in_0, w_bus_mux_in_1, w_channel);
output [7:0] w_bus_mux_out;
input [7:0] w_bus_mux_in_0, w_bus_mux_in_1;
input w_channel;
assign w_bus_mux_out = (w_channel) ? w_bus_mux_in_1 : w_bus_mux_in_0;
endmodule
// Module m_2to1_8bit_mux_with_add1 is a dual 2 to 1 multiplexer. When w_channel is HIGH,
// w_bus_mux_in_1 bus is selected, adding 1 to its value. When w_channel is LOW,
// w_bus_mux_in_0 bus is selected.
module m_2to1_8bit_mux_with_add1 (w_bus_mux_out, w_bus_mux_in_0, w_bus_mux_in_1, w_channel);
output [7:0] w_bus_mux_out;
input [7:0] w_bus_mux_in_0, w_bus_mux_in_1;
input w_channel;
assign w_bus_mux_out = (w_channel) ? (w_bus_mux_in_1 + 1) : w_bus_mux_in_0;
endmodule
// Module m_2to1_8bit_demux is a 1 to 2 demultiplexer. When w_channel
// is HIGH, w_bus_demux_out_1 takes the value of w_bus_demux_in, while
// the high impedance state is output to w_bus_demux_out_0. When
// w_channel is LOW, w_bus_demux_out_0 takes the value of w_bus_demux_in,
// while the high impedance state is output to w_bus_demux_out_1.
module m_1to2_8bit_demux (w_bus_demux_out_0, w_bus_demux_out_1, w_bus_demux_in, w_channel);
output [7:0] w_bus_demux_out_0, w_bus_demux_out_1;
input [7:0] w_bus_demux_in;
input w_channel;
assign w_bus_demux_out_0 = (w_channel) ? 8'bzzzzzzzz : w_bus_demux_in;
assign w_bus_demux_out_1 = (w_channel) ? w_bus_demux_in : 8'bzzzzzzzz;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n; cin >> a >> b >> n; cout << min(b, n) - n + min(a, n) + 1 << n ; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { int a, b, n, krok = 0; cin >> a >> b >> n; bool podm = false; int g; while (n > 0) { if (krok % 2 == 0) { g = gcd(a, n); n -= g; podm = true; } else { g = gcd(b, n); n -= g; podm = false; } krok++; } if (podm) cout << 0 << endl; else cout << 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; multiset<int> val[33]; long long sum[33]; int n = 0; int calc() { long long allsum = 0; int res = 0; for (int i = 0; i < 30; i++) { if (val[i].empty()) continue; if (allsum * 2 < *(val[i].begin())) res++; allsum += sum[i]; } return res; } int main() { int q; scanf( %d , &q); while (q--) { char s[2]; int x; scanf( %s%d , s, &x); int mn = 0; for (int i = 0; i < 30; i++) if (x >> i & 1) mn = i; if (s[0] == - ) { n--; sum[mn] -= x; val[mn].erase(val[mn].find(x)); } else { sum[mn] += x; val[mn].insert(x); n++; } printf( %d n , n - calc()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct FenwickTree { vector<long long int> bit; int n; FenwickTree(int n) { this->n = n; bit.assign(n, 0); } FenwickTree(vector<long long int> a) : FenwickTree(a.size()) { for (size_t i = 0; i < a.size(); i++) add(i, a[i]); } long long int sum(int r) { long long int ret = 0; for (; r >= 0; r = (r & (r + 1)) - 1) ret += bit[r]; return ret; } long long int sum(int l, int r) { return sum(r) - sum(l - 1); } void add(int idx, long long int delta) { for (; idx < n; idx = idx | (idx + 1)) bit[idx] += delta; } }; const int MAX_VAL = 3e5; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long int> a(n); vector<long long int> ra(MAX_VAL + 5, -1); for (int i = 0; i < n; ++i) { cin >> a[i]; ra[a[i]] = i; } vector<long long int> tr(n); vector<long long int> ctr(MAX_VAL + 5); int cidx = 0; for (int i = 1; i <= MAX_VAL; ++i) { if (ra[i] != -1) { tr[ra[i]] = cidx; cidx++; } ctr[i] = cidx - 1; } long long int csum = 0; long long int tsum = 0; FenwickTree fw(n); FenwickTree fw2(n); for (int i = 0; i < n; ++i) { csum += tsum + a[i] * fw2.sum(tr[i]); for (long long int k = 1; k * k <= a[i]; ++k) { csum -= fw.sum(ctr[a[i] / k]); if (a[i] / k > k) { csum -= (a[i] / k - a[i] / (k + 1)) * fw.sum(ctr[k]); } } for (long long int k = 2; k * a[i] <= MAX_VAL; ++k) { csum -= a[i] * (i - fw2.sum(ctr[k * a[i] - 1])); } cout << csum << ; tsum += a[i]; fw.add(tr[i], a[i]); fw2.add(tr[i], 1); } cout << endl; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
finalproject_cpu_jtag_debug_module_tck the_finalproject_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
finalproject_cpu_jtag_debug_module_sysclk the_finalproject_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic finalproject_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam finalproject_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// finalproject_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// finalproject_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// finalproject_cpu_jtag_debug_module_phy.sld_sim_action = "",
// finalproject_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_type_id = 34,
// finalproject_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_BLACKBOX_V
|
// soc_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* Testbench: arbiter
*
* Created: Sat Jun 1 19:01:54 EDT 2013
*
* Author: Berin Martini ()
*/
`timescale 1ns/10ps
`define TB_VERBOSE
//`define VERBOSE
//`define DEBUG_CONVOLVER
`include "arbiter.v"
module arbiter_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk;
always #1 clk = !clk;
//always #10 s_clk = !s_clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_header();
always @(end_trigger) display_header();
// And strobe signals at each clk
always @(posedge clk) display_signals();
`endif
// initial begin
// $dumpfile("result.vcd"); // Waveform file
// $dumpvars;
// end
/**
* Local parameters
*/
localparam NUM_PORTS = 9;
localparam SEL_WIDTH = ((NUM_PORTS > 1) ? $clog2(NUM_PORTS) : 1);
`ifdef TB_VERBOSE
initial $display("Testbench for unit 'arbiter'");
`endif
/**
* signals, registers and wires
*/
reg rst;
reg [NUM_PORTS-1:0] request;
wire [NUM_PORTS-1:0] grant;
wire [SEL_WIDTH-1:0] select;
wire active;
/**
* Unit under test
*/
arbiter #(
.NUM_PORTS (NUM_PORTS))
uut (
.clk (clk),
.rst (rst),
.request (request),
.grant (grant),
.select (select),
.active (active)
);
/**
* Wave form display
*/
task display_signals;
$display(
"%d\t%d",
$time, rst,
"\t%b\t%b\t%b",
request,
grant,
active,
"\t%d",
select,
);
endtask // display_signals
task display_header;
$display(
"\t\ttime\trst",
);
endtask
/**
* Testbench program
*/
initial begin
// init values
clk = 0;
rst = 0;
request = 1'b0;
//end init
`ifdef TB_VERBOSE
$display("RESET");
`endif
repeat(10) @(posedge clk);
rst <= 1'b1;
repeat(10) @(posedge clk);
rst <= 1'b0;
repeat(20) @(posedge clk);
`ifdef TB_VERBOSE
$display("TEST different ports request priority");
`endif
request = 9'b100000001;
repeat(15) @(posedge clk);
request = 9'b000000010;
repeat(15) @(posedge clk);
request = 9'b010000001;
repeat(15) @(posedge clk);
request = 9'b000000001;
@(posedge clk);
request = 9'b010000001;
repeat(15) @(posedge clk);
request = 9'b010000000;
repeat(5) @(posedge clk);
request = 9'b010000100;
repeat(10) @(posedge clk);
request = 9'b000000100;
repeat(15) @(posedge clk);
request = 9'b000100000;
repeat(15) @(posedge clk);
request = 9'b000000000;
@(posedge clk);
request = 9'b000100000;
repeat(10) @(posedge clk);
`ifdef TB_VERBOSE
$display("TEST when all ports request priority");
`endif
request = 9'b111111111;
repeat(10) @(posedge clk);
request = 9'b111011111;
@(posedge clk);
request = 9'b111111111;
repeat(10) @(posedge clk);
request = 9'b110111111;
@(posedge clk);
request = 9'b111111111;
repeat(10) @(posedge clk);
request = 9'b101111111;
@(posedge clk);
request = 9'b111111111;
repeat(10) @(posedge clk);
request = 9'b011111111;
@(posedge clk);
request = 9'b111111111;
repeat(10) @(posedge clk);
@(posedge clk);
`ifdef TB_VERBOSE
$display("END");
`endif
-> end_trigger;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, L, a; int t[N], l[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); srand(time(NULL)); cin >> n >> L >> a; int res = 0; for (int i = 1; i <= n; i++) { cin >> t[i] >> l[i]; int len = t[i] - (t[i - 1] + l[i - 1]); res += len / a; } res += (L - (t[n] + l[n])) / a; cout << res; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2000; int n, m, k, t, a[MAX_N + 1], b[MAX_N + 1], p[MAX_N + 1]; vector<int> x; vector<int> y; int main() { int i, j, ans = 0; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , a + i); for (i = 1; i <= n; i++) scanf( %d , b + i), p[b[i]] = i; for (i = 1; i <= n; i++) { for (k = i;; k++) if (p[a[k]] == i) break; while (k != i) { for (j = i; j <= k; j++) if (p[a[j]] >= k) { x.push_back(k); y.push_back(j); ans += k - j; swap(a[j], a[k]); k = j; } } } printf( %d n%d n , ans, x.size()); for (i = 0; i < x.size(); i++) printf( %d %d n , x[i], y[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A211OI_PP_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005; struct tr { int l, r, c, p; } a[maxn], b[maxn]; int n, k, m, maxr = 0; long long ans = 0, num[maxn << 2], sum[maxn << 2]; bool cmpl(tr a, tr b) { return a.l < b.l; } bool cmpr(tr a, tr b) { return a.r < b.r; } void update(int o, int l, int r, int c, int p) { if (l == r) { num[o] += c; sum[o] += 1LL * c * l; return; } int mid = (l + r) >> 1; if (p <= mid) update(o << 1, l, mid, c, p); else update(o << 1 | 1, mid + 1, r, c, p); num[o] = num[o << 1] + num[o << 1 | 1]; sum[o] = sum[o << 1] + sum[o << 1 | 1]; } long long query(int o, int l, int r, int p) { if (l == r) { if (p <= num[o]) return 1LL * l * p; return sum[o]; } int mid = (l + r) >> 1; if (num[o << 1] >= p) return query(o << 1, l, mid, p); return query(o << 1 | 1, mid + 1, r, p - num[o << 1]) + sum[o << 1]; } int main() { scanf( %d%d%d , &n, &k, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d%d , &a[i].l, &a[i].r, &a[i].c, &a[i].p); b[i] = a[i]; } for (int i = 1; i <= m; i++) maxr = max(maxr, a[i].p); sort(a + 1, a + m + 1, cmpl); sort(b + 1, b + m + 1, cmpr); for (int i = 1, j = 1, o = 1; i <= n; i++) { while (j <= m && a[j].l == i) update(1, 1, maxr, a[j].c, a[j].p), j++; ans += query(1, 1, maxr, k); while (o <= m && b[o].r == i) update(1, 1, maxr, -b[o].c, b[o].p), o++; } printf( %lld , ans); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/system_vga_sync_ref_1_0_stub.v
// Design : system_vga_sync_ref_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_1_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Q = 1e9 + 7; long long poww(long long a, long long b) { long long x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y); if (x > Q) x %= Q; } y = (y * y); if (y > Q) y %= Q; b /= 2; } return x; } long long C[52][52]; void binomialCoeff() { long long i, j; for (i = 0; i <= 50; i++) { for (j = 0; j <= 50; j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } } } int main() { long long n, m, k; cin >> n >> m >> k; long long ans = 0; if (m == 1) { ans = 1; } else if (k == 1 || k > n) { ans = poww(m, n); } else if (n == k) { ans = poww(m, (k + 1) / 2); ans %= Q; } else if (k % 2 != 0) { ans = m * m; ans %= Q; } else { ans = m; ans %= Q; } ans %= Q; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int MAX = 200002; int arr[MAX]; int cnt[MAX]; int main() { int n, wrong = 0; cin >> n; for (int i = (1); i <= (n); i++) { cin >> arr[i]; } string s; cin >> s; cnt[1] = s[0] - 0 ; for (int i = (2); i <= (n); i++) { cnt[i] = s[i - 1] - 0 ; cnt[i] += cnt[i - 1]; } bool yes = 1; for (int i = (1); i <= (n); i++) { if (arr[i] != i) { int has = 0; if (arr[i] > i) has = cnt[arr[i] - 1] - cnt[i - 1]; else has = cnt[i - 1] - cnt[arr[i] - 1]; if (has < abs(arr[i] - i)) { yes = 0; break; } } } if (yes) cout << YES n ; else cout << NO n ; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_axi_spi_master_1_0 -prefix
// DemoInterconnect_axi_spi_master_1_0_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_axi_spi_master_1_0(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { long long int n; cin >> n; long long int a[n + 1], b[n + 1]; for (long long int i = 1; i <= n; i++) cin >> a[i]; for (long long int i = 1; i <= n; i++) cin >> b[i]; multiset<long long int> s; for (long long int i = 1; i <= n; i++) s.insert(b[i]); for (long long int i = 1; i <= n; i++) { long long int opt1 = *s.begin(); if (s.lower_bound(n - a[i]) == s.end()) { cout << (a[i] + opt1) % n << ; s.erase(s.find(opt1)); continue; } long long int opt2 = *s.lower_bound(n - a[i]); if ((a[i] + opt1) % n < (a[i] + opt2) % n) { cout << (a[i] + opt1) % n << ; s.erase(s.find(opt1)); } else { cout << (a[i] + opt2) % n << ; s.erase(s.find(opt2)); } } } return 0; }
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave_b2b
* this module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg sselr;
reg [7:0] byte_data_sent;
reg [7:0] next_byte_data_sent;
reg [7:0] bit_cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
reg curr, last;
always@(posedge clk)
begin
if(!rst_n) begin
curr <= 1'b0;
last <= 1'b0;
end
else begin
curr <= sck;
last <= curr;
end
end
//Raising edge
assign sck_risingedge = curr & (~last);
//failing edge
assign sck_fallingedge = ~curr & (last);
/*******************************************************************************
*detect ssel status
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 1'h1;
else
sselr <= ssel;
end
assign ssel_active = (~sselr) ? 1'b0 : 1'b1; // SSEL is active high
/*******************************************************************************
*read from mosi
*******************************************************************************/
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
/*******************************************************************************
*SPI slave send data
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
byte_data_sent <= 8'h1;
next_byte_data_sent <= 8'h2;
bit_cnt <= 8'h0;
end
else begin
if(ssel_active && sck_fallingedge)
begin
if(next_byte_data_sent == 8'h41)
next_byte_data_sent <= 8'h1;
if (bit_cnt == 8'h7f)
begin
byte_data_sent <= next_byte_data_sent;
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else begin
if(ssel_active && sck_risingedge) begin
/*
update the next byte
*/
if(bit_cnt == 8'hff)
begin
bit_cnt <= 8'h0;
next_byte_data_sent <= next_byte_data_sent + 1;
end
end
end
end
end
assign miso = byte_data_sent[7]; // send MSB first
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1.01e9; const long long infll = (long long)1.01e18; const long double eps = 1e-9; const long double pi = acos((long double)-1); mt19937 mrand(chrono::steady_clock::now().time_since_epoch().count()); int rnd(int x) { return mrand() % x; } void precalc() {} const int maxn = (int)1e5 + 5; int n, m; vector<int> g[maxn]; bool read() { if (scanf( %d%d , &n, &m) < 2) { return false; } for (int i = 0; i < n; i++) { g[i].clear(); } for (int i = 0; i < m; i++) { int v, u; scanf( %d%d , &v, &u); v--; u--; g[v].push_back(u); } return true; } int used[maxn]; int tin[maxn], tout[maxn], t; void dfs0(int v) { used[v] = true; tin[v] = t++; for (int i = 0; i < ((int)(g[v]).size()); i++) { int u = g[v][i]; if (!used[u]) { dfs0(u); } } tout[v] = t; } bool anc(int v, int u) { return tin[v] <= tin[u] && tout[u] <= tout[v]; } int incnt[maxn]; int cnt[maxn], tov[maxn]; int go[maxn]; bool dfs1(int v) { used[v] = true; cnt[v] = 0; tov[v] = v; for (int i = 0; i < ((int)(g[v]).size()); i++) { int u = g[v][i]; if (used[u]) { if (!anc(u, v)) { return false; } incnt[u]++; cnt[v]++; if (anc(u, tov[v])) { tov[v] = u; } } else { if (!dfs1(u)) { return false; } cnt[v] += cnt[u]; if (anc(tov[u], tov[v])) { tov[v] = tov[u]; } } } cnt[v] -= incnt[v]; go[v] = (cnt[v] == 1 ? tov[v] : -1); return true; } int good[maxn]; void dfs2(int v) { used[v] = true; if (go[v] == v) { good[v] = true; } else if (go[v] == -1) { good[v] = false; } else { good[v] = good[go[v]]; } for (int i = 0; i < ((int)(g[v]).size()); i++) { int u = g[v][i]; if (!used[u]) { dfs2(u); } } } vector<int> ans; bool solve1(int s) { for (int i = 0; i < n; i++) { used[i] = false; } t = 0; dfs0(s); for (int i = 0; i < n; i++) { used[i] = false; incnt[i] = 0; } if (!dfs1(s)) { return false; } for (int i = 0; i < n; i++) { used[i] = false; } go[s] = s; dfs2(s); ans.clear(); for (int i = 0; i < n; i++) { if (good[i]) { ans.push_back(i); } } if (((int)(ans).size()) * 5 < n) { printf( -1 n ); } else { for (int i = 0; i < ((int)(ans).size()); i++) { printf( %d , ans[i] + 1); } printf( n ); } return true; } const int K = 70; void solve() { for (int it = 0; it < K; it++) { int s = rnd(n); if (solve1(s)) { return; } } printf( -1 n ); } int main() { precalc(); int t; scanf( %d , &t); while (read()) { solve(); } return 0; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was derived from PR617.v
**/
module main();
parameter INIT_00 = 32'hffffffff;
reg [17:0] t;
reg [8:0] c;
initial begin
t = {17'd0,INIT_00[0]}<<1;
$display("%b",t);
if (t !== 18'b00_0000_0000_0000_0010) begin
$display("FAILED");
$finish;
end
c = 0;
t = {17'd0,INIT_00[c]}<<1;
$display("%b",t);
if (t !== 18'b00_0000_0000_0000_0010) begin
$display("FAILED");
$finish;
end
c = 16;
t = {17'd0,INIT_00[c]}<<1;
$display("%b",t);
if (t !== 18'b00_0000_0000_0000_0010) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> const long long md = (1e9 + 7); const long long fakmd = 998244353; using namespace std; long long n, m; pair<long long, long long> a[100100]; long long ans[100100]; int32_t main() { cin >> n >> m; long long it = 1; long long sum = 0; for (long long i = 1; i <= m; i++) { cin >> a[i].first; sum += a[i].first; a[i].second = i; } if (sum < n) { return cout << -1, 0; } for (long long i = 1; i <= m; i++) { sum -= a[i].first; long long ln = max((n - it + 1) - sum, 1ll); if (ln > a[i].first || it + a[i].first - 1 > n) { return cout << -1, 0; } ans[a[i].second] = it; it += ln; } if (it < n) { cout << -1; } else { for (long long i = 1; i <= m; i++) { cout << ans[i] << ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_SYMBOL_V
`define SKY130_FD_SC_LS__O311AI_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 4010; int n, m, a[N], rt, tot, L[N], siz[N], R[N], ls[N], rs[N]; long long val[N], dp[N][N]; inline void build(int &p, int l, int r) { if (l > r) return; p = ++tot; int pos = l; for (int i = l; i <= r; ++i) if (a[i] < a[pos]) pos = i; val[p] = a[pos]; build(ls[p], l, pos - 1); build(rs[p], pos + 1, r); dp[p][0] = 0; dp[p][1] = m * val[p] - val[p]; siz[p] = 1; for (int i = siz[p]; i >= 0; --i) for (int j = 0; j <= siz[ls[p]]; ++j) dp[p][i + j] = max(dp[p][i + j], dp[p][i] + dp[ls[p]][j] - 2ll * i * j * val[p]); siz[p] += siz[ls[p]]; for (int i = siz[p]; i >= 0; --i) for (int j = 0; j <= siz[rs[p]]; ++j) dp[p][i + j] = max(dp[p][i + j], dp[p][i] + dp[rs[p]][j] - 2ll * i * j * val[p]); siz[p] += siz[rs[p]]; } int main() { memset(dp, -0x3f, sizeof(dp)); scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); build(rt, 1, n); printf( %lld n , dp[1][m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, mod = 1000000007, dp[2010][2010]; long long solve(long long num, long long x) { long long i; if (x == k) return 1; if (dp[num][x] != -1) return dp[num][x]; long long res = 0; for (i = 1; (i * num) <= n; i++) { res += solve(num * i, x + 1) % mod; } return dp[num][x] = (res % mod); } int main() { cin >> n >> k; memset(dp, -1, sizeof dp); cout << solve(1, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 5e5; long long id[N], a[N], pos[N]; int main() { ios_base::sync_with_stdio(false); long long n, t, m, l, k, ans, i, j, res = 0, fl; t = 1; long long x; while (t--) { long long o; cin >> n >> m >> k; for (i = 0; i < n; i++) { cin >> a[i]; pos[a[i]] = i; } long long ct = 1; j = 0; for (o = 0;; o += k) { for (i = o; i < o + k; ++i) id[a[i]] = ct; ct++; if (i > n) break; } for (i = 0; i < m; i++) { cin >> x; res += id[x]; if (pos[x] > 0) { long long p = pos[x]; long long val = a[p - 1]; swap(id[x], id[val]); swap(a[p], a[p - 1]); pos[x] = p - 1; pos[val] = p; } } cout << res << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool prime[10000007]; void SieveOfEratosthenes() { memset(prime, true, sizeof(prime)); for (long long int p = 2; p * p <= 10000007; p++) { if (prime[p] == true) { for (long long int i = p * p; i <= 10000007; i += p) prime[i] = false; } } } const long long int N = 300500; long long int fact[N]; long long int invFact[N]; long long int fast_pow(long long int a, long long int p, long long int m) { long long int res = 1; while (p) { if (p % 2 == 0) { a = (a * a) % m; p /= 2; } else { res = (res * a) % m; p--; } } return res; } void Call_For_nCr() { fact[0] = invFact[0] = 1; for (long long int i = 1; i < N; i++) { fact[i] = (fact[i - 1] * i) % 1000000007; invFact[i] = fast_pow(fact[i], 1000000007 - 2, 1000000007); } } long long int nCR(long long int n, long long int k, long long int m) { if (k > n) { return 0; } return fact[n] * invFact[k] % m * invFact[n - k] % m; } long long int sumOfDigit(long long int n, long long int b) { long long int unitDigit, sum = 0; while (n > 0) { unitDigit = n % b; sum += unitDigit; n = n / b; } return sum; } long long int factorial(long long int n) { return (n == 1 || n == 0) ? 1 : n * factorial(n - 1); } bool compare(pair<long long int, long long int> a, pair<long long int, long long int> b) { if (a.first < b.first) return 1; if (b.first < a.first) return 0; if (a.second > b.second) return 1; return 0; } void solve() { string s; cin >> s; long long int ans = 0, one = 0, ok = 0, zero = 0; for (long long int i = 0; i < s.length(); i++) { if (s[i] == 0 ) { zero = 1; ok = 1; if (one && zero) ans = 1; } if (s[i] == 1 ) { if (zero) one = 1; } } if (!ok) { cout << 0 << n ; return; } if (ans) cout << 2 << n ; else cout << 1 << n ; } void init_code() { ios_base::sync_with_stdio(false); cin.tie(NULL); } signed main() { init_code(); long long int t = 1; cin >> t; long long int i = 1; while (t--) { solve(); i++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long prod = 1; for (int i = 1; i < n; i++) prod *= i; prod *= 2; prod /= n; cout << prod << endl; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_pad_dn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS2 PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos2_pad_dn(oe ,data ,to_core ,pad ,por_l, vddo );
output to_core ;
input oe ;
input data ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire rcvr_data ;
wire por ;
wire pad_up ;
wire net58 ;
wire net59 ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (vss ),
.bsr_up (net58 ),
.bsr_dn_l (net59 ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (vss ),
.bsr_mode (vss ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (vss ),
.bsr_up (vss ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (vss ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
bw_io_cmos2_term_dn I18 (
.vddo (vddo ),
.out (pad ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; cin >> n >> m >> a >> b; int q = m * a; if (q < b) { cout << n * a; } else { int v = n / m; n -= v * m; cout << v * b + min(b, n * a); } }
|
#include <bits/stdc++.h> using namespace std; int n, m; char s[100010]; int main() { cin >> n >> m; scanf( %s , s + 1); while (m--) { int l, r; cin >> l >> r; char a[2], b[2]; scanf( %s%s , a, b); for (int i = l; i <= r; i++) if (s[i] == a[0]) s[i] = b[0]; } printf( %s , s + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct __timestamper {}; vector<vector<int>> g; vector<vector<int>> id; vector<int> used; vector<int> ts; void dfs(int v, int x) { if (used[v]) return; used[v] = 1; for (int i = 0; i < (int)g[v].size(); i++) { if (id[v][i] < x) { dfs(g[v][i], x); } } ts.push_back(v); } bool check(int x) { ts.clear(); used = vector<int>(g.size()); for (int i = 0; i < (int)g.size(); i++) { dfs(i, x); } reverse(ts.begin(), ts.end()); for (int i = 0; i + 1 < (int)ts.size(); i++) { int v = ts[i]; bool ok = false; for (int j = 0; j < (int)g[v].size(); j++) if (g[v][j] == ts[i + 1] && id[v][j] < x) { ok = true; } if (!ok) return false; } return true; } int main() { int n, m; scanf( %d%d , &n, &m); g = vector<vector<int>>(n); id = vector<vector<int>>(n); for (int i = 0; i < m; i++) { int a, b; scanf( %d%d , &a, &b); --a, --b; g[a].push_back(b); id[a].push_back(i); } if (!check(m)) { printf( -1 n ); return 0; } int l = 0; int r = m; while (r - l > 1) { int mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } printf( %d n , r); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { clock_t clk_begin = clock(); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; string s; cin >> s; int c = 0; for (int i = 0; i < n; ++i) if (s[i] == 8 ) c++; n /= 11; cout << min(n, c) << n ; ; cerr << Time taken: << (double)(clock() - clk_begin) / CLOCKS_PER_SEC << n ; return 0; ; }
|
#include <bits/stdc++.h> using namespace std; const long long iinf = 1e9 + 10; const long long inf = 1ll << 60; const long long mod = 1e9 + 87; void GG() { cout << 0 n ; exit(0); } long long mpow(long long a, long long n, long long mo = mod) { long long re = 1; while (n > 0) { if (n & 1) re = re * a % mo; a = a * a % mo; n >>= 1; } return re; } long long inv(long long b, long long mo = mod) { if (b == 1) return b; return (mo - mo / b) * inv(mo % b, mo) % mo; } const long long maxn = 1e6 + 5; unsigned long long H[maxn]; bool np[maxn]; unsigned long long val[maxn]; long long n; void RET(vector<long long> no) { vector<long long> yay(n + 1); for (long long t : no) yay[t] = 1; cout << n - (long long)no.size() << n ; for (long long i = 1; i <= n; ++i) { if (!yay[i]) cout << i << ; } cout << n ; exit(0); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); ; mt19937_64 rnd(time(0)); for (long long i = 0; i < maxn; ++i) { val[i] = rnd(); } for (long long i = 2; i < maxn; ++i) { if (!np[i]) { for (long long j = i; j < maxn; j += i) { if (j != i) np[j] = 1; long long r = j; while (r % i == 0) { r /= i; H[j] ^= val[i]; } } } } cin >> n; for (long long i = 1; i < maxn; ++i) H[i] ^= H[i - 1]; unsigned long long all = 0; for (long long i = 1; i <= n; ++i) all ^= H[i]; if (all == 0) { RET({}); } for (long long i = 1; i <= n; ++i) { if (H[i] == all) { RET({i}); } } vector<pair<unsigned long long, long long> > v; for (long long i = 1; i <= n; ++i) { v.push_back({H[i], i}); } sort(v.begin(), v.end()); for (long long i = 1; i <= n; ++i) { long long at = lower_bound(v.begin(), v.end(), pair<unsigned long long, long long>{H[i] ^ all, i + 1}) - v.begin(); if (at < (long long)v.size() && (v[at].first == (H[i] ^ all))) { RET({i, v[at].second}); } } assert(n % 2 == 1); RET({n, n / 2, 2}); }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; const long long N = 5000; long long n, m, s, t; vector<pair<long long, long long> > nei[N + 1]; vector<long long> rv[N + 1]; void ae(long long x, long long y, long long z) { nei[x].push_back(make_pair(y, z)), nei[y].push_back(make_pair(x, 0)); rv[x].push_back(nei[y].size() - 1), rv[y].push_back(nei[x].size() - 1); } long long dep[N + 1]; bool bfs() { memset(dep, -1, sizeof(dep)); dep[s] = 0; queue<long long> q; q.push(s); while (q.size()) { long long x = q.front(); q.pop(); for (long long i = 0; i < nei[x].size(); i++) { long long y = nei[x][i].first, c = nei[x][i].second; if (c && !~dep[y]) dep[y] = dep[x] + 1, q.push(y); } } return ~dep[t]; } long long now[N + 1]; long long dfs(long long x = s, long long flw = inf) { if (x == t || !flw) return flw; long long res = 0, tmp; for (long long &i = now[x]; i < nei[x].size(); i++) { long long y = nei[x][i].first, &c = nei[x][i].second; if (dep[y] == dep[x] + 1 && (tmp = dfs(y, min(flw, c)))) { res += tmp, flw -= tmp; c -= tmp, nei[y][rv[x][i]].second += tmp; if (!flw) break; } } return res; } long long dinic() { long long res = 0; while (bfs()) { memset(now, 0, sizeof(now)); res += dfs(); } return res; } long long a[N], b[N], c[N], d[N]; vector<long long> nums_x, nums_y; void discrete() { sort(nums_x.begin(), nums_x.end()), sort(nums_y.begin(), nums_y.end()); nums_x.resize(unique(nums_x.begin(), nums_x.end()) - nums_x.begin()); nums_y.resize(unique(nums_y.begin(), nums_y.end()) - nums_y.begin()); for (long long i = 1; i <= n; i++) a[i] = lower_bound(nums_x.begin(), nums_x.end(), a[i] - 1) - nums_x.begin() + 1, b[i] = lower_bound(nums_y.begin(), nums_y.end(), b[i] - 1) - nums_y.begin() + 1, c[i] = lower_bound(nums_x.begin(), nums_x.end(), c[i]) - nums_x.begin(), d[i] = lower_bound(nums_y.begin(), nums_y.end(), d[i]) - nums_y.begin(); } long long row[N], col[N]; signed main() { cin >> m >> n; for (long long i = 1; i <= n; i++) { cin >> a[i] >> b[i] >> c[i] >> d[i]; nums_x.push_back(a[i] - 1), nums_x.push_back(c[i]); nums_y.push_back(b[i] - 1), nums_y.push_back(d[i]); } discrete(); s = 1, t = 2; long long now = 2; for (long long i = 1; i < nums_x.size(); i++) row[i] = ++now, ae(s, now, nums_x[i] - nums_x[i - 1]); for (long long i = 1; i < nums_y.size(); i++) col[i] = ++now, ae(now, t, nums_y[i] - nums_y[i - 1]); for (long long i = 1; i <= n; i++) { for (long long j = a[i]; j <= c[i]; j++) for (long long k = b[i]; k <= d[i]; k++) ae(row[j], col[k], inf); } cout << dinic(); return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:52:26 06/07/2015
// Design Name:
// Module Name: joystick_protocols
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module joystick_protocols(
input wire clk,
//-- cpu interface
input wire [15:0] a,
input wire iorq_n,
input wire rd_n,
input wire [7:0] din,
output reg [7:0] dout,
output reg oe_n,
//-- interface with ZXUNO reg bank
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
//-- actual joystick and keyboard signals
input wire [4:0] kbdjoy_in,
input wire [4:0] db9joy_in,
input wire [4:0] kbdcol_in,
output reg [4:0] kbdcol_out,
input wire vertical_retrace_int_n // this is used as base clock for autofire
);
parameter
JOYCONFADDR = 8'h06,
KEMPSTONADDR = 8'h1F,
SINCLAIRP1ADDR = 12,
SINCLAIRP2ADDR = 11,
FULLERADDR = 8'h7F,
DISABLED = 3'h0,
KEMPSTON = 3'h1,
SINCLAIRP1 = 3'h2,
SINCLAIRP2 = 3'h3,
CURSOR = 3'h4,
FULLER = 3'h5;
// Input format: FUDLR . 0=pressed, 1=released
reg db9joyup = 1'b0;
reg db9joydown = 1'b0;
reg db9joyleft = 1'b0;
reg db9joyright = 1'b0;
reg db9joyfire = 1'b0;
reg kbdjoyup = 1'b0;
reg kbdjoydown = 1'b0;
reg kbdjoyleft = 1'b0;
reg kbdjoyright = 1'b0;
reg kbdjoyfire = 1'b0;
always @(posedge clk) begin
{db9joyfire,db9joyup,db9joydown,db9joyleft,db9joyright} <= ~db9joy_in;
{kbdjoyfire,kbdjoyup,kbdjoydown,kbdjoyleft,kbdjoyright} <= kbdjoy_in;
end
// Update JOYCONF from CPU
reg [7:0] joyconf = {1'b0,SINCLAIRP1, 1'b0,KEMPSTON};
always @(posedge clk) begin
if (zxuno_addr==JOYCONFADDR && zxuno_regwr==1'b1)
joyconf <= din;
end
// Autofire stuff
reg [2:0] cont_autofire = 3'b000;
reg [3:0] edge_detect = 4'b0000;
wire autofire = cont_autofire[2];
always @(posedge clk) begin
edge_detect <= {edge_detect[2:0], vertical_retrace_int_n};
if (edge_detect == 4'b0011)
cont_autofire <= cont_autofire + 1; // count only on raising edge of vertical retrace int
end
wire kbdjoyfire_processed = (joyconf[3]==1'b0)? kbdjoyfire : kbdjoyfire & autofire;
wire db9joyfire_processed = (joyconf[7]==1'b0)? db9joyfire : db9joyfire & autofire;
always @* begin
oe_n = 1'b1;
dout = 8'hZZ;
kbdcol_out = kbdcol_in;
if (zxuno_addr==JOYCONFADDR && zxuno_regrd==1'b1) begin
oe_n = 1'b0;
dout = joyconf;
end
else if (iorq_n == 1'b0 && a[7:0]==KEMPSTONADDR && rd_n==1'b0) begin
dout = 8'h00;
oe_n = 1'b0;
if (joyconf[2:0]==KEMPSTON)
dout = dout | {3'b000, kbdjoyfire_processed, kbdjoyup, kbdjoydown, kbdjoyleft, kbdjoyright};
if (joyconf[6:4]==KEMPSTON)
dout = dout | {3'b000, db9joyfire_processed, db9joyup, db9joydown, db9joyleft, db9joyright};
end
else if (iorq_n == 1'b0 && a[7:0]==FULLERADDR && rd_n==1'b0) begin
dout = 8'hFF;
oe_n = 1'b0;
if (joyconf[2:0]==FULLER)
dout = dout & {~kbdjoyfire_processed, 3'b111, ~kbdjoyright, ~kbdjoyleft, ~kbdjoydown, ~kbdjoyup};
if (joyconf[6:4]==FULLER)
dout = dout & {~db9joyfire_processed, 3'b111, ~db9joyright, ~db9joyleft, ~db9joydown, ~db9joyup};
end
else if (iorq_n==1'b0 && a[SINCLAIRP1ADDR]==1'b0 && a[0]==1'b0 && rd_n==1'b0) begin
if (joyconf[2:0]==SINCLAIRP1)
kbdcol_out = kbdcol_out & {~kbdjoyleft,~kbdjoyright,~kbdjoydown,~kbdjoyup,~kbdjoyfire_processed};
if (joyconf[6:4]==SINCLAIRP1)
kbdcol_out = kbdcol_out & {~db9joyleft,~db9joyright,~db9joydown,~db9joyup,~db9joyfire_processed};
if (joyconf[2:0]==CURSOR)
kbdcol_out = kbdcol_out & {~kbdjoydown,~kbdjoyup,~kbdjoyright,1'b1,~kbdjoyfire_processed};
if (joyconf[6:4]==CURSOR)
kbdcol_out = kbdcol_out & {~db9joydown,~db9joyup,~db9joyright,1'b1,~db9joyfire_processed};
end
else if (iorq_n==1'b0 && a[SINCLAIRP2ADDR]==1'b0 && a[0]==1'b0 && rd_n==1'b0) begin
if (joyconf[2:0]==SINCLAIRP2)
kbdcol_out = kbdcol_out & {~kbdjoyfire_processed,~kbdjoyup,~kbdjoydown,~kbdjoyright,~kbdjoyleft};
if (joyconf[6:4]==SINCLAIRP2)
kbdcol_out = kbdcol_out & {~db9joyfire_processed,~db9joyup,~db9joydown,~db9joyright,~db9joyleft};
if (joyconf[2:0]==CURSOR)
kbdcol_out = kbdcol_out & {~kbdjoyleft,4'b1111};
if (joyconf[6:4]==CURSOR)
kbdcol_out = kbdcol_out & {~db9joyleft,4'b1111};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n >= 1 && n <= 10 || n >= 22 && n <= 25) cout << 0 ; else if (n == 11) cout << 4 ; else if (n == 20) cout << 15 ; else cout << 4 ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long fn(long long x) { long long ret = (x * (x + 1)) / 2; if (x < 0) ret = 0; return ret; } long long fn(long long R, long long K1, long long K2) { long long ret = 0; K1 = min(K1, R - 1); K2 = min(K2, R); if (R - K1 >= K2) return ((K1 + 1) * K2); ret -= fn(R - K1 - 1); ret += fn(K2); ret += (R - K2) * K2; return ret; } long long N, X, Y, C; long long bin(long long start, long long end) { if (start > end) return start; long long mid = (start + end) / 2; long long ret = 1, foo = 0; foo = fn(mid, N - X, N - Y); ret += foo; foo = fn(mid, N - Y, X - 1); ret += foo; foo = fn(mid, X - 1, Y - 1); ret += foo; foo = fn(mid, Y - 1, N - X); ret += foo; if (ret >= C) return bin(start, mid - 1); else return bin(mid + 1, end); } inline void ReadInput(void) { scanf( %lld , &N); scanf( %lld , &X); scanf( %lld , &Y); scanf( %lld , &C); } inline void solve(void) { if (C == 1) cout << 0 << endl; else cout << bin(1, 2 * N) << endl; } inline void Refresh(void) {} int main() { ReadInput(); solve(); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:41:34 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_zed_hdmi_0_0 -prefix
// system_zed_hdmi_0_0_ system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, f, k; cin >> a >> b >> f >> k; int now = b; int ret = 0; for (int i = 1; i <= k; i++) { if (i % 2 == 1) { if (now < f) { return puts( -1 ), 0; } if (i == k) { if (now < a) { ret++; } if (b < a - f) { return puts( -1 ), 0; } } else { if (now < a + a - f) { ret++; now = b - (a - f); } else { now = now - a; } } } else { if (now < a - f) { return puts( -1 ), 0; } if (i == k) { if (now < a) { ret++; } if (b < f) { return puts( -1 ), 0; } } else { if (now < a + f) { ret++; now = b - f; } else { now = now - a; } } } } cout << ret << endl; return 0; }
|
module ADT7310P32LS16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: PLL1_sim.v,v 1.2 2017/06/13 14:37:16 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/PLL1_sim.v,v $
//
//=============================================================
// Simple simulation model of the PLL1 component.
`timescale 1 ps / 1 ps
module PLL1 (
inclk0,
c0,
c1,
c2
);
input inclk0;
output c0;
output c1;
output c2;
altpll altpll_component (
.inclk0 (inclk0),
.c0 (c0),
.c1 (c1),
.c2 (c2)
);
endmodule
module altpll #(
parameter inclk0_input_frequency = 20000,
parameter clk0_multiply_by = 4,
parameter clk0_divide_by = 5,
parameter clk0_phase_shift = "0",
parameter clk1_multiply_by = 4,
parameter clk1_divide_by = 5,
parameter clk1_phase_shift = "0",
parameter clk2_multiply_by = 8,
parameter clk2_divide_by = 5,
parameter clk2_phase_shift = "0")(
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
reg c0;
reg c1;
reg c2;
integer phase0;
integer phase1;
integer phase2;
// Convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp >= 48) && (tmp <= 57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign * magnitude;
end
endfunction
// Convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
initial
begin
c0 = 1'b1;
phase0 = get_int_phase_shift(clk0_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase0)
forever #(((inclk0_input_frequency*clk0_divide_by)/clk0_multiply_by)/2) c0 = ~c0;
end
initial
begin
c1 = 1'b1;
phase1 = get_int_phase_shift(clk1_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase1)
forever #(((inclk0_input_frequency*clk1_divide_by)/clk1_multiply_by)/2) c1 = ~c1;
end
initial
begin
c2 = 1'b1;
phase2 = get_int_phase_shift(clk2_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase2)
forever #(((inclk0_input_frequency*clk2_divide_by)/clk2_multiply_by)/2) c2 = ~c2;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) cout << i << ; cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_2_V
`define SKY130_FD_SC_HDLL__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_2_V
|
#include <bits/stdc++.h> using namespace std; struct msg { long long lstl = 0; long long lstr = 0; long long num = 0; }; int32_t main() { long long n, k; cin >> n >> k; long long a[n]; msg ms[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { if (a[i] == 0) { ms[i].lstl = max(i - k, 0LL); ms[i].lstr = min(i + k, n - 1); ms[i].num = 1 + ms[i].lstr - ms[i].lstl; } else { ms[i].lstl = max(i - k, 0LL); ms[i].lstr = min(i + k, n - 1); long long nmr, nml; if (ms[i].lstl <= ms[a[i] - 1].lstr) { if (ms[a[i] - 1].lstr < i) { nml = k - (ms[a[i] - 1].lstr - ms[i].lstl + 1); } else { nml = 0; } } else { nml = i - ms[i].lstl; } if (ms[a[i] - 1].lstr < i) { nmr = ms[i].lstr - i + 1; } else if (ms[a[i] - 1].lstr == i) { nmr = ms[i].lstr - i; } else { nmr = ms[i].lstr - ms[a[i] - 1].lstr; } ms[i].num = nmr + nml + ms[a[i] - 1].num; } } for (long long i = 0; i < n; i++) { cout << ms[i].num << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void File() { freopen( output.txt , w , stdout); freopen( input.txt , r , stdin); } void fast() { ios::sync_with_stdio(NULL); cout.tie(NULL); cin.tie(NULL); } const double pi = 2 * acos(0.0); const int nn = 5e2 + 5; const int oo = 0x3f3f3f3f; int main() { fast(); int n, ans = 0; pair<int, int> arr[nn]; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i].first >> arr[i].second; for (int i = 0; i < n; i++) { int cnt[4] = {}; for (int j = 0; j < n; j++) { if (i == j) continue; if (arr[i].first > arr[j].first && arr[i].second == arr[j].second) cnt[0]++; else if (arr[i].first < arr[j].first && arr[i].second == arr[j].second) cnt[1]++; else if (arr[i].first == arr[j].first && arr[i].second > arr[j].second) cnt[2]++; else if (arr[i].first == arr[j].first && arr[i].second < arr[j].second) cnt[3]++; if (cnt[0] && cnt[1] && cnt[2] && cnt[3]) { ans++; break; } } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:10:22 08/01/2014
// Design Name:
// Module Name: keytofrequency
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keytofrequency( key_code, clk, slow_rate );
input[4:0] key_code;
input clk;
output [12:0] slow_rate;
reg [12:0] slow;
always @ (posedge clk)
case (key_code)
0: slow <= 0; // 0: frequency = 0;
1: slow <= 'D1909; // 1: frequency = 'D262;
2: slow <= 'D1746; // 2: frequency = 'D294;
3: slow <= 'D1515; // 3: frequency = 'D330;
4: slow <= 'D1433; // 4: frequency = 'D349;
5: slow <= 'D1276; // 5: frequency = 'D392;
6: slow <= 'D1137; // 6: frequency = 'D440;
7: slow <= 'D1012; // 7: frequency = 'D494;
8: slow <= 'D966; // 8: frequency = 'D523;
9: slow <= 'D852; // 9: frequency = 'D587;
10: slow <= 'D759; // 10: frequency = 'D659;
11: slow <= 'D717; // 11: frequency = 'D698;
12: slow <= 'D638; // 12: frequency = 'D784;
13: slow <= 'D568; // 13: frequency = 'D880;
14: slow <= 'D506; // 14: frequency = 'D988;
15: slow <= 'D478; // 15: frequency = 'D1047;
16: slow <= 'D426; // 16: frequency = 'D1175;
17: slow <= 'D379; // 17: frequency = 'D1319;
18: slow <= 'D358; // 18: frequency = 'D1397;
19: slow <= 'D319; // 19: frequency = 'D1568;
20: slow <= 'D284; // 20: frequency = 'D1760;
21: slow <= 'D253; // 21: frequency = 'D1976;
endcase
assign slow_rate = slow;
endmodule
|
`ifndef _REGFILE
`define _REGFILE
`include "../misc/demux.v"
`include "../misc/mux.v"
`include "../reg-file/register.v"
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, writeR7, inR7, in, reset); // Modify to include R7 effects
output [15:0] out1, out2;
input [15:0] in, inR7;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset, writeR7;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
decode8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, (writeR7==1'b1)?inR7:in, ~(writeLines[7] & (~write + ~writeR7)), reset);
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; long long int MOD = 1000000007; void solve() { int p, f; cin >> p >> f; if (f > p) swap(p, f); int cs, cw; cin >> cs >> cw; int s, w; cin >> s >> w; if (w > s) { swap(w, s); swap(cs, cw); } int maxv = 0; for (int x = 0; x <= min(cw, f / w); x++) { int curr = x; int fr = f - x * w; int pr = p; int csr = cs; int cwr = cw - x; int t = min(csr, fr / s); curr += t; csr -= t; curr += min(cwr, pr / w); pr -= min(cwr, pr / w) * w; curr += min(csr, pr / s); maxv = max(maxv, curr); } cout << maxv << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tt = 1; cin >> tt; for (int ttt = 1; ttt <= tt; ttt++) { solve(); } return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/16.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_BLACKBOX_V
|
#include <bits/stdc++.h> long long arr[10000001]; using namespace std; int main() { long long n, k, m = 0; cin >> n >> k; m = (2 * n) + 1; for (int i = 1; i <= m; i++) { cin >> arr[i]; } for (int i = 2; i <= m; i += 2) { if (k == 0) { break; } if (arr[i] > arr[i - 1] + 1 && arr[i] > arr[i + 1] + 1) { --arr[i]; k--; } } for (int i = 1; i <= m; i++) { cout << arr[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { int q, ans = 0; cin >> q; if (q % 2) q -= 9, ans++; if (q < 0) ans = -1; else ans += q / 4; if (q == 2) ans = -1; cout << ans << endl; } return 0; }
|
/***************************************************************************
* pcx2mb_link_cnt.v: A counter to keep track of outstanding transactions
* to one of the five destinations of the PCX request. This
* counter will be instantiated 5 times.
*
* The core has a link credit of 2 transactions. However, it will
* speculatively send a third transaction, assuming that a grant
* will be received in time. If this block is not ready to grant
* the first transaction, then the third one must be dropped,
* because the core will re-send it.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: /import/bw-rainbow/rainbow_cvs/niagara/design/sys/iop/ccx2mb/rtl/pcx2mb_link_ctr.v,v 1.2 2007/06/01 00:09:07 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_link_ctr (
// Outputs
request_mask_pa,
// Inputs
rclk,
reset_l,
pcx_req_pa,
pcx_req_px,
pcx_atom_px,
pcx_grant_px
);
output request_mask_pa;
input rclk;
input reset_l;
input pcx_req_pa;
input pcx_req_px;
input pcx_atom_px;
input pcx_grant_px;
reg [1:0] link_count_pa;
wire request_mask_pa;
wire count_inc;
wire count_dec;
assign count_inc = pcx_req_pa || (pcx_req_px && pcx_atom_px);
assign count_dec = pcx_grant_px;
always @(posedge rclk) begin
if (!reset_l) begin
link_count_pa <= 2'b00;
end
else if (count_inc && count_dec) begin
link_count_pa <= link_count_pa;
end
else if (count_inc && !link_count_pa[1]) begin
link_count_pa <= link_count_pa + 2'b01;
end
else if (count_dec) begin
link_count_pa <= link_count_pa - 2'b01;
end
else begin
link_count_pa <= link_count_pa;
end
end
assign request_mask_pa = link_count_pa[1];
endmodule
|
/*
* Copyright (c) 2008 Gyorgy Jeney ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module fpu_li_s1();
parameter eh = 11;
parameter [eh - 1:0] alap = 1023;
parameter ih2 = 6;
parameter fh = 7;
parameter [fh - 1:0] falap = 63;
localparam ih = 1 << ih2;
localparam nh = (eh > fh ? eh : fh) + 1;
wire [nh - 1:0] exp_norm;
/* IVL compiles this fine but when trying to run it through vvp, it throws
* this error:
*
* internal error: port 0 expects wid=11, got wid=12
* vvp: concat.cc:56: virtual void vvp_fun_concat::recv_vec4(vvp_net_ptr_t, const
* vvp_vector4_t&): Assertion `0' failed.
* Aborted
*
* This is a regression caused by this commit:
* commit a914eda5eff8b088837432a6516584b6a075fcd6
* Author: Stephen Williams <>
* Date: Tue Apr 8 20:50:36 2008 -0700
*
* Get part select from vectored parameters correct.
*
* Parameters with vector descriptions that are not zero based and
* are used in net contexts should generate the properly ranged
* temporary signals. This causes subsequent part selects to work
* out properly.
*/
assign exp_norm = alap - falap + ih;
initial
begin
#1 $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int max(long long int a, long long int b) { if (a > b) return a; else return b; } long long int min(long long int a, long long int b) { if (a < b) return a; else return b; } const int dx[4] = {-1, 1, 0, 0}; const int dy[4] = {0, 0, -1, 1}; int XX[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int YY[] = {-1, 0, 1, -1, 1, -1, 0, 1}; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int k, i, j, t, a, b, l, r, x, n; cin >> n >> k; long long int arr[n]; for (i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); long long int maxi = k, count = 0; for (i = 0; i < n; i++) { long long int z = ceil(arr[i] * 1.0 / 2); if (maxi >= z) { maxi = max(maxi, arr[i]); continue; } while (maxi < z) { maxi = 2 * maxi; count++; } maxi = max(maxi, arr[i]); } cout << count; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DLXTN_FUNCTIONAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, x, c1 = 0, c2 = 0; bool flag = false; cin >> n; while (n--) { cin >> x; if (x == 100) ++c1; else ++c2; } if (c1 % 2 == 0) { if ((c1 == 0 && c2 % 2 == 0) || (c1 > 0)) flag = true; } if (flag) { cout << YES ; } else cout << NO ; }
|
module axi_master_stub(
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 64'b0;
assign M2S_AXI_WSTRB = 8'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule : axi_master_stub
/*
axi_master_stub axi_master_XXX_stub (
.M2S_AXI_ACLK(M2S_XXX_AXI_ACLK),
//Read Transaction
.M2S_AXI_ARVALID(M2S_XXX_AXI_ARVALID),
.M2S_AXI_ARREADY(M2S_XXX_AXI_ARREADY),
.M2S_AXI_ARADDR(M2S_XXX_AXI_ARADDR[31:0]),
.M2S_AXI_ARBURST(M2S_XXX_AXI_ARBURST[1:0]),
.M2S_AXI_ARLEN(M2S_XXX_AXI_ARLEN[3:0]),
.M2S_AXI_ARSIZE(M2S_XXX_AXI_ARSIZE[1:0]),
//
.M2S_AXI_RVALID(M2S_XXX_AXI_RVALID),
.M2S_AXI_RREADY(M2S_XXX_AXI_RREADY),
.M2S_AXI_RLAST(M2S_XXX_AXI_RLAST),
.M2S_AXI_RDATA(M2S_XXX_AXI_RDATA[63:0]),
//
.M2S_AXI_RRESP(M2S_XXX_AXI_RRESP[1:0]),
// Write Transaction
.M2S_AXI_AWVALID(M2S_XXX_AXI_AWVALID),
.M2S_AXI_AWREADY(M2S_XXX_AXI_AWREADY),
.M2S_AXI_AWADDR(M2S_XXX_AXI_AWADDR[31:0]),
.M2S_AXI_AWBURST(M2S_XXX_AXI_AWBURST[1:0]),
.M2S_AXI_AWLEN(M2S_XXX_AXI_AWLEN[3:0]),
.M2S_AXI_AWSIZE(M2S_XXX_AXI_AWSIZE[1:0]),
//
.M2S_AXI_WVALID(M2S_XXX_AXI_WVALID),
.M2S_AXI_WREADY(M2S_XXX_AXI_WREADY),
.M2S_AXI_WLAST(M2S_XXX_AXI_WLAST),
.M2S_AXI_WDATA(M2S_XXX_AXI_WDATA[63:0]),
.M2S_AXI_WSTRB(M2S_XXX_AXI_WSTRB[7:0]),
//
.M2S_AXI_BVALID(M2S_XXX_AXI_BVALID),
.M2S_AXI_BREADY(M2S_XXX_AXI_BREADY),
.M2S_AXI_BRESP(M2S_XXX_AXI_BRESP[1:0])
);
*/
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e9; const long long MOD = (long long)1e9 + 7; const long long P = 239; const long long MAX_N = 1000; const long long CNT = 5; const long double pi = 3.1415926535897932384626; const long double eps = 1e-6; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, l, v1, v2, k; cin >> n >> l >> v1 >> v2 >> k; long long cnt = (n + k - 1) / k; long double f = (long double)(v2 - v1) / (v2 + v1); long double t = (long double)l / (v2 * cnt - v2 * (cnt - 1) * f); cout.precision(30); t = t * cnt + t * f * (cnt - 1); cout << t; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, s, t, d[200005], v[200005], dd[200005], ma[1005][1005], ok = 1, y, ans; int main() { scanf( %d%d%d%d , &n, &m, &s, &t); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); ma[x][y] = ma[y][x] = 1; } for (int i = 1; i <= n; i++) d[i] = 1000000000, v[i] = 0; d[s] = 0; for (int i = 1; i <= n; i++) { int minv = 1000000000, u; for (int j = 1; j <= n; j++) if (!v[j] && d[j] < minv) { minv = d[j]; u = j; } v[u] = 1; for (int k = 1; k <= n; k++) if (!v[k] && ma[u][k] && d[u] + ma[u][k] < d[k]) d[k] = d[u] + ma[u][k]; } for (int i = 1; i <= n; i++) dd[i] = 1000000000, v[i] = 0; dd[t] = 0; for (int i = 1; i <= n; i++) { int minv = 1000000000, u; for (int j = 1; j <= n; j++) if (!v[j] && dd[j] < minv) { minv = dd[j]; u = j; } v[u] = 1; for (int k = 1; k <= n; k++) if (!v[k] && ma[u][k] && dd[u] + ma[u][k] < dd[k]) dd[k] = dd[u] + ma[u][k]; } for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) if (!ma[i][j]) { if (d[i] + dd[j] + 1 >= d[t] && d[j] + dd[i] + 1 >= d[t]) { ans++; } } printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long num, length, devisor = 1, rest; long long i; string str; cin >> str; length = str.length(); num = atoi(str.c_str()); for (i = 1; i <= length - 1; i++) { devisor *= 10; } rest = num % devisor; cout << devisor - rest << endl; return 0; }
|
// UC Berkeley CS150
// Lab 3, Fall 2014
// Module: ALUdecoder
// Desc: Sets the ALU operation
// Inputs: opcode: the top 6 bits of the instruction
// funct: the funct, in the case of r-type instructions
// add_rshift_type: selects whether an ADD vs SUB, or an SRA vs SRL
// Outputs: ALUop: Selects the ALU's operation
//
// This version written by Arya Reais-Parsi (), Spring 2018
`include "Opcode.vh"
`include "ALUop.vh"
module ALUdec(
input [6:0] opcode,
input [2:0] funct,
input add_rshift_type,
output reg [4:0] ALUop
);
// Implement your ALU decoder here, then delete this comment
always @(*) begin
case (opcode)
`OPC_LUI: ALUop = `ALU_COPY_B;
`OPC_AUIPC, `OPC_LOAD, `OPC_STORE, `OPC_JAL, `OPC_JALR:
ALUop = `ALU_ADD;
`OPC_BRANCH:
case (funct)
`FNC_BEQ: ALUop = `ALU_EQ;
`FNC_BNE: ALUop = `ALU_NE;
`FNC_BLT: ALUop = `ALU_LT;
`FNC_BGE: ALUop = `ALU_GE;
`FNC_BLTU: ALUop = `ALU_LTU;
`FNC_BGEU: ALUop = `ALU_GEU;
default: ALUop = `ALU_COPY_B;
endcase
`OPC_ARI_ITYPE:
case (funct)
// TODO(aryap): FNC_ADD_SUB is the only difference to the RTYPE
// decode. It doesn't depend on the add_rshift_type bit (there is no
// SUBI) Merge!
`FNC_ADD_SUB: ALUop = `ALU_ADD;
`FNC_SLT: ALUop = `ALU_SLT;
`FNC_SLTU: ALUop = `ALU_SLTU;
`FNC_XOR: ALUop = `ALU_XOR;
`FNC_OR: ALUop = `ALU_OR;
`FNC_AND: ALUop = `ALU_AND;
`FNC_SLL: ALUop = `ALU_SLL;
`FNC_SRL_SRA: ALUop = add_rshift_type == `FNC2_SRL ? `ALU_SRL : `ALU_SRA;
endcase
`OPC_ARI_RTYPE:
case (funct)
`FNC_ADD_SUB: ALUop = add_rshift_type == `FNC2_ADD ? `ALU_ADD : `ALU_SUB;
`FNC_SLL: ALUop = `ALU_SLL;
`FNC_SLT: ALUop = `ALU_SLT;
`FNC_SLTU: ALUop = `ALU_SLTU;
`FNC_XOR: ALUop = `ALU_XOR;
`FNC_SRL_SRA: ALUop = add_rshift_type == `FNC2_SRL ? `ALU_SRL : `ALU_SRA;
`FNC_OR: ALUop = `ALU_OR;
`FNC_AND: ALUop = `ALU_AND;
default: ALUop = `ALU_COPY_B;
endcase
default: ALUop = `ALU_COPY_B;
endcase
end
endmodule
|
`include "sd_defines.v"
module sd_controller_fifo_wba
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
//wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
wb_adr_i, // wb_sel_i,
//Avalon-to-wishbone
wb_ava_write_n, wb_ava_read_n, wb_ava_chipselect, wb_ava_waitrequest,
// WISHBONE master
//SD BUS
sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o,
sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
//PLL CLK_IN
`ifdef SD_CLK_EXT
,sd_clk_i_pad
`endif
);
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [2:0] wb_adr_i; // WISHBONE address input
//input [3:0] wb_sel_i; // WISHBONE byte select input
//input wb_we_i; // WISHBONE write enable input
//input wb_cyc_i; // WISHBONE cycle input
input wb_ava_write_n; // WISHBONE-to-avalon write
input wb_ava_read_n; // WISHBONE-to-avalon read
input wb_ava_chipselect; // WISHBONE-to-avalon read
output wb_ava_waitrequest; // WISHBONE-to-avalon read
//input wb_stb_i; // WISHBONE strobe input
//output reg wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
wire sd_clk_i;
wire wb_we_i; // WISHBONE write enable input
wire wb_cyc_i; // WISHBONE cycle input
wire wb_stb_i; // WISHBONE strobe input
reg wb_ack_o; // WISHBONE acknowledge output
assign wb_we_i = (!wb_ava_write_n) & wb_ava_read_n;
assign wb_cyc_i = (!wb_ava_write_n) | (!wb_ava_read_n);
assign wb_stb_i = wb_ava_chipselect;
assign wb_ava_waitrequest = !wb_ack_o;
`ifdef SD_CLK_EXT
input sd_clk_i_pad;
`endif
`define tx_cmd_fifo 4'h0
`define rx_cmd_fifo 4'h1
`define tx_data_fifo 4'h2
`define rx_data_fifo 4'h3
`define status 4'h4
`define controll 4'h5
`define timer 4'h6
reg [7:0] controll_reg;
reg [7:0] status_reg;
reg [7:0] command_timeout_reg;
`ifdef SD_CLK_BUS_CLK
assign sd_clk_i = wb_clk_i;
`endif
`ifdef SD_CLK_EXT
assign sd_clk_i = sd_clk_i_pad;
`endif
assign sd_clk_o=sd_clk_i;
reg [1:0] wb_fifo_adr_i_writer;
reg [1:0] wb_fifo_adr_i_reader;
wire [1:0] wb_fifo_adr_i;
reg add_token_read;
wire [7:0] wb_fifo_dat_i;
wire [7:0] wb_fifo_dat_o;
reg [7:0] wb_dat_i_storage;
reg [7:0] wb_dat_o_i;
reg time_enable;
assign sd_clk_o_pad = sd_clk_i ;
assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;
assign wb_fifo_dat_i =wb_dat_i_storage;
assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ;
wire [1:4]fifo_full ;
wire [1:4]fifo_empty;
reg wb_fifo_we_i;
reg wb_fifo_re_i;
wire [1:0] sd_adr_o;
wire [7:0] sd_dat_o;
wire [7:0] sd_dat_i;
sd_fifo sd_fifo_0
(
.wb_adr_i (wb_fifo_adr_i ),
.wb_dat_i (wb_fifo_dat_i),
.wb_dat_o (wb_fifo_dat_o ),
.wb_we_i (wb_fifo_we_i),
.wb_re_i (wb_fifo_re_i),
.wb_clk (wb_clk_i),
.sd_adr_i (sd_adr_o ),
.sd_dat_i (sd_dat_o),
.sd_dat_o (sd_dat_i ),
.sd_we_i (sd_we_o),
.sd_re_i (sd_re_o),
.sd_clk (sd_clk_o),
.fifo_full ( fifo_full ),
.fifo_empty (fifo_empty ),
.rst (wb_rst_i) // | controll_reg[0])
) ;
wire [1:0] sd_adr_o_cmd;
wire [7:0] sd_dat_i_cmd;
wire [7:0] sd_dat_o_cmd;
wire [1:0] sd_adr_o_dat;
wire [7:0] sd_dat_i_dat;
wire [7:0] sd_dat_o_dat;
wire [1:0] st_dat_t;
sd_cmd_phy sdc_cmd_phy_0
(
.sd_clk (sd_clk_o),
.rst (wb_rst_i ),//| controll_reg[0]),
.cmd_dat_i ( sd_cmd_dat_i ),
.cmd_dat_o (sd_cmd_out_o ),
.cmd_oe_o (sd_cmd_oe_o ),
.sd_adr_o (sd_adr_o_cmd),
.sd_dat_i (sd_dat_i_cmd),
.sd_dat_o (sd_dat_o_cmd),
.sd_we_o (sd_we_o_cmd),
.sd_re_o (sd_re_o_cmd),
.fifo_full ( fifo_full[1:2] ),
.fifo_empty ( fifo_empty [1:2]),
.start_dat_t (st_dat_t),
.fifo_acces_token (fifo_acces_token)
);
sd_data_phy sd_data_phy_0 (
.sd_clk (sd_clk_o),
.rst (wb_rst_i | controll_reg[0]),
.DAT_oe_o ( sd_dat_oe_o ),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i ),
.sd_adr_o (sd_adr_o_dat ),
.sd_dat_i (sd_dat_i_dat ),
.sd_dat_o (sd_dat_o_dat ),
.sd_we_o (sd_we_o_dat),
.sd_re_o (sd_re_o_dat),
.fifo_full ( fifo_full[3:4] ),
.fifo_empty ( fifo_empty [3:4]),
.start_dat (st_dat_t),
.fifo_acces (~fifo_acces_token)
);
assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;
assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;
assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;
assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;
assign sd_dat_i_dat = sd_dat_i;
assign sd_dat_i_cmd = sd_dat_i;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
status_reg<=0;
else begin
status_reg[0] <= fifo_full[1];
status_reg[1] <= fifo_empty[2];
status_reg[2] <= fifo_full[3];
status_reg[3] <= fifo_empty[4];
end
end
reg delayed_ack;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_ack_o <=0;
else
wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack;
end
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if ( wb_rst_i )begin
command_timeout_reg<=`TIME_OUT_TIME;
wb_dat_i_storage<=0;
controll_reg<=0;
wb_fifo_we_i<=0;
wb_fifo_adr_i_writer<=0;
time_enable<=0;
end
else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin //CS
if (wb_we_i) begin
case (wb_adr_i)
`tx_cmd_fifo : begin
wb_fifo_adr_i_writer<=0;
wb_fifo_we_i<=1&!delayed_ack;
wb_dat_i_storage<=wb_dat_i;
command_timeout_reg<=`TIME_OUT_TIME;
time_enable<=1;
end
`tx_data_fifo : begin
wb_fifo_adr_i_writer<=2;
wb_fifo_we_i<=1&!delayed_ack;
wb_dat_i_storage<=wb_dat_i;
command_timeout_reg<=`TIME_OUT_TIME;
time_enable<=0;
end
`controll : controll_reg <= wb_dat_i;
endcase
end
end
else begin
// wb_fifo_adr_i_writer<=0;
wb_fifo_we_i<=0;
if (!status_reg[1])
time_enable<=0;
if ((command_timeout_reg!=0) && (time_enable))
command_timeout_reg<=command_timeout_reg-1;
end
end
always @(posedge wb_clk_i or posedge wb_rst_i )begin
if ( wb_rst_i) begin
add_token_read<=0;
delayed_ack<=0;
wb_fifo_re_i<=0;
wb_fifo_adr_i_reader<=0;
wb_dat_o_i<=0;
end
else begin
delayed_ack<=0;
wb_fifo_re_i<=0;
if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin //C
delayed_ack<=delayed_ack+1;
add_token_read<=0;
if (!wb_we_i) begin
case (wb_adr_i)
`rx_cmd_fifo : begin
add_token_read<=1;
wb_fifo_adr_i_reader<=1;
wb_fifo_re_i<=1&delayed_ack;
end
`rx_data_fifo :begin
add_token_read<=1;
wb_fifo_adr_i_reader<=3;
wb_fifo_re_i<=1 & delayed_ack;
end
`status : wb_dat_o_i <= status_reg;
`timer : wb_dat_o_i <= command_timeout_reg;
endcase
end
end
end
end
//just to get rid of warnings....
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int N = 2e6 + 10; const long long mod = 1000000007; const double eps = 1e-9; const double PI = acos(-1); template <typename T> inline void read(T &a) { char c = getchar(); T x = 0, f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } a = f * x; } int gcd(int a, int b) { return (b > 0) ? gcd(b, a % b) : a; } int n, m; char str[N]; int main() { int T; read(T); while (T--) { read(n), read(m); scanf( %s , str + 1); int len = strlen(str + 1); int dx = 0, dy = 0; int minx = 0, miny = 0; int maxx = 0, maxy = 0; int ansx = 1, ansy = 1; for (int i = 1; i <= len; i++) { char it = str[i]; if (it == L ) dx--; else if (it == R ) dx++; else if (it == U ) dy--; else if (it == D ) dy++; minx = min(minx, dx); miny = min(miny, dy); maxx = max(maxx, dx); maxy = max(maxy, dy); if ((maxx - minx) >= m || (maxy - miny) >= n) break; ansx = 1 - minx; ansy = 1 - miny; } cout << ansy << << ansx << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string n; cin >> n; long long even = 0; long long odd = 0; long long len = n.length(); long long aeven = 0; long long aodd = 0; long long beven = 0; long long bodd = 0; for (int i = 0; i < len; i++) { if (n[i] == a ) { if (i % 2 == 1) { aodd++; odd += aodd; even += aeven; } else { aeven++; odd += aeven; even += aodd; } } else { if (i % 2 == 1) { bodd++; odd += bodd; even += beven; } else { beven++; odd += beven; even += bodd; } } } cout << even << << odd << endl; }
|
#include <bits/stdc++.h> using namespace std; long long a[500005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, i, j, k, l, m; long long t; cin >> t; long long pret = t; while (t--) { cin >> n >> k; for (i = 1; i <= n; i++) cin >> a[i]; int flag1 = 0; int flag2 = 0; for (i = 1; i <= n; i++) { if (a[i] == k) { flag1 = 1; } if (a[i] != k) { flag2 = 1; } } if (flag1 == 0) { cout << no n ; continue; } if (flag2 == 0) { cout << yes n ; continue; } a[n + 1] = 0; int flag = 0; for (i = 1; i <= n - 1; i++) { if (min(a[i], a[i + 1]) >= k) { flag = 1; break; } } for (i = 2; i <= n - 1; i++) { vector<long long> v; v.push_back(a[i - 1]); v.push_back(a[i + 1]); v.push_back(a[i]); sort(v.begin(), v.end()); if (v[1] >= k) flag = 1; } if (flag) cout << yes n ; else cout << no n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000000000000LL; const int inf = 0x3f3f3f3f; const long double EPS = 1e-9; int dirx[] = {0, 0, -1, 1}; int diry[] = {-1, 1, 0, 0}; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int test; cin >> test; while (test--) { int len; string path; cin >> len >> path; std::map<pair<long long, long long>, int> visit; long long mn = INF; pair<long long, long long> mnpath{-1, -1}, pos{0, 0}; visit[{0, 0}] = 0; for (int i = 0; i < len; i++) { if (path[i] == L ) pos.first += dirx[0], pos.second += diry[0]; else if (path[i] == R ) pos.first += dirx[1], pos.second += diry[1]; else if (path[i] == U ) pos.first += dirx[2], pos.second += diry[2]; else if (path[i] == D ) pos.first += dirx[3], pos.second += diry[3]; if (visit.find(pos) != visit.end()) { int dis = i - visit[pos] + 1; if (mn >= dis) { mn = dis; mnpath = {visit[pos] + 1, i + 1}; } } visit[pos] = i + 1; } if (mn != INF) cout << mnpath.first << << mnpath.second << endl; else cout << -1 << endl; } return 0; }
|
#include<bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int,int>; using pll = pair<ll,ll>; #ifdef eclipse #define debug(...) do{ fprintf(stderr, LINE %d: (%s) = ,__LINE__, #__VA_ARGS__ ); _do(__VA_ARGS__); }while(0) template<typename T> void _do(T &&_x) {cerr << _x << endl;} template<typename T, typename ...S> void _do(T &&_x, S &&..._t) {cerr << _x << , ; _do(_t...);} #else #define debug(...) #endif const int MAXN = 300005; int n, in[MAXN], in2[MAXN]; int calc() { int ans = 0; for (int i = 1; i < n - 1; ++i) { if (in[i] < min(in[i-1], in[i+1])) ans++; else if (in[i] > max(in[i-1], in[i+1])) ans++; } return ans; } int calc2(int idx) { int x, y; x = y = 0; for (int i = idx - 1; i <= idx + 1; ++i) { if (i == 0 || i == n - 1) continue; if (in[i] < min(in[i-1], in[i+1])) y++; else if (in[i] > max(in[i-1], in[i+1])) y++; } for (int i = idx - 1; i <= idx + 1; ++i) { if (i == 0 || i == n - 1) continue; if (in2[i] < min(in2[i-1], in2[i+1])) x++; else if (in2[i] > max(in2[i-1], in2[i+1])) x++; } return x - y; } signed main (){ ios::sync_with_stdio(0),cin.tie(0); int t; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; ++i) cin >> in[i]; for (int i = 0; i < n; ++i) in2[i] = in[i]; int ans, now = calc(); ans = now; for (int i = 1; i < n - 1; ++i) { int tmp = in[i]; in[i] = in[i-1]; ans = min(ans, now - calc2(i)); in[i] = in[i+1]; ans = min(ans, now - calc2(i)); in[i] = tmp; } cout << ans << n ; } return 0; }
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_const;
// Inputs
reg clk;
reg [5:0] addr;
// Outputs
wire [1187:0] out;
wire effective;
reg [1187:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const_ uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
initial begin
// Initialize Inputs
addr = 0; clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {6'b000101, 1182'd0};
#(`P); check;
addr = 8; w_out = {6'b001001, 1182'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 1182'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
|
// nios_solo_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_solo_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_solo_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// synopsys dc_script_begin
// synopsys dc_script_end
module Multiplexer_AC
# (parameter W = 32)
(
input wire ctrl,
input wire [W-1:0] D0,
input wire [W-1:0] D1,
output reg [W-1:0] S
);
always @(ctrl, D0, D1)
case (ctrl)
1'b0: S <= D0;
1'b1: S <= D1;
endcase
endmodule
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin : MUX_ARRAY
case (j)
SWR-1-j:begin : MUX_ARRAY11
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin : MUX_ARRAY12
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
module DW01_bsh_inst( inst_A, inst_SH, B_inst );
parameter A_width = 8;
parameter SH_width = 3;
input [A_width-1 : 0] inst_A;
input [SH_width-1 : 0] inst_SH;
output [A_width-1 : 0] B_inst;
// Instance of DW01_bsh
DW01_bsh #(A_width, SH_width)
U1 ( .A(inst_A), .SH(inst_SH), .B(B_inst) );
endmodule
module Mux_Array_DW
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire [EWR-1:0] Shift_Value_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////ge
//wire [SWR:0] Data_array[EWR+1:0];
wire [SWR:0] Data_array1;
wire [SWR:0] Data_array2;
wire [SWR:0] Data_array3;
wire [SWR:0] Data_array4;
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR+1)) first_rotate(
.Data_i({Data_i, bit_shift_i}),
.select_i(FSM_left_right_i),
.Data_o(Data_array1)
);
wire [EWR-1:0] SValue;
assign SValue = Shift_Value_i+1;
DW01_bsh_inst #(.A_width(SWR+1), .SH_width(EWR)) DW_BSHIFT (
.inst_A(Data_array1),
.inst_SH(SValue),
.B_inst(Data_array2));
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_array2),
.Q(Data_array3)
);
Rotate_Mux_Array #(.SWR(SWR+1))last_rotate(
.Data_i(Data_array3),
.select_i(FSM_left_right_i),
.Data_o(Data_array4)
);
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_array4[SWR:1]),
.Q(Data_o)
);
endmodule
|
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