text stringlengths 59 71.4k |
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: LINEALIZADOR_NORMALIZADOR
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module LINEALIZADOR #(parameter P = 32)(
input wire CLK, //system clock
input wire [P-1:0] T, //VALOR DEL ARGUMENTO DEL LOGARITMO QUE SE DESEA CALCULAR
input wire RST_LN, //system reset
input wire Begin_FSM_LN, //INICIAL EL CALCULO
output wire ACK_LN, //INDICA QUE EL CALCULO FUE REALIZADO
output wire ACK_SUMX,
output wire ACK_SUMY,
output wire ACK_SUMZ,
output wire O_FX, //BANDERA DE OVER FLOW
output wire O_FY, //BANDERA DE OVER FLOW
output wire O_FZ, //BANDERA DE OVER FLOW
output wire U_FX, //BANDERA DE UNDER FLOW
output wire U_FY, //BANDERA DE UNDER FLOW
output wire U_FZ, //BANDERA DE UNDER FLOW
output wire [P-1:0] RESULT //RESULTADO FINAL
);
wire [4:0] CONT_ITERA;
wire RST;
wire MS_1;
wire EN_REG3;
wire EN_REG4;
wire ADD_SUBT;
wire Begin_SUMX;
wire Begin_SUMY;
wire Begin_SUMZ;
wire EN_REG1X;
wire EN_REG1Z;
wire EN_REG1Y;
wire MS_2;
wire MS_3;
wire EN_REG2;
wire CLK_CDIR;
wire EN_REG2XYZ;
// wire ACK_SUMX;
// wire ACK_SUMY;
// wire ACK_SUMZ;
wire EN_MS1;
wire EN_MS2;
wire EN_MS3;
wire EN_ADDSUBT;
wire MS_1_reg;
wire MS_2_reg;
wire MS_3_reg;
wire ADD_SUBT_reg;
Coprocesador_CORDIC C_CORDIC_LN (
.T(T),
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST),
.MS_1(MS_1_reg),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT_reg),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Z(EN_REG1Z),
.EN_REG1Y(EN_REG1Y),
.MS_2(MS_2_reg),
.MS_3(MS_3_reg),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_SUMX(ACK_SUMX),
.ACK_SUMY(ACK_SUMY),
.ACK_SUMZ(ACK_SUMZ),
.O_FX(O_FX),
.U_FX(U_FX),
.O_FY(O_FY),
.U_FY(U_FY),
.O_FZ(O_FZ),
.U_FZ(U_FZ),
.RESULT(RESULT),
.CONT_ITERA(CONT_ITERA)
);
FF_D #(.P(1)) REG_ADDSUBTL( //#(.P(1))
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_ADDSUBT), //ENABLE
.D(ADD_SUBT), //ENTRADA
.Q(ADD_SUBT_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_1(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_2(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS2), //ENABLE
.D(MS_2), //ENTRADA
.Q(MS_2_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_3(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS3), //ENABLE
.D(MS_3), //ENTRADA
.Q(MS_3_reg) //SALIDA
);
FSM_C_CORDIC M_E_LN (
.CLK(CLK), //RELOJ DEL SISTEMA
.RST_LN(RST_LN), //system reset
.ACK_ADD_SUBTX(ACK_SUMX),
.ACK_ADD_SUBTY(ACK_SUMY),
.ACK_ADD_SUBTZ(ACK_SUMZ),
.Begin_FSM_LN(Begin_FSM_LN), //inicia la maquina de estados
.CONT_ITER(CONT_ITERA),
.RST(RST),
.MS_1(MS_1),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2),
.MS_3(MS_3),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_LN(ACK_LN),
.EN_ADDSUBT(EN_ADDSUBT),
.EN_MS1(EN_MS1),
.EN_MS2(EN_MS2),
.EN_MS3(EN_MS3)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename TP> inline bool rd(TP& r) { r = 0; char tmp = getchar(); while (tmp < 0 || tmp > 9 ) { if (tmp == EOF) return 0; tmp = getchar(); } while ( 0 <= tmp && tmp <= 9 ) { r = (r << 3) + (r << 1) + tmp - 0 ; tmp = getchar(); } return 1; } long long a[110], b[110], n; long long dt[110 * 110]; bool vis[1000100]; long long ab(long long num) { if (num >= 0) return num; return -num; } int main() { int t; rd(t); int tot; int nb; while (t--) { rd(n); for (int i = 1; i <= n; i++) rd(a[i]); tot = 0; for (int i = 1; i <= n; i++) for (int j = 1; j < i; j++) dt[++tot] = ab(a[i] - a[j]); sort(dt + 1, dt + tot + 1); tot = unique(dt + 1, dt + tot + 1) - (dt + 1); memset(vis, 0, sizeof(vis)); nb = 0; for (int i = 1; i <= 1000000 && nb != n; i++) if (!vis[i]) { b[++nb] = i; for (int j = 1; j <= tot && i + dt[j] < 1000100; j++) vis[i + dt[j]] = 1; } if (nb != n) printf( NO n ); else { printf( YES n ); for (int i = 1; i <= n; i++) printf( %I64d , b[i]); printf( n ); } } return 0; } |
#include <bits/stdc++.h> const int mod = 1000000007; using namespace std; int dp[5009][5009]; char s1[5009], s2[5009]; int main() { while (scanf( %s%s , s1, s2) == 2) { memset(dp, 0, sizeof(dp)); int len2 = strlen(s2); for (int i = 1; s1[i - 1]; i++) { for (int j = 1; s2[j - 1]; j++) { if (s1[i - 1] == s2[j - 1]) { dp[i][j] = (dp[i - 1][j - 1] + dp[i][j - 1] + 1) % mod; } else dp[i][j] = dp[i][j - 1]; } } int ans = 0; for (int i = 1; s1[i - 1]; i++) ans = (ans + dp[i][len2]) % mod; printf( %d n , ans); } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_a.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_a
//
// No `defines in this module
module ent_a
//
// Generated module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_17_10_5_go,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_15, // will not create a reg in inst_a
sig_16, // reg 16 in inst_a
sig_17, // reg in inst_a, ab and aa
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [5:0] p_mix_sig_17_10_5_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output [7:0] sig_15;
output [9:0] sig_16;
output [4:0] sig_17;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [5:0] p_mix_sig_17_10_5_go;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire [7:0] sig_15;
reg [9:0] sig_16;
reg [4:0] sig_17;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign p_mix_sig_17_10_5_go[5:0] = sig_17[10:5]; // __I_O_SLICE_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14), // Multiline comment 3...
.sig_17(sig_17[10:6]) // reg in inst_a, ab and aa
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14), // Multiline comment 3...
.sig_17(sig_17[5]) // reg in inst_a, ab and aa
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_data_px2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_data_px2(/*AUTOARG*/
// Outputs
pcx_data_px2, pcx_data_rdy_px2, pcx_stall_pq_buf, so,
// Inputs
pcx_data_px_l, pcx_data_rdy_px, pcx_stall_pq, rclk, si, se
);
output [`PCX_WIDTH-1:0] pcx_data_px2;
output pcx_data_rdy_px2;
output pcx_stall_pq_buf;
output so;
input [`PCX_WIDTH-1:0] pcx_data_px_l;
input pcx_data_rdy_px;
input pcx_stall_pq;
input rclk;
input si;
input se;
wire [`PCX_WIDTH-1:0] pcx_data_px2_l;
dff_s #(`PCX_WIDTH) dff_cpx_data(
.din (pcx_data_px_l[`PCX_WIDTH-1:0]),
.q (pcx_data_px2_l[`PCX_WIDTH-1:0]),
.clk (rclk),
.se (1'b0),
.si (`PCX_WIDTH'd0),
.so ());
assign pcx_data_px2 = ~pcx_data_px2_l;
dff_s #(1) dff_cpx_datardy(
.din (pcx_data_rdy_px),
.q (pcx_data_rdy_px2),
.clk (rclk),
.se (1'b0),
.si (1'd0),
.so ());
assign pcx_stall_pq_buf = pcx_stall_pq ;
endmodule // pcx_data_px2
|
#include <bits/stdc++.h> using namespace std; int main() { vector<long long> no; long long int n, m, s = 0, a[100000], l = 1, i; cin >> n >> m; for (i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); for (i = 1; i <= m; i++) { if (a[l] == i) l++; else { s += i; if (s <= m) no.push_back(i); else break; } } cout << no.size() << endl; for (int j = 0; j < no.size(); j++) cout << no[j] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; #define ll long long int #define pb push_back #define mp make_pair #define deb(x) cout<< #x << << x << n ; #define MAX 9223372036854775807 #define MIN -9223372036854775807 #define PI 3.141592653589 #define setbits(n) __builtin_popcountll(n) #define mkunique(a) a.resize(unique(a.begin(),a.end())-a.begin()); const ll mod=998244353; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll T=clock(); ll t; cin>>t; while(t--){ ll n,m; cin>>n>>m; vector<vector<ll>> a(n,vector<ll>(m)); vector<ll> p(n+m); for(ll i=0;i<n;i++){ for(ll j=0;j<m;j++){ cin>>a[i][j]; p[i+j]^=a[i][j]; } } bool ok=false; for(ll i=0;i<n+m;i++) if(p[i]!=0) ok=true; if(ok) cout<< Ashish n ; else cout<< Jeel n ; } cerr<< n nTIME: <<(double)(clock()-T)/CLOCKS_PER_SEC<< sec n ; T = clock(); return 0; } |
`default_nettype none
module dps_utim64(
//System
input wire iCLOCK, //Global Clock
input wire inRESET,
//Timer Clock
input wire iTIMER_CLOCK,
//Counter
input wire iREQ_VALID,
output wire oREQ_BUSY,
input wire iREQ_RW,
input wire [4:0] iREQ_ADDR,
input wire [31:0] iREQ_DATA,
output wire oREQ_VALID,
output wire [31:0] oREQ_DATA,
//Interrupt
output wire oIRQ_VALID,
input wire iIRQ_ACK
);
wire [3:0] utim64a_irq;
wire [3:0] utim64b_irq;
reg [1:0] b_irq_state;
reg [7:0] b_irq_flags;
reg b_flag_buffer_valid;
reg [7:0] b_flag_buffer_flags;
wire utim64a_busy;
wire utim64b_busy;
wire utim64a_req_cc;
wire utim64b_req_cc;
wire utim64_flags_cc;
assign utim64a_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h0 && iREQ_ADDR <= 5'he);
assign utim64b_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h10 && iREQ_ADDR <= 5'h1e);
assign utim64_flags_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && !iREQ_RW && (iREQ_ADDR == 5'h1f);
wire utim64a_out_valid;
wire utim64b_out_valid;
wire [31:0] utim64a_out_data;
wire [31:0] utim64b_out_data;
/************************************
Module Select State
************************************/
parameter L_PARAM_MAIN_STT_IDLE = 1'h0;
parameter L_PARAM_MAIN_STT_RD_WAIT = 1'h1;
reg [1:0] b_modsel; //0:UTIM64A | 1:UTIM64B | 2:FLAGS
reg b_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
b_modsel <= 2'b00;
end
else begin
case(b_state)
L_PARAM_MAIN_STT_IDLE:
begin
if(!iREQ_RW)begin
if(utim64a_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b00;
end
else if(utim64b_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b01;
end
else if(utim64_flags_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b10;
end
end
end
L_PARAM_MAIN_STT_RD_WAIT:
begin
if(utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
end
end
endcase
end
end
/************************************
Timer Module
************************************/
dps_utim64_module UTIM64A(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64a_req_cc),
.oREQ_BUSY(utim64a_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR(iREQ_ADDR[3:0]),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64a_out_valid),
.oREQ_DATA(utim64a_out_data),
//Interrupt
.oIRQ_IRQ(utim64a_irq)
);
dps_utim64_module UTIM64B(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64b_req_cc),
.oREQ_BUSY(utim64b_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR({1'b0, iREQ_ADDR[2:0]}),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64b_out_valid),
.oREQ_DATA(utim64b_out_data),
//Interrupt
.oIRQ_IRQ(utim64b_irq)
);
/************************************
IRQ Flags
************************************/
parameter L_PARAM_IRQ_STT_IDLE = 2'h0;
parameter L_PARAM_IRQ_STT_IRQ = 2'h1;
parameter L_PARAM_IRQ_STT_FLAG = 2'h2;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= 8'h0;
end
else begin
case(b_irq_state)
L_PARAM_IRQ_STT_IDLE:
begin
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
begin
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
/*
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
if(utim64_flags_cc)begin
b_irq_flags <= {utim64a_irq, utim64b_irq};
end
else begin
b_irq_flags <= b_irq_flags | {utim64a_irq, utim64b_irq};
end
end
else begin
if(utim64_flags_cc)begin
b_irq_flags <= 8'h00;
end
else begin
b_irq_flags <= b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_IRQ:
begin
if(iIRQ_ACK)begin
b_irq_state <= L_PARAM_IRQ_STT_FLAG;
end
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
/*
if(iIRQ_ACK)begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
else begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_FLAG:
begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= {utim64b_irq, utim64a_irq};
end
else begin
//Not Flag Load Condition
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
end
default:
begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_flag_buffer_valid <= 1'b0;
b_flag_buffer_flags <= 8'h0;
end
else begin
b_flag_buffer_valid <= utim64_flags_cc;//utim64_flags_cc && (b_irq_state == L_PARAM_IRQ_STT_IRQ);
b_flag_buffer_flags <= b_irq_flags;
end
end
/************************************
Assign
************************************/
assign oIRQ_VALID = (b_irq_state == L_PARAM_IRQ_STT_IRQ)? 1'b1 : 1'b0;
assign oREQ_BUSY = (b_state != L_PARAM_MAIN_STT_IDLE) || utim64a_busy || utim64b_busy;
assign oREQ_VALID = utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid;
assign oREQ_DATA = (b_modsel == 2'h0)? utim64a_out_data : (
(b_modsel == 2'h1)? utim64b_out_data : b_flag_buffer_flags
);
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_clocking.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.1
// \ \ Application : Generated by Xilinx PCI Express Wizard
// / / Filename : pcie_clocking.v
// /___/ /\ Module : pcie_clocking
// \ \ / \
// \___\/\___\
//
//------------------------------------------------------------------------------
module pcie_clocking #
( parameter G_DIVIDE_VAL = 2, // use 2 or 4
parameter REF_CLK_FREQ = 1 // use 0 or 1
)
(
input clkin_pll,
input clkin_dcm,
input rst,
output coreclk,
output userclk,
output gtx_usrclk,
output txsync_clk,
output locked,
input fast_train_simulation_only
);
wire clkfbout;
wire clkfbin;
wire clkout0;
wire clkout1;
wire clkout2;
wire txsync_clkout;
wire clk0;
wire clkfb;
wire clkdv;
wire [15:0] not_connected;
reg [7:0] lock_wait_cntr_7_0;
reg [7:0] lock_wait_cntr_15_8;
reg pll_locked_out_r;
reg pll_locked_out_r_d;
reg pll_locked_out_r_2d;
reg time_elapsed;
parameter G_DVIDED_VAL_PLL = G_DIVIDE_VAL*2;
generate
begin : use_pll
// CALCULATED WAY (easier): must use bitgen -g plladv_xNyM_use_calc:Yes to enable this attribute
// synthesis attribute CLKOUT1_DIVIDE pll1 "4";
// synthesis attribute CLKOUT1_PHASE pll1 "0";
// synthesis attribute CLKOUT1_DUTY_CYCLE pll1 "0.5";
// synthesis attribute PLL_OPT_INV pll1 "001001";
// synthesis attribute PLL_CP pll1 "2";
// synthesis attribute PLL_RES pll1 "8";
PLL_ADV #
(
// 5 for 100 MHz, 2 for 250 MHz
.CLKFBOUT_MULT (5-(REF_CLK_FREQ*3)),
.CLKFBOUT_PHASE(0),
// 10 for 100 MHz, 4 for 250 MHz
.CLKIN1_PERIOD (10-(REF_CLK_FREQ*6)),
.CLKIN2_PERIOD (10-(REF_CLK_FREQ*6)),
.CLKOUT0_DIVIDE(2),
.CLKOUT0_PHASE (0),
.CLKOUT1_DIVIDE(G_DVIDED_VAL_PLL),
.CLKOUT1_PHASE (0),
.CLKOUT2_DIVIDE (4), // always 125 MHz for gtx_usrclk
.CLKOUT2_PHASE (0),
.CLKOUT3_DIVIDE (4), // always 125 MHz for tx_sync
.CLKOUT3_PHASE (0)
// .PLL_OPT_INV (6'b001000),
)
pll_adv_i
(
.CLKIN1(clkin_pll),
.CLKINSEL(1'b1),
.CLKFBIN(clkfbin),
.RST(rst),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(txsync_clkout),
.CLKFBOUT(clkfbout),
//.LOCKED(locked)
.LOCKED(pll_lk_out)
);
// PLL w/ internal feedback loop per UG190 Fig 3-11
assign clkfbin = clkfbout;
BUFG coreclk_pll_bufg (.O(coreclk), .I(clkout0)); // 250 MHz
BUFG gtxclk_pll_bufg (.O(gtx_usrclk), .I(clkout2)); // 125 MHz
BUFG txsync_clk_pll_bufg (.O(txsync_clk), .I(txsync_clkout)); // txsync_clk
if (REF_CLK_FREQ == 1) // 250Mhz
begin
// lock not valid until 100us after PLL is released from reset
always @(posedge clkin_pll or posedge rst)
begin
if(rst)
begin
lock_wait_cntr_7_0 <= 8'h0;
lock_wait_cntr_15_8 <= 8'h0;
pll_locked_out_r <= 1'b0;
time_elapsed <= 1'b0;
end else begin
if ((lock_wait_cntr_15_8 == 8'h80) | time_elapsed)
begin
pll_locked_out_r <= pll_lk_out;
time_elapsed <= 1'b1;
end else begin
lock_wait_cntr_7_0 <= lock_wait_cntr_7_0 + 1'b1;
lock_wait_cntr_15_8 <= (lock_wait_cntr_7_0 == 8'hff) ?
(lock_wait_cntr_15_8 + 1'b1) : lock_wait_cntr_15_8;
end
end
end
end
else // 100Mhz
begin
// lock not valid until 100us after PLL is released from reset
always @(posedge clkin_pll or posedge rst)
begin
if(rst)
begin
lock_wait_cntr_7_0 <= 8'h0;
lock_wait_cntr_15_8 <= 8'h0;
pll_locked_out_r <= 1'b0;
time_elapsed <= 1'b0;
end else begin
if ((lock_wait_cntr_15_8 == 8'h33) | time_elapsed)
begin
pll_locked_out_r <= pll_lk_out;
time_elapsed <= 1'b1;
end else begin
lock_wait_cntr_7_0 <= lock_wait_cntr_7_0 + 1'b1;
lock_wait_cntr_15_8 <= (lock_wait_cntr_7_0 == 8'hff) ?
(lock_wait_cntr_15_8 + 1'b1) : lock_wait_cntr_15_8;
end
end
end
end
// bring locked into PLL output domain
always @(posedge coreclk or posedge rst)
begin
if (rst)
begin
pll_locked_out_r_d <= 0;
pll_locked_out_r_2d <= 0;
end
else
begin
pll_locked_out_r_d <= pll_locked_out_r;
pll_locked_out_r_2d <= pll_locked_out_r_d;
end
end
assign locked = fast_train_simulation_only ?
pll_lk_out : pll_locked_out_r_2d;
end
endgenerate
generate
if (G_DIVIDE_VAL == 1)
begin : sameclk
assign userclk = coreclk;
end
else
begin : notsame
BUFG usrclk_pll_bufg (.O(userclk), .I(clkout1)); // 125 MHz or 62.5 MHz
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int search(int n, long long int a[n], long long int target) { int i; if (a[0] >= target) { printf( 1 %lld n , target); return 0; } int L = 0, R = n - 1; int M; while ((R - L) > 1) { if ((L + R) % 2 == 0) { M = (L + R) / 2; } else { M = (L + R - 1) / 2; } if (a[M] < target) { L = M; } else if (a[M] == target) { printf( %d %lld n , M + 1, target - a[M - 1]); return 0; } else { R = M; } } if (target == a[L]) { printf( %d %lld n , L + 1, target); return 0; } else if (target == a[R]) { printf( %d %lld n , R + 1, target - a[R - 1]); } else { printf( %d %lld n , L + 2, target - a[L]); } } int main() { int n, m, i; scanf( %d %d , &n, &m); long long int a[n]; long long int b[m]; long long int sum = 0; long long int tmp; for (i = 0; i < n; i++) { scanf( %lld , &tmp); a[i] = tmp + sum; sum = tmp + sum; } for (i = 0; i < m; i++) { scanf( %lld , &b[i]); } for (i = 0; i < m; i++) search(n, a, b[i]); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long int a, b; cin >> a >> b; long long int sumo = 0, sume = 0; for (int i = 1;; i++) { sumo = i * i; if (sumo > a) { cout << Vladik << endl; break; } sume = i * (i + 1); if (sume > b) { cout << Valera << endl; break; } } } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module tlu_controller #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter DIVISOR = 8,
parameter WIDTH = 8,
parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17,
parameter TIMESTAMP_N_OF_BIT = 32
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire TRIGGER_CLK, // clock of the TLU FSM, usually connect clock of command sequencer here
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire FIFO_PREEMPT_REQ,
output wire TRIGGER_ENABLED,
output wire [WIDTH-1:0] TRIGGER_SELECTED,
output wire TLU_ENABLED,
input wire [WIDTH-1:0] TRIGGER,
input wire [WIDTH-1:0] TRIGGER_VETO,
input wire TIMESTAMP_RESET,
input wire EXT_TRIGGER_ENABLE,
input wire TRIGGER_ACKNOWLEDGE,
output wire TRIGGER_ACCEPTED_FLAG,
input wire TLU_TRIGGER,
input wire TLU_RESET,
output wire TLU_BUSY,
output wire TLU_CLOCK,
input wire [TIMESTAMP_N_OF_BIT-1:0] EXT_TIMESTAMP,
output wire [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR) ,
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
tlu_controller_core #(
.DIVISOR(DIVISOR),
.ABUSWIDTH(ABUSWIDTH),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(TLU_TRIGGER_MAX_CLOCK_CYCLES),
.WIDTH(WIDTH),
.TIMESTAMP_N_OF_BIT(TIMESTAMP_N_OF_BIT)
) i_tlu_controller_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.TRIGGER_CLK(TRIGGER_CLK),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_PREEMPT_REQ(FIFO_PREEMPT_REQ),
.TRIGGER(TRIGGER),
.TRIGGER_VETO(TRIGGER_VETO),
.TIMESTAMP_RESET(TIMESTAMP_RESET),
.TRIGGER_SELECTED(TRIGGER_SELECTED),
.EXT_TRIGGER_ENABLE(EXT_TRIGGER_ENABLE),
.TRIGGER_ACKNOWLEDGE(TRIGGER_ACKNOWLEDGE),
.TRIGGER_ACCEPTED_FLAG(TRIGGER_ACCEPTED_FLAG),
.TRIGGER_ENABLED(TRIGGER_ENABLED),
.TLU_ENABLED(TLU_ENABLED),
.TLU_TRIGGER(TLU_TRIGGER),
.TLU_RESET(TLU_RESET),
.TLU_BUSY(TLU_BUSY),
.TLU_CLOCK(TLU_CLOCK),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.TIMESTAMP(TIMESTAMP)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mp[2005]; int main() { memset(mp, 0, sizeof mp); long long key[2001], a[2001], n, k, p, i, j; cin >> n >> k >> p; for (i = 0; i < n; i++) { scanf( %lld , a + i); } for (i = 0; i < k; i++) { scanf( %lld , key + i); } sort(a, a + n); sort(key, key + k); long long mn = 1e18; for (i = 0; i < k - n + 1; i++) { long long x = -1; for (int j = i, l = 0; l < n; l++, j++) { long long y = abs(a[l] - key[j]) + abs(p - key[j]); x = max(y, x); } mn = min(x, mn); } cout << mn; } |
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:pointer_basic:1.0
// IP Revision:
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_pointer_basic_0_1 (
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID" *)
input wire s_axi_pointer_basic_io_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY" *)
output wire s_axi_pointer_basic_io_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA" *)
input wire [31 : 0] s_axi_pointer_basic_io_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB" *)
input wire [3 : 0] s_axi_pointer_basic_io_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID" *)
input wire s_axi_pointer_basic_io_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY" *)
output wire s_axi_pointer_basic_io_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID" *)
output wire s_axi_pointer_basic_io_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY" *)
input wire s_axi_pointer_basic_io_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID" *)
input wire s_axi_pointer_basic_io_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY" *)
output wire s_axi_pointer_basic_io_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA" *)
output wire [31 : 0] s_axi_pointer_basic_io_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID" *)
output wire s_axi_pointer_basic_io_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50\
000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY" *)
input wire s_axi_pointer_basic_io_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK\
_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
pointer_basic #(
.C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH(5),
.C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH(32)
) inst (
.s_axi_pointer_basic_io_AWADDR(s_axi_pointer_basic_io_AWADDR),
.s_axi_pointer_basic_io_AWVALID(s_axi_pointer_basic_io_AWVALID),
.s_axi_pointer_basic_io_AWREADY(s_axi_pointer_basic_io_AWREADY),
.s_axi_pointer_basic_io_WDATA(s_axi_pointer_basic_io_WDATA),
.s_axi_pointer_basic_io_WSTRB(s_axi_pointer_basic_io_WSTRB),
.s_axi_pointer_basic_io_WVALID(s_axi_pointer_basic_io_WVALID),
.s_axi_pointer_basic_io_WREADY(s_axi_pointer_basic_io_WREADY),
.s_axi_pointer_basic_io_BRESP(s_axi_pointer_basic_io_BRESP),
.s_axi_pointer_basic_io_BVALID(s_axi_pointer_basic_io_BVALID),
.s_axi_pointer_basic_io_BREADY(s_axi_pointer_basic_io_BREADY),
.s_axi_pointer_basic_io_ARADDR(s_axi_pointer_basic_io_ARADDR),
.s_axi_pointer_basic_io_ARVALID(s_axi_pointer_basic_io_ARVALID),
.s_axi_pointer_basic_io_ARREADY(s_axi_pointer_basic_io_ARREADY),
.s_axi_pointer_basic_io_RDATA(s_axi_pointer_basic_io_RDATA),
.s_axi_pointer_basic_io_RRESP(s_axi_pointer_basic_io_RRESP),
.s_axi_pointer_basic_io_RVALID(s_axi_pointer_basic_io_RVALID),
.s_axi_pointer_basic_io_RREADY(s_axi_pointer_basic_io_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
// bsg_tag_master
//
// 8/30/2016
//
// Usage: send a stream of 0's to reset master node and/or noop.
// Then, send a single <1> followed by a packet:
// < id > < data_not_reset > < payload length > < payload >
// ****************************************************************************
// $clog2(els_p+1) 1 $clog2(max_payload_length+1) (variable size)
//
// To reset client nodes, set data_not_reset to 0, and payload to 1's.
//
//
`include "bsg_defines.v"
`include "bsg_tag.vh"
// will not build in verilator without this
// possibly resulting incorrect behavior :(
// verilator lint_off BLKANDNBLK
module bsg_tag_master
import bsg_tag_pkg::bsg_tag_s;
// els_p is the number of clients to attach
// lg_width_p is the number of bits used to describe the payload size
#(parameter `BSG_INV_PARAM(els_p), `BSG_INV_PARAM(lg_width_p), debug_level_lp=2)
(
// from pins
input clk_i
,input en_i
,input data_i
, output bsg_tag_s [els_p-1:0] clients_r_o
);
`declare_bsg_tag_header_s(els_p,lg_width_p)
localparam max_packet_len_lp = `bsg_tag_max_packet_len(els_p,lg_width_p);
localparam reset_len_lp = `bsg_tag_reset_len(els_p,lg_width_p);
// counts 0..max_packet_len_lp
localparam lg_max_packet_len_lp = `BSG_SAFE_CLOG2(max_packet_len_lp+1);
// synopsys translate_off
if (debug_level_lp > 2)
always @(negedge clk_i)
$display("## bsg_tag_master clients=%b (%m)",clients_r_o);
// synopsys translate_on
logic data_i_r;
always @(posedge clk_i)
data_i_r <= data_i;
// ***************************
// RESET LOGIC
// extra bit to detect carry out in counter
localparam ctr_width_lp = lg_max_packet_len_lp+1;
logic [ctr_width_lp-1:0] zeros_ctr_r;
wire tag_reset_req = zeros_ctr_r[ctr_width_lp-1];
// this self-clearing counter detects a certain number
// of consecutive 0's
// indicating a tag_master reset condition
//
bsg_counter_clear_up #(.max_val_p((1 << ctr_width_lp)-1)
,.init_val_p(0)
) bccu
(.clk_i (clk_i)
,.reset_i(1'b0)
// we clear the counter if we hit the limit
,.clear_i(data_i_r | tag_reset_req)
,.up_i (~data_i_r)
,.count_o(zeros_ctr_r)
);
// veri lator doesn't support -d
// synopsys translate_off
initial
$display("## %m instantiating bsg_tag_master with els_p=%d, lg_width_p=%d, max_packet_len_lp=%d, reset_zero_len=%d"
,els_p,lg_width_p,max_packet_len_lp,reset_len_lp);
// synopsys translate_on
//
// END RESET LOGIC
// ***************************
logic [lg_max_packet_len_lp-1:0] hdr_ptr_r, hdr_ptr_n;
bsg_tag_header_s hdr_r, hdr_n;
// sending
logic v_n;
// value to send
bsg_tag_s bsg_tag_n;
typedef enum logic [1:0] {eStart, eHeader, eTransfer, eStuck} state_e;
state_e state_r, state_n;
// synopsys sync_set_reset "tag_reset_req, data_i_r"
always_ff @(posedge clk_i)
// if we hit the counter AND (subtle bug) there is no valid incoming data that would get lost
if (tag_reset_req & ~data_i_r)
begin
// synopsys translate_off
if (debug_level_lp > 2) $display("## bsg_tag_master RESET time %t (%m)",$time);
// synopsys translate_on
state_r <= eStart;
// we put this here because DC did not currently infer "reset" logic
hdr_ptr_r <= 0;
end
else
begin
state_r <= state_n;
hdr_ptr_r <= hdr_ptr_n;
end
always_ff @(posedge clk_i)
hdr_r <= hdr_n;
// synopsys translate_off
always_ff @(negedge clk_i)
if (state_n != state_r)
if (debug_level_lp > 1) $display("## bsg_tag_master STATE CHANGE # %s --> %s #",state_r.name(),state_n.name());
// synopsys translate_on
always_comb
begin
state_n = state_r;
hdr_ptr_n = hdr_ptr_r;
hdr_n = hdr_r;
// outgoing
v_n = 1'b0;
bsg_tag_n.op = 1'b0;
bsg_tag_n.param = 1'b0;
case (state_r)
// first 1 after zero indicates beginning of packet
eStart:
begin
if (data_i_r)
state_n = eHeader;
hdr_ptr_n = 0;
hdr_n = 0;
end
eHeader:
begin
// synopsys translate_off
if (debug_level_lp > 1)
$display("## bsg_tag_master RECEIVING HEADER (%m) (%d) = %b",hdr_ptr_r,data_i_r);
// synopsys translate_on
hdr_n = { data_i_r, hdr_r[1+:($bits(bsg_tag_header_s)-1)] };
hdr_ptr_n = hdr_ptr_r + 1'b1;
// if we are at the next to last value
if (hdr_ptr_r == lg_max_packet_len_lp'($bits(bsg_tag_header_s)-1))
begin
if (hdr_n.len == 0)
begin
state_n = eStart;
// synopsys translate_off
$display("## bsg_tag_master NULL PACKET, len=0 (%m)");
// synopsys translate_on
end
else
begin
// synopsys translate_off
if (debug_level_lp > 1)
$display("## bsg_tag_master PACKET HEADER RECEIVED (length=%b,data_not_reset=%b,nodeID=%b) (%m) "
,hdr_n.len,hdr_n.data_not_reset,hdr_n.nodeID);
// synopsys translate_on
// if we have data to transfer go to transfer state
state_n = eTransfer;
end
end
end // case: eHeader
eTransfer:
begin
// transmit data
// if hdr_r.reset = 1, then we send <0,data> for hdr_r.len cycles
// otherwise we send <1,data> for hdr_r.len cycles
// typically for reset, we will send 1's.
v_n = 1'b1;
bsg_tag_n.op = hdr_r.data_not_reset;
bsg_tag_n.param = data_i_r;
// synopsys translate_off
if (debug_level_lp > 2)
$display("## bsg_tag_master PACKET TRANSFER op,param=<%b,%b> (%m)", bsg_tag_n.op, bsg_tag_n.param);
// synopsys translate_on
// finishing words
if (hdr_r.len== lg_width_p ' (1))
begin
state_n = eStart;
// synopsys translate_off
if (debug_level_lp > 1) $display("## bsg_tag_master PACKET END (%m)");
// synopsys translate_on
end
hdr_n.len = hdr_r.len - 1;
end
eStuck:
state_n = eStuck;
default:
begin
state_n = eStuck;
// synopsys translate_off
$display("## bsg_tag_master transitioning to error state; be sure to run gate-level netlist to avoid sim/synth mismatch (%m)");
// synopsys translate_on
end
endcase // case (state_r)
end // always_comb
genvar i;
// demultiplex the stream to the target node
wire [els_p-1:0] clients_decode = (v_n << hdr_r.nodeID);
for (i = 0; i < els_p; i=i+1)
begin: rof
always_ff @(posedge clk_i)
begin
clients_r_o[i].op <= clients_decode[i] & bsg_tag_n.op;
clients_r_o[i].param <= clients_decode[i] & bsg_tag_n.param;
end
assign clients_r_o[i].clk = clk_i;
assign clients_r_o[i].en = en_i;
end
endmodule // bsg_tag_master
`BSG_ABSTRACT_MODULE(bsg_tag_master)
// verilator lint_on BLKANDNBLK
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long infl = 1LL << 60; mt19937 rnd(time(0)); inline int myrand(int l, int r) { return rnd() % (r - l + 1) + l; } inline int read() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 , c = getchar(); } return x * f; } const int maxn = 3e5 + 10; vector<int> linker[maxn]; int n, m, q[maxn], dis[maxn], pre[maxn]; bool mark[maxn], vis[maxn]; vector<int> v; void dfs(int x) { vis[x] = 1, v.push_back(x); for (int cur : linker[x]) if (!vis[cur]) dfs(cur); } void print() { vector<int> ans(0); int x = n; while (x) ans.push_back(x), x = pre[x]; reverse(ans.begin(), ans.end()); for (int cur : ans) printf( %d , cur); puts( ); } int main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int u = read(), v = read(); linker[u].push_back(v); linker[v].push_back(u); } int head = 1, tail = 0; memset(dis, 0x3f, sizeof dis); q[++tail] = 1, dis[1] = 0; while (head <= tail) { int x = q[head++]; for (int cur : linker[x]) if (dis[cur] == inf) dis[cur] = dis[x] + 1, q[++tail] = cur, pre[cur] = x; } if (dis[n] <= 4) return printf( %d n , dis[n]), print(), 0; for (int cur : linker[1]) mark[cur] = 1; mark[1] = 1; for (int cur : linker[1]) { for (int to : linker[cur]) if (!mark[to]) { printf( %d n%d %d %d %d %d n , 4, 1, cur, to, 1, n); return 0; } } vis[1] = 1; for (int x : linker[1]) if (!vis[x]) { dfs(x); for (int y : v) { if (mark[y] && linker[y].size() - 1 < v.size() - 1) { printf( %d n , min(dis[n], 5)); if (dis[n] < 5) print(); else { memset(mark, 0, sizeof mark); for (int cur : linker[y]) mark[cur] = 1; mark[y] = 1; for (int cur : linker[y]) if (cur != 1) for (int foo : linker[cur]) if (!mark[foo]) { printf( %d %d %d %d %d %d n , 1, y, cur, foo, y, n); return 0; } } return 0; } } v.clear(); } if (dis[n] == inf) return puts( -1 ), 0; else { printf( %d n , dis[n]); print(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_TB_V
`define SKY130_FD_SC_HS__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 B1 = 1'b0;
#380 B2 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B2 = 1'b1;
#500 B1 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B2 = 1'bx;
#640 B1 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_TB_V
`define SKY130_FD_SC_LS__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int mod = 998244353; const int M = 1e6 + 10; const int N = 1e5 + 10; inline long long read() { long long b = 1, sum = 0; char c = getchar(); while (!isdigit(c)) { if (c == - ) b = -1; c = getchar(); } while (isdigit(c)) { sum = sum * 10 + c - 0 ; c = getchar(); } return b * sum; } int a[N], in[N], d[N]; int n, m, k, T; int vis[N]; vector<int> e[N]; vector<pair<int, int> > ans; void dfs(int x, int _fa, int need) { int i, j; if (x == 1) { for (i = 0; i < e[x].size(); i++) { int y = e[x][i]; ans.push_back({y, i + 1}); dfs(y, x, i); } return; } int cha = need - in[x] + 1, sum = 0; if (in[x] == 1) { ans.push_back({x, need}); } else if (cha >= 0) { ans.push_back({x, cha}); for (i = 0; i < e[x].size(); i++) { int y = e[x][i]; if (y == _fa) continue; ans.push_back({y, cha + sum + 1}); dfs(y, x, cha + sum); sum++; } } else { int now = need + 1, sum = 0; for (i = 0; sum < -cha && i < e[x].size(); i++) { int y = e[x][i]; if (y == _fa) continue; ans.push_back({y, now + 1}); dfs(y, x, now); now++; sum++; } ans.push_back({x, 0}); sum = 0; for (; i < e[x].size(); i++) { int y = e[x][i]; if (y == _fa) continue; ans.push_back({y, sum + 1}); dfs(y, x, sum); sum++; } } ans.push_back({_fa, need + 1}); } int main() { int i, j; n = read(); for (i = 1; i <= n - 1; i++) { int x = read(), y = read(); e[x].push_back(y); e[y].push_back(x); in[x]++; in[y]++; } ans.push_back({1, 0}); dfs(1, 0, 0); printf( %d n , ans.size()); for (i = 0; i < ans.size(); i++) { printf( %d %d n , ans[i].first, ans[i].second); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Programmable Interrupt Controller ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PIC according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pic.v,v $
// Revision 1.4 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_pic(
// RISC Internal Interface
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
pic_wakeup, intr,
// PIC Interface
pic_int
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output pic_wakeup; // Wakeup to the PM
output intr; // interrupt
// exception request
//
// PIC Interface
//
input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
`ifdef OR1200_PIC_IMPLEMENTED
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
`else
wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
`endif
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
`else
wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
`endif
//
// Internal wires & regs
//
wire picmr_sel; // PICMR select
wire picsr_sel; // PICSR select
wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg [31:0] spr_dat_o; // SPR data out
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
if (rst)
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
else if (picmr_sel && spr_write) begin
picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
if (rst)
picsr <= {`OR1200_PIC_INTS{1'b0}};
else if (picsr_sel && spr_write) begin
picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
end else
picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
`OR1200_PIC_OFS_PICMR: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
`endif
default: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
endcase
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
//
// Generate intr
//
assign intr = |um_ints;
//
// Assert pic_wakeup when intr is asserted
//
assign pic_wakeup = intr;
`else
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign intr = pic_int[1] | pic_int[0];
assign pic_wakeup= intr;
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_FUNCTIONAL_V |
#include <bits/stdc++.h> int n; struct camel { int x, d; inline bool operator<(const camel& a) const { return x < a.x; } } c[105]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , &c[i].x, &c[i].d); std::sort(c, c + n); for (int i = 0; i < n; i++) for (int j = i; j < n; j++) if ((c[i].x + c[i].d == c[j].x) && (c[j].x + c[j].d == c[i].x)) { puts( YES ); return 0; } puts( NO ); } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T f = 0, x = 0; char c = getchar(); while (!isdigit(c)) f = c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 48, c = getchar(); return f ? -x : x; } namespace run { inline char getc() { char c = getchar(); while (!isalpha(c)) c = getchar(); return c; } const int N = 2e5 + 9; int head[N], nex[N], to[N], cnt, deg[N]; inline void add(int u, int v) { deg[v]++, nex[++cnt] = head[u], head[u] = cnt, to[cnt] = v; } int n, m, bel[N], tot, dfn[N], num, dwn[N]; inline void dfs(int u) { dfn[u] = ++num; for (int i = head[u]; i; i = nex[i]) dfs(to[i]); dwn[u] = num; } struct node { int x, l, r, v; explicit node() {} node(int _x, int _l, int _r, int _v) : x(_x), l(_l), r(_r), v(_v) {} inline bool operator<(const node &A) const { return x < A.x; } } q[N << 1]; namespace Seg { int sum[N << 2], num[N << 2]; inline void pushup(int k, int l, int r) { if (l == r) return num[k] = sum[k] > 0, void(); if (sum[k]) num[k] = r - l + 1; else num[k] = num[(k << 1)] + num[(k << 1 | 1)]; } inline void modify(int k, int l, int r, int _l, int _r, int v) { if (_l <= l && r <= _r) return sum[k] += v, pushup(k, l, r); if (_l <= ((l + r) >> 1)) modify((k << 1), l, ((l + r) >> 1), _l, _r, v); if (_r > ((l + r) >> 1)) modify((k << 1 | 1), ((l + r) >> 1) + 1, r, _l, _r, v); pushup(k, l, r); } } // namespace Seg inline int id(int x, int y) { return (x - 1) * m + y; } int main() { n = read<int>(), m = read<int>(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { char c = getc(); if (c == D ) { bel[id(i - 1, j)] = id(i, j), bel[id(i, j)] = id(i - 1, j); if (i > 2) add(id(i - 2, j), id(i, j)); if (i + 1 <= n) add(id(i + 1, j), id(i - 1, j)); } if (c == R ) { bel[id(i, j - 1)] = id(i, j), bel[id(i, j)] = id(i, j - 1); if (j > 2) add(id(i, j - 2), id(i, j)); if (j + 1 <= m) add(id(i, j + 1), id(i, j - 1)); } } for (int i = 1; i <= n * m; i++) if (!deg[i]) dfs(i); for (int i = 1; i <= n * m; i++) { int l = dfn[bel[i]], r = dwn[bel[i]]; q[++tot] = node(dfn[i], l, r, 1), q[++tot] = node(dwn[i] + 1, l, r, -1); } sort(q + 1, q + tot + 1); long long ans = 0; for (int i = 1, j, las = 0; i <= tot; i = j + 1) { j = i; while (j + 1 <= tot && q[j + 1].x == q[i].x) j++; ans += 1LL * (q[i].x - las) * Seg::num[1], las = q[i].x; for (int k = i; k <= j; k++) Seg::modify(1, 1, n * m, q[k].l, q[k].r, q[k].v); } printf( %lld n , ans >> 1); return 0; } } // namespace run int main() { return run::main(); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR4_FUNCTIONAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_FUNCTIONAL_PP_V |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream crosspoint
*/
module axis_crosspoint #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire [M_COUNT*$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata_reg = {S_COUNT*DATA_WIDTH{1'b0}};
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_COUNT*KEEP_WIDTH{1'b0}};
reg [S_COUNT-1:0] s_axis_tvalid_reg = {S_COUNT{1'b0}};
reg [S_COUNT-1:0] s_axis_tlast_reg = {S_COUNT{1'b0}};
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid_reg = {S_COUNT*ID_WIDTH{1'b0}};
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest_reg = {S_COUNT*DEST_WIDTH{1'b0}};
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser_reg = {S_COUNT*USER_WIDTH{1'b0}};
reg [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata_reg = {M_COUNT*DATA_WIDTH{1'b0}};
reg [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_COUNT*KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}};
reg [M_COUNT-1:0] m_axis_tlast_reg = {M_COUNT{1'b0}};
reg [M_COUNT*ID_WIDTH-1:0] m_axis_tid_reg = {M_COUNT*ID_WIDTH{1'b0}};
reg [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest_reg = {M_COUNT*DEST_WIDTH{1'b0}};
reg [M_COUNT*USER_WIDTH-1:0] m_axis_tuser_reg = {M_COUNT*USER_WIDTH{1'b0}};
reg [M_COUNT*CL_S_COUNT-1:0] select_reg = {M_COUNT*CL_S_COUNT{1'b0}};
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : {M_COUNT{1'b1}};
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {M_COUNT*USER_WIDTH{1'b0}};
integer i;
always @(posedge clk) begin
if (rst) begin
s_axis_tvalid_reg <= {S_COUNT{1'b0}};
m_axis_tvalid_reg <= {S_COUNT{1'b0}};
select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
end else begin
s_axis_tvalid_reg <= s_axis_tvalid;
for (i = 0; i < M_COUNT; i = i + 1) begin
m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
end
select_reg <= select;
end
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tkeep_reg <= s_axis_tkeep;
s_axis_tlast_reg <= s_axis_tlast;
s_axis_tid_reg <= s_axis_tid;
s_axis_tdest_reg <= s_axis_tdest;
s_axis_tuser_reg <= s_axis_tuser;
for (i = 0; i < M_COUNT; i = i + 1) begin
m_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DATA_WIDTH +: DATA_WIDTH];
m_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*KEEP_WIDTH +: KEEP_WIDTH];
m_axis_tlast_reg[i] <= s_axis_tlast_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
m_axis_tid_reg[i*ID_WIDTH +: ID_WIDTH] <= s_axis_tid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*ID_WIDTH +: ID_WIDTH];
m_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DEST_WIDTH +: DEST_WIDTH];
m_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*USER_WIDTH +: USER_WIDTH];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_LP_V
`define SKY130_FD_SC_LP__DLCLKP_LP_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlclkp_lp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlclkp_lp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_LP_V
|
#include <bits/stdc++.h> using namespace std; long long int hell = 9223372036854775807; bool a[40000000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; while (t--) { for (long long int i = 1; i < 4000000; i++) { a[i] = true; } for (long long int i = 2; i * i < 4000000; i++) { if (a[i]) for (long long int j = i * i; j < 4000000; j = j + i) a[j] = false; } long long int n; cin >> n; vector<long long int> v; long long int k = 0; for (long long int i = 2; i * i <= n; i++) { if (n % i == 0 && a[i]) { v.push_back(i); if (n % (i * i) == 0) v.push_back(i); } if (n % i == 0) k++; } if (k == 0) cout << 1 << endl << 0; else if (v.size() > 1) { if (v[0] * v[1] < n) cout << 1 << endl << v[0] * v[1]; else cout << 2 ; } else cout << 2 ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 9; int seg[MAX * 4][2], n, k, a, b, q, ar[MAX]; void upd(int x, int s = 0, int e = n, int id = 0) { if (e - s == 1) { seg[id][0] = min(ar[s], a), seg[id][1] = min(ar[s], b); return; } int mid = s + e >> 1; if (x < mid) upd(x, s, mid, id * 2 + 1); else upd(x, mid, e, id * 2 + 2); seg[id][0] = seg[id * 2 + 1][0] + seg[id * 2 + 2][0]; seg[id][1] = seg[id * 2 + 1][1] + seg[id * 2 + 2][1]; } pair<int, int> gt(int l, int r, int s = 0, int e = n, int id = 0) { pair<int, int> ret = {0, 0}; if (r <= s || e <= l) return ret; if (l <= s && e <= r) return {seg[id][0], seg[id][1]}; int mid = s + e >> 1; pair<int, int> le = gt(l, r, s, mid, id * 2 + 1), ri = gt(l, r, mid, e, id * 2 + 2); ret = {le.first + ri.first, le.second + ri.second}; return ret; } int main() { cin >> n >> k >> a >> b >> q, n++; while (q--) { int t, d, a; cin >> t >> d; if (t == 1) cin >> a, ar[d] += a, upd(d); else cout << gt(0, d).second + gt(d + k, n).first << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 22:59:56
// Design Name:
// Module Name: delay_line1_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_line1_behavior_tb(
);
reg Clk, ShiftIn;
wire ShiftOut;
delay_line1_behavior DUT (.Clk(Clk), .ShiftIn(ShiftIn), .ShiftOut(ShiftOut));
initial begin
#180 $finish;
end
initial begin
Clk = 0; ShiftIn = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftIn = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftIn = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftIn = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftIn = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_2_V
`define SKY130_FD_SC_HDLL__DFRTP_2_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_2_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > Div[5 * int(1e5 + 100)]; int a[2 * int(1e5 + 100)]; bool Have[2 * int(1e5 + 100)]; int calc[5 * int(1e5 + 100)]; int root[5 * int(1e5 + 100)]; int val = 1; void Prime(int x) { int u = x; root[x] = 1; for (int i = 2; i <= sqrt(x); i++) if (x % i == 0) { Div[u].push_back(pair<int, int>(i, 1)); while (x % i == 0) x /= i; root[u] *= i; } if (x > 1) { Div[u].push_back(pair<int, int>(x, 1)); root[u] *= x; } } void Generate(int x, int n, int maxnumber, int number, int pos) { if (number > maxnumber) { Div[x].push_back(pair<int, int>(val, maxnumber)); return; } for (int j = pos; j <= n - (maxnumber - number); j++) { val *= Div[x][j].first; Generate(x, n, maxnumber, number + 1, j + 1); val /= Div[x][j].first; } } int main() { for (int i = 2; i <= 5e5; i++) { Prime(i); if (i != root[i]) Div[i].clear(); } for (int i = 2; i <= 5e5; i++) if (i == root[i]) { int n = Div[i].size(); for (int j = 2; j <= n; j++) Generate(i, n - 1, j, 1, 0); } int n, q; cin >> n >> q; for (int i = 0; i < n; i++) scanf( %d , &a[i]); int Size = 0; long long ans = 0; for (int i = 1; i <= q; i++) { int x, base; scanf( %d , &x); x--; if (!Have[x]) { Have[x] = true; base = 1; ans += 1ll * Size; Size++; } else { Have[x] = false; base = -1; Size--; ans -= 1ll * Size; } for (int j = 0; j < Div[root[a[x]]].size(); j++) { int base2; if (Div[root[a[x]]][j].second % 2 == 1) base2 = -1; else base2 = 1; if (base == -1) calc[Div[root[a[x]]][j].first]--; ans = ans + (1ll * base * base2 * calc[Div[root[a[x]]][j].first]); if (base == 1) calc[Div[root[a[x]]][j].first]++; } printf( %I64d n , ans); } } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:50:00 2016
/////////////////////////////////////////////////////////////
module ACA_I_N8_Q5 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_18_CI, intadd_18_n3, intadd_18_n2, intadd_18_n1, n2, n3, n4,
n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18;
CMPR32X2TS intadd_18_U4 ( .A(in2[1]), .B(in1[1]), .C(intadd_18_CI), .CO(
intadd_18_n3), .S(res[1]) );
CMPR32X2TS intadd_18_U3 ( .A(in2[2]), .B(in1[2]), .C(intadd_18_n3), .CO(
intadd_18_n2), .S(res[2]) );
CMPR32X2TS intadd_18_U2 ( .A(in2[3]), .B(in1[3]), .C(intadd_18_n2), .CO(
intadd_18_n1), .S(res[3]) );
AO21XLTS U2 ( .A0(n8), .A1(n3), .B0(n9), .Y(n4) );
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_18_CI) );
AOI2BB2XLTS U4 ( .B0(in2[5]), .B1(n5), .A0N(n5), .A1N(in2[5]), .Y(n6) );
OAI2BB2XLTS U5 ( .B0(n17), .B1(n16), .A0N(in1[6]), .A1N(in2[6]), .Y(n18) );
OAI32X2TS U6 ( .A0(n14), .A1(n9), .A2(n8), .B0(n13), .B1(n14), .Y(n10) );
AOI22X2TS U7 ( .A0(in2[4]), .A1(in1[4]), .B0(in2[3]), .B1(in1[3]), .Y(n13)
);
OAI211XLTS U8 ( .A0(in1[2]), .A1(in2[2]), .B0(in2[1]), .C0(in1[1]), .Y(n3)
);
AOI2BB1XLTS U9 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_18_CI), .Y(res[0])
);
NOR2X2TS U10 ( .A(in2[4]), .B(in1[4]), .Y(n14) );
AOI21X1TS U11 ( .A0(in1[4]), .A1(in2[4]), .B0(n14), .Y(n2) );
XOR2XLTS U12 ( .A(n2), .B(intadd_18_n1), .Y(res[4]) );
NAND2X1TS U13 ( .A(in1[2]), .B(in2[2]), .Y(n8) );
NOR2X1TS U14 ( .A(in2[3]), .B(in1[3]), .Y(n9) );
AOI21X1TS U15 ( .A0(n4), .A1(n13), .B0(n14), .Y(n7) );
INVX2TS U16 ( .A(in1[5]), .Y(n5) );
XNOR2X1TS U17 ( .A(n7), .B(n6), .Y(res[5]) );
NOR2X1TS U18 ( .A(in1[6]), .B(in2[6]), .Y(n17) );
AOI21X1TS U19 ( .A0(in1[6]), .A1(in2[6]), .B0(n17), .Y(n12) );
AOI222X1TS U20 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n10), .C0(in1[5]), .C1(n10), .Y(n11) );
XNOR2X1TS U21 ( .A(n12), .B(n11), .Y(res[6]) );
NOR2X1TS U22 ( .A(n14), .B(n13), .Y(n15) );
AOI222X1TS U23 ( .A0(in1[5]), .A1(n15), .B0(in1[5]), .B1(in2[5]), .C0(n15),
.C1(in2[5]), .Y(n16) );
CMPR32X2TS U24 ( .A(in2[7]), .B(in1[7]), .C(n18), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("ACA_I_N8_Q5_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string S, S1, S2, S11, S21; getline(cin, S); int N = S.length(); int i, j, k; int t = 0, t3 = 0; for (i = 0; i < N; i++) { if (S[i] != S[N - i - 1] and t3 == 0) { t3 = 1; if (S[i + 1] == S[N - i - 1]) { t = 1; S1 = S; S1 += S1[N - 1]; for (j = N - 1; j > N - i - 1; j--) { S1[j + 1] = S1[j]; }; S1[N - i] = S1[i]; } if (S[i] == S[N - i - 2]) { t = 1; S2 = S; S2 += S2[N - 1]; for (j = N - 1; j > i - 1; j--) { S2[j + 1] = S2[j]; }; S2[i] = S2[N - i]; } if (t == 0) { t = 1; cout << NA ; return 0; } } } S11 = S1 + 1 ; S21 = S2 + 1 ; if (t3 == 0) { S += S[N - 1]; for (j = N - 1; j >= (N - 1) / 2; j--) { S[j + 1] = S[j]; }; cout << S; return 0; }; int t1 = 0, t2 = 0, t5 = 0, t6 = 0; for (i = 0; i <= N; i++) { if (S1[i] != S1[N - i]) { t1 = 1; } } for (i = 0; i <= N; i++) { if (S2[i] != S2[N - i]) { t2 = 1; } } if (t1 == 0 and S11 != 1 ) { cout << S1; return 0; } if (t2 == 0 and S21 != 1 ) { cout << S2; return 0; } cout << NA ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/04/2016 07:18:18 PM
// Design Name:
// Module Name: Problem2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem2(
input A,
input B,
input C,
input D,
input E,
input F,
output X,
output Y
);
assign X = (A & B & C & D) | (A & B & C & E) | (A & B & D & E) | (C & D & A & E) | (C & D & B & E) | (A & B & C & F) | (A & B & D & F) | (C & D & A & F) | (C & D & B & F) | (C & D & E & F) | (A & B & E & F) | (B & D & E & F) | (A & D & E & F) | (B & C & E & F) | (A & C & E & F);
assign Y = ~((A & B & C & D) | (A & B & C & E) | (A & B & D & E) | (C & D & A & E) | (C & D & B & E) | (A & B & C & F) | (A & B & D & F) | (C & D & A & F) | (C & D & B & F) | (C & D & E & F) | (A & B & E & F) | (B & D & E & F) | (A & D & E & F) | (B & C & E & F) | (A & C & E & F));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_2_V
`define SKY130_FD_SC_HD__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_2_V
|
#include <bits/stdc++.h> using namespace std; string s, dum; int idx = 0; int A[5000]; stack<int> S; int main() { while (cin >> dum) { s += dum; } for (int i = 0; i < s.length(); i++) { dum = ; while (s[i] != > ) { dum += s[i]; i++; } dum += > ; if (dum == <table> ) { S.push(idx); idx++; } else if (dum == </table> ) { S.pop(); } else if (dum == <td> ) { A[S.top()]++; } } sort(A, A + idx); for (int i = 0; i < idx; i++) { if (i > 0) printf( ); printf( %d , A[i]); } printf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using db = double; const int mxn = 300006; const ll mod = 1E9L + 7; int n; ll a[mxn]; ll p[mxn]; int main() { cin >> n; for (int i = 0; i < n; ++i) scanf( %lld , &a[i]); sort(a, a + n); p[0] = 1; for (int i = 1; i <= n; ++i) p[i] = p[i - 1] * 2 % mod; ll ans = 0; for (int i = 0; i < n; ++i) { ans -= a[i] * p[n - 1 - i]; ans += a[i] * p[i]; ans %= mod; } cout << (ans + mod) % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200001; int n; int d[maxn], anc[maxn][18], p[maxn]; array<int, 2> tree[maxn * 4]; int jua(int x, int y) { int dd = d[y] - d[x]; for (int i = 17; i >= 0; i--) { if (dd >= 1 << i) { y = anc[y][i]; dd -= (1 << i); } } return x == y; } int lca(int x, int y) { if (d[x] < d[y]) swap(x, y); int dd = d[x] - d[y]; for (int i = 17; i >= 0; i--) { if (dd >= 1 << i) { x = anc[x][i]; dd -= (1 << i); } } if (x == y) return x; for (int i = 17; i >= 0; i--) { if (anc[x][i] != anc[y][i]) { x = anc[x][i]; y = anc[y][i]; } } return anc[x][0]; } void cmb2(array<int, 2> &p0, int x) { if (p0[0] == -1 || x == -1) { p0[0] = -1; p0[1] = -1; return; } if (d[p0[0]] > d[p0[1]]) swap(p0[0], p0[1]); if (jua(p0[0], p0[1])) { if (d[x] >= d[p0[0]] && d[x] <= d[p0[1]] && jua(x, p0[1])) { return; } if (jua(p0[1], x)) { p0[1] = x; return; } int c = lca(p0[1], x); if (d[c] > d[p0[0]]) { p0[0] = p0[1] = -1; return; } p0[0] = x; } else { int c = lca(p0[0], p0[1]); if (d[x] >= d[c] && (jua(x, p0[0]) || jua(x, p0[1]))) { return; } if (jua(p0[0], x)) { p0[0] = x; return; } if (jua(p0[1], x)) { p0[1] = x; return; } p0[0] = p0[1] = -1; } return; } array<int, 2> cmb(array<int, 2> p1, array<int, 2> p2) { cmb2(p1, p2[0]); cmb2(p1, p2[1]); return p1; } void update(int v, array<int, 2> pp, int k, int l, int r) { if (l == r) { tree[k] = pp; return; } int mid = (l + r) / 2; if (v <= mid) update(v, pp, k * 2, l, mid); else update(v, pp, k * 2 + 1, mid + 1, r); tree[k] = cmb(tree[k * 2], tree[k * 2 + 1]); } int query(int k, int l, int r, array<int, 2> p) { array<int, 2> t = tree[k]; if (l) t = cmb(t, p); if (t[0] != -1) { return r + 1; } if (l == r) return l; int mid = (l + r) / 2; array<int, 2> tt = tree[k * 2]; if (l) tt = cmb(tt, p); if (tt[0] != -1) return query(k * 2 + 1, mid + 1, r, tt); else return query(k * 2, l, mid, p); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> p[i]; } memset(anc[0], -1, sizeof(anc[0])); anc[1][0] = -1; d[1] = 1; for (int i = 1; i < n; i++) { int x; cin >> x, x--; anc[i][0] = x; d[i] = d[x] + 1; } for (int i = 1; i < n; i++) { for (int j = 0; j < 17; j++) { if (anc[i][j] != -1) anc[i][j + 1] = anc[anc[i][j]][j]; else anc[i][j + 1] = -1; } } for (int i = 0; i < n; i++) { update(p[i], {i, i}, 1, 0, n - 1); } int q; cin >> q; while (q--) { int ju; cin >> ju; if (ju == 1) { int x, y; cin >> x >> y; x--, y--; swap(p[x], p[y]); update(p[x], {x, x}, 1, 0, n - 1); update(p[y], {y, y}, 1, 0, n - 1); } else { cout << query(1, 0, n - 1, {}) << endl; } } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 9; int n; int fs[maxn]; int pj[maxn]; long long ansji, ansou; void solve() { int i; for (i = 1; i <= n; ++i) fs[i] += fs[i - 1]; for (i = 1; i <= n; ++i) { pj[i] = pj[i - 1] + (fs[i] & 1); } for (i = 1; i <= n; ++i) { if (fs[i] & 1) { ansji += i - pj[i - 1]; ansou += pj[i - 1]; } else { ansji += pj[i - 1]; ansou += i - pj[i - 1]; } } } void _solve() { solve(); cout << ansji << << ansou << endl; } void _prepare() { cin >> n; for (int i = 1; i <= n; ++i) { int x; cin >> x; fs[i] = x < 0; } } int _main_prog() { _prepare(); _solve(); return 0; } int main() { return _main_prog(); } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m, k; int a[N]; int b[N]; int main() { cin >> n >> m >> k; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n - 1; ++i) { b[i] = a[i + 1] - a[i] - 1; } sort(b, b + n - 1); int kk = n; long long ans = n; for (int i = 0; i < n - 1; ++i) { if (kk == k) break; ans += b[i]; kk--; if (kk == k) break; } cout << ans << endl; return 0; } |
// megafunction wizard: %LPM_FIFO+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_40x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_40x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw);
input [39:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [39:0] q;
output full;
output empty;
output [6:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "40"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL data[39..0]
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL q[39..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_40x128_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V |
//=======================================================
// ECE3400 Fall 2017
// Lab 3: Template top-level module
//
// Top-level skeleton from Terasic
// Modified by Claire Chen for ECE3400 Fall 2017
//=======================================================
`define ONE_SEC 25000000
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
localparam ONE_SEC = 25000000; // one second in 25MHz clock cycles
localparam white = 8'b11111111;
localparam black = 8'b0;
localparam pink = 8'b11110011;
localparam cyan = 8'b10011011;
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
/////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg CLOCK_25;
wire reset; // active high reset signal
wire [9:0] PIXEL_COORD_X; // current x-coord from VGA driver
wire [9:0] PIXEL_COORD_Y; // current y-coord from VGA driver
reg [7:0] PIXEL_COLOR; // input 8-bit pixel color for current coords
wire [2:0] GRID_X;
wire [2:0] GRID_Y;
reg grid [19:0][7:0];
reg visited [19:0];
GRID_SELECTOR gridSelector(
.CLOCK_50(CLOCK_50),
.PIXEL_COORD_X(PIXEL_COORD_X),
.PIXEL_COORD_Y(PIXEL_COORD_Y),
.GRID_X(GRID_X),
.GRID_Y(GRID_Y)
);
reg[7:0] grid1[3:0] [4:0];
reg[7:0] currentGrid;
reg[24:0] counter;
//state machine
always @(posedge CLOCK_25) begin
if (GRID_X > 3) begin //colors squares that aren't in the 4x5 grid black
PIXEL_COLOR <= black;
end
else begin
currentGrid <= grid1[GRID_X][GRID_Y];
if (currentGrid == 0) begin // if no input, current square white
PIXEL_COLOR <= white;
end
if (currentGrid[0] == 1) begin //if LSB is 1, current square pink
PIXEL_COLOR <= pink;
end
end
end
reg[2:0] x;
reg[2:0] y;
//demo
// always @(posedge CLOCK_25) begin
// if (reset) begin
// counter <= 25'b0;
// x <= 3'b0;
// y <= 3'b0;
// end
// if (counter == ONE_SEC) begin
// counter <= 25'b0;
// x <= x + 3'b1;
// y <= y + 3'b1;
//
// grid1[x][y] <= 8'b1;
// end
//
// else begin
// counter <= counter+ 25'b1;
// end
// end
//assign GPIO_0_D[31] = 1'd1;
//assign GPIO_0_D[33] = 1'd1;
reg [24:0] led_counter; // timer to keep track of when to toggle LED
reg led_state; // 1 is on, 0 is off
// Module outputs coordinates of next pixel to be written onto screen
VGA_DRIVER driver(
.RESET(reset),
.CLOCK(CLOCK_25),
.PIXEL_COLOR_IN(PIXEL_COLOR),
.PIXEL_X(PIXEL_COORD_X),
.PIXEL_Y(PIXEL_COORD_Y),
.PIXEL_COLOR_OUT({GPIO_0_D[9],GPIO_0_D[11],GPIO_0_D[13],GPIO_0_D[15],GPIO_0_D[17],GPIO_0_D[19],GPIO_0_D[21],GPIO_0_D[23]}),
.H_SYNC_NEG(GPIO_0_D[7]),
.V_SYNC_NEG(GPIO_0_D[5])
);
assign reset = ~KEY[0]; // reset when KEY0 is pressed
// assign PIXEL_COLOR = 8'b000_111_00; // Green
assign LED[0] = led_state;
//=======================================================
// Structural coding
//=======================================================
// Generate 25MHz clock for VGA, FPGA has 50 MHz clock
always @ (posedge CLOCK_50) begin
CLOCK_25 <= ~CLOCK_25;
end // always @ (posedge CLOCK_50)
// Simple state machine to toggle LED0 every one second
always @ (posedge CLOCK_25) begin
if (reset) begin
led_state <= 1'b0;
led_counter <= 25'b0;
x <= 3'b0;
y <= 3'b0;
grid1[0][0] = 8'b0;
grid1[0][1] = 8'b0;
grid1[0][2] = 8'b0;
grid1[0][3] = 8'b0;
grid1[0][4] = 8'b0;
grid1[1][0] = 8'b0;
grid1[1][1] = 8'b0;
grid1[1][2] = 8'b0;
grid1[1][3] = 8'b0;
grid1[1][4] = 8'b0;
grid1[2][0] = 8'b0;
grid1[2][1] = 8'b0;
grid1[2][2] = 8'b0;
grid1[2][3] = 8'b0;
grid1[2][4] = 8'b0;
grid1[3][0] = 8'b0;
grid1[3][1] = 8'b0;
grid1[3][2] = 8'b0;
grid1[3][3] = 8'b0;
grid1[3][4] = 8'b0;
end
if (led_counter == ONE_SEC) begin
led_state <= ~led_state;
led_counter <= 25'b0;
if (y==3'b100) begin // you're at the bottom of the grid
y<= 3'b0;
x<=x+3'b001;
end
else begin
y <= y + 3'b1;
end
grid1[x][y] <= 8'b1;
end
else begin
led_state <= led_state;
led_counter <= led_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
endmodule |
#include <bits/stdc++.h> const double PI = 3.141592653589793238460; using namespace std; vector<int> d; vector<int> l; vector<int> r; vector<int> u; bool isPossibleL(string st) { for (char ch : st) { for (int n : l) if (ch - 0 == n) return false; } return true; } bool isPossibleR(string st) { for (char ch : st) { for (int n : r) if (ch - 0 == n) return false; } return true; } bool isPossibleU(string st) { for (char ch : st) { for (int n : u) if (ch - 0 == n) return false; } return true; } bool isPossibleD(string st) { for (char ch : st) { for (int n : d) if (ch - 0 == n) return false; } return true; } int main() { l.push_back(1), l.push_back(4), l.push_back(7), l.push_back(0); r.push_back(3), r.push_back(6), r.push_back(9), r.push_back(0); d.push_back(7), d.push_back(0), d.push_back(9); u.push_back(1), u.push_back(2), u.push_back(3); int n; string st; cin >> n >> st; if (isPossibleL(st) || isPossibleR(st) || isPossibleU(st) || isPossibleD(st)) cout << NO ; else cout << YES ; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; int n1, n2, n3; cin >> n1 >> n2 >> n3; vector<int> v[n + 1]; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } auto out = []() { cout << NO n ; exit(0); }; if (n2 == 0) { if (m == 0) { cout << YES n ; cout << string(n1, 1 ) + string(n3, 3 ) << n ; exit(0); } else out(); } vector<int> vis(n + 1, 0); vector<vector<int>> one; vector<vector<int>> two; vector<vector<array<int, 2>>> dp(n + 1, vector<array<int, 2>>(n + 1, {0, 0})); dp[0][0] = {-1, 1}; int comp = 0; for (int i = 1; i <= n; i++) { if (vis[i] != 0) continue; comp++; queue<int> q; q.push(i); vis[i] = 1; vector<int> d[3]; vector<int> cnt(3, 0); d[1].push_back(i); cnt[1] = 1; while (!q.empty()) { int x = q.front(); q.pop(); for (int to : v[x]) { if (vis[to] == 0) { q.push(to); vis[to] = 3 - vis[x]; d[vis[to]].push_back(to); cnt[vis[to]]++; } else if (vis[to] == vis[x]) out(); } } one.push_back(d[1]); two.push_back(d[2]); for (int j = 0; j <= n; j++) { if (dp[comp - 1][j][1] == 0) continue; for (int k = 1; k <= 2; k++) if (dp[comp][j + cnt[k]][1] == 0) dp[comp][j + cnt[k]] = {(int)one.size() - 1, k}; } } if (dp[comp][n2][1] == 0) out(); string res(n + 1, 0 ); int c = comp; int now = n2; while (now > 0) { if (dp[c][now][1] == 1) { for (int x : one[dp[c][now][0]]) res[x] = 2 ; now -= one[dp[c][now][0]].size(); } else { for (int x : two[dp[c][now][0]]) res[x] = 2 ; now -= two[dp[c][now][0]].size(); } c--; } for (int i = 1; i <= n; i++) { if (res[i] == 2 ) continue; if (n1 > 0) { res[i] = 1 ; n1--; } else res[i] = 3 ; } cout << YES n ; cout << res.substr(1, n) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string second; int ans = 0, a = 1; cin >> second; int k = second.length() - 1; for (int i = 1; i < second.size(); i++) { ans += (1 << i); } for (int i = 0; i < second.length(); i++) { if (i == k) { if (second[i] == 4 ) ans += 1; else ans += 2; continue; } if (second[i] == 4 ) continue; ans += (1 << (k - i)); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 50; const int MOD = 1e9 + 9; int n, k, a, b, c, d, m, L, R, tot = 1; pair<int, int> cities[MAXN]; struct TreeNode { int x, l, r, lson, rson; pair<int, int> v; } tree[MAXN]; int newNode(int &x) { return x = ++tot; } pair<int, int> calc(pair<int, int> l, pair<int, int> r) { return {l.second + r.second, max(l.first + r.second, l.second + r.first) + 1}; } void build(int o, int l, int r) { int max_y = -1, max_id = l; for (int i = l; i <= r; i++) { if (cities[i].second > max_y) { max_y = cities[i].second; max_id = i; } } tree[o].l = cities[l].first; tree[o].r = cities[r].first; tree[o].x = cities[max_id].first; if (l < max_id) build(newNode(tree[o].lson), l, max_id - 1); if (max_id < r) build(newNode(tree[o].rson), max_id + 1, r); tree[o].v = calc(tree[tree[o].lson].v, tree[tree[o].rson].v); } pair<int, int> query(int o, int l, int r) { if (o == 0 || l > tree[o].r || r < tree[o].l) return {-1, 0}; if (l <= tree[o].l && tree[o].r <= r) return tree[o].v; if (r < tree[o].x) return query(tree[o].lson, l, r); if (l > tree[o].x) return query(tree[o].rson, l, r); return calc(query(tree[o].lson, l, r), query(tree[o].rson, l, r)); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < k; i++) { scanf( %d%d , &cities[i].first, &cities[i].second); } scanf( %d%d%d%d , &a, &b, &c, &d); for (int i = k; i < n; i++) { cities[i].first = (1LL * a * cities[i - 1].first + b) % MOD; cities[i].second = (1LL * c * cities[i - 1].second + d) % MOD; } sort(cities, cities + n); tree[0].v = {-1, 0}; build(1, 0, n - 1); scanf( %d , &m); while (m--) { scanf( %d%d , &L, &R); printf( %d n , query(1, L, R).second); } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_oebscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_oebscan(bsr_si ,update_dr ,in ,bsr_hiz_l ,
test_mode_oe ,mode_ctl ,shift_dr ,clock_dr ,out_type ,bsr_so ,out
);
output bsr_so ;
output out ;
input bsr_si ;
input update_dr ;
input in ;
input bsr_hiz_l ;
input test_mode_oe ;
input mode_ctl ;
input shift_dr ;
input clock_dr ;
input out_type ;
wire upd_hiz ;
wire net32 ;
wire net40 ;
wire net44 ;
wire net51 ;
wire net53 ;
wire net55 ;
wire net60 ;
bw_u1_muxi21_2x bs_mux (
.z (net44 ),
.d0 (in ),
.d1 (upd_hiz ),
.s (net32 ) );
bw_u1_inv_1x se_inv (
.z (net53 ),
.a (test_mode_oe ) );
bw_u1_nand3_1x hiz_nand (
.z (net55 ),
.a (net51 ),
.b (bsr_hiz_l ),
.c (net53 ) );
bw_u1_inv_2x ctl_inv2x (
.z (net32 ),
.a (net60 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (net51 ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_nand2_1x hiz_se_nand (
.z (upd_hiz ),
.a (net55 ),
.b (net40 ) );
bw_u1_nand2_1x se_nand (
.z (net40 ),
.a (test_mode_oe ),
.b (out_type ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net44 ) );
bw_u1_nor2_1x ctl_nor1x (
.z (net60 ),
.a (mode_ctl ),
.b (test_mode_oe ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; double L, R; int n, i; int a[10000]; double jami; long long ans1, ans2, ans; int main() { L = 10.0; R = 1000000000; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) { L = max(L, (double)((double)a[i] / i) * 10.0); R = min(R, (double)((double)(a[i] + 1) / i) * 10.0); } R -= 0.000000001; jami = (n + 1) * L; jami -= 10 * a[n]; jami = floor(jami); ans1 = jami / 10; jami = (n + 1) * R; jami -= 10 * a[n]; jami = floor(jami); ans2 = jami / 10; if (ans1 == ans2) { cout << unique << endl; cout << a[n] + ans1 << endl; return 0; } cout << not unique << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { double ans, B, H; cin >> ans; double ff = 999999999.9; for (double h = 1; h <= 10; h++) { for (double b = 1; b <= 10; b++) { double sum = h * b / sqrt(4 * h * h + b * b); double d = fabs(ans - sum); if (d < ff) { ff = d; B = b; H = h; } } } cout << B << << H << endl; } |
#include <bits/stdc++.h> using namespace std; int t, n, pl; string s; int main() { std::ios::sync_with_stdio(false); cin >> t; for (int qqw = 1; qqw <= t; qqw++) { cin >> n; cin >> s; pl = -1; for (int i = 1; i <= n; i++) if (s[i - 1] == 0 ) pl = i; if (pl > 0) { if (n % 2 == 0) { if (pl <= n / 2) { cout << pl << << n << << pl + 1 << << n << n ; continue; } cout << 1 << << pl << << 1 << << pl - 1 << n ; } else { if (pl <= n / 2) { cout << pl << << n << << pl + 1 << << n << n ; continue; } cout << 1 << << pl << << 1 << << pl - 1 << n ; } } else { cout << 1 << << n - 1 << << 2 << << n << n ; continue; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 1000005; int sp[maxN]; void seive() { for (int i = 2; i <= 1000000; ++i) { if (sp[i] != 0) continue; for (int j = i; j <= 1000000; j += i) { if (sp[j] == 0) sp[j] = i; } } } int nxtpow(int x) { int p = 1; while (p < x) p <<= 1; return p; } int main() { seive(); int n; scanf( %d , &n); int pow = 0; int x = n; int val = 1; vector<int> pows; while (x > 1) { int p = sp[x]; int cnt = 1; while (x > 1 && sp[x / p] == p) { x /= p; ++cnt; } x /= p; pow = max(pow, nxtpow(cnt)); val *= p; pows.push_back(cnt); } int ans = 0; for (int x : pows) { if (x != pow) { ++ans; break; } } while (pow > 1) { pow >>= 1; ++ans; } printf( %d %d n , val, ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 500; long long dp[N]; long long n; void init() { dp[0] = 1ll; dp[1] = 2ll; for (int i = 2; i < N; i++) { dp[i] = dp[i - 2] + dp[i - 1]; } } int main() { init(); while (cin >> n) { int cur = 0; while (dp[cur] <= n) cur++; cout << cur - 1 << endl; } return 0; } |
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
Debug State Capture
Trigger captures the state of 3 x 32-bit words (96 bits total). A
clock counter is started. Everytime the 96-bit input bits change
an entry is made in the buffer with the previous state and how many
clocks that state was detected.
Addr
0x000 : Control/Status
0x004 : Live Input Data (32-bit Word 0)
0x008 : Live Input Data (32-bit Word 1)
0x00C : Live Input Data (32-bit Word 2)
0x010 : [Clock Count #0]
0x014 : [Word0 #0]
0x018 : [Word1 #0]
0x01C : [Word2 #0]
0x020 : [Clock Count #1]
0x024 : [Word0 #1]
0x028 : [Word1 #1]
0x02C : [Word2 #1]
(...)
16-bytes per state detected. First word is "clock count".
Next three words are state detected for the clock count.
(...)
0xFFF :
Control -
[0] Arm Trigger
[1] Force Trigger (Arm must also be set)
[2] Sample Done
[3] Sample Running
[7-4] RESERVED
[15-8] Mode (to debug target to select data/trigger settings)
[31-16] RESERVED
*/
module debug_state
(
input av_clk,
input av_rst,
input [9:0] av_address,
input av_write,
input av_read,
input [31:0] av_writedata,
output reg [31:0] av_readdata,
output reg av_readdatavalid,
output reg [7:0] lsa_mode,
input lsa_clk,
input lsa_trigger,
input [95:0] lsa_data
);
parameter INIT_ARMED = 1;
parameter INIT_FORCED = 0;
parameter INIT_MODE = 8'd0;
//
// Clock domain crossing
//
reg [1:0] sync_av;
reg [1:0] sync_lsa;
reg [1:0] sync_lsa_av;
reg ctrl_arm;
reg av_arm;
reg lsa_arm;
reg ctrl_force;
reg av_force;
reg lsa_force;
reg [7:0] ctrl_mode;
reg [7:0] av_mode;
// lsa_mode in port list
reg sample_done;
reg av_done;
reg lsa_done;
wire sample_running;
reg av_running;
reg lsa_running;
wire [95:0] sample_live = lsa_data;
reg [95:0] av_live;
reg [95:0] lsa_live;
always @ (posedge av_clk or posedge av_rst)
if (av_rst)
begin
sync_lsa_av <= 2'd0;
sync_av <= 2'd0;
end
else
begin
sync_lsa_av <= sync_lsa;
sync_av <= (sync_lsa_av == sync_av) ? sync_av + 2'd1 : sync_av;
end
always @ (posedge lsa_clk)
sync_lsa <= sync_av;
always @ (posedge av_clk)
if (sync_av == 2'b01)
{av_live, av_running, av_done, av_mode, av_force, av_arm} <=
{lsa_live, lsa_running, lsa_done, ctrl_mode, ctrl_force, ctrl_arm};
always @ (posedge lsa_clk)
if (sync_lsa == 2'b10)
{lsa_live, lsa_running, lsa_done, lsa_mode, lsa_force, lsa_arm} <=
{sample_live, sample_running, sample_done, av_mode, av_force, av_arm};
//
// Sample state machine
//
reg [8:0] sample_waddr;
assign sample_running = sample_waddr[8];
reg [127:0] sample_data[255:0];
reg [95:0] sample_state;
reg [95:0] sample_state_d1;
wire sample_next = (sample_state != sample_state_d1);
reg [31:0] sample_cnt;
always @ (posedge lsa_clk)
sample_done <= lsa_arm && (sample_waddr == 8'd0);
always @ (posedge lsa_clk)
if (!lsa_arm)
sample_waddr <= 9'h001;
else if (!sample_waddr[8] && |sample_waddr[7:0])
sample_waddr <= sample_waddr + 9'd1;
else if (sample_waddr == 9'h100)
sample_waddr <= (lsa_force || lsa_trigger) ? 9'h101 : 9'h100;
else if (sample_next && (sample_waddr != 9'h000))
sample_waddr <= sample_waddr + 9'd1;
always @ (posedge lsa_clk)
begin
sample_state <= lsa_data;
sample_state_d1 <= sample_state;
sample_cnt <= (!sample_running || sample_next) ? 32'd1 :
(sample_cnt != 32'hFFFFFFFF) ? sample_cnt + 32'd1
: sample_cnt;
end
always @ (posedge lsa_clk)
if (lsa_arm)
sample_data[sample_waddr[7:0]] <= (sample_waddr[8]) ? {sample_state_d1, sample_cnt} : 96'd0;
//
// Control register
//
reg init_cycle;
always @ (posedge av_clk or posedge av_rst)
if (av_rst)
begin
ctrl_arm <= 1'b0;
ctrl_force <= 1'b0;
ctrl_mode <= 8'd0;
init_cycle <= 1'b0;
end
else if (!init_cycle)
begin
ctrl_arm <= (INIT_ARMED != 0);
ctrl_force <= (INIT_FORCED != 0);
ctrl_mode <= INIT_MODE;
init_cycle <= 1'b1;
end
else if (av_write && (av_address == 10'd0))
begin
ctrl_arm <= av_writedata[0];
ctrl_force <= av_writedata[1];
ctrl_mode <= av_writedata[15:8];
end
always @ (posedge av_clk)
av_readdatavalid <= av_read;
always @ (posedge av_clk)
if (av_address == 10'd0)
av_readdata <= {16'd0, ctrl_mode, 4'd0, av_running, av_done, ctrl_force, ctrl_arm};
else if (av_address == 10'd1)
av_readdata <= av_live[31:0];
else if (av_address == 10'd2)
av_readdata <= av_live[63:32];
else if (av_address == 10'd3)
av_readdata <= av_live[95:64];
else if (av_address[1:0] == 2'b00)
av_readdata <= sample_data[av_address[9:2]][31:0];
else if (av_address[1:0] == 2'b01)
av_readdata <= sample_data[av_address[9:2]][63:32];
else if (av_address[1:0] == 2'b10)
av_readdata <= sample_data[av_address[9:2]][95:64];
else
av_readdata <= sample_data[av_address[9:2]][127:96];
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isValid(string s) { bool valid = true; if (s.length() < 1 || s.length() > 16) return false; for (int i = 0; i < s.length(); i++) { if (s[i] < 48 || (s[i] > 57 && s[i] < 65) || (s[i] > 90 && s[i] < 95) || (s[i] > 95 && s[i] < 97) || s[i] > 122) { valid = false; break; } } return valid; } int main() { string s; cin >> s; size_t f1, f2, f3; f1 = s.find( @ ); if (f1 != string::npos) { string t; t = s.substr(0, int(f1)); if (isValid(t)) { bool resource = false; f2 = s.find( / ); if (f2 != string::npos && int(f2) > int(f1)) { resource = true; t = s.substr(int(f1) + 1, int(f2) - int(f1) - 1); } else t = s.substr(int(f1) + 1); if (t.length() < 1 || t.length() > 32) { cout << NO ; return 0; } do { f3 = t.find( . ); if (f3 != string::npos && int(f3) > 0) { string aux = t.substr(0, int(f3)); if (isValid(aux)) t.erase(0, int(f3) + 1); else { cout << NO ; return 0; } } else { if (isValid(t)) { if (resource) { string aux = s.substr(int(f2) + 1); if (isValid(aux)) cout << YES ; else cout << NO ; return 0; } else { cout << YES ; return 0; } } else { cout << NO ; return 0; } } } while (f3 != string::npos); } else { cout << NO ; return 0; } } else { cout << NO ; return 0; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_4_V
`define SKY130_FD_SC_MS__A311OI_4_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// File : instruction_memory.v
// Creation date : 28.11.2017
// Creation time : 12:45:25
// Description : Used to supplant instruction memory in simulations. NOTICE: Ports are described in interfaces.local_memory.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:cpu.logic.test:instruction_memory:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic.test/instruction_memory/1.0/instruction_memory.1.0.xml
//-----------------------------------------------------------------------------
module instruction_memory #(
parameter INSTRUCTION_ADDRESS_WIDTH = 8, // Width of an instruction address.
parameter INSTRUCTION_WIDTH = 28 // Total width of an instruction
) (
// Interface: slave
input [INSTRUCTION_ADDRESS_WIDTH-1:0] iaddr_i,
output reg [INSTRUCTION_WIDTH-1:0] instruction_feed,
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam MAX_CLOCKS = 10000;
reg [INSTRUCTION_WIDTH-1:0] instruction_memory [(2**INSTRUCTION_ADDRESS_WIDTH)-1:0];
integer total_clk;
initial begin
$readmemh("program.hex", instruction_memory);
end
initial begin
instruction_feed = 0;
total_clk = 0;
@(negedge rst_i); // wait for reset
forever begin
instruction_feed = instruction_memory[iaddr_i];
@(posedge clk_i);
total_clk = total_clk + 1;
if (total_clk >= MAX_CLOCKS || instruction_feed[27:24] == 'hF)
$stop;
end
@(posedge clk_i);
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; int Power(int n, int x) { int mul = n; int res = 1; while (x > 0) { if (x & 1) res = 1ll * res * mul % MOD; mul = 1ll * mul * mul % MOD; x /= 2; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int n; cin >> n; vector<int> a(n + 1), pref(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(begin(a) + 1, end(a), greater<int>()); for (int i = 1; i <= n; i++) { pref[i] = (a[i] + pref[i - 1]) % MOD; } vector<int> ans; for (int k = 1; k <= n; k++) { int res = 0; for (int i = 0, j = 0; i <= n; i += k, j++) { res = (res + (1ll * j * ((pref[min(i + k, n)] - pref[i]) % MOD) % MOD)) % MOD; } ans.emplace_back(1ll * res * Power(n, MOD - 2) % MOD); } for (auto i : ans) { if (i < 0) i += MOD; cout << i << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T& x) { static char c; static int f; for (c = getchar(), f = 1; c < 0 || c > 9 ; c = getchar()) if (c == - ) f = -f; for (x = 0; c >= 0 && c <= 9 ; c = getchar()) x = x * 10 + (c & 15); x *= f; } template <typename T> void write(T x) { static char q[65]; int cnt = 0; if (x < 0) putchar( - ), x = -x; q[++cnt] = x % 10, x /= 10; while (x) q[++cnt] = x % 10, x /= 10; while (cnt) putchar(q[cnt--] + 0 ); } const int mod = 1000000007, maxn = 1000005; int mo(const int x) { return x >= mod ? x - mod : x; } int iac[maxn], fac[maxn], _n[maxn], _m[maxn]; int main() { int n, m, a, b; read(n), read(m), read(a), read(b); int mx = max(n, m); iac[0] = iac[1] = fac[0] = fac[1] = _n[1] = _m[0] = 1; _m[1] = m; for (int i = 2; i <= mx; ++i) iac[i] = 1ll * (mod - mod / i) * iac[mod % i] % mod; _n[0] = iac[n]; for (int i = 2; i <= mx; ++i) iac[i] = 1ll * iac[i - 1] * iac[i] % mod, fac[i] = 1ll * fac[i - 1] * i % mod, _m[i] = 1ll * _m[i - 1] * m % mod, _n[i] = 1ll * _n[i - 1] * n % mod; int ans = 0; for (int i = 1; i <= n - 1 && i <= m; ++i) ans = mo(ans + 1ll * (i + 1) * _n[n - 1 - i] % mod * _m[n - 1 - i] % mod * iac[n - 1 - i] % mod * iac[m - i] % mod * iac[i - 1] % mod); ans = 1ll * ans * fac[n - 2] % mod * fac[m - 1] % mod; write(ans), putchar( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_BLACKBOX_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e7 + 10; int n, fac[MAX_N], pri[MAX_N], pri_n, fac_cnt[MAX_N], phi[MAX_N]; long long ans; void init() { scanf( %d , &n); for (int i = 2; i <= n; i++) { if (!fac[i]) { phi[i] = (fac[i] = pri[++pri_n] = i) - 1; fac_cnt[i] = 1; } for (int j = 1; j <= pri_n && pri[j] * i <= n && pri[j] <= fac[i]; j++) { fac[pri[j] * i] = pri[j]; fac_cnt[pri[j] * i] = fac_cnt[i] + (pri[j] == fac[i] ? 0 : 1); phi[pri[j] * i] = phi[i] * (pri[j] - (pri[j] == fac[i] ? 0 : 1)); } } } long long get_pair_suc() { long long suc = 0; for (int i = 2; i <= n; i++) if (i * 2 <= n || fac[i] != i) suc++; return suc * (suc - 1) / 2; } long long get_pair_1() { long long res = 0; for (int i = 2; i <= n; i++) res += i - 1 - phi[i]; return res; } long long get_pair_2() { static int pref_fac[MAX_N]; int pref_pri = 0; long long res = 0; for (int i = 2; i <= n; i++) { if (fac[i] == i) pref_pri++; else res += phi[i] - (pref_pri - fac_cnt[i]) - 1; } for (int i = 2; i <= n; i++) pref_fac[fac[i]]++; for (int i = 2; i <= n; i++) pref_fac[i] += pref_fac[i - 1]; for (int i = 2; i <= n; i++) { if (fac[i] != i) continue; int lim = n / fac[i]; res += pref_fac[lim]; for (int j = i; j <= n; j += i) if (fac[j] <= lim) res--; } for (int i = 2; i <= n; i++) if (fac_cnt[i] == 2 && fac[i / fac[i]] == i / fac[i]) res--; return res; } void solve() { long long pair_suc = get_pair_suc(); long long pair_1 = get_pair_1(); long long pair_2 = get_pair_2(); long long pair_3 = pair_suc - pair_1 - pair_2; long long ans = pair_1 * 1 + pair_2 * 2 + pair_3 * 3; printf( %lld n , ans); } int main() { init(); solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_2_V
`define SKY130_FD_SC_HDLL__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int trn = 1 << (n + 1); trn--; int a[30000]; for (int i = 2; i <= trn; i++) cin >> a[i]; int q = 1 << n; int mx = 0; int leng[30000]; for (int i = q; i <= trn; i++) { leng[i] = 0; int j = i; while (j > 0) { leng[i] += a[j]; j /= 2; } mx = max(mx, leng[i]); } int add[30000]; for (int i = q; i <= trn; i++) add[i] = mx - leng[i]; for (int depth = n + 1; depth > 1; depth--) { q = 1 << (depth - 1); for (int i = q; i < q * 2; i += 2) { if ((add[i] > 0) && (add[i + 1] > 0)) { int t = min(add[i], add[i + 1]); add[i / 2] = t; add[i] = add[i] - t; add[i + 1] = add[i + 1] - t; } } } int ans = 0; for (int i = 0; i <= trn; i++) ans += add[i]; cout << ans; } |
`timescale 1ns / 1ps
module ALUnitSim();
reg [31:0] a;
reg [31:0] b;
reg [2:0] op;
wire [31:0] result;
wire zero;
ALUnit alu(
.a(a),
.b(b),
.op(op),
.result(result),
.zero(zero)
);
initial begin
a = 0;
b = 0;
op = 0;
// a + b
#100
a = 11;
b = 1;
op = 3'B000;
// a - b
#100
a = 11;
b = 1;
op = 3'B001;
// b << a
#100
a = -6;
b = -1234;
op = 3'B010;
// a | b
#100
a = 1234;
b = 1111;
op = 3'B011;
// a & b
#100
a = 1234;
b = 1111;
op = 3'B100;
// a < b unsigned
#100
a = -12;
b = 11;
op = 3'B101;
// a < b signed
#100
a = -12;
b = -11;
op = 3'B110;
// a ^ b
#100
a = 1234;
b = 1111;
op = 3'B111;
end
endmodule
|
module sockit_test (
input CLOCK_50,
input [3:0] KEY,
output [3:0] LED,
output [12:0] hps_memory_mem_a,
output [2:0] hps_memory_mem_ba,
output hps_memory_mem_ck,
output hps_memory_mem_ck_n,
output hps_memory_mem_cke,
output hps_memory_mem_cs_n,
output hps_memory_mem_ras_n,
output hps_memory_mem_cas_n,
output hps_memory_mem_we_n,
output hps_memory_mem_reset_n,
inout [7:0] hps_memory_mem_dq,
inout hps_memory_mem_dqs,
inout hps_memory_mem_dqs_n,
output hps_memory_mem_odt,
output hps_memory_mem_dm,
input hps_memory_oct_rzqin
);
// internal signals
wire [3:0] key_os;
wire [3:0] delay;
wire main_clk = CLOCK_50;
assign delay[1] = 0;
assign delay[2] = 0;
//wire test_out;
oneshot os (
.clk (main_clk), // port mappings
.edge_sig (KEY),
.level_sig (key_os)
);
soc_system soc (
.delay_ctrl_slower (delay[0]),
.delay_ctrl_faster (key_os[1]),
.memory_mem_a (hps_memory_mem_a),
.memory_mem_ba (hps_memory_mem_ba),
.memory_mem_ck (hps_memory_mem_ck),
.memory_mem_ck_n (hps_memory_mem_ck_n),
.memory_mem_cke (hps_memory_mem_cke),
.memory_mem_cs_n (hps_memory_mem_cs_n),
.memory_mem_ras_n (hps_memory_mem_ras_n),
.memory_mem_cas_n (hps_memory_mem_cas_n),
.memory_mem_we_n (hps_memory_mem_we_n),
.memory_mem_reset_n (hps_memory_mem_reset_n),
.memory_mem_dq (hps_memory_mem_dq),
.memory_mem_dqs (hps_memory_mem_dqs),
.memory_mem_dqs_n (hps_memory_mem_dqs_n),
.memory_mem_odt (hps_memory_mem_odt),
.memory_mem_dm (hps_memory_mem_dm),
.memory_oct_rzqin (hps_memory_oct_rzqin),
.clk_clk (main_clk),
.reset_reset_n (!key_os[3])
);
blinker b (
.clk (main_clk),
.delay (delay),
.led (LED),
.reset (key_os[3]),
.pause (key_os[2])
);
endmodule
|
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart2_rx #(parameter WIDTH = 8, parameter real BAUD = 9600) (
input reset,
input clk,
input uld_rx_data,
output reg [WIDTH-1:0] rx_data = {WIDTH{1'b0}},
input rx_enable,
input rx_in,
output reg byte_rdy = 1'b0
);
//parameter ML505 = 0; //default to 0 if not specified
//parameter BAUD = 9600; // default to 9600 Baud
//Variable/custom Baud rate little-endian 8N1 UART-RX
`ifdef ML505 localparam real CLK_FREQ = 100e6;
`else localparam real CLK_FREQ = 40e6;
`endif
localparam BAUD_CNT_SIZE = bits_to_fit(CLK_FREQ/BAUD);
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+2);
localparam [BAUD_CNT_SIZE-1:0] FRAME_WIDTH = CLK_FREQ/BAUD;
localparam [BAUD_CNT_SIZE-1:0] FRAME_MIDPOINT = FRAME_WIDTH/2;
// Internal registers
reg [WIDTH-1:0] rx_reg = {WIDTH{1'b0}};
reg [BAUD_CNT_SIZE-1:0] rx_sample_cnt = {BAUD_CNT_SIZE{1'b0}};
reg [BIT_CNT_SIZE-1:0] rx_cnt = {BIT_CNT_SIZE{1'b0}};
(* ASYNC_REG = "true" *) reg rx_da = 1'b1, rx_db = 1'b1;
reg rx_busy = 1'b0;
// UART RX Logic
always @ (posedge clk) begin
if (reset) begin
rx_reg <= {WIDTH{1'b0}};
rx_data <= {WIDTH{1'b0}};
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= {BIT_CNT_SIZE{1'b0}};
byte_rdy <= 1'b0;
rx_da <= 1'b1;
rx_db <= 1'b1;
rx_busy <= 1'b0;
end else begin // if (~reset)
if (rx_enable) begin // Receive data only when rx is enabled
// Synchronize the asynch signal
rx_da <= rx_in;
rx_db <= rx_da;
rx_data <= (uld_rx_data) ? rx_reg : rx_data;
/*if (uld_uart_data) begin // drive ouputs first
byte_rdy <= 1'b0;
//else byte_rdy <= byte_recd;
//byte_rdy <= (uld_uart_data) ?
end else if (rx_busy) begin //drive logic, counters etc*/
if (rx_busy) begin //drive logic, counters etc
if (rx_sample_cnt == FRAME_WIDTH) begin
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= rx_cnt + 1;
case (rx_cnt)
{BIT_CNT_SIZE{1'b0}}: begin
rx_busy <= ~rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
WIDTH+1: begin
rx_busy <= 1'b0;
byte_rdy <= rx_db;
end
default: begin
rx_reg[rx_cnt - 1'b1] <= rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
endcase
end else begin
rx_sample_cnt <= rx_sample_cnt + 1'b1;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
end else begin //if (~rx_busy)
rx_busy <= ~rx_db;
rx_sample_cnt <= FRAME_MIDPOINT;
rx_cnt <= 1'b0;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
//rx_reg <= 8'd0;
end // if (~rx_busy)
end else begin // if (~rx_enable)
rx_reg <= {WIDTH{1'b0}};
rx_data <= {WIDTH{1'b0}};
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= {BIT_CNT_SIZE{1'b0}};
byte_rdy <= 1'b0;
rx_da <= 1'b1;
rx_db <= 1'b1;
rx_busy <= 1'b0;
end // if (~rx_enable)
end //if (~reset)
end //always
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0;clog2=clog2+1)
value = value>>1;
end
endfunction
function integer bits_to_fit;
input [31:0] value;
for (bits_to_fit=0; value>0; bits_to_fit=bits_to_fit+1)
value = value >> 1;
endfunction
endmodule
|
`timescale 1ns / 1ps
/*
tab size 4
*/
module jt51_test;
reg clk;
reg rst;
// Channel frequency
reg [6:0] kc;
reg [5:0] kf;
// Operator multiplying
reg [3:0] mul;
// Operator detuning
reg [2:0] dt1;
reg [1:0] dt2;
// phase modulation from LFO
reg signed [7:0] pm;
reg [2:0] pms;
// phase operation
wire [ 4:0] keycode_III;
`ifndef LFO_PM
`define LFO_PM 0
`endif
`ifndef LFP_PMS
`define LFP_PMS 0
`endif
initial begin
clk = 0;
forever #140 clk = ~clk;
end
initial begin
rst = 0;
#20 rst = 1;
#300 rst = 0;
$display("DUMP START");
end
`ifdef LFO_TEST
reg fin;
always @(posedge clk ) begin
if( rst ) begin
kc <= { 3'd3, 4'd4 };
kf <= 6'd0;
dt2<= 2'd0;
dt1<= 3'd0;
mul<= 4'd1;
pm <= 0;
pms<= 3'd1;
fin<=1'b0;
end
else begin
{ fin,pms, pm } <= {fin,pms,pm} + 1'd1;
if( fin ) begin
#(280*7) $display("DUMP END");
$finish;
end
end
end
`endif
`ifdef LFO_FULL_TEST
reg fin;
always @(posedge clk or posedge rst ) begin
if( rst ) begin
kc <= 7'd0;
kf <= 6'd0;
dt2<= 2'd0;
dt1<= 3'd0;
mul<= 4'd1;
pm <= 0;
pms<= 3'd1;
fin<=1'b0;
end
else begin
{ fin,pms, kc, kf, pm } <= {fin,pms, kc, kf, pm} + 1'd1;
if( fin ) begin
#(280*7) $display("DUMP END");
$finish;
end
end
end
`endif
`ifdef KC_TEST
always @(posedge clk or posedge rst ) begin
if( rst ) begin
kc <= 7'd0;
kf <= 6'd0;
dt2<= 2'd0;
dt1<= 3'd0;
mul<= 4'd1;
pm <= `LFO_PM;
pms<= `LFO_PMS;
end
else begin
{ dt2, dt1, kc, kf } <= { dt2, dt1, kc, kf } + 1'd1;
if( &{ dt2, dt1, kc, kf }==1'b1 ) begin
#(280*7) $display("DUMP END");
$finish;
end
end
end
`endif
jt51_pg u_uut(
.clk(clk),
.cen(1'b1),
// Channel frequency
.kc_I(kc),
.kf_I(kf),
// Operator multiplying
.mul_VI(mul),
// Operator detuning
.dt1_II(dt1),
.dt2_I(dt2),
// phase modulation from LFO
.pm(pm),
.pms_I(pms),
// phase operation
.pg_rst_III(1'b0),
//.keycode_III(keycode_III),
.pg_phase_X( )
);
initial begin
`ifdef DUMPSIGNALS
`ifdef NCVERILOG
$shm_open("jt51_test.shm");
$shm_probe(jt51_test,"AS");
`else
$dumpfile("jt51_test.lxt");
$dumpvars();
$dumpon;
`endif
#(280*10000) $finish;
`endif
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 16:07:32
// Design Name:
// Module Name: lab1_4_1_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab1_4_1_tb(
);
reg u,v,w,s0,s1;
wire m;
reg e_m,tra;
reg [4:0] pro;
integer i;
lab1_4_1 dut(u,v,w,s0,s1,m);
function expected_m;
input u,v,w,s0,s1;
begin
tra = (~s0 & u) | (s0 & v);
expected_m = (~s1 & tra) | (s1 & w);
end
endfunction
initial
begin
for (i=0; i < 32; i=i+1)
begin
#5 pro=i;
#3 u=pro[0]; v=pro[1]; w=pro[2]; s0=pro[3]; s1=pro[4];
#3 e_m = expected_m(u,v,w,s0,s1);
if(m == e_m)
$display("output matched at", $time);
else
$display("output mis-matched at ",$time,": expected: %b, actual: %b", e_m, m);
end
end
endmodule
|
module testbench( input logic writeRead,
input logic newService,
input logic multiblock,
input logic timeoutenable,
input logic reset,
input logic[3:0] blockSize,
input logic fifo_full,
input logic [15:0] timeout ,
input logic SDclock,
input logic clock,
input logic [31:0] fromFifo_toPS,
input logic fromSD_SP,
output wire complete,
output wire toSD_PS,
output wire padState,// entrada o salida del pad
output wire padEnable, //habilita el oad
output wire timeOutFail,
output wire [31:0] fromSP_toFifo,
output wire pop,
output wire push,
output wire IDLE_out);
DAT DUT0(.writeRead(writeRead),.newService(newService),.multiblock(multiblock),.timeoutenable(timeoutenable), .reset(reset),.blockSize(blockSize)
,.fifo_full(fifo_full),.timeout(timeout) ,.SDclock(SDclock),.clock(clock),.fromFifo_toPS(fromFifo_toPS),.fromSD_SP(fromSD_SP), .complete(complete),
.toSD_PS(toSD_PS),.padState(padState),.padEnable(padEnable), .timeOutFail(timeOutFail),.fromSP_toFifo(fromSP_toFifo),.pop(pop),.push(push),.IDLE_out(IDLE_out));
probador DUT1( .writeRead(writeRead),.pop(pop),.push(push),.newService(newService),.multiblock(multiblock),.timeoutenable(timeoutenable), .reset(reset),.blockSize(blockSize)
,.fifo_full(fifo_full),.timeout(timeout) ,.SDclock(SDclock),.clock(clock),.fromFifo_toPS(fromFifo_toPS),.fromSD_SP(fromSD_SP));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7, N = 2e5 + 5; int par[N], over[N]; int getpar(int u) { if (par[par[u]] == par[u]) return par[u]; return par[u] = getpar(par[u]); } bool unite(int a, int b) { a = getpar(a); b = getpar(b); if (a == b) { if (over[a]) return false; over[a] += 1; return true; } else { if (over[a] && over[b]) { return false; } par[a] = b; over[b] += over[a]; return true; } assert(false); } struct Edge { int a, b, c; bool operator<(const Edge &t) const { return c > t.c; } }; int main() { iota(par, par + N, 0); int n, m; cin >> n >> m; vector<Edge> edges(m); for (int i = 0; i < m; ++i) scanf( %d %d %d , &edges[i].a, &edges[i].b, &edges[i].c); sort(edges.begin(), edges.end()); int ans = 0; for (auto cur : edges) if (unite(cur.a, cur.b)) ans += cur.c; cout << ans << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2016 02:04:39 PM
// Design Name:
// Module Name: LZA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZA
#(parameter SWR=26, parameter EWR=5)(
//#(parameter SWR=55, parameter EWR=6)(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] P_i,
input wire [SWR-1:1] C_i,
input wire A_S_op_i,
/////////////////////////////////////////////7
output wire [EWR-1:0] Shift_Value_o
);
wire [SWR-1:0] Comb_to_Codec;
wire [EWR-1:0] Codec_to_Reg;
Combinational_Logic_LZA #(.SWR(SWR)) Combinational_Logic_LZA (
.P_i(P_i),
.C_i(C_i),
.A_S_i(A_S_op_i),
.S_o(Comb_to_Codec)
);
generate
case (SWR)
26:begin
Priority_Codec_32 Codec_32(
.Data_Dec_i(Comb_to_Codec),
.Data_Bin_o(Codec_to_Reg)
);
end
55:begin
Priority_Codec_64 Codec_64(
.Data_Dec_i(Comb_to_Codec),
.Data_Bin_o(Codec_to_Reg)
);
end
endcase
endgenerate
RegisterAdd #(.W(EWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Codec_to_Reg),
.Q(Shift_Value_o)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:25 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: clock_module.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CLOCK_MODULE
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: A module provided as a convenience for desingners using 4-byte
// lane Aurora Modules. This module takes the MGT reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 10 ps
module CLOCK_MODULE
(
MGT_REFERENCE_CLOCK,
USER_CLK,
USER_CLK_2X_N,
DCM_NOT_LOCKED
);
`define DLY #1
//***********************************Port Declarations*******************************
input MGT_REFERENCE_CLOCK;
output USER_CLK;
output USER_CLK_2X_N;
output DCM_NOT_LOCKED;
//*********************************Wire Declarations**********************************
wire [15:0] not_connected_i;
wire clkfb_i;
wire clkdv_i;
wire clk0_i;
wire locked_i;
//*********************************Main Body of Code**********************************
// Instantiate a DCM module to divide the reference clock.
DCM clock_divider_i
(
.CLK0(clk0_i),
.CLK180(not_connected_i[0]),
.CLK270(not_connected_i[1]),
.CLK2X(not_connected_i[2]),
.CLK2X180(not_connected_i[3]),
.CLK90(not_connected_i[4]),
.CLKDV(clkdv_i),
.CLKFX(not_connected_i[5]),
.CLKFX180(not_connected_i[6]),
.LOCKED(locked_i),
.PSDONE(not_connected_i[7]),
.STATUS(not_connected_i[15:8]),
.CLKFB(clkfb_i),
.CLKIN(MGT_REFERENCE_CLOCK),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(1'b0)
);
// BUFG for the feedback clock. The feedback signal is phase aligned to the input
// and must come from the CLK0 or CLK2X output of the DCM. In this case, we use
// the CLK0 output.
BUFG feedback_clock_net_i
(
.I(clk0_i),
.O(clkfb_i)
);
// We invert the feedback clock to get USER_CLK_2X_N.
INV user_clk_2x_inverter_i
(
.I(clkfb_i),
.O(USER_CLK_2X_N)
);
// The User Clock is distributed on a global clock net.
BUFG user_clk_net_i
(
.I(clkdv_i),
.O(USER_CLK)
);
// The DCM_NOT_LOCKED signal is created by inverting the DCM's locked signal.
assign DCM_NOT_LOCKED = ~locked_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int d[2005]; vector<int> E[2005]; bool h[2005]; const int INF = 1e9 + 7; void add(int u, int v) { E[u].push_back(v); } void bfs() { queue<int> q; d[0] = 0; q.push(0); while (q.size()) { int t = q.front(); q.pop(); for (int i = 0; i < E[t].size(); i++) { if (d[E[t][i]] == INF) { d[E[t][i]] = d[t] + 1; q.push(E[t][i]); if (E[t][i] == 1001) { return; } } } } return; } int main() { scanf( %d%d , &n, &k); for (int i = 0; i <= 2001; i++) d[i] = INF; for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); x -= n; if (!h[x + 1001]) { add(0, x + 1001); h[x + 1001] = 1; } } for (int i = 1; i <= 2001; i++) { for (int j = 1; j <= 2001; j++) { if (h[j] && (0 <= i + j - 1001 && i + j - 1001 <= 2001)) { add(i, i + j - 1001); } } } bfs(); if (d[1001] != INF) printf( %d n , d[1001]); else puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); string s; cin >> s; int n = s.length(); vector<int> v; for (int i = 0; i < n; i++) if (i == n - 1 || s[i] != s[i + 1]) v.push_back(i); if (s.back() == b ) v.pop_back(); vector<int> res(n); for (int p : v) res[p] = 1; for (int id : res) cout << id << ; cout << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:49 03/30/2016
// Design Name: ALU
// Module Name: Y:/TEOCOA/EXPR3_DIGITAL/ALU_TEST.v
// Project Name: EXPR3_DIGITAL
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ALU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_TEST;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [2:0] ALU_OP;
// Outputs
wire ZF;
wire OF;
wire [31:0] F;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.A(A),
.B(B),
.ZF(ZF),
.OF(OF),
.F(F),
.ALU_OP(ALU_OP)
);
initial begin
// Initialize Inputs
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 0;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 1;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 2;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 3;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 4;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 5;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 6;
#20;
A=32'h1e45d9f9;
B=32'hd4c41db0;
ALU_OP= 7;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 0;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 1;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 2;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 3;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 4;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 5;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 6;
#20;
A=32'h48342e09;
B=32'ha5f5973e;
ALU_OP= 7;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 0;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 1;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 2;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 3;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 4;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 5;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 6;
#20;
A=32'h73254ed5;
B=32'h92292c55;
ALU_OP= 7;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 0;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 1;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 2;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 3;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 4;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 5;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 6;
#20;
A=32'hd0d65f3d;
B=32'h6c2cb5e9;
ALU_OP= 7;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 0;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 1;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 2;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 3;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 4;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 5;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 6;
#20;
A=32'he76929f0;
B=32'h3ee9520c;
ALU_OP= 7;
#20;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long, string> dic; int main() { long long n; scanf( %lld , &n); for (long long i = 2; (long long)i * i <= n; i++) { for (long long j = i * i, p = 2; j <= n; j *= i, p++) { string str = to_string(i) + ^ + to_string(p); if (dic.find(j) == dic.end()) dic[j] = str; else if (dic[j].size() > str.size()) dic[j] = str; } } string ans = to_string(n); for (auto it = dic.begin(); it != dic.end(); it++) { long long v = it->first; string str = it->second; long long mul = n / v; long long add = n % v; string all_str; if (mul > 1) { string mul_str = to_string(mul); if (dic.find(mul) != dic.end() && dic[mul].size() < mul_str.size()) all_str += dic[mul] + * ; else all_str += mul_str + * ; } all_str += str; if (add > 0) { all_str += + ; string add_str = to_string(add); if (dic.find(add) != dic.end() && dic[add].size() < add_str.size()) all_str += dic[add]; else all_str += add_str; } if (all_str.size() < ans.size()) ans = all_str; } puts(ans.c_str()); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[100005], ac[100005]; int last[100005]; int main() { int n, m, t, x, v, y, q; string s; while (cin >> n >> m) { for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= m; i++) { cin >> t; if (t == 1) { cin >> v >> x; a[v] = x; last[v] = i; ac[i] = ac[i - 1]; } else { if (t == 2) { cin >> y; ac[i] = ac[i - 1] + y; } else { cin >> q; cout << a[q] + ac[i - 1] - ac[last[q]] << endl; ac[i] = ac[i - 1]; } } } } } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); int d, n; cin >> d >> n; vector<int> days(n); for (int i = 0; i < n; i++) cin >> days[i]; int count = 0; for (int i = 1; i < n; i++) count += d - days[i - 1]; cout << count << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n; map<int, int> uchs; for (int i = 0; i < n; i++) { int x; cin >> x; if (uchs.find(x) != uchs.end()) { (uchs.at(x))++; } else uchs.insert(pair<int, int>(x, 1)); } cin >> m; vector<int> films; films.reserve(m); int max = 0; for (int j = 0; j < m; j++) { int x; cin >> x; if (uchs.find(x) != uchs.end()) { if (uchs.at(x) > max) { films.clear(); max = uchs.at(x); films.push_back(j); } else if (uchs.at(x) == max) { films.push_back(j); } } else if (max == 0) { films.push_back(j); } } int kinco = films[0] + 1; int newmax = 0; int r = 0; for (int j = 0; j < m; j++) { int x; cin >> x; if (films[r] == j) { r++; if (uchs.find(x) != uchs.end()) { if (uchs.find(x)->second > newmax) { kinco = j + 1; newmax = uchs.find(x)->second; } } if (r == films.size()) break; } } cout << kinco; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long DIM = 2e5 + 7; long long n, used[27][DIM], a[DIM], tests; int in; int main() { in = scanf( %lld , &tests); for (long long test = 1; test <= tests; test++) { in = scanf( %lld , &n); long long result = 0; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= 26; j++) { used[j][i] = used[j][i - 1]; } in = scanf( %lld , &a[i]); used[a[i]][i]++; } for (long long i = 1; i <= 26; i++) result = max(result, used[i][n]); long long cntin = 0, cntout = 0; for (long long l = 1; l <= n; l++) { for (long long r = l; r <= n; r++) { cntin = 0; cntout = 0; for (long long x = 1; x <= 26; x++) { cntin = max(cntin, used[x][r] - used[x][l - 1]); } for (long long x = 1; x <= 26; x++) cntout = max(cntout, min(used[x][l - 1], used[x][n] - used[x][r]) * 2); result = max(result, cntout + cntin); } } printf( %lld n , result); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= 26; j++) { used[j][i] = 0; } } } return 0; } |
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 09:17:01 09/23/2011
// Module Name: uart_light_clk_gen
//////////////////////////////////////////////////////////////////////////////////
module uart_light_clk_gen
#( //Die Default-Werte der folgenden Parameter werden für Baudrate 460800 genutzt
parameter BR_DIVISOR_TX = 54,
parameter BR_DIVISOR_RX = 5,
parameter BRD_SIZE_TX = 6,
parameter BRD_SIZE_RX = 3
)(
output wire clk_rx,
output wire clk_tx,
input wire clk_peri,
input wire reset
);
reg [BRD_SIZE_TX-1:0] divisor_tx;
reg [BRD_SIZE_RX-1:0] divisor_rx;
assign clk_tx = divisor_tx[BRD_SIZE_TX-1];
assign clk_rx = divisor_rx[BRD_SIZE_RX-1];
always @(posedge clk_peri, posedge reset) begin
if(reset) begin
divisor_tx <= {(BRD_SIZE_TX){1'b0}};
divisor_rx <= {(BRD_SIZE_RX){1'b0}};
end
else begin
if(divisor_tx == (BR_DIVISOR_TX - 1'b1))
divisor_tx <= {(BRD_SIZE_TX){1'b0}};
else
divisor_tx <= divisor_tx + 1'b1;
if(divisor_rx == (BR_DIVISOR_RX - 1'b1))
divisor_rx <= {(BRD_SIZE_RX){1'b0}};
else
divisor_rx <= divisor_rx + 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[8][8], n, m, u, v, k = INT_MAX; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; cin >> n >> m; for (long long i = 0; i < m; i++) { cin >> u >> v; a[u][v] = 1; a[v][u] = 1; } if (n <= 6) cout << m << n ; else { for (long long i = 1; i <= 7; i++) { for (long long j = i + 1; j <= 7; j++) { long long c = 0; for (long long l = 1; l <= 7; l++) if (a[i][l] == 1 && a[j][l] == 1) ++c; k = min(k, c); } } cout << m - k << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5 + 100000; int n, m, len_behind, len_front; struct TREE { int fg; int M11[3]; } T[maxn * 4]; inline int L(int &x) { return x << 1; } inline int R(int &x) { return x << 1 | 1; } void f_maintain(int root, int len) { int a = L(root), b = R(root), lena = (len + 1) >> 1, lenb = len >> 1; T[root].M11[0] = T[a].M11[0]; if (T[root].M11[0] == lena) T[root].M11[0] += T[b].M11[0]; T[root].M11[1] = T[b].M11[1]; if (T[root].M11[1] == lenb) T[root].M11[1] += T[a].M11[1]; T[root].M11[2] = max(T[a].M11[2], T[b].M11[2]); T[root].M11[2] = max(T[root].M11[2], T[L(root)].M11[1] + T[R(root)].M11[0]); } void f_build(int root, int le, int ri) { T[root].fg = -1; T[root].M11[0] = T[root].M11[1] = T[root].M11[2] = ri - le + 1; if (le == ri) return; int mid = (le + ri) >> 1; f_build(L(root), le, mid); f_build(R(root), mid + 1, ri); } void f_giveson(int fg, int son, int len) { T[son].fg = fg; T[son].M11[0] = T[son].M11[1] = T[son].M11[2] = fg * len; } void f_pushdown(int root, int len) { if (len == 1) return; int a = L(root), b = R(root), lena = (len + 1) >> 1, lenb = len >> 1; if (T[root].fg != -1) { f_giveson(T[root].fg, a, lena); f_giveson(T[root].fg, b, lenb); T[root].fg = -1; } } void f_update(int root, int le, int ri, int Mle, int Mri, int fg) { if (Mle <= le && ri <= Mri) { f_giveson(fg, root, ri - le + 1); return; } f_pushdown(root, ri - le + 1); int mid = (le + ri) >> 1; if (Mle <= mid) f_update(L(root), le, mid, Mle, Mri, fg); if (Mri > mid) f_update(R(root), mid + 1, ri, Mle, Mri, fg); f_maintain(root, ri - le + 1); } int f_query(int root, int le, int ri, int x) { if (le == ri) return le; f_pushdown(root, ri - le + 1); int mid = (le + ri) >> 1; if (T[L(root)].M11[2] >= x) return f_query(L(root), le, mid, x); else if (T[L(root)].M11[1] + T[R(root)].M11[0] >= x) return mid - T[L(root)].M11[1] + 1; return f_query(R(root), mid + 1, ri, x); } int one[2][105]; int main() { char ss[33]; while (scanf( %d %d %d %d , &n, &len_behind, &len_front, &m) + 1) { f_build(1, 1, n); memset(one, -1, sizeof one); int e, t, newlen, leaveid; for (e = 1; e <= m; e++) { scanf( %d , &t); if (t == 1) { scanf( %d , &newlen); if ((T[1].M11[0] == n && n >= newlen) || (T[1].M11[0] >= newlen + len_front)) { puts( 0 ); f_update(1, 1, n, 1, newlen, 0); one[0][e] = 1; one[1][e] = newlen; continue; } if (T[1].M11[2] >= newlen + len_behind + len_front) { int x = f_query(1, 1, n, newlen + len_behind + len_front); printf( %d n , x - 1 + len_behind); f_update(1, 1, n, x + len_behind, x + len_behind + newlen - 1, 0); one[0][e] = x + len_behind; one[1][e] = x + len_behind + newlen - 1; continue; } if (T[1].M11[1] >= newlen + len_behind) { int x = n + 1 - T[1].M11[1]; printf( %d n , x - 1 + len_behind); f_update(1, 1, n, x + len_behind, x + len_behind + newlen - 1, 0); one[0][e] = x + len_behind; one[1][e] = x + len_behind + newlen - 1; continue; } puts( -1 ); } else { scanf( %d , &leaveid); if (one[0][leaveid] != -1) { f_update(1, 1, n, one[0][leaveid], one[1][leaveid], 1); one[0][leaveid] = one[1][leaveid] = -1; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 50005; char str[Maxn]; int hs[26]; int main() { scanf( %s , str); int len = strlen(str), cCnt = 0; int xNum = 0, sta = 0; bool ok = false; int i; for (i = 0; i < len; i++) { if (i - sta >= 26 && cCnt + xNum == 26) { ok = true; for (int j = sta; j < sta + 26; j++) { if (str[j] == ? ) { for (int k = 0; k < 26; k++) { if (hs[k] == 0) { hs[k] = 1; str[j] = A + k; break; } } } } break; } if (str[i] == ? ) xNum++; else { if (hs[str[i] - A ] == 0) { hs[str[i] - A ] = 1; cCnt++; } else { hs[str[i] - A ]++; cCnt++; for (int j = sta; j < i; j++) { if (str[j] == str[i]) { hs[str[j] - A ]--; cCnt--; sta = j + 1; break; } else { if (str[j] == ? ) xNum--; else { hs[str[j] - A ]--; cCnt--; } } } } } } if (!ok && i - sta >= 26 && cCnt + xNum == 26) { ok = true; for (int j = sta; j < sta + 26; j++) { if (str[j] == ? ) { for (int k = 0; k < 26; k++) { if (hs[k] == 0) { hs[k] = 1; str[j] = A + k; break; } } } } } if (ok) { for (int i = 0; i < len; i++) { if (str[i] == ? ) str[i] = A ; } printf( %s n , str); } else { puts( -1 ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:17:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: FxP_ABS_Function
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Fixed Point Absolute Value Function
//
// Input Data in Fixed Point Two's Complement Format
// Output Data is positive value integer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module FxP_ABS_Function
#(
parameter DATA_WIDTH = 16
)
(
// Data Signals
input [DATA_WIDTH-1:0] DATA_IN,
output [DATA_WIDTH-1:0] DATA_ABS
);
//
// Two's Complement Absolute Function
//
// If the sign-bit (MSB) is high, then
// DATA_ABS = ~DATA_IN + 1'b1
// Else
// DATA_ABS = DATA_IN
//
assign DATA_ABS = DATA_IN[DATA_WIDTH-1] ? ~DATA_IN + 1'b1 : DATA_IN;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_1_V
`define SKY130_FD_SC_MS__NOR4BB_1_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4bb_1 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4bb_1 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_1_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const long long INF_LL = 1000000000000000000LL; const double pi = 2 * acos(0.0); template <class T> void smin(T& a, T b) { if (a > b) a = b; } template <class T> void smax(T& a, T b) { if (a < b) a = b; } template <class T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <class T> T sqr(T a) { return a * a; } template <typename Iterator> void print(const char* fmt, Iterator begin, Iterator end, const char* separator = ) { for (Iterator it = begin; it != end; ++it) { if (it != begin) printf(separator); printf(fmt, *it); } printf( n ); } long long t, a, b; int main() { scanf( %I64d%I64d%I64d , &t, &a, &b); int ans = 0; if (a == b) ++ans; if (t > a || a > b) { printf( %d n , ans); return 0; } if (a > 1) { vector<int> c; while (b) c.push_back(b % a), b /= a; for (int i(int((c).size()) - 1), _b(0); i >= _b; --i) { b *= t; b += c[i]; } if (b == a) ++ans; if (t == 1 && b == 1 && int((c).size()) > 2) ++ans; } else { if (b == 1) ans = -1; } if (ans == -1) printf( inf n ); else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[10100], b[1010]; int main() { int n, m, c, ans; scanf( %d%d%d , &n, &m, &c); ans = (n + m + c) / 2; if (n + c >= ans && m + c >= ans) printf( %d n , ans * 2); else printf( %d n , min(n + c, m + c) * 2); } |
#include <bits/stdc++.h> using namespace std; int j, i, a, b, c, k, d, e, f[1005], n, mi, ma; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> f[i]; ma = max(f[i], ma); } for (i = 0; i < n - 1; i++) for (j = i + 1; j < n; j++) { c = 0; for (k = i; k <= j; k++) c = f[k] ^ c; ma = max(ma, c); } cout << ma; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, l, c, d, p, nl, nd, np, min = 0, totl, totp, res; cin >> n >> k >> l >> c >> d >> p >> nl >> np; nd = d * c; totl = (k * l) / nl; totp = p / np; if (totl <= nd && totl <= totp) min = totl; else if (nd <= totl && nd <= totp) min = nd; else if (totp <= totl && totp <= nd) min = totp; res = min / n; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> domain; int domain_index(int x) { int id = lower_bound(domain.begin(), domain.end(), x) - domain.begin(); assert(domain[id] == x); return id; } struct Seg { Seg *lc, *rc; int L, M, R; int sum, val; Seg(int l, int r) : L(l), R(r) { lc = rc = NULL; M = (L + R) / 2; sum = 0; val = -1; if (L < R) { lc = new Seg(L, M); rc = new Seg(M + 1, R); } } void upd() { sum = lc->sum + rc->sum; val = max(lc->val, rc->val); } void add(int p, int v) { if (L == R) { sum += v; return; } if (p <= M) lc->add(p, v); else rc->add(p, v); upd(); } void update_maximum(int p, int v) { if (L == R) { val = max(val, v); return; } if (p <= M) lc->update_maximum(p, v); else rc->update_maximum(p, v); upd(); } int range_sum(int l, int r) { if (l <= L && R <= r) return sum; int ans = 0; if (l <= M) ans += lc->range_sum(l, r); if (r > M) ans += rc->range_sum(l, r); return ans; } int range_max(int l, int r) { if (l > r) return -1; if (l <= L && R <= r) return val; int ans = -1; if (l <= M) ans = max(ans, lc->range_max(l, r)); if (r > M) ans = max(ans, rc->range_max(l, r)); return ans; } }; struct Leader { bool is_query; int lo, hi, id, ans; int a, r, v; bool operator<(const Leader &t) const { if (r != t.r) return r < t.r; return is_query > t.is_query; } }; bool comp(const Leader &a, const Leader &b) { if (a.is_query != b.is_query) return a.is_query > b.is_query; return a.id < b.id; } int main() { int n, k; cin >> n >> k; vector<pair<int, int> > input(n); vector<Leader> leaders(n); for (int i = 0; i < n; ++i) scanf( %d , &leaders[i].r); for (int i = 0; i < n; ++i) scanf( %d , &leaders[i].a); for (int i = 0; i < n; ++i) { domain.push_back(leaders[i].a); domain.push_back(leaders[i].a - k); domain.push_back(leaders[i].a + k); input[i].first = leaders[i].r; input[i].second = leaders[i].a; } sort(domain.begin(), domain.end()); domain.erase(unique(domain.begin(), domain.end()), domain.end()); sort(leaders.begin(), leaders.end()); Seg evaluate_leaders(0, domain.size() - 1); int l = 0; for (Leader &leader : leaders) { while (l < n && leaders[l].r <= leader.r) { evaluate_leaders.add(domain_index(leaders[l].a), 1); ++l; } leader.v = evaluate_leaders.range_sum(domain_index(leader.a - k), domain_index(leader.a + k)); leader.a = domain_index(leader.a); leader.is_query = false; } int q; cin >> q; vector<Leader> queries(q); for (int i = 0; i < q; ++i) { int a, b; scanf( %d %d , &a, &b); --a, --b; int min_age = domain_index(max(input[a].second, input[b].second) - k); int max_age = domain_index(min(input[a].second, input[b].second) + k); int min_resp = max(input[a].first, input[b].first); queries[i].lo = min_age; queries[i].hi = max_age; queries[i].r = min_resp; queries[i].id = i; queries[i].is_query = true; leaders.push_back(queries[i]); } sort(leaders.rbegin(), leaders.rend()); Seg find_leader(0, domain.size() - 1); for (auto &leader : leaders) { if (leader.is_query) leader.ans = find_leader.range_max(leader.lo, leader.hi); else find_leader.update_maximum(leader.a, leader.v); } sort(leaders.begin(), leaders.end(), comp); for (int i = 0; i < q; ++i) printf( %d n , leaders[i].ans); } |
`timescale 1ns / 1ps
module Microcontroller(
output [31:0] DATO1,
output [31:0] DATO2,
output [31:0] RESULTADO,
input [31:0] MouseData,
input CLK,
input MOUSECLICK
);
/* First of all, let's talk about wires */
wire [1:0] RegSrc, ImmSrc, ALUControl; /* ControlUnit */
wire PCSrc, RegWrite, MemWrite, MemtoReg, ALUSrc;
wire [31:0] INSTR; /* Instruction memory */
wire [31:0] PC, PCp4, PCp8; /* PC */
wire [3:0] MUXRB; /* RegisterFile MUXES */
wire [31:0] OPERA, OPERB, ReadDataA, ReadDataB, StackPointer; /* Register File */
wire [31:0] ExtImm; /* Extend unit */
wire [31:0] ALUResult, RotateResult; /* ALU */
wire N, Z, C, V;
wire [31:0] ReadData; /* DataMemory */
wire [31:0] Result; /* MEM/ALU MUX */
wire [31:0] PCPrev1, PCPrev2; //PCPrev2; /* MEM/ALU/PC MUXES */
/* Last but not less important the conections */
ControlUnit cu (PCSrc, RegWrite, MemWrite, MemtoReg, ALUSrc,
ImmSrc, RegSrc, ALUControl, INSTR[31:28], {N,Z,C,V}, INSTR[27:26], INSTR[25:20], INSTR[15:12], CLK);
PC pc (PC, PCPrev2, CLK);
InstructionMemory im (INSTR, PC);
PCplus4 pcp4 (PCp4, PC);
PCplus4 pcp8 (PCp8, PCp4);
MUX_4 muxRB (MUXRB, INSTR[3:0], INSTR[15:12], RegSrc[1]);
/* EXTRA */
reg NotCompare;
always @ (*) begin
if (RegWrite & INSTR[24:21]!=4'b1010) NotCompare = 1;
else NotCompare = 0;
end
RegisterFile rf (ReadDataA, ReadDataB, StackPointer, INSTR[19:16], MUXRB, INSTR[15:12], Result,
NotCompare, CLK);
Extend e (ExtImm, ImmSrc, INSTR[23:0]);
MUX muxALUB (OPERB, ReadDataB, ExtImm, ALUSrc);
MUX muxALUA (OPERA, ReadDataA, PCp8, RegSrc[0]);
ALU alu (ALUResult, N, Z, V, C, OPERA, OPERB, ALUControl);
Rotate rot (RotateResult, INSTR[6:5], ReadDataB, INSTR[11:7]);
/* */
wire [31:0] RESULT;
reg ShiftSrc;
always @ (*) begin ShiftSrc = (INSTR[27:26]==2'b00 & INSTR[24:21]==4'b1101 & ~INSTR[25]); end
MUX muxResult (RESULT, ALUResult, RotateResult, ShiftSrc);
/* */
//DataMemory dm (ReadData, RESULT, ReadDataB, MemWrite, CLK);
DataMemory dm (ReadData, DATO1, DATO2, RESULTADO, RESULT,
ReadDataB, MouseData, MOUSECLICK, MemWrite, CLK);
MUX muxRESULT (Result, RESULT, ReadData, MemtoReg);
MUX muxPC (PCPrev1, PCp4, Result, PCSrc);
MUX muxPC2 (PCPrev2, PCPrev1, StackPointer, MOUSECLICK);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_TB_V
`define SKY130_FD_SC_HDLL__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_TB_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_axi_bram_ctrl_0_bram_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input [7 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input [63 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output [63 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *)
input rstb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
input [7 : 0] web;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input [31 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
input [63 : 0] dinb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output [63 : 0] doutb;
blk_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(2),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("NONE"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_RST_TYPE("SYNC"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(8),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(64),
.C_READ_WIDTH_A(64),
.C_WRITE_DEPTH_A(1024),
.C_READ_DEPTH_A(1024),
.C_ADDRA_WIDTH(32),
.C_HAS_RSTB(1),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(8),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(64),
.C_READ_WIDTH_B(64),
.C_WRITE_DEPTH_B(1024),
.C_READ_DEPTH_B(1024),
.C_ADDRB_WIDTH(32),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_ENABLE_32BIT_ADDRESS(1),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_USE_BRAM_BLOCK(1),
.C_CTRL_ECC_ALGO("NONE")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'B0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(clkb),
.rstb(rstb),
.enb(enb),
.regceb(1'B0),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb),
.injectsbiterr(1'B0),
.injectdbiterr(1'B0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.s_aclk(1'B0),
.s_aresetn(1'B0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'B0),
.s_axi_awready(),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'B0),
.s_axi_wvalid(1'B0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'B0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'B0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'B0),
.s_axi_injectsbiterr(1'B0),
.s_axi_injectdbiterr(1'B0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, c; int main() { cin >> a >> b >> c; int i, s = 0; for (i = 1; i <= a - 1; i++) s += i; cout << (c + a - 1) * (b + a - 1) - 2 * s; } |
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