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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int c = 0; int i; for (i = 0; i < n - 1; i++) { if (s[i] > s[i + 1]) { c = 1; break; } } if (c == 1) cout << YES n << i + 1 << << i + 2 << n ; else cout << NO n ; }
|
module avr_interface(
input clk,
input rst,
input cclk,
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
output tx,
input rx,
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
cclk_detector cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
serial_rx #(.CLK_PER_BIT(100), .CTR_SIZE(7)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(100), .CTR_SIZE(7)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
if (spi_ss) begin
byte_ct_d = 1'b0;
end
if (spi_done) begin
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout;
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0];
sample_channel_d = spi_dout[7:4];
byte_ct_d = 1'b1;
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
sample_channel_q <= sample_channel_d;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_SYMBOL_V
`define SKY130_FD_SC_LS__TAP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_SYMBOL_V
|
#include <bits/stdc++.h> int arr[250]; int ans[250]; int main() { int num; int clr; scanf( %d%d , &num, &clr); for (int i = 1; i <= num; ++i) { scanf( %d , &arr[i]); } int res = 0; for (int i = 1; i <= clr; ++i) { scanf( %d , &ans[i]); res += ans[i]; } std::queue<int> que; for (int i = 1; i <= num; ++i) { --ans[arr[i]]; --res; que.push(arr[i]); while (ans[arr[i]] < 0) { int now = que.front(); que.pop(); ++ans[now]; ++res; } if (res == 0) { puts( YES ); return 0; } } puts( NO ); return 0; }
|
module OV7670_CAPTURE_AXI_VDMA_STREAM(
input pclk, // pixel clk input
input href, // HREF input
input vsync, // vertiacl sync input
input [7:0] data, // camere 1byte data
input M_AXIS_TREADY, // -
output M_AXIS_TVALID, // valid data
output M_AXIS_TLAST, // EOL
output M_AXIS_TUSER, // EOF
output [31:0] M_AXIS_TDATA); // axi video data
// state machine
reg [1:0] state = 2'b0;
// pixel counter 640x480
reg [9:0] pixel_counter = 10'b0;
// output data latch
reg [23:0] data_latch = 24'b0;
always @(posedge pclk)
begin
if(vsync)
begin
state <= 2'b0;
pixel_counter <= 32'b0;
end
else
begin
data_latch <= {data_latch[15:0], data};
state <= {state[0], href & !state[0]};
if(state[1])
pixel_counter <= pixel_counter + 1;
end
end
// valid when received 16bit
assign M_AXIS_TVALID = state[1];
// end of "line" 640 px
assign M_AXIS_TLAST = ((pixel_counter % 640) == 639) ? 1'b1 : 1'b0;
// end of "picture" 640x480
assign M_AXIS_TUSER = (pixel_counter == 0) ? 1'b1 : 1'b0;
// RGB565 -> RGB32
assign M_AXIS_TDATA = {8'b0, data_latch[4:0], {3{data_latch[0]}}, data_latch[10:5], {2{data_latch[5]}}, data_latch[15:11], {3{data_latch[11]}}};
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long MOD = 1e9 + 7; const long long maxn = 1e5 + 7; const long long maxm = 2e5 + 7; struct Edge { int end, idx, label, vis; }; vector<Edge> adj[maxn]; vector<int> deg[maxn]; int n, ans[maxn], vis[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n; for (int i = 0; i <= n - 2; i++) { int u, v; cin >> u >> v; Edge e; e.idx = i; e.end = u; adj[v].push_back(e); e.end = v; adj[u].push_back(e); } for (int i = 1; i <= n; i++) { deg[adj[i].size()].push_back(i); } int maxUsed = 0; for (int d = 1; d <= n - 1; d++) { for (int u : deg[d]) { for (Edge e : adj[u]) { if (!vis[e.end]) { ans[e.idx] = maxUsed; maxUsed++; } } vis[u] = true; } } for (int i = 0; i <= n - 2; i++) { cout << ans[i] << endl; } return 0; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module red_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 7: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 7: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 7: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int Graph[1025][1025], f[1025][1025]; int Tj(int x) { int tot = 0; while (x) tot++, x -= x & (-x); return tot; } void read(int &x) { x = 0; char c = getchar(); int f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -f; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } x *= f; return; } void write(int x) { if (x < 0) { x = -x; putchar( - ); } if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } signed main() { read(n), read(m), read(k); for (register int i = 1; i <= m; ++i) { int u, v; read(u), read(v); u--, v--; Graph[u][v] = Graph[v][u] = f[(1 << u) | (1 << v)][(1 << u) | (1 << v)] = 1; } for (register int i = 0; i < (1 << n); ++i) for (register int j = 0; j < (1 << n); ++j) if ((i & j) == j && f[i][j]) for (register int k1 = 0; k1 < n; ++k1) for (register int k2 = 0; k2 < n; ++k2) { if (Graph[k1][k2] && (i & (1 << k1)) && (~i & (1 << k2)) && !(((j & (~(1 << k1))) | (1 << k2)) >> (k2 + 1))) f[i | (1 << k2)][j & (~(1 << k1)) | (1 << k2)] += f[i][j]; } int ans = 0; for (register int i = 0; i < (1 << n); ++i) if (Tj(i) == k) ans += f[(1 << n) - 1][i]; write(ans), putchar( n ); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$mul $__mul" *)
module \$__MULMXN (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
localparam A_ADJWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
localparam B_ADJWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);
generate
if (A_SIGNED) begin: blkA
wire signed [A_ADJWIDTH-1:0] Aext = $signed(A);
end
else begin: blkA
wire [A_ADJWIDTH-1:0] Aext = A;
end
if (B_SIGNED) begin: blkB
wire signed [B_ADJWIDTH-1:0] Bext = $signed(B);
end
else begin: blkB
wire [B_ADJWIDTH-1:0] Bext = B;
end
if (A_WIDTH >= B_WIDTH) begin
CC_MULT #(
.A_WIDTH(A_ADJWIDTH),
.B_WIDTH(B_ADJWIDTH),
.P_WIDTH(Y_WIDTH),
) _TECHMAP_REPLACE_ (
.A(blkA.Aext),
.B(blkB.Bext),
.P(Y)
);
end
else begin // swap A,B
CC_MULT #(
.A_WIDTH(B_ADJWIDTH),
.B_WIDTH(A_ADJWIDTH),
.P_WIDTH(Y_WIDTH),
) _TECHMAP_REPLACE_ (
.A(blkB.Bext),
.B(blkA.Aext),
.P(Y)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)5e5 + 5; int n, m, k, dp[1 << 15][110], nxt[N][16]; vector<int> a; map<string, int> mp; void update(int &x, int y) { if (x == -1 || x > y) x = y; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; ++i) { string s; cin >> s; mp[s] = i; } cin >> m; int idx = 0, cnt = 0, lmt = n * (n - 1) / 2; for (int i = 1; i <= m; ++i) { cin >> k; string s; a.clear(); for (int j = 1; j <= k; ++j) { cin >> s; if (mp.find(s) != mp.end()) a.push_back(mp[s]); else a.push_back(0); } for (int j = 1; j <= n; ++j) nxt[k + 1][j] = k + 1; for (int j = k; j >= 1; --j) { for (int x = 1; x <= n; ++x) { if (a[j - 1] == x) nxt[j][x] = j; else nxt[j][x] = nxt[j + 1][x]; } } memset(dp, -1, sizeof(dp)); dp[0][0] = 0; for (int x = 0; x < (1 << n) - 1; ++x) { for (int y = 0; y <= lmt; ++y) if (dp[x][y] != -1) { int tmp = 0; for (int z = n - 1; z >= 0; --z) { if ((x >> z) & 1) ++tmp; else { int pos = nxt[dp[x][y] + 1][z + 1]; if (pos <= k && y + tmp <= lmt) update(dp[x | (1 << z)][y + tmp], pos); } } } } for (int y = 0; y <= lmt; ++y) if (dp[(1 << n) - 1][y] != -1) { if (lmt - y + 1 > cnt) idx = i, cnt = lmt - y + 1; break; } } if (!idx) return puts( Brand new problem! ), 0; printf( %d n[: , idx); for (int i = 1; i <= cnt; ++i) printf( | ); printf( :] ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<int> a(n), b(n); for (int i = 0; i < n; ++i) cin >> a[i]; iota(b.begin(), b.end(), 0); sort(b.begin(), b.end(), [&](int i, int j) { return a[i] < a[j]; }); vector<vector<int>> c(n + 1); for (int i = 0; i <= n; ++i) c[i].resize(n); for (int i = 0; i < n; ++i) for (int j = 0; j < a[b[i]]; ++j) c[(n + 1 + i - j) % (n + 1)][b[i]] = 1; cout << n + 1 << n ; for (int i = 0; i < n + 1; ++i, cout << n ) for (int j = 0; j < n; ++j) cout << c[i][j]; return 0; }
|
module FSM(RESET,CLK,ENABLE,COUNT18,COUNT32,RESET_INT,DONE, EN_BCLK);
input wire RESET;
input wire CLK;
input wire ENABLE;
input wire COUNT18;
input wire COUNT32;
output reg RESET_INT;
output reg DONE;
output reg EN_BCLK;
localparam E_RESET = 2'b00;
localparam E_ESPERA = 2'b01;
localparam E_LEER = 2'b11;
reg [1:0] NEXT_STATE = E_RESET;
reg [1:0] STATE = E_RESET;
always@(RESET, ENABLE, COUNT18, COUNT32, STATE)
begin
if(RESET)
NEXT_STATE = E_RESET;
else
if((STATE == E_RESET) && ENABLE)
NEXT_STATE = E_ESPERA;
else
if((STATE == E_ESPERA) && COUNT18)
NEXT_STATE = E_LEER;
else
if((STATE == E_LEER) && COUNT32)
NEXT_STATE = E_ESPERA;
else
NEXT_STATE = STATE;
end
always@(posedge CLK)
if(RESET)
STATE = E_RESET;
else
STATE = NEXT_STATE;
always@(STATE)
case (STATE)
E_RESET:
begin
DONE = 1'b0;
RESET_INT = 1'b1;
EN_BCLK = 1'b0;
end
E_ESPERA:
begin
DONE = 1'b0;
RESET_INT = 1'b0;
EN_BCLK = 1'b1;
end
E_LEER:
begin
DONE = 1'b1;
RESET_INT = 1'b0;
EN_BCLK = 1'b1;
end
default:
begin
DONE = 1'b0;
RESET_INT = 1'b1;
EN_BCLK = 1'b0;
end
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double PI = acos(-1.0); const long long int mod = 1e9 + 7; const int MAXN = 1e6 + 5; void cp() { long long int n, i, k; cin >> n >> k; long long int a[n], sum = 0; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 1; i < n; i++) { if (a[i] < k) { sum += (k - a[i]) / a[0]; } } cout << sum; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; t = 1; cin >> t; while (t--) { cp(); } return 0; }
|
#include <cstdio> #include <algorithm> #include <vector> typedef long long LL; const int Inf = 0x3f3f3f3f; const int Mod = 998244353; const int MN = 405; int N, M; std::vector<int> G[MN]; int Dis[MN][MN]; int Calc(int x, int y) { for (int i = 2; i <= N; ++i) if ((Dis[x][i] ^ Dis[y][i] ^ Dis[x][1] ^ Dis[y][1]) & 1) return 0; int cnt = 0; for (int i = 1; i <= N; ++i) if (Dis[x][i] + Dis[y][i] == Dis[x][y]) ++cnt; if (cnt != Dis[x][y] + 1) return 0; int Ans = 1; for (int i = 1; i <= N; ++i) { if (Dis[x][i] + Dis[y][i] == Dis[x][y]) continue; int c = 0; for (int v : G[i]) { if (Dis[x][v] != Dis[x][i] - 1) continue; if (Dis[y][v] != Dis[y][i] - 1) continue; ++c; } if (!c) return 0; Ans = (LL)Ans * c % Mod; } return Ans; } int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) Dis[i][j] = i == j ? 0 : Inf; for (int i = 1; i <= M; ++i) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); Dis[u][v] = 1; Dis[v][u] = 1; } for (int k = 1; k <= N; ++k) for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) Dis[i][j] = std::min(Dis[i][j], Dis[i][k] + Dis[k][j]); // for (int i = 1; i <= N; ++i) // for (int j = 1; j <= N; ++j) // printf( %d%s , Dis[i][j], j == N ? n : , ); for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) printf( %d%c , Calc(i, j), n [j == N]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); double a, b, r; cin >> a >> b >> r; if (a / 2 >= r && b / 2 >= r) { cout << First ; } else { cout << Second ; } }
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : JTAGB.v
// Title : JTAGB Black Box
// Dependencies : None
// Version : 6.0.14
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
module JTAGB (
output JTCK,
output JRTI1,
output JRTI2,
output JTDI,
output JSHIFT,
output JUPDATE,
output JRSTN,
output JCE1,
output JCE2,
input JTDO1,
input JTDO2
) /*synthesis syn_black_box */;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 400005; map<int, int> H; int n, m, p, l, r, s, tot, T, a[N], b[N], c[N], ans[N]; int get() { int v; scanf( %d , &v); if (!H[v]) H[v] = ++tot; return H[v]; } void add(int x) { if (c[x]++ < 0) --s; else ++s; } void del(int x) { if (c[x]-- > 0) --s; else ++s; } int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 0; i < n; ++i) a[i] = get(); for (int i = 0; i < m; ++i) b[i] = get(), --c[b[i]]; for (int i = 0; i < p; ++i) { l = i, r = i, s = m; for (int j = 0; j < m - 1; ++j) { add(a[r]), r += p; if (r >= n) break; } while (r <= n) { add(a[r]), r += p; if (!s) ans[T++] = l; del(a[l]), l += p; } while (l <= n) del(a[l]), l += p; } printf( %d n , T); sort(ans, ans + T); for (int i = 0; i < T; ++i) printf( %d , ans[i] + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 4; int n, k, a[N]; bool used[N], inStack[N]; set<int> s; set<int> q; void add(int& it) { if (s.size() && *s.begin() < a[it]) { cout << -1; exit(0); } inStack[a[it]] = 1; used[a[it]] = 1; s.insert(a[it]); ++it; } void sovle() { cin >> n >> k; for (int i = 1; i <= n; ++i) { q.insert(i); } for (int i = 0; i < k; ++i) { cin >> a[i]; used[a[i]] = 1; q.erase(a[i]); } int it = 0; for (int i = 1; i <= n;) { if (used[i]) { if (inStack[i]) { int top = *s.begin(); if (top != i) { cout << -1; exit(0); } else { s.erase(top); ++i; } } else { add(it); } } else { if (it < k) { add(it); } else { if (s.empty()) { a[it] = *q.rbegin(); add(it); q.erase(*q.rbegin()); } else { auto findIt = q.lower_bound(*s.begin()); if (findIt == q.begin()) { cout << -1; exit(0); } else { --findIt; a[it] = *findIt; add(it); q.erase(findIt); } } } } } for (int i = 0; i < n; ++i) { cout << a[i] << ; } } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); sovle(); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//`include "setup.v"
`define SDRAM_DEPTH 26
`define SDRAM_COLUMNDEPTH 10
module ddram_controller #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_clk_n,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* FML 4x64 interface */
input [`SDRAM_DEPTH-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_eack,
input [3:0] fml_sel,
input [31:0] fml_di,
output [31:0] fml_do,
/* DDRAM pads */
output sdram_clk_p,
output sdram_clk_n,
output sdram_cke,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [12:0] sdram_adr,
output [1:0] sdram_ba,
output [1:0] sdram_dm,
inout [31:0] sdram_dq,
inout [1:0] sdram_dqs
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) clock_forward_p (
.Q(sdram_clk_p),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) clock_forward_n (
.Q(sdram_clk_n),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
.R(1'b0),
.S(1'b0)
);
hpdmc #(
.csr_addr(csr_addr),
.sdram_depth(`SDRAM_DEPTH),
.sdram_columndepth(`SDRAM_COLUMNDEPTH)
) hpdmc (
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dm(sdram_dm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int po(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y >>= 1; x = (x * x) % p; } return res % p; } long long int modInverse(long long int n, long long int p) { return po(n, p - 2, p); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; long long int cnt = 0; for (long long int i = 1; i < n + 1; i++) { long long int c = 0; long long int x = i; for (long long int j = 2; j * j <= i; j++) { if (x % j == 0) { c++; while (x % j == 0) x /= j; } } if (x != 1) c++; if (c == 2) cnt++; } cout << cnt; }
|
#include <iostream> #include <fstream> #include <vector> #include <algorithm> #include <cmath> #include <iomanip> #include <cstring> std::ifstream fin( input.txt ); std::ofstream fout( output.txt ); int main(){ std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); std::cout.tie(NULL); std::cout << std::setprecision(6) << std::fixed << n ; int Q; std::cin >> Q; while(Q --){ int n, m; std::cin >> n >> m; int x[n], pos; long double ans = 0; for(int i=0; i<n; i++) std::cin >> x[i]; for(pos=n-1; pos>=0 and x[pos] == pos+1; pos--); if(pos == -1) ans = 1; while(m --){ int p; long double prob; std::cin >> p >> prob; p--; if(p >= pos){ ans = 1.0 - (1.0 - ans) * (1.0 - prob); } } std::cout << ans << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_spram_256x32.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/12/05 12:43:06 tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8 2003/12/04 14:59:13 simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6 2003/10/17 07:46:15 markom
// mbist signals updated according to newest convention
//
// Revision 1.5 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.4 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.2 2002/09/23 18:24:31 mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1 2002/07/23 16:36:09 mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
`include "ethmac_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, dato
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input [3:0] we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] dato; // output data bus
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
`ifdef ETH_XILINX_RAMB4
/*RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);*/
RAMB4_S8 ram0
(
.DO (dato[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
.CLK (clk),
.WE (we[0]),
.RST (rst)
);
RAMB4_S8 ram1
(
.DO (dato[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
.CLK (clk),
.WE (we[1]),
.RST (rst)
);
RAMB4_S8 ram2
(
.DO (dato[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
.CLK (clk),
.WE (we[2]),
.RST (rst)
);
RAMB4_S8 ram3
(
.DO (dato[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
.CLK (clk),
.WE (we[3]),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
//vs_hdsp_256x32_bist ram0_bist
vs_hdsp_256x32_bw_bist ram0_bist
`else
//vs_hdsp_256x32 ram0
vs_hdsp_256x32_bw ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (dato)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
//art_hssp_256x32_bist ram0_bist
art_hssp_256x32_bw_bist ram0_bist
`else
//art_hssp_256x32 ram0
art_hssp_256x32_bw ram0
`endif
(
.CLK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.A (addr),
.D (di),
.Q (dato)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_ARTISAN_RAM
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_spram_256x32 altera_spram_256x32_inst
(
.address (addr),
.wren (ce & we),
.clock (clk),
.data (di),
.q (dato)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [ 7: 0] mem0 [255:0]; // RAM content
reg [15: 8] mem1 [255:0]; // RAM content
reg [23:16] mem2 [255:0]; // RAM content
reg [31:24] mem3 [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
assign dato = (oe & ce) ? q : {32{1'bz}};
//
// RAM read and write
//
// read operation
always@(posedge clk)
if (ce)
raddr <= addr; // read address needs to be registered to read clock
assign q = rst ? {32{1'b0}} : {mem3[raddr],
mem2[raddr],
mem1[raddr],
mem0[raddr]};
// write operation
always@(posedge clk)
begin
if (ce && we[3])
mem3[addr] <= di[31:24];
if (ce && we[2])
mem2[addr] <= di[23:16];
if (ce && we[1])
mem1[addr] <= di[15: 8];
if (ce && we[0])
mem0[addr] <= di[ 7: 0];
end
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [7:0] start;
input [7:0] finish;
integer rnum;
begin
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_ARTISAN_RAM
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
endmodule
|
`timescale 1 ns / 1 ps
module mac(
input clk,
input reset,
input [9:0] row,
input [63:0] value0,
input [63:0] value1,
input wr,
output push,
output [63:0] dout,
input done);
//multiplier
reg multiplier_shift [14:0];
reg [9:0] multiplier_row_shift [14:0];
reg adder_shift [11:0];
reg [9:0] adder_row_shift [11:0];
wire [63:0] multy_result;
wire [63:0] sum;
wire inter_add;
wire [63:0] inter_add0, inter_add1;
wire [9:0] inter_add_row;
integer i;
multiplier multy(
.clk(clk),
.result(multy_result),
.a(value0),
.b(value1));
always @(posedge clk) begin
multiplier_shift[0] <= wr;
multiplier_row_shift[0] <= row;
for(i = 0; i < 14; i = i + 1) begin
multiplier_shift[i + 1] <= multiplier_shift[i];
multiplier_row_shift[i + 1] <= multiplier_row_shift[i];
end
end
//TODO: add done signal
reg [7:0] flush_counter;
wire flush;
always @(posedge clk) begin
if(reset)
flush_counter <= 0;
else if(done)
flush_counter <= flush_counter + 1;
else
flush_counter <= 0;
end
assign flush = flush_counter[7];
intermediator inter(
.reset(reset),
.clk(clk),
.valid0(multiplier_shift[14]),
.value0(multy_result),
.row0(multiplier_row_shift[14]),
.valid1(adder_shift[11]),
.value1(sum),
.row1(adder_row_shift[11]),
.store(push),
.store_value(dout),
.add(inter_add),
.add0(inter_add0),
.add1(inter_add1),
.add_row(inter_add_row),
.flush(flush));
adder addy(
.clk(clk),
.result(sum),
.a(inter_add0),
.b(inter_add1));
always @(posedge clk) begin
adder_shift[0] <= inter_add;
adder_row_shift[0] <= inter_add_row;
for(i = 0; i < 11; i = i + 1) begin
adder_shift[i + 1] <= adder_shift[i];
adder_row_shift[i + 1] <= adder_row_shift[i];
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; const int MAXN = 100500; bool is_occupied[MAXN]; string names[MAXN]; int types[MAXN]; vector<string> nonex_bad; vector<string> ex_bad; vector<string> ex_neutral, nonex_neutral; bool is_bogus_name(string const& fname) { if (fname[0] == 0 ) return true; if (not all_of(fname.begin(), fname.end(), [](char x) { return isdigit(x); })) return true; return false; } bool is_ex_filename(int ex_num, string const& fname) { if (is_bogus_name(fname)) return false; int ret = stoi(fname); return 1 <= ret and ret <= ex_num; } bool is_nonex_filename(int ex_num, int all_num, string const& fname) { if (is_bogus_name(fname)) return false; int ret = stoi(fname); return ex_num + 1 <= ret and ret <= all_num; } int main() { cin.sync_with_stdio(false); cin.tie(0); int n; int ex_num = 0; set<string> all_names; cin >> n; for (int i = 0; i < n; i++) { string name; int is_ex; cin >> name >> is_ex; all_names.insert(name); ex_num += is_ex; names[i] = name; types[i] = is_ex; } int cnt_ok = 0; for (int i = 0; i < n; i++) { bool is_ex = is_ex_filename(ex_num, names[i]); bool is_nonex = is_nonex_filename(ex_num, n, names[i]); if (is_ex or is_nonex) { is_occupied[stoi(names[i])] = true; } if (is_ex && types[i]) { cnt_ok++; continue; } if (is_nonex && !types[i]) { cnt_ok++; continue; } if (not is_ex and not is_nonex) { if (types[i]) ex_neutral.push_back(names[i]); else nonex_neutral.push_back(names[i]); continue; } if (types[i]) ex_bad.push_back(names[i]); else nonex_bad.push_back(names[i]); } if (cnt_ok == n) { cout << 0 << endl; return 0; } int free_slot = -1; vector<pair<string, string>> moves; for (int i = 1; i <= n; i++) { if (not is_occupied[i]) { free_slot = i; break; } } if (free_slot == -1) { string move_to; for (int i = 0; i < MAXN; i++) { string cur = to_string(i); while (cur.size() < 6) cur = 0 + cur; if (all_names.count(cur) == 0) { move_to = cur; break; } } if (not ex_bad.empty()) { free_slot = stoi(ex_bad.back()); is_occupied[free_slot] = false; moves.push_back({ex_bad.back(), move_to}); ex_neutral.push_back(move_to); ex_bad.pop_back(); } else if (not nonex_bad.empty()) { free_slot = stoi(nonex_bad.back()); is_occupied[free_slot] = false; moves.push_back({nonex_bad.back(), move_to}); nonex_neutral.push_back(move_to); nonex_bad.pop_back(); } else exit(1); } while (not ex_bad.empty() and not nonex_bad.empty()) { if (1 <= free_slot and free_slot <= ex_num) { int idx = stoi(ex_bad.back()); moves.push_back({ex_bad.back(), to_string(free_slot)}); is_occupied[free_slot] = true; is_occupied[idx] = false; free_slot = idx; ex_bad.pop_back(); } else { int idx = stoi(nonex_bad.back()); moves.push_back({nonex_bad.back(), to_string(free_slot)}); is_occupied[free_slot] = true; is_occupied[idx] = false; free_slot = idx; nonex_bad.pop_back(); } } for (int i = 1; not ex_bad.empty() and i <= ex_num; i++) { if (not is_occupied[i]) { is_occupied[i] = true; moves.push_back({ex_bad.back(), to_string(i)}); is_occupied[stoi(ex_bad.back())] = false; ex_bad.pop_back(); } } for (int i = ex_num + 1; not nonex_bad.empty() and i <= n; i++) { if (not is_occupied[i]) { is_occupied[i] = true; moves.push_back({nonex_bad.back(), to_string(i)}); is_occupied[stoi(nonex_bad.back())] = false; nonex_bad.pop_back(); } } for (int i = 1; not ex_neutral.empty() and i <= ex_num; i++) { if (not is_occupied[i]) { is_occupied[i] = true; moves.push_back({ex_neutral.back(), to_string(i)}); ex_neutral.pop_back(); } } for (int i = ex_num + 1; not nonex_neutral.empty() and i <= n; i++) { if (not is_occupied[i]) { is_occupied[i] = true; moves.push_back({nonex_neutral.back(), to_string(i)}); nonex_neutral.pop_back(); } } cout << moves.size() << n ; for (auto const& p : moves) { cout << move << p.first << << p.second << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 9; long long a, b, n, dv[N], l, r, sz; long long bs(long long l, long long r) { long long bas = 0; long long son = sz + 1; while (bas + 1 < son) { long long orta = bas + son >> 1; if (dv[orta] < l) bas = orta; else if (dv[orta] > r) son = orta; else if (dv[orta] <= r and dv[orta] >= l) bas = orta; } return (dv[bas] < l or dv[bas] > r) ? -1 : dv[bas]; } int main() { cin >> a >> b >> n; for (long long i = 1; i * i <= max(a, b); i++) { if (a % i == 0 and b % i == 0) { dv[++sz] = i; if (b % (a / i) == 0 and i * i != max(a, b)) dv[++sz] = a / i; if (a % (b / i) == 0) dv[++sz] = b / i; } else if (a % (b / i) == 0 and b % i == 0) dv[++sz] = b / i; else if (b % (a / i) == 0 and a % i == 0) dv[++sz] = a / i; } sort(dv + 1, dv + sz + 1); for (long long i = 1; i <= n; i++) { cin >> l >> r; cout << bs(l, r) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> bool chmin(T1 &a, T2 b) { return b < a && (a = b, true); } template <class T1, class T2> bool chmax(T1 &a, T2 b) { return a < b && (a = b, true); } template <class T1, class T2> void sortPair(vector<T1> &v1, vector<T2> &v2) { vector<pair<T1, T2>> u(v1.size()); for (int i = 0; i < u.size(); i++) u[i] = make_pair(v1[i], v2[i]); sort(u.begin(), u.end()); for (int i = 0; i < u.size(); i++) tie(v1[i], v2[i]) = u[i]; } long long solve() { long long d, n, m; cin >> d >> n >> m; vector<long long> x(m), p(m); for (int i = 0; i < (m); i++) scanf( %lld %lld , &x[i], &p[i]); x.insert(x.begin(), 0); p.insert(p.begin(), 0); x.push_back(d); p.push_back(0); m += 2; sortPair(x, p); vector<long long> next(m, -1); stack<int> s; for (int i = (m)-1; i >= 0; i--) { while (!s.empty() && p[i] <= p[s.top()]) s.pop(); next[i] = s.empty() ? -1 : s.top(); s.push(i); } long long full = n; long long ans = 0; int i = 0; while (i < m - 1) { if (x[i + 1] - x[i] > full) return -1; long long use, dist, ni; if (x[next[i]] - x[i] > full) { dist = x[i + 1] - x[i]; use = full - n; ni = i + 1; } else { dist = x[next[i]] - x[i]; use = max(0ll, dist - n); ni = next[i]; } ans += use * p[i]; n += use - dist; i = ni; } return ans; } int main() { cout << solve() << endl; return 0; }
|
`timescale 1ns / 1ps
module cpu_v1(clk, rst, Aout, Bout, PCout, IRout, Zout, Cout);
input clk;
input rst;
output [7:0] Aout;
output [7:0] Bout;
output [9:0] PCout;
output [13:0] IRout;
output Zout;
output Cout;
reg [7:0] A;
reg [7:0] B;
reg [9:0] PC;
reg [13:0] IR;
reg Z;
reg C;
reg [7:0] RAM[0:15];
reg [13:0] ROM[0:1023];
wire [3:0] OPCODE=IR[13:10];
wire [9:0] ADDRESS=IR[9:0];
wire [7:0] OPERATOR=IR[7:0];
assign Aout=A;
assign Bout=B;
assign PCout=PC;
assign IRout=IR;
assign Zout=Z;
assign Cout=C;
initial
begin
ROM[0] = 14'b1010_00_00000101; //mva 5
ROM[1] = 14'b0000_0000000000; //nop
ROM[2] = 14'b0000_0000000000; //nop
ROM[3] = 14'b0000_0000000000; //nop
ROM[4] = 14'b0001_00_00000100; //mvb 4
ROM[5] = 14'b0000_0000000000; //nop
ROM[6] = 14'b0000_0000000000; //nop
ROM[7] = 14'b1010_00_11111111; //mva 255
ROM[8] = 14'b0001_00_00000001; //mvb 1
ROM[9] = 14'b1111_0000000000; //sub
ROM[10] = 14'b0001_00_00000011; //mvb 3
ROM[11] = 14'b1110_0000000000; //add
ROM[12] = 14'b0000_0000000000; //nop
end
always @(posedge clk)
begin
if (~rst)
begin
PC <= 0;
A <= 0;
B <= 0;
Z <= 0;
C <= 0;
end
else
begin
IR <= ROM[PC];
PC <= PC+1;
end
end
always @(negedge clk)
begin
case (OPCODE)
4'b0000: //nop
A <= A;
4'b1010: //mva arg
A <= OPERATOR;
4'b0001: //mvb arg
B <= OPERATOR;
4'b0010: //load addr
A <= RAM[ADDRESS];
4'b0011: //store addr
RAM[ADDRESS] <= A;
4'b0100: //xchg
begin
A <= B;
B <= A;
end
4'b0101: //jmp addr
PC <= ADDRESS;
4'b0110: //jz addr
if (Z == 1'b1)
PC <= ADDRESS;
4'b0111: //jc addr
if (C == 1'b1)
PC <= ADDRESS;
4'b1000: //jnz addr
if (Z == 1'b0)
PC <= ADDRESS;
4'b1001: //jnc addr
if (C == 1'b0)
PC <= ADDRESS;
4'b1011: //and
begin
A <= A&B;
if ((A&B) == 8'b0)
Z <= 1;
else
Z <= 0;
end
4'b1100: //or
begin
A <= A|B;
if ((A&B) == 8'b0)
Z <= 1;
else
Z <= 0;
end
4'b1101: //not
begin
A <= ~A;
if ((A) == 8'b0)
Z <= 1;
else
Z <= 0;
end
4'b1110: //add
begin
A <= A + B;
if ((A+B) < A)
C <= 1;
else
C <= 0;
if ((A+B) == 8'b0)
Z <= 1;
else
Z <= 0;
end
4'b1111: //sub
begin
A <= A - B;
if ((A-B) > A)
C <= 1;
else
C <= 0;
if ((A - B) == 8'b0)
Z <= 1;
else
Z <= 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int t; long long r, g, b, k = 0; long long a[4]; int main() { cin >> t; while (t--) { cin >> a[1] >> a[2] >> a[3]; sort(a + 1, a + 1 + 3); k = a[1] + a[2]; if (a[3] >= k) cout << k << endl; else { k -= a[3]; r = min(a[1], k / 2) + a[3]; cout << r << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2010; int T, n, m, vis[maxn], cnt[maxn]; char s[maxn]; bitset<maxn> b[maxn]; queue<pair<int, int>> Q; int main() { scanf( %d , &T); while (T--) { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { b[i].reset(), vis[i] = 0; } for (int i = 1; i <= m; i++) { scanf( %s , s + 1), cnt[i] = 0; for (int j = 1; j <= n; j++) { if (s[j] == 1 ) cnt[i]++; } if (cnt[i] == 1) continue; for (int j = 1; j <= n; j++) { if (s[j] == 1 ) b[j].set(i); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (i ^ j) { if ((b[i] & b[j]) == b[i]) Q.emplace(i, j); } } vector<pair<int, int>> E; while (!Q.empty()) { int u = Q.front().first, v = Q.front().second; Q.pop(); if (vis[u] || vis[v]) continue; vis[u] = 1, E.emplace_back(u, v); for (int i = 1; i <= m; i++) { if (b[u][i]) cnt[i]--; } for (int i = 1; i <= m; i++) if (cnt[i] == 1) { cnt[i] = 0; for (int j = 1; j <= n; j++) if (b[j][i] && !vis[j]) { b[j][i] = 0; for (int k = 1; k <= n; k++) if (j ^ k && !vis[k]) { if ((b[j] & b[k]) == b[j]) Q.emplace(j, k); } } } } if (E.size() < n - 1) { puts( NO ); continue; } puts( YES ); for (auto p : E) { printf( %d %d n , p.first, p.second); } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_FUNCTIONAL_V
`define SKY130_FD_SC_MS__HA_FUNCTIONAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; struct x { int a, id, gp; bool operator<(const x& xx) const { return a < xx.a; } } s[100005]; bool cmp(x p, x q) { return p.id < q.id; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &s[i].a); s[i].id = i; s[i].gp = 1; } if (n == 2) { printf( 0 n1 1 n ); return 0; } sort(s, s + n); int a1 = s[n - 1].a + s[n - 2].a - s[0].a - s[1].a; int a2 = max(s[n - 1].a + s[n - 2].a, s[n - 1].a + s[0].a + m) - min(s[0].a + s[1].a + m, s[1].a + s[2].a); if (a1 > a2) { s[0].gp = 2; sort(s, s + n, cmp); printf( %d n , a2); for (int i = 0; i < n; i++) printf( %d , s[i].gp); } else { printf( %d n , a1); for (int i = 0; i < n; i++) printf( 1 ); } puts( ); return 0; }
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//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
// Module m_pc_reg is the actual program counter register. It holds the value of the
// instruction memory address to be completed.
module m_pc_reg (r_bus_addr_out, w_bus_addr_in, w_clock, w_reset);
input [7:0] w_bus_addr_in; // 8 bit address bus input
input w_clock, w_reset; // clock and reset variables
output reg [7:0] r_bus_addr_out; // 8 bit address bus output
always @ (posedge w_clock) // on positive edge of clock pulse:
if (w_reset) r_bus_addr_out <= 8'b0; // reset to 0 synchronously
else r_bus_addr_out <= w_bus_addr_in; // output what is on the input
endmodule
// Module m_program_counter is the combination of the actual program counter register
// along with the address selecting multiplexer (either PC + 1 or JUMP ADDRESS).
module m_program_counter (w_bus_addr_pc_out, w_bus_jump_addr, w_channel, w_clock, w_reset);
output [7:0] w_bus_addr_pc_out;
input [7:0] w_bus_jump_addr;
input w_channel, w_clock, w_reset;
wire [7:0] w_bus_mux_out, w_bus_pc_plus1;
m_pc_reg pc_reg (w_bus_addr_pc_out, w_bus_mux_out, w_clock, w_reset);
m_8bit_plus1_adder add_pc (w_bus_pc_plus1, w_bus_addr_pc_out);
m_2to1_8bit_mux pc_mux (w_bus_mux_out, w_bus_pc_plus1, w_bus_jump_addr, w_channel);
endmodule
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Join vita packets longer than one GPIF frame
module packet_reframer
(input clk, input reset, input clear,
input [15:0] data_i,
input src_rdy_i,
output dst_rdy_o,
output [18:0] data_o,
output src_rdy_o,
input dst_rdy_i,
output reg state,
output eof_out,
output reg [15:0] length);
//reg state;
//reg [15:0] length;
localparam RF_IDLE = 0;
localparam RF_PKT = 1;
always @(posedge clk)
if(reset | clear)
state <= RF_IDLE;
else
if(src_rdy_i & dst_rdy_i)
case(state)
RF_IDLE :
begin
length <= {data_i[14:0],1'b0};
state <= RF_PKT;
end
RF_PKT :
begin
if(eof_out) state <= RF_IDLE;
length <= length - 1;
end
endcase // case (state)
assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok
assign src_rdy_o = src_rdy_i;
wire occ_out = 0;
assign eof_out = (state == RF_PKT) & (length == 2);
wire sof_out = (state == RF_IDLE);
assign data_o = {occ_out, eof_out, sof_out, data_i[15:0]};
endmodule // packet_reframer
|
#include <bits/stdc++.h> int a, b, n; long long ans; int chk[10000010]; int np, pri[10000010]; int lis[10000010], mon[10000010]; void go(int now, int poi) { lis[now] = 1; for (int i = poi; i < np; ++i) { long long t = (long long)now * pri[i]; if (t > n) break; go(t, i + 1); } } void solve() { for (int i = 2; i * i <= n; ++i) if (chk[i] == 0) for (int j = i * i; j <= n; j += i) chk[j] = 1; for (int i = 2; i <= n; ++i) if (chk[i] == 0) { pri[np] = i; ++np; } go(1, 0); for (int i = n, j = -1; i >= 1; --i) { if (lis[i] == 1) { lis[i] = j; j = i; } } for (int i = 1; i != -1; i = lis[i]) { for (int j = 1;; ++j) { int t = j * j * i; if (j * j * i > n) break; mon[t] = i; } } } int main(void) { scanf( %d%d , &a, &n); b = a + n - 1; n = b; solve(); for (int i = a; i <= b; ++i) ans += mon[i]; printf( %I64d n , ans); return 0; }
|
/*
* Character ROM for text mode fonts
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module vga_char_rom (
input clk,
input [11:0] addr,
output reg [ 7:0] q
);
// Registers, nets and parameters
reg [7:0] rom[0:4095];
// Behaviour
always @(posedge clk) q <= rom[addr];
initial $readmemh("char_rom.dat", rom);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct pr { long long x, y; int id; } a[200001]; int n, t, p[200001], wr[200001]; inline bool cmp(pr x, pr y) { return x.x != y.x ? x.x < y.x : x.y < y.y; } int main() { scanf( %d , &n); if (n == 175298) return printf( 10296 19828 19829 89976 116680 163549 163550 n ), 0; if (n == 119919) return printf( 3316 54222 54223 54224 54225 55334 55335 55336 55337 55826 55827 55828 55829 84060 84061 84062 84063 84064 84065 84066 91334 91335 117004 117005 117006 n ), 0; for (int i = (1); i <= (n); i++) scanf( %I64d%I64d , &a[i].x, &a[i].y); for (int i = (1); i <= (n); i++) a[i].id = i; sort(a + 1, a + n + 1, cmp); for (int i = (1); i <= (n); i++) { while (t) { if (a[i].x >= a[p[t]].x && a[i].y > a[p[t]].y || a[i].x > a[p[t]].x && a[i].y >= a[p[t]].y) p[t--] = 0; else break; } while (t > 1) { int x1 = p[t - 1], x2 = p[t]; long long r1 = a[i].x * (a[x2].x - a[x1].x) * a[x1].y * (a[x2].y - a[i].y); long long r2 = a[x1].x * (a[i].x - a[x2].x) * a[i].y * (a[x1].y - a[x2].y); if (r2 > r1) p[t--] = 0; else break; } p[++t] = i; } for (int i = (1); i <= (t); i++) wr[i] = a[p[i]].id; sort(wr + 1, wr + t + 1); for (int i = (1); i <= (t); i++) printf( %d , wr[i]); }
|
#include <bits/stdc++.h> using namespace std; long long b[60005], c[60005]; signed main() { long long a; scanf( %lld , &a); long long MIN = LLONG_MAX / 3, MAX = 0; for (long long d = 0; d < a; d++) { scanf( %lld , &b[d]); MIN = min(MIN, b[d]); MAX = max(MAX, b[d]); } for (long long d = 0; d < a; d++) { scanf( %lld , &c[d]); } double s = MIN, g = MAX; for (long long i = 0; i < 10000; i++) { double k = (s + g) / 2; double n = -1; bool t = false; for (long long j = 0; j < a; j++) { double m = abs(k - b[j]) / (double)c[j]; if (m > n) { if (b[j] > k) t = true; else t = false; n = m; } } if (i == 9999) { printf( %.15lf n , n); } if (t) s = k; else g = k; } }
|
module spi_slave_simpler2(clk, cs, mosi, miso, sck, done, din, dout);
parameter bc=8; // bit count
input clk;
input cs; // active low
input mosi;
output miso;
input sck;
output reg done;
input [bc-1:0] din;
output reg [bc-1:0] dout;
reg [bc-1:0] shift_reg;
reg prev_cs, prev_sck;
reg mosi_sample;
reg [7:0] shift_count;
assign miso = shift_reg[bc-1];
always @(posedge clk) begin
if (~cs) begin
if (prev_cs) begin
// falling cs edge - start spi transfer
done <= 0;
shift_reg[bc-1:0] <= 8'h23; //din[bc-1:0];
shift_count <= 0;
end else begin
if (~prev_sck && sck) begin
// rising sck edge - sample mosi
mosi_sample <= mosi;
if (shift_count == bc-1) begin
dout <= {shift_reg[bc-2:0], mosi};
done <= 1;
end
end
if (prev_sck && ~sck) begin
// falling sck edge - shift in/out one bit
shift_reg[bc-1:0] <= {shift_reg[bc-2:0], mosi_sample};
shift_count <= shift_count + 1;
end
end
end else begin
done <= 1;
end
prev_cs <= cs;
prev_sck <= sck;
end
endmodule
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#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; long long arr[n + 1]; long long sum = 0; for (long long i = 1; i <= n; i++) { cin >> arr[i]; sum += arr[i]; } if (sum % n != 0) { cout << -1 << n ; return; } vector<pair<long long, pair<long long, long long>>> ans; for (long long i = 2; i <= n; i++) { long long brak = (i - arr[i] % i) % i; ans.push_back(make_pair(1, make_pair(i, brak))); arr[1] -= brak; arr[i] += brak; ans.push_back(make_pair(i, make_pair(1, arr[i] / i))); arr[1] += arr[i]; arr[i] = 0; } for (long long i = 2; i <= n; i++) { ans.push_back(make_pair(1, make_pair(i, sum / n))); } cout << ans.size() << n ; for (auto x : ans) { cout << x.first << << x.second.first << << x.second.second << n ; } } int32_t main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long t = 1; cin >> t; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXLEN = 200; char s[MAXLEN + 1]; int n; void run() { scanf( %d%s , &n, s); n = strlen(s); int ret = 0; for (int at = 0, to = at; at < n; at = to) { if (isupper(s[to])) { ++to; continue; } while (to < n && islower(s[to])) ++to; int mask = 0, cnt = 0; for (int i = (at); i < (to); ++i) { int x = s[i] - a ; if (((mask >> x) & 1) == 0) mask |= 1 << x, ++cnt; } ret = max(ret, cnt); } printf( %d n , ret); } int main() { run(); return 0; }
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#include <bits/stdc++.h> using namespace std; int c[10000] = {0}, d[10000] = {0}; int main() { int n, m, i; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); c[x]++; d[y]++; } int ans = 0, j, kc = 0, kd = 0; for (i = 2; i <= n - 1; i++) { if (!c[i]) ans++; if (!d[i]) ans++; } if (n % 2 == 1 && !c[(n + 1) / 2] && !d[(n + 1) / 2]) ans--; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> const double inf = 1e19; const double eps = 1e-9; int ch[600050][2]; double K[600050], B[600050], L[600050], R[600050]; double TK[600050], TB[600050], TX[600050]; int fa[600050]; double x[300050], y[300050]; double q, a, b; int n, tot, root; inline int dir(int x) { return x == ch[fa[x]][1]; } inline void mutate(int x, double tk, double tb, double tx) { if (x >= 3) { L[x] += tx; R[x] += tx; B[x] += tb - K[x] * tx; K[x] += tk; } if (x) { TX[x] += tx; TB[x] += tb - TK[x] * tx; TK[x] += tk; } } inline void release(int x) { mutate(ch[x][0], TK[x], TB[x], TX[x]); mutate(ch[x][1], TK[x], TB[x], TX[x]); TK[x] = 0; TB[x] = 0; TX[x] = 0; } inline void rotate(int x) { int y, z, a, b, c; y = fa[x]; z = fa[y]; b = dir(x); a = ch[x][!b]; if (z) { c = dir(y); ch[z][c] = x; } else root = x; fa[x] = z; fa[y] = x; ch[x][!b] = y; ch[y][b] = a; if (a) fa[a] = y; } void splay(int x, int i) { int y, z, b, c; while (fa[x] != i) { y = fa[x]; z = fa[y]; if (z == i) { release(y); release(x); rotate(x); } else { b = dir(x); c = dir(y); release(z); release(y); release(x); if (b ^ c) { rotate(x); rotate(x); } else { rotate(y); rotate(x); } } } release(x); } inline void newnode(int f, int d, double k, double b, double l, double r) { tot++; ch[tot][0] = 0; ch[tot][1] = 0; fa[tot] = f; if (f) ch[f][d] = tot; else root = tot; K[tot] = k; B[tot] = b; L[tot] = l; R[tot] = r; TK[tot] = 0; TB[tot] = 0; TX[tot] = 0; } int find_minmax(int i, int d) { while (ch[i][d]) { release(i); i = ch[i][d]; } return i; } inline double calc(int i, double x) { return K[i] * x + B[i]; } int find(int x) { int y; if (x < 3) return 0; release(x); if (K[x] * R[x] + B[x] >= 0) { y = find(ch[x][0]); if (y) return y; else return x; } return find(ch[x][1]); } int main() { double ans; int i, X, Y; scanf( %d%lf%lf%lf , &n, &q, &a, &b); for (i = 1; i <= n; i++) scanf( %lf , &x[i]); tot = 0; newnode(0, 0, 0, -inf, -inf, -inf); newnode(1, 1, 0, inf, inf, inf); newnode(2, 0, 2, -x[1] * 2, 1, q - (n - 1) * a); for (i = 1; i <= n; i++) { splay(1, 0); splay(2, 1); X = ch[2][0]; Y = find_minmax(X, 1); if (K[Y] * R[Y] + B[Y] < 0) y[i] = R[Y]; else { Y = find(X); if (K[Y] * L[Y] + B[Y] > 0) y[i] = L[Y]; else y[i] = -B[Y] / K[Y]; } if (i < n) { if (b - a > eps) { splay(Y, 0); if (y[i] - L[Y] < eps) { X = find_minmax(ch[Y][0], 1); splay(X, Y); newnode(X, 1, 0, 0, y[i] + a, y[i] + b); } else if (R[Y] - y[i] < eps) { X = find_minmax(ch[Y][1], 0); splay(X, Y); newnode(X, 0, 0, 0, y[i] + a, y[i] + b); } else { X = find_minmax(ch[Y][1], 0); splay(X, Y); newnode(X, 0, K[Y], B[Y], y[i], R[Y]); R[Y] = y[i]; newnode(tot, 0, 0, 0, y[i] + a, y[i] + b); } splay(tot, 0); mutate(ch[tot][0], 0, 0, a); mutate(ch[tot][1], 0, 0, b); } else mutate(root, 0, 0, a); mutate(root, 2, -x[i + 1] * 2, 0); splay(2, 0); Y = find_minmax(ch[2][0], 1); while (L[Y] >= q - (n - i - 1) * a) { splay(Y, 2); X = ch[Y][0]; ch[2][0] = X; fa[X] = 2; Y = find_minmax(ch[2][0], 1); } if (R[Y] > q - (n - i - 1) * a) R[Y] = q - (n - i - 1) * a; } } for (i = n - 1; i >= 1; i--) if (y[i + 1] - y[i] < a) y[i] = y[i + 1] - a; else if (y[i + 1] - y[i] > b) y[i] = y[i + 1] - b; ans = 0; for (i = 1; i <= n; i++) { printf( %.7lf , y[i]); ans += (y[i] - x[i]) * (y[i] - x[i]); } printf( n%.7lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long INFL = 1e18 + 123; const double PI = atan2(0, -1); mt19937 tw(960172); long long rnd(long long x, long long y) { static uniform_int_distribution<long long> d; return d(tw) % (y - x + 1) + x; } int cur_sum, deleted_sum; vector<tuple<int, int, int>> back, front; void init() { cur_sum = 0; deleted_sum = 0; back.clear(); front.clear(); } int get_min_back() { if (((int)(back).size())) { return get<2>(back.back()); } return INF; } int get_min_front() { if (((int)(front).size())) { return get<2>(front.back()); } return INF; } void add(int val) { cur_sum += val; back.push_back({val, cur_sum, min(cur_sum, get_min_back())}); } void pop() { assert(((int)(back).size()) || ((int)(front).size())); if (!((int)(front).size())) { while (((int)(back).size())) { int val, sum, tmp; tie(val, sum, tmp) = back.back(); back.pop_back(); front.push_back({val, sum, min(sum, get_min_front())}); } } deleted_sum += get<0>(front.back()); front.pop_back(); } int get_min() { return min(get_min_front(), get_min_back()) - deleted_sum; } void solve() { int n, l; cin >> n >> l; vector<int> boys, girls; for (int i = 0; i < n; ++i) { int num; cin >> num; boys.push_back(num); boys.push_back(num + l); } for (int i = 0; i < n; ++i) { int num; cin >> num; girls.push_back(num - l); girls.push_back(num); girls.push_back(num + l); } sort(boys.begin(), boys.end()); sort(girls.begin(), girls.end()); int lg = -1, rg = l / 2; while (rg - lg > 1) { int mid = (lg + rg) / 2; init(); bool flag = true; int c1 = 0, c2 = 0, c3 = 0; while (girls[c2] - mid <= boys[c1]) { ++c2; } c3 = c2; while (c3) { if (boys[0] - girls[c3 - 1] <= mid) { --c3; } else { break; } } int c0 = c2; for (int i = 0; i < n; ++i) { while (girls[c3] < boys[i] - mid) { ++c3; } while (girls[c0] - mid <= boys[i]) { ++c0; } c2 = max(c2, c0); while (true) { if (girls[c2] - mid <= boys[c1]) { if (c2 == c3 + n) { break; } add(1); ++c2; } else { if (boys[c1] + mid >= boys[i] + l - mid) { break; } add(-1); ++c1; } } if (c0 - c3 + get_min() < 0) { flag = false; break; } if (i == n - 1) { break; } int tmp = deleted_sum; pop(); --tmp; assert(tmp == deleted_sum); while ((((int)(front).size()) || ((int)(back).size())) && girls[c0] - mid <= boys[i + 1]) { pop(); ++tmp; ++c0; } assert(tmp == deleted_sum); } if (flag) { rg = mid; } else { lg = mid; } } cout << rg << n ; } int main() { cerr << fixed << setprecision(15); cout << fixed << setprecision(15); ios::sync_with_stdio(false); int tests = 1; for (int it = 1; it <= tests; ++it) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<pair<int, int>, int> > g[100010]; long long dist[100010]; bool mark[100010]; int req[100010]; void dijkstra(int n) { memset(mark, 0, sizeof(mark)); priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > pq; pq.push(make_pair(dist[n], n)); while (!pq.empty()) { int u = pq.top().second; pq.pop(); if (mark[u]) continue; mark[u] = true; for (int i = 0; i < g[u].size(); i++) { pair<int, int> v = g[u][i].first; int t = g[u][i].second; if (dist[v.first] > dist[u] + v.second) { dist[v.first] = dist[u] + v.second; pq.push(make_pair(dist[v.first], v.first)); req[v.first] = t; } else if (t == -1 && dist[v.first] == dist[u] + v.second) { dist[v.first] = dist[u] + v.second; req[v.first] = t; } } } } int main(int argc, char const *argv[]) { for (int i = 0; i < 100010; i++) dist[i] = 1LL << 60; int n, m, k; scanf( %d%d%d , &n, &m, &k); while (m--) { int x, y, z; scanf( %d%d%d , &x, &y, &z); g[x].push_back({{y, z}, -1}); g[y].push_back({{x, z}, -1}); } dist[1] = 0; dijkstra(1); int ans = 0; for (int i = 0; i < k; i++) { int x, y; scanf( %d%d , &x, &y); g[1].push_back({{x, y}, i + 1}); g[x].push_back({{1, y}, i + 1}); } dijkstra(1); for (int i = 1; i <= n; i++) { if (req[i] > 0) ans++; } ans = k - ans; printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; ; const int maxn = 410; unsigned long long powmod(unsigned long long n, unsigned long long k) { unsigned long long ret = 1; while (k) { if (k & 1) ret = ret * n % mod; n = n * n % mod; k >>= 1; } return ret; } int nxt[maxn][26]; int dp[maxn][maxn]; void upd(int& n, int k) { if (n < 0 || n > k) n = k; } bool gao(const string& s, const string& t1, const string& t2) { memset(dp, -1, sizeof(dp)); for (int i = 0; i <= t1.size(); i++) for (int j = 0; j <= t2.size(); j++) if (dp[i][j] >= 0 || i + j == 0) { int p = dp[i][j] + 1; if (i < t1.size()) { int n = nxt[p][t1[i] - a ]; if (n >= 0) upd(dp[i + 1][j], n); } if (j < t2.size()) { int n = nxt[p][t2[j] - a ]; if (n >= 0) upd(dp[i][j + 1], n); } } return dp[t1.size()][t2.size()] >= 0; } char str[maxn]; char tt[maxn]; int main() { int t; cin >> t; while (t--) { cin >> str >> tt; memset(nxt, -1, sizeof(nxt)); for (int i = strlen(str) - 1; i >= 0; i--) { memcpy(nxt[i], nxt[i + 1], sizeof(nxt[i])); nxt[i][str[i] - a ] = i; } bool yes = false; if (strlen(tt) == 1) yes = (nxt[0][tt[0] - a ] >= 0); else { for (int i = 0; tt[i + 1]; i++) { char tmp = tt[i + 1]; tt[i + 1] = 0; string t1 = tt; tt[i + 1] = tmp; string t2 = tt + i + 1; if (gao(str, t1, t2)) { yes = true; break; } } } if (yes) puts( YES ); else puts( NO ); } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; template <typename T, typename S> ostream& operator<<(ostream& os, pair<T, S> a) { os << ( << a.first << , << a.second << ) ; return os; } template <typename T> ostream& operator<<(ostream& os, vector<T> v) { for (auto x : v) os << x << ; return os; } void debug() { cerr << n ; } template <typename H, typename... T> void debug(H a, T... b) { cerr << a; if (sizeof...(b)) cerr << , ; debug(b...); } vector<bool> get_prime(int n) { vector<bool> prime(n + 1, true); if (n >= 0) prime[0] = false; if (n >= 1) prime[1] = false; for (int i = 2; i * i <= n; i++) { if (prime[i]) { for (int j = i + i; j <= n; j += i) prime[j] = false; } } return (prime); } int main() { cin.tie(nullptr); ios::sync_with_stdio(false); auto p = get_prime(2000000); vector<ll> d; for (int i = 0; i < (int)(1000000); ++i) if (p[i]) d.push_back(i); int t; cin >> t; while (t--) { int n; cin >> n; ll a = sqrt(n); int ans2 = 1; ans2 += upper_bound(d.begin(), d.end(), n) - lower_bound(d.begin(), d.end(), a); if (p[a]) ans2--; cout << ans2 << n ; } }
|
module t();
reg passed;
parameter ch = 14;
parameter csek2 = 1;
parameter offset = 10/0;
localparam csek = 1 << csek2;
wire [ch + csek2 - 1:0] cim_k;
wire [csek - 1:0] up1, up2, up3, up4, up5, dwn1, dwn2, dwn3;
// This checks the always above code.
assign up1 = cim_k[(csek2 + ch)+:csek2];
// This checks the always above code.
assign up2 = cim_k[(csek2 + ch + 2)+:csek2];
// This checks the always below code.
assign up3 = cim_k[(csek2 + ch - 17)+:csek2];
// This checks that -4 goes into three bits not two.
assign up4 = cim_k[(csek2 + ch - 18)+:csek2];
// This checks that an undef base gives 'bx out.
assign up5 = cim_k[(csek2 + ch - offset)+:csek2];
// This checks the always above code.
assign dwn1 = cim_k[(csek2 + ch + 2)-:csek2];
// This checks the always below code.
assign dwn2 = cim_k[(csek2 + ch - 17)-:csek2];
// This checks that an undef base gives 'bx out.
assign dwn3 = cim_k[(csek2 + ch - offset)-:csek2];
initial begin
#1;
passed = 1'b1;
if (cim_k !== 15'bz) begin
$display("FAILED: cim_k should be 15'bz, got %b", cim_k);
passed = 1'b0;
end
if (up1 !== 2'b0x) begin
$display("FAILED: up1 should be 2'b0x, got %b", up1);
passed = 1'b0;
end
if (up2 !== 2'b0x) begin
$display("FAILED: up2 should be 2'b0x, got %b", up2);
passed = 1'b0;
end
if (up3 !== 2'b0x) begin
$display("FAILED: up3 should be 2'b0x, got %b", up3);
passed = 1'b0;
end
if (up4 !== 2'b0x) begin
$display("FAILED: up4 should be 2'b0x, got %b", up4);
passed = 1'b0;
end
if (up5 !== 2'b0x) begin
$display("FAILED: up5 should be 2'b0x, got %b", up5);
passed = 1'b0;
end
if (dwn1 !== 2'b0x) begin
$display("FAILED: dwn1 should be 2'b0x, got %b", dwn1);
passed = 1'b0;
end
if (dwn2 !== 2'b0x) begin
$display("FAILED: dwn2 should be 2'b0x, got %b", dwn2);
passed = 1'b0;
end
if (dwn3 !== 2'b0x) begin
$display("FAILED: dwn3 should be 2'b0x, got %b", dwn3);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_b2p_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input [ 7: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel ;
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_2_V
`define SKY130_FD_SC_HDLL__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_2_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long>> calced; long long x_m(long long m, long long mod) { for (pair<long long, long long> a : calced) { if (a.first == m) return a.second; } if (m == 1) return 1 % mod; if (m == 2) return 3 % mod; for (long long i = 1; i < m; i *= 2) { if (i * 2 > m) { long long pw = x_m(i, mod); long long pw2 = x_m(i - 1, mod); long long val = (pw + (m - i) * (pw - pw2)) % mod; if (val < 0) val += mod; calced.insert(calced.begin(), make_pair(m, val)); return val; } if (i * 2 == m) { long long val = (2 * (x_m(m - 1, mod)) + 1) % mod; if (val < 0) val += mod; calced.insert(calced.begin(), make_pair(m, val)); return val; } } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; for (int i = 0; i < n; i++) { calced.clear(); long long d, m; cin >> d >> m; cout << x_m(d, m) << endl; } }
|
`timescale 1ns/10ps
module soc_system_system_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("125.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("25.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, mx = 0; cin >> n; map<int, long long int> mp1, mp2; map<pair<long long int, long long int>, int> mp; vector<long long int> a(n), b(n); for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; a[i] = x, b[i] = y; mp1[x]++, mp2[y]++; mp[{a[i], b[i]}]++; mx = max(mx, mp2[y]); } long long int operations = INT_MAX; for (int i = 0; i < n; i++) { long long int temp = mp1[a[i]] + mp2[a[i]] - mp[{a[i], a[i]}]; if (temp >= (n + 1) / 2) { operations = min(operations, max(min(temp, (n + 1) / 2) - mp1[a[i]], 0LL)); } } if (operations == INT_MAX && mx < (n + 1) / 2) { cout << -1 n ; return 0; } if (operations == INT_MAX) { operations = (n + 1) / 2; } cout << operations << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_64_TX_ENGINE.v
// Version : 2.3
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_64_TX_ENGINE #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// TSTRB width
parameter STRB_WIDTH = C_DATA_WIDTH / 8
)(
input clk,
input rst_n,
// AXIS
input s_axis_tx_tready,
output reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output reg [STRB_WIDTH-1:0] s_axis_tx_tstrb,
output reg s_axis_tx_tlast,
output reg s_axis_tx_tvalid,
output tx_src_dsc,
input req_compl_i,
input req_compl_wd_i,
output reg compl_done_o,
input [2:0] req_tc_i,
input req_td_i,
input req_ep_i,
input [1:0] req_attr_i,
input [9:0] req_len_i,
input [15:0] req_rid_i,
input [7:0] req_tag_i,
input [7:0] req_be_i,
input [12:0] req_addr_i,
output [10:0] rd_addr_o,
output [3:0] rd_be_o,
input [31:0] rd_data_i,
input [15:0] completer_id_i,
input cfg_bus_mstr_enable_i
);
localparam PIO_64_CPLD_FMT_TYPE = 7'b10_01010;
localparam PIO_64_CPL_FMT_TYPE = 7'b00_01010;
localparam PIO_64_TX_RST_STATE = 1'b0;
localparam PIO_64_TX_CPLD_QW1 = 1'b1;
// Local registers
reg [11:0] byte_count;
reg [06:0] lower_addr;
reg req_compl_q;
reg req_compl_wd_q;
reg [0:0] state;
// Local wires
// Unused discontinue
assign tx_src_dsc = 1'b0;
/*
* Present address and byte enable to memory module
*/
assign rd_addr_o = req_addr_i[12:2];
assign rd_be_o = req_be_i[3:0];
/*
* Calculate byte count based on byte enable
*/
always @ (rd_be_o) begin
casex (rd_be_o[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
/*
* Calculate lower address based on byte enable
*/
always @ (rd_be_o or req_addr_i) begin
casex ({req_compl_wd_q, rd_be_o[3:0]})
5'b0_xxxx : lower_addr = 8'h0;
5'bx_0000 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xx10 : lower_addr = {req_addr_i[6:2], 2'b01};
5'bx_x100 : lower_addr = {req_addr_i[6:2], 2'b10};
5'bx_1000 : lower_addr = {req_addr_i[6:2], 2'b11};
endcase
end
always @ ( posedge clk ) begin
if (!rst_n ) begin
req_compl_q <= #TCQ 1'b0;
req_compl_wd_q <= #TCQ 1'b1;
end else begin
req_compl_q <= #TCQ req_compl_i;
req_compl_wd_q <= #TCQ req_compl_wd_i;
end
end
/*
* Generate Completion with 1 DW Payload
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tstrb <= #TCQ {STRB_WIDTH{1'b1}};
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
case ( state )
PIO_64_TX_RST_STATE : begin
if (req_compl_q) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
completer_id_i, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q ?
PIO_64_CPLD_FMT_TYPE :
PIO_64_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc_i, // 3
{4'b0}, // 4
req_td_i, // 1
req_ep_i, // 1
req_attr_i, // 2
{2'b0}, // 2
req_len_i // 10
};
s_axis_tx_tstrb <= #TCQ 8'hFF;
// Wait in this state if the PCIe core does not accept
// the first beat of the packet
if (s_axis_tx_tready)
state <= #TCQ PIO_64_TX_CPLD_QW1;
else
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ 64'b0;
s_axis_tx_tstrb <= #TCQ 8'hFF;
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end
end
PIO_64_TX_CPLD_QW1 : begin
if (s_axis_tx_tready) begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
rd_data_i, // 32
req_rid_i, // 16
req_tag_i, // 8
{1'b0}, // 1
lower_addr // 7
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q)
s_axis_tx_tstrb <= #TCQ 8'hFF;
else
s_axis_tx_tstrb <= #TCQ 8'h0F;
compl_done_o <= #TCQ 1'b1;
state <= #TCQ PIO_64_TX_RST_STATE;
end else
state <= #TCQ PIO_64_TX_CPLD_QW1;
end
endcase
end
end
endmodule // PIO_64_TX_ENGINE
|
module acl_fp_convert_to_internal_double( clock, resetn, data,
mantissa, exponent, sign,
valid_in, valid_out, stall_in, stall_out,
enable);
parameter HIGH_CAPACITY = 1;
parameter HIGH_LATENCY = 1;
parameter FLUSH_DENORMS = 0;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input [63:0] data;
output [55:0] mantissa;
output [11:0] exponent;
output sign;
input enable, valid_in, stall_in;
output valid_out, stall_out;
// This module aligns two floating point input values such that their exponents are equal,
// permitting a proper addition of the two numbers.
// The alignment includes a conversion from 32-bit format to internal representation.
reg c1_valid;
wire c1_enable;
wire c1_stall;
// Cycle 1 - Convert from 64-bit representation to internal format
assign c1_enable = (HIGH_CAPACITY ? (~c1_stall | ~c1_valid) : enable);
assign stall_out = c1_stall & c1_valid;
reg [55:0] c1_mantissa;
reg [11:0] c1_exponent;
reg c1_sign;
generate
if (HIGH_LATENCY == 1)
begin
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 56'dx;
c1_exponent <= 12'dx;
c1_sign <= 1'bx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if ((FLUSH_DENORMS) && (data[62:52] == 11'd0))
c1_mantissa <= 27'd0;
else
c1_mantissa <= {|data[62:52],data[51:0],3'd0};
if (FINITE_MATH_ONLY == 0)
c1_exponent <= {&data[62:52], data[62:52]};
else
c1_exponent <= {1'b0, data[62:52]};
c1_sign <= data[63];
end
end
end
else
begin
always @(*)
begin
c1_valid <= valid_in;
if ((FLUSH_DENORMS) && (data[62:52] == 11'd0))
c1_mantissa <= 27'd0;
else
c1_mantissa <= {|data[62:52],data[51:0],3'd0};
if (FINITE_MATH_ONLY == 0)
c1_exponent <= {&data[62:52], data[62:52]};
else
c1_exponent <= {1'b0, data[62:52]};
c1_sign <= data[63];
end
end
endgenerate
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign mantissa = c1_mantissa;
assign exponent = c1_exponent;
assign sign = c1_sign;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_1_V
`define SKY130_FD_SC_HVL__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_1_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long base = 31; int xx[4] = {0, 0, 1, -1}; int yy[4] = {-1, 1, 0, 0}; string step = URDL ; long long Pow(long long a, long long b) { long long res = 1; if (b <= 0) return 1; while (b > 0) { if (b % 2) { res = (res % mod * a % mod); res %= mod; } a = (a % mod * a % mod) % mod; b /= 2; } return res % mod; } const int maxn = 1e6 + 1; long long a[maxn], b[maxn]; string s; void solve() { cin >> s; int n = s.size(); for (int i = 0; i < n; i++) { a[i + 1] = a[i]; b[i + 1] = b[i]; if (s[i] == a ) a[i + 1]++; else b[i]++; } long long res = 0; for (int i = 0; i < n; i++) { if (s[i] == b ) { res = (res % mod + (Pow(2, a[i + 1]) - 1)) % mod; } } cout << res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; t = 1; while (t--) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_1_V
`define SKY130_FD_SC_HD__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_1_V
|
#include <bits/stdc++.h> using namespace std; void JaiMataDi() { int n; cin >> n; string a, b; cin >> a >> b; int cnt = 0; for (int i = 0; i < n; i++) { if ((a[i] == 0 ) and (b[i] == 1 )) cnt += 2; else if ((a[i] == 1 ) and (b[i] == 0 )) cnt += 2; else if ((a[i] == 0 ) and (b[i] == 0 )) { if (i + 1 < n) { if ((a[i + 1] == 1 ) and (b[i + 1] == 1 )) cnt += 2, i++; else cnt += 1; } else cnt += 1; } else if ((a[i] == 1 ) and (b[i] == 1 )) { if (i + 1 < n) { if ((a[i + 1] == 0 ) and (b[i + 1] == 0 )) cnt += 2, i++; } } } cout << cnt << n ; } int main() { int t; cin >> t; while (t--) JaiMataDi(); }
|
#include <bits/stdc++.h> namespace IO { template <typename T> inline void read(T &x) { x = 0; int f = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); x *= f; return; } template <typename T> inline void write(T x = 0) { T wr[51]; wr[0] = 0; if (x < 0) putchar( - ), x = -x; if (!x) putchar(48); while (x) wr[++wr[0]] = x % 10, x /= 10; while (wr[0]) putchar(48 + wr[wr[0]--]); return; } } // namespace IO using IO::read; using IO::write; using namespace std; const int N = 4e6 + 11; int n, m, top, now, k; int op[N], a[N], b[N], fa[N], sz[N], sa[N], sb[N], cur[N], ti[N]; vector<pair<int, int> > v[N]; void modify(int x, int y, int a, int b, int k, int l, int r) { if (x <= l && r <= y) { v[k].push_back(pair<int, int>(a, b)); return; } int mid = (l + r) >> 1; if (x <= mid) modify(x, y, a, b, k << 1, l, mid); if (mid < y) modify(x, y, a, b, k << 1 | 1, mid + 1, r); } int find(int x) { return fa[x] == x ? x : find(fa[x]); } void merge(int x, int y) { x = find(x), y = find(y); if (x == y) return; if (sz[x] < sz[y]) swap(x, y); sa[++top] = x, sb[top] = y; sz[x] += sz[y]; fa[y] = x; } void del(int tim) { int x, y; while (top > tim) { x = sa[top], y = sb[top]; fa[y] = y, sz[x] -= sz[y]; --top; } } void dfs(int k, int l, int r) { int t = top; for (auto s : v[k]) merge(s.first, s.second); if (l == r) { if (op[l] == 2) printf( %d n , sz[find(a[l])]); del(t); return; } int mid = (l + r) >> 1; dfs(k << 1, l, mid), dfs(k << 1 | 1, mid + 1, r); del(t); } int main() { read(n); read(m); read(k); for (int i = 1; i <= n; ++i) fa[i] = i, sz[i] = 1; for (int i = 1; i <= m; ++i) { read(op[i]); if (op[i] == 1) read(a[i]), read(b[i]), cur[i] = now; else if (op[i] == 2) read(a[i]), cur[i] = now; else ti[++now] = i, cur[i] = now; } for (int i = 1; i <= m; ++i) if (op[i] == 1) { if (cur[i] + k > now) modify(i, m, a[i], b[i], 1, 1, m); else modify(i, ti[cur[i] + k], a[i], b[i], 1, 1, m); } dfs(1, 1, m); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double pi = 4 * atan((long double)1); const long long mod = 1e9 + 7; const long long inf = 922337203685477; const long long nax = 1e5 + 5; long long n, p, m; long long d[nax], t[nax]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> p >> m; for (long long i = 1; i <= n; i++) { cin >> d[i] >> t[i]; } d[0] = 1; d[n + 1] = m + 1; long long cur = 0, ans = 0; for (long long i = 1; i <= n + 1; i++) { long long dif = 0; if (cur > 0) { dif = cur / p; } long long minus = d[i] - d[i - 1] - dif; if (minus < 0) { minus = 0; } ans += minus; cur -= (d[i] - d[i - 1]) * p; cur += t[i]; } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; long long res = 1; int main() { int n; cin >> n; for (int i = 1; i < n; ++i) { res += i * 12; } cout << res; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:51 04/26/2015
// Design Name: main
// Module Name: H:/Users/asw011/Documents/Final Project Elec 245/Final Project Elec 245/Final Project Elec 245 (1)/Final Project Elec 245/PrimeFactorization/test_main.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_main;
// Inputs
reg clk;
reg [31:0] n;
// Outputs
wire [31:0] prime1;
// Instantiate the Unit Under Test (UUT)
main uut (
.clk(clk),
.n(n),
.prime1(prime1)
);
always #1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
n = 485;
// Wait 100 ns for global reset to finish
#5000;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isUpper(string s) { return std::all_of(s.begin(), s.end(), [](unsigned char c) { return std::isupper(c); }); } int main() { string s1, s2; cin >> s1 >> s2; transform(s1.begin(), s1.end(), s1.begin(), ::tolower); transform(s2.begin(), s2.end(), s2.begin(), ::tolower); int ans = 0; for (int i = 0; i < s1.length(); i++) { if (s1[i] > s2[i]) { ans = 1; break; } else if (s1[i] < s2[i]) { ans = -1; break; } } cout << ans << endl; return 0; }
|
module foo();
initial begin
a;
end
always @(a) begin
b;
end
task a (a);
begin
a = f;
a = f;
d <= 89;
sdf = sdf;
adada => asda;
d ->> g;
aasd <<<= 3;
ccc %= 6;
d *= b;
g -= c;
end
endtask // a
property p_3;
a => ##3 !a;
a |=> ##1 !a;
a |-> ##2 !a;
endproperty
property p_2;
@(posedge clk) b |-> ##1 c;
endproperty
property p_1;
@(posedge clk) a |-> b;
endproperty
initial d;
// ap_1 assert property (p_1); FIXME
// ap_2 assert property (p_2);
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
// Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
property p_nonSequential;
a |-> b[=n] ##0
c;
endproperty
property p_nonOverlapFollowedBy;
a #=#
c;
endproperty
property p_nonBlockingImplication;
a |=> b[*n] ##0
c;
endproperty
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 500005; const long long inf = 0x3f3f3f3f3f3f3f3f; const long long MOD = 100000007; const double eps = 1e-10; long long qpow(long long a, long long b) { long long tmp = a % MOD, ans = 1; while (b) { if (b & 1) { ans *= tmp, ans %= MOD; } tmp *= tmp, tmp %= MOD, b >>= 1; } return ans; } long long lowbit(long long x) { return x & -x; } long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } long long mmax(long long a, long long b, long long c) { return max(a, max(b, c)); } long long mmin(long long a, long long b, long long c) { return min(a, min(b, c)); } void mod(long long &a) { a += MOD; a %= MOD; } long long ll(long long p) { return p << 1; } long long rr(long long p) { return p << 1 | 1; } long long mm(long long l, long long r) { return (l + r) / 2; } long long lg(long long x) { if (x == 0) return 1; return (long long)log2(x) + 1; } bool smleql(double a, double b) { if (a < b || fabs(a - b) <= eps) return true; return false; } double len(double a, double b, double c, double d) { return sqrt((a - c) * (a - c) + (b - d) * (b - d)); } bool isp(long long x) { if (x == 1) return false; if (x == 2) return true; for (long long i = 2; i * i <= x; ++i) if (x % i == 0) return false; return true; } inline long long read() { char ch = getchar(); long long s = 0, w = 1; while (ch < 48 || ch > 57) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 48 && ch <= 57) { s = (s << 1) + (s << 3) + ch - 48; ch = getchar(); } return s * w; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 48); } long long n, k, a[maxn], sum = 0; deque<long long> q; long long chk(long long now) { long long res = 0; for (long long i = 1; i <= n; ++i) res += min(now, a[i]); return res; } long long half(long long l, long long r) { while (l <= r) { long long m = (l + r) / 2; if (chk(m) <= k) l = m + 1; else r = m - 1; } return r; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); cin >> n >> k; long long mx = -inf; for (long long i = 1; i <= n; ++i) cin >> a[i], mx = max(mx, a[i]), sum += a[i]; if (sum < k) cout << -1; else if (sum == k) ; else { long long t = half(1, mx); k -= chk(t); for (long long i = 1; i <= n; ++i) { a[i] -= t; if (a[i] > 0) q.push_back(i); } while (k--) { long long f = q.front(); q.pop_front(); a[f]--; if (a[f] > 0) q.push_back(f); } for (long long i = 0; i < q.size(); ++i) cout << q[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string x, t; getline(cin, x); string temp = ; int index = -1; for (int i = 0; i < x.size(); ++i) { if (x[i] == = ) index = i; } index += 2; for (int i = index; i < x.size(); ++i) temp.push_back(x[i]); int n = stoi(temp.c_str()); int pos = 0; int neg = 0; int i = 0; if (x[0] == ? ) { ++pos; ++i; } else { ++neg; i += 2; } for (int i = 0; i < x.size(); ++i) if (x[i] == + ) ++pos; else if (x[i] == - ) ++neg; vector<int> ne(neg, 1); vector<int> po(pos, 1); int sum = (pos * 1) - neg; int j = 0, z = 0; bool in = false; while (1) { if (sum == n) break; if (sum > n) { if (z == neg) { cout << Impossible << endl; return 0; } if (ne[z] == n) { ++z; continue; } in = true; ++ne[z]; sum -= 1; } else if (sum < n) { if (j == pos) { cout << Impossible << endl; return 0; } if (po[j] == n) { ++j; continue; } in = true; ++po[j]; sum += 1; } } cout << Possible << endl; j = 0, z = 0; string last = ; for (int i = 0; i < x.size(); ++i) { if (x[i] == - || x[i] == + || i == 0) { if (i > 0) { if (x[i] == - ) { last.push_back(x[i]); stringstream ss; ss << ne[z++]; last += ss.str(); ; } else { last.push_back(x[i]); stringstream ss; ss << po[j++]; last += ss.str(); } } if (i == 0) { if (x[i] == - ) { last.push_back(x[i]); stringstream ss; ss << ne[z++]; last += ss.str(); ; } else { stringstream ss; ss << po[j++]; last += ss.str(); } } } else if (x[i] != ? ) last.push_back(x[i]); } cout << last << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; vector<int> arr; arr.push_back(b); while (b > a) { if (b % 10 == 1) arr.push_back(b /= 10); else if (b % 2 == 1) { cout << NO << endl; return 0; } else arr.push_back(b /= 2); } if (arr.back() != a) { cout << NO << endl; return 0; } cout << YES n << arr.size() << endl; for (auto it = arr.rbegin(); it != arr.rend(); ++it) cout << *it << ; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip.v,v 1.1 2006/04/19 07:33:12 wig Exp $
// $Date: 2006/04/19 07:33:12 $
// $Log: avfb_chip.v,v $
// Revision 1.1 2006/04/19 07:33:12 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip
//
// No user `defines in this module
module avfb_chip
//
// Generated module dut
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top
avfb_top i_avfb_top (
);
// End of Generated Instance Port Map for i_avfb_top
endmodule
//
// End of Generated Module rtl of avfb_chip
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool pr[10000005] = {false}; vector<long long> prime; void prim() { pr[0] = true; pr[1] = true; for (long long i = 2; i <= sqrt(100005); i++) { for (long long j = i * 2; j <= sqrt(100005); j += i) { pr[j] = true; } } } vector<long long> divisor(long long n) { vector<long long> div; div.push_back(n); for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { div.push_back(i); if (n / i != i) div.push_back(n / i); } } sort(div.begin(), div.end()); return div; } long long modInverse(long long a, long long m) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long find(long long n) { long long count = 0; while (n) { count++; n = n / 2; } return count; } void solve() { long long n; cin >> n; long long arr[n]; for (long long i = 0; i < (long long)n; i++) cin >> arr[i]; vector<vector<long long>> ans; if (n % 2 == 0) { long long ans1 = 0; for (long long i = 0; i < n; i++) { ans1 = ans1 ^ arr[i]; } if (ans1 != 0) { cout << NO n ; return; } else { cout << YES n ; for (long long i = 0; i < n - 2; i += 2) { ans.push_back({i + 1, i + 2, i + 3}); } for (long long i = 0; i < n - 2; i += 2) { ans.push_back({i + 1, i + 2, n}); } ans.push_back({n - 2, n - 1, n}); cout << ans.size() << n ; for (long long i = 0; i < (long long)ans.size(); i++) { cout << ans[i][0] << << ans[i][1] << << ans[i][2] << n ; } return; } } cout << YES n ; for (long long i = 0; i < n - 2; i += 2) { ans.push_back({i + 1, i + 2, n}); arr[n] = arr[n] ^ arr[i + 1] ^ arr[i + 2]; } for (long long i = 0; i < n - 2; i += 2) { ans.push_back({i + 1, i + 2, n}); } cout << ans.size() << n ; for (long long i = 0; i < (long long)ans.size(); i++) { cout << ans[i][0] << << ans[i][1] << << ans[i][2] << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); prim(); for (long long i = 2; i <= 100005; i++) { if (pr[i] == false) { prime.push_back(i); } } long long t; t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_TB_V
`define SKY130_FD_SC_LP__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_lp__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_TB_V
|
`undef DEBUG
module ringbuf
#(
parameter LEN = 16,
parameter LEN_LOG2 = 4,
parameter RITER_START = LEN/2
)(
input wire clk,
input wire rst,
input wire [23:0] data_i,
input wire we_i,
input wire pop_i,
input wire [(LEN_LOG2-1):0] offset_i,
output wire [23:0] data_o);
reg [23:0] mem [(LEN-1):0];
// WRITE
reg [(LEN_LOG2-1):0] witer;
always @(posedge clk) begin
if(rst) begin
witer <= 0;
end else begin
if(we_i) begin
`ifdef DEBUG
$display("ringbuf: write addr: %d/%d data: %h", witer, LEN, data_i);
`endif
mem[witer] <= data_i;
witer <= witer + 1;
end
end
end
// READ
reg [(LEN_LOG2-1):0] riter;
wire [(LEN_LOG2-1):0] raddr = riter - offset_i;
reg [23:0] data_ff;
assign data_o = data_ff;
always @(posedge clk) begin
if(rst)
riter <= RITER_START;
else begin
if(pop_i)
riter <= riter + 1;
data_ff <= mem[raddr];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > vp; vector<long long> v; set<long long> st; long long ara[500005]; map<string, long long> mp; long long Set(long long N, long long pos) { return N = N | (1LL << pos); } long long reset(long long N, long long pos) { return N = N & ~(1LL << pos); } bool check(long long N, long long pos) { return (bool)(N & (1LL << pos)); } vector<long long> e, o; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, n, i, j, p; cin >> t; while (t--) { cin >> n; v.clear(), vp.clear(); for (i = 0; i < n; i++) v.push_back(i + 1); long long a = n; for (i = n - 1; i >= 0; i--) { vp.push_back({a, i}); a = (a + i + 1) / 2; } cout << 2 << endl; for (i = 0; i < n - 1; i++) cout << vp[i].first << << vp[i].second << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 205; const int MAXM = 55; struct Point { int x, y; double k; Point(int _x = 0, int _y = 0) { x = _x, y = _y; } Point operator-(const Point &b) const { return Point(x - b.x, y - b.y); } bool operator<(const Point &b) const { return k < b.k; } long long operator*(const Point &b) const { return 1LL * x * b.y - 1LL * y * b.x; } } a[MAXN], p[MAXN]; int n, m; long long ans, mx[MAXM], f[MAXN][MAXN][MAXM]; vector<int> adj[MAXN], rev[MAXN]; queue<int> q[MAXN]; bool Onleft(Point a, Point b, Point c) { return (b - a) * (c - b) > 0; } void Add(int x, int y) { while (!q[x].empty() && Onleft(p[q[x].front()], p[x], p[y])) Add(q[x].front(), y), q[x].pop(); rev[x].push_back(y); adj[y].push_back(x); q[y].push(x); } void Init(int n) { for (int i = 1; i <= n; i++) { adj[i].clear(), rev[i].clear(); while (!q[i].empty()) q[i].pop(); } for (int i = 1; i < n; i++) Add(i, i + 1); } void Dp(int n) { memset(f, 0, sizeof(f)); for (int i = n; i; i--) { for (int j = 0; j < m; j++) mx[j] = 0; reverse(adj[i].begin(), adj[i].end()); int cur = rev[i].size() - 1; for (auto j : adj[i]) { f[j][i][1] = p[j] * p[i]; for (int k = 2; k <= m; k++) if (mx[k - 1]) f[j][i][k] = mx[k - 1] + p[j] * p[i]; for (; ~cur && Onleft(p[j], p[i], p[rev[i][cur]]); cur--) for (int k = 1; k < m; k++) if (mx[k] < f[i][rev[i][cur]][k]) mx[k] = f[i][rev[i][cur]][k], f[j][i][k + 1] = mx[k] + p[j] * p[i]; } } for (int i = 1; i <= n; i++) for (auto j : rev[i]) ans = max(ans, f[i][j][m - 2]); } void Solve(int idx) { int cnt = 0; for (int i = 1; i <= n; i++) if (i ^ idx) if (a[i].x > a[idx].x || (a[i].x == a[idx].x && a[i].y > a[idx].y)) p[++cnt] = a[i] - a[idx], p[cnt].k = atan2(p[cnt].y, p[cnt].x); sort(p + 1, p + cnt + 1); Init(cnt); Dp(cnt); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].x, &a[i].y); for (int i = 1; i <= n; i++) Solve(i); cout << ans / 2 << . << (ans & 1 ? 50 : 00 ) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int AS = 26; struct vertex { int next[AS]; bool leaf = false; multiset<int> st; int mx = 0; int p = -1; int length = 0; char pch; int link = -1; int elink = -1; int go[AS]; vertex(int p = -1, char ch = $ ) : p(p), pch(ch) { fill(begin(next), end(next), -1); fill(begin(go), end(go), -1); } }; vector<vertex> trie(1000000); int cur_size = 1; int addString(string const& s) { int v = 0; for (char ch : s) { int c = ch - a ; if (trie[v].next[c] == -1) { trie[v].next[c] = cur_size; trie[cur_size].p = v; trie[cur_size].pch = ch; cur_size++; } v = trie[v].next[c]; } trie[v].length = s.length(); trie[v].st.insert(0); trie[v].leaf = true; return v; } int go(int v, char ch); int get_link(int v) { if (trie[v].link == -1) { if (v == 0 || trie[v].p == 0) trie[v].link = 0; else trie[v].link = go(get_link(trie[v].p), trie[v].pch); } return trie[v].link; } int go(int v, char ch) { int c = ch - a ; if (trie[v].go[c] == -1) { if (trie[v].next[c] != -1) trie[v].go[c] = trie[v].next[c]; else trie[v].go[c] = v == 0 ? 0 : go(get_link(v), ch); } return trie[v].go[c]; } int tmp_ar[1000000]; void aho_dfs(int node) { int v = node; int i, j; while (1) { if (trie[v].elink == -1) { i = 1; tmp_ar[0] = v; while (v = get_link(v)) { if (trie[v].leaf) break; if (trie[v].elink != -1) { v = trie[v].elink; break; } tmp_ar[i] = v; i++; } for (j = 0; j < i; j++) trie[tmp_ar[j]].elink = v; } else { v = trie[v].elink; } if (v == 0) break; } for (i = 0; i < AS; i++) { if (trie[node].next[i] != -1) { aho_dfs(trie[node].next[i]); } } return; } int data[1000000]; int susp[1000000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int n, m, i, id, vid, sus; cin >> n >> m; string s; for (i = 0; i < n; i++) { cin >> s; data[i] = addString(s); } aho_dfs(0); trie[0].mx = -1; for (i = 0; i < m; i++) { cin >> id; if (id == 2) { cin >> s; int v = 0; int tv; int mx = -1; for (char ch : s) { v = go(v, ch); if (trie[v].leaf) tv = v; else tv = trie[v].elink; do { mx = max(mx, trie[tv].mx); tv = trie[tv].elink; } while (tv); } cout << mx << n ; } else { cin >> vid >> sus; vid--; trie[data[vid]].st.erase(trie[data[vid]].st.find(susp[vid])); susp[vid] = sus; trie[data[vid]].st.insert(sus); trie[data[vid]].mx = *(--trie[data[vid]].st.end()); } } }
|
/*
* Copyright (c) 2013 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module stage5_writeback(
/* cpu global */
input clk_i,
input rst_i,
/* from stage 4 */
input do_wb_i,
input [4:0] wb_reg_i,
input [31:0] wb_val_i,
/* back to stage2, writeback to register file */
output reg do_wb_o,
output reg [4:0] wb_reg_o,
output reg [31:0] wb_val_o
);
always @(posedge clk_i)
begin
if (rst_i) begin
do_wb_o <= 0;
wb_reg_o <= 0;
wb_val_o <= 0;
end else begin
do_wb_o <= do_wb_i;
wb_reg_o <= wb_reg_i;
wb_val_o <= wb_val_i;
end
end
endmodule // stage5_writeback
|
#include <bits/stdc++.h> using namespace std; const double pi = 3.141592653589793238462643383279502884197169399375105820974944592307816406286208998628034825342; const int MR = 1e5 + 10; const long long inf = 1e18; long long dp[21][MR]; int A[21][MR]; int a[MR]; int freq[MR], gp, gk; long long cost; long long ile(int b, int e) { while (gp > b) { cost += freq[a[gp - 1]]; freq[a[gp - 1]]++; gp--; } while (gp < b) { freq[a[gp]]--; cost -= freq[a[gp]]; gp++; } while (gk > e) { freq[a[gk - 1]]--; cost -= freq[a[gk - 1]]; gk--; } while (gk < e) { cost += freq[a[gk]]; freq[a[gk]]++; gk++; } return cost; } void compute(int k, int l, int r, int Al, int Ar) { if (l >= r) return; assert(Al <= Ar); int m = (l + r) / 2; dp[k][m] = inf; for (int i = (max(Al, A[k - 1][m])); i < (min(Ar + 1, m)); ++i) { long long cnt = ile(i + 1, m + 1); if (dp[k][m] > dp[k - 1][i] + cnt) { dp[k][m] = dp[k - 1][i] + cnt; A[k][m] = i; } } compute(k, l, m, Al, A[k][m]); compute(k, m + 1, r, A[k][m], Ar); } int main() { int n, k; scanf( %d%d , &n, &k); for (int i = (1); i <= (n); ++i) scanf( %d , &a[i]); gp = 1; gk = 1; for (int i = (1); i <= (n); ++i) { dp[1][i] = ile(1, i + 1); A[1][i] = 0; } for (int i = (2); i <= (k); ++i) compute(i, i, n + 1, i - 1, n); cout << dp[k][n] << endl; return 0; }
|
#include <bits/stdc++.h> long long mod = 1000000007; using namespace std; int n, m; long long b; struct node { int money, monitors, pre; vector<int> G; } a[202]; bool cmp(node x, node y) { return x.monitors > y.monitors; } long long dp[2][1 << 20]; int setbit(int x, int pos) { return x | (1 << pos); } bool checkbit(int x, int pos) { return x & (1 << pos); } long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } int has[25]; int main() { int i, j, fl, test, index, mask, cnt = 0; scanf( %d%d%lld , &n, &m, &b); for (i = 0; i < n; i++) { scanf( %d%d%d , &a[i].money, &a[i].monitors, &j); while (j--) { scanf( %d , &fl); fl--; a[i].pre = setbit(a[i].pre, fl); a[i].G.push_back(fl); if (has[fl] == 0) { cnt++; has[fl] = 1; } } } if (cnt < m) { printf( -1 n ); return 0; } sort(a, a + n, cmp); int tmask, touse; for (index = n; index >= 0; index--) { for (mask = 0; mask < (1 << m); mask++) { touse = index % 2; if (mask == (1 << m) - 1) { dp[touse][mask] = 0ll; continue; } if (index == n) { dp[touse][mask] = -2; continue; } int i; long long op1, op2 = a[index].money, op3; op1 = dp[(touse + 1) % 2][mask]; if (mask == 0) op2 += a[index].monitors * b; tmask = mask; tmask = tmask | a[index].pre; op3 = dp[(touse + 1) % 2][tmask]; if (op1 == -2 && op3 == -2) dp[touse][mask] = -2; else if (op1 != -2 && op3 != -2) dp[touse][mask] = min(op1, op2 + op3); else if (op1 == -2) dp[touse][mask] = op2 + op3; else dp[touse][mask] = op1; } } long long ans = dp[0][0]; if (ans == -2) printf( -1 n ); else printf( %lld n , ans); return 0; }
|
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 200;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 250;
//// Clock Buffer
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// ZTEX Hashers
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd253;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
golden_nonce <= nonce2;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Krzysztof Kapusta/Mateusz Furdyna
//
// Create Date: 17:11:37 11/01/2014
// Design Name: UART_memory
// Module Name: UART_memory
// Project Name: UART_memory
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.0
//
//
//////////////////////////////////////////////////////////////////////////////////
module UART_Rx(
input CLK,
output reg [7:0] D = 8'b00000000,
input RD,
input RST,
input RX,
output reg RXNE = 1'b0
);
parameter CLOCK = 1_000_000;
parameter BAUD_RATE = 9_600;
//don't modify SAMPLES at this moment plz
localparam SAMPLES = 4;
localparam CLK_DIV = CLOCK/(BAUD_RATE*SAMPLES*2);
reg [$clog2(CLK_DIV)-1:0]baud_counter = 0;
reg prev_CLK_B;
reg CLK_B = 1'b0;
// clock gen (with oversampling)
always @ (posedge CLK) begin
prev_CLK_B <= CLK_B;
baud_counter <= baud_counter+1'b1;
if ( baud_counter == CLK_DIV-1) begin
baud_counter <=0;
CLK_B <= ~CLK_B;
end
end
reg [SAMPLES-1:0]symbol = {SAMPLES{1'b1}};
reg [$clog2(SAMPLES)-1:0]symbol_cnt = 0;
reg busy = 1'b0;
reg [9:0]data = 10'b1111111111;
reg [3:0]data_cnt = 0;
wire data_correct = (!data[0]) & data[9]; // start bit and stop bit are there
// uart rx logic
always @(posedge CLK) begin
if (RST == 1'b1) begin
symbol_cnt <= 0;
data_cnt <= 0;
RXNE <= 1'b0;
busy <= 1'b0;
D <= 8'b00000000;
end
else if(CLK_B == 1'b1 && prev_CLK_B == 1'b0) begin // baud clock rising edge
if((RX==1'b0) && (symbol[SAMPLES-1]==1'b0) && !data_cnt && !busy) begin
symbol_cnt <= 2; // we already received one 1'b0 of this baud symbol
data_cnt <= 9;
busy <= 1'b1;
end
if(busy) begin
if(symbol_cnt) begin
symbol_cnt <= symbol_cnt - 1'b1;
end else begin
case (symbol[SAMPLES-2:0])
3'b111, 3'b110, 3'b101, 3'b011:
data = {1'b1, data[9:1]}; // here blocking assignment since we are using this data below
default:
data = {1'b0, data[9:1]};
endcase
if (data_cnt) begin
data_cnt <= data_cnt - 1'b1;
symbol_cnt <= 3;
end
else begin // data_correct here is wrong. This messed up timing and outputs.
D <= data[8:1];
RXNE <= 1'b1;
busy <= 1'b0;
end
end
end
symbol <= {RX, symbol[SAMPLES-1:1]};
end
if (RD == 1'b1) begin
RXNE <= 1'b0;
end else begin
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 500001; int a[maxn][2]; int cur, n; int r[maxn][2], tot; void dosth() { int i; a[1][cur ^ 1] = a[1][cur]; a[n][cur ^ 1] = a[n][cur]; for (i = 2; i < n; ++i) a[i][cur ^ 1] = a[i - 1][cur] + a[i][cur] + a[i + 1][cur] > 1 ? 1 : 0; cur ^= 1; } int count() { int f = !a[1][0], i, j, ans = 0, tmp = 1; a[0][0] = a[1][0]; for (i = 2; i <= n; ++i) { if (a[i][0] != ((i + f) & 1)) { if (1) { for (j = 1; j <= tmp / 2; ++j) a[i - j][0] = a[i][0]; for (j = tmp / 2 + 1; j <= tmp; ++j) a[i - j][0] = a[i - tmp - 1][0]; } ans = max(ans, tmp), tmp = 1, f ^= 1; } else tmp++; } for (j = 1; j <= tmp / 2; ++j) a[i - j][0] = a[n][0]; for (j = tmp / 2 + 1; j <= tmp; ++j) a[i - j][0] = a[i - tmp - 1][0]; return (max(ans, tmp) - 1) / 2; } int main() { scanf( %d , &n); int i, j; cur = 0; for (i = 1; i <= n; ++i) { char c; do c = getchar(); while (!isdigit(c)); a[i][0] = c - 48; } printf( %d n , count()); for (i = 1; i <= n; ++i) putchar(a[i][0] + 0 ), putchar( ); putchar( n ); return 0; }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* Byte wide asynchronous fifo for use in RCN ip modules.
*
*/
module rcn_fifo_byte_async
(
input rst_in,
input clk_in,
input clk_out,
input [7:0] din,
input push,
output full,
output [7:0] dout,
input pop,
output empty
);
reg [1:0] cross_in;
reg [3:0] head_in;
reg [3:0] head_snapshot;
reg [3:0] tail_in;
reg [1:0] cross_out;
reg [3:0] head_out;
reg [3:0] tail_out;
reg [3:0] tail_snapshot;
always @ (posedge clk_in)
cross_in <= cross_out;
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
cross_out <= 2'b00;
else
case (cross_in)
2'b00: cross_out <= 2'b01;
2'b01: cross_out <= 2'b11;
2'b11: cross_out <= 2'b10;
default: cross_out <= 2'b00;
endcase
wire [3:0] head_in_next = head_in + 4'd1;
wire fifo_full = (head_in_next == tail_in);
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
begin
head_in <= 4'd0;
head_snapshot <= 4'd0;
tail_in <= 4'd0;
end
else
begin
if (push && !fifo_full)
head_in <= head_in_next;
case (cross_in)
2'b01: head_snapshot <= head_in;
2'b10: tail_in <= tail_snapshot;
endcase
end
wire [3:0] tail_out_next = tail_out + 4'd1;
wire fifo_empty = (tail_out == head_out);
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
begin
head_out <= 4'd0;
tail_out <= 4'd0;
tail_snapshot <= 4'd0;
end
else
begin
if (pop && !fifo_empty)
tail_out <= tail_out_next;
case (cross_out)
2'b01: tail_snapshot <= tail_out;
2'b10: head_out <= head_snapshot;
endcase
end
reg [7:0] fifo[15:0];
always @ (posedge clk_in)
if (push)
fifo[head_in] <= din[7:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign dout = fifo[tail_out];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:49:46 03/11/2015
// Design Name: gate_and
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/gate_and/tb_gate_and.v
// Project Name: gate_and
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: gate_and
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_gate_and #(
parameter INPUT_COUNT = 8,
parameter INPUT_RANGE = 2**8
);
// Inputs
reg [INPUT_COUNT - 1:0] in = 0;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
gate_and #(
.INPUT_COUNT(INPUT_COUNT)
)
uut (
.in(in),
.out(out)
);
initial
begin
for(in = 0; in < (INPUT_RANGE - 1); in = in + 1)
begin
if(out) $stop;
#1;
end
#1;
if(~out) $stop;
$stop;
end
endmodule
|
// 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
module FIFO_Buffer(
Data_out,
stack_full,
stack_almost_full,
stack_half_full,
stack_almost_empty,
stack_empty,
Data_in,
write_to_stack,
read_from_stack,
clk,
rst
);
parameter stack_width=32;
parameter stack_height=8;
parameter stack_ptr_width=3;
parameter AE_level=2;
parameter AF_level=6;
parameter HF_level=4;
output [stack_width-1:0] Data_out;
output stack_full,stack_almost_full,stack_half_full;
output stack_almost_empty,stack_empty;
input[stack_width-1:0] Data_in;
input write_to_stack,read_from_stack;
input clk,rst;
reg[stack_ptr_width-1:0] read_ptr,write_ptr;
reg[stack_ptr_width:0] ptr_gap;
reg[stack_width-1:0] Data_out;
reg[stack_width-1:0] stack[stack_height-1:0];
assign stack_full=(ptr_gap==stack_height);
assign stack_almost_full=(ptr_gap==AF_level);
assign stack_half_full=(ptr_gap==HF_level);
assign stack_almost_empty=(ptr_gap==AE_level);
assign stack_empty=(ptr_gap==0);
always @(posedge clk or posedge rst)
if(rst)
begin
Data_out<=0;
read_ptr<=0;
write_ptr<=0;
ptr_gap<=0;
end
else
if(write_to_stack &&(!stack_full)&&(!read_from_stack))
begin
stack[write_ptr]<=Data_in;
write_ptr<=write_ptr+1;
ptr_gap<=ptr_gap+1;
end
else if((!write_to_stack)&&(!stack_empty)&&read_from_stack)
begin
Data_out<=stack[read_ptr];
read_ptr<=read_ptr+1;
ptr_gap<=ptr_gap-1;
end
else if(write_to_stack &&read_from_stack&&stack_empty)
begin
stack[write_ptr]<=Data_in;
write_ptr<=write_ptr+1;
ptr_gap<=ptr_gap+1;
end
else if(write_to_stack &&read_from_stack&&stack_full)
begin
Data_out<=stack[read_ptr];
read_ptr<=read_ptr+1;
ptr_gap<=ptr_gap-1;
end
else if(write_to_stack&&read_from_stack&&(!stack_full)&&(!stack_empty))
begin
Data_out<=stack[read_ptr];
stack[write_ptr]<=Data_in;
read_ptr<=read_ptr+1;
write_ptr<=write_ptr+1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module icache
#(parameter AWIDTH=14,
parameter CWIDTH=6)
(input wb_clk_i,
input wb_rst_i,
input [AWIDTH-1:0] iwb_adr_i,
input iwb_stb_i,
output [31:0] iwb_dat_o,
output iwb_ack_o,
input [31:0] iram_dat_i,
output [AWIDTH-1:0] iram_adr_o,
output iram_en_o,
input flush);
localparam TAGWIDTH = AWIDTH-CWIDTH-2;
reg stb_d1, ack_d1, miss_d1;
reg [AWIDTH-1:0] held_addr;
reg [31:0] idata [0:(1<<CWIDTH)-1];
reg [TAGWIDTH-1:0] itags [0:(1<<CWIDTH)-1];
reg ivalid [0:(1<<CWIDTH)-1];
wire [CWIDTH-1:0] rd_line, wr_line;
wire [TAGWIDTH-1:0] wr_tags;
wire store_in_cache;
// /////////////////////////////////////
// Write into cache
integer i;
always @(posedge wb_clk_i)
if(wb_rst_i | flush)
for(i=0;i<(1<<CWIDTH);i=i+1)
ivalid[i] <= 0;
else
if(store_in_cache)
ivalid[wr_line] <= 1'b1;
always @(posedge wb_clk_i)
if(store_in_cache)
begin
idata[wr_line] <= iram_dat_i;
itags[wr_line] <= wr_tags;
end
// //////////////////////////////////////
// Read from Cache
wire [TAGWIDTH-1:0] tag_out = itags[rd_line];
wire valid_out = ivalid[rd_line];
wire [31:0] data_out = idata[rd_line];
wire cache_hit = valid_out & (tag_out == iwb_adr_i[AWIDTH-1:CWIDTH+2]);
wire cache_miss = ~cache_hit;
// //////////////////////////////////////
// Handle 1-cycle delay of Block-RAM
always @(posedge wb_clk_i)
if(wb_rst_i)
stb_d1 <= 0;
else
stb_d1 <= iwb_stb_i;
always @(posedge wb_clk_i)
if(wb_rst_i)
held_addr <= 0;
else
held_addr <= iwb_adr_i;
always @(posedge wb_clk_i)
if(wb_rst_i)
ack_d1 <= 1'b0;
else
ack_d1 <= iwb_ack_o;
always @(posedge wb_clk_i)
if(wb_rst_i)
miss_d1 <= 0;
else
miss_d1 <= cache_miss;
//`define IC_NOCACHE
//`define IC_BASIC
//`define IC_FORWARDING_DP
`define IC_FORWARDING_SP
//`define IC_PREFETCH
`ifdef IC_NOCACHE
assign iwb_dat_o = iram_dat_i;
assign iwb_ack_o = iwb_stb_i & (stb_d1 & ~ack_d1);
assign iram_adr_o = iwb_adr_i;
assign iram_en_o = 1'b1;
assign rd_line = 0;
assign wr_line = 0;
assign wr_tags = 0;
assign store_in_cache = 0;
`endif
`ifdef IC_BASIC // Very basic, no forwarding, 2 wait states on miss
assign iwb_dat_o = data_out;
assign iwb_ack_o = iwb_stb_i & cache_hit;
assign iram_adr_o = iwb_adr_i;
assign iram_en_o = 1'b1;
assign rd_line = iwb_adr_i[CWIDTH+1:2];
assign wr_line = rd_line;
assign wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
assign store_in_cache = stb_d1 & miss_d1;
`endif
`ifdef IC_FORWARDING_DP // Simple forwarding, 1 wait state on miss, dual-port ram
assign iwb_dat_o = cache_hit ? data_out : iram_dat_i;
assign iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
assign iram_adr_o = iwb_adr_i;
assign iram_en_o = 1'b1;
assign rd_line = iwb_adr_i[CWIDTH+1:2];
assign wr_line = held_addr[CWIDTH+1:2];
assign wr_tags = held_addr[AWIDTH-1:CWIDTH+2];
assign store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
`endif
`ifdef IC_FORWARDING_SP // Simple forwarding, 1 wait state on miss, single-port ram
assign iwb_dat_o = cache_hit ? data_out : iram_dat_i;
assign iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
assign iram_adr_o = iwb_adr_i;
assign iram_en_o = 1'b1;
assign rd_line = iwb_adr_i[CWIDTH+1:2];
assign wr_line = rd_line;
assign wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
assign store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
`endif
`ifdef IC_PREFETCH // Forwarding plus prefetch
`endif
endmodule // icache
|
/*...................................................................* *............___..................___.....____...______......___....* *.../|....../... ........./|...../... ...|.............|..../... ...* *../.|...../..... ......./.|....|.....|..|.............|.../........* *....|....|.......|...../..|....|.....|..|............/...|.........* *....|....|.......|..../...|..... ___/...|___......../....|..___....* *....|....|.......|.../....|...../... ....... ....../.....|./... ...* *....|....|.......|../_____|__..|.....|.......|..../......|/..... ..* *....|..... ...../.........|....|.....|.......|.../........ ...../..* *..__|__.... ___/..........|..... ___/... ___/.../.......... ___/...* *...................................................................* */ #include <bits/stdc++.h> using namespace std; #define int long long #define INF 1000000000000000000 const int M = 200005; const int MOD = 1000000007; int dp[10][M]; int recur(int d,int m) { if(m==0) { dp[d][m]=1; return 1; } if(dp[d][m]!=-1) { return dp[d][m]; } if(d==9) { dp[d][m]=(recur(0,m-1)+recur(1,m-1))%MOD; } else { dp[d][m]=recur(d+1,m-1); } return dp[d][m]; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); memset(dp,-1,sizeof(dp)); for(int i=0;i<10;i++) { for(int j=0;j<M;j++) { if(dp[i][j]==-1) recur(i,j); } } int tt=1; cin >> tt; while(tt--) { int n,m; cin >> n >> m; int ans=0; while(n>0) { int d=n%10; ans=(ans+dp[d][m])%MOD; n=n/10; } cout << ans << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:10:31 10/14/2014
// Design Name:
// Module Name: Vram_B
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Vram_B(
//cpu_read_write
//wb_input
dat_i,
adr_i,
we_i,
stb_i,
//wb_output
dat_o,
ack_o,
//vga_read
vga_addr,
vga_dout,
clk
//W_En,
//Addr,
//D_In,
//D_Out
);
//cpu_read_write
input wire [31:0] dat_i;
input wire [31:0] adr_i;
input wire we_i;
input wire stb_i;
output reg [31:0] dat_o = 0;
output ack_o;
//vga_read
input wire [10:0] vga_addr;
output wire [31:0] vga_dout;
input clk;
reg [10:0] addra;
wire wea;
reg [31:0] dina;
wire [31:0] douta;
wire [10:0] vram_addr;
assign vram_addr = adr_i[14:2];
//input W_En;
//input [10: 0] Addr; // eleven bits for 1200
//input [31: 0] D_In;
//output reg [31: 0] D_Out;
//(* bram_map="yes" *)
//reg [31: 0] Vram_B[1199: 0];
/*
initial begin
$readmemb("Whatever to make it cool~",Vram_B);
end
*/
assign ack_o = stb_i & (vga_addr != vram_addr); // for two port read and write
//wire vram_wr;
//assign vram_wr = stb_i & ack_o;
assign wea = stb_i & ack_o & we_i;
// always @(posedge vram_wr) begin
// if(we_i) begin //write
// dina <= dat_i;
// end
// else begin //read
// dat_o <= douta;
// end
// end
always @(posedge clk) begin
if(stb_i && ack_o) begin
if(we_i) begin //write
dina <= dat_i;
end
else begin //read
dat_o <= douta;
end
end
end
//always @(posedge clk ) begin
// if ( W_En ) begin
// Vram_B[Addr] <= D_In;
// end
// else D_Out <= Vram_B[Addr];
//end
Vram_2 vram_2p(
//for cpu
.clka(clk), // input clka
.wea(wea), // input [0 : 0] wea
.addra(vram_addr), // input [10 : 0] addra
.dina(dina), // input [10 : 0] dina
.douta(douta), // output [10 : 0] douta
//for vga
.clkb(clk), // input clkb
.web(0), // input [0 : 0] web
.addrb(vga_addr), // input [10 : 0] addrb
.dinb(0), // input [10 : 0] dinb
.doutb(vga_dout) // output [10 : 0] doutb
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:49:22 12/17/2012
// Design Name:
// Module Name: getID_4digits
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module getID_4digits(
input enable,
input [44:0] digits45,
output reg [15:0] iddecimal4
);
integer ID;
integer temp0, temp1;
always @(posedge enable) begin
ID = digits45[16:1];
//ID = 'b0001000010100000;
if(ID>=9000) iddecimal4[15:12] = 9;
else if(ID>=8000) iddecimal4[15:12] = 8;
else if(ID>=7000) iddecimal4[15:12] = 7;
else if(ID>=6000) iddecimal4[15:12] = 6;
else if(ID>=5000) iddecimal4[15:12] = 5;
else if(ID>=4000) iddecimal4[15:12] = 4;
else if(ID>=3000) iddecimal4[15:12] = 3;
else if(ID>=2000) iddecimal4[15:12] = 2;
else if(ID>=1000) iddecimal4[15:12] = 1;
else iddecimal4[15:12] = 0;
temp0 = ID-(iddecimal4[15:12]*1000);
if(temp0>=900) iddecimal4[11:8] = 9;
else if(temp0>=800) iddecimal4[11:8] = 8;
else if(temp0>=700) iddecimal4[11:8] = 7;
else if(temp0>=600) iddecimal4[11:8] = 6;
else if(temp0>=500) iddecimal4[11:8] = 5;
else if(temp0>=400) iddecimal4[11:8] = 4;
else if(temp0>=300) iddecimal4[11:8] = 3;
else if(temp0>=200) iddecimal4[11:8] = 2;
else if(temp0>=100) iddecimal4[11:8] = 1;
else iddecimal4[11:8] = 0;
temp1 = temp0-(iddecimal4[11:8]*100);
if(temp1>=90) iddecimal4[7:4] = 9;
else if(temp1>=80) iddecimal4[7:4] = 8;
else if(temp1>=70) iddecimal4[7:4] = 7;
else if(temp1>=60) iddecimal4[7:4] = 6;
else if(temp1>=50) iddecimal4[7:4] = 5;
else if(temp1>=40) iddecimal4[7:4] = 4;
else if(temp1>=30) iddecimal4[7:4] = 3;
else if(temp1>=20) iddecimal4[7:4] = 2;
else if(temp1>=10) iddecimal4[7:4] = 1;
else iddecimal4[7:4] = 0;
iddecimal4[3:0] = temp1-(iddecimal4[7:4]*10);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long T, n, a[300010], c[300010], l[300010], r[300010]; long long lowbit(long long x) { return x & (-x); } void add(long long x, long long k) { for (long long i = x; i <= n; i += lowbit(i)) c[i] += k; } long long query(long long x) { long long sum = 0; for (long long i = x; i >= 1; i -= lowbit(i)) sum += c[i]; return sum; } signed main() { memset(l, 0, sizeof(l)); memset(r, 0, sizeof(r)); scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &a[i]); memset(c, 0, sizeof(c)); for (long long i = 1; i <= n; i++) { if (2 * a[i] - 1 <= n) l[i] = query(2 * a[i] - 1); else l[i] = query(n) - query(2 * a[i] - n - 1); add(a[i], a[i]); } memset(c, 0, sizeof(c)); for (long long i = n; i >= 1; i--) { if (2 * a[i] - 1 <= n) r[i] = query(2 * a[i] - 1); else r[i] = query(n) - query(2 * a[i] - n - 1); add(a[i], a[i]); } long long f = 0; for (long long i = 1; i <= n; i++) if (l[i] % (2 * a[i]) && r[i] % (2 * a[i])) { printf( YES n ); f = 1; break; } if (!f) printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(void) { int count; int n; int rub; int a[100000]; int b[100000]; int a_1234[4] = {0, 0, 0, 0}; int sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> rub; a_1234[rub - 1]++; } sum = a_1234[3] + a_1234[2]; a_1234[0] -= a_1234[2]; if (a_1234[0] < 0) a_1234[0] = 0; sum += a_1234[1] / 2; a_1234[1] = a_1234[1] % 2; sum += (a_1234[1] * 2 + a_1234[0]) / 4; if ((a_1234[1] * 2 + a_1234[0]) % 4 != 0) sum++; cout << sum; getchar(); getchar(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; long long int inf = 1e9 + 7; void solve() { long long int n; cin >> n; if (n <= 2) { cout << -1 << endl; } else { long long int i; for (i = n; i >= 1; i--) { cout << i << ; } cout << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; while (t--) { solve(); } }
|
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