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#include <bits/stdc++.h> using namespace std; const int MAX = 50050; vector<int> e[MAX]; vector<int> ee[MAX]; int c[MAX][555]; int vis[MAX]; int n, k; void solve(int indx) { c[indx][0] = 1; vis[indx] = 1; for (int i = 0; i < e[indx].size(); i++) { if (vis[e[indx][i]] == 1) continue; int cindx = e[indx][i]; ee[indx].push_back(cindx); solve(cindx); for (int j = 0; j <= k; j++) { if (c[cindx][j] == 0) break; c[indx][j + 1] += c[cindx][j]; } } } long long solve1() { long long ans = 0; for (int i = 1; i <= n; i++) { long long ret = 0; for (int j = 0; j < ee[i].size(); j++) { for (int K = 1; K < k; K++) { long long first = 0, second = 0; first = c[ee[i][j]][K - 1]; second = c[i][k - K] - c[ee[i][j]][k - K - 1]; ret += (first * second); } } ans += ret / 2; ans += c[i][k]; } return ans; } int main() { cin >> n >> k; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; e[x].push_back(y); e[y].push_back(x); } solve(1); cout << solve1() << endl; }
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/*
* ram_w.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1 ps / 1 ps
module ram_w(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_w_address,
input ram_w_waitrequest,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_w_byteenable,
output wire ram_w_write,
output wire[DATA_WIDTH-1:0] ram_w_writedata,
output wire[BURST_WIDTH_W-1:0] ram_w_burstcount,
input [DATA_WIDTH-1:0] data_fifo_out,
input data_valid_fifo_out,
input start_fifo_out,
input [ADD_WIDTH-1:0] address_fifo_out,
input [DATA_WIDTH-1:0] n_burst_fifo_out,
output wire bussy_fifo_out,
output wire full_fifo_out,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter MAX_BURST_COUNT_W = 32;
parameter BURST_WIDTH_W = 5;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
reg write;
wire set_write;
wire reset_write;
wire write_complete;
reg [BURST_WIDTH_W:0] burst_write_n;
wire write_burst_end;
reg [DATA_WIDTH-1:0] out_n;
reg [ADD_WIDTH-1:0] write_address;
wire fifo_full;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_out),
.clock(clk),
.data(data_fifo_out),
.wrreq(data_valid_fifo_out),
.q(ram_w_writedata),
.rdreq(write_complete),
.full(fifo_full),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "ON";
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
write <= 0;
end else begin
if (reset_write == 1) begin
write <= 0;
end else begin
if (set_write == 1) begin
write <= 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
out_n <= 0;
end else begin
if (start_fifo_out == 1) begin
out_n <= n_burst_fifo_out * MAX_BURST_COUNT_W;
end else begin
if (write_complete == 1) begin
out_n <= out_n - 1;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_out == 1) begin
burst_write_n <= MAX_BURST_COUNT_W;
end
else begin
if (write_burst_end == 1) begin
burst_write_n <= MAX_BURST_COUNT_W;
end else begin
if (write_complete == 1) begin
burst_write_n <= burst_write_n - 1;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_out == 1) begin
write_address <= address_fifo_out;
end else begin
if (write_burst_end == 1) begin
write_address <= write_address + MAX_BURST_COUNT_W * BYTE_ENABLE_WIDTH;
end
end
end
assign write_complete = (write == 1) & (ram_w_waitrequest == 0);
assign write_burst_end = (burst_write_n == 1) & (write_complete == 1);
assign fifo_used[FIFO_DEPTH_LOG2] = fifo_full;
assign set_write = (out_n != 0) & (fifo_used >= MAX_BURST_COUNT_W);
assign reset_write = ((fifo_used <= MAX_BURST_COUNT_W) | (out_n == 1)) & (write_burst_end == 1);
assign ram_w_address = write_address;
assign ram_w_write = write;
assign ram_w_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_w_burstcount = MAX_BURST_COUNT_W;
assign bussy_fifo_out = out_n != 0;
assign full_fifo_out = fifo_full;
assign usedw_fifo_out = fifo_used;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 20; int n; int part[N][2]; bool vis[N]; vector<int> ans; vector<pair<int, int> > G[N]; void dfs(int u) { vis[u] = true; for (auto v : G[u]) if (!vis[v.first]) dfs(v.first); } bool check(int Mask) { for (int i = 0; i <= Mask; ++i) G[i].clear(), vis[i] = false; for (int i = 1; i <= n; ++i) { int u = part[i][0] & Mask; int v = part[i][1] & Mask; G[u].push_back({v, 2 * i - 1}); G[v].push_back({u, 2 * i - 2}); } int comps = 0; for (int i = 0; i <= Mask; ++i) { if (G[i].size() & 1) return false; if (!vis[i] && G[i].size() > 0) { ++comps; dfs(i); } } return comps == 1; } void go(int u, int prv = -1) { while (G[u].size()) { auto e = G[u].back(); G[u].pop_back(); if (vis[e.second / 2]) continue; vis[e.second / 2] = true; go(e.first, e.second); } if (prv != -1) { ans.push_back(prv); ans.push_back(prv ^ 1); } } void restore(int Mask) { for (int i = 0; i <= n; ++i) vis[i] = false; for (int i = 0; i <= Mask; ++i) if (G[i].size()) { go(i); break; } for (int i = 0; i < n + n; ++i) printf( %d%c , ans[i] + 1, n [i + 1 == n + n]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d %d , &part[i][0], &part[i][1]); for (int i = 20; i >= 0; --i) if (check((1 << i) - 1)) { printf( %d n , i); restore((1 << i) - 1); exit(0); } assert(false); return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 5e3 + 10; int dp[maxn][maxn]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; string a, b; cin >> a >> b; int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i - 1] == b[j - 1]) { dp[i][j] = dp[i - 1][j - 1] + 2; } else dp[i][j] = max({0, dp[i - 1][j] - 1, dp[i][j - 1] - 1}); ans = max(ans, dp[i][j]); } } cout << ans << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_V
|
#include <bits/stdc++.h> int main() { int n, k, i; scanf( %d , &n); int a[n][2]; for (i = 0; i < n; i++) { scanf( %d%d , &a[i][0], &a[i][1]); } scanf( %d , &k); for (i = 0; i < n; i++) { if (k >= a[i][0] && k <= a[i][1]) { printf( %d , n - i); break; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n / 2 * 2 + (n + 1) / 2 << endl; for (int i = 2; i <= n; i += 2) cout << i << ; for (int i = 1; i <= n; i += 2) cout << i << ; for (int i = 2; i <= n; i += 2) cout << i << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; const long long MOD = 1e9 + 7; set<char> seen; void solve() { int n; cin >> n; string a; string b; cin >> a >> b; for (int i = 0; i < n; i++) { if (a[i] > b[i]) { cout << -1 n ; return; } } int ans = 0; for (char c = a ; c <= t ; c++) { char smallest = z ; for (int i = 0; i < n; i++) { if (a[i] == c) { if (a[i] != b[i]) smallest = min(smallest, b[i]); } } if (smallest != z ) { ans++; for (int i = 0; i < n; i++) { if (a[i] == c) { if (a[i] != b[i]) { a[i] = smallest; } } } } } cout << ans << n ; } int main() { cin.sync_with_stdio(0); cin.tie(0); int TC; cin >> TC; while (TC--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:36777216 ) template <class T> inline T &RD(T &); template <class T> inline void OT(const T &); inline int RD() { int x; return RD(x); } inline double &RF(double &); inline double RF() { double x; return RF(x); } inline char *RS(char *s); inline char &RC(char &c); inline char RC(); inline char &RC(char &c) { scanf( %c , &c); return c; } inline char RC() { char c; return RC(c); } template <class T> inline T &RDD(T &x) { char c; for (c = getchar(); c < - ; c = getchar()) ; if (c == - ) { x = 0 - getchar(); for (c = getchar(); 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + 0 - c; } else { x = c - 0 ; for (c = getchar(); 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; } return x; } inline int RDD() { int x; return RDD(x); } template <class T0, class T1> inline T0 &RD(T0 &x0, T1 &x1) { RD(x0), RD(x1); return x0; } template <class T0, class T1, class T2> inline T0 &RD(T0 &x0, T1 &x1, T2 &x2) { RD(x0), RD(x1), RD(x2); return x0; } template <class T0, class T1, class T2, class T3> inline T0 &RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3) { RD(x0), RD(x1), RD(x2), RD(x3); return x0; } template <class T0, class T1, class T2, class T3, class T4> inline T0 &RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4); return x0; } template <class T0, class T1, class T2, class T3, class T4, class T5> inline T0 &RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5); return x0; } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline T0 &RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5, T6 &x6) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5), RD(x6); return x0; } template <class T0, class T1> inline void OT(const T0 &x0, const T1 &x1) { OT(x0), OT(x1); } template <class T0, class T1, class T2> inline void OT(const T0 &x0, const T1 &x1, const T2 &x2) { OT(x0), OT(x1), OT(x2); } template <class T0, class T1, class T2, class T3> inline void OT(const T0 &x0, const T1 &x1, const T2 &x2, const T3 &x3) { OT(x0), OT(x1), OT(x2), OT(x3); } template <class T0, class T1, class T2, class T3, class T4> inline void OT(const T0 &x0, const T1 &x1, const T2 &x2, const T3 &x3, const T4 &x4) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void OT(const T0 &x0, const T1 &x1, const T2 &x2, const T3 &x3, const T4 &x4, const T5 &x5) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void OT(const T0 &x0, const T1 &x1, const T2 &x2, const T3 &x3, const T4 &x4, const T5 &x5, const T6 &x6) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5), OT(x6); } inline char &RC(char &a, char &b) { RC(a), RC(b); return a; } inline char &RC(char &a, char &b, char &c) { RC(a), RC(b), RC(c); return a; } inline char &RC(char &a, char &b, char &c, char &d) { RC(a), RC(b), RC(c), RC(d); return a; } inline char &RC(char &a, char &b, char &c, char &d, char &e) { RC(a), RC(b), RC(c), RC(d), RC(e); return a; } inline char &RC(char &a, char &b, char &c, char &d, char &e, char &f) { RC(a), RC(b), RC(c), RC(d), RC(e), RC(f); return a; } inline char &RC(char &a, char &b, char &c, char &d, char &e, char &f, char &g) { RC(a), RC(b), RC(c), RC(d), RC(e), RC(f), RC(g); return a; } inline double &RF(double &a, double &b) { RF(a), RF(b); return a; } inline double &RF(double &a, double &b, double &c) { RF(a), RF(b), RF(c); return a; } inline double &RF(double &a, double &b, double &c, double &d) { RF(a), RF(b), RF(c), RF(d); return a; } inline double &RF(double &a, double &b, double &c, double &d, double &e) { RF(a), RF(b), RF(c), RF(d), RF(e); return a; } inline double &RF(double &a, double &b, double &c, double &d, double &e, double &f) { RF(a), RF(b), RF(c), RF(d), RF(e), RF(f); return a; } inline double &RF(double &a, double &b, double &c, double &d, double &e, double &f, double &g) { RF(a), RF(b), RF(c), RF(d), RF(e), RF(f), RF(g); return a; } inline void RS(char *s1, char *s2) { RS(s1), RS(s2); } inline void RS(char *s1, char *s2, char *s3) { RS(s1), RS(s2), RS(s3); } template <class T0, class T1> inline void RDD(const T0 &a, const T1 &b) { RDD(a), RDD(b); } template <class T0, class T1, class T2> inline void RDD(const T0 &a, const T1 &b, const T2 &c) { RDD(a), RDD(b), RDD(c); } template <class T> inline void RST(T &A) { memset(A, 0, sizeof(A)); } template <class T> inline void FLC(T &A, int x) { memset(A, x, sizeof(A)); } template <class T> inline void CLR(T &A) { A.clear(); } template <class T0, class T1> inline void RST(T0 &A0, T1 &A1) { RST(A0), RST(A1); } template <class T0, class T1, class T2> inline void RST(T0 &A0, T1 &A1, T2 &A2) { RST(A0), RST(A1), RST(A2); } template <class T0, class T1, class T2, class T3> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { RST(A0), RST(A1), RST(A2), RST(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5), RST(A6); } template <class T0, class T1> inline void FLC(T0 &A0, T1 &A1, int x) { FLC(A0, x), FLC(A1, x); } template <class T0, class T1, class T2> inline void FLC(T0 &A0, T1 &A1, T2 &A2, int x) { FLC(A0, x), FLC(A1, x), FLC(A2, x); } template <class T0, class T1, class T2, class T3> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, int x) { FLC(A0, x), FLC(A1, x), FLC(A2, x), FLC(A3, x); } template <class T0, class T1, class T2, class T3, class T4> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, int x) { FLC(A0, x), FLC(A1, x), FLC(A2, x), FLC(A3, x), FLC(A4, x); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, int x) { FLC(A0, x), FLC(A1, x), FLC(A2, x), FLC(A3, x), FLC(A4, x), FLC(A5, x); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6, int x) { FLC(A0, x), FLC(A1, x), FLC(A2, x), FLC(A3, x), FLC(A4, x), FLC(A5, x), FLC(A6, x); } template <class T> inline void CLR(priority_queue<T, vector<T>, less<T> > &Q) { while (!Q.empty()) Q.pop(); } template <class T> inline void CLR(priority_queue<T, vector<T>, greater<T> > &Q) { while (!Q.empty()) Q.pop(); } template <class T0, class T1> inline void CLR(T0 &A0, T1 &A1) { CLR(A0), CLR(A1); } template <class T0, class T1, class T2> inline void CLR(T0 &A0, T1 &A1, T2 &A2) { CLR(A0), CLR(A1), CLR(A2); } template <class T0, class T1, class T2, class T3> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { CLR(A0), CLR(A1), CLR(A2), CLR(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5), CLR(A6); } template <class T> inline void CLR(T &A, int n) { for (int i = 0; i < int(n); ++i) CLR(A[i]); } template <class T> inline T &SRT(T &A) { sort(A.begin(), A.end()); return A; } template <class T, class C> inline T &SRT(T &A, C B) { sort(A.begin(), A.end(), B); return A; } template <class T> inline T &UNQ(T &A) { A.resize(unique(SRT(A).begin(), SRT(A).end()) - A.begin()); return A; } const int dx4[] = {-1, 0, 1, 0}; const int dy4[] = {0, 1, 0, -1}; const int dx8[] = {-1, 0, 1, 0, -1, -1, 1, 1}; const int dy8[] = {0, 1, 0, -1, -1, 1, -1, 1}; const int dxhorse[] = {-2, -2, -1, -1, 1, 1, 2, 2}; const int dyhorse[] = {1, -1, 2, -2, 2, -2, 1, -1}; const int MOD = 1000000007; const int INF = 0x3f3f3f3f; const double EPS = 1e-9; const double OO = 1e15; const double PI = acos(-1.0); template <class T> inline void checkMin(T &a, const T b) { if (b < a) a = b; } template <class T> inline void checkMax(T &a, const T b) { if (a < b) a = b; } template <class T> inline void checkMin(T &a, T &b, const T x) { checkMin(a, x), checkMin(b, x); } template <class T> inline void checkMax(T &a, T &b, const T x) { checkMax(a, x), checkMax(b, x); } template <class T, class C> inline void checkMin(T &a, const T b, C c) { if (c(b, a)) a = b; } template <class T, class C> inline void checkMax(T &a, const T b, C c) { if (c(a, b)) a = b; } template <class T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline T min(T a, T b, T c, T d) { return min(min(a, b), min(c, d)); } template <class T> inline T max(T a, T b, T c, T d) { return max(max(a, b), max(c, d)); } template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T cub(T a) { return a * a * a; } inline int ceil(int x, int y) { return (x - 1) / y + 1; } inline int sgn(double x) { return x < -EPS ? -1 : x > EPS; } inline int sgn(double x, double y) { return sgn(x - y); } template <class T> inline T &RD(T &x) { char c; for (c = getchar(); c < 0 ; c = getchar()) ; x = c - 0 ; for (c = getchar(); 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; return x; } inline double &RF(double &x) { scanf( %lf , &x); return x; } inline char *RS(char *s) { scanf( %s , s); return s; } int Case; template <class T> inline void OT(const T &x) { cout << x << endl; } const int N = 309; int a[N][N]; int t, tt; int tp, tu, td; int n, m; int U[N][N], D[N][N], L[N][N], R[N][N]; struct ANS { int T; int lx, ly, rx, ry; } ans; void upd(int lx, int rx, int ly, int ry, int T) { if (ans.T == -1 || abs(T - t) < abs(ans.T - t)) { ans.T = T; ans.lx = lx; ans.ly = ly; ans.rx = rx; ans.ry = ry; } } set<pair<int, int> > hh; int f(int pre, int now) { if (pre < now) return tu; if (pre > now) return td; return tp; } int main() { RD(n, m); RD(t, tp, tu, td); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) RD(a[i][j]); RST(U, D, L, R); ans.T = -1; for (int i = 1; i <= n; ++i) { for (int j = 2; j <= m; ++j) { L[i][j] = L[i][j - 1]; if (a[i][j] > a[i][j - 1]) L[i][j] += tu; else if (a[i][j] == a[i][j - 1]) L[i][j] += tp; else L[i][j] += td; } } for (int i = 2; i <= n; ++i) { for (int j = 1; j <= m; ++j) { U[i][j] = U[i - 1][j]; if (a[i][j] < a[i - 1][j]) U[i][j] += tu; else if (a[i][j] == a[i - 1][j]) U[i][j] += tp; else U[i][j] += td; } } for (int i = n - 1; i >= 1; --i) { for (int j = 1; j <= m; ++j) { D[i][j] = D[i + 1][j]; if (a[i][j] < a[i + 1][j]) D[i][j] += tu; else if (a[i][j] == a[i + 1][j]) D[i][j] += tp; else D[i][j] += td; } } for (int i = 1; i <= n; ++i) { for (int j = m - 1; j >= 1; --j) { R[i][j] = R[i][j + 1]; if (a[i][j] > a[i][j + 1]) R[i][j] += tu; else if (a[i][j] == a[i][j + 1]) R[i][j] += tp; else R[i][j] += td; } } for (int lx = 1; lx <= n; ++lx) for (int rx = lx + 3 - 1; rx <= n; ++rx) { hh.clear(); int head = 1; int tot = 0, now; for (int ry = 1; ry <= m; ++ry) { if (ry != 1) { tot += f(a[lx][ry - 1], a[lx][ry]); tot += f(a[rx][ry], a[rx][ry - 1]); } now = tot + D[lx][ry] - D[rx][ry]; if (!hh.empty()) { static set<pair<int, int> >::iterator iter, liter, riter; iter = hh.lower_bound(make_pair(t - now, 0)); liter = iter, riter = iter; if (liter != hh.begin()) liter--; if (riter != hh.end()) riter++; if (iter != hh.end()) { pair<int, int> me = *iter; upd(lx, rx, me.second, ry, now + me.first); } if (liter != hh.end()) { pair<int, int> me = *liter; upd(lx, rx, me.second, ry, now + me.first); } if (riter != hh.end()) { pair<int, int> me = *riter; upd(lx, rx, me.second, ry, now + me.first); } } while (ry + 1 - head + 1 >= 3) { pair<int, int> me; me.first = 0; me.second = head; me.first += U[rx][head] - U[lx][head]; me.first -= L[lx][head]; me.first -= R[rx][1] - R[rx][head]; hh.insert(me); ++head; } } } cout << ans.lx << << ans.ly << << ans.rx << << ans.ry << endl; }
|
#include <bits/stdc++.h> using namespace std; constexpr int MOD = 998244353; int main() { int R, C; cin >> R >> C; int X = 1; while (R--) X = (2 * X) % MOD; while (C--) X = (2 * X) % MOD; cout << X << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_1_V
`define SKY130_FD_SC_LS__A222O_1_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222o_1 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_1_V
|
`default_nettype none
`timescale 1ns/1ns
module tb_memif();
wire clk, reset;
clock clock(clk, reset);
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [1:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
wire [17:0] b_address;
wire b_write;
wire b_read;
wire [35:0] b_writedata;
wire [35:0] b_readdata;
wire b_waitrequest;
memif memif0(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.m_address(b_address),
.m_write(b_write),
.m_read(b_read),
.m_writedata(b_writedata),
.m_readdata(b_readdata),
.m_waitrequest(b_waitrequest));
dlymemory memory(
.i_clk(clk),
.i_reset_n(reset),
.i_address(b_address),
.i_write(b_write),
.i_read(b_read),
.i_writedata(b_writedata),
.o_readdata(b_readdata),
.o_waitrequest(b_waitrequest));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
memory.mem[4] = 123;
memory.mem[5] = 321;
memory.mem['o123] = 36'o112233445566;
#5;
#200;
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o123;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read)
a_read <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long r; cin >> r; if ((r - 1) % 2 == 0 && r > 3) cout << 1 << << (r - 3) / 2; else cout << NO ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_TB_V
`define SKY130_FD_SC_HDLL__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { solve(); } return 0; } void solve() { string s, t; cin >> s >> t; long long a[10]; memset(a, 0, sizeof(a)); if (s.length() == 1 && s[0] == 0 ) { if (t == s) { cout << OK ; return; } else { cout << WRONG_ANSWER ; return; } } for (long long i = 0; i < s.length(); i++) { a[s[i] - 0 ]++; } string ans; if (a[0] == 0) { ans = s; sort(ans.begin(), ans.end()); if (ans == t) { cout << OK ; return; } else { cout << WRONG_ANSWER ; return; } } else { long long index; for (long long i = 1; i < 10; i++) { if (a[i] != 0) { index = i; break; } } a[index]--; for (long long i = 0; i < 10; i++) { if (a[i] != 0) { while (a[i]--) { char temp = 0 + i; ans += string(1, temp); } } } sort(ans.begin(), ans.end()); char t2 = 0 + index; string rtans = string(1, t2); rtans += ans; if (rtans == t) { cout << OK ; return; } else { cout << WRONG_ANSWER ; return; } } return; }
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#include <bits/stdc++.h> using namespace std; const int INFint = 2e9; const long long INF = 1e18; const long long MOD = 1000000007ll; int g[100][100]; vector<int> used; set<int> roots; int n, m; void dfs(int v, int p) { used[v] = 1; for (int i = 0; i < n; i++) { if (i == p || !g[v][i]) continue; if (used[i] || roots.count(i)) { cout << NO ; exit(0); } dfs(i, v); } used[v] = 1; } vector<int> anc; void addCycle(int st, int en) { int v = en; while (v != st) { roots.insert(v); v = anc[v]; } roots.insert(st); } bool cycle(int v, int p = -1) { used[v] = 1; for (int i = 0; i < n; i++) { if (i == p || !g[v][i]) continue; if (used[i]) { addCycle(i, v); return 1; } anc[i] = v; if (cycle(i, v)) return 1; } used[v] = 1; return 0; } vector<int> p; int get(int v) { return p[v] == v ? v : p[v] = get(p[v]); } void unite(int a, int b) { a = get(a); b = get(b); if (a == b) return; if (rand() & 1) swap(a, b); p[a] = b; } int main() { ios_base::sync_with_stdio(0); cin >> n >> m; used.resize(n); p.resize(n); for (int i = 0; i < n; i++) p[i] = i; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; unite(a, b); g[a][b] = g[b][a] = 1; } int cnt = 0; for (int i = 0; i < n; i++) if (p[i] == i) cnt++; if (cnt != 1) { cout << NO ; return 0; } anc.resize(n); for (int i = 0; i < n; i++) { if (!used[i]) { if (cycle(i)) break; } } if (roots.size() < 3) { cout << NO ; return 0; } used.assign(n, 0); for (auto v : roots) { for (int i = 0; i < n; i++) { if (g[v][i] && !roots.count(i)) { dfs(i, v); } } } cout << FHTAGN! ; fprintf(stderr, nTIME = %lf n , 1.0 * clock() / CLOCKS_PER_SEC); ; return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:300000000 ) #pragma warning(disable : 4800) using namespace std; const double pi = 3.1415926535897932384626433832795; template <class T> T abs(const T &a) { return a >= 0 ? a : -a; }; template <class T> T sqr(const T &x) { return x * x; } int n, m, k; vector<vector<int> > g; vector<bool> visited; vector<int> ans; vector<pair<int, int> > traders; pair<int, int> erased; bool isErased(int x, int y) { return pair<int, int>(x, y) == erased || pair<int, int>(y, x) == erased; } void dfs(int k) { if (visited[k]) return; visited[k] = true; for (int i = 0; i < (int((g[k]).size())); i++) { int to = g[k][i]; if (!isErased(k, to)) dfs(to); } } void work(int x, int y) { erased = pair<int, int>(x, y); visited.assign(n, false); dfs(x); for (int i = 0; i < (k); i++) if (visited[traders[i].first] && !visited[traders[i].second]) ans[i]++; } int main() { cin >> n >> m; g.resize(n); for (int i = 0; i < (m); i++) { int x, y; cin >> x >> y; x--, y--; g[x].push_back(y); g[y].push_back(x); } cin >> k; ans.resize(k); traders.resize(k); for (int i = 0; i < (k); i++) { cin >> traders[i].first >> traders[i].second; traders[i].first--; traders[i].second--; } for (int i = 0; i < (n); i++) for (int j = 0; j < (int((g[i]).size())); j++) work(i, g[i][j]); for (int i = 0; i < (k); i++) cout << ans[i] << endl; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const double EPS = 1e-9; int n, k, deg[1000015], ans, vis[1000015]; vector<int> e[1000015]; int dfs(int u) { if (e[u].size() == 1) return 1; vis[u] = 1; vector<int> d; for (int i = 0; i < e[u].size(); ++i) { int v = e[u][i]; if (vis[v]) continue; int x = dfs(v); if (~x) d.push_back(x); } sort(d.begin(), d.end()); if (0 == d.size()) { return -1; } else if (1 == d.size()) { if (d[0] >= k) { ++ans; return -1; } else { return ~d[0] ? d[0] + 1 : d[0]; } } int i = 0; while (i + 1 < d.size() && d[i] + d[i + 1] <= k) ++i; ans += d.size() - i - 1; return ~d[i] ? d[i] + 1 : d[i]; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); ++deg[u], ++deg[v]; e[u].push_back(v), e[v].push_back(u); } for (int i = 1; i <= n; ++i) { if (1 != deg[i]) { if (~dfs(i)) ++ans; break; } } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % m; a = (a * a) % m; b >>= 1; } return res; } void solve() { long long int x, n, y, z, ans = 1; cin >> x >> n; vector<long long int> v; y = x; for (long long int i = 2; i * i <= x; i++) { if (y % i == 0) { v.push_back(i); while (y % i == 0) y /= i; } } if (y != 1) v.push_back(y); for (long long int i = 0; i < v.size(); i++) { long long int a = v[i], b = 0; while (a <= n) { z = (n / a); b += z; if (z < v[i]) break; a *= v[i]; } ans = (ans * binpow(v[i], b, 1000000007)) % 1000000007; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; int i, j, k, n, l, n1, n2, m, m1, m2; cin >> s; l = s.size(); for (i = l - 1; i >= 0; i--) { n = s[i] - 48; m = n; if (m == 0) { cout << YES << endl << 0 << endl; exit(0); } if (n % 2 == 0) { if (m % 8 == 0) { cout << YES << endl << m << endl; exit(0); } if (i == 0) { break; } for (j = i - 1; j >= 0; j--) { n1 = (s[j] - 48) * 10; m1 = n1 + m; if (m1 % 8 == 0) { cout << YES << endl << m1 << endl; exit(0); } if (j == 0) { break; } for (k = j - 1; k >= 0; k--) { n2 = (s[k] - 48) * 100; m2 = n2 + m1; if (m2 % 8 == 0) { cout << YES << endl << m2 << endl; exit(0); } } } } } cout << NO << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<long long> a(n); vector<int> nx(n); for (int i = 0; i < n; i++) { cin >> a[i]; } map<long long, int> mp; long long sig = 0; for (int i = 0; i < 3 * n; i++) { int ri = (i % n); nx[mp[sig]] = ri; mp[sig] = ri; sig += a[ri]; } int res = n; for (int i = 0; i < n; i++) { int len = 1, p = nx[i]; if (p == -1) { continue; } nx[i] = -1; while (p != i) { len++; int np = nx[p]; nx[p] = -1; p = np; } res = min(n - len, res); } cout << res << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, k; int per; int main() { cin >> n >> m >> k; per = 2; int flag = 0; int sum = 0; int ff = 0; int a = 1; for (int i = 1; i <= n; ++i) { if (!flag) { for (int j = 1; j <= m; ++j) { if (sum % 2 == 0 && a == k) { if (ff++) cout << endl; cout << n * m - 2 * (k - 1); a++; } if (sum % 2 == 0 && a < k) { if (ff++) cout << endl; cout << 2 ; a++; } cout << << i << << j; sum++; } flag = 1; continue; } if (flag) { for (int j = m; j >= 1; --j) { if (sum % 2 == 0 && a == k) { if (ff++) cout << endl; cout << n * m - 2 * (k - 1); a++; } if (sum % 2 == 0 && a < k) { if (ff++) cout << endl; cout << 2 ; a++; } cout << << i << << j; sum++; } flag = 0; continue; } } }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int INF = 1000000001; const long long int LLINF = 1000000000000000001LL; struct ITree { vector<long long int> T; int p = 1; ITree(int n) { while (p < n) p *= 2; T.resize(2 * p - 1, 0); } int par(int x) { return (x - 1) / 2; } void Set(int l, long long int v) { l += p - 1; T[l] = v; while (l > 0) { l = par(l); T[l] = T[2 * l + 1] + T[2 * l + 2]; } } long long int Query(int l, int r) { l += p - 1; r += p - 1; long long int ans = T[l]; if (l < r) ans += T[r]; while (par(l) != par(r)) { if (l % 2 == 1) ans += T[l + 1]; if (r % 2 == 0) ans += T[r - 1]; l = par(l); r = par(r); } return ans; } }; int main() { ios_base::sync_with_stdio(0); int n, k, a, b, q; cin >> n >> k >> a >> b >> q; ITree treeA(n), treeB(n); vector<long long int> A(n, 0); while (q--) { int type; cin >> type; if (type == 1) { int day, add; cin >> day >> add; day--; A[day] += add; treeB.Set(day, min((long long int)b, A[day])); treeA.Set(day, min((long long int)a, A[day])); } else { int l; cin >> l; l--; int r = l + k - 1; long long int ans = 0; if (l > 0) ans += treeB.Query(0, l - 1); if (r < n - 1) ans += treeA.Query(r + 1, n - 1); cout << ans << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; long long maxi; maxi = -9999999999; cin >> n >> k; for (int i = 1; i <= n; i++) { int a, b; long long tmp; cin >> a >> b; if (b > k) { tmp = a - (b - k); } else { tmp = a; } maxi = max(tmp, maxi); } cout << maxi; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, p, q, i = 1, j, k, temp = 0, flag = 0; string s; cin >> n >> p >> q; cin >> s; if (n % p == 0 && n != p + q || n % q == 0 && n != p + q) { if (n % p == 0) { cout << n / p << endl; for (i = 0; i < n; i++) { cout << s[i]; if ((i + 1) % p == 0) cout << endl; } } else { cout << n / q << endl; for (i = 0; i < n; i++) { cout << s[i]; if ((i + 1) % q == 0) cout << endl; } } } else { while (1) { j = n - (p * i); k = n - (q * i); if (j < 0 || k < 0) break; if (j % q == 0) { temp = 1; break; } if (k % p == 0) { flag = 1; break; } if (j < 0 && k < 0) break; i++; } if (temp == 1) { cout << i + (j / q) << endl; for (int x = 0; x < i * p; x++) { cout << s[x]; if ((x + 1) % p == 0) cout << endl; } j = 1; for (int x = i * p; x < n; x++) { cout << s[x]; if ((j) % q == 0) cout << endl; j++; } } else if (flag == 1) { cout << i + (k / p) << endl; for (int x = 0; x < i * q; x++) { cout << s[x]; if ((x + 1) % q == 0) cout << endl; } j = 1; for (int x = i * q; x < n; x++) { cout << s[x]; if ((j) % p == 0) cout << endl; j++; } } else { cout << -1 << endl; } } }
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// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: MULT_sumXsq.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MULT_sumXsq (
dataa,
datab,
result);
input [25:0] dataa;
input [23:0] datab;
output [49:0] result;
wire [49:0] sub_wire0;
wire [49:0] result = sub_wire0[49:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 26,
lpm_mult_component.lpm_widthb = 24,
lpm_mult_component.lpm_widthp = 50;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "26"
// Retrieval info: PRIVATE: WidthB NUMERIC "24"
// Retrieval info: PRIVATE: WidthP NUMERIC "50"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "50"
// Retrieval info: USED_PORT: dataa 0 0 26 0 INPUT NODEFVAL "dataa[25..0]"
// Retrieval info: USED_PORT: datab 0 0 24 0 INPUT NODEFVAL "datab[23..0]"
// Retrieval info: USED_PORT: result 0 0 50 0 OUTPUT NODEFVAL "result[49..0]"
// Retrieval info: CONNECT: @dataa 0 0 26 0 dataa 0 0 26 0
// Retrieval info: CONNECT: @datab 0 0 24 0 datab 0 0 24 0
// Retrieval info: CONNECT: result 0 0 50 0 @result 0 0 50 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_sumXsq_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.1up/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2013/11/05 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// modelling dma_sequencer.v together with dma_access.v
`define CLK_PERIOD 40
//`define NO_CPU
module tb;
parameter DEVNUM = 4;
integer i,j,k;
reg clk,rst_n;
reg can_go;
tri1 iorq_n,mreq_n,rd_n,wr_n;
tri0 busrq_n,busak_n;
trireg [15:0] zaddr;
tri [7:0] zdata;
wire dma_req,dma_rnw;
wire dma_ack,dma_end;
wire dma_busynready;
wire [20:0] dma_addr;
wire [7:0] dma_wd;
wire [7:0] dma_rd;
tri0 [DEVNUM-1:0] req;
tri1 [DEVNUM-1:0] rnw;
wire [DEVNUM-1:0] done;
wire [DEVNUM-1:0] ack;
tri0[20:0] addr[0:DEVNUM-1];
tri0 [7:0] wd[0:DEVNUM-1];
wire [7:0] rd;
wire mem_dma_bus;
wire [15:0] mem_dma_addr;
wire [7:0] mem_dma_wd;
wire [7:0] mem_dma_rd;
wire mem_dma_rnw;
wire mem_dma_oe;
wire mem_dma_we;
initial
begin
clk = 1'b0;
forever #(`CLK_PERIOD/2) clk = ~clk;
end
`ifndef NO_CPU
T80a z80( .RESET_n(rst_n),
.CLK_n(clk),
.WAIT_n(1'b1),
.INT_n(1'b1),
.NMI_n(1'b1),
.MREQ_n(mreq_n),
.IORQ_n(iorq_n),
.RD_n(rd_n),
.WR_n(wr_n),
.BUSRQ_n(busrq_n),
.BUSAK_n(busak_n),
.A(zaddr),
.D(zdata) );
`endif
rom myrom( .addr(zaddr),
.data(zdata),
.ce_n( (zaddr<16'h8000)?(mreq_n|rd_n):1'b1 ) );
assign zaddr = mem_dma_bus ? mem_dma_addr[15:0] : 16'hZZZZ;
assign zdata = (mem_dma_bus&(!mem_dma_rnw)) ? mem_dma_wd : 8'hZZ;
assign mem_dma_rd = zdata;
ram myram( .addr(zaddr),
.data(zdata),
.ce_n( (zaddr>=16'h8000)?1'b0:1'b1 ),
.oe_n( mem_dma_bus ? mem_dma_oe : (mreq_n|rd_n) ),
.we_n( mem_dma_bus ? mem_dma_we : (mreq_n|wr_n) ) );
dma_sequencer myseq( .clk(clk),
.rst_n(rst_n),
.rd (rd),
.addr0(addr[0]),
.wd0 (wd[0]),
.req0 (req[0]),
.rnw0 (rnw[0]),
.ack0 (ack[0]),
.end0 (done[0]),
.addr1(addr[1]),
.wd1 (wd[1]),
.req1 (req[1]),
.rnw1 (rnw[1]),
.ack1 (ack[1]),
.end1 (done[1]),
.addr2(addr[2]),
.wd2 (wd[2]),
.req2 (req[2]),
.rnw2 (rnw[2]),
.ack2 (ack[2]),
.end2 (done[2]),
.addr3(addr[3]),
.wd3 (wd[3]),
.req3 (req[3]),
.rnw3 (rnw[3]),
.ack3 (ack[3]),
.end3 (done[3]),
.dma_req(dma_req),
.dma_rnw(dma_rnw),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_addr(dma_addr),
.dma_wd(dma_wd),
.dma_rd(dma_rd) );
dma_access mydma( .dma_req(dma_req),
.dma_rnw(dma_rnw),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_addr(dma_addr),
.dma_wd(dma_wd),
.dma_rd(dma_rd),
.dma_busynready(dma_busynready),
.mem_dma_rd(zdata),
.mem_dma_wd(mem_dma_wd),
.mem_dma_bus(mem_dma_bus),
.mem_dma_addr(mem_dma_addr),
.mem_dma_rnw(mem_dma_rnw),
.mem_dma_oe(mem_dma_oe),
.mem_dma_we(mem_dma_we),
.clk(clk),
.rst_n(rst_n),
.busrq_n(busrq_n),
.busak_n(busak_n) );
generate
genvar gv;
for(gv=0;gv<DEVNUM;gv=gv+1)
begin : instantiate_testers
dma_tester #( .BEG_ADDR(21'h0A000+21'd4096*gv) ) mytest (
.clk(clk),
.can_go(can_go),
.req(req[gv]),
.rnw(rnw[gv]),
.wd(wd[gv]),
.addr(addr[gv]),
.ack(ack[gv]),
.done(done[gv]),
.rd(rd)
);
end
endgenerate
/*
reg start [0:DEVNUM-1];
reg rnw_in [0:DEVNUM-1];
wire inprogress [0:DEVNUM-1];
generate
genvar gv;
for(gv=0;gv<DEVNUM;gv=gv+1)
begin : dmaers
dmaer g( .clk(clk), .rst_n(rst_n),
.start(start[gv]),
.rnw_in(rnw_in[gv]),
.inprogress(inprogress[gv]),
.req(req[gv]),
.rnw(rnw[gv]),
.ack(ack[gv]),
.done(done[gv]) );
end
endgenerate
*/
initial
begin
rst_n = 1'b0;
can_go = 1'b0;
for(i=0;i<DEVNUM;i=i+1)
begin
//start[i] = 1'b0;
//rnw_in[i] = 1'b1;
//addr[i] = 21'h8001;
//wd[i] = 1+i+(i<<2)+(i<<6);
end
repeat(4) @(posedge clk);
rst_n <= 1'b1;
repeat(10) @(posedge clk);
can_go <= 1'b1;
/* start[1] <= 1'b1;
@(posedge ack[1]);
start[1] <= 1'b0;
@(negedge inprogress[1]);
repeat (5) @(posedge clk);
rnw_in[1] = 1'b0;
rnw_in[1] = 1'b1;
rnw_in[1] = 1'b1;
rnw_in[1] = 1'b1;
start[0] = 1'b1;
start[1] = 1'b1;
start[2] = 1'b1;
start[3] = 1'b1;
fork
begin
repeat (3) @(posedge ack[0]);
start[0] <= 1'b0;
end
begin
repeat (3) @(posedge ack[1]);
start[1] <= 1'b0;
repeat(9) @(posedge clk);
start[1] <= 1'b1;
repeat(2) @(posedge ack[1]);
start[1] <= 1'b0;
end
begin
repeat(13) @(posedge ack[2]);
start[2] <= 1'b0;
end
begin
repeat(17) @(posedge ack[3]);
start[3] <= 1'b0;
end
join
*/
// $stop;
end
endmodule
module dmaer(
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial
begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
always @(negedge rst_n)
begin
disable main_loop;
req = 1'b0;
rnw = 1'b1;
inprogress = 1'b0;
end
always
begin : main_loop
wait(rst_n);
wait(start);
begin : dma_loop
forever
begin
inprogress <= 1'b1;
rnw <= rnw_in;
req <= 1'b1;
@(negedge ack);
if( !start ) disable dma_loop;
end
end
req <= 1'b0;
wait(done);/*@(posedge done);*/
inprogress <= 1'b0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; long long int n, i, j, t, ans, arr[3009], crr[3009][3009]; int main() { scanf( %lld , &t); while (t--) { scanf( %lld , &n); ans = 0; for (i = 1; i <= n; i++) scanf( %lld , &arr[i]); for (i = n; i >= 1; i--) { for (j = i - 1; j >= 1; j--) { ans += crr[arr[i]][arr[j]]; } for (j = i + 1; j <= n; j++) { crr[arr[j]][arr[i]]++; } } printf( %lld n , ans); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) crr[i][j] = 0; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; const long long mod = 1e9 + 7; void solve(); signed main() { ios::sync_with_stdio(false); cin.tie(0); long long tests = 1; while (tests--) solve(); return 0; } void solve() { long long n; cin >> n; pair<long long, long long> a[n]; for (long long i = 0; i < n; i++) { cin >> a[i].second; long long x = a[i].second; long long cnt = 0; while (x % 3 == 0) { x = x / 3; ++cnt; } a[i].first = -cnt; } sort(a, a + n); for (long long i = 0; i < n; i++) { cout << a[i].second << ; } cout << endl; }
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//======================================================================
//
// Module Name: WHIRLPOOL_WCIPHER_SBOX
// Description: SBox function of Whirlpool W-Cipher
//
// Language: Verilog-2001
//
// Module Dependencies: none
//
// Developer: Saied H. Khayat
// URL: https://github.com/saiedhk
// Date: May 2014
//
// Copyright Notice: Free use of this library is permitted under the
// guidelines and in accordance with the MIT License (MIT).
// http://opensource.org/licenses/MIT
//
//======================================================================
`timescale 1ns/1ps
//`define DEBUG
// Sub-byte operation (a purely combinational module)
module WHIRLPOOL_WCIPHER_SBOX (
output reg [7:0 ] odata,
input [7:0 ] idata
);
//---------wires, registers----------
reg [3:0] a, b, d;
wire [3:0] c, g, h;
//---------combinational processes----------
// E-inverse mini-box
always @*
begin
case (idata[3:0])
4'h0: a = 4'hF;
4'h1: a = 4'h0;
4'h2: a = 4'hD;
4'h3: a = 4'h7;
4'h4: a = 4'hB;
4'h5: a = 4'hE;
4'h6: a = 4'h5;
4'h7: a = 4'hA;
4'h8: a = 4'h9;
4'h9: a = 4'h2;
4'hA: a = 4'hC;
4'hB: a = 4'h1;
4'hC: a = 4'h3;
4'hD: a = 4'h4;
4'hE: a = 4'h8;
4'hF: a = 4'h6;
endcase
end
// E mini-box
always @*
begin
case (idata[7:4])
4'h0: b = 4'h1;
4'h1: b = 4'hB;
4'h2: b = 4'h9;
4'h3: b = 4'hC;
4'h4: b = 4'hD;
4'h5: b = 4'h6;
4'h6: b = 4'hF;
4'h7: b = 4'h3;
4'h8: b = 4'hE;
4'h9: b = 4'h8;
4'hA: b = 4'h7;
4'hB: b = 4'h4;
4'hC: b = 4'hA;
4'hD: b = 4'h2;
4'hE: b = 4'h5;
4'hF: b = 4'h0;
endcase
end
// R mini-box
always @*
begin
case (c[3:0])
4'h0: d = 4'h7;
4'h1: d = 4'hC;
4'h2: d = 4'hB;
4'h3: d = 4'hD;
4'h4: d = 4'hE;
4'h5: d = 4'h4;
4'h6: d = 4'h9;
4'h7: d = 4'hF;
4'h8: d = 4'h6;
4'h9: d = 4'h3;
4'hA: d = 4'h8;
4'hB: d = 4'hA;
4'hC: d = 4'h2;
4'hD: d = 4'h5;
4'hE: d = 4'h1;
4'hF: d = 4'h0;
endcase
end
assign c[3:0] = { a[3]^b[3] , a[2]^b[2] , a[1]^b[1] , a[0]^b[0] };
assign g[3:0] = { a[3]^d[3] , a[2]^d[2] , a[1]^d[1] , a[0]^d[0] };
assign h[3:0] = { d[3]^b[3] , d[2]^b[2] , d[1]^b[1] , d[0]^b[0] };
// E-inverse mini-box
always @*
begin
case (g[3:0])
4'h0: odata[3:0] = 4'hF;
4'h1: odata[3:0] = 4'h0;
4'h2: odata[3:0] = 4'hD;
4'h3: odata[3:0] = 4'h7;
4'h4: odata[3:0] = 4'hB;
4'h5: odata[3:0] = 4'hE;
4'h6: odata[3:0] = 4'h5;
4'h7: odata[3:0] = 4'hA;
4'h8: odata[3:0] = 4'h9;
4'h9: odata[3:0] = 4'h2;
4'hA: odata[3:0] = 4'hC;
4'hB: odata[3:0] = 4'h1;
4'hC: odata[3:0] = 4'h3;
4'hD: odata[3:0] = 4'h4;
4'hE: odata[3:0] = 4'h8;
4'hF: odata[3:0] = 4'h6;
endcase
end
// E mini-box
always @*
begin
case (h[3:0])
4'h0: odata[7:4] = 4'h1;
4'h1: odata[7:4] = 4'hB;
4'h2: odata[7:4] = 4'h9;
4'h3: odata[7:4] = 4'hC;
4'h4: odata[7:4] = 4'hD;
4'h5: odata[7:4] = 4'h6;
4'h6: odata[7:4] = 4'hF;
4'h7: odata[7:4] = 4'h3;
4'h8: odata[7:4] = 4'hE;
4'h9: odata[7:4] = 4'h8;
4'hA: odata[7:4] = 4'h7;
4'hB: odata[7:4] = 4'h4;
4'hC: odata[7:4] = 4'hA;
4'hD: odata[7:4] = 4'h2;
4'hE: odata[7:4] = 4'h5;
4'hF: odata[7:4] = 4'h0;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const ll OO = 1e18; int di[8] = {0, 0, 1, -1, -1, 1, -1, 1}; int dj[8] = {1, -1, 0, 0, 1, 1, -1, -1}; string ys = YES , no = NO ; const long double dgr = acos(-1) / 180, dg = 180 / acos(-1); const int mod = 1e9 + 9, N = 1e5 + 5, M = 2001; ll fast_power(ll base, ll power) { ll ans = 1; while (power > 0) { if (power & 1) ans = (ans * base) % mod; base = (base * base) % mod; power >>= 1; } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; ll n, m; cin >> n >> m; ll pw_m = fast_power(2, m); ll ans = 1; for (int i = 1; i <= n; i++) { ans = ans * (pw_m - i) % mod; } cout << ans % mod << n ; }
|
// $Id: $
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2014 Dmitry Murzinov () //
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ns
module tb ();
// clock generator settings:
parameter cycles_reset = 2; // rst active (clk)
parameter clk_period = 10; // clk period ns
parameter clk_delay = 0; // clk initial delay
reg clk; // clock
reg rst; // sync reset
reg mode; // 0 - encrypt, 1 - decrypt
//reg select; // if GOST_R_3411_BOTH defined: 0 - Using the GOST R 34.11-94 TestParameter S-boxes; 1 - Using the CryptoPro S-boxes
reg load; // load plain text and start cipher cycles
wire done; // cipher text ready for output read
reg kload; // load cipher key
reg [255:0] key; // cipher key input
reg [63:0] pdata; // plain text input
wire [63:0] cdata; // cipher text output
reg [63:0] pdata_d; // plain text input
wire [63:0] cdata_d; // cipher text output
reg [63:0] reference_data; // reference data for verify
wire [63:0] data = {u.a,u.b};
wire [63:0] data2 = {u.b,u.a};
wire EQUAL = cdata == reference_data;
wire [8*4-1:0] STATUS = EQUAL ? "OK" : "FAIL";
// instance connect
gost_28147_89
u (
.clk(clk),
.rst(rst),
.mode(mode),
.load(load),
.done(done),
//.kload(kload),
.key(key),
.pdata(pdata),
.cdata(cdata)
);
reg [24:0] clk_counter; // just clock counter for debug
// Clock generation
always begin
# (clk_delay);
forever # (clk_period/2) clk = ~clk;
end
// Initial statement
initial begin
#0 clk = 1'b0;
load = 0;
kload = 0;
mode = 0;
//select = 0;
key = 256'h0;
pdata = 64'h0;
clk_counter = 0;
// Reset
#0 rst = 1'bX;
#0 rst = 1'b0;
# ( 2*clk_period *cycles_reset) rst = 1'b1;
# ( 2*clk_period *cycles_reset) rst = 1'b0;
// key load
@ ( posedge clk ) #1 kload = 1;
key = swapkey(256'hBE5EC200_6CFF9DCF_52354959_F1FF0CBF_E95061B5_A648C103_87069C25_997C0672);
@ ( posedge clk ) #1 kload = 0;
// Crypt mode
@ ( posedge clk ) #1 load = 1; mode = 0;
pdata = swapdata(64'h0DF82802_B741A292);
reference_data = swapdata(64'h07F9027D_F7F7DF89);
@ ( posedge clk ) #1 load = 0;
// Decrypt mode
@ ( posedge done );
@ ( posedge clk ) #1 load = 1; mode = 1;
pdata = swapdata(64'h07F9027D_F7F7DF89);
reference_data = swapdata(64'h0DF82802_B741A292);
@ ( posedge clk ) #1 load = 0;
//$finish;
@ ( posedge done );
@ ( posedge clk )
#1 $stop;
end
always begin
@( posedge clk );
clk_counter <= clk_counter + 1;
end // always
always @( posedge done )
if (mode == 0)
#1 $display("KEY: %H \nCRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s\n", key, pdata, reference_data, cdata, STATUS);
else if (mode == 1)
#1 $display("KEY: %H \nDECRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s\n", key, pdata, reference_data, cdata, STATUS);
always @(posedge clk)
#1 $display("i = %H load=%b done=%b \t data = %H | %H", u.i, u.load, u.done, data, data2);
/////////////// dumping
initial
begin
$dumpfile("gost_28147_89.vcd");
$dumpvars(0,tb);
end
// ======= swap4(x) =======
function [31:0] swap4( input [31:0] x );
begin
swap4 = {x[7:0],x[15:8],x[23:16],x[31:24]};
end
endfunction
// ======= swapdate(data) =======
function [63:0] swapdata( input [63:0] data );
begin
swapdata = {swap4(data[31:0]),swap4(data[63:32])};
end
endfunction
// ======= swapkey(key) =======
function [255:0] swapkey( input [255:0] key );
reg [31:0] K [0:7];
begin
K[0] = swap4(key[255:224]);
K[1] = swap4(key[223:192]);
K[2] = swap4(key[191:160]);
K[3] = swap4(key[159:128]);
K[4] = swap4(key[127:96]);
K[5] = swap4(key[95:64]);
K[6] = swap4(key[63:32]);
K[7] = swap4(key[31:0]);
swapkey = {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]};
end
endfunction
endmodule
// eof
|
#include <bits/stdc++.h> using namespace std; const int MAX = 60; const int A = 26; const int INF = 1000000001; char G[MAX + 2][MAX + 3]; int D[MAX + 2][MAX + 2]; bool ok[A + 1]; pair<int, int> S, T; vector<char> ans; vector<int> K; int n, m, k; inline int con(char c) { return a <= c && c <= z ? c - a : A; } vector<pair<int, int> > Q; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; bool vis[A + 1][A + 1][A + 1][A + 1]; void bfs() { sort((K).begin(), (K).end()); K.erase(unique((K).begin(), (K).end()), K.end()); if (K.back() == A) K.pop_back(); if (K.size() > k || K.empty()) return; if (vis[K[0]][K.size() > 1 ? K[1] : A][K.size() > 2 ? K[2] : A] [K.size() > 3 ? K[3] : A]) return; vis[K[0]][K.size() > 1 ? K[1] : A][K.size() > 2 ? K[2] : A] [K.size() > 3 ? K[3] : A] = true; for (int i = 0; i < K.size(); ++i) ok[K[i]] = true; for (int i = 0; i <= n + 1; ++i) memset(D[i], -1, sizeof(int) * (m + 2)); Q.clear(); Q.push_back(T); D[T.first][T.second] = 0; for (int foo = 0; foo < Q.size(); ++foo) { pair<int, int> v = Q[foo]; if (v == S) break; for (int foo = 0; foo < 4; ++foo) { int i = v.first + dx[foo]; int j = v.second + dy[foo]; if (ok[con(G[i][j])] && D[i][j] == -1) { D[i][j] = D[v.first][v.second] + 1; Q.push_back(make_pair(i, j)); } } } for (int i = 0; i < K.size(); ++i) ok[K[i]] = false; int d = INF; for (int foo = 0; foo < 4; ++foo) { int i = S.first + dx[foo]; int j = S.second + dy[foo]; if (D[i][j] != -1) d = min(d, D[i][j]); } if (d > ans.size()) return; int com = 0; int index = 0; vector<char> tmp; tmp.reserve(d); vector<pair<int, int> > V[2]; bool now = false; V[0].push_back(S); while (d) { int best = 200; for (int i = 0; i < K.size(); ++i) for (__typeof((V[now]).begin()) u = (V[now]).begin(); u != (V[now]).end(); ++u) for (int foo = 0; foo < 4; ++foo) { int x = u->first + dx[foo]; int y = u->second + dy[foo]; if (G[x][y] == K[i] + a && D[x][y] == d) { best = K[i]; goto out; } } out: tmp.push_back(best + a ); if (!com) { if (tmp.back() < ans[index]) com = -1; else if (tmp.back() > ans[index]) com = 1; } ++index; V[!now].clear(); for (__typeof((V[now]).begin()) u = (V[now]).begin(); u != (V[now]).end(); ++u) for (int foo = 0; foo < 4; ++foo) { int x = u->first + dx[foo]; int y = u->second + dy[foo]; if (G[x][y] == best + a && D[x][y] == d) { V[!now].push_back(make_pair(x, y)); D[x][y] = -1; } } --d; now = !now; } if (tmp.size() < ans.size() || com == -1) ans = tmp; } void solve(int x, int i) { if (x >= k) { vector<int> tmpK = K; bfs(); K = tmpK; return; } if (i == A) return; solve(x, i + 1); for (; i < A; ++i) { K.push_back(i); solve(x + 1, i + 1); K.pop_back(); } } int main(int argc, char *argv[]) { scanf( %d %d %d , &n, &m, &k); ans.resize(n * m + 10); for (int i = 0; i <= n + 1; ++i) memset(G[i], $ , m + 2); for (int i = 1; i <= n; ++i) scanf( %s , G[i] + 1); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (G[i][j] == S ) S = make_pair(i, j); else if (G[i][j] == T ) T = make_pair(i, j); if (abs(S.first - T.first) + abs(S.second - T.second) == 1) return 0; for (int xs = S.first - 1; xs <= S.first + 1; ++xs) for (int ys = S.second - 1; ys <= S.second + 1; ++ys) if (abs(xs - S.first) + abs(ys - S.second) == 1) for (int xt = T.first - 1; xt <= T.first + 1; ++xt) for (int yt = T.second - 1; yt <= T.second + 1; ++yt) if (abs(xt - T.first) + abs(yt - T.second) == 1) { K.clear(); K.push_back(con(G[xs][ys])); K.push_back(con(G[xt][yt])); if (K[0] == K[1]) K.pop_back(); solve(K.size(), 0); } if (ans.size() == n * m + 10) { printf( -1 n ); return 0; } for (__typeof((ans).begin()) i = (ans).begin(); i != (ans).end(); ++i) printf( %c , *i); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, l, r; vector<pair<int, int> > G[100005]; int seq[100005], cnts, siz[100005], rch[100005], num[100005]; bool vis[100005]; int rt, Min; void dfs(int now, int ff, int tsz) { int Max = 0; siz[now] = 1; rch[now] = 0; for (int i = 0, v, sz = G[now].size(); i < sz; i++) if ((v = G[now][i].first) != ff && !vis[v]) { dfs(v, now, tsz); rch[now] = max(rch[now], rch[v] + 1); siz[now] += siz[v]; Max = max(Max, siz[v]); } Max = max(Max, tsz - siz[now]); if (Max < Min) Min = Max, rt = now; } int Gert(int now, int tsz) { Min = 0x3f3f3f3f; dfs(now, -1, tsz); return rt; } bool cmp(const pair<int, int> &a, const pair<int, int> &b) { return rch[a.first] < rch[b.first]; } void setsiz(int now, int ff) { siz[now] = 1, rch[now] = 0; for (int i = 0, sz = G[now].size(), v; i < sz; i++) if ((v = G[now][i].first) != ff && !vis[v]) { setsiz(v, now); siz[now] += siz[v]; rch[now] = max(rch[now], rch[v] + 1); } } void Solve(int now) { seq[++cnts] = now; setsiz(now, -1); vis[now] = 1; rch[now] = 0; sort(G[now].begin(), G[now].end(), cmp); for (int v, i = 0, sz = G[now].size(); i < sz; i++) if (!vis[(v = G[now][i].first)]) Solve(Gert(v, siz[v])); } int f[100005], g[100005], floc[100005], gloc[100005], ansx, ansy; int Maxdep; void ser(int now, int ff, int dist, int cost, int Lim) { Maxdep = max(Maxdep, dist); if (cost > g[dist]) g[dist] = cost, gloc[dist] = now; for (int i = 0, sz = G[now].size(), v; i < sz; i++) if ((v = G[now][i].first) != ff && !vis[v]) ser(v, now, dist + 1, cost + (G[now][i].second >= Lim ? 1 : -1), Lim); } int Q[100005], L, R; bool check(int Lim) { memset(vis, 0, sizeof vis); memset(f, -0x3f, sizeof f); memset(g, -0x3f, sizeof g); f[0] = 0; int premaxdep = 0; for (int u, id = 1; id <= n; id++) { for (int i = 1; i <= premaxdep; i++) f[i] = -0x3f3f3f3f, g[i] = -0x3f3f3f3f; premaxdep = 0; vis[u = seq[id]] = 1; floc[0] = u; for (int predep = 0, i = 0, v, sz = G[u].size(); i < sz; i++) if (!vis[v = G[u][i].first]) { for (int j = 1; j <= predep; j++) g[j] = -0x3f3f3f3f; Maxdep = 0; ser(v, -1, 1, G[u][i].second >= Lim ? 1 : -1, Lim); L = R = 0; for (int j = 0, k = min(r, Maxdep); j <= predep; j++) { for (; j + k >= l && k >= 0; k--) { for (; L < R && g[k] >= g[Q[R - 1]]; R--) ; Q[R++] = k; } for (; L < R && Q[L] + j > r; L++) ; if (L < R && f[j] + g[Q[L]] >= 0) { ansx = floc[j]; ansy = gloc[Q[L]]; return 1; } } for (int j = 1; j <= Maxdep; j++) if (f[j] < g[j]) f[j] = g[j], floc[j] = gloc[j]; predep = Maxdep; premaxdep = max(premaxdep, Maxdep); } } return 0; } int main() { int u, v, w; scanf( %d%d%d , &n, &l, &r); for (int i = 1; i < n; i++) { scanf( %d%d%d , &u, &v, &w); G[u].push_back(make_pair(v, w)); G[v].push_back(make_pair(u, w)); } Solve(Gert(1, n)); int L = 0, R = 1000000000, Mid; while (L < R) { Mid = (L + R + 1) >> 1; if (check(Mid)) L = Mid; else R = Mid - 1; } check(L); printf( %d %d n , ansx, ansy); }
|
// `include "../define.v"
module memory (
input rst,
input ce,
input[`MemDataWidth-1:0] data_i,
input[`MemAddrWidth-1:0] addr_i,
input we,
input[`ByteSlctWidth-1:0] byte_slct,
`ifdef DEBUG
output reg[`MemDataWidth-1:0] data_o,
output[`MemDataWidth-1:0] mem20,
output[`MemDataWidth-1:0] mem21,
output[`MemDataWidth-1:0] mem22,
output[`MemDataWidth-1:0] mem23,
output[`MemDataWidth-1:0] mem24
`endif
`ifndef DEBUG
output reg[`MemDataWidth-1:0] data_o
`endif
);
`ifdef DEBUG
assign mem20 = mem_data[20];
assign mem21 = mem_data[21];
assign mem22 = mem_data[22];
assign mem23 = mem_data[23];
assign mem24 = mem_data[24];
`endif
parameter MemoryDataNum = 2048;
reg[`MemDataWidth-1:0] mem_data[MemoryDataNum-1:0];
wire[7:0] mem_byte_0;
wire[7:0] mem_byte_1;
wire[7:0] mem_byte_2;
wire[7:0] mem_byte_3;
wire[`MemDataWidth-1:0] data_temp;
assign mem_byte_3 = (byte_slct[3] == 1'b1) ? data_i[31:24] : mem_data[addr_i >> 2][31:24];
assign mem_byte_2 = (byte_slct[2] == 1'b1) ? data_i[23:16] : mem_data[addr_i >> 2][23:16];
assign mem_byte_1 = (byte_slct[1] == 1'b1) ? data_i[15:8] : mem_data[addr_i >> 2][15:8];
assign mem_byte_0 = (byte_slct[0] == 1'b1) ? data_i[7:0] : mem_data[addr_i >> 2][7:0];
// always @(*) begin
// mem_byte_3 <= (byte_slct[3] == 1'b1) ? data_i[31:24] : mem_data[addr_i >> 2][31:24];
// mem_byte_2 <= (byte_slct[2] == 1'b1) ? data_i[23:16] : mem_data[addr_i >> 2][23:16];
// mem_byte_1 <= (byte_slct[1] == 1'b1) ? data_i[15:8] : mem_data[addr_i >> 2][15:8];
// mem_byte_0 <= (byte_slct[0] == 1'b1) ? data_i[7:0] : mem_data[addr_i >> 2][7:0];
// end
assign data_temp = {mem_byte_3, mem_byte_2, mem_byte_1, mem_byte_0};
// reset
always @(*) begin : proc_reset
integer i;
if (rst == `RstEnable) begin
for (i = 0; i < MemoryDataNum; i = i + 1)
mem_data[i] <= `ZeroWord;
end
end
// write operation
always @ (*) begin
if (rst == ~`RstEnable && we == `WriteEnable)
#0.1 mem_data[addr_i >> 2] <= data_temp;
end
// read operation
always @ (*) begin
if (rst == ~`RstEnable && ce == `ChipEnable)
data_o <= mem_data[addr_i >> 2];
else
data_o <= `ZeroWord;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_out #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
// data interface
input [(DATA_WIDTH-1):0] data_s0,
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
input [(DATA_WIDTH-1):0] data_s3,
input [(DATA_WIDTH-1):0] data_s4,
input [(DATA_WIDTH-1):0] data_s5,
input [(DATA_WIDTH-1):0] data_s6,
input [(DATA_WIDTH-1):0] data_s7,
output [(DATA_WIDTH-1):0] data_out_se,
output [(DATA_WIDTH-1):0] data_out_p,
output [(DATA_WIDTH-1):0] data_out_n);
localparam DEVICE_7SERIES = 0;
localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR";
// internal signals
wire [(DATA_WIDTH-1):0] data_out_s;
wire [(DATA_WIDTH-1):0] serdes_shift1_s;
wire [(DATA_WIDTH-1):0] serdes_shift2_s;
assign data_out_se = data_out_s;
// instantiations
genvar l_inst;
generate
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
if (DEVICE_TYPE == DEVICE_7SERIES) begin
OSERDESE2 #(
.DATA_RATE_OQ (DR_OQ_DDR),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (SERDES_FACTOR),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_serdes (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.D3 (data_s2[l_inst]),
.D4 (data_s3[l_inst]),
.D5 (data_s4[l_inst]),
.D6 (data_s5[l_inst]),
.D7 (data_s6[l_inst]),
.D8 (data_s7[l_inst]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (clk),
.CLKDIV (div_clk),
.OQ (data_out_s[l_inst]),
.TQ (),
.OFB (),
.TFB (),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TCE (1'b0),
.RST (rst));
end
OBUFDS i_obuf (
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]),
.OB (data_out_n[l_inst]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int MAXN = 1000100; int q = 0, qq, n; double x[MAXN], y[MAXN]; double c1[MAXN]; double c2[MAXN]; double c[MAXN]; void solve() { cin >> n; for (int i = 0; i < n; ++i) { cin >> c1[i]; } for (int i = 0; i < n; ++i) { cin >> c2[i]; c[i] = c2[i] + c1[i]; } double s1 = 0, s2 = 0; for (int i = 0; i < n; ++i) { double b = (c[i] + s2 - s1); double x1 = -(-b + sqrt(max(0.0, ((b) * (b)) + 4 * (c[i] * s1 - c1[i])))) / 2; double x2 = -(-b - sqrt(max(0.0, ((b) * (b)) + 4 * (c[i] * s1 - c1[i])))) / 2; x[i] = max(x1, x2); y[i] = c[i] - x[i]; s1 += x[i]; s2 += y[i]; } cout.precision(10); for (int i = 0; i < n; ++i) cout << fixed << x[i] << ; cout << endl; for (int i = 0; i < n; ++i) cout << fixed << y[i] << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); srand(1313); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; priority_queue<pair<int, string> > all[10010]; int main() { int n, m; cin >> n >> m; string name; int reg, sc; for (int i = 0; i < n; i++) { cin >> name >> reg >> sc; all[reg].push(make_pair(sc, name)); } for (int i = 1; i <= m; i++) { int tt[4]; int tool = 0; pair<int, string> p[4]; while (all[i].size()) { p[tool] = all[i].top(); all[i].pop(); tt[tool++] = p[tool].first; if (tool == 3) break; } if (tool == 2) { cout << p[0].second << << p[1].second << endl; } else { if (p[0].first == p[2].first || p[1].first == p[2].first) { cout << ? << endl; } else { cout << p[0].second << << p[1].second << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ii = pair<ll, ll>; using vi = vector<ll>; using vb = vector<bool>; using vvi = vector<vi>; using vii = vector<ii>; using vvii = vector<vii>; const int INF = 2000000000; const ll LLINF = 9000000000000000000; void fix_mod(ll &v, ll M) { v = ((v - 1) % M + M) % M + 1; } int main() { int N; ll M; ll T; cin >> N >> M >> T; vii Si(N, {0LL, 0LL}); vi pos(N, 0LL); ll shift = 0; for (int i = 0; i < N; i++) { ll x; char c; cin >> x >> c; ll slope = (c == L ? -1 : 1); ll ic = (slope == 1 ? 1 - x : x); shift += ((T / M) % N) * slope; fix_mod(ic, M); if (ic <= T % M) shift += slope; Si[i] = {x, i}; pos[i] = x + (T % M) * slope; fix_mod(pos[i], M); } sort(Si.begin(), Si.end()); sort(pos.begin(), pos.end()); fix_mod(shift, N); vi ans(N, 0LL); for (int i = 0; i < N; i++) ans[Si[i].second] = pos[(i + shift) % N]; for (int i = 0; i < N - 1; i++) cout << ans[i] << ; cout << ans[N - 1] << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk; // surefire lint_off_line UDDIXN
integer _mode; initial _mode=0;
reg [31:0] ord1; initial ord1 = 32'h1111;
wire [31:0] ord2;
reg [31:0] ord3;
wire [31:0] ord4;
wire [31:0] ord5;
wire [31:0] ord6;
wire [31:0] ord7;
// verilator lint_off UNOPT
t_chg_a a (
.a(ord1), .a_p1(ord2),
.b(ord4), .b_p1(ord5),
.c(ord3), .c_p1(ord4),
.d(ord6), .d_p1(ord7)
);
// surefire lint_off ASWEMB
assign ord6 = ord5 + 1;
// verilator lint_on UNOPT
always @ (/*AS*/ord2) ord3 = ord2 + 1;
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
if (_mode==1) begin
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//if (ord2 == 2 && ord7 != 7) $stop;
end
end
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_chg: Running\n", $time);
_mode<=1;
ord1 <= 1;
end
else if (_mode==1) begin
_mode<=2;
if (ord7 !== 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_chg_a (/*AUTOARG*/
// Outputs
a_p1, b_p1, c_p1, d_p1,
// Inputs
a, b, c, d
);
input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1;
input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1;
input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1;
input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1;
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g #
(
parameter DATA_WIDTH = 8,
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* GMII interface
*/
input wire [DATA_WIDTH-1:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [DATA_WIDTH-1:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_gmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_gmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:20 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_4096/bram_4096_stub.v
// Design : bram_4096
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_4096(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
`timescale 1 ps / 1 ps
module ov7670_marker_tracker_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output intr,
input [7:0]OV7670_D,
input OV7670_HREF,
input OV7670_PCLK,
output OV7670_PWDN,
output OV7670_RESET,
output OV7670_SIOC,
inout OV7670_SIOD,
input OV7670_VSYNC,
output OV7670_XCLK,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ov7670_marker_tracker_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ov7670_marker_tracker_v1_0_S00_AXI_inst (
.intr(intr),
.OV7670_D,
.OV7670_HREF,
.OV7670_PCLK,
.OV7670_PWDN,
.OV7670_RESET,
.OV7670_SIOC,
.OV7670_SIOD,
.OV7670_VSYNC,
.OV7670_XCLK,
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
#include<bits/stdc++.h> using namespace std; #define ll long long int const ll mod = 1e9+7; void solve(){ int a; cin>>a; float arr[a]; float sum=0; for(int i=0;i<a;i++){ cin>>arr[i]; sum+=arr[i]; } float avg = sum/(float)a; sort(arr,arr+a); int ans=0; for(int i=0;i<a;i++){ if(arr[i]>arr[0]) ans++; } cout<<ans<<endl; } int main(){ int t; cin>>t; while(t--){ solve(); } }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module Altera_UP_SYNC_FIFO (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 128;
parameter ADDR_WIDTH = 7;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DATA_WIDTH:1] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [ADDR_WIDTH:1] words_used;
output [DATA_WIDTH:1] read_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data)
// Unused
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DATA_WIDTH,
Sync_FIFO.lpm_widthu = ADDR_WIDTH,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; long long mod_add(long long a, long long b, long long m) { a = a % m; b = b % m; return (((a + b) % m) + m) % m; } long long mod_mul(long long a, long long b, long long m) { a = a % m; b = b % m; return (((a * b) % m) + m) % m; } long long mod_sub(long long a, long long b, long long m) { a = a % m; b = b % m; return (((a - b) % m) + m) % m; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modInverse(long long n, long long p) { return power(n, p - 2, p); } long long nCrMODp(long long n, long long r, long long p) { if (n < r) return 0; if (r == 0) return 1; long long fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } void divisors(int n) { for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) cout << << i; else cout << << i << << n / i; } } } void primeFactors(int n) { while (n % 2 == 0) { cout << 2 << ; n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { cout << i << ; n = n / i; } } if (n > 2) cout << n << ; } void solve() { int t; cin >> t; cin.ignore(); while (t--) { int i, x = 0, y = 0; string str; cin >> str; for (i = 0; i < str.size(); i++) str[i] == B ? x++ : y++; y == x ? cout << YES n : cout << NO n ; } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); auto start1 = high_resolution_clock::now(); solve(); auto stop1 = high_resolution_clock::now(); auto duration = duration_cast<microseconds>(stop1 - start1); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct edge { int v, nxt, c; } e[1505 * 1505 * 2]; int p[1505], eid; void init() { memset(p, -1, sizeof p); eid = 0; } void insert(int u, int v, int c) { e[eid].v = v; e[eid].c = c; e[eid].nxt = p[u]; p[u] = eid++; } void add(int u, int v, int c) { insert(u, v, c); insert(v, u, 0); } int ch[10000005][2], cnt[10000005], tot, ys[1505], nxt[10000005], g[755][755], L[1505], R[1505], ha[10000005]; string st; queue<int> q; void insert(int id) { int p = 0, len = st.length(); L[id] = ha[0] + 1; for (int i = 0; i < len; i++) { ha[++ha[0]] = st[i] - a ; if (!ch[p][st[i] - a ]) ch[p][st[i] - a ] = ++tot; p = ch[p][st[i] - a ]; } cnt[p] = id; R[id] = ha[0]; } void build() { for (int i = 0; i < 2; i++) if (ch[0][i]) q.push(ch[0][i]); while (q.size()) { int u = q.front(); q.pop(); for (int i = 0; i < 2; i++) { if (!ch[u][i]) ch[u][i] = ch[nxt[u]][i]; else nxt[ch[u][i]] = ch[nxt[u]][i], q.push(ch[u][i]); } } } int vis[10000005]; void run(int id) { int p = 0; vis[0] = 1; for (int i = L[id]; i <= R[id]; i++) { p = ch[p][ha[i]]; int pp = p, tt; while (pp) { if (cnt[pp] && cnt[pp] != id) { g[id][cnt[pp]] = 1; break; } pp = nxt[pp]; } int haha = pp; pp = p; while (pp) { if (cnt[pp] && cnt[pp] != id) { break; } tt = pp; pp = nxt[pp]; nxt[tt] = haha; } } } int dis[1505], S, T, n; int bfs() { memset(dis, -1, sizeof dis); dis[S] = 1; q.push(S); while (q.size()) { int u = q.front(); q.pop(); for (int i = p[u]; i + 1; i = e[i].nxt) { int v = e[i].v; if (dis[v] == -1 && e[i].c) { dis[v] = dis[u] + 1; q.push(v); } } } return dis[T] != -1; } int dfs(int u, int flow) { if (u == T) return flow; int ret = 0; for (int i = p[u]; i + 1; i = e[i].nxt) { int c = e[i].c, v = e[i].v; if (c && dis[v] == dis[u] + 1) { int tmp = dfs(v, min(flow, c)); ret += tmp, flow -= tmp; e[i].c -= tmp, e[i ^ 1].c += tmp; if (!flow) break; } } if (!ret) dis[u] = -1; return ret; } int Dinic() { int ret = 0; for (; bfs();) ret += dfs(S, 2147483646 / 2); return ret; } int main() { ios::sync_with_stdio(false); init(); cin >> n; T = 2 * n + 1; for (int i = 1; i <= n; i++) cin >> st, insert(i); build(); for (int i = 1; i <= n; i++) run(i); for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) g[i][j] |= (g[i][k] & g[k][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (g[i][j] && i != j) add(i, j + n, 1); for (int i = 1; i <= n; i++) add(S, i, 1), add(i + n, T, 1), vis[i + n] = 0; cout << n - Dinic() << endl; for (int i = 1; i <= n; i++) if (dis[i] != -1 && dis[i + n] == -1) cout << i << ; return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; template <typename T> using V = vector<T>; const int N = 1e5 + 5; bool taken[3 * N]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tc; cin >> tc; while (tc--) { int n, m; cin >> n >> m; for (int i = 1; i <= 3 * n; ++i) taken[i] = false; vector<pii> edges(m); vector<int> matching; for (auto &e : edges) { cin >> e.first >> e.second; } int id = 0; for (auto &e : edges) { ++id; if (taken[e.first] or taken[e.second]) continue; matching.push_back(id); taken[e.first] = taken[e.second] = true; } if ((int)matching.size() >= n) { cout << Matching n ; for (int i = 0; i < n; ++i) { cout << matching[i] << ; } } else { cout << IndSet n ; for (int i = 1, cnt = 0; cnt < n; ++i) { if (!taken[i]) { cout << i << ; ++cnt; } } } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<long long, int> MP; int Q = 1; vector<pair<int, int> > adj[500005]; long long C[500005]; set<int> S; int p[500005]; long long pw(int x) { if (!x) return 1LL; if (x & 1) return 2 * pw(x - 1) % 1000000007; long long hf = pw(x / 2); return hf * hf % 1000000007; } int par(int x) { if (p[x] == x) return x; return p[x] = par(p[x]); } int main() { int N, M, K; scanf( %d%d%d , &N, &M, &K); long long X = (1LL << K); for (int i = 1; i <= N; i++) scanf( %lld , &C[i]); for (int i = 0; i < M; i++) { int u, v; scanf( %d%d , &u, &v); long long x = C[u] ^ C[v]; int t = MP[x]; if (!t) { MP[x] = Q; adj[Q].push_back(pair<int, int>(u, v)); Q++; } else { adj[t].push_back(pair<int, int>(u, v)); } } int ans = 0; for (int i = 1; i <= N; i++) p[i] = i; for (int i = 1; i < Q; i++) { int sz = N; for (pair<int, int> j : adj[i]) { int u = j.first, v = j.second; S.insert(u); S.insert(v); if (par(u) != par(v)) { sz--; p[p[v]] = p[u]; } } ans = (ans + pw(sz)) % 1000000007; while (S.size()) { int now = *(S.begin()); p[now] = now; S.erase(S.begin()); } } printf( %lld n , ((X - Q + 1) % 1000000007 * pw(N) % 1000000007 + ans) % 1000000007); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { char i = getchar(); long long f = 1, res = 0; while (i < 0 || i > 9 ) { if (i == - ) f = -1; i = getchar(); } while (i >= 0 && i <= 9 ) { res = res * 10 + i - 0 ; i = getchar(); } return res * f; } const int N = 1e5 + 50; long long h[N], a[N], n, m, k, p; struct bamboo { long long time, id; bool operator<(const bamboo& A) const { return time > A.time; } bamboo(long long T, long long ID) : time(T), id(ID) {} }; priority_queue<bamboo> q; long long cnt[N]; bool pd(long long mid) { while (!q.empty()) { q.pop(); } memset(cnt, 0, sizeof(cnt)); for (register int i = 1; i <= n; ++i) { if (mid - a[i] * m < h[i]) { q.push(bamboo(mid / a[i], i)); } } for (register int i = 1; i <= m; ++i) { if (q.empty()) { break; } for (register int j = 1; j <= k; ++j) { if (q.empty()) { break; } bamboo now = q.top(); q.pop(); if (now.time < i) { return false; } cnt[now.id]++; if (mid + cnt[now.id] * p - a[now.id] * m < h[now.id]) { q.push(bamboo((mid + cnt[now.id] * p) / a[now.id], now.id)); } } } return q.empty(); } int main() { n = read(); m = read(); k = read(); p = read(); long long l = 0, r = -10, ans = -1, mid; for (register int i = 1; i <= n; ++i) { h[i] = read(); a[i] = read(); r = max(r, h[i] + a[i] * m); } while (l <= r) { mid = (l + r) >> 1; if (pd(mid)) { r = mid - 1; ans = mid; } else l = mid + 1; } printf( %lld , ans); }
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#include <bits/stdc++.h> using namespace std; inline void sfr(int *a) { char c = 0; while (c < 33) c = fgetc(stdin); *a = 0; while (c > 33) { *a = *a * 10 + c - 0 ; c = fgetc(stdin); } } inline void sfp(int a) { char c[1000]; sprintf(c, %d , a); puts(c); } int main() { int n; cin >> n; ; int m; cin >> m; ; int A[n][m]; getchar(); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char c = n ; while (c == n ) c = getchar(); A[i][j] = (c == 1 ); } } int B[n]; int mx = 0; for (int i = n - 1; i >= 0; i--) B[i] = 0; for (int i = m - 1; i >= 0; i--) { vector<int> D; for (int j = 0; j < n; j++) { if (A[j][i]) { B[j] = B[j] + 1; D.push_back(B[j]); } else { B[j] = 0; D.push_back(0); } } sort(D.begin(), D.end()); for (int j = 0; j < n; j++) mx = max(mx, D[j] * (n - j)); } cout << mx << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100105; const double eps = 1e-6; long double x1, y1_, x2, y2, mx, my, vx, vy, d, L, ans = 1e16; vector<pair<long double, int> > V; int X[N], Y[N], R[N], n, s = 0; long double check(int k, long double t, int op) { return ((sqrt(d * d + t * t) + op * R[k]) * (sqrt(d * d + t * t) + op * R[k])) - ((X[k] - mx - vx * t) * (X[k] - mx - vx * t)) - ((Y[k] - my - vy * t) * (Y[k] - my - vy * t)); } long double BI(int k, int op) { long double l = -1e12, r = 1e12, mid, c = check(k, l, op), cc; while (r - l > eps) { mid = (l + r) / 2, cc = check(k, mid, op); (c > 0 && cc > 0 || c < 0 && cc < 0) ? l = mid : r = mid; } return (l + r) / 2; } int main() { scanf( %Lf%Lf%Lf%Lf%d , &x1, &y1_, &x2, &y2, &n); for (int i = (1); i <= (n); ++i) scanf( %d%d%d , &X[i], &Y[i], &R[i]); mx = (x1 + x2) / 2, my = (y1_ + y2) / 2, L = sqrt(((x1 - x2) * (x1 - x2)) + ((y1_ - y2) * (y1_ - y2))), vx = (y1_ - y2) / L, vy = (x2 - x1) / L, d = L / 2; for (int i = (1); i <= (n); ++i) { long double l = BI(i, 1), r = BI(i, -1); if (l > r) swap(l, r); V.push_back(make_pair(l - eps, -1)), V.push_back(make_pair(r + eps, 1)); } V.push_back(make_pair(0, 0)); sort((V).begin(), (V).end()); for (int i = 0; i < V.size(); i++) { s += V[i].second; if (s == 0 || V[i].second == -1 && s == -1) ans = min(ans, sqrt(((V[i].first) * (V[i].first)) + ((d) * (d)))); } printf( %.12Lf n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_4_V
`define SKY130_FD_SC_MS__O21BAI_4_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_4_V
|
//--------------------------------------------------------------------------------
// trigger.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Complex 4 stage 32 channel trigger.
//
// All commands are passed on to the stages. This file only maintains
// the global trigger level and it outputs the run condition if it is set
// by any of the stages.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Ian Davis (IED) - Verilog version, changed to use LUT based
// masked comparisons, and other cleanups created - mygizmos.org
//
`timescale 1ns/100ps
module trigger #(
parameter integer DW = 32
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire [3:0] wrMask, // Write trigger mask register
input wire [3:0] wrValue, // Write trigger value register
input wire [3:0] wrConfig, // Write trigger config register
input wire [31:0] config_data, // Data to write into trigger config regs
input wire arm,
input wire demux_mode,
// input stream
input wire sti_valid,
input wire [DW-1:0] sti_data, // Channel data...
// status
output reg capture, // Store captured data in fifo.
output wire run // Tell controller when trigger hit.
);
reg [1:0] levelReg = 2'b00;
// if any of the stages set run, then capturing starts...
wire [3:0] stageRun;
assign run = |stageRun;
//
// IED - Shift register initialization handler...
//
// Much more space efficient in FPGA to compare this way.
//
// Instead of four seperate 32-bit value, 32-bit mask, and 32-bit comparison
// functions & all manner of flops & interconnect, each stage uses LUT table
// lookups instead.
//
// Each LUT RAM evaluates 4-bits of input. The RAM is programmed to
// evaluate the original masked compare function, and is serially downloaded
// by the following verilog.
//
//
// Background:
// ----------
// The original function was:
// hit = ((data[31:0] ^ value[31:0]) & mask[31:0])==0;
//
//
// The following table shows the result for a single bit:
// data value mask hit
// x x 0 1
// 0 0 1 1
// 0 1 1 0
// 1 0 1 0
// 1 1 1 1
//
// If a mask bit is zero, it always matches. If one, then
// the result of comparing data & value matters. If data &
// value match, the XOR function results in zero. So if either
// the mask is zero, or the input matches value, you get a hit.
//
//
// New code
// --------
// To evaluate the data, each address of the LUT RAM's evalutes:
// What hit value should result assuming my address as input?
//
// In other words, LUT for data[3:0] stores the following at given addresses:
// LUT address 0 stores result of: (4'h0 ^ value[3:0]) & mask[3:0])==0
// LUT address 1 stores result of: (4'h1 ^ value[3:0]) & mask[3:0])==0
// LUT address 2 stores result of: (4'h2 ^ value[3:0]) & mask[3:0])==0
// LUT address 3 stores result of: (4'h3 ^ value[3:0]) & mask[3:0])==0
// LUT address 4 stores result of: (4'h4 ^ value[3:0]) & mask[3:0])==0
// etc...
//
// The LUT for data[7:4] stores the following:
// LUT address 0 stores result of: (4'h0 ^ value[7:4]) & mask[7:4])==0
// LUT address 1 stores result of: (4'h1 ^ value[7:4]) & mask[7:4])==0
// LUT address 2 stores result of: (4'h2 ^ value[7:4]) & mask[7:4])==0
// LUT address 3 stores result of: (4'h3 ^ value[7:4]) & mask[7:4])==0
// LUT address 4 stores result of: (4'h4 ^ value[7:4]) & mask[7:4])==0
// etc...
//
// Eight LUT's are needed to evalute all 32-bits of data, so the
// following verilog computes the LUT RAM data for all simultaneously.
//
//
// Result:
// ------
// It functionally does exactly the same thing as before. Just uses
// less FPGA. Only requirement is the Client software on your PC issue
// the value & mask's for each trigger stage in pairs.
//
reg [DW-1:0] maskRegister;
reg [DW-1:0] valueRegister;
reg [3:0] wrcount = 0;
reg [3:0] wrenb = 4'b0;
wire [7:0] wrdata;
always @ (posedge clk)
begin
maskRegister <= (|wrMask ) ? config_data : maskRegister;
valueRegister <= (|wrValue) ? config_data : valueRegister;
end
always @ (posedge clk, posedge rst)
if (rst) begin
wrcount <= 0;
wrenb <= 4'h0;
end else begin
// Do 16 writes when value register written...
if (|wrenb) begin
wrcount <= wrcount + 'b1;
if (&wrcount) wrenb <= 4'h0;
end else begin
wrcount <= 0;
wrenb <= wrenb | wrValue;
end
end
// Compute data for the 8 target LUT's...
assign wrdata = {
~|((~wrcount^valueRegister[31:28])&maskRegister[31:28]),
~|((~wrcount^valueRegister[27:24])&maskRegister[27:24]),
~|((~wrcount^valueRegister[23:20])&maskRegister[23:20]),
~|((~wrcount^valueRegister[19:16])&maskRegister[19:16]),
~|((~wrcount^valueRegister[15:12])&maskRegister[15:12]),
~|((~wrcount^valueRegister[11: 8])&maskRegister[11: 8]),
~|((~wrcount^valueRegister[7 : 4])&maskRegister[ 7: 4]),
~|((~wrcount^valueRegister[3 : 0])&maskRegister[ 3: 0])
};
//
// Instantiate stages...
//
wire [3:0] stageMatch;
stage stage [3:0] (
// system signals
.clk (clk),
.rst (rst),
// input stream
.dataIn (sti_data),
.validIn (sti_valid),
//.wrMask (wrMask),
//.wrValue (wrValue),
.wrenb (wrenb),
.din (wrdata),
.wrConfig (wrConfig),
.config_data(config_data),
.arm (arm),
.level (levelReg),
.demux_mode (demux_mode),
.run (stageRun),
.match (stageMatch)
);
//
// Increase level on match (on any level?!)...
//
always @(posedge clk, posedge rst)
begin : P2
if (rst) begin
capture <= 1'b0;
levelReg <= 2'b00;
end else begin
capture <= arm | capture;
if (|stageMatch) levelReg <= levelReg + 'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; int n; cin >> n >> a >> b; int T[n], pom[n]; for (int i = 0; i < n; ++i) T[i] = -1; for (int i = 0; i < n; ++i) { bool ud = false; for (int j = 0; j < n; ++j) { if (T[j] == -1 && a[j] == b[i]) { ud = true; T[j] = i; break; } } if (!ud) { cout << -1 << endl; return 0; } } queue<int> ans; int t = (T[n - 1] == 0 ? n - 1 : n); while (t > 0) { int np = -1; for (int i = 0; i < n; ++i) if (T[i] == n - t) { np = i; break; } ans.push(n - np - 1); ans.push(1); ans.push(n); int id = 0; for (int i = np - 1; i >= 0; --i) { pom[id++] = T[i]; } for (int i = np + 1; i < t; ++i) { pom[i - 1] = T[i]; } t--; for (int i = 0; i < t; ++i) T[i] = pom[i]; for (int i = t; i < n; ++i) { T[i] = i - t; } } cout << ans.size() << endl; while (!ans.empty()) { cout << ans.front() << ; ans.pop(); } cout << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9152_core (
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
// dma interface
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [15:0] dac_data_0_0;
output [15:0] dac_data_0_1;
output [15:0] dac_data_0_2;
output [15:0] dac_data_0_3;
output [15:0] dac_data_1_0;
output [15:0] dac_data_1_1;
output [15:0] dac_data_1_2;
output [15:0] dac_data_1_3;
// dma interface
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [31:0] up_rdata_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// dac valid
assign dac_valid_0 = 1'b1;
assign dac_valid_1 = 1'b1;
assign dac_valid_2 = 1'b1;
assign dac_valid_3 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
end
end
// dac channel
axi_ad9152_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
.dac_data ({dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}),
.dma_data (dac_ddata_0),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac channel
axi_ad9152_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
.dac_data ({dac_data_1_3, dac_data_1_2, dac_data_1_1, dac_data_1_0}),
.dma_data (dac_ddata_1),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long x, d; int cntDist = 0; string inp; cin >> n >> x; getline(cin, inp); for (int i = 0; i < n; i++) { getline(cin, inp); stringstream ss(inp.substr(2)); ss >> d; if (inp[0] == + ) { x += d; } else { if (x < d) cntDist++; else x -= d; } } cout << x << << cntDist; return 0; }
|
#include <bits/stdc++.h> using namespace std; int total_operation = 0; bool is_prime(long long n) { if (n == 2) return true; if (n % 2 == 0 || n < 2) return false; for (int i = 3; i * i <= n; i += 2) { if (n % i == 0) return false; } return true; } int countprime_in_range(int n) { vector<bool> isprime(n + 1, true); isprime[0] = isprime[1] = false; for (int i = 2; i * i <= n; ++i) { if (isprime[i]) { for (int j = 2 * i; j <= n; j += i) { isprime[j] = 0; } } } int cnt = 0; for (int i = 0; i <= n; i++) { if (isprime[i]) cnt++; } return cnt; } int main() { int fact1[3], fact2[3]; fact1[0] = fact1[1] = fact1[2] = 0; fact2[0] = fact2[1] = fact2[2] = 0; int A, B; cin >> A >> B; if (A == B) { cout << 0 ; return 0; } while (A) { if (!(A % 2)) fact1[0]++, A /= 2; else if (!(A % 3)) fact1[1]++, A /= 3; else if (!(A % 5)) fact1[2]++, A /= 5; else break; } while (B) { if (!(B % 2)) fact2[0]++, B /= 2; else if (!(B % 3)) fact2[1]++, B /= 3; else if (!(B % 5)) fact2[2]++, B /= 5; else break; } if (A != B) cout << -1 ; else cout << abs(fact1[0] - fact2[0]) + abs(fact1[1] - fact2[1]) + abs(fact1[2] - fact2[2]); }
|
#include <bits/stdc++.h> using namespace std; int main() { string str; int n; cin >> n >> str; int A[n], m = 0; string RE[n]; A[0] = 0; for (int i = 1, t = 0, tmp = [ ; i < n; i++) { if (str[i] == tmp) { if (str[i] == ] ) t--; else t++; } A[i] = t; if (t > m) m = t; tmp = str[i]; } for (int i = 0; i < m + 2; i++) { for (int j = 0; j < n; j++) { if (A[j] == i) { if (str[j] == [ ) RE[i].append( +- ); else if (str[j] == ] && str[j - 1] == [ ) RE[i].append( -+ ); else RE[i].append( -+ ); } else if (A[j] > i) { if (str[j - 1] == str[j]) RE[i].append( ); else if (str[j - 1] == [ && str[j] == ] ) RE[i].append( ); else RE[i].append( ); } else { if (str[j - 1] == [ && str[j] == ] ) { RE[i].append( | ); } else { RE[i].append( | ); } } } cout << RE[i] << endl; } for (int i = m; i >= 0; i--) { cout << RE[i] << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long cross2(long long x1, long long y1, long long x2, long long y2) { return x1 * y2 - x2 * y1; } long long cross(long long i, long long j, long long k, const long long* xx, const long long* yy) { return cross2(xx[j] - xx[i], yy[j] - yy[i], xx[k] - xx[i], yy[k] - yy[i]); } int main() { int n; cin >> n; auto* xx = new long long[n]; auto* yy = new long long[n]; for (int i = 0; i < n; i++) { cin >> xx[i]; cin >> yy[i]; } bool flip = xx[0] < xx[1]; long long x = xx[1], y = yy[1]; for (int i = 0; i < n; i++) { xx[i] -= x; yy[i] -= y; if (flip) { xx[i] = -xx[i]; yy[i] = -yy[i]; } } long long left = 0, right = xx[0]; for (int i = 2; i + 1 < n; i++) { long long cright = cross(i, i + 1, 0, xx, yy); long long cleft = cross(i, i + 1, 1, xx, yy); if (cright > 0 && cleft > 0) { cout << 0; return 0; } long long x0 = xx[i], y0 = yy[i], x1 = xx[i + 1], y1 = yy[i + 1]; if (cright > 0 || cleft > 0) { long long p = x0 * (y1 - y0) - y0 * (x1 - x0); long long q = y1 - y0; if (q < 0) { p = -p; q = -q; } if (cright > 0) right = min(right, (p / q)); else left = max(left, ((p + q - 1) / q)); } } cout << (left <= right ? right - left + 1 : 0) << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int main() { cin >> n >> m >> k; if (m >= n && k >= n) cout << Yes ; else cout << No ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T euclide(T a, T b, T& x, T& y) { if (a < 0) { T d = euclide(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = euclide(a, -b, x, y); y = -y; return d; } if (b == 0) { x = 1; y = 0; return a; } else { T d = euclide(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <class T> inline void checkmin(T& a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T& a, T b) { if (b > a) a = b; } template <class T> T Abs(T x) { return x > 0 ? x : -x; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline bool isPrime(T n) { if (n <= 1) return false; for (T i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } template <class T> inline T Mod(T n, T m) { return (n % m + m) % m; } template <class T> string toString(T n) { ostringstream oss; oss << n; oss.flush(); return oss.str(); } int toInt(string s) { int r = 0; istringstream sin(s); sin >> r; return r; } long long toLl(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } template <class T> void debug(const T& e) { cout << e << endl; } template <class T1, class T2> void debug(const T1& e1, const T2& e2) { cout << e1 << t << e2 << endl; } template <class T1, class T2, class T3> void debug(const T1& e1, const T2& e2, const T3& e3) { cout << e1 << t << e2 << t << e3 << endl; } template <class T1, class T2, class T3, class T4> void debug(const T1& e1, const T2& e2, const T3& e3, const T4& e4) { cout << e1 << t << e2 << t << e3 << t << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void debug(const T1& e1, const T2& e2, const T3& e3, const T4& e4, const T5& e5) { cout << e1 << t << e2 << t << e3 << t << e4 << t << e5 << endl; } template <class T> void debug(vector<T>& e) { int i; for (i = 0; i < (int)e.size(); i++) cout << e[i] << ; cout << endl; } template <class T> void debug(vector<basic_string<T> >& e) { int i, j; for (i = 0; i < (int)e.size(); i++) { for (j = 0; j < (int)e[i].size(); j++) cout << e[i][j]; cout << endl; } cout << endl; } template <class T> void debug(vector<vector<T> >& e, int row, int col) { int i, j; for (i = 0; i < row; i++) { for (j = 0; j < col; j++) cout << e[i][j] << t ; cout << endl; } cout << endl; } template <class T> void debug(T e[100010][100010], int row, int col) { int i, j; for (i = 0; i < row; i++) { for (j = 0; j < col; j++) cout << e[i][j] << ; cout << endl; } } long long Pow(long long B, long long P) { long long R = 1; while (P > 0) { if (P % 2 == 1) R = (R * B); P /= 2; B = (B * B); } return R; } int x[100010], y[100010], a[100010]; int main() { int i, j, test, Case = 1, n, cnt; while (scanf( %d , &n) == 1) { for (i = 0; i < n; i++) scanf( %d , &a[i]); x[0] = a[0]; for (i = 1; i < n; i++) x[i] = a[i] + x[i - 1]; y[n - 1] = a[n - 1]; for (i = n - 2; i >= 0; i--) y[i] = a[i] + y[i + 1]; cnt = 0; for (i = 0; i < n - 1; i++) if (x[i] == y[i + 1]) cnt++; printf( %d n , cnt); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void display(std::vector<int> v) { for (int i = 3; i >= 0; i--) { for (int j = 0; j < v[i]; j++) { if (i == 3) cout << 7; else if (i == 2) cout << 5; else if (i == 1) cout << 3; else if (i == 0) cout << 2; } } } int main() { int n; cin >> n; std::vector<int> v = {0, 0, 0, 0}; while (n--) { char c; cin >> c; if (c == 2 ) v[0]++; else if (c == 3 ) v[1]++; else if (c == 4 ) { v[0] += 2; v[1]++; } else if (c == 5 ) v[2]++; else if (c == 6 ) { v[1] += 1; v[2]++; } else if (c == 7 ) v[3]++; else if (c == 8 ) { v[3]++; v[0] += 3; } else if (c == 9 ) { v[1] += 2; v[0]++; v[3]++; } } display(v); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m, k; cin >> n >> m >> k; string ans; for (int i = 0; i < n; i++) ans += U ; for (int i = 0; i < m; i++) ans += L ; for (int i = 0; i < n; i++) { for (int j = 0; j < m - 1; j++) { ans += (i % 2 ? L : R ); } if (i < n - 1) ans += D ; } cout << ans.size() << n << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int tree[262192]; int a[262192], pre[262192], ok[262192]; int n; void check() { int i, all_1 = 1; for (i = 1; i <= n; ++i) { if (a[i] != 1) all_1 = 0; } if (all_1) { printf( 1 n ); exit(0); } } void update(int pt, int l, int r, int index, int val) { if (l > r || pt < l || pt > r) return; if (l == r) { tree[index] = max(tree[index], val); return; } if (pt <= ((l + r) >> 1)) { update(pt, l, ((l + r) >> 1), (index << 1), val); } else { update(pt, ((l + r) >> 1) + 1, r, (index << 1 | 1), val); } tree[index] = min(tree[(index << 1)], tree[(index << 1 | 1)]); } int query(int start, int end, int l, int r, int index) { if (start > end || l > r || start > r || l > end) return 0; if (start <= l && r <= end) return tree[index]; if (end <= ((l + r) >> 1)) return query(start, end, l, ((l + r) >> 1), (index << 1)); if (start >= ((l + r) >> 1) + 1) return query(start, end, ((l + r) >> 1) + 1, r, (index << 1 | 1)); return min(query(start, end, l, ((l + r) >> 1), (index << 1)), query(start, end, ((l + r) >> 1) + 1, r, (index << 1 | 1))); } int main() { int i; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); check(); for (i = 1; i <= n; ++i) { if (query(1, a[i] - 1, 1, n, 1) > pre[a[i]]) { ok[a[i]] = 1; } pre[a[i]] = i; update(a[i], 1, n, 1, i); } for (i = 1; i <= n; ++i) { if (query(1, i, 1, n, 1) > pre[i + 1]) { ok[i + 1] = 1; } } for (i = 2; i <= n + 2; ++i) { if (!ok[i]) { printf( %d n , i); break; } } return 0; }
|
// soc_design_mm_interconnect_0_avalon_st_adapter_006.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter_006 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_006_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int nega = 1; while (!isdigit(ch)) { if (ch == - ) nega = -1; ch = getchar(); } int ans = 0; while (isdigit(ch)) { ans = ans * 10 + ch - 48; ch = getchar(); } if (nega == -1) return -ans; return ans; } int fa[200005 * 2], siz[200005 * 2], n; int find(int u) { return fa[u] == u ? u : fa[u] = find(fa[u]); } int a[200005], b[200005]; vector<int> v[200005]; void merge(int u, int v) { u = find(u), v = find(v); if (u == v) return; fa[u] = v; siz[v] += siz[u]; } bool vis[200005 * 2], ch[200005 * 2]; void work() { cin >> n; for (int i = 1; i <= n; i++) v[i].clear(); for (int i = 1; i <= n; i++) a[i] = read(), v[a[i]].push_back(i); for (int i = 1; i <= n; i++) b[i] = read(), v[b[i]].push_back(i + n); for (int i = 1; i <= 2 * n; i++) fa[i] = i; for (int i = 1; i <= n; i++) siz[i] = 1; for (int i = n + 1; i <= 2 * n; i++) siz[i] = 0; for (int i = 1; i <= n * 2; i++) vis[i] = ch[i] = 0; for (int i = 1; i <= n; i++) { if (v[i].size() != 2) { cout << -1 n ; return; } int a = v[i][0], b = v[i][1]; if (a > b) swap(a, b); if (a == b - n) continue; if (a > n) { a -= n, b -= n; merge(a, b + n), merge(a + n, b); } else if (b <= n) merge(a, b + n), merge(a + n, b); else { b -= n; merge(a, b), merge(a + n, b + n); } } for (int i = 1; i <= n; i++) { if (find(i) == find(i + n)) { cout << -1 n ; return; } } int ans = 0; for (int i = 1; i <= n; i++) { int u = find(i), v = find(i + n); if (vis[u] || vis[v]) continue; ans += min(siz[u], siz[v]); vis[u] = vis[v] = 1; if (siz[u] < siz[v]) ch[u] = 1; else ch[v] = 1; } cout << ans << endl; for (int i = 1; i <= n; i++) { int u = find(i); if (ch[u]) printf( %d , i); } cout << n ; } signed main() { int T = read(); while (T--) work(); return 0; }
|
//#############################################################################
//# Function: 12:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux12 #(parameter DW = 1 ) // width of mux
(
input sel11,
input sel10,
input sel9,
input sel8,
input sel7,
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in11,
input [DW-1:0] in10,
input [DW-1:0] in9,
input [DW-1:0] in8,
input [DW-1:0] in7,
input [DW-1:0] in6,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0] |
{(DW){sel5}} & in5[DW-1:0] |
{(DW){sel6}} & in6[DW-1:0] |
{(DW){sel7}} & in7[DW-1:0] |
{(DW){sel8}} & in8[DW-1:0] |
{(DW){sel9}} & in9[DW-1:0] |
{(DW){sel10}} & in10[DW-1:0] |
{(DW){sel11}} & in11[DW-1:0]);
endmodule // oh_mux12
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Double-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common double-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// double-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - add additional RAMs ////
//// - xilinx rams need external tri-state logic ////
//// ////
//// Author(s): ////
//// - Nir Mor, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2005 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_256x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dpram_256x32(
// Generic synchronous double-port RAM interface
clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(16'h0000),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB()
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(16'h0000),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB()
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36_S36 ramb16_s36_s36(
.CLKA(clk_a),
.SSRA(rst_a),
.ADDRA({1'b0, addr_a}),
.DIA(32'h00000000),
.DIPA(4'h0),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a),
.DOPA(),
.CLKB(clk_b),
.SSRB(rst_b),
.ADDRB({1'b0, addr_b}),
.DIB(di_b),
.DIPB(4'h0),
.ENB(ce_b),
.WEB(we_b),
.DOB(),
.DOPB()
);
`else
//
// Generic double-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
//
// RAM read
//
always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
if (rst_a == `OR1200_RST_VALUE)
addr_a_reg <= {aw{1'b0}};
else if (ce_a)
addr_a_reg <= addr_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b && we_b)
mem[addr_b] <= di_b;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int arr[1000005], t = 0; int main() { int n, cnt; cin >> n; map<long long int, int> m; for (int i = 0; i < n; i++) { cin >> arr[i]; } cnt = 1; long long int t = arr[0]; m[t]++; for (int i = 1; i < n; i++) { t = t + arr[i]; m[t]++; cnt = max(cnt, m[t]); } cout << n - cnt << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double PI(acos((long double)-1.0)); struct cpx { long double r, i; cpx() : r(0), i(0) {} cpx(long double a, long double b) : r(a), i(b) {} cpx conj() { return cpx(r, -i); } } u[20], iu[20], a[524288], b[524288]; cpx operator+(const cpx &l, const cpx &r) { return cpx(l.r + r.r, l.i + r.i); } cpx operator-(const cpx &l, const cpx &r) { return cpx(l.r - r.r, l.i - r.i); } cpx operator*(const cpx &l, const cpx &r) { return cpx(l.r * r.r - l.i * r.i, l.r * r.i + r.r * l.i); } void dif(cpx *a, cpx *unt, int l) { int lv, i, j; cpx u, v, w; for (lv = l; lv; --lv) for (i = 0; i < 1 << l; i += 1 << lv) for (j = i, w = {1, 0}; j < i + (1 << lv - 1); ++j, w = w * unt[lv]) { u = a[j]; v = a[j + (1 << lv - 1)]; a[j] = u + v; a[j + (1 << lv - 1)] = (u - v) * w; } } void dit(cpx *a, cpx *unt, int l) { int lv, i, j; cpx u, v, w; for (lv = 1; lv <= l; ++lv) for (i = 0; i < 1 << l; i += 1 << lv) for (j = i, w = {1, 0}; j < i + (1 << lv - 1); ++j, w = w * unt[lv]) { u = a[j]; v = a[j + (1 << lv - 1)] * w; a[j] = u + v; a[j + (1 << lv - 1)] = u - v; } } int main() { int tn, n, x, i, j, l; long long a0; scanf( %d%d , &n, &x); for (tn = 0, l = -1, a0 = 0, i = 0; i < n; ++i) { scanf( %d , &j); if (j < x) { a0 += (long long)(i - l) * (i - l - 1); a[++tn].r = i - l; l = i; } } a0 += (long long)(n - l) * (n - l - 1); a[++tn].r = n - l; for (l = 1; 1 << l < tn; ++l) ; ++l; for (i = 1; i < tn; ++i) b[(1 << l) - i].r = a[i].r; for (i = 1; i <= l; ++i) iu[i] = (u[i] = cpx(cos(2 * PI / (1 << i)), -sin(2 * PI / (1 << i)))).conj(); dif(a, u, l); dif(b, u, l); for (i = 0; i < 1 << l; ++i) a[i] = a[i] * b[i]; dit(a, iu, l); long double t((long double)1.0 / (1 << l)); printf( %lld , a0 / 2); for (i = 1; i < tn && i <= n; ++i) printf( %lld , (long long)(a[i].r * t + 0.1)); for (; i <= n; ++i) printf( 0 ); printf( n ); return 0; }
|
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/06/2013 06:51:42 PM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main (
// Clk Input
input clk_in,
// Data Pins
output reset,
output sclk, // Half the speed of data_clk, a 20,000th the speed of clk
output sdata,
output scmd,
// Power Pins
output vbat,
output vdd,
// LED String Data Pins
output status_led,
output light_clk,
output light_data
);
// GPIO OUT MAP
// 0 - VDD
// 1 - VBAT
// 2 - RESET
// 3 - SCLK
// 4 - SDATA
// 5 - SCMD
//wire [31 : 0] gpio;
zynq_1_wrapper cpu();
assign vdd = 0;
assign vbat = 0;
assign reset = 0;
assign sclk = 0;
assign sdata = 0;
assign scmd = 0;
//assign status_led = gpio[6];
assign light_clk = 0;
assign light_data = 0;
assign status_led = 1;
wire clk;
IBUFG clk_buf(.I(clk_in), .O(clk)); // Clock Buffer Conversion
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning....");
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool b[123][123]; int arr[123][123]; int k[123]; int z[123]; int main() { cin.tie(0); ios_base::sync_with_stdio(0); bool valid = 0, flag = 0; pair<int, int> ans1, ans2; int n; cin >> n; string s, t; cin >> s >> t; for (int i = 0; i < s.size(); i++) { if (s[i] != t[i]) { if (b[t[i] - a ][s[i] - a ]) { ans2 = make_pair(arr[t[i] - a ][s[i] - a ] + 1, i + 1); flag = 1; break; } if (!valid) { if (z[t[i] - a ] == 1) { ans1 = make_pair(k[t[i] - a ] + 1, i + 1); valid = 1; } else if (z[s[i] - a ] == 2) { ans1 = make_pair(k[s[i] - a ] + 1, i + 1); valid = 1; } } z[s[i] - a ] = 1; z[t[i] - a ] = 2; k[s[i] - a ] = i; k[t[i] - a ] = i; b[s[i] - a ][t[i] - a ] = 1; arr[s[i] - a ][t[i] - a ] = i; } } int h = 0; for (int i = 0; i < s.size(); i++) { if (s[i] != t[i]) h++; } if (flag) { cout << h - 2 << endl; cout << ans2.first << << ans2.second << endl; } else if (valid) { cout << h - 1 << endl; cout << ans1.first << << ans1.second << endl; } else { cout << h << endl; cout << -1 << << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; const char E = n ; const int N = 1005; const ll mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k, x, dp[2][1024] = {0}; cin >> n >> k >> x; for (int i = 1; i <= n; i++) { int y; cin >> y; dp[1][y]++; } for (int i = 1; i <= k; i++) { int used = 0; for (int j = 0; j <= 1023; j++) { int bit, nbit; bit = i & 1, nbit = i & 1 ^ 1; if (!(dp[bit][j] & 1)) { dp[nbit][j] += (dp[bit][j] >> 1); dp[nbit][j ^ x] += (dp[bit][j] >> 1); } else if (dp[bit][j]) { dp[nbit][j] += (dp[bit][j] >> 1) + (used & 1); dp[nbit][j ^ x] += (dp[bit][j] >> 1) + (used & 1 ^ 1); } used += dp[bit][j]; dp[bit][j] = 0; } } int mx = 0, mn = 1024; for (int i = 0; i <= 1023; i++) { if (dp[k & 1 ^ 1][i]) { mx = max(mx, i); mn = min(mn, i); } } cout << mx << << mn << E; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; int n, k; long long dp[2005][2005][2]; string s; int main() { cin >> n >> k >> s; dp[n][0][0] = 1; dp[n][0][1] = 1; for (int i = n - 1; i >= 0; --i) { for (int j = 0; j <= k; ++j) { for (int eq = 0; eq <= 1; ++eq) { dp[i][j][eq] = (dp[i][j][eq] + dp[i + 1][j][1]) % mod; dp[i][j][eq] = (dp[i][j][eq] + (dp[i + 1][j][0] * (s[i] - a ) % mod)) % mod; if (!eq) { int till = -1; for (int a = 0; i + a < n; ++a) { if (j >= ((a + 1) * (n - (i + a)))) { dp[i][j][eq] += dp[i + a + 1][j - ((a + 1) * (n - (i + a)))][0] * ( z - s[a + i]); dp[i][j][eq] %= mod; till = a + 1; } else { break; } } if (till == -1) till = 0; for (int a = n - 1 - i; a >= till; --a) { if (j >= ((a + 1) * (n - (i + a)))) { dp[i][j][eq] += dp[i + a + 1][j - ((a + 1) * (n - (i + a)))][0] * ( z - s[a + i]); dp[i][j][eq] %= mod; } else break; } } } } } cout << dp[0][k][0] << n ; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub (
clk,
A,
Amax,
out,
CE
);
// parameters
parameter A_DATA_WIDTH = 32;
parameter B_DATA_VALUE = 32'h1;
parameter ADD_OR_SUB_N = 0;
localparam ADDER = 1;
localparam SUBSTRACTER = 0;
// I/O definitions
input clk;
input [(A_DATA_WIDTH-1):0] A;
input [(A_DATA_WIDTH-1):0] Amax;
output [(A_DATA_WIDTH-1):0] out;
input CE;
// registers
reg [(A_DATA_WIDTH-1):0] out = 'b0;
reg [A_DATA_WIDTH:0] out_d = 'b0;
reg [A_DATA_WIDTH:0] out_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d = 'b0;
reg [(A_DATA_WIDTH-1):0] A_d2 = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;
reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve
always @(posedge clk) begin
if ( ADD_OR_SUB_N == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule
|
/* * yaswanth phani kommineni */ #include <bits/stdc++.h> using namespace std; typedef long long int ll; #define endl n ; void solve(){ ll n; cin >> n; n*=2; vector <ll> v(n); map <ll,ll> m; for(ll i=0;i<n;i++){ cin >> v[i]; m[v[i]]++; } sort(v.begin(),v.end()); for(ll i=0;i<n-1;i++){ auto mp = m; auto V = v; vector <pair<ll,ll>> ans; ans.push_back(make_pair(v[n-1],v[i])); mp[v[n-1]]--; mp[v[i]]--; ll cur = v[n-1]; while(true){ while(!V.empty() && !mp[V.back()]){ V.pop_back(); } if(V.empty()) break; ll last = V.back(); mp[last]--; if(!mp[cur-last]){ break; } ans.push_back(make_pair(last,cur-last)); mp[cur-last]--; cur = last; } if((ll)ans.size()==n/2){ cout << YES << endl; cout << ans.front().first + ans.front().second << endl; for(auto x : ans){ cout << x.second << << x.first << endl; } return; } } cout << NO << endl; } int main(){ //freopen( input.txt , r ,stdin); //freopen( output.txt , w ,stdout); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc; tc = 1; cin >> tc; for(int i=1;i<=tc;i++){ solve(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2e5 + 9, MOD = 1e9 + 7; int n; long long arr[maxN], ot[maxN]; long long maxsub(long long *arr, int n) { long long cr = LLONG_MIN / 4, maxi = LLONG_MIN / 4; for (int i = 0; i < n; i++) { cr = max(arr[i], cr + arr[i]); maxi = max(maxi, cr); } return maxi; } long long trr(long long *arr, int sta) { int ct = 0; for (int i = sta, cnd = 1; i + 1 < n; i++, cnd *= -1) { ot[ct++] = abs(arr[i] - arr[i + 1]) * cnd; } return maxsub(ot, ct); } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } cout << max(trr(arr, 0), trr(arr, 1)) << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int gizzly; cin >> gizzly; priority_queue<int> scoreList; for (int i = 1; i < n; i++) { int x; cin >> x; scoreList.push(x); } int candy = 0; while (gizzly <= scoreList.top()) { int opponent = scoreList.top(); scoreList.pop(); opponent -= 1; gizzly += 1; candy += 1; scoreList.push(opponent); } cout << candy << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int f[20]; bool ischange[300000]; int main() { memset(ischange, 0, sizeof ischange); int n; scanf( %d , &n); string a; cin >> a; for (int i = 1; i <= 9; i++) { scanf( %d , &f[i]); } int ff = 0; for (int i = 0; i < a.length(); i++) { if (ff == 1) break; int now = a[i] - 0 ; int change = f[now]; if (change > now) { ff = 1; while (f[a[i] - 0 ] >= a[i] - 0 && i < a.length()) { ischange[i] = 1; i++; } } if (ff == 1) break; } for (int i = 0; i < a.length(); i++) { if (ischange[i]) cout << f[a[i] - 0 ]; else cout << a[i]; } return 0; }
|
//`include "vga.v"
`timescale 10ns/10ns
module vga_export_tb();
// Declare inputs as regs and outputs as wires
reg clk;
reg[0:0] rst;
wire red;
wire green;
wire blue;
wire hsync;
wire vsync;
vga_export DUT(
.CLOCK_50(clk) , // input CLOCK_50_sig
.KEY(rst) , // input [0]:EY[0]] KEY_sig
.VGA_RED(red) , // output VGA_RED_sig
.VGA_GREEN(green) , // output VGA_GREEN_sig
.VGA_BLUE(blue) , // output VGA_BLUE_sig
.VGA_HSYNC(hsync) , // output VGA_HSYNC_sig
.VGA_VSYNC(vsync) // output VGA_VSYNC_sig
);
/*
CLOCK_50,
KEY,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HSYNC,
VGA_VSYNC
input wire CLOCK_50;
input wire [0:0] KEY;
output wire VGA_RED;
output wire VGA_GREEN;
output wire VGA_BLUE;
output wire VGA_HSYNC;
output wire VGA_VSYNC;
*/
// Initialize all variables
initial begin
clk = 1;
rst = 0;
#2
rst = 1;
//#2
//rst = 0;
//#110
//$stop; // Terminate simulation
end
always begin
#1 clk = !clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_LP_V
`define SKY130_FD_SC_LP__A32O_LP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long b; while (cin >> b) { long long ans = 0; long long i; for (i = 1; i * i < b; i++) { if (b % i == 0) ans += 2; } if (i * i == b) ans++; cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; scanf( %d , &q); while (q--) { int n; scanf( %d , &n); int sum = 0, a; for (int i = 0; i < n; ++i) { scanf( %d , &a); sum += a; } printf( %d n , (int)ceil(sum * 1.0 / n)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN(1e3 + 10); int N, M, P[maxN], A[maxN][maxN], C; void dfs(const int u) { C++; for (int v = 1; v <= N; v++) if (A[u][v] && !P[v]) { P[v] = u; dfs(v); } } int main() { cin >> N >> M; if (M != N - 1) { cout << no ; return 0; } for (int i = 0; i < M; i++) { int u, v; cin >> u >> v; A[u][v] = A[v][u] = 1; } P[1] = -1; dfs(1); cout << (C == N ? yes : no ); }
|
`timescale 1ns / 1ps
module MultiState(
input clk,
input rst,
input [5:0] op,
output [2:0] state
);
reg [2:0] tmp;
assign state = tmp;
always@(posedge clk) begin
if (rst == 0) begin
tmp = 3'B000;
end else begin
case (tmp)
3'B000: tmp = 3'B001;
3'B001: begin
if (op[5:3] == 3'B111) begin // j, jal, jr, halt
tmp = 3'B000;
end else begin // others
tmp = 3'B010;
end
end
3'B010: begin
if (op[5:2] == 4'B1101) begin // beq, bltz
tmp = 3'B000;
end else if (op[5:2] == 4'B1100) begin // sw, lw
tmp = 3'B100;
end else begin // others
tmp = 3'B011;
end
end
3'B011: tmp = 3'B000;
3'B100: begin
if (op[0] == 1) begin // lw
tmp = 3'B011;
end else begin
tmp = 3'B000;
end
end
endcase
end
end
endmodule
|
`ifndef _alu
`define _alu
/*`include "rc_adder.v"*/
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero);
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
/*rc_adder #(.N(32)) add0(.a(a), .b(b), .s(add_ab));*/
// overflow occurs (with 2s complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on whether addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (ctl)
4'd2: out <= add_ab; /* add */
4'd0: out <= a & b; /* and */
4'd12: out <= ~(a | b); /* nor */
4'd1: out <= a | b; /* or */
4'd7: out <= {{31{1'b0}}, slt}; /* slt */
4'd6: out <= sub_ab; /* sub */
4'd13: out <= a ^ b; /* xor */
default: out <= 0;
endcase
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e7 + 5; const long long inf = 1e10; const long long mod = 1e9 + 7; long long n; long long a[maxN]; double f[maxN]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; } long long cnt = 0; for (long long i = 1; i <= n; i++) { for (long long j = i + 1; j <= n; j++) if (a[i] > a[j]) cnt++; } f[0] = 0.0; f[1] = 1.0; for (long long i = 2; i <= cnt + 2; i++) { f[i] = f[i - 2] + 4.0; } printf( %.10f , f[cnt]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[300007]; int main() { int n, k; scanf( %d%d , &n, &k); string s; cin >> s; int sum = 1; a[0] = 1; for (int i = (1); i <= (n - 1); ++i) { if (sum && s[i] == . ) a[i] = 1; sum += a[i]; if (i >= k) sum -= a[i - k]; } if (a[n - 1]) puts( YES ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int num[N], tot; int main() { int n, a1 = 2, a2 = 1, ans = 1; cin >> n; while (a1 - a2 <= n) { if (n % (a1 - a2) == 0) ans = a1 - a2; a1 *= 4; a2 *= 2; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long aa; bool bb; char ch; long long scan() { while (ch = getchar(), (ch < 0 || ch > 9 ) && ch != - ) ; ch == - ? (bb = 1, aa = 0) : (bb = 0, aa = ch - 48); while (ch = getchar(), (ch >= 0 && ch <= 9 )) aa = aa * 10 + ch - 48; return (bb ? (-aa) : (aa)); } inline int Min(int u, int v) { return u < v ? u : v; } const int INF = 2147483647; int len_str; char s[100000], str[100000]; int len[100000]; int pos[100000]; int g[100000][30] = {}; int fail[100000] = {}, sz = 0; int K[100000], Q; int n; int ans[100000]; int set_num = 0, num[100000]; set<int> Set[100000]; queue<int> q; struct E { int to, next; } e[100000]; int last[100000] = {}, tot = 0; void add(int u, int v) { e[++tot].next = last[u]; last[u] = tot; e[tot].to = v; } void ins(int p) { int i, u; u = 0; for (i = 0; i < len[p]; ++i) { s[i] = s[i] - a ; if (!g[u][s[i]]) { g[u][s[i]] = ++sz; } u = g[u][s[i]]; } pos[u] = p; } void build_ac() { int i, u, v; for (i = 0; i < 26; ++i) if (g[0][i]) q.push(g[0][i]); while (!q.empty()) { u = q.front(); q.pop(); for (i = 0; i < 26; ++i) { if (g[u][i]) { v = g[u][i]; q.push(v); fail[v] = g[fail[u]][i]; } else if (u) g[u][i] = g[fail[u]][i]; } } } void build_tree() { for (int i = 1; i <= sz; ++i) add(fail[i], i); } void dfs(int u) { int max_node = u; for (int i = last[u]; i; i = e[i].next) { dfs(e[i].to); if (Set[num[e[i].to]].size() > Set[num[max_node]].size()) max_node = e[i].to; } set<int>::iterator j; for (int i = last[u]; i; i = e[i].next) { if (e[i].to == max_node) continue; for (j = Set[num[e[i].to]].begin(); j != Set[num[e[i].to]].end(); j++) Set[num[max_node]].insert(*j); } if (max_node != u) { for (j = Set[num[u]].begin(); j != Set[num[u]].end(); j++) Set[num[max_node]].insert(*j); num[u] = num[max_node]; } if (pos[u]) { vector<int> p; for (j = Set[num[u]].begin(); j != Set[num[u]].end(); j++) p.push_back(*j); int tmp = INF; for (int k = K[pos[u]], h = k - 1; h < p.size(); ++h) tmp = Min(tmp, p[h] - p[h - k + 1]); if (tmp == INF) ans[pos[u]] = -1; else ans[pos[u]] = tmp + len[pos[u]]; } } int main() { scanf( %s , str); len_str = strlen(str); scanf( %d , &Q); for (int i = 1; i <= Q; ++i) { scanf( %d , &K[i]); scanf( %s , s); len[i] = strlen(s); ins(i); } build_ac(); build_tree(); int u = 0; for (int i = 0; i < len_str; ++i) { u = g[u][str[i] - a ]; if (!num[u]) num[u] = ++set_num; Set[num[u]].insert(i); } dfs(0); for (int i = 1; i <= Q; ++i) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n; cin >> n; string s = <3 ; for (int i = 0; i < n; i++) { string a; cin >> a; s += a; s += <3 ; } string b; cin >> b; long long int j = 0; for (int i = 0; i < b.size(); i++) { if (b[i] == s[j]) j++; } if (j >= s.size()) { cout << yes ; } else { cout << no ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
|
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