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`timescale 1ns / 100ps
// UART Protocol Layer
module QMFIR_uart_if (/*AUTOARG*/
// Outputs
uart_dout, uart_addr, uart_mem_we, uart_mem_re, reg_we, uart_tx,
// Inputs
uart_mem_i, uart_reg_i, clk, arst_n, uart_rx
);
output [31:0] uart_dout;
output [13:0] uart_addr;
output uart_mem_we;
output uart_mem_re;
output reg_we;
output uart_tx;
input [23:0] uart_mem_i;
input [23:0] uart_reg_i;
input clk;
input arst_n;
input uart_rx;
reg [15:0] cmd;
reg [31:0] uart_dout;
parameter stIdle = 0;
parameter stCmd1 = 1;
parameter stCmd2 = 2;
parameter stData1 = 3;
parameter stData2 = 4;
parameter stData3 = 5;
parameter stData4 = 6;
parameter stWr = 7;
parameter stRd = 8;
reg [3:0] state;
reg [7:0] din_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout_o; // From uart_ of sasc_top.v
wire empty_o; // From uart_ of sasc_top.v
wire full_o; // From uart_ of sasc_top.v
wire sio_ce; // From baud_ of sasc_brg.v
wire sio_ce_x4; // From baud_ of sasc_brg.v
// End of automatics
wire cmdRd;
wire cmdMem;
reg re_i;
reg we_i;
sasc_top uart_ (// Outputs
.txd_o (uart_tx),
.rts_o (),
// Inputs
.rxd_i (uart_rx),
.cts_i (1'b0),
.rst_n (arst_n),
/*AUTOINST*/
// Outputs
.dout_o (dout_o[7:0]),
.full_o (full_o),
.empty_o (empty_o),
// Inputs
.clk (clk),
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
.din_i (din_i[7:0]),
.re_i (re_i),
.we_i (we_i));
sasc_brg baud_ (/*AUTOINST*/
// Outputs
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
// Inputs
.clk (clk),
.arst_n (arst_n));
always @ (posedge clk or negedge arst_n)
if (~arst_n)
state <= stIdle;
else
case (state)
stIdle : if (~empty_o) state <= stCmd1;
stCmd1 : if (~empty_o) state <= stCmd2;
stCmd2 : if (cmdRd) state <= stRd; // read
else if (~empty_o) state <= stData1; // write
stData1: if (cmdRd) state <= stData2; // read
else if (~empty_o) state <= stData2; // write
stData2: if (cmdRd) state <= stData3; // read
else if (~empty_o) state <= stData3; // write
stData3: if (cmdRd) state <= stData4; // read done
else if (~empty_o) state <= stData4; //write
stData4: if (cmdRd) state <= stIdle;
else state <= stWr; // write commit
stWr: state <= stIdle;
stRd: state <= stData1;
endcase // case(state)
// --------------- Command Word Capture ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n) cmd <= 0;
else
begin
if (state==stIdle) cmd[15:8] <= dout_o[7:0];
if (state==stCmd1) cmd[7:0] <= dout_o[7:0];
end
assign cmdRd = ~cmd[15];
assign cmdMem = cmd[14];
assign uart_addr = cmd[13:0];
// --------------- Write Command ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n)
uart_dout <= 0;
else
begin
if (state==stCmd2 & ~cmdRd) uart_dout[31:24] <= dout_o[7:0];
if (state==stData1 & ~cmdRd) uart_dout[23:16] <= dout_o[7:0];
if (state==stData2 & ~cmdRd) uart_dout[15:8] <= dout_o[7:0];
if (state==stData3 & ~cmdRd) uart_dout[7:0] <= dout_o[7:0];
end
always @ (/*AS*/cmdRd or empty_o or state)
case (state)
stIdle : re_i = ~empty_o;
stCmd1 : re_i = ~empty_o;
stCmd2 : re_i = ~empty_o & ~cmdRd;
stData1: re_i = ~empty_o & ~cmdRd;
stData2: re_i = ~empty_o & ~cmdRd;
stData3: re_i = ~empty_o & ~cmdRd;
default: re_i = 0;
endcase // case(state)
assign uart_mem_we = (state==stWr) & cmdMem;
assign reg_we = (state==stWr) & ~cmdMem;
// --------------- Read Command ----------------- //
always @ (/*AS*/cmdMem or state or uart_mem_i or uart_reg_i)
case (state)
stData2: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
stData3: din_i[7:0] = cmdMem ? uart_mem_i[15:8] : uart_reg_i[15:8];
stData4: din_i[7:0] = cmdMem ? uart_mem_i[7:0] : uart_reg_i[7:0];
default: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
endcase // case(state)
always @ (/*AS*/cmdRd or state)
case (state)
stData1: we_i = cmdRd;
stData2: we_i = cmdRd;
stData3: we_i = cmdRd;
stData4: we_i = cmdRd;
default: we_i = 0;
endcase // case(state)
assign uart_mem_re = (state==stRd);
endmodule // QMFIR_uart_if
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#include <bits/stdc++.h> using namespace std; int n, m, v; pair<int, int> p[10]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( n ); for (int j = 1; j <= m; ++j) { char ch = getchar(); if (ch == * ) p[++v] = make_pair(i, j); } } if (p[1].first == p[2].first && p[1].second == p[3].second) printf( %d %d , p[3].first, p[2].second); else if (p[1].first == p[3].first && p[1].second == p[2].second) printf( %d %d , p[2].first, p[3].second); else if (p[2].first == p[1].first && p[2].second == p[3].second) printf( %d %d , p[3].first, p[1].second); else if (p[2].first == p[3].first && p[2].second == p[1].second) printf( %d %d , p[1].first, p[3].second); else if (p[3].first == p[1].first && p[3].second == p[2].second) printf( %d %d , p[2].first, p[1].second); else if (p[3].first == p[2].first && p[3].second == p[1].second) printf( %d %d , p[1].first, p[2].second); return 0; }
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#include <bits/stdc++.h> using namespace std; int dp[1024], n, m, c1, c2, c3, c4, an[1024], am[1024]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> c1 >> c2 >> c3 >> c4; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> an[i]; for (int i = 0; i < m; ++i) cin >> am[i]; int mini = INT_MAX; mini = min(mini, c4); mini = min(mini, 2 * c3); int s1 = 0; for (int i = 0; i < n; ++i) { s1 += min(c1 * an[i], c2); } mini = min(mini, c3 + s1); int s2 = 0; for (int i = 0; i < m; ++i) { s2 += min(c1 * am[i], c2); } mini = min(mini, c3 + s2); mini = min(mini, s1 + s2); cout << mini << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__bufinv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; map<string, string> mp; set<string> st; int n; char in[30]; string read() { scanf( %s , in); return (string)in; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i += 1) { string a = read(); string b = read(); if (st.find(b) != st.end()) { continue; } st.insert(a); if (mp.find(a) != mp.end()) { mp[b] = mp[a]; mp.erase(a); continue; } mp[b] = a; } printf( %d n , mp.size()); for (auto x : mp) { if (x.second == _ ) { continue; } printf( %s %s n , x.second.c_str(), x.first.c_str()); } }
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///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_7_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_7_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_7_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_7_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
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#include <bits/stdc++.h> using namespace std; const int block_size = 320; const long long mod = 1e9 + 7; const long long inf = 1e9 + 7; const long double eps = 1e-9; const double PI = atan(1) * 4; template <typename T> inline int sign(const T &a) { if (a < 0) return -1; if (a > 0) return 1; return 0; } string to_string(string s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T, typename S> inline bool upmin(T &a, const S &b) { return a > b ? a = b, 1 : 0; } template <typename T, typename S> inline bool upmax(T &a, const S &b) { return a < b ? a = b, 1 : 0; } template <typename T> inline void in(T &x) { x = 0; T f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } long long twop(int x) { return 1LL << x; } template <typename A, typename B> inline void in(A &x, B &y) { in(x); in(y); } template <typename A, typename B, typename C> inline void in(A &x, B &y, C &z) { in(x); in(y); in(z); } template <typename A, typename B, typename C, typename D> inline void in(A &x, B &y, C &z, D &d) { in(x); in(y); in(z); in(d); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } namespace SOLVE { int n, q; string s; int nxt[100010][26]; int dp[255][255][255]; vector<int> word[3]; void solve(int i, int j, int k) { dp[i][j][k] = inf; if (i and dp[i - 1][j][k] <= n) upmin(dp[i][j][k], nxt[dp[i - 1][j][k]][word[0][i]]); if (j and dp[i][j - 1][k] <= n) upmin(dp[i][j][k], nxt[dp[i][j - 1][k]][word[1][j]]); if (k and dp[i][j][k - 1] <= n) upmin(dp[i][j][k], nxt[dp[i][j][k - 1]][word[2][k]]); } void main() { cin >> n >> q >> s; for (long long i = 0; i < n; i++) s[i] -= a ; s = + s; for (long long i = 0; i < 26; i++) nxt[n][i] = inf; for (long long i = n - 1; i >= 0; i--) { for (long long j = 0; j < 26; j++) nxt[i][j] = nxt[i + 1][j]; nxt[i][s[i + 1]] = i + 1; } for (long long i = 0; i < 3; i++) word[i].push_back(0); dp[0][0][0] = 0; while (q--) { string op; cin >> op; int id; cin >> id; id--; if (op == + ) { string sss; cin >> sss; int ch = sss[0] - a ; word[id].push_back(ch); if (id == 0) { for (long long b = 0; b < ((int)word[1].size()); b++) { for (long long c = 0; c < ((int)word[2].size()); c++) { solve(((int)word[0].size()) - 1, b, c); } } } if (id == 1) { for (long long b = 0; b < ((int)word[0].size()); b++) { for (long long c = 0; c < ((int)word[2].size()); c++) { solve(b, ((int)word[1].size()) - 1, c); } } } if (id == 2) { for (long long b = 0; b < ((int)word[0].size()); b++) { for (long long c = 0; c < ((int)word[1].size()); c++) { solve(b, c, ((int)word[2].size()) - 1); } } } } else { word[id].pop_back(); } cout << ((dp[((int)word[0].size()) - 1][((int)word[1].size()) - 1] [((int)word[2].size()) - 1] <= n) ? YES : NO ) << endl; } } } // namespace SOLVE signed main() { int t; t = 1; while (t--) { SOLVE::main(); } return 0; }
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// $Id: c_credit_tracker.v 2061 2010-05-31 05:10:37Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// module for tracking available credit in a buffer
module c_credit_tracker
(clk, reset, debit, credit, free, errors);
`include "c_functions.v"
`include "c_constants.v"
// total number of credits available
parameter num_credits = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
// width required to select an individual credit
localparam credit_idx_width = clogb(num_credits);
// width required to represent full range of credit count (0..num_credits)
localparam true_idx_width = clogb(num_credits+1);
input clk;
input reset;
// inputs for subtracting and adding credits
input debit;
input credit;
// at least one credit available?
output free;
wire free;
// internal error condition encountered
output [0:1] errors;
wire [0:1] errors;
wire set_cred, reset_cred;
wire cred_s, cred_q;
assign cred_s = set_cred | (cred_q & ~reset_cred);
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
credq
(.clk(clk),
.reset(reset),
.d(cred_s),
.q(cred_q));
assign free = cred_q;
wire incr;
assign incr = credit & ~debit;
wire decr;
assign decr = debit & ~credit;
wire error_underflow;
wire error_overflow;
wire [0:true_idx_width-1] true_count;
generate
// if we only have a single credit, we don't need explicit credit counter
if(num_credits == 1)
begin
assign set_cred = incr;
assign reset_cred = decr;
assign error_underflow = ~cred_q & debit;
assign error_overflow = cred_q & credit;
assign true_count = cred_q;
end
// if we have more than one credit, we need an extra counter to keep track
else
begin
wire [0:credit_idx_width-1] cred_count_q;
wire cred_count_zero;
assign cred_count_zero = ~|cred_count_q;
wire incr_count;
assign incr_count = incr & ~(~cred_q & cred_count_zero);
wire decr_count;
assign decr_count = decr & ~(cred_q & cred_count_zero);
wire [0:credit_idx_width-1] cred_count_s;
assign cred_count_s
= (incr | decr) ?
((cred_count_q - decr_count) + incr_count) :
cred_count_q;
c_dff
#(.width(credit_idx_width),
.reset_type(reset_type),
.reset_value(num_credits-1))
cred_countq
(.clk(clk),
.reset(reset),
.d(cred_count_s),
.q(cred_count_q));
assign set_cred = incr & ~cred_q & cred_count_zero;
assign reset_cred = decr & cred_q & cred_count_zero;
assign error_underflow
= !cred_q && (cred_count_q == 0) && debit;
assign error_overflow
= cred_q && (cred_count_q == (num_credits - 1)) && credit;
assign true_count = cred_count_q + cred_q;
end
// synopsys translate_off
if(num_credits == 0)
begin
initial
begin
$display({"ERROR: Credit tracker module %m requires at least ",
"one credit."});
$stop;
end
end
// synopsys translate_on
endgenerate
assign errors = {error_underflow, error_overflow};
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[100005]; int st[100005][22]; bool mark[100005]; long long dp[100005]; int n, k; void build() { int i, j; for (j = 1; 1 << j <= n; j++) { for (i = 0; i + (1 << j) <= n; i++) { st[i][j] = min(st[i][j - 1], st[i + (1 << (j - 1))][j - 1]); } } } int getMin(int l, int r) { int num = r - l + 1, k = 0; while (num >= 2) num /= 2, k++; return min(st[l][k], st[r - (1 << k) + 1][k]); } long long f(int i) { if (i >= n) return 0; if (mark[i]) return dp[i]; mark[i] = 1; long long ret = getMin(i - k + 1, i) + f(i + k); ret = max(ret, f(i + 1)); return dp[i] = ret; } int main() { scanf( %d %d , &n, &k); long long sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &st[i][0]); sum += st[i][0]; } build(); printf( %lld n , sum - f(k - 1)); return 0; }
|
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* UART interface
*/
input wire rxd,
output wire txd,
/*
* Status
*/
output wire tx_busy,
output wire rx_busy,
output wire rx_overrun_error,
output wire rx_frame_error,
/*
* Configuration
*/
input wire [1:0] uart_bits,
input wire [1:0] uart_parity,
input wire [1:0] uart_stopbit,
input wire [15:0] prescale
);
// Decoder
reg [3:0] uart_data_width;
always @(uart_bits or uart_parity) begin
case(uart_bits)
2'b00: uart_data_width = 4'd8;
2'b01: uart_data_width = 4'd7;
2'b10: uart_data_width = 4'd6;
2'b11: uart_data_width = 4'd5;
default: uart_data_width = 4'd8;
endcase
if(uart_parity) uart_data_width = uart_data_width + 1;
end
uart_tx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
// output
.txd(txd),
// status
.busy(tx_busy),
// configuration
.uart_bits(uart_bits),
.uart_data_width(uart_data_width),
.uart_parity(uart_parity),
.uart_stopbit(uart_stopbit),
.prescale(prescale)
);
uart_rx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
.clk(clk),
.rst(rst),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
// input
.rxd(rxd),
// status
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
// configuration
.uart_data_width(uart_data_width),
.uart_parity(uart_parity),
.uart_stopbit(uart_stopbit),
.prescale(prescale)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int mv = pow(10, 5) + 1; void pfn() { char x[mv], y[mv]; cin >> x >> y; int ly = strlen(y) - 1, i; i = ly; while (i >= 0 && y[i] != 1 ) i--; int lx = strlen(x) - 1 - ly + i; i = lx; while (i >= 0 && x[i] != 1 ) i--; cout << lx - i << n ; } int main() { int t; cin >> t; while (t--) pfn(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int kd[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int n, i, j; char s[666666]; int cnt[42][42][42]; int mx, ad, am, ay; int main() { scanf( %s , s); int n = strlen(s); memset(cnt, 0, sizeof(cnt)); for (i = 0; i + 9 < n; i++) { if (s[i + 2] != - || s[i + 5] != - ) continue; int ok = 1; for (j = 0; j < 10; j++) if (j != 2 && j != 5 && s[i + j] == - ) ok = 0; if (!ok) continue; int dd = (s[i] - 48) * 10 + (s[i + 1] - 48); int mm = (s[i + 3] - 48) * 10 + (s[i + 4] - 48); if (s[i + 6] != 2 || s[i + 7] != 0 || s[i + 8] != 1 ) continue; int yy = s[i + 9] - 48; if (yy < 3 || yy > 5) continue; if (mm < 1 || mm > 12) continue; if (dd < 1 || dd > kd[mm]) continue; cnt[dd][mm][yy]++; if (cnt[dd][mm][yy] > mx) { mx = cnt[dd][mm][yy]; ad = dd; am = mm; ay = yy; } } printf( %d%d-%d%d-%d n , ad / 10, ad % 10, am / 10, am % 10, 2010 + ay); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XNOR2_PP_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_2_V
`define SKY130_FD_SC_LP__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_2_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T inline SQR(const T &a) { return a * a; } long long MOD = 1000000007LL; long long mypow(long long a, long long p) { if (p == 0) return 1LL; long long ans = mypow(a, p / 2); ans *= ans; ans %= MOD; if (p & 1) return (a * ans) % MOD; return ans; } int n, m, k; int dp[1005][1005]; int solve(int pLeft, int sd) { if (pLeft == 0) return 1; if (sd <= 0) return 0; int &val = dp[pLeft][sd]; if (val != -1) return val; long long aux = 0; for (int i = 1; i < sd - 1; ++i) { aux += 1ll * (sd - 1 - i) * solve(pLeft - 1, i); } return val = aux % MOD; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; int MAXS = max(n, m) + 1; for (int i = 0; i < k + 1; ++i) for (int j = 0; j < MAXS; ++j) dp[i][j] = -1; cout << (1ll * solve(k, n) * solve(k, m)) % MOD << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_TB_V
`define SKY130_FD_SC_HD__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O32A_FUNCTIONAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_FUNCTIONAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module foo
#(parameter type bar = logic)
(output int bar_size);
localparam baz = $bits(bar);
assign bar_size = baz;
endmodule
module foo_wrapper
#(parameter bar_bits = 9)
(output int bar_size);
foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size));
endmodule
module t();
logic [7:0] qux1;
int bar_size1;
foo #(.bar (logic [ $bits(qux1) - 1 : 0]))
foo_inst1 (.bar_size (bar_size1));
logic [7:0] qux2;
int bar_size2;
foo #(.bar (logic [ $bits(qux2) - 1 : 0]))
foo_inst2 (.bar_size (bar_size2));
logic [7:0] qux3;
int bar_size3;
foo #(.bar (logic [ $bits(qux3) - 1 : 0]))
foo_inst3 (.bar_size (bar_size3));
localparam bar_bits = 13;
int bar_size_wrapper;
foo_wrapper #(.bar_bits (bar_bits))
foo_wrapper_inst (.bar_size (bar_size_wrapper));
initial begin
if ($bits(qux1) != foo_inst1.baz) begin
$display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)",
$bits(qux1), foo_inst1.baz);
$stop();
end
if ($bits(qux2) != foo_inst2.baz) begin
$display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)",
$bits(qux2), foo_inst2.baz);
$stop();
end
if ($bits(qux3) != foo_inst3.baz) begin
$display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)",
$bits(qux3), foo_inst3.baz);
$stop();
end
if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin
$display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)",
bar_bits, foo_wrapper_inst.foo_inst.baz);
$stop();
end
if (bar_size1 != $bits(qux1)) begin
$display("%m: bar_size1 != bits of qux1 (%0d, %0d)",
bar_size1, $bits(qux1));
$stop();
end
if (bar_size2 != $bits(qux2)) begin
$display("%m: bar_size2 != bits of qux2 (%0d, %0d)",
bar_size2, $bits(qux2));
$stop();
end
if (bar_size3 != $bits(qux3)) begin
$display("%m: bar_size3 != bits of qux3 (%0d, %0d)",
bar_size3, $bits(qux3));
$stop();
end
if (bar_size_wrapper != bar_bits) begin
$display("%m: bar_size_wrapper != bar_bits (%0d, %0d)",
bar_size_wrapper, bar_bits);
$stop();
end
end
genvar m;
generate
for (m = 1; m <= 8; m+=1) begin : gen_m
initial begin
if (m != foo_inst.baz) begin
$display("%m: m != bits of foo_inst.baz (%0d, %0d)",
m, foo_inst.baz);
$stop();
end
end
foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ());
end
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e7; const long long MOD = 1e9 + 7; const long long mod = 998244353; const int MAX_N = 1e5 + 5; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } vector<int> adj[1005]; int tsz[1005]; bool ga[1005]; void dfs(int u, int v = -1) { tsz[u] = 1; if (adj[u].size() == 1) ga[u] = true; for (auto xd : adj[u]) { if (xd == v) continue; dfs(xd, u); tsz[u] += tsz[xd]; } } int main() { int tc; cin >> tc; while (tc--) { for (int i = 0; i < 1005; i++) { adj[i].clear(); tsz[i] = 0; } int n, x; cin >> n >> x; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } dfs(x); if (adj[x].size() <= 1) { cout << Ayush << endl; continue; } long long p = tsz[x] - 1; if (p % 2 == 0) cout << Ashish << endl; else cout << Ayush << endl; } }
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: io_mux.v
//
// *Module Description:
// I/O mux for port function selection.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module io_mux (
// Function A (typically GPIO)
a_din,
a_dout,
a_dout_en,
// Function B (Timer A, ...)
b_din,
b_dout,
b_dout_en,
// IO Cell
io_din,
io_dout,
io_dout_en,
// Function selection (0=A, 1=B)
sel
);
// PARAMETERs
//============
parameter WIDTH = 8;
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input [WIDTH-1:0] a_dout;
input [WIDTH-1:0] a_dout_en;
// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input [WIDTH-1:0] b_dout;
input [WIDTH-1:0] b_dout_en;
// IO Cell
//===============================
input [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;
// Function selection (0=A, 1=B)
//===============================
input [WIDTH-1:0] sel;
//=============================================================================
// 1) I/O FUNCTION SELECTION MUX
//=============================================================================
function [WIDTH-1:0] mux (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input [WIDTH-1:0] SEL
);
integer i;
begin
mux = {WIDTH{1'b0}};
for (i = 0; i < WIDTH; i = i + 1)
mux[i] = sel[i] ? B[i] : A[i];
end
endfunction
assign a_din = mux( io_din, {WIDTH{1'b0}}, sel);
assign b_din = mux({WIDTH{1'b0}}, io_din, sel);
assign io_dout = mux( a_dout, b_dout, sel);
assign io_dout_en = mux( a_dout_en, b_dout_en, sel);
endmodule // io_mux
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T& x) { x = 0; char c; int sign = 1; do { c = getchar(); if (c == - ) sign = -1; } while (c < 0 || c > 9 ); do { x = x * 10 + c - 0 ; c = getchar(); } while (c <= 9 && c >= 0 ); x *= sign; } const int N = 101, inf = 1e6; int t, n, cnt, a[N], k[N]; bool vis[inf << 1]; bool check(int x) { for (register int i = 1; i <= n; ++i) if (vis[a[i] + x]) return 0; for (register int i = 1; i <= n; ++i) vis[a[i] + x] = 1; return 1; } inline int solve() { cnt = 0; memset(vis, 0, sizeof vis); read(n); for (register int i = 1; i <= n; ++i) read(a[i]); sort(a + 1, a + n + 1); for (register int i = 2; i <= n; ++i) if (a[i] == a[i - 1]) return puts( NO ), 0; for (register int i = 1; i <= inf; ++i) if (cnt == n) break; else if (check(i)) k[++cnt] = i; if (cnt == n) { puts( YES ); for (register int i = 1; i <= n; ++i) printf( %d , k[i]); printf( n ); } else puts( NO ); return 0; } int main() { read(t); while (t--) solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND3B_BEHAVIORAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_BEHAVIORAL_V
|
/*
* File: imx_cbu.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description: Core Bridge Unit - ÇŽÓcoreµÄimxºÍƬÉÏ»¥Á¬ÐÒé
* IMXºÍWBµÄÒìͬ
1£¬IMXÎÞÐèslaveʹÓÃrtyÐźţ¬masterÔÚslaveûÓзµ»ØackÇ°±£³ÖÇëÇó
2£¬IMXÐèÒª·µ»Øµ±Ç°ÇëÇóµÄaddrÐźÅ
3£¬IMXµÄΨһÍê³ÉÐźÅΪack£¬errÔÚackΪÓÐЧʱֵ²ÅÓÐÒâÒå
* Task.I:
verification environment for complex imx-cbu-wb interaction
1, IMXÁ¬ÐøÇëÇóÇé¿ö
2, ²»Í¬×ÜÏßʱ¿ÌÈ¡ÏûIMXÇëÇóµÄÇé¿ö£¬È¡Ïûºó»Ö¸´ÓÐЧ»òÐÂÇëÇóÓÐЧµÄÇé¿ö
3, ÊÇ·ñ´æÔÚIMXÇëÇóÒ»Ö±ÓÐЧ£¬µ«µØÖ··¢Éú±ä»¯µÄÇé¿ö£¿´¦ÀíÆ÷ÄÚºËÓ¦¸Ã²»»á³öÏÖ£¬ÇëÇóÈ¡Ïûʱ±ØÐëÓÐÒ»ÅÄ¿ÕÏÐ
* Task.II:
¿çʱÖÓÓòÖ§³Ö
Burst´«ÊäÖ§³Ö
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module imx_cbu(
clk, rst,
wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o, wb_cti_o, wb_bte_o,
wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
cbu_dat_i, cbu_adr_i, cbu_rqt_i, cbu_we_i, cbu_sel_i,
cbu_ack_o, cbu_dat_o, cbu_err_o, cbu_adr_o
);
parameter dw = 32;
parameter aw = 32;
// currently no burst support
`define WB_CTI 3'b000
`define WB_BTE 2'b00
//
// core clock, reset and clock control
//
input clk; // core clock
input rst; // core reset
//
// core-bridge unit interface
//
input [aw-1:0] cbu_adr_i; // core request address
input [dw-1:0] cbu_dat_i; // core request data
input cbu_rqt_i; // core request valid
input cbu_we_i; // core request w/r flag
input [3:0] cbu_sel_i; // core request byte selects
output cbu_ack_o; // bus response valid(ack)
output cbu_err_o; // bus response error
output [dw-1:0] cbu_dat_o; // bus response data
output [aw-1:0] cbu_adr_o; // bus response address
//
// WISHBONE interface
//
input wb_ack_i; // normal termination
input wb_err_i; // termination with error
input wb_rty_i; // termination with retry
input [dw-1:0] wb_dat_i; // data input
output wb_cyc_o; // cycle valid output
output [aw-1:0] wb_adr_o; // address output
output wb_stb_o; // strobe output
output wb_we_o; // indicates write/read transfer
output [3:0] wb_sel_o; // byte select output
output [dw-1:0] wb_dat_o; // data output
output [2:0] wb_cti_o; // cycle type identifier
output [1:0] wb_bte_o; // burst type extension
//
// reg & wires
//
reg wb_cyc_o;
reg [aw-1:0] wb_adr_o;
reg wb_stb_o;
reg wb_we_o;
reg [3:0] wb_sel_o;
reg [dw-1:0] wb_dat_o;
reg [2:0] wb_cti_o;
reg [1:0] wb_bte_o;
reg [dw-1:0] cbu_dat_o;
reg cbu_ack_o;
reg cbu_err_o;
reg [aw-1:0] cbu_adr_o;
//
// logic implementation
//
// registered request
always @(posedge clk or posedge rst) begin
if (rst) begin
wb_cyc_o <= #1 1'b0;
wb_stb_o <= #1 1'b0;
wb_dat_o <= #1 32'd0;
wb_adr_o <= #1 32'd0;
wb_sel_o <= #1 4'd0;
wb_we_o <= #1 1'd0;
wb_cti_o <= #1 3'd0;
wb_bte_o <= #1 2'd0;
end
else begin
if (cbu_rqt_i)
begin
wb_cyc_o <= #1 cbu_rqt_i;
wb_stb_o <= #1 cbu_rqt_i;
wb_dat_o <= #1 cbu_dat_i;
wb_adr_o <= #1 cbu_adr_i;
wb_sel_o <= #1 cbu_sel_i;
wb_we_o <= #1 cbu_we_i;
wb_cti_o <= #1 `WB_CTI;
wb_bte_o <= #1 `WB_BTE;
end
else begin // when core cancel bus request
wb_cyc_o <= #1 1'b0;
wb_stb_o <= #1 1'b0;
wb_dat_o <= #1 32'd0;
wb_adr_o <= #1 32'd0;
wb_sel_o <= #1 4'd0;
wb_we_o <= #1 1'd0;
wb_cti_o <= #1 3'd0;
wb_bte_o <= #1 2'd0;
end
end
end
// registered request
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_ack_o <= #1 1'b0;
cbu_err_o <= #1 1'b0;
end
else begin
if (cbu_rqt_i)
begin
cbu_ack_o <= #1 wb_ack_i;
cbu_err_o <= #1 wb_err_i;
end
else begin
cbu_ack_o <= #1 1'b0;
cbu_err_o <= #1 1'b0;
end
end
end
// special case for IMX
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_dat_o <= #1 32'd0;
end
else begin
cbu_dat_o <= #1 wb_dat_i;
end
end
// special case for IMX
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_adr_o <= #1 32'd0;
end
else begin
cbu_adr_o <= #1 cbu_adr_i;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100100; int n, m; int was[MAXN]; vector<int> g[MAXN]; bool was2[3][MAXN]; bool dfs(int v, int col = 1) { was[v] = col; for (int i = 0; i < (int)g[v].size(); ++i) { if (!was[g[v][i]]) { if (dfs(g[v][i], 3 - col)) { return true; } } else if (was[v] == was[g[v][i]]) return true; } return false; } int dfs2(int v, int col) { was2[col][v] = true; int res = was[v] == col; for (int i = 0; i < (int)g[v].size(); ++i) { if (!was2[col][g[v][i]]) { res += dfs2(g[v][i], col); } } return res; } unsigned long long C(int n, int k) { if (k > n) return 0; unsigned long long res = 1; for (int i = 0; i < k; ++i) res *= n - i; for (int i = 2; i <= k; ++i) res /= i; return res; } int main() { scanf( %d%d , &n, &m); for (int i = 0, a, b; i < m; ++i) { scanf( %d%d , &a, &b); g[a].push_back(b); g[b].push_back(a); } for (int i = 1; i <= n; ++i) { if (!was[i] && dfs(i)) { puts( 0 1 ); return 0; } } unsigned long long one = 0; for (int i = 1; i <= n; ++i) { if (!was2[1][i]) { one += C(dfs2(i, 1), 2); one += C(dfs2(i, 2), 2); } } if (one) { cout << 1 << << one << endl; return 0; } if (m) { cout << 2 << << m * 1ll * (n - 2) << n ; return 0; } cout << 3 << << C(n, 3) << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/03/2015 04:15:25 PM
// Design Name:
// Module Name: source
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "system.vh"
module test_engine_dummy #(parameter Thold = 5)
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire start_strobe_din,
input wire [(2 * `CHANNEL_WIDTH)-1:0] wordA_din,
input wire [(2 * `CHANNEL_WIDTH)-1:0] wordB_din,
// -- outputs ------------------------------------------------ >>>>>
output reg done_strobe_dout,
output reg active_test_engine_dout,
output reg [(2 * `CHANNEL_WIDTH)-1:0] wordC_dout,
output reg [(2 * `CHANNEL_WIDTH)-1:0] wordD_dout
);
reg [63:0] wordC;
reg [63:0] wordD;
integer packet_counter = 0;
event valid_data;
initial
begin
done_strobe_dout = 0;
active_test_engine_dout = 0;
wordC_dout = 0;
wordD_dout = 0;
end
always
@(posedge start_strobe_din)
begin
@(posedge clk);
#(Thold);
wordC <= wordB_din;
wordD <= wordA_din;
active_test_engine_dout <= 1;
repeat(16)
@(posedge clk);
#(Thold);
-> valid_data;
end
always
begin
@(valid_data);
active_test_engine_dout <= 0;
done_strobe_dout <= 1;
wordC_dout <= wordC;
wordD_dout <= wordD;
@(posedge clk);
#(Thold);
done_strobe_dout <= 0;
wordC_dout <= {64{1'bx}};
wordD_dout <= {64{1'bx}};
packet_counter = packet_counter + 1;
end
endmodule // test_engine_dummy
/* -- Plantilla de instancia ------------------------------------- >>>>>
test_engine_dummy
#(
.Thold(Thold)
)
test_engine_dummy
(
.clk(clk),
// -- inputs ------------------------------------------------- >>>>>
.start_strobe_din(start_strobe_din),
.wordA_din(wordA_din),
.wordB_din(wordB_din),
// -- outputs ------------------------------------------------ >>>>>
.done_strobe_dout(done_strobe_dout),
.active_test_engine_dout(active_test_engine_dout),
.wordC_dout(wordC_dout),
.wordD_dout(wordD_dout)
);
*/
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`ifndef DV1
`define DV1 6
`define FX1_d 3
`define FX1_m 10
`define FX2_d 8
`define FX2_m 2
`define prd 6.25
`endif
`timescale 1ns / 1ps
module clk_gen(
input wire CLKIN,
output wire BUS_CLK,
output wire U1_CLK8,
output wire U2_CLK16,
output wire U2_CLK40,
output wire U2_CLK160,
output wire U2_CLK320,
output wire U2_LOCKED
);
wire U1_CLK0, U1_CLK0_BUF, U1_CLKDV, U1_CLKDV_BUF;
wire U2_CLKDV_BUF, U2_CLK0_BUF, U2_CLK2X_BUF, U2_CLKFX_BUF;
assign BUS_CLK = U1_CLK0_BUF;
assign U2_CLK40 = U2_CLKFX_BUF;
assign U2_CLK16 = U2_CLKDV_BUF;
assign U2_CLK160 = U2_CLK0_BUF;
assign U2_CLK320 = U2_CLK2X_BUF;
assign U1_CLK8 = U1_CLKDV_BUF;
BUFG CLKFB_BUFG_INST (.I(U1_CLK0), .O(U1_CLK0_BUF));
BUFG CLKDV_BUFG_INST (.I(U1_CLKDV), .O(U1_CLKDV_BUF));
wire U1_CLKFX;
wire U1_LOCKED;
DCM #(
.CLKDV_DIVIDE(`DV1), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(`FX1_d), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(`FX1_m), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.833), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_BUS (
.CLKFB(U1_CLK0_BUF),
.CLKIN(CLKIN),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(1'b0),
.CLKDV(U1_CLKDV),
.CLKFX(U1_CLKFX),
.CLKFX180(),
.CLK0(U1_CLK0),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(U1_LOCKED),
.PSDONE(),
.STATUS());
wire U1_CLKFX_BUF, U2_CLKDV;
wire U2_CLK0, U2_CLKFX, U2_CLK2X;
BUFG CLKFX_2_BUFG_INST (.I(U1_CLKFX), .O(U1_CLKFX_BUF));
BUFG CLKDV_2_BUFG_INST (.I(U2_CLKDV), .O(U2_CLKDV_BUF));
BUFG CLKFB_2_BUFG_INST (.I(U2_CLK0), .O(U2_CLK0_BUF));
BUFG CLKFX2_2_BUFG_INST (.I(U2_CLKFX), .O(U2_CLKFX_BUF));
BUFG U2_CLK2X_INST (.I(U2_CLK2X), .O(U2_CLK2X_BUF));
DCM #(
.CLKDV_DIVIDE(10), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(`FX2_d), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(`FX2_m), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(`prd), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_U2 (
.DSSEN(1'b0),
.CLK0(U2_CLK0), // 0 degree DCM_SP CLK output
.CLK180(), // 180 degree DCM_SP CLK output
.CLK270(), // 270 degree DCM_SP CLK output
.CLK2X(U2_CLK2X), // 2X DCM_SP CLK output
.CLK2X180(), // 2X, 180 degree DCM_SP CLK out
.CLK90(), // 90 degree DCM_SP CLK output
.CLKDV(U2_CLKDV), // DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(U2_CLKFX), // DCM_SP CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(U2_LOCKED), // DCM_SP LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM_SP status bits output
.CLKFB(U2_CLK0_BUF), // DCM_SP clock feedback
.CLKIN(U1_CLKFX_BUF), // Clock input (from IBUFG, BUFG or DCM_SP)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(!U1_LOCKED)// // DCM_SP asynchronous reset input
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: swrvr_dlib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// DP library
// 2:1 MUX WITH ENCODED SELECT
module dp_mux2es (dout, in0, in1, sel) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
reg [SIZE-1:0] dout ;
always @ (sel or in0 or in1)
begin
case (sel)
1'b1: dout = in1 ;
1'b0: dout = in0;
default:
begin
if (in0 == in1) begin
dout = in0;
end
else
dout = {SIZE{1'bx}};
end
endcase // case(sel)
end
endmodule // dp_mux2es
// ----------------------------------------------------------------------
// 4:1 MUX WITH DECODED SELECTS
module dp_mux4ds (dout, in0, in1, in2, in3,
sel0_l, sel1_l, sel2_l, sel3_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk4 ($one_cold ({sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [3:0] sel = {sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3)
case ({sel3_l,sel2_l,sel1_l,sel0_l})
4'b1110 : dout = in0 ;
4'b1101 : dout = in1 ;
4'b1011 : dout = in2 ;
4'b0111 : dout = in3 ;
4'b1111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux4ds
// ----------------------------------------------------------------------
// 5:1 MUX WITH DECODED SELECTS
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk5 ($one_cold ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [4:0] sel = {sel4_l,sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or sel4_l or
in0 or in1 or in2 or in3 or in4)
case ({sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
5'b11110 : dout = in0 ;
5'b11101 : dout = in1 ;
5'b11011 : dout = in2 ;
5'b10111 : dout = in3 ;
5'b01111 : dout = in4 ;
5'b11111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux5ds
// --------------------------------------------------------------------
// 8:1 MUX WITH DECODED SELECTS
module dp_mux8ds (dout, in0, in1, in2, in3,
in4, in5, in6, in7,
sel0_l, sel1_l, sel2_l, sel3_l,
sel4_l, sel5_l, sel6_l, sel7_l) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input [SIZE-1:0] in5;
input [SIZE-1:0] in6;
input [SIZE-1:0] in7;
input sel0_l;
input sel1_l;
input sel2_l;
input sel3_l;
input sel4_l;
input sel5_l;
input sel6_l;
input sel7_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk8 ($one_cold ({sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}));
`endif
wire [7:0] sel = {sel7_l,sel6_l,sel5_l,sel4_l,
sel3_l,sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or sel3_l or in0 or in1 or in2 or in3 or
sel4_l or sel5_l or sel6_l or sel7_l or in4 or in5 or in6 or in7)
case ({sel7_l,sel6_l,sel5_l,sel4_l,sel3_l,sel2_l,sel1_l,sel0_l})
8'b11111110 : dout = in0 ;
8'b11111101 : dout = in1 ;
8'b11111011 : dout = in2 ;
8'b11110111 : dout = in3 ;
8'b11101111 : dout = in4 ;
8'b11011111 : dout = in5 ;
8'b10111111 : dout = in6 ;
8'b01111111 : dout = in7 ;
8'b11111111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux8ds
// ----------------------------------------------------------------------
// 3:1 MUX WITH DECODED SELECTS
module dp_mux3ds (dout, in0, in1, in2,
sel0_l, sel1_l, sel2_l);
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0_l;
input sel1_l;
input sel2_l;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint dl_1c_chk3 ($one_cold ({sel2_l,sel1_l,sel0_l}));
`endif
wire [2:0] sel = {sel2_l,sel1_l,sel0_l}; // 0in one_cold
always @ (sel0_l or sel1_l or sel2_l or in0 or in1 or in2)
case ({sel2_l,sel1_l,sel0_l})
3'b110 : dout = in0 ;
3'b101 : dout = in1 ;
3'b011 : dout = in2 ;
default : dout = {SIZE{1'bx}} ;
endcase
endmodule // dp_mux3ds
// ----------------------------------------------------------------------
module dp_buffer(dout, in);
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in;
assign dout = in;
endmodule // dp_buffer
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O32AI_FUNCTIONAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_FUNCTIONAL_PP_V
|
// Copyright 2021 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module ifte(i, t, e, out);
input [7:0] e;
input i;
output [7:0] out;
input [7:0] t;
imux2 _0_ (
.A(t[0]),
.B(e[0]),
.S(i),
.Y(out[0])
);
imux2 _1_ (
.A(t[1]),
.B(e[1]),
.S(i),
.Y(out[1])
);
imux2 _2_ (
.A(t[2]),
.B(e[2]),
.S(i),
.Y(out[2])
);
imux2 _3_ (
.A(t[3]),
.B(e[3]),
.S(i),
.Y(out[3])
);
imux2 _4_ (
.A(t[4]),
.B(e[4]),
.S(i),
.Y(out[4])
);
imux2 _5_ (
.A(t[5]),
.B(e[5]),
.S(i),
.Y(out[5])
);
imux2 _6_ (
.A(t[6]),
.B(e[6]),
.S(i),
.Y(out[6])
);
imux2 _7_ (
.A(t[7]),
.B(e[7]),
.S(i),
.Y(out[7])
);
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter_004.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter_004 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long strL[200005], patL[200005], n, m, pref[200005], ans, tempL[200005]; char strC[200005], tempC[200005]; vector<long long> endings; string patC = ; long long lenP, lenS; void calcPrefixFunction() { for (long long i = 1, k = 0; i < m - 2; i++) { while (k > 0 && (patC[k] != patC[i] || patL[k] != patL[i])) k = pref[k - 1]; if (patC[k] == patC[i] && patL[i] == patL[k]) pref[i] = ++k; else pref[i] = k; } } void kmp() { for (long long i = 0, k = 0; i < n; i++) { while (k > 0 && (strL[i] != patL[k] || strC[i] != patC[k])) k = pref[k - 1]; if (strL[i] == patL[k] && strC[i] == patC[k]) k++; if (k == m - 2) { endings.push_back(i); k = pref[k - 1]; } } } long long tempSolve1() { long long ret = 0; for (long long i = 0; i < n; i++) if (tempL[0] <= strL[i] && strC[i] == tempC[0]) ret += strL[i] - tempL[0] + 1; return ret; } long long tempSolve2() { long long ret = 0; for (long long i = 0; i < n - 1; i++) if (tempL[0] <= strL[i] && strC[i] == tempC[0]) if (tempL[1] <= strL[i + 1] && strC[i + 1] == tempC[1]) ret++; return ret; } void solve() { if (lenP > lenS) { puts( 0 ); return; } if (m == 1) { printf( %I64d , tempSolve1()); return; } if (m == 2) { printf( %d , tempSolve2()); return; } calcPrefixFunction(); kmp(); for (long long i = 0; i < endings.size(); i++) { long long start, end; end = endings[i] + 1; start = end - m + 1; if (end >= n || start < 0) continue; if (strC[start] == tempC[0] && strL[start] >= tempL[0]) if (strC[end] == tempC[m - 1] && strL[end] >= tempL[m - 1]) ans++; } printf( %d , ans); } void input() { scanf( %d %d , &n, &m); for (long long i = 0; i < n; i++) { scanf( %d-%c , &strL[i], &strC[i]); if (i && strC[i] == strC[i - 1]) { strL[i - 1] += strL[i]; n--; i--; } lenS += strL[i]; } for (long long i = 0; i < m; i++) { scanf( %d-%c , &tempL[i], &tempC[i]); lenP += tempL[i]; if (i && tempC[i] == tempC[i - 1]) { tempL[i - 1] += tempL[i]; if (i - 2 >= 0) patL[i - 2] = tempL[i - 1]; i--; m--; } else if (i && i < m - 1) patC += tempC[i], patL[i - 1] = tempL[i]; } } int main() { input(); solve(); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 7; const int maxm = 1e9 + 7; int n; int a[maxn], b[maxn], c[maxn], ans[maxn]; map<int, int> mp; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } queue<int> q; q.push(n); mp[a[n]] = n; for (int i = n; i >= 1; i--) { if (a[i] < a[q.back()]) { q.push(i); mp[a[q.back()]] = i; } } sort(b + 1, b + 1 + n); int num = unique(b + 1, b + n + 1) - b; int p = 0; for (int i = 1; i <= num - 1; i++) { int j = b[i]; if (!mp[j]) mp[j] = p; else { swap(mp[j], p); } } for (int i = 1; i <= n; i++) { if (i >= mp[a[i]]) printf( -1 ); else printf( %d , mp[a[i]] - i - 1); } }
|
#include <bits/stdc++.h> using namespace std; char ch[100001]; int N, n, m; long long a[1 << 20], b[1 << 20]; int g[21][100001]; void FWT(long long p[], int flag) { int temp = N; for (int i = 2; i <= temp; i *= 2) { int t = i / 2; for (int j = 0; j < temp; j += i) { for (int k = j; k < j + t; k++) { long long x = p[k]; long long y = p[k + t]; p[k] = x + y; p[k + t] = x - y; if (flag == -1) { p[k] /= 2; p[k + t] /= 2; } } } } } int main() { cin >> n >> m; N = 1 << n; for (int i = 1; i <= n; i++) { scanf( %s , ch + 1); for (int j = 1; j <= m; j++) { g[i][j] = ch[j] - 0 ; } } for (int i = 1; i <= m; i++) { int x = 0; for (int j = 1; j <= n; j++) { x = (x * 2) | g[j][i]; } a[x]++; } for (int i = 0; i < N; ++i) b[i] = b[i >> 1] + (i & 1); for (int i = 0; i < N; ++i) b[i] = min(b[i], n - b[i]); FWT(a, 1); FWT(b, 1); for (int i = 0; i < N; ++i) a[i] *= b[i]; FWT(a, -1); long long ans = n * m; for (int i = 0; i < N; ++i) ans = min(ans, a[i]); printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); } bool isSubSequence(string str1, string str2, int m, int n) { if (m == 0) return true; if (n == 0) return false; if (str1[m - 1] == str2[n - 1]) return isSubSequence(str1, str2, m - 1, n - 1); return isSubSequence(str1, str2, m, n - 1); } int main() { fast(); long long int t = 1; cin >> t; while (t--) { long long int n, p, k; cin >> n >> p >> k; vector<long long int> v; long long int i, x; for (i = 0; i < n; i++) { cin >> x; v.push_back(x); } sort(v.begin(), v.end()); long long int ans = 0; long long int left = p; vector<long long int> possible; if (v[0] > left) { cout << 0 << endl; } else if (v[0] == left) { if (n >= 2 && v[0] == v[1]) { cout << 2 << endl; } else { cout << 1 << endl; } } else { ans = 1; left -= v[0]; vector<long long int> temp; for (i = 2; i < n; i += 2) { temp.push_back(v[i]); } if (temp.size() == 0) { if (p >= v[1]) { cout << 2 << endl; continue; } else { cout << 1 << endl; continue; } } else { if (v[n - 1] == temp[temp.size() - 1]) { for (i = 0; i < temp.size(); i++) { if (left >= temp[i]) { left -= temp[i]; ans += 2; } } possible.push_back(ans); } else { for (i = 0; i < temp.size(); i++) { if (left >= temp[i]) { left -= temp[i]; ans += 2; } } if (left >= v[n - 1]) { ans += 1; } possible.push_back(ans); } } ans = 0; left = p; for (i = 1; i < n; i += 2) { if (left >= v[i]) { ans += 2; left -= v[i]; } } possible.push_back(ans); sort(possible.begin(), possible.end()); cout << possible[possible.size() - 1] << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 gen(chrono::system_clock::now().time_since_epoch().count()); const int N = 1e6 + 10; const long long MOD = 1e9 + 7; const long long p1 = 57, M1 = 1e9 + 3; const int rx[4] = {-1, 0, 1, 0}; const int ry[4] = {0, 1, 0, -1}; const int hx[8] = {-2, -2, -1, 1, 2, 2, 1, -1}; const int hy[8] = {-1, 1, 2, 2, 1, -1, -2, -2}; const long double eps = 1e-7; const double pi = acos(-1.0); const long long INF = 1e14 + 1000; struct segtree { vector<pair<int, int> > t; vector<int> lazy; int nw; segtree(int n) { nw = (1 << (32 - __builtin_clz(n) - (__builtin_popcount(n) == 1))); t.resize(nw << 1, {0, 1}); lazy.resize(nw << 1); for (int i = nw - 1; i > 0; i--) { t[i].second = t[i * 2].second + t[i * 2 + 1].second; } } void push(int v) { t[v * 2].first += lazy[v]; t[v * 2 + 1].first += lazy[v]; lazy[v * 2] += lazy[v]; lazy[v * 2 + 1] += lazy[v]; lazy[v] = 0; } void upd(int v, int cl, int cr, int l, int r, int x) { if (cl >= l && cr <= r) { t[v].first += x; lazy[v] += x; return; } if (cl >= r || cr <= l) return; push(v); int mid = (cl + cr) / 2; upd(v * 2, cl, mid, l, r, x); upd(v * 2 + 1, mid, cr, l, r, x); if (t[v * 2].first < t[v * 2 + 1].first) { t[v] = t[v * 2]; } else if (t[v * 2 + 1].first < t[v * 2].first) { t[v] = t[v * 2 + 1]; } else { t[v] = t[v * 2]; t[v].second += t[v * 2 + 1].second; } } void upd(int l, int r, int x) { upd(1, 1, nw + 1, l, r + 1, x); } int kol(int v, int cl, int cr, int l, int r) { if (cl >= l && cr <= r) { if (t[v].first == 0) return t[v].second; else return 0; } if (cl >= r || cr <= l) return 0; push(v); int mid = (cl + cr) / 2; return kol(v * 2, cl, mid, l, r) + kol(v * 2 + 1, mid, cr, l, r); } int kol(int l, int r) { return kol(1, 1, nw + 1, l, r + 1); } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; a[i]--; } vector<int> pos[n]; long long res = 0; segtree sgt(n); for (int i = 0; i < n; i++) { pos[a[i]].push_back(i); int sz = pos[a[i]].size(); if (sz == 1) { sgt.upd(1, i + 1, 1); } else if (sz == 2) { sgt.upd(1, pos[a[i]][0] + 1, -1); sgt.upd(1, i + 1, 1); } else if (sz == 3) { sgt.upd(1, pos[a[i]][1] + 1, -1); sgt.upd(pos[a[i]][0] + 2, i + 1, 1); } else if (sz == 4) { sgt.upd(pos[a[i]][0] + 2, pos[a[i]][2] + 1, -1); sgt.upd(1, pos[a[i]][0] + 1, 1); sgt.upd(pos[a[i]][1] + 2, i + 1, 1); } else { sgt.upd(1, pos[a[i]][sz - 5] + 1, -1); sgt.upd(pos[a[i]][sz - 4] + 2, pos[a[i]][sz - 2] + 1, -1); sgt.upd(1, pos[a[i]][sz - 4] + 1, 1); sgt.upd(pos[a[i]][sz - 3] + 2, i + 1, 1); } res += sgt.kol(1, i + 1); } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)2e9; int main() { int k, n, m, q; cin >> k >> n >> m >> q; map<string, map<string, int>> rec; vector<string> art(n); map<int, map<string, int>> b; for (int(i) = (int)(0); (i) < (int)n; ++(i)) cin >> art[i]; sort(art.begin(), art.end()); string s; getline(cin, s); for (int(i) = (int)(0); (i) < (int)m; ++(i)) { getline(cin, s); int p = s.find( : ); string ar = s.substr(0, p); s = s.substr(p + 2, s.size()); s += , ; while (s != ) { p = s.find( ); string t = s.substr(0, p); s = s.substr(p + 1, s.size()); p = s.find( , ); string t2 = s.substr(0, p); s = s.substr(p + 2, s.size()); int col = atoi(t2.c_str()); rec[ar][t] = col; } } for (int(i) = (int)(0); (i) < (int)q; ++(i)) { int t; cin >> t; string st; cin >> st; b[t][st]++; for (map<string, map<string, int>>::iterator it1 = rec.begin(); it1 != rec.end(); ++it1) { bool ok = true; for (map<string, int>::iterator it2 = it1->second.begin(); it2 != it1->second.end(); ++it2) { if (b[t].find(it2->first) == b[t].end() || b[t][it2->first] < it2->second) { ok = false; break; } } if (ok) { for (map<string, int>::iterator it2 = it1->second.begin(); it2 != it1->second.end(); ++it2) { b[t][it2->first] -= it2->second; if (b[t][it2->first] == 0) b[t].erase(it2->first); } b[t][it1->first]++; break; } } } for (int(i) = (int)(1); (i) < (int)k + 1; ++(i)) { cout << b[i].size() << n ; for (map<string, int>::iterator it = b[i].begin(); it != b[i].end(); ++it) if (it->second) cout << it->first << << it->second << n ; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Apr 14 18:32:23 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top bd_proc_sys_reset_1_0 -prefix
// bd_proc_sys_reset_1_0_ bd_proc_sys_reset_0_0_stub.v
// Design : bd_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module bd_proc_sys_reset_1_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { int n, k; cin >> n >> k; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } if (n == 1) { if (a[0] == k) { cout << yes n ; } else { cout << no n ; } continue; } bool flag = false; bool k_flag = false; for (int i = 0; i < n; ++i) { if (a[i] == k) { k_flag = true; break; } } if (!k_flag) { cout << no n ; continue; } for (int i = 0; i < n; ++i) { if (a[i] != k) { continue; } if (i - 1 >= 0 && a[i - 1] >= k || i + 1 < n && a[i + 1] >= k) { flag = true; break; } if (i - 2 >= 0 && a[i - 2] >= k || i + 2 < n && a[i + 2] >= k) { flag = true; break; } if (flag) { break; } } for (int i = 0; i < n - 1; ++i) { if (a[i] >= k && a[i + 1] >= k) { flag = true; } } for (int i = 0; i < n - 2; ++i) { if (a[i] >= k && a[i + 2] >= k) { flag = true; } } if (flag) { cout << yes n ; } else { cout << no n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0), eps = 1e-4; double fgcd(double a, double b) { return fabs(a) < eps ? b : (fabs(b) < eps ? a : fgcd(b, fmod(a, b))); } int main() { double a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; c -= a; e -= a; d -= b; f -= b; a = (c * c + d * d) / 2; b = (e * e + f * f) / 2; double ov = 1.0 / (d * e - c * f); double A = (d * b - f * a) * ov, B = (e * a - c * b) * ov; double R = sqrt(A * A + B * B), G1 = asin(sqrt(a * 2) / (R * 2)), G2 = asin(sqrt(b * 2) / (R * 2)), G = asin(hypot(c - e, d - f) / (R * 2)); G = fgcd(G1, fgcd(G2, pi)); G = pi / round(pi / G); A = round(pi / G) * R * R * sin(G * 2) / 2; printf( %.8lf n , A); }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fei4_rx_core
#(
parameter DSIZE = 10,
parameter DATA_IDENTIFIER = 0,
parameter ABUSWIDTH = 32
)
(
input wire RX_CLK,
input wire RX_CLK2X,
input wire RX_CLK2X_IOCE,
input wire DATA_CLK,
input wire RX_DATA,
output wire RX_READY,
output wire RX_8B10B_DECODER_ERR,
output wire RX_FIFO_OVERFLOW_ERR,
input wire FIFO_CLK,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire RX_FIFO_FULL,
output wire RX_ENABLED,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 3;
// 0 - soft reset
// 1 - status
// 2-3 fifo size
// 4 - decoder_err_cnt
// 5 - lost_err_cnt
// reset sync and registers
// when write to addr = 0 then reset
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
reg RST_FF, RST_FF2;
always @(posedge BUS_CLK) begin
RST_FF <= SOFT_RST;
RST_FF2 <= RST_FF;
end
reg BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
// reset sync only
wire RX_RST;
assign RX_RST = (BUS_ADD==1 && BUS_WR);
reg RX_RST_FF, RX_RST_FF2;
always @(posedge BUS_CLK) begin
RX_RST_FF <= RX_RST;
RX_RST_FF2 <= RX_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~RST_FF2 & RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RST;
assign RST = BUS_RST_FLAG | SOFT_RST_FLAG;
wire RX_RST_FLAG;
assign RX_RST_FLAG = ~RX_RST_FF2 & RX_RST_FF;
wire ready_rec;
wire [15:0] fifo_size; // BUS_ADD==3, 4
reg [15:0] fifo_size_buf;
wire [7:0] decoder_err_cnt; // BUS_ADD==5
reg [7:0] decoder_err_cnt_buf;
wire [7:0] lost_err_cnt; // BUS_ADD==6
reg [7:0] lost_err_cnt_buf;
assign RX_READY = (ready_rec==1'b1) ? 1'b1 : 1'b0;
assign RX_8B10B_DECODER_ERR = (decoder_err_cnt!=8'b0);
assign RX_FIFO_OVERFLOW_ERR = (lost_err_cnt!=8'b0);
reg [7:0] status_regs;
wire CONF_EN_INVERT_RX_DATA; // BUS_ADD==2 BIT==1
assign CONF_EN_INVERT_RX_DATA = status_regs[1];
wire CONF_EN_RX; // BUS_ADD==2 BIT==2
assign CONF_EN_RX = status_regs[2];
assign RX_ENABLED = CONF_EN_RX;
always @(posedge BUS_CLK) begin
if(RST)
status_regs <= 8'b0000_0100; // enable Rx by default
else if(BUS_WR && BUS_ADD == 2)
status_regs <= BUS_DATA_IN;
end
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {status_regs[7:1], RX_READY};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= fifo_size[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= fifo_size_buf[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= decoder_err_cnt_buf;
else if(BUS_ADD == 6)
BUS_DATA_OUT <= lost_err_cnt_buf;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire [23:0] FE_DATA;
wire [7:0] DATA_HEADER;
assign DATA_HEADER = DATA_IDENTIFIER;
assign FIFO_DATA = {DATA_HEADER, FE_DATA};
always @ (posedge BUS_CLK)
begin
if (BUS_ADD == 3 && BUS_RD)
fifo_size_buf <= fifo_size;
end
always @ (posedge BUS_CLK)
begin
decoder_err_cnt_buf <= decoder_err_cnt;
end
always @ (posedge BUS_CLK)
begin
lost_err_cnt_buf <= lost_err_cnt;
end
receiver_logic #(
.DSIZE(DSIZE)
) ireceiver_logic (
.RESET(RST | RX_RST_FLAG),
.WCLK(DATA_CLK),
.FCLK(RX_CLK),
.FCLK2X(RX_CLK2X),
.FCLK2X_IOCE(RX_CLK2X_IOCE),
.BUS_CLK(BUS_CLK),
.RX_DATA(RX_DATA),
.read(FIFO_READ),
.data(FE_DATA),
.empty(FIFO_EMPTY),
.full(RX_FIFO_FULL),
.rec_sync_ready(ready_rec),
.lost_err_cnt(lost_err_cnt),
.decoder_err_cnt(decoder_err_cnt),
.fifo_size(fifo_size),
.invert_rx_data(CONF_EN_INVERT_RX_DATA),
.enable_rx(CONF_EN_RX),
.FIFO_CLK(FIFO_CLK)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char rd; int sig; template <class T> inline void read(T &a) { for (a = 0, rd = getchar(); ( 0 > rd || rd > 9 ) && rd != - ; rd = getchar()) ; for (rd == - ? sig = -1, rd = getchar() : sig = 1; 0 <= rd && rd <= 9 ;) a *= 10, a += rd - 0 , rd = getchar(); a *= sig; } int n, k, l[100005], r[100005]; int main() { read(n); read(k); int tot = 0; for (int i = (1); i <= (n); ++i) read(l[i]), read(r[i]), tot += r[i] - l[i] + 1; int ans = (k - tot % k) % k; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; long long max3(long long x, long long y, long long z) { return max(max(x, y), z); } long long min3(long long x, long long y, long long z) { return min(min(x, y), z); } const long long N = 1e5 + 10, M = 2e5 + 10, M2 = 1e6 + 10, mod = 1e9 + 7, inf = 1e17 + 10; const long long INF = 1e9 + 7; void add(long long& a, long long b) { a += b; if (a >= mod) { a -= mod; } } long long X[] = {0, 1, 0, -1}; long long Y[] = {-1, 0, 1, 0}; long long power(long long x, long long n) { long long result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % mod; x = ((x % mod) * (x % mod)) % mod; n = n / 2; } return result; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; vector<string> s(n); long long f[26] = {0}; for (long long i = 0; i < n; i++) { cin >> s[i]; for (long long j = 0; j < s[i].size(); j++) { f[s[i][j] - a ]++; } } bool flag = true; for (long long i = 0; i < 26; i++) { if (f[i] % n != 0) flag = false; } if (flag) cout << YES n ; else cout << NO n ; } return 0; }
|
module avr109tx (
input rst,
input clk,
input[7:0] tx_data,
input tx_avail,
output txd,
output tx_ready
);
parameter CLK_FREQUENCY = ;
parameter BAUD_RATE = 19200;
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam BAUDDIV = (CLK_FREQUENCY / BAUD_RATE);
localparam LOG2_BAUDDIV = log2(BAUDDIV);
reg [8:0] txshift_d, txshift_q;
reg [3:0] txcnt_d, txcnt_q;
reg tx_active_d, tx_active_q;
reg [LOG2_BAUDDIV-1:0] txbaud_d, txbaud_q;
assign txd = txshift_q[0];
assign tx_ready = ~tx_active_q;
always @(*) begin
txshift_d = txshift_q;
txcnt_d = txcnt_q;
tx_active_d = tx_active_q;
txbaud_d = txbaud_q;
if (tx_active_q) begin
if (txbaud_q == BAUDDIV-1) begin
txshift_d = {1'b1, txshift_q[8:1]};
if (txcnt_q == 9)
tx_active_d = 0;
txcnt_d = txcnt_q + 1;
txbaud_d = 0;
end else begin
txbaud_d = txbaud_q + 1;
end
end else if (tx_avail) begin
txshift_d = {tx_data, 1'b0};
txcnt_d = 0;
txbaud_d = 0;
tx_active_d = 1;
end
end
always @(posedge clk) begin
if (rst) begin
txshift_q <= 9'b111111111;
txcnt_q <= 4'b0;
tx_active_q <= 1'b0;
txbaud_q <= {LOG2_BAUDDIV{1'b0}};
end else begin
txshift_q <= txshift_d;
txcnt_q <= txcnt_d;
tx_active_q <= tx_active_d;
txbaud_q <= txbaud_d;
end
end
endmodule // avr109tx
|
#include <bits/stdc++.h> using namespace std; int n, a, ans; int main() { cin >> n; int sq; ans = -1e9; for (int i = 0; i < n; i++) { cin >> a; if (a < 0) { ans = max(ans, a); continue; } sq = sqrt(a); if (sq * sq != a) { ans = max(ans, a); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> h(n + 5); vector<long long> deg(n + 5, 0), a(n + 5, 0); for (long long i = 1; i <= n; i++) cin >> h[i]; for (long long i = 1; i <= n; i++) cin >> a[i], deg[a[i]]++; long long c = -1; long long maxi = 0; for (long long i = 1; i <= n; i++) { if (h[i] == 1) { long long x = a[i]; long long cnt = 1; while (x > 0 && deg[x] == 1) cnt++, x = a[x]; if (cnt > maxi) { maxi = cnt; c = i; } } } vector<long long> temp; temp.push_back(c); c = a[c]; while (c > 0 && deg[c] == 1) temp.push_back(c), c = a[c]; long long l = (long long)temp.size(); cout << l << n ; for (long long i = l - 1; i >= 0; i--) cout << temp[i] << ; }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
// File name : UniversalCounter10bitsV5.v
// Written by : Jianjian Song
// 4-bit universal bidirectional counter
`timescale 1ns / 1ps
module UniversalCounter10bitsV5(P,BeginCount, EndCount, Q,S1,S0,TerminalCount, Reset, CLOCK) ;
parameter length = 10;
input S1, S0, Reset, CLOCK;
input [length-1:0] P, BeginCount, EndCount;
output reg [length-1:0] Q;
output reg TerminalCount; //TerminalCount=1 when the counter wraps around
reg [length-1:0] NextQ;
always @ (posedge CLOCK or posedge Reset)
if(Reset==1) Q <= BeginCount;
else Q<=NextQ;
always@(Q or S1 or S0 or P or EndCount or BeginCount)
case ({S1,S0})
2'b00: begin NextQ <= Q; TerminalCount<=0; end // hold
2'b01: begin if (Q>=EndCount) begin TerminalCount<=1; NextQ<=0; end
else begin TerminalCount<=0; NextQ <= Q+1'b1; end
end // count up
2'b10: begin if (Q==BeginCount) begin TerminalCount<=1; NextQ<=EndCount; end
else begin TerminalCount<=0; NextQ <= Q-1'b1; end
end // count down
2'b11: begin NextQ <= P; TerminalCount<=1'b0; end // parallel load
endcase
endmodule
|
module datacache (A,D,Q,M,WEN,clk);
input [9:0] A;
input [128+22-1:0] D;
output reg [128+22-1:0] Q;
input clk;
input WEN;
input [15:0] M;
reg [21:0] MemU [1023:0];
reg [7:0] Mem1 [1023:0];
reg [7:0] Mem2 [1023:0];
reg [7:0] Mem3 [1023:0];
reg [7:0] Mem4 [1023:0];
reg [7:0] Mem5 [1023:0];
reg [7:0] Mem6 [1023:0];
reg [7:0] Mem7 [1023:0];
reg [7:0] Mem8 [1023:0];
reg [7:0] Mem9 [1023:0];
reg [7:0] Mem10 [1023:0];
reg [7:0] Mem11 [1023:0];
reg [7:0] Mem12 [1023:0];
reg [7:0] Mem13 [1023:0];
reg [7:0] Mem14 [1023:0];
reg [7:0] Mem15 [1023:0];
reg [7:0] Mem16 [1023:0];
always @(posedge clk) Q <= {MemU[A],
Mem16[A],Mem15[A],Mem14[A],Mem13[A],Mem12[A],Mem11[A],Mem10[A],Mem9[A],
Mem8[A],Mem7[A],Mem6[A],Mem5[A],Mem4[A],Mem3[A],Mem2[A],Mem1[A]};
always @(posedge clk) if ((WEN ==0)&&(M[ 0]==1'b1)) Mem1[A] <= D[ 7: 0];
always @(posedge clk) if ((WEN ==0)&&(M[ 1]==1'b1)) Mem2[A] <= D[ 15: 8];
always @(posedge clk) if ((WEN ==0)&&(M[ 2]==1'b1)) Mem3[A] <= D[ 23: 16];
always @(posedge clk) if ((WEN ==0)&&(M[ 3]==1'b1)) Mem4[A] <= D[ 31: 24];
always @(posedge clk) if ((WEN ==0)&&(M[ 4]==1'b1)) Mem5[A] <= D[ 39: 32];
always @(posedge clk) if ((WEN ==0)&&(M[ 5]==1'b1)) Mem6[A] <= D[ 47: 40];
always @(posedge clk) if ((WEN ==0)&&(M[ 6]==1'b1)) Mem7[A] <= D[ 55: 48];
always @(posedge clk) if ((WEN ==0)&&(M[ 7]==1'b1)) Mem8[A] <= D[ 63: 56];
always @(posedge clk) if ((WEN ==0)&&(M[ 8]==1'b1)) Mem9[A] <= D[ 71: 64];
always @(posedge clk) if ((WEN ==0)&&(M[ 9]==1'b1)) Mem10[A] <= D[ 79: 72];
always @(posedge clk) if ((WEN ==0)&&(M[10]==1'b1)) Mem11[A] <= D[ 87: 80];
always @(posedge clk) if ((WEN ==0)&&(M[11]==1'b1)) Mem12[A] <= D[ 95: 88];
always @(posedge clk) if ((WEN ==0)&&(M[12]==1'b1)) Mem13[A] <= D[103: 96];
always @(posedge clk) if ((WEN ==0)&&(M[13]==1'b1)) Mem14[A] <= D[111:104];
always @(posedge clk) if ((WEN ==0)&&(M[14]==1'b1)) Mem15[A] <= D[119:112];
always @(posedge clk) if ((WEN ==0)&&(M[15]==1'b1)) Mem16[A] <= D[127:120];
always @(posedge clk) if (WEN ==0) MemU[A] <= D[149:128];
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, n, k, x, ans, c; pair<int, int> a[100005]; int main() { cin >> n >> k; for (i = 0; i < n; i++) { cin >> x; a[i].first = 10 - x % 10; a[i].second = x; } sort(a, a + n); for (i = 0; i < n; i++) { if (a[i].second < 100 && (k - (10 - a[i].second % 10) >= 0)) { a[i].second += 10 - a[i].second % 10; k -= a[i].first; } else { break; } if (i == n - 1) { break; } } for (i = 0; i < n; i++) { ans += a[i].second / 10; } cout << min(n * 10, ans + k / 10); }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is designed for use on an Altera DE0-Nano Development Board. *
* It allows a user to interface with the on-board Analog-to-Digital *
* Converter. *
* *
******************************************************************************/
module niosII_system_de0_nano_adc_0 (
clock,
reset,
read,
write,
readdata,
writedata,
address,
waitrequest,
adc_sclk,
adc_cs_n,
adc_din,
adc_dout
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter tsclk = 8'd16;
parameter numch = 4'd4;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clock, reset, read, write;
input [31:0] writedata;
input [2:0] address;
output reg [31:0] readdata;
output reg waitrequest;
input adc_dout;
output adc_sclk, adc_cs_n, adc_din;
reg go;
reg [11:0] values [7:0];
reg auto_run;
wire done;
wire [11:0] outs [7:0];
defparam ADC_CTRL.T_SCLK = tsclk, ADC_CTRL.NUM_CH = numch;
adv_adc ADC_CTRL (clock, reset, go, adc_sclk, adc_cs_n, adc_din, adc_dout, done, outs[0],
outs[1], outs[2], outs[3], outs[4], outs [5], outs[6], outs[7]);
// - - - - - - - readdata & waitrequest - - - - - - -
always @(*)
begin
readdata =0;
waitrequest =0;
if (write && done) //need done to be lowered before re-raising go
waitrequest=1;
if (read) begin
if (go&&!auto_run)
waitrequest=1;
else
readdata = {address,17'b0, values[address]};
end
end
// - - - - - - - - - - go - - - - - - - - -
always @ (posedge clock)
begin
if (reset)
go<=1'b0;
else if (done)
go<=1'b0;
else if (write && address == 3'b0)
go<=1'b1;
else if (auto_run)
go<=1'b1;
end
// - - - - - - - values - - - - - - - - - - - - -
always @ (posedge clock)
if (done) begin
values[0] <= outs[0];
values[1] <= outs[1];
values[2] <= outs[2];
values[3] <= outs[3];
values[4] <= outs[4];
values[5] <= outs[5];
values[6] <= outs[6];
values[7] <= outs[7];
end
// - - - - - - - - - - auto run - - - - - - - - - -
always @(posedge clock)
if (write && address == 3'd1)
auto_run <= writedata[0];
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ContrastTransform
:Function
Change the contrast of an image.
Give the first output after mul_delay + 1 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-16
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module ContrastTransform(
clk,
rst_n,
ct_scale,
in_enable,
in_data,
out_ready,
out_data
);
/*
::description
This module's working mode.
::range
0 for Pipelines, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
Channels for color, 1 for gray, 3 for rgb, etc.
*/
parameter color_channels = 3;
/*
::description
Color's bit wide
::range
1 - 12
*/
parameter[3: 0] color_width = 8;
/*
::description
Delay for multiplier.
::range
Depend your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Scale for contrast, fixed, 12bits.12bits.
*/
input[23 : 0] ct_scale;
/*
::description
Input data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [color_channels * color_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[color_channels * color_width - 1 : 0] out_data;
reg[2 : 0] con_enable;
genvar i;
generate
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == mul_delay + 1)
con_enable <= con_enable;
else
con_enable <= con_enable +1;
end
assign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
`define h (i + 1) * color_width - 1
`define l i * color_width
for (i = 0; i < color_channels; i = i + 1) begin: channel
wire[11 : 0] mul_a;
wire[23 : 0] mul_b;
wire[23 : 0] mul_p;
if(work_mode == 0) begin
assign mul_a = in_data[`h : `l];
assign mul_b = ct_scale;
end else begin
reg[11 : 0] reg_mul_a;
reg[23 : 0] reg_mul_b;
always @(posedge in_enable) begin
reg_mul_a = in_data[`h : `l];
reg_mul_b = ct_scale;
end
assign mul_a = reg_mul_a;
assign mul_b = reg_mul_b;
end
/*
::description
Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
Multiplier12x24CT Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
//For overflow
reg [color_width - 1 : 0] out_buffer;
always @(posedge clk) begin
out_buffer <= mul_p[23 : color_width] != 0 ?
{color_width{1'b1}} :
mul_p[color_width - 1 : 0];
end
assign out_data[`h : `l] = out_ready ? out_buffer : 0;
end
`undef h
`undef l
endgenerate
endmodule
|
/**
* Fill the memory with initial values.
*/
module memory_init(
input clk,
input reset,
output [7:0] out
);
reg [12:0] address;
reg m1_we, m2_we, m3_we;
wire [15:0] q1, q2, q3;
reg [15:0] d;
reg [7:0] out_buf;
always @(posedge clk or posedge reset) begin
if (reset) begin
address <= 0;
d <= 16'b1111_1111_1111_1111;
end else begin
address <= address + 13'd1;
d <= 16'b1111_1111_1111_1111;
end
end
// Mux for which memory to use.
always @* begin
m1_we = 0; // 32
m2_we = 0; // 16
m3_we = 0; // 8
out_buf = 0;
if (address < 13'd2048) begin
m1_we = 1;
out_buf = q1[7:0];
end else if (address < (13'd2048 + 13'd1024)) begin
m2_we = 1;
out_buf = q2[7:0];
end else if (address < (13'd2048 + 13'd1024 + 13'd512)) begin
m3_we = 1;
out_buf <= q3[7:0];
end
end
ram_32 mem32 (.q(q1), .d(d), .write_address(address), .read_address(address - 1), .we(m1_we), .clk(clk));
ram_16 mem16 (.q(q2), .d(d), .write_address(address), .read_address(address - 1), .we(m2_we), .clk(clk));
ram_8 mem8 (.q(q3), .d(d), .write_address(address), .read_address(address - 1), .we(m3_we), .clk(clk));
assign out = out_buf;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5 + 1; struct Node { int t, x, l, c; } pnt[maxN]; long long t, pos[maxN]; int m, n; int solve(long long t) { int l, r, m; while (t > 0) { l = 1, r = n + 1; while (l + 1 < r) { m = (l + r) >> 1; if (pos[m] < t) l = m; else r = m; } if (pnt[l].t == 1) return pnt[l].x; t = ((t - pos[l] - 1) % pnt[l].l) + 1; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &pnt[i].t); if (pnt[i].t == 1) { scanf( %d , &pnt[i].x); pos[i + 1] = pos[i] + 1; } else { scanf( %d%d , &pnt[i].l, &pnt[i].c); pos[i + 1] = pos[i] + pnt[i].l * pnt[i].c; } } scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %I64d , &t); printf( %d , solve(t)); if (i < m) printf( ); else printf( n ); } }
|
// EE 454
// Spring 2015
// Lab 2 Part 2
// John Timms
// accumulator_memory.v
//
// clk, reset - self explanatory
// op - operation desired by the processor
// signal - memory tells the processor when it's done
// read -
// write -
// load - indicates that the testbench wants to load numbers
// full - goes high when the memory is full (i.e. index is 1023)
// index - reports the value of I
// preview - reports the value of M[I]
// state - reports the current state
// load, full, index, preview, and state wires are only for the testbench's convenience
//
`timescale 1 ns / 100 ps
module accumulator_memory (clk, reset, op, signal, read, write, load, full, index, preview, state);
input clk, reset, load;
input [1:0] op;
input [31:0] write;
output [31:0] read;
output [31:0] preview;
output signal, full, state;
output [9:0] index;
reg [31:0] M [0:1023];
reg [9:0] I;
reg [4:0] state;
reg signal;
reg [31:0] read;
localparam
NOP = 2'b00, // No operation
FETCH = 2'b01, // Fetch an operand from the memory
SEND = 2'b10; // Send a result to the memory
localparam
INI = 5'b00001, // Initial state - loads the memory from the testbench
READ = 5'b00010, // Read state - sends a number to the processor
WRITE = 5'b00100, // Write state - writes a number received from the processor
READY = 5'b01000, // Ready state - waits for the next processor contact
DONE = 5'b10000; // Done state - sends the result over the bus
assign preview = M[I];
assign full = ( I == 10'b1111111111 );
assign index = I;
reg [5*8:1] state_string;
always @(*)
begin
case (state)
5'b00001: state_string = "INI ";
5'b00010: state_string = "READ ";
5'b00100: state_string = "WRITE";
5'b01000: state_string = "READY";
5'b10000: state_string = "DONE ";
default: state_string = "UNKN ";
endcase
end
always @(posedge clk, posedge reset)
begin
if (reset) begin
state <= INI;
I <= 0;
signal <= 0;
end
else begin
case (state)
// Initial state
INI :
begin
if (load && write != 0) begin
M[I] <= write;
I <= I + 1;
end
if (!load && op == FETCH) begin
state <= READ;
end
if (!load && op == SEND) begin
state <= WRITE;
end
end
// Read state
// Finds an M[I] that is non-zero by traveling up the index
// Puts M[I] on the bus, sets M[I] to zero, increments I
// Always increments I (if I is not terminal) because reads are 2x common as writes, so it should be faster
// If I is terminal (i.e. equals 1023) and M[1023] has already been read then it just puts zero on the bus
READ :
begin
if (I == 1023 && M[I] == 0) begin
read <= 0;
signal <= 1;
state <= READY;
end
else begin
if (M[I] != 0) begin
read <= M[I];
signal <= 1;
M[I] <= 0;
if (I != 1023)
I <= I + 1;
state <= READY;
end
else begin
I <= I + 1;
end
end
end
// Write state
// Finds an M[I] that is zero by traveling down the index
// Puts data into M[I]
// If I is terminal (i.e. equals 1023) then go to the done state
WRITE :
begin
if (I == 1023 && M[I] == 0) begin
M[I] <= write;
signal <= 1;
I <= I - 1;
state <= DONE;
end
else begin
if (M[I] == 0) begin
M[I] <= write;
signal <= 1;
state <= READY;
end
else begin
I <= I - 1;
end
end
end
// Ready state
// Sets signal low (signal is only ever high for one clock)
// Erases the current read value (if any) to prevent confusion
// Enforces a period of at least one clock before accepting another operation.
READY :
begin
signal <= 0;
read <= 'bx;
if (signal == 0 && op == FETCH) begin
state <= READ;
end
if (signal == 0 && op == SEND) begin
state <= WRITE;
end
end
// Done state
// Puts M[I] on the bus.
// This state can only be reached when a processor writes and I = 1023.
DONE :
begin
signal <= 0;
read <= 'bx;
// This is necessary because of the processor random slowdown
if (signal == 0 && op == FETCH) begin
read <= 0;
signal <= 1;
end
if (signal == 0 && op == SEND && I == 1022) begin
M[I] <= write;
signal <= 1;
I <= I - 1;
end
if (signal == 0 && op == SEND && I == 1021) begin
M[I] <= write;
signal <= 1;
I <= I - 1;
end
if (signal == 0 && op == SEND && I == 1020) begin
M[I] <= write;
signal <= 1;
I <= I - 1;
end
if (signal == 0 && I == 1019) begin
read <= (M[1023] + M[1022] + M[1021] + M[1020]);
end
end
endcase
end
end
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: realcb.v,v 1.1 2003/02/10 05:14:13 stevewilliams Exp $
*/
module main;
real x, y;
initial begin
$my_watchreal(x, y);
#1 x = 1.0;
#1 y = 2.0;
#1 x = 1.5;
#1 y = 5.1;
end
endmodule // main
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) using namespace std; int matrix[22][22]; int mas[22]; int matrix1[22][22]; int matrix2[22][22]; int best = 0; int minv[22]; bool used[22]; int u[22]; int v[22]; int p[22]; int way[22]; int getresult(int n) { int res = 0; for (int i = 0; i <= n; i++) u[i] = 0; for (int i = 0; i <= n; i++) v[i] = 0; for (int i = 0; i <= n; i++) p[i] = 0; for (int i = 0; i <= n; i++) way[i] = 0; int m = n; const int INF = 1e9; for (int i = 1; i <= n; ++i) { p[0] = i; int j0 = 0; for (int x = 0; x <= m; x++) minv[x] = INF; for (int x = 0; x <= m; x++) used[x] = false; do { used[j0] = true; int i0 = p[j0], delta = INF, j1; for (int j = 1; j <= m; ++j) if (!used[j]) { int cur = matrix[i0][j] - u[i0] - v[j]; if (cur < minv[j]) minv[j] = cur, way[j] = j0; if (minv[j] < delta) delta = minv[j], j1 = j; } for (int j = 0; j <= m; ++j) if (used[j]) u[p[j]] += delta, v[j] -= delta; else minv[j] -= delta; j0 = j1; } while (p[j0] != 0); do { int j1 = way[j0]; p[j0] = p[j1]; j0 = j1; } while (j0); } return -v[0]; } int line1max[22]; int line2max[22]; int colmax[22]; int rr[22]; bool stop = false; int itt = 0; int go(int pos, int N, int N2, int cnt1 = 0, int cnt2 = 0) { if (stop) return 0; if (pos == N) { int res = 0; int maxres = 0; int maxres2 = 0; for (int i = 0; i < N; i++) colmax[i] = 0; for (int i = 0; i < N; i++) { if (mas[i] == 1) { for (int j = 0; j < N; j++) matrix[i + 1][j + 1] = -matrix1[i][j], colmax[j] = max(colmax[j], matrix1[i][j]); maxres += line1max[i]; } else { for (int j = 0; j < N; j++) matrix[i + 1][j + 1] = -matrix2[i][j], colmax[j] = max(colmax[j], matrix2[i][j]); maxres += line2max[i]; } } for (int i = 0; i < N; i++) maxres2 += colmax[i]; if (maxres > best && maxres2 > best) { res = -getresult(N); best = max(best, res); } return res; } int res = 0; if (rr[pos]) { if (cnt1 < N2) { mas[pos] = 1; res = max(res, go(pos + 1, N, N2, cnt1 + 1, cnt2)); } if (cnt2 < N2) { mas[pos] = 2; res = max(res, go(pos + 1, N, N2, cnt1, cnt2 + 1)); } } else { if (cnt2 < N2) { mas[pos] = 2; res = max(res, go(pos + 1, N, N2, cnt1, cnt2 + 1)); } if (cnt1 < N2) { mas[pos] = 1; res = max(res, go(pos + 1, N, N2, cnt1 + 1, cnt2)); } } itt++; if (itt & 63) { if (clock() * 1e-3 > 0.8) { stop = true; return res; } } return res; } int rowperm[22]; int colperm[22]; bool visrow[22]; bool viscol[22]; int main() { int N; scanf( %d , &N); for (int i = 0; i < N; i++) rowperm[i] = i; for (int i = 0; i < N; i++) colperm[i] = i; srand(time(0)); random_shuffle(rowperm, rowperm + N); random_shuffle(colperm, colperm + N); for (int i = 0; i < N; i++) rr[i] = rand() % 2; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) scanf( %d , &matrix1[rowperm[i]][colperm[j]]); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { line1max[i] = max(line1max[i], matrix1[i][j]); } } for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) scanf( %d , &matrix2[rowperm[i]][colperm[j]]); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { line2max[i] = max(line2max[i], matrix2[i][j]); } } int ost1 = N / 2; int ost2 = N / 2; memset(visrow, true, sizeof(visrow)); memset(viscol, true, sizeof(viscol)); for (int step = 0; step < N; step++) { int maxi1 = 0; int r1 = 0, c1 = 0; int maxi2 = 0; int r2 = 0, c2 = 0; for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { if (matrix1[i][j] > maxi1 && visrow[i] && viscol[j]) { maxi1 = matrix1[i][j]; r1 = i; c1 = j; } if (matrix2[i][j] > maxi2 && visrow[i] && viscol[j]) { maxi2 = matrix2[i][j]; r2 = i; c2 = j; } } } if (ost1 > 0 && maxi1 > maxi2) { ost1--; best += maxi1; visrow[r1] = false; viscol[c1] = false; } else if (ost2 > 0 && maxi2 > maxi1) { ost2--; best += maxi2; visrow[r2] = false; viscol[c2] = false; } else if (maxi1 == maxi2) { if (ost1 > ost2) { ost1--; best += maxi1; visrow[r1] = false; viscol[c1] = false; } else { ost2--; best += maxi2; visrow[r2] = false; viscol[c2] = false; } } else if (ost1 > 0) { ost1--; best += maxi1; visrow[r1] = false; viscol[c1] = false; } else { ost2--; best += maxi2; visrow[r2] = false; viscol[c2] = false; } } printf( %d n , max(best, go(0, N, N / 2))); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A2BB2O_FUNCTIONAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2bb2o (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// 2nd level of lead 0 counters. Lead 0 count for 8 bits.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_cnt_lead0_lvl2 (
din_7_4_eq_0,
din_7_6_eq_0,
lead0_4b_0_hi,
din_3_0_eq_0,
din_3_2_eq_0,
lead0_4b_0_lo,
din_7_0_eq_0,
lead0_8b_1,
lead0_8b_0
);
input din_7_4_eq_0; // data in[7:4] is zero
input din_7_6_eq_0; // data in[7:6] is zero
input lead0_4b_0_hi; // bit[0] of lead 0 count- data in[7:4]
input din_3_0_eq_0; // data in[3:0] is zero
input din_3_2_eq_0; // data in[3:2] is zero
input lead0_4b_0_lo; // bit[0] of lead 0 count- data in[3:0]
output din_7_0_eq_0; // data in[7:0] is zero
output lead0_8b_1; // bit[1] of lead 0 count
output lead0_8b_0; // bit[0] of lead 0 count
wire din_7_0_eq_0;
wire lead0_8b_1;
wire lead0_8b_0;
assign din_7_0_eq_0= din_3_0_eq_0 && din_7_4_eq_0;
assign lead0_8b_1= ((!din_7_4_eq_0) && din_7_6_eq_0)
|| (din_7_4_eq_0 && din_3_2_eq_0);
assign lead0_8b_0= ((!din_7_4_eq_0) && lead0_4b_0_hi)
|| (din_7_4_eq_0 && lead0_4b_0_lo);
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[100009], mark[100009], vis[100009]; map<pair<int, int>, int> mp; map<pair<int, int>, int>::iterator ii; int main() { int n, i; scanf( %d , &n); for (i = 0; i < n; ++i) scanf( %d , &arr[i]); memset(mark, 0, sizeof mark); for (i = 0; i < n; ++i) mark[arr[i]] += 1; int cnt = 0; for (i = 1; i <= 100000; ++i) if (mark[i] != 0) ++cnt; long long ans = 0; memset(vis, -1, sizeof vis); for (i = 0; i < n; ++i) { int val = arr[i]; mark[val]--; if (mark[val] == 0) cnt--; if (vis[val] == -1) { vis[val] = 1; ans = ans + (long long)cnt; } } printf( %lld n , ans); }
|
#include <bits/stdc++.h> int main() { int m, n, i, j, p, q; scanf( %d %d , &m, &n); scanf( %d %d , &p, &q); int ar[m], br[n]; for (i = 0; i < m; i++) { scanf( %d , &ar[i]); } for (i = 0; i < n; i++) { scanf( %d , &br[i]); } if (ar[p - 1] < br[n - q]) printf( YES n ); else printf( NO n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_TB_V
/**
* udp_dlatch$P_pp$PG: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_p_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$P_pp$PG dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2017 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VERILATOR
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
`else
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
`endif
module t (/*AUTOARG*/);
int i_i [2:0];
int o_i [2:0];
import "DPI-C" function int dpii_failure();
import "DPI-C" function void dpii_open_i(input int i [], output int o []);
reg [95:0] crc;
initial begin
crc = 96'h8a10a572_5aef0c8d_d70a4497;
i_i[0] = crc[31:0];
i_i[1] = crc[63:32];
i_i[2] = crc[95:64];
dpii_open_i(i_i, o_i);
`checkh(o_i[0], ~i_i[0]);
`checkh(o_i[1], ~i_i[1]);
`checkh(o_i[2], ~i_i[2]);
if (dpii_failure()!=0) begin
$write("%%Error: Failure in DPI tests\n");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_slave_wbm
*/
module test_i2c_slave_wbm;
// Parameters
parameter FILTER_LEN = 4;
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 16;
parameter WB_SELECT_WIDTH = WB_DATA_WIDTH/8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
reg enable = 0;
reg [6:0] device_address = 0;
// Outputs
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
i2c_scl_i,
i2c_sda_i,
wb_dat_i,
wb_ack_i,
wb_err_i,
enable,
device_address
);
$to_myhdl(
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t,
wb_adr_o,
wb_dat_o,
wb_we_o,
wb_sel_o,
wb_stb_o,
wb_cyc_o,
busy,
bus_addressed,
bus_active
);
// dump file
$dumpfile("test_i2c_slave_wbm.lxt");
$dumpvars(0, test_i2c_slave_wbm);
end
i2c_slave_wbm #(
.FILTER_LEN(FILTER_LEN),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300000 + 10; struct Node { int x, y; Node(int x, int y) : x(x), y(y) {} bool operator<(const Node& rhs) const { return x < rhs.x || (x == rhs.x && y < rhs.y); } }; int n, m, size[N], color[N], col = 1; vector<int> G[N], grp[N]; map<int, int> toid; map<vector<int>, int> id; map<Node, int> check; void dfs(int u) { color[u] = col++; for (int v : grp[u]) if (!color[v]) dfs(v); } int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) G[i].push_back(i); int x, y; for (int i = 0; i < m; i++) { cin >> x >> y; x--; y--; G[x].push_back(y); G[y].push_back(x); } m = 0; for (int i = 0; i < n; i++) { sort(G[i].begin(), G[i].end()); if (id.count(G[i])) toid[i] = id[G[i]]; else { id[G[i]] = m; toid[i] = m++; } } for (int i = 0; i < n; i++) for (int u : G[i]) if (toid[i] != toid[u] && !check.count(Node(toid[i], toid[u]))) { grp[toid[i]].push_back(toid[u]); grp[toid[u]].push_back(toid[i]); check[Node(toid[i], toid[u])] = 1; check[Node(toid[u], toid[i])] = 1; } for (int i = 0; i < m; i++) if (grp[i].size() >= 3) { cout << NO << endl; return 0; } for (int i = 0; i < m; i++) if (!color[i] && ((grp[i].size() == 1) || grp[i].size() == 0)) { dfs(i); col++; } for (int i = 0; i < m; i++) if (!color[i]) { cout << NO << endl; return 0; } cout << YES << endl; for (int i = 0; i < n; i++) cout << color[toid[i]] << ; cout << endl; return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 23217 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8192,
w8191,
w64,
w8255,
w128,
w129,
w516,
w7739,
w30956,
w23217;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w23217 = w30956 - w7739;
assign w30956 = w7739 << 2;
assign w516 = w129 << 2;
assign w64 = w1 << 6;
assign w7739 = w8255 - w516;
assign w8191 = w8192 - w1;
assign w8192 = w1 << 13;
assign w8255 = w8191 + w64;
assign o_data0 = w23217;
//multiplier_block area estimate = 8681.903915;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> using V = vector<T>; const int MM = 5e5 + 5; using T = long long; bool QUERY; struct Line { mutable T a, b, p; T Eval(T first) const { return a * first + b; } bool operator<(const Line& o) const { return QUERY ? p < o.p : a < o.a; } }; struct ConvexHull : multiset<Line> { const T kInf = numeric_limits<T>::max(); T div(T a, T b) { return a / b - ((a ^ b) < 0 && a % b); } bool isect(iterator first, iterator second) { if (second == end()) { first->p = kInf; return false; } if (first->a == second->a) { first->p = first->b > second->b ? kInf : -kInf; } else { first->p = div(second->b - first->b, first->a - second->a); } return first->p >= second->p; } void InsertLine(T a, T b) { auto nx = insert({a, b, 0}), it = nx++, pv = it; while (isect(it, nx)) { nx = erase(nx); } if (pv != begin() && isect(--pv, it)) { isect(pv, it = erase(it)); } while ((it = pv) != begin() && (--pv)->p >= it->p) { isect(pv, erase(it)); } } T EvalMax(T first) { if (empty()) { return -2e18; } QUERY = 1; auto it = lower_bound({0, 0, first}); QUERY = 0; return it->Eval(first); } }; vector<vector<int>> tree; long long sub[MM]; long long n; long long sq(long long e) { return e * e; } void dfs1(int cur, int par) { sub[cur] = 1; for (auto u : tree[cur]) { if (u != par) { dfs1(u, cur); sub[cur] += sub[u]; } } } long long dp1[MM]; void dfs2(int cur, int par) { dp1[cur] = sq(sub[cur]); for (int u : tree[cur]) { if (u != par) { dfs2(u, cur); dp1[cur] = min(dp1[cur], sq(sub[cur] - sub[u]) + dp1[u]); } } } vector<long long> ans; void dfs3(int cur, int par) { ConvexHull CH; ans[cur] = sq(n); for (int u : tree[cur]) { if (u != par) { dfs3(u, cur); long long val = dp1[u] - CH.EvalMax(sub[u]) + sq(sub[u]); ans[cur] = min(ans[cur], val); ans[cur] = min(ans[cur], dp1[u] + sq(n - sub[u])); CH.InsertLine(2 * (n - sub[u]), -(dp1[u] + sq(n - sub[u]))); } } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; tree.resize(n); ans.resize(n); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; u--; v--; tree[u].push_back(v); tree[v].push_back(u); } dfs1(0, -1); dfs2(0, -1); dfs3(0, -1); cout << (n * n - n) / 2 + (sq(n) - *min_element((ans).begin(), (ans).end())) / 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e6 + 7; const int ALPHA = 40; const long long INF = 1e16 + 7; const int MOD = 1e9 + 7; const int LOG = 22; const int BASE[2] = {313, 239}; long long n, d; bool ns[MAXN], seen[MAXN]; vector<long long> group[MAXN], plast[MAXN]; void solve() { cin >> n >> d; for (int i = 0; i < n; i++) { group[i].clear(); plast[i].clear(); } for (int i = 0; i < n; i++) cin >> ns[i]; fill(seen, seen + n, 0); long long ptr = 0, cnt = 0; for (int i = 0; i < n; i++) { ptr = i; if (seen[ptr]) continue; while (!seen[ptr]) { seen[ptr] = 1; group[cnt].push_back(ns[ptr]); ptr = (ptr + d) % n; } cnt++; } for (int i = 0; i < cnt; i++) { long long k = group[i].size(); for (int j = 0; j < k; j++) group[i].push_back(group[i][j]); long long last = -INF; for (int j = 0; j < group[i].size(); j++) { if (!group[i][j]) last = j; plast[i].push_back(j - last); } } long long maxim = 0; for (int i = 0; i < cnt; i++) { for (int j = 0; j < group[i].size() / 2; j++) { maxim = max(maxim, min(plast[i][j], plast[i][j + (group[i].size() / 2)])); } } if (maxim >= INF) cout << -1 << n ; else cout << maxim << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); ; int t; cin >> t; while (t--) solve(); }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Wed Jul 19 05:51:36 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../intra.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.3 2006/07/19 07:35:16 wig Exp $
// $Date: 2006/07/19 07:35:16 $
// $Log: ent_a.v,v $
// Revision 1.3 2006/07/19 07:35:16 wig
// Updated testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
`define const_17_c 8'b00000000 // __I_ConvConstant: 0x0
module ent_a
//
// Generated Module inst_a
//
(
const_p_19, // Constant on inst_a
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Module parameters:
parameter generic_15 = 4660;
// Generated Module Inputs:
input [15:0] const_p_19;
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire [15:0] const_p_19;
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] const_17;
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign const_17 = `const_17_c;
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.const_p_17(const_17), // Constant
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using vi = vector<int>; using pii = pair<int, int>; const int BSZ = 600; const int N = 100228; const int LG = 17; int n, m; vector<vi> g; vi pred; vi in, out; int timer; int up[LG][N]; vi ts; vi evs; vi sgn; vector<bool> alive; vi cnt; vi dif; vector<bool> any; int cur_add; vi ans; vi bkt[2 * N]; vi srt[2 * BSZ]; void dfs(int v) { in[v] = timer++; for (int to : g[v]) { dfs(to); } out[v] = timer++; } bool upper(int u, int v) { return (in[u] <= in[v] && out[v] <= out[u]); } int lca(int u, int v) { if (in[u] > in[v]) { swap(u, v); } if (upper(u, v)) { return u; } for (int i = LG - 1; i >= 0; i--) { if (!upper(up[i][u], v)) { u = up[i][u]; } } return up[0][u]; } void dfs_calc(int v) { cnt[v] = !alive[v]; for (int to : g[v]) { dfs_calc(to); cnt[v] += cnt[to]; any[v] = any[v] | any[to]; } dif[v] = ts[v] - cnt[v]; if (!any[v] && alive[v]) { cur_add += (dif[v] < 0); } } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; pred.resize(n, -1); g.resize(n); for (int i = 0; i < n - 1; i++) { int p; cin >> p; --p; pred[i + 1] = p; g[p].push_back(i + 1); up[0][i + 1] = p; } ts.resize(n); for (auto& x : ts) { cin >> x; } for (int j = 1; j < LG; j++) { for (int i = 0; i < n; i++) { up[j][i] = up[j - 1][up[j - 1][i]]; } } in.resize(n); out.resize(n); dfs(0); evs.resize(m); sgn.resize(m); for (int i = 0; i < m; i++) { auto& x = evs[i]; cin >> x; sgn[i] = (x > 0 ? -1 : 1); x = abs(x) - 1; } alive.resize(n, true); cnt.resize(n); dif.resize(n); any.resize(n); ans.resize(m, 0); for (int lb = 0; lb < m; lb += BSZ) { int rb = min(m, lb + BSZ); vi guys(rb - lb); fill((any).begin(), (any).end(), false); for (int i = lb; i < rb; i++) { guys[i - lb] = evs[i]; any[guys[i - lb]] = true; } sort((guys).begin(), (guys).end(), [](int u, int v) { return (in[u] < in[v]); }); guys.reserve(2 * (int)((guys).size())); for (int i = (int)((guys).size()) - 2; i >= 0; i--) { guys.push_back(lca(guys[i], guys[i + 1])); } guys.push_back(0); sort((guys).begin(), (guys).end(), [](int u, int v) { return (in[u] < in[v]); }); guys.resize(unique((guys).begin(), (guys).end()) - guys.begin()); vi comp_pred((int)((guys).size()), -1); vi st; int edge_check = 0; for (int i = 0; i < (int)((guys).size()); i++) { while (!st.empty() && !upper(guys[st.back()], guys[i])) { st.pop_back(); } if (!st.empty()) { comp_pred[i] = st.back(); edge_check++; } st.push_back(i); } assert(edge_check == (int)((guys).size()) - 1); cur_add = 0; dfs_calc(0); for (int i = lb; i < rb; i++) { ans[i] = cur_add; } for (int i = 0; i < (int)((guys).size()); i++) { srt[i].clear(); } for (int i = 0; i < 2 * N; i++) { bkt[i].clear(); } for (int i = 0; i < (int)((guys).size()); i++) { int u = guys[i]; bool st = alive[u]; int udif = dif[u]; for (int j = lb; j < rb; j++) { if (upper(u, evs[j])) { udif += sgn[j]; } if (evs[j] == u) { st = !st; } if (st) { ans[j] += (udif < 0); } } if (i) { int anc = guys[comp_pred[i]]; int v = pred[u]; if (anc != v) { while (v != anc) { if (alive[v]) { bkt[dif[v] + N].push_back(i); } v = pred[v]; } } } } for (int i = 0; i < 2 * N; i++) { for (int who : bkt[i]) { srt[who].push_back(i - N); } } for (int i = 0; i < (int)((guys).size()); i++) { auto u = guys[i]; auto& difs = srt[i]; vector<pii> pref; pref.reserve((int)((difs).size())); for (auto x : difs) { if (pref.empty()) { pref.push_back({x, 1}); } else if (x != pref.back().first) { pref.push_back({x, pref.back().second + 1}); } else { pref.back().second++; } } int pt = (int)((pref).size()); while (pt > 0 && pref[pt - 1].first >= 0) { pt--; } int bound = 0; for (int j = lb; j < rb; j++) { if (upper(u, evs[j])) { bound -= sgn[j]; if (pt < (int)((pref).size()) && pref[pt].first < bound) { pt++; } if (pt > 0 && pref[pt - 1].first >= bound) { pt--; } } ans[j] += (pt ? pref[pt - 1].second : 0); } } for (int i = lb; i < rb; i++) { int u = evs[i]; alive[u] = !alive[u]; } } for (int i = 0; i < m; i++) { cout << ans[i] << ; } }
|
#include <bits/stdc++.h> const int N = 22; const int M = (1 << 22); const int INF = 0x3f3f3f3f; bool dp[M] = {0}; int neib[N] = {0}, ex[M] = {0}; int main() { int m, n, u, v; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { neib[i] = (1 << i); dp[1 << i] = true; } for (int i = 0; i < m; ++i) { scanf( %d%d , &u, &v); --u; --v; dp[(1 << u) | (1 << v)] = true; neib[u] |= (1 << v); neib[v] |= (1 << u); } if (n == 1 || m == n * (n - 1) / 2) { printf( 0 n ); return 0; } for (int i = 0; i < (1 << n); ++i) if (dp[i]) { for (int j = 0; j < n; ++j) if (i & (1 << j)) { ex[i] |= neib[j]; } for (int j = 0; j < n; ++j) if (ex[i] & (1 << j)) { dp[i | (1 << j)] = true; } } int best = INF; std::vector<int> ans; for (int i = 0; i < (1 << n); ++i) if (dp[i] && ex[i] == (1 << n) - 1) { int cnt = 0; for (int j = 0; j < n; ++j) if (i & (1 << j)) ++cnt; if (cnt >= best) continue; best = cnt; ans.clear(); for (int j = 0; j < n; ++j) if (i & (1 << j)) ans.push_back(j); } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); ++i) printf( %d , ans[i] + 1); putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3000 + 50; const int maxm = 3000 + 50; const int maxt = 3000000 + 100; const int maxk = 10 + 3; const long long unit = 1LL; const int INF = 0x3f3f3f3f; const long long Inf = 0x3f3f3f3f3f3f3f3fLL; const double eps = 1e-3; const double inf = 1e15; const double pi = acos(-1.0); const long long mod = 1000000007LL; inline long long read() { long long x = 0; bool t = false; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = true, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return t ? -x : x; } inline long long add(long long x, long long y) { return x + y >= mod ? x + y - mod : x + y; } inline long long sub(long long x, long long y) { return x < y ? x - y + mod : x - y; } inline long long mul(long long x, long long y) { return x * y - x * y / mod * mod; } struct EasyMath { inline long long Quick_Pow(long long a, long long b) { long long sum = 1; for (; b; b >>= 1, a = (long long)a * a % mod) if (b & 1) sum = sum * a % mod; return sum; } inline long long inv(long long x) { return Quick_Pow(x, mod - 2); } } em; long long n, d; long long f[maxn][maxn], g[maxn], s[maxn][maxn], C[maxn][maxn]; long long inv[maxn], fac[maxn], ifac[maxn]; void GetInv(int n) { inv[1] = fac[0] = fac[1] = ifac[0] = ifac[1] = 1; for (register int i = (2); i <= (n); ++i) { inv[i] = ((mod - mod / i)) * inv[mod % i] % mod; fac[i] = fac[i - 1] * i % mod; ifac[i] = ifac[i - 1] * inv[i] % mod; } } struct Edge { int to, next; } edge[maxm]; int tot, head[maxn]; void init() { tot = 1; memset(head, 0, sizeof(head)); } void AddEdge(int u, int v) { edge[tot] = (Edge){v, head[u]}; head[u] = tot++; } void dfs(int u) { for (int i = head[u]; i; i = edge[i].next) { int v = edge[i].to; dfs(v); for (int j = 1; j <= n; ++j) (f[u][j] *= s[v][j]) %= mod; } for (int j = 1; j <= n; ++j) s[u][j] = (s[u][j - 1] + f[u][j]) % mod; } inline long long CC(long long n, long long m) { long long ans = 1; for (long long i = 0; i < m; ++i) (ans *= ((n - i) * inv[i + 1]) % mod) %= mod; return ans; } int main() { init(); n = read(), d = read(); GetInv(n + 10); C[0][0] = 1; for (register int i = (1); i <= (n); ++i) { C[i][0] = C[i][i] = 1; for (register int j = (1); j <= (n); ++j) { f[i][j] = 1; } for (register int j = (1); j <= (i - 1); ++j) { C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } } int x; for (register int i = (2); i <= (n); ++i) { x = read(); AddEdge(x, i); } dfs(1); for (register int j = (1); j <= (n); ++j) { g[j] = f[1][j]; for (register int i = (1); i <= (j - 1); ++i) { g[j] = ((g[j] - C[j - 1][j - i] * g[i] % mod) % mod + mod) % mod; } } long long ans = 0; for (register int i = (1); i <= (min(n, d)); ++i) { (ans += CC(d, i) * g[i] % mod) %= mod; } printf( %lld n , ans); return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Ram_Real.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 us / 1 ps
// synopsys translate_on
module Ram_Real (
address,
byteena,
clock,
data,
wren,
q);
input [9:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "TRUE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; namespace io { const int __SIZE = (1 << 21) + 1; char ibuf[__SIZE], *iS, *iT, obuf[__SIZE], *oS = obuf, *oT = oS + __SIZE - 1, __c, qu[55]; int __f, qr, _eof; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout), oS = obuf; } inline void gc(char &x) { x = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); } inline void pc(char x) { *oS++ = x; if (oS == oT) flush(); } inline void pstr(const char *s) { int __len = strlen(s); for (__f = 0; __f < __len; ++__f) pc(s[__f]); } inline void gstr(char *s) { for (__c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); __c < 32 || __c > 126 || __c == ;) __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); for (; __c > 31 && __c < 127 && __c != ; ++s, __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) *s = __c; *s = 0; } template <class I> inline bool gi(I &x) { _eof = 0; for (__f = 1, __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); (__c < 0 || __c > 9 ) && !_eof; __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) { if (__c == - ) __f = -1; _eof |= __c == EOF; } for (x = 0; __c <= 9 && __c >= 0 && !_eof; __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) x = x * 10 + (__c & 15), _eof |= __c == EOF; x *= __f; return !_eof; } template <class I> inline void print(I x) { if (!x) pc( 0 ); if (x < 0) pc( - ), x = -x; while (x) qu[++qr] = x % 10 + 0 , x /= 10; while (qr) pc(qu[qr--]); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io::gc; using io::gi; using io::gstr; using io::pc; using io::print; using io::pstr; using ll = long long; using pii = pair<int, int>; const int MOD = 1000000007; pii dat[500005 << 2]; bool laz[500005 << 2]; void push(int idx, int l, int r) { if (!laz[idx] || l == r) return; dat[idx * 2] = {dat[idx * 2].second, dat[idx * 2].first}; laz[idx * 2] = !laz[idx * 2]; dat[idx * 2 + 1] = {dat[idx * 2 + 1].second, dat[idx * 2 + 1].first}; laz[idx * 2 + 1] = !laz[idx * 2 + 1]; laz[idx] = 0; } void upd(int idx, int l, int r, int i, pii v) { if (!(l <= i && i <= r)) return; push(idx, l, r); if (l == r) { dat[idx] = v; return; } upd(idx * 2, l, (l + r) / 2, i, v); upd(idx * 2 + 1, (l + r) / 2 + 1, r, i, v); dat[idx] = {max(dat[idx * 2].first, dat[idx * 2 + 1].first), max(dat[idx * 2].second, dat[idx * 2 + 1].second)}; } void tag(int idx, int l, int r, int ql, int qr) { if (qr < l || r < ql) return; push(idx, l, r); if (ql <= l && r <= qr) { dat[idx] = {dat[idx].second, dat[idx].first}; laz[idx] = !laz[idx]; return; } tag(idx * 2, l, (l + r) / 2, ql, qr); tag(idx * 2 + 1, (l + r) / 2 + 1, r, ql, qr); dat[idx] = {max(dat[idx * 2].first, dat[idx * 2 + 1].first), max(dat[idx * 2].second, dat[idx * 2 + 1].second)}; } pii el2[500005]; vector<pii> elist[500005]; pii dfsfar(int u, int f) { pii ans = {0, u}; for (pii &v : elist[u]) if (v.first != f) ans = max(ans, dfsfar(v.first, u)); return {ans.first + 1, ans.second}; } int clck = 1; int n; int L[500005], R[500005]; int qr[500005], ans[500005]; void dfs(int u, int f, int dep, int cnt) { L[u] = clck++; if (cnt % 2 == 0) upd(1, 1, n, L[u], {dep, 0}); else upd(1, 1, n, L[u], {0, dep}); for (pii &v : elist[u]) if (v.first != f) dfs(v.first, u, dep + 1, cnt + v.second); R[u] = clck - 1; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); gi(n); for (int i = (0); i < (n - 1); i++) { int u, v, w; gi(u), gi(v), gi(w); el2[i] = {u, v}; elist[u].push_back({v, w}); elist[v].push_back({u, w}); } int root = dfsfar(1, -1).second; dfs(root, -1, 0, 0); int q; gi(q); for (int i = (0); i < (q); i++) gi(qr[i]); for (int i = (0); i < (q); i++) { int par = el2[qr[i] - 1].first, ch = el2[qr[i] - 1].second; if (R[par] - L[par] < R[ch] - L[ch]) swap(par, ch); tag(1, 1, n, L[ch], R[ch]); ans[i] = max(ans[i], dat[1].first); } root = dfsfar(root, -1).second; memset(dat, 0, sizeof dat); memset(laz, 0, sizeof laz); clck = 1; dfs(root, -1, 0, 0); for (int i = (0); i < (q); i++) { int par = el2[qr[i] - 1].first, ch = el2[qr[i] - 1].second; if (R[par] - L[par] < R[ch] - L[ch]) swap(par, ch); tag(1, 1, n, L[ch], R[ch]); ans[i] = max(ans[i], dat[1].first); print(ans[i]), pc( n ); } }
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#include <bits/stdc++.h> using namespace std; void swap(long long &a, long long &b) { auto tm = a; a = b; b = tm; } const long long mod = 1000000009; const long long mod2 = 998244353; const long long INF = (1LL << 20) - 1; const long long N = 2e5 + 25; long long n, m, a, b; vector<long long> v[N]; set<long long> c, d; bool vt[N]; void dfs1(long long x) { vt[x] = 1; for (auto &(i) : (v[x])) { if (i == b) { c.insert(x); continue; } if (vt[i] == 0) dfs1(i); } } void dfs2(long long x) { vt[x] = 1; for (auto &(i) : (v[x])) { if (i == a) { d.insert(x); continue; } if (vt[i] == 0) dfs2(i); } } void bheja_fry() { c.clear(); d.clear(); cin >> n >> m >> a >> b; for (long long(i) = (0); (i) < (n + 1); ++(i)) { v[i].clear(); vt[i] = 0; } long long x, y; for (long long(i) = (0); (i) < (m); ++(i)) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } long long ct1 = 0, ct2 = 0; dfs1(a); for (long long(i) = (0); (i) < (n + 1); ++(i)) vt[i] = 0; dfs2(b); queue<long long> q; for (auto &(i) : (v[b])) { if (c.find(i) == c.end()) q.push(i); } for (long long(i) = (0); (i) < (n + 1); ++(i)) vt[i] = 0; vt[b] = 1; while (!q.empty()) { x = q.front(); q.pop(); if (vt[x]) continue; ct1++; vt[x] = 1; for (auto &(i) : (v[x])) { if (vt[i] == 0) q.push(i); } } for (auto &(i) : (v[a])) { if (d.find(i) == d.end()) q.push(i); } for (long long(i) = (0); (i) < (n + 1); ++(i)) vt[i] = 0; vt[a] = 1; while (!q.empty()) { x = q.front(); q.pop(); if (vt[x]) continue; ct2++; vt[x] = 1; for (auto &(i) : (v[x])) { if (vt[i] == 0) q.push(i); } } cout << ct1 * ct2; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; for (long long(i) = (1); (i) < (t + 1); ++(i)) { bheja_fry(); if (i < t) cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, i, x, y, s, p; cin >> n >> m; s = 0; k = 1; for (i = 1; i <= n; i++) { cin >> x >> y; k = x - k; p = k % m; x -= p; s += y - x + 1; k = y + 1; } cout << s << endl; }
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#include <bits/stdc++.h> using namespace std; int n, m; char arr[1503][1503]; int inix, iniy; bool visit[4503][4504]; int X[] = {0, 0, 1, -1}; int Y[] = {1, -1, 0, 0}; int nn, mm; int colax[4503 * 4503]; int colay[4503 * 4503]; bool dentro(int a, int b) { if (a < 0 || b < 0 || a >= nn || b >= mm) return false; return true; } inline void bfs(int x, int y) { visit[x][y] = true; int xx, yy; int q = 0; colax[q] = x; colay[q++] = y; for (int j = 0; j < q; j++) { x = colax[j]; y = colay[j]; for (int i = 0; i < 4; i++) { xx = x + X[i]; yy = y + Y[i]; if (!visit[(xx + nn) % nn][(yy + mm) % mm] && arr[(xx + n) % n][(yy + m) % m] != # ) { visit[(xx + nn) % nn][(yy + mm) % mm] = true; colax[q] = (xx + nn) % nn; colay[q++] = (yy + mm) % mm; } } } } int main() { scanf( %d %d , &n, &m); nn = n * 3; mm = m * 3; for (int i = 0; i < n; i++) scanf( %s , arr[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (arr[i][j] == S ) { inix = i, iniy = j; }; iniy += m; inix += n; bfs(inix, iniy); for (int i = -1; i < 2; i++) for (int j = -1; j < 2; j++) { if (i == j && i == 0) continue; if (visit[inix + i * n][iniy + j * m]) { cout << Yes << endl; return 0; } } cout << No << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100111; long long n, arr[N], x, k; int main() { cin >> n; while (n--) { cin >> k >> x; long long u = 9 * k; cout << u - (9 - x) << endl; } }
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module add_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b1_100; // + -1/2
// -3/2
#5
a = 3'b0_1_1; // 3/2
b = 4'b1_110; // + -1/4
// 5/4
#10 ;
$finish;
end //initial
add #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule //add_tb
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#include <bits/stdc++.h> using namespace std; int n; int da[550]; int dp[550][1050]; int dp2[550][550]; struct kutija { int in, out, w, s, v; } K[505]; bool cmp(const kutija &a, const kutija &b) { if (a.in != b.in) return a.in < b.in; if (a.out != b.out) return a.out > b.out; return a.s > b.s; } int rek(int x, int g) { if (g < 0) return -1e9; if (x == n + 1) return 0; if (dp[x][g] != -1) return dp[x][g]; memset(dp2[x], 0, sizeof dp2[x]); for (int i = x + 1; i <= n; i++) { dp2[x][i + 1] = max(dp2[x][i + 1], dp2[x][i]); if (K[i].in >= K[x].out || K[i].out > K[x].out) continue; dp2[x][da[i]] = max(dp2[x][da[i]], dp2[x][i] + K[i].v + rek(i, min(K[i].s, g - K[i].w))); } dp[x][g] = dp2[x][n + 1]; return dp2[x][n + 1]; } int main(void) { scanf( %d%d , &n, &K[0].s); K[0].in = 0; K[0].out = 2 * n; K[0].w = 0; K[0].v = 0; for (int i = 1; i <= n; i++) scanf( %d%d%d%d%d , &K[i].in, &K[i].out, &K[i].w, &K[i].s, &K[i].v); sort(K, K + n + 1, cmp); memset(dp, -1, sizeof dp); for (int i = 0; i <= n; i++) { da[i] = n + 1; for (int j = 0; j < n + 1; j++) { if (K[i].out <= K[j].in) { da[i] = j; break; } } } printf( %d , rek(0, K[0].s)); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int a[maxn], b[maxn]; int main() { int n, x, T; cin >> T; while (T--) { cin >> n; set<int> s; s.clear(); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); } int l = 1, r = n; while (l <= n && a[l] == b[l]) l++; while (r >= 1 && a[r] == b[r]) r--; if (l > r) { cout << YES n ; continue; } int flag = 1; if (a[l] - b[l] > 0) flag = 0; for (int i = l + 1; i <= r; i++) { if (a[l] - b[l] != a[i] - b[i]) flag = 0; } if (flag) cout << YES n ; else cout << NO n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n + 1]; int b[2 * n + 1]; int temp[2 * n + 1]; for (int i = 1; i <= 2 * n; i++) temp[i] = 0; bool con1 = false, con2 = false; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 1) con1 = true; if (a[i] == 2 * n) con2 = true; temp[a[i]] = 1; } if (con1 == false or con2 == true) cout << -1 << endl; else { int check = 0; for (int i = 1; i <= n; i++) { b[2 * i - 1] = a[i]; int j; for (j = a[i] + 1; j <= 2 * n; j++) { if (temp[j] == 0) { temp[j] = 1; b[2 * i] = j; break; } } if (j == 2 * n + 1) { check = -1; } } if (check != -1) { for (int i = 1; i <= 2 * n; i++) cout << b[i] << ; cout << endl; } else cout << -1 << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using db = long double; using pl = pair<ll, ll>; using pi = pair<int, int>; vector<pi> viz[100010]; pi p[100010]; double num[100010]; bool no; set<int> val; vector<int> in; void dfs(int u) { in.push_back(u); for (auto x : viz[u]) { int v = x.first, c = x.second; if (p[v].first != 0) { if (p[v].first != p[u].first) { if ((p[v].second == c - p[u].second)) continue; else no = true; } if (p[v].first == p[u].first) { val.insert((c - p[v].second - p[u].second) * p[v].first); } } else { p[v].first = -p[u].first; p[v].second = c - p[u].second; dfs(v); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int a, b, c; cin >> a >> b >> c; viz[a].push_back({b, c}); viz[b].push_back({a, c}); } no = false; for (int i = 1; i <= n; i++) { if (p[i].first == 0) { val.clear(); in.clear(); p[i] = {1, 0}; dfs(i); if (val.size() > 1) no = true; if (val.size() == 0) { vector<int> fd; for (auto x : in) fd.push_back(p[x].first * p[x].second); sort(begin(fd), end(fd)); int c = -fd[fd.size() / 2]; for (auto x : in) num[x] = (double)p[x].first * c + p[x].second; } else { double c = (double)*val.begin() / 2; for (auto x : in) num[x] = (double)p[x].first * c + p[x].second; } } } if (no) cout << NO << endl; else { cout << YES << endl; for (int i = 1; i <= n; i++) cout << num[i] << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; bool ans[310000]; struct Query { int x1, y1, x2, y2, id; } querys[310000]; bool operator<(Query a, Query b) { return a.x2 < b.x2; } struct Point { int x, y; } points[310000]; bool operator<(Point a, Point b) { return a.x < b.x; } int minv[310000 << 2]; void pushup(int o) { minv[o] = min(minv[((o) << 1)], minv[((o) << 1 | 1)]); } void update(int o, int L, int R, int x, int val) { if (L == R) { minv[o] = val; return; } int M = (L + R) >> 1; if (x <= M) update(((o) << 1), L, M, x, val); else update(((o) << 1 | 1), M + 1, R, x, val); pushup(o); } int query(int o, int L, int R, int ql, int qr) { if (ql <= L && R <= qr) return minv[o]; int M = (L + R) >> 1; int ans = 0x3f3f3f3f; if (ql <= M) ans = min(ans, query(((o) << 1), L, M, ql, qr)); if (qr > M) ans = min(ans, query(((o) << 1 | 1), M + 1, R, ql, qr)); return ans; } int main() { int n, m, t, q; scanf( %d%d%d%d , &n, &m, &t, &q); for (int i = 1; i <= t; i++) scanf( %d%d , &points[i].x, &points[i].y); for (int i = 1; i <= q; i++) scanf( %d%d%d%d , &querys[i].x1, &querys[i].y1, &querys[i].x2, &querys[i].y2), querys[i].id = i; sort(points + 1, points + t + 1); sort(querys + 1, querys + q + 1); for (int i = 1, j = 1; i <= q; i++) { while (j <= t && points[j].x <= querys[i].x2) { update(1, 1, m, points[j].y, points[j].x); j++; } ans[querys[i].id] |= query(1, 1, m, querys[i].y1, querys[i].y2) >= querys[i].x1; } swap(n, m); for (int i = 1; i <= t; i++) swap(points[i].x, points[i].y); for (int i = 1; i <= q; i++) { swap(querys[i].x1, querys[i].y1); swap(querys[i].x2, querys[i].y2); } sort(points + 1, points + t + 1); sort(querys + 1, querys + q + 1); memset(minv, 0, sizeof(minv)); for (int i = 1, j = 1; i <= q; i++) { while (j <= t && points[j].x <= querys[i].x2) { update(1, 1, m, points[j].y, points[j].x); j++; } ans[querys[i].id] |= query(1, 1, m, querys[i].y1, querys[i].y2) >= querys[i].x1; } for (int i = 1; i <= q; i++) { if (ans[i]) printf( YES n ); else printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_SYMBOL_V
`define SKY130_FD_SC_LP__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const string FILENAME = input ; vector<pair<int, int> > best; vector<int> a; int main() { int n, m; cin >> n >> m; vector<int> has(2 * n, 0); vector<int> pr(2 * n, -1); vector<pair<int, int> > next(2 * n, {0, 0}); for (int i = 0; i < 2 * n; i++) { int t; cin >> t; a.push_back(t); next[i] = {-a[i], i}; } sort((next).begin(), (next).end()); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; pr[x] = y; pr[y] = x; if (a[x] > a[y]) { swap(x, y); } best.push_back({y, x}); } int ans; int cnt = 0; int t; cin >> t; if (t == 1) { for (int i = 0; i < m; i++) { cout << best[i].first + 1 << endl; cin >> ans; if (ans == -1) return 0; has[best[i].first] = 1; has[ans - 1] = 1; } for (int i = 0; i < 2 * n; i++) { if (has[next[i].second] == 0) { cout << next[i].second + 1 << endl; cin >> ans; if (ans == -1) return 0; has[ans - 1] = 1; has[next[i].second] = 1; } } return 0; } cin >> ans; ans--; has[ans] = 1; cnt++; while (pr[ans] != -1) { cout << pr[ans] + 1 << endl; cnt++; if (cnt == 2 * n) return 0; has[pr[ans]] = 1; cin >> ans; cnt++; if (ans == -1) return 0; ans--; has[ans] = 1; } for (int i = 0; i < m; i++) { if (has[best[i].first] == 0) { has[best[i].first] = 1; cout << best[i].first + 1 << endl; cnt++; if (cnt == 2 * n) return 0; cin >> ans; cnt++; if (ans == -1) return 0; ans--; has[ans] = 1; } } for (int i = 0; i < 2 * n; i++) { if (has[next[i].second] == 0) { cout << next[i].second + 1 << endl; cnt++; if (cnt == 2 * n) return 0; cin >> ans; cnt++; if (ans == -1) return 0; ans--; has[ans] = 1; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.141592653589793238462643383; int w; int visit[37] = {0}; int Ceil(int a, int b) { if (a % b == 0) return a / b; else return (a / b) + 1; } struct TrieNode { struct TrieNode *children[37]; bool isEndofWord; int cnt[37]; int snum[37]; int visit[37]; }; TrieNode *getNode() { TrieNode *x = new TrieNode; x->isEndofWord = false; for (int i = 0; i < (37); ++i) x->children[i] = NULL; for (int i = 0; i < (37); ++i) x->cnt[i] = 0; for (int i = 0; i < (37); ++i) x->snum[i] = -1; for (int i = 0; i < (37); ++i) x->visit[i] = -1; return x; } int find(char c) { if (c == . ) { return 26; } if (c >= a && c <= z ) { return c - a ; } return 27 + c - 0 ; } void insert(TrieNode *root, string s, int num) { TrieNode *p = root; for (int i = 0; i < (s.size()); ++i) { int index; index = find(s[i]); if (!p->children[index]) { p->children[index] = getNode(); } if (p->visit[index] != num) p->cnt[index]++; p->snum[index] = num; p->visit[index] = num; p = p->children[index]; } p->isEndofWord = true; } int search(TrieNode *root, string s) { TrieNode *p = root; int ans; for (int i = 0; i < (s.size()); ++i) { int index; index = find(s[i]); if (!p->children[index]) { return 0; } ans = p->cnt[index]; w = p->snum[index]; p = p->children[index]; } return ans; } int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); int n; cin >> n; string a[n]; TrieNode *root = getNode(); int e = 0; while (n--) { string s; cin >> s; a[e] = s; e++; int y = s.size() - 1; for (int i = 0; i < (s.size()); ++i) { string str; int x = s.size() - i; str.resize(x); int q = 0; for (int j = i; j <= (y); ++j) { str[q] = s[j]; q++; } insert(root, str, e); } } int q; cin >> q; while (q--) { string s; cin >> s; int y = search(root, s); if (y == 0) { cout << 0 - << n ; } else { cout << y << << a[w - 1] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool good() { string input; cin >> input; stack<int> pm; for (int i = 0; i < input.length(); i++) if (pm.empty() || input[i] != pm.top()) pm.push(input[i]); else pm.pop(); return pm.empty(); } int main() { cout << (good() ? Yes : No ) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100001], n; int main() { int i, h; scanf( %d n , &n); for (i = 1; i <= n; ++i) scanf( %d n , &a[i]); h = a[1]; for (i = 2; i <= n; ++i) if (a[i - 1] < a[i]) h += a[i] - a[i - 1] + 1; else h += a[i - 1] - a[i] + 1; h += n; printf( %d , h); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long const N = 1e5 + 100, INF = 1ll * 1e9 * 1e9 + 100; long long n, m, s, t; long long h[N], d[N], dis[2][N], ans[N]; pair<pair<long long, long long>, long long> e[N]; vector<long long> f[N], g[N]; set<pair<long long, long long> > st; bool vis[N]; void dij(bool b, long long s) { dis[b][s] = 0; st.insert({0, s}); while (st.size()) { long long v = st.begin()->second; st.erase(st.begin()); for (long long i : g[v]) { long long u = e[i].first.first + e[i].first.second - v, w = e[i].second; if (b ^ (u != e[i].first.second)) continue; if (dis[b][v] + w < dis[b][u]) { st.erase({dis[b][u], u}); dis[b][u] = dis[b][v] + w; st.insert({dis[b][u], u}); } } } } void cut_edge(long long v = 0, long long i = -1) { long long p = (~i ? e[i].first.first + e[i].first.second - v : -1); vis[v] = 1; d[v] = h[v]; for (long long j : f[v]) { long long u = e[j].first.first + e[j].first.second - v; if (vis[u]) { if (i != j) { ans[j] = 1; d[v] = min(d[v], h[u]); if (h[u] == h[p]) ans[i] = 1; } continue; } h[u] = h[v] + 1; cut_edge(u, j); if (d[u] != h[u]) ans[j] = 1; d[v] = min(d[v], d[u]); } } int32_t main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); fill(d, d + N, INF); fill(dis[0], dis[0] + N, INF); fill(dis[1], dis[1] + N, INF); cin >> n >> m >> s >> t; s--, t--; for (long long i = 0, u, v, w; i < m; i++) { cin >> u >> v >> w; u--, v--; e[i] = {{u, v}, w}; g[u].push_back(i); g[v].push_back(i); } dij(0, s), dij(1, t); for (long long i = 0; i < m; i++) { long long u = e[i].first.first, v = e[i].first.second, w = e[i].second; long long path = dis[0][u] + w + dis[1][v]; if (path == dis[0][t]) { f[u].push_back(i); f[v].push_back(i); } else { ans[i] = path - dis[0][t] + 1; } } cut_edge(s); for (long long i = 0; i < m; i++) { long long w = e[i].second; if (w - ans[i] <= 0) cout << NO n ; else if (!ans[i]) cout << YES n ; else cout << CAN << ans[i] << n ; } }
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
`timescale 1ns / 1ps
`include "constants.vh"
module tb_Absorb;
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
reg [175:0] data;
wire [263:0] state_out;
wire rdy;
Absorb uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
integer i;
integer databitlen;
integer counter;
initial begin
databitlen = 176;
data = "Hello WorldHello World";
counter = 0;
state_in = 0;
clk = 0;
rst = 1;
en = 0;
#100;
rst = 0;
$display("[INITIALIZING]");
// for (i=0; i<`nSBox; i=i+1) begin
// state_in = state_in | i<<(i*8);
// end
state_in = 0;
en = 1;
while (databitlen >= `rate) begin
$display("counter %d", counter);
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state_in[i+:8] = state_in[i+:8] ^ data[databitlen - (i+8) +:8];
$display("data: %d %h", databitlen - (i+8), data[databitlen - (i+8) +:8]);
end
$display("state in: %h", state_in);
$display("data: %h", data);
repeat(70*135) begin
#5;
end
if (rdy) begin
state_in = state_out;
$display("state_out: %h", state_out);
counter = counter + 1;
databitlen = databitlen - `rate;
end
end
end
always begin
#5; clk = !clk;
end
always @ (rdy) begin
if (rdy == 1) begin
state_in = state_out;
$display("state_out: %h", state_out);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_SYMBOL_V
`define SKY130_FD_SC_MS__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j; const double eps = 1e-9; struct nd { double x, y; }; nd operator-(nd x, nd y) { return (nd){x.x - y.x, x.y - y.y}; } bool cmp(nd x, nd y) { if (x.x == y.x) return x.y < y.y; return x.x < y.x; } double dis(nd x, nd y) { return abs(x.x - y.x) + abs(x.y - y.y); } double dis2(nd x, nd y) { return sqrt((x.x - y.x) * (x.x - y.x) + (x.y - y.y) * (x.y - y.y)); } double crs(nd x, nd y) { return x.x * y.y - x.y * y.x; } vector<nd> all, cov; nd stk[2000005]; int tp; void update1(nd x) { if (0 <= x.x && x.x <= 1e5 && 0 <= x.y && x.y <= 1e5) all.push_back(x); } void update2(nd p, double r, nd x) { if (dis(p, x) <= r) all.push_back(x); } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { double x, y, r; scanf( %lf%lf%lf , &x, &y, &r); if (x + r <= 1e5) update1((nd){x + r, y}); else { update1((nd){1e5, y - (r - (1e5 - x))}); update1((nd){1e5, y + (r - (1e5 - x))}); } if (x - r >= 0) update1((nd){x - r, y}); else { update1((nd){0, y - (r - x)}); update1((nd){0, y + (r - x)}); } if (y + r <= 1e5) update1((nd){x, y + r}); else { update1((nd){x - (r - (1e5 - y)), 1e5}); update1((nd){x + (r - (1e5 - y)), 1e5}); } if (y - r >= 0) update1((nd){x, y - r}); else { update1((nd){x - (r - y), 0}); update1((nd){x + (r - y), 0}); } update2((nd){x, y}, r, (nd){0, 0}); update2((nd){x, y}, r, (nd){0, 1e5}); update2((nd){x, y}, r, (nd){1e5, 0}); update2((nd){x, y}, r, (nd){1e5, 1e5}); } sort(all.begin(), all.end(), cmp); stk[tp = 1] = all[0]; for (i = 1; i < all.size(); i++) { if (all[i].x == all[i - 1].x && all[i].y == all[i - 1].y) continue; while (tp > 1 && crs(stk[tp] - stk[tp - 1], all[i] - stk[tp]) > -eps) tp--; stk[++tp] = all[i]; } for (i = 1; i < tp; i++) cov.push_back(stk[i]); reverse(all.begin(), all.end()); stk[tp = 1] = all[0]; for (i = 1; i < all.size(); i++) { if (all[i].x == all[i - 1].x && all[i].y == all[i - 1].y) continue; while (tp > 1 && crs(stk[tp] - stk[tp - 1], all[i] - stk[tp]) > -eps) tp--; stk[++tp] = all[i]; } for (i = 1; i < tp; i++) cov.push_back(stk[i]); double ans = -1e18; int res = 0; for (i = 0; i < cov.size(); i++) { int j = (i + 1) % cov.size(); int k = (i + 2) % cov.size(); double tmp = dis2(cov[i], cov[j]) * dis2(cov[i], cov[k]) * dis2(cov[j], cov[k]) / 4 / abs(crs(cov[j] - cov[i], cov[k] - cov[i]) / 2); if (tmp > ans) { ans = tmp; res = i; } } printf( %.0f %.0f n , cov[res].x, cov[res].y); printf( %.0f %.0f n , cov[(res + 1) % cov.size()].x, cov[(res + 1) % cov.size()].y); printf( %.0f %.0f n , cov[(res + 2) % cov.size()].x, cov[(res + 2) % cov.size()].y); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_BLACKBOX_V
|
`timescale 1ns / 1ps
module sim_menu;
// Inputs
reg clk;
reg reset;
reg boton_arriba;
reg boton_abajo;
reg boton_izq;
reg boton_der;
reg boton_elige;
// Outputs
wire text_red;
wire text_green;
wire text_blue;
wire [9:0] char_scale;
wire es_mayuscula;
wire nuevo;
wire guardar;
wire cerrar;
wire [2:0] where_fila;
wire [2:0] where_columna;
// Instantiate the Unit Under Test (UUT)
Controlador_Menu_Editor uut (
.clk(clk),
.reset(reset),
.boton_arriba(boton_arriba),
.boton_abajo(boton_abajo),
.boton_izq(boton_izq),
.boton_der(boton_der),
.boton_elige(boton_elige),
.text_red(text_red),
.text_green(text_green),
.text_blue(text_blue),
.char_scale(char_scale),
.es_mayuscula(es_mayuscula),
.nuevo(nuevo),
.guardar(guardar),
.cerrar(cerrar),
.where_fila(where_fila),
.where_columna(where_columna)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 1;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
end
endmodule
|
// -----------------------------------------------------------------------------
//
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : delay.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHORS EMAIL :
//
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module delay
//----------- Parameters Declarations -------------------------------------------
#(
parameter DELAY = 128
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_n_i,
input sig_i,
output reg sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DELAY-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_n_i == 0)
begin
shift_reg <= 0;
sig_o <= 0;
end
else
begin
shift_reg <= {shift_reg[DELAY-2:0], sig_i};
sig_o <= shift_reg[DELAY-1];
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sub_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Titor - Barrel Processor - A convenience module for referencing fields of the instruction
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Splitter
`else
`define INC_Splitter
`timescale 1 ns / 100 ps
// Combinational module
// splits the instruction into constituent pieces
module Splitter (
instruction,
fld_opcode,
fld_affect,
fld_field0,
fld_field1,
fld_field2,
fld_shift_type,
fld_shift_IR,
fld_shamt_S,
fld_shamt_I,
fld_shamt_R,
fld_immediate
);
`include "definition/Definition.v"
input [WORD-1 :0] instruction;
output reg [WIDTH_OPCODE-1 :0] fld_opcode;
output reg [WIDTH_AFFECT-1 :0] fld_affect;
output reg [WIDTH_FIELD0-1 :0] fld_field0;
output reg [WIDTH_FIELD1-1 :0] fld_field1;
output reg [WIDTH_FIELD2-1 :0] fld_field2;
output reg [WIDTH_SHIFT_TYPE-1 :0] fld_shift_type;
output reg [WIDTH_SHIFT_IR-1 :0] fld_shift_IR;
output reg [WIDTH_SHAMT_S-1 :0] fld_shamt_S;
output reg [WIDTH_SHAMT_I-1 :0] fld_shamt_I;
output reg [WIDTH_SHAMT_R-1 :0] fld_shamt_R;
output reg [WIDTH_IMMEDIATE-1 :0] fld_immediate;
always @(*) begin
fld_opcode <= instruction[VECT_OPCODE_H :VECT_OPCODE_L];
fld_affect <= instruction[VECT_AFFECT_H :VECT_AFFECT_L];
fld_field0 <= instruction[VECT_FIELD0_H :VECT_FIELD0_L];
fld_field1 <= instruction[VECT_FIELD1_H :VECT_FIELD1_L];
fld_field2 <= instruction[VECT_FIELD2_H :VECT_FIELD2_L];
fld_shift_type <= instruction[VECT_SHIFT_TYPE_H :VECT_SHIFT_TYPE_L];
fld_shift_IR <= instruction[VECT_SHIFT_IR_H :VECT_SHIFT_IR_L];
fld_shamt_S <= instruction[VECT_SHAMT_S_H :VECT_SHAMT_S_L];
fld_shamt_I <= instruction[VECT_SHAMT_I_H :VECT_SHAMT_I_L];
fld_shamt_R <= instruction[VECT_SHAMT_R_H :VECT_SHAMT_R_L];
fld_immediate <= instruction[VECT_IMMEDIATE_H :VECT_IMMEDIATE_L];
end
endmodule
`endif
|
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