text
stringlengths 59
71.4k
|
|---|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file read operands mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Mux for two register file read operands. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_operandmuxes.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:05 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_operandmuxes(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] ex_forw;
input [width-1:0] wb_forw;
input [width-1:0] simm;
input [`OR1200_SEL_WIDTH-1:0] sel_a;
input [`OR1200_SEL_WIDTH-1:0] sel_b;
output [width-1:0] operand_a;
output [width-1:0] operand_b;
output [width-1:0] muxed_b;
//
// Internal wires and regs
//
reg [width-1:0] operand_a;
reg [width-1:0] operand_b;
reg [width-1:0] muxed_a;
reg [width-1:0] muxed_b;
reg saved_a;
reg saved_b;
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_a <= #1 32'd0;
saved_a <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
saved_a <= #1 1'b1;
end else if (!ex_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
end else if (!ex_freeze && !id_freeze)
saved_a <= #1 1'b0;
end
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_b <= #1 32'd0;
saved_b <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
saved_b <= #1 1'b1;
end else if (!ex_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
end else if (!ex_freeze && !id_freeze)
saved_b <= #1 1'b0;
end
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_a = wb_forw;
default:
muxed_a = rf_dataa;
endcase
end
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
`OR1200_SEL_EX_FORW:
muxed_b = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_b = wb_forw;
default:
muxed_b = rf_datab;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool m[1001][1001]; bool ff[1001][1001]; int n, num; int ans; int main() { cin >> n >> num; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= i + num; j++) if (!m[i][(j - 1) % n + 1]) { m[i][(j - 1) % n + 1] = true; m[(j - 1) % n + 1][i] = true; ff[i][(j - 1) % n + 1] = true; } else { cout << -1 << endl; return 0; } if (n == 1) { cout << -1 << endl; return 0; } cout << num * n << endl; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (ff[i][j]) printf( %d %d n , i, j); }
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "intr_defs.v"
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module intr_periph
(
// General - Clocking & Reset
clk_i,
rst_i,
intr_o,
// Interrupts
intr0_i,
intr1_i,
intr2_i,
intr3_i,
intr4_i,
intr5_i,
intr6_i,
intr7_i,
intr_ext_i,
// Peripheral bus
addr_i,
data_o,
data_i,
we_i,
stb_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter EXTERNAL_INTERRUPTS = 1;
parameter INTERRUPT_COUNT = EXTERNAL_INTERRUPTS + 8;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output intr_o /*verilator public*/;
input intr0_i /*verilator public*/;
input intr1_i /*verilator public*/;
input intr2_i /*verilator public*/;
input intr3_i /*verilator public*/;
input intr4_i /*verilator public*/;
input intr5_i /*verilator public*/;
input intr6_i /*verilator public*/;
input intr7_i /*verilator public*/;
input [(EXTERNAL_INTERRUPTS - 1):0] intr_ext_i /*verilator public*/;
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input we_i /*verilator public*/;
input stb_i /*verilator public*/;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [31:0] data_o;
reg intr_o;
// IRQ Status
wire intr_in;
reg [INTERRUPT_COUNT-1:0] irq_status;
reg [INTERRUPT_COUNT-1:0] irq_mask;
reg [INTERRUPT_COUNT-1:0] v_irq_status;
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
irq_status <= {(INTERRUPT_COUNT){1'b0}};
irq_mask <= {(INTERRUPT_COUNT){1'b0}};
intr_o <= 1'b0;
end
else
begin
// Get current IRQ status
v_irq_status = irq_status;
// IRQ0
if (intr0_i == 1'b1)
v_irq_status[0] = 1'b1;
// IRQ1
if (intr1_i == 1'b1)
v_irq_status[1] = 1'b1;
// IRQ2
if (intr2_i == 1'b1)
v_irq_status[2] = 1'b1;
// IRQ3
if (intr3_i == 1'b1)
v_irq_status[3] = 1'b1;
// IRQ4
if (intr4_i == 1'b1)
v_irq_status[4] = 1'b1;
// IRQ5
if (intr5_i == 1'b1)
v_irq_status[5] = 1'b1;
// IRQ6
if (intr6_i == 1'b1)
v_irq_status[6] = 1'b1;
// IRQ7
if (intr7_i == 1'b1)
v_irq_status[7] = 1'b1;
// External interrupts
begin : ext_ints_loop
integer i;
for (i=0; i< EXTERNAL_INTERRUPTS; i=i+1)
begin
if (intr_ext_i[i] == 1'b1)
v_irq_status[(`IRQ_EXT_FIRST + i)] = 1'b1;
end
end
// Update IRQ status
irq_status <= v_irq_status;
// Generate interrupt based on masked status
intr_o <= ((v_irq_status & irq_mask) != {(INTERRUPT_COUNT){1'b0}}) ? 1'b1 : 1'b0;
// Write Cycle
if (we_i & stb_i)
begin
case (addr_i)
`IRQ_MASK_SET :
irq_mask <= (irq_mask | data_i[INTERRUPT_COUNT-1:0]);
`IRQ_MASK_CLR :
irq_mask <= (irq_mask & ~ (data_i[INTERRUPT_COUNT-1:0]));
`IRQ_STATUS : // (IRQ Acknowledge)
irq_status <= (v_irq_status & ~ (data_i[INTERRUPT_COUNT-1:0]));
default :
;
endcase
end
end
end
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ *
begin
case (addr_i[7:0])
`IRQ_MASK_SET :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
`IRQ_MASK_CLR :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
`IRQ_STATUS :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
default :
data_o = 32'h00000000;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const long long N = (long long)1e5 * 4; const long long INF = (long long)1e18; const double eps = (double)1e-6; string s; vector<long long> v; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s; long long cnt = 0, col = 0; s += a ; bool ok = 0; for (long long i = 1; i < (long long)(s.size()); ++i) { if (s[i] == o ) { col++; } if (s[i] == s[i - 1] && s[i] == v ) { if (col != 0 && (long long)(v.size()) != 0) v.push_back(col); col = 0; cnt++; } else { if (cnt != 0) v.push_back(cnt); cnt = 0; } } long long sum = 0; for (long long i = 0; i < (long long)(v.size()); ++i) { if (i % 2 == 0) sum += v[i]; } long long ans = 0; cnt = 0; for (long long i = 0; i < (long long)(v.size()); ++i) { if (i % 2 == 0) { cnt += v[i]; sum -= v[i]; } else { ans += (cnt * v[i]) * sum; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_1_V
`define SKY130_FD_SC_HS__A221O_1_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_1_V
|
#include <bits/stdc++.h> int main() { srand(1598743157); int v[4]; for (int i = 0; i < 4; i++) scanf( %d , &v[i]); while (v[0] != 1 || v[1] != 1 || v[2] != 1 || v[3] != 1) { bool ok = true; bool was = false; while (ok) { ok = false; for (int i = 0; i < 4; i++) if (v[i] % 2 == 0 && v[(i + 1) % 4] % 2 == 0) { printf( /%d n , i + 1); v[i] /= 2; v[(i + 1) % 4] /= 2; ok = true; was = true; } } if (was) continue; int i = rand() % 4; printf( +%d n , i + 1); v[i]++; v[(i + 1) % 4]++; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_SYMBOL_V
`define SKY130_FD_SC_MS__AND4_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, a[4], num, sum; string s[4], str; bool check(char ch) { return ch == a || ch == e || ch == i || ch == o || ch == u ; } int work() { sum = 0; for (int i = str.length() - 1; i >= 0; i--) { sum += check(str[i]); if (sum == m) return i; } return -1; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 0; j < 4; j++) { cin >> str; num = work(); if (!~num) { puts( NO ); return 0; } s[j] = str.substr(num); } if (s[0] == s[1] && s[1] == s[2] && s[2] == s[3]) a[0] = 1; else if (s[0] == s[1] && s[2] == s[3]) a[1] = 1; else if (s[0] == s[2] && s[1] == s[3]) a[2] = 1; else if (s[0] == s[3] && s[1] == s[2]) a[3] = 1; else { puts( NO ); return 0; } } if (a[0] && !(a[1] || a[2] || a[3])) puts( aaaa ); else if (a[1] && !(a[2] || a[3])) puts( aabb ); else if (a[2] && !(a[1] || a[3])) puts( abab ); else if (a[3] && !(a[1] || a[2])) puts( abba ); else puts( NO ); return 0; }
|
/* Line buffer producing a window of inputs.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`ifndef LIB_LINE_BUFFER_V_
`define LIB_LINE_BUFFER_V_
`timescale 1ns/1ps
`include "fifo.v"
`include "tapped_fifo.v"
// This line buffer generates a "window" of pixels from an input stream, with no
// flow control. It's parameterized in four ways:
// WIDTH: Wordsize
// LINE_LENGTH: Length of each line
// NUM_LINES: How many lines to buffer
// WINDOW_WIDTH: How wide the window should be.
//
// The first line is just the tapped fifo, of WINDOW_WIDTH width, and after
// that, each line is a vanilla fifo of (LINE_LENGTH-WINDOW_WIDTH) length, and
// a tapped fifo of length WINDOW_LENGTH.
//
// In essence, if + is a tapped buffer, and - is a plain FIFO, for a 5x5 window
// with a line length of 20:
//
// in>+++++>1
// 1>---------------+++++>2
// 2>---------------+++++>3
// 3>---------------+++++>4
// 4>---------------+++++
//
// Where 1 is connected to 1, 2 is connected to 2, and so on.
module line_buffer#(
parameter WIDTH=1,
parameter LINE_LENGTH=1,
parameter NUM_LINES=1,
parameter WINDOW_WIDTH=1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] inp,
output wire [WIDTH*NUM_LINES*WINDOW_WIDTH-1:0] outp
);
localparam OUT_WIDTH = WIDTH*NUM_LINES*WINDOW_WIDTH;
localparam TAP_WIDTH = WIDTH*WINDOW_WIDTH;
wire[WIDTH*WINDOW_WIDTH-1:0] window_line[NUM_LINES];
wire[WIDTH-1:0] next_line[NUM_LINES];
tapped_fifo#(.WIDTH(WIDTH), .DEPTH(WINDOW_WIDTH))
tf(clk, rst, inp, window_line[0], next_line[0]);
assign outp[(OUT_WIDTH-1):(OUT_WIDTH-TAP_WIDTH)] = window_line[0];
genvar i;
generate
for (i = 1; i < NUM_LINES; i++) begin : lines
wire[WIDTH-1:0] connection;
fifo#(.WIDTH(WIDTH), .DEPTH(LINE_LENGTH-WINDOW_WIDTH))
f(clk, rst, next_line[i-1], connection);
tapped_fifo#(.WIDTH(WIDTH), .DEPTH(WINDOW_WIDTH))
tf(clk, rst, connection, window_line[i], next_line[i]);
assign outp[(OUT_WIDTH-TAP_WIDTH*(i)-1):(OUT_WIDTH-TAP_WIDTH*(i+1))] =
window_line[i];
end
endgenerate
endmodule
`endif // LIB_LINE_BUFFER_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_TB_V
`define SKY130_FD_SC_LS__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<int> v1[3010], v2[3010]; int dista[3010][3010], distb[3010][3010]; pair<int, int> besta[3010][3], bestb[3010][3]; int n, m; void dijkstra(int x) { for (int i = 1; i <= n; i++) dista[x][i] = 1000000009; dista[x][x] = 0; priority_queue<pair<int, int> > q; q.push(make_pair(0, x)); while (!q.empty()) { pair<int, int> t = q.top(); q.pop(); int u = t.second; for (int i = 0; i < v1[u].size(); i++) { if (dista[x][v1[u][i]] > dista[x][u] + 1) { dista[x][v1[u][i]] = dista[x][u] + 1; q.push(make_pair(-dista[x][v1[u][i]], v1[u][i])); } } } for (int i = 1; i <= n; i++) { if (dista[x][i] != 1000000009 && dista[x][i] > besta[x][0].first) besta[x][2] = besta[x][1], besta[x][1] = besta[x][0], besta[x][0] = make_pair(dista[x][i], i); else if (dista[x][i] != 1000000009 && dista[x][i] > besta[x][1].first) besta[x][2] = besta[x][1], besta[x][1] = make_pair(dista[x][i], i); else if (dista[x][i] != 1000000009 && dista[x][i] > besta[x][2].first) besta[x][2] = make_pair(dista[x][i], i); } } void dijkstra2(int x) { for (int i = 1; i <= n; i++) distb[x][i] = 1000000009; distb[x][x] = 0; priority_queue<pair<int, int> > q; q.push(make_pair(0, x)); while (!q.empty()) { pair<int, int> t = q.top(); q.pop(); int u = t.second; for (int i = 0; i < v2[u].size(); i++) { if (distb[x][v2[u][i]] > distb[x][u] + 1) { distb[x][v2[u][i]] = distb[x][u] + 1; q.push(make_pair(-distb[x][v2[u][i]], v2[u][i])); } } } for (int i = 1; i <= n; i++) { if (distb[x][i] != 1000000009 && distb[x][i] > bestb[x][0].first) bestb[x][2] = bestb[x][1], bestb[x][1] = bestb[x][0], bestb[x][0] = make_pair(distb[x][i], i); else if (distb[x][i] != 1000000009 && distb[x][i] > bestb[x][1].first) bestb[x][2] = bestb[x][1], bestb[x][1] = make_pair(distb[x][i], i); else if (distb[x][i] != 1000000009 && distb[x][i] > bestb[x][2].first) bestb[x][2] = make_pair(distb[x][i], i); } } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); v1[x].push_back(y); v2[y].push_back(x); } int ans = -1, ansa, ansb, ansc, ansd; for (int i = 1; i <= n; i++) dijkstra(i); for (int i = 1; i <= n; i++) dijkstra2(i); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { for (int a = 0; a < 3; a++) { for (int d = 0; d < 3; d++) { int aa = bestb[i][a].second, dd = besta[j][d].second; if (aa == 0 || dd == 0) continue; if (i == j || i == aa || i == dd || j == aa || j == dd || aa == dd) continue; if (bestb[i][a].first == 1000000009 || besta[j][d].first == 1000000009 || dista[i][j] == 1000000009) continue; int val = bestb[i][a].first + besta[j][d].first + dista[i][j]; if (val > ans) { ans = val; ansa = aa; ansb = i; ansc = j; ansd = dd; } } } } } cout << ansa << << ansb << << ansc << << ansd << endl; return 0; }
|
// Experiment about implementing of a 100% asynchronous "AND" function between
// request signals
// THis is just a arbitrer with the equivalent of a call function
// where xor gates have been replaced by AND gates
// using arbitrer_r1_2ph
module and_r1_2ph (/*AUTOARG*/
// Outputs
a1, a2, r,
// Inputs
r1, r2, a, rstn
);
// Input pandts
input r1;
output a1;
input r2;
output a2;
// output pandt
output r;
input a;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTANDEG*/
/*AUTOWIRE*/
wire r;
wire r1,r2;
wire a1,a2;
wire g1,g2;
wire d1,d2;
arbitrer_r1_2ph U_ARBITRER(
// Input pandts
.r1 (r1),
.a1 (a1),
.r2 (r2),
.a2 (a2),
// Output pandts
.g1 (g1),
.g2 (g2),
.d1 (d1),
.d2 (d2),
.rstn (rstn));
// Structure is similar to the call block
// replacing the xor by an and
// and also inside the decision-wait element
// UPDATE : this does not work
// The following code seems to work way better
// If port #2 is zero, then the output r
// is already zero and not ready (a==1)
// else we have to wait for a
mux2 U_MUX2_1(.z(d1pre),
.s(d2),
.a0(g1),
.a1(a));
mux2 U_MUX2_2(.z(d2pre),
.s(d1),
.a0(g2),
.a1(a));
// and2 U_AND2_1(.z(d1pre), .a(a), .b(d2));
// and2 U_AND2_2(.z(d2pre), .a(d1), .b(a));
// We need some memory to keep the feedback when state change
// on the other port
muller2 U_MULLER_ACK1(.a(g1),.b(d1pre),.rstn(rstn),.z(d1));
muller2 U_MULLER_ACK2(.a(g2),.b(d2pre),.rstn(rstn),.z(d2));
and2 U_AND2_OUT(.z(r), .a(g1), .b(g2));
endmodule // and_r1_2ph
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_nios2_qsys_0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEII",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEII",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; using pil = pair<long long, long long>; using pii = pair<long long, long long>; using pid = pair<double, double>; long long mod = 1e9 + 7; long long power(long long a, long long n) { long long res = 1; while (n) { if (n % 2) res = (res * a) % mod; a = (a * a) % mod; n /= 2; } return res; } void solve() { long long a, b; cin >> a >> b; long long B = (b * (b - 1) / 2) % mod; long long A = ((a * (a + 1) / 2) % mod) * b + a; A %= mod; long long ans = (A * B) % mod; cout << ans << endl; } int32_t main() { long long t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; static const int maxn = 3e5 + 5; signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; multiset<int> ms; for (int i = 0; i < n; i++) { int x; cin >> x; ms.insert(x); } int ans = 0; while (ms.empty() == false) { int mini = *ms.begin(); ++ans; vector<int> del; for (int x : ms) { if (x % mini == 0) del.push_back(x); } for (int x : del) ms.erase(ms.find(x)); } cout << ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_7_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_7_V
/**
* sleep_pargate_plv: ????.
*
* Verilog wrapper for sleep_pargate_plv with size of 7 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_7 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_7 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_7_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, kol = 0, sum = 0, a; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a; if (sum + a > m) { kol++; sum = a; } else sum += a; } cout << kol + 1; }
|
#include <bits/stdc++.h> using namespace std; long long n, tmp, ans, curr; string s; deque<pair<long long, long long> > v; void add(long long val, long long pos) { while (v.front().first <= val) { curr -= v.front().first * (v[1].second - v.front().second); v.pop_front(); } v.push_front({val, pos}); curr += v.front().first * (v[1].second - v.front().second); } int main() { cin >> n >> s; curr = ans = tmp = 0; v.push_front({1000000, n}); for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == 0 ) { while (tmp >= 0) { add(tmp, i + tmp); tmp--; } tmp = 0; } else { tmp++; ans += (tmp * (tmp + 1)) / 2ll; add(tmp, i + tmp); } ans += curr; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; const long double PI = atan(1) * 4; const long long M = 1000000007; struct PT { double x, y; PT() {} PT(double x, double y) : x(x), y(y) {} PT(const PT &p) : x(p.x), y(p.y) {} PT operator+(const PT &p) const { return PT(x + p.x, y + p.y); } PT operator-(const PT &p) const { return PT(x - p.x, y - p.y); } PT operator*(double c) const { return PT(x * c, y * c); } PT operator/(double c) const { return PT(x / c, y / c); } }; double dot(PT p, PT q) { return p.x * q.x + p.y * q.y; } double dist2(PT p, PT q) { return dot(p - q, p - q); } double cross(PT p, PT q) { return p.x * q.y - p.y * q.x; } double cos_u2v(const PT &u, const PT &v) { return dot(u, v) / sqrt(dot(u, u) * dot(v, v)); } double sin_u2v(const PT &u, const PT &v) { return cross(u, v) / sqrt(dot(u, u) * dot(v, v)); } ostream &operator<<(ostream &os, const PT &p) { os << ( << p.x << , << p.y << ) ; } double vector2angle(const PT &v) { return atan2(v.y, v.x); } struct UnionFind { vector<long long> C; UnionFind(long long n) : C(n) { for (int i = 0; i < n; i++) C[i] = i; } long long find(long long x) { return (C[x] == x) ? x : C[x] = find(C[x]); } void merge(long long x, long long y) { C[find(x)] = find(y); } }; long long mod(long long x, long long m) { return ((x % m) + m) % m; } long long gcd(long long a, long long b) { for (; b > 0; swap(a, b)) a %= b; return a; } long long extended_euclid(long long a, long long b, long long &x, long long &y) { long long xx = y = 0; long long yy = x = 1; while (b) { long long q = a / b; long long t = b; b = a % b; a = t; t = xx; xx = x - q * xx; x = t; t = yy; yy = y - q * yy; y = t; } return a; } long long mod_inverse(long long a, long long n) { long long x, y; long long d = extended_euclid(a, n, x, y); if (d > 1) return -1; return mod(x, n); } long long discretize(vector<long long> &x) { set<long long> avset(x.begin(), x.end()); map<long long, long long> vmap; long long dn = 0; for (auto it = avset.begin(); it != avset.end(); it++) vmap[*it] = dn++; for (long long i = 0, n = x.size(); i < n; i++) x[i] = vmap[x[i]]; return dn; } struct LPSolver { int m, n; vector<long long> B, N; vector<vector<long double>> D; LPSolver(const vector<vector<long double>> &A, const vector<long double> &b, const vector<long double> &c) : m(b.size()), n(c.size()), N(n + 1), B(m), D(m + 2, vector<long double>(n + 2)) { for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) D[i][j] = A[i][j]; for (int i = 0; i < m; i++) { B[i] = n + i; D[i][n] = -1; D[i][n + 1] = b[i]; } for (int j = 0; j < n; j++) { N[j] = j; D[m][j] = -c[j]; } N[n] = -1; D[m + 1][n] = 1; } void Pivot(int r, int s) { for (int i = 0; i < m + 2; i++) if (i != r) for (int j = 0; j < n + 2; j++) if (j != s) D[i][j] -= D[r][j] * D[i][s] / D[r][s]; for (int j = 0; j < n + 2; j++) if (j != s) D[r][j] /= D[r][s]; for (int i = 0; i < m + 2; i++) if (i != r) D[i][s] /= -D[r][s]; D[r][s] = 1.0 / D[r][s]; swap(B[r], N[s]); } bool Simplex(int phase) { int x = phase == 1 ? m + 1 : m; while (true) { int s = -1; for (int j = 0; j <= n; j++) { if (phase == 2 && N[j] == -1) continue; if (s == -1 || D[x][j] < D[x][s] || D[x][j] == D[x][s] && N[j] < N[s]) s = j; } if (D[x][s] > -EPS) return true; int r = -1; for (int i = 0; i < m; i++) { if (D[i][s] < EPS) continue; if (r == -1 || D[i][n + 1] / D[i][s] < D[r][n + 1] / D[r][s] || (D[i][n + 1] / D[i][s]) == (D[r][n + 1] / D[r][s]) && B[i] < B[r]) r = i; } if (r == -1) return false; Pivot(r, s); } } long double solve(vector<long double> &x) { int r = 0; for (int i = 1; i < m; i++) if (D[i][n + 1] < D[r][n + 1]) r = i; if (D[r][n + 1] < -EPS) { Pivot(r, n); if (!Simplex(1) || D[m + 1][n + 1] < -EPS) return -numeric_limits<long double>::infinity(); for (int i = 0; i < m; i++) if (B[i] == -1) { int s = -1; for (int j = 0; j <= n; j++) if (s == -1 || D[i][j] < D[i][s] || D[i][j] == D[i][s] && N[j] < N[s]) s = j; Pivot(i, s); } } if (!Simplex(2)) return numeric_limits<long double>::infinity(); x = vector<long double>(n); for (int i = 0; i < m; i++) if (B[i] < n) x[B[i]] = D[i][n + 1]; return D[m][n + 1]; } }; void buildadjlist(long long n, const vector<long long> &froms, const vector<long long> &tos, vector<long long> &v2e0, vector<long long> &e2n) { v2e0.resize(n); v2e0.assign(n, -1); long long en = froms.size(); e2n.resize(en); for (int i = 0; i < en; i++) { long long f = froms[i]; long long t = tos[i]; e2n[i] = v2e0[f]; v2e0[f] = i; } } void dijkstra(const vector<long long> &v2e0, const vector<long long> &e2t, const vector<long long> &e2c, const vector<long long> &e2n, long long src, vector<long long> &dist, vector<long long> &prec) { long long n = v2e0.size(); dist.resize(n); dist.assign(n, INT_MAX); prec.resize(n); prec.assign(n, -1); vector<bool> arr(n); long long sel = src; dist[sel] = 0; while (sel >= 0) { arr[sel] = true; for (long long i = v2e0[sel]; i >= 0; i = e2n[i]) { long long to = e2t[i]; long long cost = e2c[i]; if (!arr[to] && dist[to] > dist[sel] + cost) { dist[to] = dist[sel] + cost; prec[to] = sel; } } sel = -1; for (long long i = 0; i < n; i++) if (!arr[i] && (sel == -1 || dist[i] < dist[sel])) sel = i; } } void tarjan_dfs(long long v, long long &timer, long long &cn, vector<long long> &vtime, vector<long long> &rtime, const vector<long long> &v2e0, const vector<long long> &e2t, const vector<long long> &e2n, vector<long long> &v2c, stack<long long> &stk) { stk.push(v); rtime[v] = vtime[v] = timer++; for (long long i = v2e0[v]; i >= 0; i = e2n[i]) { long long w = e2t[i]; if (vtime[w] == -1) { tarjan_dfs(w, timer, cn, vtime, rtime, v2e0, e2t, e2n, v2c, stk); rtime[v] = min(rtime[v], rtime[w]); } else if (v2c[w] == -1) rtime[v] = min(rtime[v], vtime[w]); } if (vtime[v] == rtime[v]) { while (true) { long long pv = stk.top(); v2c[pv] = cn; stk.pop(); if (pv == v) break; } cn++; } } void tarjan_strong(long long n, const vector<long long> &v2e0, const vector<long long> &e2t, const vector<long long> &e2n, vector<long long> &v2c) { v2c.assign(n, -1); vector<long long> vtime(n, -1); vector<long long> rtime(n, -1); stack<long long> stk; long long timer = 0, cn = 0; for (long long i = 0; i < n; i++) { if (vtime[i] >= 0) continue; tarjan_dfs(i, timer, cn, vtime, rtime, v2e0, e2t, e2n, v2c, stk); } } struct FordFulk { const vector<long long> &v2e0; const vector<long long> &e2f; const vector<long long> &e2t; const vector<long long> &e2c; const vector<long long> &e2n; long long s, t; FordFulk(const vector<long long> &_v2e0, const vector<long long> &_e2f, const vector<long long> &_e2t, const vector<long long> &_e2c, const vector<long long> &_e2n, long long _s, long long _t) : s(_s), t(_t), v2e0(_v2e0), e2f(_e2f), e2t(_e2t), e2c(_e2c), e2n(_e2n) {} long long _find_aug_path(const vector<long long> &v2e0, const vector<long long> &e2f, const vector<long long> &e2t, const vector<long long> &e2c, const vector<long long> &e2n, long long s, long long t, vector<long long> &epath) { vector<long long> q2v; vector<long long> q2p; vector<long long> q2e; vector<long long> q2f; vector<bool> inq(v2e0.size(), false); q2v.push_back(s); q2p.push_back(-1); q2e.push_back(-1); q2f.push_back(INT_MAX); inq[s] = true; for (long long i = 0; i < q2v.size(); i++) { long long crt = q2v[i]; long long f = q2f[i]; for (long long j = v2e0[crt]; j != -1; j = e2n[j]) { long long to = e2t[j]; long long rem = e2c[j]; if (inq[to]) continue; if (rem <= 0) continue; q2v.push_back(to); q2p.push_back(i); q2e.push_back(j); q2f.push_back(min(f, rem)); inq[to] = true; } } for (long long i = 0; i < q2v.size(); i++) { if (q2v[i] != t) continue; stack<long long> stk; for (long long j = i; j > 0; j = q2p[j]) { stk.push(q2e[j]); } while (!stk.empty()) { epath.push_back(stk.top()); stk.pop(); } return q2f[i]; } return 0; } long long eval() { long long en = e2f.size(); map<pair<long long, long long>, long long> rsd; for (long long i = 0; i < en; i++) { long long f = e2f[i]; long long t = e2t[i]; rsd[make_pair(f, t)] += e2c[i]; rsd[make_pair(t, f)] += 0; } map<pair<long long, long long>, long long> nei; long long ren = 0; for (auto er : rsd) { nei[er.first] = ren++; } long long rvn = v2e0.size(); vector<long long> rv2e0(rvn, -1); vector<long long> re2f(ren); vector<long long> re2t(ren); vector<long long> re2c(ren); vector<long long> re2n(ren); vector<long long> re2p(ren); long long rei = 0; for (auto er : rsd) { long long f = er.first.first; long long t = er.first.second; long long c = er.second; re2f[rei] = f; re2t[rei] = t; re2c[rei] = c; re2p[rei] = nei[make_pair(t, f)]; re2n[rei] = rv2e0[f]; rv2e0[f] = rei; ++rei; } long long sol = 0; vector<long long> epath; while (true) { epath.clear(); long long res = _find_aug_path(rv2e0, re2f, re2t, re2c, re2n, s, t, epath); if (res == 0) break; for (auto ei : epath) { re2c[ei] -= res; re2c[re2p[ei]] += res; } sol += res; } return sol; } }; template <typename T> struct BIT1D { long long n; vector<T> v; T (*fnx)(long long, T); T (*fab)(T, T); long long rg(long long k) { return ((k ^ (k + 1)) + 1) / 2; } BIT1D(long long _n, T v0, T (*_fnx)(long long, T), T (*_fab)(T, T)) : n(_n), v(_n), fnx(_fnx), fab(_fab) { for (long long i = 0; i < n; i++) v[i] = fnx(rg(i), v0); } void update(long long i, T v1) { for (; i < n; i += rg(i)) v[i] = fab(v[i], v1); } T query(long long i) { long long j = i - rg(i); return (j < 0) ? v[i] : (query(j) + v[i]); } }; template <typename T> struct LazySegTree1D { vector<T> v; vector<long long> opr; vector<T> opd; vector<long long> nxt; long long LEFT; long long RGHT; T (*fnx)(long long, T); T (*fab)(T, T); LazySegTree1D(long long _l, long long _r, T _v, T (*_fnx)(long long, T), T (*_fab)(T, T)) : v(1), opr(1), opd(1), nxt(1), LEFT(_l), RGHT(_r), fnx(_fnx), fab(_fab) { v[0] = fnx(RGHT - LEFT + 1, _v); opr[0] = 0; opd[0] = _v; nxt[0] = -1; } void _split(long long i, long long l0, long long r0) { assert(nxt[i] == -1); assert(opr[i] == 0); assert(l0 < r0); long long n = v.size(); nxt[i] = n; long long m0 = (l0 + r0) / 2; v.push_back(fnx(m0 - l0 + 1, opd[i])); v.push_back(fnx(r0 - m0, opd[i])); opr.push_back(0); opr.push_back(0); opd.push_back(opd[i]); opd.push_back(opd[i]); nxt.push_back(-1); nxt.push_back(-1); } void _pushdown(long long i, long long l0, long long r0) { if (opr[i] == -1) return; long long m0 = (l0 + r0) / 2; if (nxt[i] == -1) _split(i, l0, r0); else if (opr[i] >= 0) { _set(nxt[i], l0, m0, l0, m0, opr[i], opd[i]); _set(nxt[i] + 1, m0 + 1, r0, m0 + 1, r0, opr[i], opd[i]); } opr[i] = -1; } void _set(long long i, long long l0, long long r0, long long l1, long long r1, long long o1, T v1) { assert(l1 >= l0 && r1 <= r0); if (l0 == l1 && r0 == r1) { if (o1 == 0) { v[i] = fnx(r0 - l0 + 1, v1); opr[i] = 0; opd[i] = v1; } else if (o1 == 1) { v[i] = fab(v[i], fnx(r0 - l0 + 1, v1)); if (opr[i] == -1) { opr[i] = 1; opd[i] = v1; } else if (opr[i] == 0) { opr[i] = 0; opd[i] = fab(opd[i], v1); } else if (opr[i] == 1) { opr[i] = 1; opd[i] = fab(opd[i], v1); } } return; } long long m0 = (l0 + r0) / 2; _pushdown(i, l0, r0); if (l1 <= m0) _set(nxt[i], l0, m0, l1, min(r1, m0), o1, v1); if (r1 > m0) _set(nxt[i] + 1, m0 + 1, r0, max(l1, m0 + 1), r1, o1, v1); v[i] = fab(v[nxt[i]], v[nxt[i] + 1]); } T _get(long long i, long long l0, long long r0, long long l1, long long r1) { assert(l0 <= l1 && r1 <= r0); if (l0 == l1 && r1 == r0) return v[i]; _pushdown(i, l0, r0); long long m0 = (l0 + r0) / 2; if (r1 <= m0) return _get(nxt[i], l0, m0, l1, r1); if (m0 + 1 <= l1) return _get(nxt[i] + 1, m0 + 1, r0, l1, r1); T lv = _get(nxt[i], l0, m0, l1, m0); T rv = _get(nxt[i] + 1, m0 + 1, r0, m0 + 1, r1); return fab(lv, rv); } void updres(long long l1, long long r1, T v1) { _set(0, LEFT, RGHT, l1, r1, 1, v1); } void setval(long long l1, long long r1, T v1) { _set(0, LEFT, RGHT, l1, r1, 0, v1); } T get(long long l1, long long r1) { return _get(0, LEFT, RGHT, l1, r1); } }; void suffix_array(const string &s, vector<long long> &sa, vector<long long> &rank) { long long n = s.size(); long long ri = 0; vector<vector<long long>> tmprank(2, vector<long long>(n)); vector<pair<pair<long long, long long>, long long>> kni(n); for (long long g = 1; g / 2 <= n - 1; g *= 2, ri = 1 - ri) { for (long long i = 0; i < n; i++) { long long key1 = (g == 1) ? s[i] : tmprank[ri][i]; long long key2 = (g == 1) ? 0 : (i + g / 2 < n) ? (tmprank[ri][i + g / 2]) : -1; kni[i] = make_pair(make_pair(key1, key2), i); } sort(kni.begin(), kni.end()); for (long long i = 0, last_rank = -1; i < n; i++) { long long this_rank = (i > 0 && kni[i].first == kni[i - 1].first) ? last_rank : i; last_rank = tmprank[1 - ri][kni[i].second] = this_rank; } } rank.resize(n); rank.assign(tmprank[ri].begin(), tmprank[ri].end()); sa.resize(n); for (long long i = 0; i < n; i++) sa[rank[i]] = i; } struct SuffixTree { string str; vector<unordered_map<long long, long long>> sta; vector<unordered_map<long long, long long>> end; vector<unordered_map<long long, long long>> nxt; vector<long long> suflink; long long capacity; long long node_count; long long act_node; long long act_br; long long act_len; long long todo_count; bool _nodehasbr(long long node, long long br) { auto m = nxt[node]; return m.find(br) != m.end(); } long long _newnode() { if (node_count < capacity) { long long newi = node_count++; suflink[newi] = -1; sta[newi].clear(); end[newi].clear(); nxt[newi].clear(); return newi; } sta.emplace_back(); end.emplace_back(); nxt.emplace_back(); suflink.push_back(-1); ++node_count; ++capacity; return node_count - 1; } long long _edgerealend(long long node, long long br) { long long tmp = end[node][br]; return (tmp == -1) ? (str.size() - 1) : tmp; } long long _edgelen(long long node, long long br) { return (br == -1) ? 0 : (!_nodehasbr(node, br)) ? 0 : (_edgerealend(node, br) - sta[node][br] + 1); } void clear() { node_count = 0; act_node = 0; act_br = -1; act_len = 0; todo_count = 0; _newnode(); } SuffixTree(long long est_strlen) { capacity = 0; if (est_strlen > 0) { long long est_nodecnt = est_strlen * 2; capacity = est_nodecnt; sta = vector<unordered_map<long long, long long>>(est_nodecnt); end = vector<unordered_map<long long, long long>>(est_nodecnt); nxt = vector<unordered_map<long long, long long>>(est_nodecnt); suflink = vector<long long>(est_nodecnt, -1); } clear(); } bool _tryextend(long long chr) { if (act_len == 0) { if (!_nodehasbr(act_node, chr)) return false; act_br = chr; ++act_len; return true; } if (act_len == _edgelen(act_node, act_br)) { long long nxtnode = nxt[act_node][act_br]; if (!_nodehasbr(nxtnode, chr)) return false; act_node = nxtnode; act_br = chr; act_len = 1; return true; } long long start = sta[act_node][act_br]; if (chr != str[start + act_len]) return false; ++act_len; return true; } void _branch(long long node, long long chr) { long long newnode = _newnode(); sta[node][chr] = str.size() - 1; end[node][chr] = -1; nxt[node][chr] = newnode; } long long _actsplit(long long chr) { long long new0 = _newnode(); long long new1 = _newnode(); long long start = sta[act_node][act_br]; sta[new0][str[start + act_len]] = start + act_len; end[new0][str[start + act_len]] = end[act_node][act_br]; nxt[new0][str[start + act_len]] = nxt[act_node][act_br]; sta[new0][chr] = str.size() - 1; end[new0][chr] = -1; nxt[new0][chr] = new1; sta[act_node][act_br] = start; end[act_node][act_br] = start + act_len - 1; nxt[act_node][act_br] = new0; return new0; } long long _splitorbranch(long long chr) { if (act_br >= 0 && act_len < _edgelen(act_node, act_br)) return _actsplit(chr); long long target_node = (act_len == 0) ? 0 : nxt[act_node][act_br]; _branch(target_node, chr); return target_node; } string _edgestr(long long node, long long br) { long long start = sta[node][br]; long long end = _edgerealend(node, br); return str.substr(start, end - start + 1); } void _actsupdate(long long node, long long br, long long len) { act_node = node, act_br = br, act_len = len; } void _actfastfwd(long long start, long long slen) { if (act_br == -1) return; while (true) { long long elen = _edgelen(act_node, act_br); if (slen <= elen) return; long long new_act_node = nxt[act_node][act_br]; long long new_act_br = str[start + elen]; long long new_act_len = act_len - elen; _actsupdate(new_act_node, new_act_br, new_act_len); start += elen; slen -= elen; } } bool _actsgotonextsuf() { if (act_len == 0) return false; long long estart = sta[act_node][act_br]; if (act_node == 0) { act_br = (act_len == 1) ? (-1) : str[estart + 1]; --act_len; _actfastfwd(estart + 1, act_len); } else { act_node = (suflink[act_node] >= 0) ? suflink[act_node] : 0; _actfastfwd(estart, act_len); } } void insert(long long chr) { str.push_back(chr); ++todo_count; long long prev_created = -1; for (long long waitlink = -1; todo_count > 0; --todo_count) { bool suffix_exists = _tryextend(chr); if (suffix_exists) { waitlink = act_node; } else { waitlink = _splitorbranch(chr); } if (prev_created >= 0) suflink[prev_created] = waitlink; prev_created = waitlink; if (suffix_exists) break; _actsgotonextsuf(); } } }; const int N = 100; int l0[N] = {}; int l1[N] = {}; int r0[N] = {}; int r1[N] = {}; int main() { srand(time(NULL)); int n, m; cin >> n >> m; int p = 1; for (int i = 0; i < n; ++i) { if (p > m) break; l0[i] = p++; if (p > m) break; r0[i] = p++; if (p > m) break; } for (int i = 0; i < n; ++i) { if (p > m) break; l1[i] = p++; if (p > m) break; r1[i] = p++; if (p > m) break; } for (int i = 0; i < n; ++i) { if (l1[i] > 0) printf( %d , l1[i]); if (l0[i] > 0) printf( %d , l0[i]); if (r1[i] > 0) printf( %d , r1[i]); if (r0[i] > 0) printf( %d , r0[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> al[100001]; long long vis[100001]; long long no(long long num) { long long min = num % 10, max = num % 10; while (num > 0) { long long a = num % 10; num /= 10; if (min > a) min = a; if (max < a) max = a; } return min * max; } int main() { long long t; cin >> t; while (t--) { long long a, k; cin >> a >> k; for (long long i = 0; i < k - 1; i++) { long long b = no(a); if (b == 0) break; a += b; } cout << a << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; long long a[200000 + 5]; int main() { long long i, j, k, l; long long n, m; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; a[n] = 2000000009; long long maxn = 0; k = 0; for (i = 1; i <= n; i++) { if (a[i] > a[i - 1] * 2) { maxn = max(maxn, i - k); k = i; } } cout << maxn << endl; }
|
#include <bits/stdc++.h> using namespace std; void showvec(vector<long long> &arr); inline void solve() { long long n; cin >> n; vector<long long> arr(n); for (long long i = 0; i < n; i++) { cin >> arr[i]; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); vector<long long> arr(200005); long long t = 1; cin >> t; while (t--) { long long n; cin >> n; fill(arr.begin(), arr.end(), -1); long long ans = INT_MAX; for (long long i = 0; i < n; i++) { long long ele; cin >> ele; if (arr[ele] != -1) { ans = min(ans, i - arr[ele] + 1); } arr[ele] = i; } cout << (ans == INT_MAX ? -1 : ans); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int tree[100010 << 2]; bool flag; struct node { int row, col, pos; friend bool operator<(node a, node b) { if (a.row == b.row) return a.col < b.col; return a.row < b.row; } }; node p[100010]; inline void pushUp(int rt) { tree[rt] = min(tree[rt << 1], tree[rt << 1 | 1]); } void update(int x, int y, int val, int L, int R, int rt) { if (flag) return; if (L == R) { if (tree[rt] == 0) { flag = true; tree[rt] = val; } return; } else if (x <= L && R <= y) { int mid = (L + R) >> 1; if (tree[rt << 1] == 0) update(x, y, val, L, mid, rt << 1); else if (tree[rt << 1 | 1] == 0) update(x, y, val, mid + 1, R, rt << 1 | 1); } else { int mid = (L + R) >> 1; if (x <= mid) update(x, y, val, L, mid, rt << 1); if (y > mid) update(x, y, val, mid + 1, R, rt << 1 | 1); } pushUp(rt); } void out(int L, int R, int rt) { if (L == R) { if (tree[rt]) printf( %d , tree[rt]); } else { int mid = (L + R) >> 1; out(L, mid, rt << 1); out(mid + 1, R, rt << 1 | 1); } } int main() { int i; int n, m, cnt; while (~scanf( %d%d , &n, &m)) { memset(tree, 0, sizeof(tree)); for (i = 0; i < m; i++) { scanf( %d%d , &p[i].row, &p[i].col); p[i].pos = i + 1; } sort(p, p + m); for (cnt = i = 0; i < m; i++) { flag = false; update(n - p[i].col + 1, p[i].row, p[i].pos, 1, n, 1); if (flag) cnt++; } printf( %d n , cnt); out(1, n, 1); putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int pushes = 0; int buttons; cin >> buttons; for (int i = 1; i <= buttons; i++) { pushes += 1 + (i * (buttons - i)); } cout << pushes << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; vector<int> V; bool solve(int n); int main() { ios_base::sync_with_stdio(false); int i, st, dr, mid; cin >> N; V.resize(N); for (i = 0; i < N; ++i) { cin >> V[i]; } sort(V.begin(), V.end()); st = 1; dr = N; while (st < dr) { mid = (st + dr) / 2; if (solve(mid)) { dr = mid; } else { st = mid + 1; } } cout << dr << n ; return 0; } bool solve(int n) { int i, j, nr; vector<int> piles; piles.resize(n, 101); j = 0; for (i = N - 1; i >= 0; --i) { nr = 0; while (piles[j] == 0) { ++j; ++nr; if (j == n) j = 0; if (nr == n + 1) break; } if (nr == n + 1) break; piles[j] = min(piles[j] - 1, V[i]); ++j; if (j == n) j = 0; } if (i == -1) { return true; } return false; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:11 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.4 2005/11/30 14:04:15 wig Exp $
// $Date: 2005/11/30 14:04:15 $
// $Log: ent_bb.v,v $
// Revision 1.4 2005/11/30 14:04:15 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/***********************************************************************
WISHBONE miscellaneous timer
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Implements the micro and milliseconds timers. Also a CPU blocker,
used for small time delays.
This module also implements the 6 PWMs.
Lower 32 bits is a 32 bits microseconds counter
Upper 32 bits is a milliseconds counter
Port Read Write
0 µs B0 PWM0
1 µs B1 PWM1
2 µs B2 PWM2
3 µs B3 PWM3
4 ms B0 PWM4
5 ms B1 PWM5
6 ms B2 PWM Pin Enable
7 ms B3 Block CPU µs
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar>
Copyright (c) 2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: TMCounter(RTL) (Entity and architecture)
File name: tmcounter.v
Note: None
Limitations: None known
Errors: None known
Library: lattuino
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice iCECube2 2016.02.27810
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
------------------------------------------------------------------------------
Wishbone Datasheet
1 Revision level B.3
2 Type of interface SLAVE
3 Defined signal names RST_I => wb_rst_i
CLK_I => wb_clk_i
ADR_I => wb_adr_i
DAT_I => wb_dat_i
DAT_O => wb_dat_o
WE_I => wb_we_i
ACK_O => wb_ack_o
STB_I => wb_stb_i
4 ERR_I Unsupported
5 RTY_I Unsupported
6 TAGs None
7 Port size 8-bit
8 Port granularity 8-bit
9 Maximum operand size 8-bit
10 Data transfer ordering N/A
11 Data transfer sequencing Undefined
12 Constraints on the CLK_I signal None
***********************************************************************/
module TMCounter
#(
parameter CNT_PRESC=24,
parameter ENA_TMR=1
)
(
// WISHBONE signals
input wb_clk_i, // Clock
input wb_rst_i, // Reset input
input [2:0] wb_adr_i, // Adress bus
output [7:0] wb_dat_o, // DataOut Bus
input [7:0] wb_dat_i, // DataIn Bus
input wb_we_i, // Write Enable
input wb_stb_i, // Strobe
output wb_ack_o, // Acknowledge
output [5:0] pwm_o, // 6 PWMs
output [5:0] pwm_e_o // Pin enable for the PWMs
);
localparam integer CNT_BITS=$clog2(CNT_PRESC);
// Microseconds counter
reg [31:0] cnt_us_r=0;
// Microseconds counter for the ms counter
reg [9:0] cnt_us2_r=0;
wire tc_cnt_us2;
// Milliseconds counter
reg [31:0] cnt_ms_r=0;
// Latched value
reg [31:0] latched_r=0;
// Prescaler for the Microseconds counters
wire ena_cnt;
reg [CNT_BITS-1:0] pre_cnt_r;
// Microseconds blocker counter
reg [7:0] cnt_blk_r=0;
// Prescaler for the Microseconds blocker counter
wire ena_blk_cnt;
reg [CNT_BITS-1:0] pre_bk_r;
// Blocker FSM
localparam IDLE=0, DELAY=1; // state_t
reg state;
// Blocker WE
wire blk_we;
// PWM values
reg [7:0] pwm_val_r[0:5];
// PWM counter
wire [7:0] pwm_count;
// Auxiliar for config
reg [7:0] wb_dat; // DataOut Bus
// Pin enable for the PWMs
reg [5:0] pwm_e_r;
////////////////////////////////////////////////////////////////////////////
// 32 bits Microseconds counter
////////////////////////////////////////////////////////////////////////////
// Microseconds time source for the counters
always @(posedge wb_clk_i)
begin : tmr_prescaler
if (wb_rst_i)
pre_cnt_r <= 0;
else
begin
pre_cnt_r <= pre_cnt_r+1;
if (pre_cnt_r==CNT_PRESC-1)
pre_cnt_r <= 0;
end
end //tmr_prescaler
assign ena_cnt=pre_cnt_r==CNT_PRESC-1;
// Microseconds counter, 32 bits
always @(posedge wb_clk_i)
begin : do_cnt_us
if (wb_rst_i)
cnt_us_r <= 0;
else if (ena_cnt)
cnt_us_r <= cnt_us_r+1;
end // do_cnt_us
////////////////////////////////////////////////////////////////////////////
// 32 bits Milliseconds counter
////////////////////////////////////////////////////////////////////////////
// Microseconds counter, 10 bits (0 to 999)
always @(posedge wb_clk_i)
begin : do_cnt_us2
if (wb_rst_i || tc_cnt_us2)
cnt_us2_r <= 0;
else if (ena_cnt)
cnt_us2_r <= cnt_us2_r+1;
end // do_cnt_us2
assign tc_cnt_us2=cnt_us2_r==999 && ena_cnt;
// Milliseconds counter, 32 bits
always @(posedge wb_clk_i)
begin : do_cnt_ms
if (wb_rst_i)
cnt_ms_r <= 0;
else if (tc_cnt_us2)
cnt_ms_r <= cnt_ms_r+1;
end // do_cnt_ms
////////////////////////////////////////////////////////////////////////////
// WISHBONE read
////////////////////////////////////////////////////////////////////////////
// Latched value
always @(posedge wb_clk_i)
begin : do_cnt_usr
if (wb_rst_i)
latched_r <= 0;
else if (wb_stb_i)
begin
if (wb_adr_i==3'b0)
latched_r <= cnt_us_r;
else if (wb_adr_i==3'b100)
latched_r <= cnt_ms_r;
end
end // do_cnt_usr
always @(wb_adr_i or cnt_us_r or latched_r or cnt_ms_r)
begin
case (wb_adr_i)
3'b000: wb_dat= cnt_us_r[ 7: 0];
3'b001: wb_dat=latched_r[15: 8];
3'b010: wb_dat=latched_r[23:16];
3'b011: wb_dat=latched_r[31:24];
3'b100: wb_dat= cnt_ms_r[ 7: 0];
3'b101: wb_dat=latched_r[15: 8];
3'b110: wb_dat=latched_r[23:16];
3'b111: wb_dat=latched_r[31:24];
default: wb_dat=0;
endcase
end
assign wb_dat_o=ENA_TMR ? wb_dat : 0;
assign blk_we=wb_stb_i && wb_we_i && wb_adr_i==3'b111 && ENA_TMR;
// ACK all reads and writes when the counter is 0
assign wb_ack_o=wb_stb_i && (!blk_we || (state==DELAY && cnt_blk_r==0));
////////////////////////////////////////////////////////////////////////////
// Microseconds CPU blocker
////////////////////////////////////////////////////////////////////////////
// Blocker FSM (idle and delay)
always @(posedge wb_clk_i)
begin : do_fsm
if (wb_rst_i)
state <= IDLE;
else
if (state==IDLE)
begin
if (blk_we)
state <= DELAY;
end
else // state==DELAY
begin
if (!cnt_blk_r)
state <= IDLE;
end
end // do_fsm
// Blocker counter (down counter)
always @(posedge wb_clk_i)
begin : do_bk_cnt
if (wb_rst_i)
cnt_blk_r <= 0;
else if (state==IDLE && blk_we)
cnt_blk_r <= wb_dat_i;
else if (ena_blk_cnt)
cnt_blk_r <= cnt_blk_r-1;
end // do_bk_cnt
// Microseconds time source for the Blocker counter
always @(posedge wb_clk_i)
begin : tmr_prescaler_bk
if (wb_rst_i || (state==IDLE && blk_we))
pre_bk_r <= CNT_PRESC-1;
else
begin
pre_bk_r <= pre_bk_r-1;
if (!pre_bk_r)
pre_bk_r <= CNT_PRESC-1;
end
end // tmr_prescaler_bk
assign ena_blk_cnt=pre_bk_r==0;
////////////////////////////////////////////////////////////////////////////
// 6 PWMs (8 bits, 250 kHz clock, 976.56 Hz carrier)
////////////////////////////////////////////////////////////////////////////
// PWM value write
always @(posedge wb_clk_i)
begin : do_pwm_val_write
if (!wb_rst_i && wb_stb_i && wb_we_i &&
wb_adr_i!=3'b111 && wb_adr_i!=3'b110)
pwm_val_r[wb_adr_i] <= wb_dat_i;
end // do_pwm_val_write
// 8 bits counter (1 MHz/4)
assign pwm_count=cnt_us_r[9:2];
// PWM outputs (comparators)
genvar i;
generate
for (i=0; i<=5; i=i+1)
begin: do_pwm_outs
assign pwm_o[i]=pwm_count<=pwm_val_r[i];
end
endgenerate
// PWM Pin Enable (1 the pin should use the PWM output)
always @(posedge wb_clk_i)
begin : do_pwm_ena_write
if (wb_rst_i)
pwm_e_r <= 0;
else
if (wb_stb_i && wb_we_i && wb_adr_i==3'b110)
pwm_e_r <= wb_dat_i[5:0];
end // do_pwm_ena_write
assign pwm_e_o=pwm_e_r;
endmodule // TMCounter
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T& x) { x = 0; char c; while (!isdigit(c = getchar())) ; do { x = x * 10 + c - 0 ; } while (isdigit(c = getchar())); } template <typename T> inline void write(T x) { if (x > 9) write(x / 10); putchar(x % 10 + 48); } void Write(string s) { for (int i = 0; i < s.length(); i++) { putchar(s[i]); } } void Sangnt(bool nt[], int n) { int x = sqrt(n); nt[0] = true, nt[1] = true; for (int i = 2; i <= x; i++) { if (nt[i] == false) { for (int j = i * i; j <= n; j += i) { nt[j] = true; } } } } void Congdon(int a[], int n) { for (int i = 1; i < n; i++) { a[i] += a[i - 1]; } } unsigned long long POW(int a, int b) { if (b == 0) return 1; unsigned long long y = POW(a, b / 2); if (b % 2 == 0) return y * y; else return y * y * a; } long long UCLN(long long x, long long y) { long long r, a, b; a = max(x, y), b = min(x, y); while (b) { r = a % b; a = b, b = r; } return a; } string add(string a, string b) { string ans; while (a.length() < b.length()) a = 0 + a; while (b.length() < a.length()) b = 0 + b; ans = a; int n = ans.length(); int digit, Add = 0; for (int i = n - 1; i >= 0; i--) { digit = (a[i] - 0 + b[i] - 0 + Add) % 10; Add = (a[i] - 0 + b[i] - 0 + Add) / 10; ans[i] = digit + 0 ; } if (Add == 1) ans = 1 + ans; while (ans[0] == 0 and ans.length() > 1) ans.erase(0, 1); return ans; } string Minu(string a, string b) { string ans; while (a.length() < b.length()) a = 0 + a; while (b.length() < a.length()) b = 0 + b; ans = a; int n = ans.length(); int digit, Add = 0; for (int i = n - 1; i >= 0; i--) { digit = a[i] - b[i] - Add; if (digit < 0) { digit = digit + 10; Add = 1; } else Add = 0; ans[i] = digit + 0 ; } while (ans[0] == 0 and ans.length() > 1) ans.erase(0, 1); return ans; } double a, b, c, x, y; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); cin >> a >> b >> c; if (a == 0) { if (b == 0) { if (c == 0) { cout << -1; } else { cout << 0; } } else { cout << 1 << endl; printf( %.10f , -c / b); } } else { double delta = b * b - 4 * a * c; if (delta == 0) { x = -b / 2 / a; cout << 1 << endl; printf( %.10f , x); } else if (delta < 0) { cout << 0; } else { cout << 2 << endl; x = -(b + sqrt(delta)) / 2 / a; y = -(b - sqrt(delta)) / 2 / a; if (x > y) { swap(x, y); } printf( %.10f n , x); printf( %.10f , y); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; int n = s.length(); int m; cin >> m; int b[m + 2]; for (int i = 1; i <= m; i++) { cin >> b[i]; } char ans[m + 2]; sort(s.begin(), s.end()); map<int, int> mp; for (int i = 0; i < n; i++) mp[s[i] - a ]++; int j = n - 1; while (true) { vector<int> v; int count = 0; for (int i = 1; i <= m; i++) { if (b[i] == 0) { count++; v.push_back(i); } } if (count == 0) break; if (mp[s[j] - a ] < count) { j = j - mp[s[j] - a ]; continue; } int flag = j; j = j - mp[s[j] - a ]; for (int i = 1; i <= m; i++) { if (b[i] == 0) { ans[i] = s[flag--]; b[i] = -1; } else { for (int k = 0; k < v.size(); k++) { b[i] = b[i] - abs(i - v[k]); } } } } for (int i = 1; i <= m; i++) { cout << ans[i]; } cout << endl; } }
|
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* *
* Altera products are protected under numerous U.S. and foreign patents, *
* maskwork rights, copyrights and other intellectual property laws. *
* *
* This reference design file, and your use thereof, is subject to and *
* governed by the terms and conditions of the applicable Altera Reference *
* Design License Agreement (either as signed by you, agreed by you upon *
* download or as a "click-through" agreement upon installation andor found *
* at www.altera.com). By using this reference design file, you indicate your *
* acceptance of such terms and conditions between you and Altera Corporation. *
* In the event that you do not agree with such terms and conditions, you may *
* not use the reference design file and please promptly destroy any copies *
* you have made. *
* *
* This reference design file is being provided on an "as-is" basis and as an *
* accommodation and therefore all warranties, representations or guarantees *
* of any kind (whether express, implied or statutory) including, without *
* limitation, warranties of merchantability, non-infringement, or fitness for *
* a particular purpose, are specifically disclaimed. By making this refer- *
* ence design file available, Altera expressly does not recommend, suggest *
* or require that this reference design file be used in combination with any *
* other product not provided by Altera. *
* *
* Module Name: erase_keys File Name: erase_keys.v *
* *
* Module Function: This module implements the control mechanism for deter- *
* mining which key to erase when removing keys. There are *
* 4 possible modes that can be used: *
* MODE 1: Full External - All control is external to CAM. *
* MODE 2: Random Internal - Keys stored internal with *
* external control of index for random selection. *
* MODE 3: FIFO Internal - Keys stored internal in FIFO with *
* external control of index when storing. *
* MODE 4: FIFO Auto - Keys stored internal in FIFO with *
* automatic sequential index. *
* *
* Modules Used: *
* erase_ram For storing keys *
* decoder For decoding upper index bits (for Sections) *
* *
* Parameters and Defines Used: *
* FULL_EXTERNAL Fully external control of random key erasure *
* RANDOM_INTERNAL Internal control of random key erasure *
* FIFO_INTERNAL Internal control of FIFO key erasure (TBD) *
* FIFO_AUTO Fully automated FIFO key erasure (TBD) *
* FAMILY Cyclone III/IV, or Stratix III/IV *
* S_KEY Section KEY *
* ENTRIES Total Entries in CAM *
* *
* (Local) *
* INDEX log 2 (ENTRIES) *
* *
* Created by: Jim Schwalbe Created on: 10/05/2009 *
* *
* REVISION HISTORY: *
* * Revision 1.0 10/05/2009 Jim Schwalbe *
* - Initial Revision *
* * Revision 1.1 10/20/2010 Jim Schwalbe *
* - Added latch to erase_keys since data from Erase RAM changes on *
* falling edge of wr_clk for generation of key_addr. *
* - Added pipeline register to wr_key and wr_erase_n for generation of *
* key_addr.
* *
******************************************************************************/
module erase_keys (
reset,
wr_clk,
wr_en,
wr_key,
wr_index,
wr_erase_n,
key_addr,
index_reg,
cam_full,
multi_index
);
// Configuration of erase key management; select (uncomment) only one
//`define FULL_EXTERNAL
`define RANDOM_INTERNAL
//`define FIFO_INTERNAL
//`define FIFO_AUTO
// Target FPGA Family
parameter FAMILY = "Stratix IV";
// Section KEY
parameter S_KEY = 8; // Default (8)
// CAM ENTRIES
parameter ENTRIES = 416;
localparam INDEX = log2(ENTRIES); // Default (9)
localparam ADJ_ENTRY = 2**INDEX;
input reset;
input wr_clk, wr_en;
input [S_KEY-1:0] wr_key;
input [INDEX-1:0] wr_index;
input wr_erase_n;
output [S_KEY-1:0] key_addr;
output [ADJ_ENTRY-1:0] index_reg;
output cam_full, multi_index;
reg rst_reg1, rst_reg2;
// Synchronize reset to wr_clk
always @(posedge wr_clk or posedge reset)
begin
if (reset)
begin
rst_reg2 <= 1'b1;
rst_reg1 <= 1'b1;
end
else
begin
rst_reg2 <= rst_reg1;
rst_reg1 <= 1'b0;
end
end
wire wr_rst = rst_reg2;
`ifdef RANDOM_INTERNAL
reg [ADJ_ENTRY-1:0] index_reg;
reg multi_index;
reg [S_KEY-1:0] lat_erase_key;
reg reg_wr_erase_n;
reg [S_KEY-1:0] reg_wr_key;
wire [S_KEY-1:0] erase_key;
wire [ADJ_ENTRY-1:0] wr_index_decode;
wire [S_KEY-1:0] key_addr = reg_wr_erase_n ? reg_wr_key : lat_erase_key;
wire cam_full = &index_reg;
always @(posedge wr_clk or posedge wr_rst)
begin
if (wr_rst)
begin: reset_keys
index_reg <= {ADJ_ENTRY{1'b0}};
multi_index <= 1'b0;
reg_wr_erase_n <= 1'b0;
reg_wr_key <= {S_KEY{1'b0}};
end
else if (wr_en && wr_erase_n)
begin: write_key
index_reg <= index_reg | wr_index_decode;
reg_wr_erase_n <= wr_erase_n;
reg_wr_key <= wr_key;
if ((index_reg & wr_index_decode) != 0)
multi_index <= 1'b1;
else
multi_index <= 1'b0;
end
else if (wr_en && !wr_erase_n)
begin: remove_key
index_reg <= index_reg & ~wr_index_decode;
multi_index <= 1'b0;
reg_wr_erase_n <= wr_erase_n;
reg_wr_key <= wr_key;
end
else
begin
index_reg <= index_reg;
multi_index <= 1'b0;
reg_wr_erase_n <= reg_wr_erase_n;
reg_wr_key <= reg_wr_key;
end
end
// Latch the erase_key because it changes on falling edge of wr_clk
always @(erase_key or wr_clk)
begin
if (wr_clk)
begin
lat_erase_key <= erase_key;
end
end
//
// Instantiations
//
// Erase Key Store
erase_ram #(
.FAMILY ( FAMILY ),
.S_KEY ( S_KEY ),
.ENTRIES ( ADJ_ENTRY )
) erase_ram_inst (
.address ( wr_index ),
.clock ( wr_clk ),
.data ( wr_key ),
.wren ( wr_en ),
.q ( erase_key )
);
// Decoder for key
decoder #(
.WIDTH ( ADJ_ENTRY )
) decoder_inst (
.encode_in ( wr_index ),
.data_out ( wr_index_decode )
);
`else `ifdef FIFO_INTERAL
// Future enhancement
`else `ifdef FIFO_AUTO
// Future enhancement
`else //`ifdef FULL_EXTERNAL
// These outputs are not used
wire [ADJ_ENTRY-1:0] index_reg = ADJ_ENTRY'b0;
wire multi_index = 0;
wire cam_full = 0;
// Pass the key through
wire [S_KEY-1:0] key_addr = wr_key;
`endif
`endif
`endif
function integer log2;
input [31:0] bits;
integer k;
begin
log2 = 1;
for (k=0; 2**k < bits; k=k+1)
log2 = k + 1;
end
endfunction // log2
endmodule // erase_keys
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_2kx32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_2kx32 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [10:0] rdaddress;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL rdaddress[10..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_2kx32_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y; node(int x1 = 0, int y1 = 0) : x(x1), y(y1){}; bool operator=(const node &b) const { return (x == b.x) && (y == b.y); } }; const int dx[5] = {0, 0, 0, 1, -1}; const int dy[5] = {0, 1, -1, 0, 0}; int N, M, Q; char maze[1007][1007]; int ans = 0; int vis[1007][1007]; int memo[1000007]; void dfs(int x, int y, int id) { if (maze[x][y] == * ) return; for (int i = 1; i <= 4; i++) { int x1 = x + dx[i]; int y1 = y + dy[i]; if (x1 > 0 && x1 <= N && y1 > 0 && y1 <= M && maze[x1][y1] == * ) ans++; } for (int i = 1; i <= 4; i++) { int x1 = x + dx[i]; int y1 = y + dy[i]; if (maze[x1][y1] == . && vis[x1][y1] == 0 && x1 > 0 && x1 <= N && y1 > 0 && y1 <= M) { vis[x1][y1] = id; dfs(x1, y1, id); } } return; } int main() { scanf( %d%d%d , &N, &M, &Q); for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) { cin >> maze[i][j]; } } int k = 1; while (Q--) { int x, y; scanf( %d%d , &x, &y); if (vis[x][y] == 0) { ans = 0; vis[x][y] = k; dfs(x, y, k); memo[k] = ans; k++; } printf( %d n , memo[vis[x][y]]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool vis[100001]; int pi[100001]; int level[100001]; list<int> adj[100001]; void dfs(int s) { vis[s] = 1; bool flag = 1; for (list<int>::iterator it = adj[s].begin(); it != adj[s].end(); ++it) if (!vis[*it]) { level[*it] = level[s] + 1; pi[*it] = s; dfs(*it); flag = 0; } if (flag) { int least = s; stack<int> stk; for (list<int>::iterator it = adj[s].begin(); it != adj[s].end(); ++it) if (level[least] > level[(*it)]) least = *it; while (s != least) { stk.push(s); s = pi[s]; } stk.push(s); cout << stk.size() << n ; while (!stk.empty()) { cout << stk.top() << ; stk.pop(); } exit(0); } } int main() { int n, m, k, i, l, r; cin >> n >> m >> k; for (i = 1; i <= m; ++i) { cin >> l >> r; adj[l].push_back(r); adj[r].push_back(l); } pi[1] = -1; dfs(1); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename G> struct triple { G first, second, T; }; struct BIT { vector<int> v; BIT(int n) : v(n + 10) {} void upd(int p) { for (; p < v.size(); p += (p & (-p))) ++v[p]; } int query(int p) { int x = 0; for (; p > 0; p -= (p & (-p))) x += v[p]; return x; } }; struct fraction { long long x, y; bool operator<(fraction o) { return x * o.y < y * o.x; } bool operator>(fraction o) { return x * o.y > y * o.x; } bool operator!=(fraction o) { return x * o.y != y * o.x; } }; struct info { fraction f1, f2; int ind; info(long long x, long long v, long long _ind, long long w) : ind(_ind) { f1 = {abs(x), abs(v - w)}; f2 = {abs(x), abs(v + w)}; } }; bool cmp1(info x, info y) { if (x.f1 != y.f1) return x.f1 < y.f1; if (x.f2 != y.f2) return x.f2 > y.f2; return x.ind < y.ind; } bool cmp2(info x, info y) { if (x.f2 != y.f2) return x.f2 < y.f2; if (x.f1 != y.f1) return x.f1 > y.f1; return x.ind > y.ind; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, w; cin >> n >> w; vector<info> a; for (int i = 0; i < n; i++) { int x, v; cin >> x >> v; a.push_back({x, v, i, w}); } vector<int> t1(n), t2(n); sort(a.begin(), a.end(), cmp1); for (int i = 0; i < n; i++) t1[i] = a[i].ind; sort(a.begin(), a.end(), cmp2); for (int i = 0; i < n; i++) t2[i] = a[i].ind; vector<int> p(n); for (int i = 0; i < n; i++) p[t1[i]] = i + 1; long long ans = 0; BIT abi(n); for (int i = 0; i < n; i++) { ans += i - abi.query(p[t2[i]]); abi.upd(p[t2[i]]); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool sortmahstyle(const pair<int, int> &a, const pair<int, int> &b) { if (a.first == b.first && a.second < b.second) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, m, d; cin >> n >> m >> d; long long int a[n * m]; for (long long int i = 0; i < n * m; i++) cin >> a[i]; long long int ans = 0; sort(a, a + (n * m)); for (long long int i = 0; i < n * m; i++) ans += abs(a[i] - a[n * m / 2]); if (ans % d == 0) cout << ans / d << n ; else cout << -1 n ; return 0; }
|
`timescale 1ns / 1ps
// @input
// clk_src: input event detective
// switch_power: power on/off state switch
// switch_en: start/pause state switch
// sig_change: plus signal for sel_value
// @output
// sel_value
module selector_mode
#(parameter LO = 2, HI = 5, CLK_CH = 25)
(
input [31:0]clk,
input switch_power,
input switch_en,
input sig_change,
input [1:0]washing_machine_running,
output reg push,
output reg [2:0] sel_value
);
reg init_flag;
wire real_clk;
initial begin
init_flag <= 1;
sel_value <= LO;
push <= 1'b0;
end
// change signal change to level change(with clk[CLK_CH] Hz)
always @(posedge clk[CLK_CH]) begin
if (switch_power) begin
// pause
if (!switch_en) begin
// washing finished
if(washing_machine_running[1]) begin
push = 1'b1;
sel_value = LO;
// true pause
end else begin
if(init_flag) begin
sel_value = LO;
init_flag = 0;
push = 1'b0;
end
// start to change value
if (sig_change) begin
sel_value = (sel_value + 1) % (HI+1) ? (sel_value + 1) % (HI+1) : LO;
push = 1'b1;
// otherwise, keep current state
end else begin
sel_value = sel_value;
push = push;
end
end
// washing running
end else begin
push = 1'b0;
sel_value = sel_value;
end
// power off
end else begin
init_flag = 1;
sel_value = LO;
push = 1'b0;
end
end
endmodule
|
module dds_gen(clk, key1, key2, da_clk, da_db);
input wire clk;
input wire key1;
input wire key2;
output wire da_clk;
output wire [7:0] da_db;
wire clk100M;
pll100M gen_100MHz(.inclk0(clk),
.c0(clk100M));
reg [31:0] dds_accum; initial dds_accum <= 32'd0;
reg [31:0] dds_adder; initial dds_adder <= 32'd179272; // 440 Hz
reg [31:0] delay_cnt; initial delay_cnt <= 32'd0;
//assign clk100M = clk;
//трех битный буфер
reg [2:0] gate_buff1;
reg [2:0] gate_buff2;
always @ (posedge clk100M) begin
gate_buff1 <= {gate_buff1[1:0],~key1};
gate_buff2 <= {gate_buff2[1:0],~key2};
end
//буфферизированное значение
assign GATE1_D = (gate_buff1 == 3'b111);
assign GATE2_D = (gate_buff2 == 3'b111);
always @(posedge clk100M) begin
dds_accum <= dds_accum + dds_adder;
delay_cnt <= delay_cnt + 1'b1;
if(delay_cnt==32'd0) begin
delay_cnt <= 32'd1000000;
dds_adder <= (GATE1_D) ? dds_adder + 32'd100 :
(GATE2_D) ? dds_adder - 32'd100 : dds_adder;
end else begin
delay_cnt <= delay_cnt - 1'b1;
end
end
assign da_db = dds_accum[31:31-7]; //high bits of dds accum
assign da_clk = clk100M;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n; cin >> n; if (n == 1) { cout << 0 << n ; continue; } long long int ans = 0; while (n != 1) { ans++; if (n % 2 == 0) { n = n / 2; } else if (n % 3 == 0) { n = 2 * n / 3; } else if (n % 5 == 0) { n = 4 * n / 5; } else { ans = -1; break; } } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int o = 0; int z = 0; for (int i = 0; i < n; i++) { int y; cin >> y; if (y == 1) o++; else z++; } if (z == o) { cout << n / 2 << n ; for (int i = 1; i <= n / 2; i++) cout << 0 ; } else if (z > o) { cout << n / 2 << n ; for (int i = 1; i <= n / 2; i++) cout << 0 ; } else { int y = n / 2; if (y % 2 == 0) { cout << y << n ; for (int i = 0; i < y; i++) cout << 1 ; } else { cout << (y + 1) << n ; for (int i = 0; i < y + 1; i++) cout << 1 << ; } } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 111, K = 26; int n; string name[MAX]; namespace G { struct V : vector<int> { V() : odw(false) {} bool odw; int wyj; }; V g[K]; void krawedz(char a, char b) { g[int(a) - int( a )].push_back(int(b) - int( a )); } int t = 0; stack<int> stos; void dfs(int v) { g[v].odw = true; for (int i = 0; i < ((int((g[v]).size()))); i++) { int u = g[v][i]; if (!g[u].odw) dfs(u); } stos.push(v); g[v].wyj = t++; } bool poprawne_sortowanie() { for (int v = 0; v < (K); v++) for (int i = 0; i < ((int((g[v]).size()))); i++) { int u = g[v][i]; if (g[v].wyj < g[u].wyj) return false; } return true; } bool sortowanie_topologiczne() { for (int i = 0; i < (K); i++) if (!g[i].odw) dfs(i); return poprawne_sortowanie(); } void wypisz_sortowanie() { assert((int((stos).size())) == 26); while (!stos.empty()) { cout << char(int( a ) + stos.top()); stos.pop(); } cout << n ; } } // namespace G void wczytaj_dane() { cin >> n; for (int i = 0; i < (n); i++) cin >> name[i]; } int roznica(const string& a, const string& b) { int m = min((int((a).size())), (int((b).size()))); for (int i = 0; i < (m); i++) if (a[i] != b[i]) return i; return -1; } bool porownuj(const string& a, const string& b) { int i = roznica(a, b); if (i == -1) return (int((a).size())) < (int((b).size())); G::krawedz(a[i], b[i]); return true; } void zrob_test() { wczytaj_dane(); for (int i = 0; i < (n - 1); i++) if (!porownuj(name[i], name[i + 1])) { cout << Impossible n ; return; } if (G::sortowanie_topologiczne()) G::wypisz_sortowanie(); else cout << Impossible n ; } int main() { ios_base::sync_with_stdio(0); zrob_test(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define zednkw 200
module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
input zfghtn;
input [4:0] cjtmau;
input vipmpg;
input [7:0] knquim;
input [7:0] kqxkkr;
reg covfok;
reg [15:0] xwieqw;
reg [2:0] ofnjjt;
reg [37:0] hdsejo[0:1];
reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
reg vrqrih, ryyjxy;
reg fgzsox;
wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
wire smxixw = vrqrih | (ryyjxy & ktsveg);
wire [7:0] grvsrs, kyxrft, uxhkka;
wire [7:0] eianuv = 8'h01 << ofnjjt;
wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
wire [7:0] nahzat = {8{iytyol}} & eianuv;
genvar i;
generate
for (i=0;i<8;i=i+1)
begin : dnlpyw
DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
knquim[3:0], covfok, grvsrs[i]);
DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
knquim[7:4], covfok, kyxrft[i]);
DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
kqxkkr[3:0], covfok, uxhkka[i]);
end
endgenerate
endmodule
module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
input clk, fgzsox, fckiyr, covfok;
input [3:0] uezcjy;
output juvlsh;
task Xinit;
begin
`ifdef TEST_HARNESS
khgawe = 1'b0;
`endif
end
endtask
function X;
input vrdejo;
begin
`ifdef TEST_HARNESS
if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
`endif
X = vrdejo;
end
endfunction
task Xcheck;
input vzpwwy;
begin
end
endtask
reg [3:0] udbvtl;
assign juvlsh = |udbvtl;
wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
always @(posedge clk)
begin
Xinit;
if (X(qqibou))
udbvtl <= #`zednkw mppedc;
Xcheck(fgzsox);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200 * 1000 + 5; pair<long long int, long long int> b[MAXN]; long long int dp[MAXN]; long long int rem[MAXN]; inline pair<long long int, long long int> cst(int x, int y) { long long int tt = ((b[x].first - rem[y] + b[y].second - 1) / b[y].second); return make_pair(tt + dp[y], rem[y] + tt * b[y].second - b[x].first); } bool cmp(const pair<long long int, long long int>& x, const pair<long long int, long long int>& y) { if (x.first != y.first) return x.first < y.first; return x.second > y.second; } inline bool isBet(int i, int j, int k) { return !cmp(cst(i, k), cst(i, j)); } int main() { ios::sync_with_stdio(false); int n; long long int s; cin >> n >> s; for (int i = 0; i < n; i++) cin >> b[i].second >> b[i].first; b[n].first = s; sort(b, b + n, cmp); assert(!b[0].first); deque<pair<int, int> > cands; cands.push_back(make_pair(0, 1)); long long int ans = cst(n, 0).first; long long int lst = b[0].second; for (int i = 1; i < n; i++) { if (b[i].second <= lst) continue; while (cands.size() > 1 && isBet(i, cands[1].first, cands[0].first)) cands.pop_front(); pair<long long int, long long int> tmp = cst(i, cands[0].first); dp[i] = tmp.first; rem[i] = tmp.second; ans = min(ans, cst(n, i).first); while (cands.size() && isBet(cands.back().second, i, cands.back().first)) cands.pop_back(); if (cands.size()) { int d = cands.back().second, u = n - 1; while (d < u - 1) { int mid = (d + u) / 2; if (isBet(mid, i, cands.back().first)) u = mid; else d = mid; } if (isBet(u, i, cands.back().first)) cands.push_back(make_pair(i, u)); } lst = b[i].second; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long OO = (long long)1e9 + 7; using namespace std; long long inv(long long a, long long b) { return 1 < a ? b - inv(b % a, a) * b / a : 1; } long long Pow(long long B, long long P) { long long R = 1; while (P > 0) { if (P & 1) R = (R * B); P /= 2; B = (B * B); } return R; } long long GCD(long long a, long long b) { while (b) { b ^= a ^= b ^= a %= b; } return a; } long long LCM(long long a, long long b) { return (a / GCD(a, b) * b); } long long BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P & 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return (long long)R; } vector<long long> primes; void factorization(long long n) { for (long long i = 2; i * i <= n; ++i) while (n % i == 0) primes.push_back(i), n /= i; if (n > 1) primes.push_back(n); } int main() { ios::sync_with_stdio(0); long long n; cin >> n; factorization(n); if (primes.size() == 2) { cout << 2; } else { if (n == 1 || primes.size() == 1) { cout << 1 n0 ; } else { cout << 1 << endl; cout << primes[0] * primes[1]; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 100; int c[maxn], a[maxn]; int main() { int n, m, l = 0, ans = 0; cin >> n >> m; for (int i = 0; i < n; i++) cin >> c[i]; for (int i = 0; i < m; i++) cin >> a[i]; for (int i = 0; i < n; i++) if (a[l] >= c[i]) { ans++; l++; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q, n, sum; cin >> q; while (q--) { cin >> n; int m = n; sum = 0; while (n--) { int x; cin >> x; sum += x; } double y = (double)sum / m; int rs = y; if (y == rs) { cout << rs << endl; } else { cout << rs + 1 << endl; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
|
/*
Copyright (C) 2016
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : submodule of asyn_fifo_controller
// read function
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module asyn_fifo_read #(
parameter FWFTEN = 1, // 0 : disable
parameter ADDRWIDTH = 6,
parameter [ADDRWIDTH:0] FIFODEPTH = 44,
parameter [ADDRWIDTH:0] MINBIN2 = 0,
parameter [ADDRWIDTH:0] MAXBIN2 = 7
) (
input wire r_clk ,
input wire r_rst_n ,
input wire r_en ,
input wire [ADDRWIDTH:0] w2r_ptr ,
output reg [ADDRWIDTH-1:0] rbin ,
output reg [ADDRWIDTH:0] rptr ,
output inc ,
output reg r_valid ,
output reg [ADDRWIDTH:0] r_counter,
output reg r_error
);
//
wire zero = (r_counter == {(ADDRWIDTH+1){1'b0}} );
// FWFT (First Word Fall Through)
wire fwft = FWFTEN ? (!r_valid && !zero) : 1'b0;
//
assign inc = (r_en && !zero) || fwft;
//---------------------------------------------------------------
// "rbin2" is double the amount of "rbin"
//---------------------------------------------------------------
reg [ADDRWIDTH:0] rbin2;
wire [ADDRWIDTH:0] rbnext = (rbin2>=MINBIN2 && rbin2<MAXBIN2) ?
(rbin2 + 1'b1) : MINBIN2;
//
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rbin2 <= MINBIN2;
else if (inc)
rbin2 <= rbnext;
//---------------------------------------------------------------
// memory address
//---------------------------------------------------------------
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rbin <= {ADDRWIDTH{1'b0}};
else if (inc)
rbin <= rbnext[ADDRWIDTH] ? rbnext[ADDRWIDTH-1:0] :
(rbnext[ADDRWIDTH-1:0] - MINBIN2[ADDRWIDTH-1:0]);
//---------------------------------------------------------------
// GRAY pointer
//---------------------------------------------------------------
// binary-to-gray conversion
wire [ADDRWIDTH:0] rptr_gray = {1'b0,rbnext[ADDRWIDTH:1]} ^ rbnext;
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rptr <= (MINBIN2>>1) ^ MINBIN2;
else if (inc)
rptr <= rptr_gray;
//---------------------------------------------------------------
// from other-side
//---------------------------------------------------------------
reg [ADDRWIDTH:0] w2r_bin;
always @(w2r_ptr)
begin: GrayToBin
integer i;
for (i=ADDRWIDTH; i>=0; i=i-1)
w2r_bin[i] = ^(w2r_ptr>>i);
end
//---------------------------------------------------------------
// output signals
//---------------------------------------------------------------
wire [ADDRWIDTH:0] distance = ( (w2r_bin >= rbin2) ?
(w2r_bin - rbin2) :
(w2r_bin - rbin2 - (MINBIN2<<1) )
) - inc;
// "r_counter" is precise.
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_counter <= {(ADDRWIDTH+1){1'b0}};
else
r_counter <= distance;
// "r_valid" is alignment with "dout" because of FWFT
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_valid <= 1'b0;
else if (r_en || fwft)
r_valid <= !zero;
//
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_error <= 1'b0;
else
r_error <= (r_counter > FIFODEPTH);
//
endmodule
|
#include <bits/stdc++.h> using namespace std; static const int N = 500005; long long l[N]; long long d[N]; char s[N]; int main() { int a, b, t, n; cin >> n >> a >> b >> t; scanf( %s , &s); l[0] = 1 + b * (s[0] == w ); for (int i = 1; i < n; i++) l[i] = 1 + l[i - 1] + a + b * (s[i] == w ); for (int i = n - 1; i >= 0; i--) d[i] = 1 + d[i + 1] + a + b * (s[i] == w ); int j = 1; int m = 0; for (int i = 0; i < n; i++) { while (j < n && l[i] + d[j] + i * a > t) j++; if ((j < n || l[i] <= t) && i + 1 + n - j > m) m = i + 1 + n - j; } int m1 = m; int i = 1; j = n - 1; while (i < j) { swap(s[i], s[j]); i++; j--; } l[0] = 1 + b * (s[0] == w ); for (int i = 1; i < n; i++) l[i] = 1 + l[i - 1] + a + b * (s[i] == w ); for (int i = n - 1; i >= 0; i--) d[i] = 1 + d[i + 1] + a + b * (s[i] == w ); j = 1; m = 0; for (int i = 0; i < n; i++) { while (j < n && l[i] + d[j] + i * a > t) j++; if ((j < n || l[i] <= t) && i + 1 + n - j > m) m = i + 1 + n - j; } m = max(m, m1); cout << min(m, n) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 510, mod = 1LL * 1000 * 1000 * 1000 + 7; int dp[N][N], n, b[N], num[N][N]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> b[i]; for (int j = 1; j <= n; j++) for (int i = j - 1; i >= 0; i--) { if (j - i <= 2) { dp[i][j] = num[i][j] = 1; continue; } for (int k = i + 1; k + 1 < j; k++) if (b[k] < b[j - 1]) (num[i][j] += 1LL * num[i][k + 1] * dp[k][j - 1] % mod) %= mod; for (int k = i + 1; k < j; k++) (dp[i][j] += 1LL * num[i][k + 1] * dp[k][j] % mod) %= mod; } cout << dp[0][n] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; std::vector<std::string> alph; class IAlphabet { public: virtual int encode(char symbol) = 0; virtual char decode(int code) = 0; virtual int size() = 0; }; class alphabet_eng : public IAlphabet { public: virtual int encode(char symbol); virtual char decode(int code); virtual int size() { return 26; }; }; int alphabet_eng::encode(char symbol) { if ((symbol < 97) || (symbol >= 123)) return -1; else return (symbol - 97); } char alphabet_eng::decode(int code) { if ((code < 0) || (code >= 26)) return 0; else return (code + 97); } class VocabularyTrie { public: VocabularyTrie(IAlphabet& alphabet); VocabularyTrie(VocabularyTrie& parent); void Fill(); int GetSize(); bool m_end_of_word; IAlphabet& m_alphabet; int winner; int loser; std::vector<std::unique_ptr<VocabularyTrie>> m_children; VocabularyTrie* m_parent; }; std::set<std::pair<int, VocabularyTrie*>> proce; VocabularyTrie::VocabularyTrie(IAlphabet& alphabet) : m_end_of_word(false), m_children(alphabet.size()), m_parent(nullptr), m_alphabet(alphabet) { winner = 2; } VocabularyTrie::VocabularyTrie(VocabularyTrie& parent) : m_end_of_word(false), m_children(parent.GetSize()), m_parent(&parent), m_alphabet(parent.m_alphabet) {} int VocabularyTrie::GetSize() { return m_alphabet.size(); } void VocabularyTrie::Fill() { for (int i = 0; i < alph.size(); i++) { std::string word; word = alph[i]; VocabularyTrie* trie_ptr = this; for (int letter = 0; letter < word.length(); letter++) { int curr_letter_code = m_alphabet.encode(word[letter]); if (trie_ptr->m_children[curr_letter_code] == nullptr) { trie_ptr->m_children[curr_letter_code].reset( new VocabularyTrie(*trie_ptr)); } trie_ptr = trie_ptr->m_children[curr_letter_code].get(); } trie_ptr->m_end_of_word = true; proce.insert(std::make_pair(word.length(), trie_ptr)); } } int main() { int m, n, k; cin >> n >> k; for (int i = 0; i < n; i++) { std::string x; cin >> x; alph.push_back(x); } alphabet_eng alphabet; VocabularyTrie nn(alphabet); nn.Fill(); while (proce.size() >= 1) { auto h = proce.end(); h--; int x = h->first; VocabularyTrie* y = h->second; proce.erase(std::make_pair(x, y)); int winner = 2; int loser = 1; for (int i = 0; i < 26; i++) { if (y->m_children[i] != nullptr) loser = 2; } if (y == nullptr) continue; for (int i = 0; i < 26; i++) { if ((y->m_children[i] != nullptr) && (y->m_children[i]->winner == 2)) winner = 1; if ((y->m_children[i] != nullptr) && (y->m_children[i]->loser == 2)) loser = 1; } y->winner = winner; y->loser = loser; if (x > 0) proce.insert(std::make_pair(x - 1, y->m_parent)); } int whowins = 1; int u = nn.winner; int v = nn.loser; if (u == 2) whowins = 2; else { if (v == 1) whowins = 1; else whowins = 2 - (k % 2); } if (whowins == 2) cout << Second ; else cout << First ; return 0; }
|
// bsg_strobe
//
// N
// Outputs sequence ( 1 0 )* for 0 <= N=init_val_i <= (1<<width_p)-1
//
// init_val_i = # of cycles to count between asserting 1
// (e.g 0 means assert 1 continuously)
//
// One usage is clock downsampling.
//
// The paper "The Power of Carry-Save Addition" by Lutz and Jayasimha
// is a good introduction to the use of carry-save addition. However
// the version in this code is significantly evolved versus the
// one in the paper; many of the gates were unnecessary.
//
// This should run well above a GHZ in 250 nm; it is a little more than one XOR delay
// on top of the flop.
//
// init_val_i can be changed on the fly; new values are captured on the same clk edge that the
// output strobe appears so the switch from one strobe delay to another is atomic and no
// unspecifed delays appear.
//
// Both reset_r and init_val_r are recommended to be driven out of registers to reduce
// cycle time.
//
// MBT 8/31/16
//
// FIXME (bug found by Yichao Wu): does not handle case of width_p=1
//
`include "bsg_defines.v"
module bsg_strobe #(`BSG_INV_PARAM(width_p)
,harden_p=0)
(input clk_i
, input reset_r_i
, input [width_p-1:0] init_val_r_i
, output logic strobe_r_o
);
localparam debug_lp = 0;
logic strobe_n, strobe_n_buf;
logic [width_p-1:0 ] S_r, S_n, S_n_n,C_n_prereset;
logic [width_p-1-1:0] C_r, C_n;
wire new_val = reset_r_i | strobe_n;
bsg_dff #(.width_p(width_p-1)
,.harden_p(harden_p)
,.strength_p(2)
) C_reg
(.clk_i (clk_i)
,.data_i (C_n )
,.data_o (C_r )
);
// complement of new sum bit
// assign S_n = ~ (S_r ^ {C_r, 1'b1} );
bsg_xnor #(.width_p(width_p),.harden_p(1)) xnor_S_n
(.a_i(S_r),.b_i({C_r,1'b1}),.o(S_n));
// A B S0 Y
bsg_muxi2_gatestack #(.width_p(width_p),.harden_p(1)) muxi2_S_n
(.i0(S_n) //i2 == 0 (complement of sum bit)
, .i1(init_val_r_i) //i2 == 1 // note: implicitly, this is getting inverted
// which is what we want -- we want to take the complement of init_val_r_i
, .i2( {width_p {new_val} })
,.o(S_n_n) // final sum bit, after reset
);
// when we receive a new value; we load sum bits with the init value
bsg_dff #(.width_p(width_p)
,.harden_p(harden_p)
,.strength_p(4) // need some additional power on this one
) S_reg
(.clk_i(clk_i)
,.data_i(S_n_n)
,.data_o(S_r)
);
// increment-by-one in carry-save representation (i.e. a counter)
// the "1" is add by one.
// implementable with an array of half-adders
bsg_nand #(.width_p(width_p),.harden_p(1)) nand_C_n
(.a_i(S_r)
,.b_i({C_r,1'b1})
,.o(C_n_prereset) // lo true
);
// this implements reset. if any of the three conditions
// are true, then the carry is zerod:
// 1. strobe is asserted
// 2. reset is asserted
// 3. C_nprereset (lo true) is asserted
bsg_nor3 #(.width_p(width_p-1),.harden_p(1)) nor3_C_n
(.a_i ({ (width_p-1) {strobe_n_buf} })
,.b_i(C_n_prereset[0+:width_p-1])
,.c_i({ (width_p-1) {reset_r_i}})
,.o (C_n)
);
// we strobe when our CS value reaches -1. In CS representation, -1 iff every bit in C and S are different.
// Moreover, in our counter representation, we further can show -1 is represented by all S bits being set.
bsg_reduce #(.and_p(1)
,.harden_p(1)
,.width_p(width_p)
) andr
(.i(S_r)
,.o(strobe_n)
);
// DC/ICC botches the buffering of this signal so we give it some help
bsg_buf #(.width_p(1)) strobe_buf_gate
(.i(strobe_n)
,.o(strobe_n_buf)
);
always_ff @(posedge clk_i)
strobe_r_o <= strobe_n_buf;
// synopsys translate_off
if (debug_lp)
begin : debug
always @(negedge clk_i)
// if (strobe_n)
$display("%t (C=%b,S=%b) reset_r_i=%d new_val=%b init_val=%d val(C,S)=%b C^S=%b",$time
, C_r,S_r, reset_r_i, new_val, init_val_r_i, (C_r << 1)+S_r, strobe_n);
end
// synopsys translate_on
// synopsys translate_off
always @(negedge clk_i)
assert((strobe_n === 'X) || strobe_n == & ((C_r << 1) ^ S_r))
else $error("## faulty assumption about strobe signal in %m (C_r=%b, S_r=%b, strobe_n=%b)", C_r,S_r, strobe_n);
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_strobe)
|
`timescale 1ns / 1ps
//Sumador de 32 bits con signo.
/*
* Números de 32 bits donde, si a es número, entonces:
* a[31] : signo de a.
* a[30:10] : parte entera de a.
* a[9:0] : parte decimal de a.
*/
module Sumador(
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] Z,
output reg ovf
);
//Inicializar
reg [31:0] a32 = 32'b0;
reg [31:0] b32 = 32'b0;
reg [31:0] ab = 32'b0;
always @* begin
if(a[31] == b[31]) begin
//a y b son positivos o negativos.
a32[30:0] = a[30:0];
b32[30:0] = b[30:0];
ab = a32 + b32;
Z[30:0] = ab[30:0];
Z[31] = a[31];
ovf = ab[31];
end
else begin
a32[30:0] = (a[31]) ? a[30:0] : b[30:0];
b32[30:0] = (a[31]) ? b[30:0] : a[30:0];
ab = b32 - a32;
if(b32[30:0] < a32[30:0]) begin
Z[30:0] = -ab[30:0];
Z[31] = 1'b1;
end
else begin
Z[30:0] = ab[30:0];
Z[31] = 1'b0;
end
ovf = 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 21 | 1; int n, p[N]; long long a[N], b[N], c[N]; char s[N], t[N]; void OR(long long* a) { int i, j, u, v, l, t; for (i = 2; i <= n; i <<= 1) for (j = 0, t = i >> 1; j < n; j += i) for (u = j, v = l = j + t; u < l; ++u, ++v) a[v] += a[u]; } void IOR(long long* a) { int i, j, u, v, l, t; for (i = 2; i <= n; i <<= 1) for (j = 0, t = i >> 1; j < n; j += i) for (u = j, v = l = j + t; u < l; ++u, ++v) a[v] -= a[u]; } int main() { int m, i; scanf( %d%s%s , &m, s, t), n = 1 << m; for (i = 1; i < n; ++i) p[i] = p[i - (i & -i)] + 2; for (i = 0; i < n; ++i) a[i] = (s[i] - 48ll) << p[i], b[i] = (t[i] - 48ll) << p[i]; OR(a), OR(b); for (i = 0; i < n; ++i) c[i] = a[i] * b[i]; IOR(c); for (i = 0; i < n; ++i) putchar(c[i] >> p[i] & 3 | 48); return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Set the clock signal, and its frequency
*
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/*
* Clock frequency is arbitrarily chosen
* Period = 10 ns, frequency = 100MHz
*/
#5 ck = 0;
#5 ck = 1;
end
/**
* Instantiate an instance of a convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
bin = 1'b0;
rset=0;
// @ t=3,
#3;
bin = 1'b1;
rset=0;
// @ t=10,
#7;
bin = 1'b0;
rset=0;
// @ t=19,
#9;
bin = 1'b1;
rset=0;
// @ t=29,
#10;
bin = 1'b0;
rset=0;
// @ t=39,
#10;
bin = 1'b1;
rset=0;
// @ t=50-1,
#10;
bin = 1'b0;
rset=0;
// @ t=60-1,
#10;
bin = 1'b1;
rset=0;
// @ t=70-1,
#10;
bin = 1'b0;
rset=0;
// @ t=80-1,
#10;
bin = 1'b0;
rset=0;
// @ t=90-1,
#10;
bin = 1'b1;
rset=0;
// @ t=100-1,
#10;
bin = 1'b1;
rset=1;
// @ t=110-1,
#9;
bin = 1'b0;
rset=0;
// @ t=120-1,
#10;
bin = 1'b1;
rset=0;
// @ t=130-1,
#10;
bin = 1'b0;
rset=0;
// @ t=140-1,
#10;
bin = 1'b1;
rset=1;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int k; long long s[16], sum; map<long long, int> id; vector<long long> v; bool vis[16]; bool dp[1 << 15]; vector<pair<int, int> > way[1 << 15]; int pre[1 << 15]; pair<int, int> ans[16]; int main() { scanf( %d , &k); for (int i = 0; i < k; i++) { int n; scanf( %d , &n); while (n--) { int x; scanf( %d , &x); s[i] += x, sum += x; id[x] = i; v.push_back(x); } } if (sum % k) printf( No n ); else { sum /= k; for (auto x : v) { for (int i = 0; i < k; i++) vis[i] = false; long long now = x; int mask = 0; vector<pair<int, int> > opt; bool f = true; while (!vis[id[now]]) { vis[id[now]] = true; long long pre = now; now = sum - s[id[now]] + now; if (id.count(now) == 0) { f = false; break; } if (vis[id[now]] && now != x) { f = false; break; } mask |= 1 << id[pre]; opt.push_back(pair<int, int>(now, pre)); } if (f == true) way[mask] = opt; } dp[0] = 1; for (int i = 1; i < (1 << k); i++) { for (int j = i - 1; j != i; j = (j - 1) & i) { if (dp[j] && !way[i ^ j].empty()) { dp[i] = 1; pre[i] = j; break; } } } if (!dp[(1 << k) - 1]) printf( No n ); else { printf( Yes n ); int now = (1 << k) - 1; while (now) { int x = now ^ (pre[now]); for (auto p : way[x]) ans[id[p.first]] = pair<int, int>(p.first, id[p.second]); now = pre[now]; } for (int i = 0; i < k; i++) printf( %d %d n , ans[i].first, ans[i].second + 1); } } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.2 2001/07/03 12:55:41 mohor
// Minor changes because of the synthesys warnings.
//
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
`include "timescale.v"
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b0;
StateDrop <= 1'b1;
StatePreamble <= 1'b0;
StateSFD <= 1'b0;
StateData0 <= 1'b0;
StateData1 <= 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartIdle)
StateDrop <= 1'b0;
else
if(StartDrop)
StateDrop <= 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= 1'b0;
else
if(StartSFD)
StateSFD <= 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= 1'b0;
else
if(StartData0)
StateData0 <= 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= 1'b0;
else
if(StartData1)
StateData1 <= 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule
|
module controlunit(input [5:0] imemout,output brnch,output memorywrite,output memoryread,output alusrc,output regw,output regdst,output aluop,output memtoreg);
reg brnch,memorywrite,memoryread,aluop;
reg memtoreg,alusrc,regw,regdst;
always @ ( imemout )
begin
if(imemout[5:0] == 6'b000000)
begin
brnch = 1'b0;
memorywrite = 1'b0;
memoryread = 1'b0;
alusrc = 1'b0;
regw = 1'b1;
regdst = 1'b1;
aluop = 1'b1;
memtoreg = 1'b1;
end
else
if(imemout[5:0] == 6'b100011)
begin
brnch = 1'b0;
memorywrite = 1'b0;
memoryread = 1'b1;
alusrc = 1'b1;
regw = 1'b1;
regdst = 1'b0;
aluop = 1'b0;
memtoreg = 1'b0;
end
else
if(imemout[5:0] == 6'b101011)
begin
brnch = 1'b0;
memorywrite = 1'b1;
memoryread = 1'b0;
alusrc = 1'b1;
regw = 1'b0;
regdst = 1'b0;
aluop = 1'b0;
memtoreg = 1'b0;
end
else
if(imemout[5:0] == 6'b000100)
begin
brnch = 1'b1;
memorywrite = 1'b0;
memoryread = 1'b0;
alusrc = 1'b0;
regw = 1'b0;
regdst = 1'b0;
aluop = 1'b0;
memtoreg = 1'b0;
end
else
begin
brnch = 1'b0;
memorywrite = 1'b0;
memoryread = 1'b0;
alusrc = 1'b0;
regw = 1'b0;
regdst = 1'b0;
aluop = 1'b0;
memtoreg = 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, sx, ex; char s[1010]; int main() { scanf( %d%d%s , &n, &k, s); for (int i = 0; i < n; i++) { if (s[i] == G ) sx = i; if (s[i] == T ) ex = i; } if (sx > ex) swap(sx, ex); if ((ex - sx) % k != 0) printf( NO n ); else { bool f = 1; for (int i = sx + k; i < ex; i += k) { if (s[i] == # ) f = 0; } if (f) printf( YES n ); else printf( NO n ); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:59:24 11/29/2014
// Design Name:
// Module Name: multiplexor32a1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multiplexor32a1 #(parameter Width = 3)
(coeff00,coeff01,coeff02,coeff03,coeff04,coeff05,coeff06,coeff07,coeff08,coeff09,
coeff10,coeff11,coeff12,coeff13,coeff14,coeff15,coeff16,coeff17,coeff18,coeff19,
coeff20,coeff21,coeff22,coeff23,coeff24,coeff25,coeff26,coeff27,coeff28,coeff29,
coeff30,coeff31,SEL,outMUX);
input [4:0] SEL;
input signed [Width-1:0] coeff00,coeff01,coeff02,coeff03,coeff04,coeff05,coeff06,coeff07,coeff08,coeff09,
coeff10,coeff11,coeff12,coeff13,coeff14,coeff15,coeff16,coeff17,coeff18,coeff19,
coeff20,coeff21,coeff22,coeff23,coeff24,coeff25,coeff26,coeff27,coeff28,coeff29,
coeff30,coeff31;
output reg signed [Width-1:0] outMUX;
always @*begin
case (SEL)
5'd00: outMUX <= coeff00;
5'd01: outMUX <= coeff01;
5'd02: outMUX <= coeff02;
5'd03: outMUX <= coeff03;
5'd04: outMUX <= coeff04;
5'd05: outMUX <= coeff05;
5'd06: outMUX <= coeff06;
5'd07: outMUX <= coeff07;
5'd08: outMUX <= coeff08;
5'd09: outMUX <= coeff09;
5'd10: outMUX <= coeff10;
5'd11: outMUX <= coeff11;
5'd12: outMUX <= coeff12;
5'd13: outMUX <= coeff13;
5'd14: outMUX <= coeff14;
5'd15: outMUX <= coeff15;
5'd16: outMUX <= coeff16;
5'd17: outMUX <= coeff17;
5'd18: outMUX <= coeff18;
5'd19: outMUX <= coeff19;
5'd20: outMUX <= coeff20;
5'd21: outMUX <= coeff21;
5'd22: outMUX <= coeff22;
5'd23: outMUX <= coeff23;
5'd24: outMUX <= coeff24;
5'd25: outMUX <= coeff25;
5'd26: outMUX <= coeff26;
5'd27: outMUX <= coeff27;
5'd28: outMUX <= coeff28;
5'd29: outMUX <= coeff29;
5'd30: outMUX <= coeff30;
5'd31: outMUX <= coeff31;
endcase
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long c; vector<int> a; int N; long long C[65][65]; long long nCk(long long n, long long k) { if (k > n) return 0; return C[n][k]; } long long f(int index, int onesNeeded, int tight) { if (index == N) { if (onesNeeded == 0) return 1; else return 0; } if (a[index] == 0) { return f(index + 1, onesNeeded, tight); } else { long long ans = nCk(N - index - 1, onesNeeded); if (onesNeeded >= 1) ans += f(index + 1, onesNeeded - 1, tight); return ans; } } int brute(int n) { int ans = 0; for (int i = 1; i <= n; i++) { int t = i, cnt = 0; while (t) { if (t % 2 == 1) cnt++; t /= 2; } if (cnt == 5) ans++; } return ans; } int main() { for (int i = 0; i <= 60; i++) C[i][0] = 1, C[i][i] = 1; for (int n = 1; n <= 60; n++) { for (int r = 1; r <= n; r++) { C[n][r] = C[n - 1][r] + C[n - 1][r - 1]; } } long long n, t; cin >> n >> t; n++; int ok = 0; if ((t & (t - 1)) == 0) ok = 1; while (t) { t /= 2; c++; }; if (!ok) { cout << 0 << endl; return 0; } while (n) { a.push_back(n % 2); n /= 2; } reverse(a.begin(), a.end()); N = a.size(); long long ans1 = f(0, c, 1); if (c == 1) ans1--; cout << ans1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 1; const int MOD = 1e9 + 7; long long a[MAXN], b[MAXN]; bool used[MAXN]; vector<int> g[MAXN]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long n, m, cnt = 0, ans = 0; bool y = 0; cin >> n; a[1] = 1; for (int i = 2; i <= n; i++) { cin >> a[i]; } cnt = n; while (cnt != 1) { ans++; b[ans] = cnt; cnt = a[cnt]; } reverse(b + 1, b + ans + 1); cout << 1 << ; for (int i = 1; i <= ans; i++) { cout << b[i] << ; } return 0; }
|
`timescale 10ns/10ns
module test;
wire button;
reg clk;
/* camera signal generator */
reg href;
reg vsync;
reg pclk;
reg [7:0] data;
parameter Tline = 786 * 2;
reg spi_clk,
spi_mosi,
cs;
initial begin
forever begin
spi_clk = 0;
spi_mosi = 0;
cs = 1;
//start
#50 spi_mosi = 1;
#10 cs = 0;
#40 spi_clk = 1;
#50 spi_clk = 0;
//2nd bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//3rd bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//4th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//5th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//6th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//7th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//8th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
#20 cs = 1;
//=========//
spi_clk = 0;
spi_mosi = 0;
cs = 1;
//start
#50 spi_mosi = 0;
#10 cs = 0;
#40 spi_clk = 1;
#50 spi_clk = 0;
//2nd bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//3rd bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//4th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//5th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//6th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//7th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//8th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
#20 cs = 1;
end
end
initial begin
clk = 0;
data = 0;
forever begin
#1 clk = ~clk;
end
end
initial begin
pclk = 1;
forever begin
#16 pclk = ~pclk;
end
end
always @(negedge pclk) begin
data <= data + 8'b1;
end
always @(posedge href) begin
data <= 8'h00;
end
always @(negedge href) begin
data <= 8'hxx;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
#10
repeat (10) begin
vsync = 1;
href = 0;
repeat (1 * Tline) @(negedge pclk);
vsync <= 0;
repeat (3 * Tline) @(negedge pclk);
repeat (480) begin
href <= 1;
repeat (640 * 2) @(negedge pclk);
href <= 0;
repeat (144 * 2) @(negedge pclk);
end
repeat (10 * Tline) @(negedge pclk);
end
#100 $stop;
end
wire capture;
wire [7:0] led;
wire busy;
wire locked;
balldetector bd0 (
.inclk(clk),
.ahref(href),
.avsync(vsync),
.apclk(pclk),
.xclk(xclk),
.adata(data),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.cs(cs),
.led(led),
.i2c_clk(i2c_clk),
.i2c_sda(i2c_sda),
.busy(busy),
.pwm0(pwm)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, i = 1; cin >> n >> k; while (~k & 1) k >>= 1, i++; cout << i; return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace IO { const int maxn(1 << 21 | 1); char *iS, *iT, ibuf[maxn], obuf[maxn], *oS = obuf, *oT = obuf + maxn - 1, c, st[20]; int f, tp, len; inline char getc() { return iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, maxn, stdin), iS == iT ? EOF : *iS++) : *iS++; } template <class T> inline void read(T &x) { for (c = getc(), f = 1; c < 0 || c > 9 ; c = getc()) f = c == - ? -1 : 1; for (x = 0; c >= 0 && c <= 9 ; c = getc()) x = x * 10 + (c ^ 48); x *= f; } template <class T, class... Other> inline void read(T &x, Other &...y) { read(x), read(y...); } inline void flush() { fwrite(obuf, 1, oS - obuf, stdout), oS = obuf; } inline void putc(char ch) { *oS++ = ch; if (oS == oT) flush(); } template <class T> inline void print(T x, char ch = n ) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = -x; while (x) st[++tp] = x % 10 + 0 , x /= 10; while (tp) putc(st[tp--]); putc(ch); } template <class T, class... Other> inline void print(T x, Other... y) { print(x), print(y...); } inline void print_str(char *s) { for (len = strlen(s), f = 0; f < len; ++f) putc(s[f]); } inline void read_str(char *s, int &l) { for (l = 0, c = getc(); (c < a || c > z ) && (c < A || c > Z ); c = getc()) ; for (; (c >= a && c <= z ) || (c >= A && c <= Z ); c = getc()) s[l++] = c; s[l] = 0 ; } } // namespace IO using IO ::flush; using IO ::print; using IO ::print_str; using IO ::read; using IO ::read_str; template <class T> inline void cmax(T &x, T y) { x = x >= y ? x : y; } template <class T, class... Other> inline void cmax(T &x, T y, Other... z) { Cmax(x, y), Cmax(x, z...); } template <class T> inline void cmin(T &x, T y) { x = x <= y ? x : y; } template <class T, class... Other> inline void cmin(T &x, T y, Other... z) { Cmin(x, y), Cmin(x, z...); } inline int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } const int mod(1e9 + 7); inline void inc(int &x, const int y) { x = x + y >= mod ? x + y - mod : x + y; } inline void dec(int &x, const int y) { x = x - y < 0 ? x - y + mod : x - y; } inline int add(const int x, const int y) { return x + y >= mod ? x + y - mod : x + y; } inline int sub(const int x, const int y) { return x - y < 0 ? x - y + mod : x - y; } inline int fpow(long long x, int y) { long long ret = 1; for (; y; y >>= 1, x = x * x % mod) if (y & 1) ret = ret * x % mod; return ret; } const int maxn(1e5 + 5); int k, lg[23], ans = 1, f[55][10005], num, inv[55]; long long n, d[23]; inline int solve(int p, int lim) { int i, j, l, ret = 0; memset(f, 0, sizeof(f)), f[lim][0] = 1; for (i = 1; i <= k; ++i) for (j = 0; j <= lim; ++j) for (l = j; l <= lim; ++l) inc(f[j][i], (long long)f[l][i - 1] * inv[l + 1] % mod); for (ret = 0, i = 0; i <= lim; ++i) inc(ret, (long long)f[i][k] * fpow(p, i) % mod); return ret; } int main() { long long i; read(n, k), ans = 1; for (i = 1; i <= 50; ++i) inv[i] = fpow(i, mod - 2); for (i = 2; i * i <= n; ++i) if (n % i == 0) { d[++num] = i; while (n % i == 0) n /= i, ++lg[num]; } if (n > 1) d[++num] = n, lg[num] = 1; for (i = 1; i <= num; ++i) ans = (long long)ans * solve(d[i] % mod, lg[i]) % mod; print(ans); return flush(), 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Tick Timer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// TT according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/02/12 01:33:47 lampret
// No longer using async rst as sync reset for the counter.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:00:49 lampret
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
//
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_tt(
// RISC Internal Interface
clk, rst, du_stall,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
intr
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input du_stall; // DU stall
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output intr; // Interrupt output
`ifdef OR1200_TT_IMPLEMENTED
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg [31:0] ttmr; // TTMR bits
`else
wire [31:0] ttmr; // No TTMR register
`endif
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg [31:0] ttcr; // TTCR bits
`else
wire [31:0] ttcr; // No TTCR register
`endif
//
// Internal wires & regs
//
wire ttmr_sel; // TTMR select
wire ttcr_sel; // TTCR select
wire match; // Asserted when TTMR[TP]
// is equal to TTCR[27:0]
wire restart; // Restart counter when asserted
wire stop; // Stop counter when asserted
reg [31:0] spr_dat_o; // SPR data out
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
always @(posedge clk or posedge rst)
if (rst)
ttmr <= 32'b0;
else if (ttmr_sel && spr_write)
ttmr <= #1 spr_dat_i;
else if (ttmr[`OR1200_TT_TTMR_IE])
ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
`endif
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
always @(posedge clk or posedge rst)
if (rst)
ttcr <= 32'b0;
else if (restart)
ttcr <= #1 32'b0;
else if (ttcr_sel && spr_write)
ttcr <= #1 spr_dat_i;
else if (!stop)
ttcr <= #1 ttcr + 32'd1;
`else
assign ttcr = 32'b0;
`endif
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_TT_READREGS
`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
default: spr_dat_o = ttcr;
endcase
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
`else
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 2e5 + 5; const double pi = acos(-1.0); long long addM(long long a, long long b) { return (a + b) % MOD; } long long multM(long long a, long long b) { return (a * b) % MOD; } long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res *= a; a *= a; b >>= 1; } return res; } long long ModInverse(long long n) { return binpow(n, MOD - 2); } vector<long long> findFact() { vector<long long> fact(N); fact[0] = 1; for (long long i = 1; i <= N; i++) { fact[i] = multM(i, fact[i - 1]); } return fact; } long long ncr(long long n, long long r) { vector<long long> fact = findFact(); return ((fact[n] * ModInverse(fact[n - r])) % MOD * ModInverse(fact[r])) % MOD; } vector<bool> findPrime() { vector<bool> is_prime(N + 1, true); is_prime[0] = false; is_prime[1] = false; for (long long i = 2; i <= N; i++) { if (is_prime[i] && i * i <= N) { for (long long j = i * i; j <= N; j += i) is_prime[j] = false; } } return is_prime; } vector<bool> segmentedSieveNoPreGen(long long L, long long R) { vector<bool> isPrime(R - L + 1, true); long long lim = sqrt(R); for (long long i = 2; i <= lim; ++i) for (long long j = max(i * i, (L + i - 1) / i * i); j <= R; j += i) isPrime[j - L] = false; if (L == 1) isPrime[0] = false; return isPrime; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long tt; cin >> tt; while (tt--) { long long n; cin >> n; string x, y; cin >> x >> y; bool check = true; for (long long i = 0; i < n; i++) { if (x[i] > y[i]) { check = false; } } if (check) { long long ans = 0; for (char c = a ; c <= z ; c++) { char mn = z ; bool check = false; for (long long i = 0; i < n; i++) { if (x[i] == c && x[i] != y[i]) { check = true; mn = min(mn, y[i]); } } for (long long i = 0; i < n; i++) { if (x[i] == c && x[i] != y[i]) { x[i] = mn; } } if (check) ans++; } cout << ans << n ; } else { cout << -1 n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int l, r, a; int main() { cin >> l >> r >> a; if (l > r) swap(l, r); if (l == r) return cout << (l + a / 2) * 2, 0; if (l < r) { if (l + a >= r) { a -= abs(l - r), l = r; cout << l * 2 + (a / 2) * 2; } else cout << (l + a) * 2; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s1, s2; cin >> s1 >> s2; int a, b, c, d; a = s1[0] - 0 ; b = s1[1] - 0 ; c = s2[1] - 0 ; d = s2[0] - 0 ; vector<int> v1({a, b, c, d}); map<vector<int>, int> mp; mp[{a, b, c, d}] = 1; n--; while (n--) { string s; cin >> s; cin >> s1 >> s2; a = s1[0] - 0 ; b = s1[1] - 0 ; c = s2[1] - 0 ; d = s2[0] - 0 ; vector<int> v1({a, b, c, d}); vector<int> v2({b, c, d, a}); vector<int> v3({c, d, a, b}); vector<int> v4({d, a, b, c}); if (mp.find({a, b, c, d}) != mp.end()) { continue; } else if (mp.find({b, c, d, a}) != mp.end()) { continue; } else if (mp.find({c, d, a, b}) != mp.end()) { continue; } else if (mp.find({d, a, b, c}) != mp.end()) { continue; } else mp[{a, b, c, d}] = 1; } cout << mp.size() << endl; return 0; }
|
#include <bits/stdc++.h> typedef long long ll; using namespace std; int k; int addk(int a,int b) { int base,aw,bw,ret=0; for(base=1;base<=max(a,b);base*=k) { aw=a/base%k; bw=b/base%k; ret+=(aw+bw)%k*base; } return ret; } int subk(int a,int b) { int base,aw,bw,ret=0; for(base=1;base<=max(a,b);base*=k) { aw=a/base%k; bw=b/base%k; ret+=(aw-bw+k)%k*base; } return ret; } int main() { int T,n,y,i,r; scanf( %d ,&T); while(T--) { scanf( %d%d ,&n,&k); for(i=0;i<n;i++) { if(i==0) y=0; else if(i&1) y=subk(i-1,i); else y=subk(i,i-1); printf( %d n ,y); fflush(stdout); scanf( %d ,&r); if(r==1) break; } } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-need to work on dual mode for pn sequence
`timescale 1ns/100ps
module axi_axis_rx_core (
// adc interface
adc_clk,
adc_valid,
adc_data,
// dma interface
dma_clk,
dma_valid,
dma_last,
dma_data,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
// adc interface
input adc_clk;
input adc_valid;
input [DW:0] adc_data;
// dma interface
input dma_clk;
output dma_valid;
output dma_last;
output [DW:0] dma_data;
input dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal clocks and resets
wire adc_rst;
wire dma_rst;
// internal signals
wire dma_ovf_s;
wire dma_unf_s;
wire dma_status_s;
wire [31:0] dma_bw_s;
wire dma_start_s;
wire dma_stream_s;
wire [31:0] dma_count_s;
// dma interface
ad_axis_dma_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_dma_rx (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_valid (dma_valid),
.dma_last (dma_last),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s));
// processor control
up_axis_dma_rx i_up_axis_dma_rx (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`include "defines.v"
`timescale 1ns/1ps
module tb(
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `control_w flit1c;
wire `control_w port0_co, port1_co, port2_co, port3_co, port4_co;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(144'h0), .port2_co(port2_co),
.port3_ci(144'h0), .port3_co(port3_co),
.port4_ci(144'h0), .port4_co(port4_co),
.port4_ready(injrd), .port4_ack(injack)
);
initial begin
$set_toggle_region(tb.r);
$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef012345789abcdef1857; // MSHR 1; valid / seq 0; source 5; dest 7
flit1c = 144'h0123456789abcdef012345789abcdef284c;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 144'h0;
flit1c = 144'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$toggle_stop();
$toggle_report("./calf_backward_2.saif", 1.0e-9, "tb.r");
$finish;
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for udp_arb_mux
*/
module test_udp_arb_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT-1:0] s_udp_hdr_valid = 0;
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
reg [S_COUNT*16-1:0] s_eth_type = 0;
reg [S_COUNT*4-1:0] s_ip_version = 0;
reg [S_COUNT*4-1:0] s_ip_ihl = 0;
reg [S_COUNT*6-1:0] s_ip_dscp = 0;
reg [S_COUNT*2-1:0] s_ip_ecn = 0;
reg [S_COUNT*16-1:0] s_ip_length = 0;
reg [S_COUNT*16-1:0] s_ip_identification = 0;
reg [S_COUNT*3-1:0] s_ip_flags = 0;
reg [S_COUNT*13-1:0] s_ip_fragment_offset = 0;
reg [S_COUNT*8-1:0] s_ip_ttl = 0;
reg [S_COUNT*8-1:0] s_ip_protocol = 0;
reg [S_COUNT*16-1:0] s_ip_header_checksum = 0;
reg [S_COUNT*32-1:0] s_ip_source_ip = 0;
reg [S_COUNT*32-1:0] s_ip_dest_ip = 0;
reg [S_COUNT*16-1:0] s_udp_source_port = 0;
reg [S_COUNT*16-1:0] s_udp_dest_port = 0;
reg [S_COUNT*16-1:0] s_udp_length = 0;
reg [S_COUNT*16-1:0] s_udp_checksum = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep = 0;
reg [S_COUNT-1:0] s_udp_payload_axis_tvalid = 0;
reg [S_COUNT-1:0] s_udp_payload_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser = 0;
reg m_udp_hdr_ready = 0;
reg m_udp_payload_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_udp_hdr_ready;
wire [S_COUNT-1:0] s_udp_payload_axis_tready;
wire m_udp_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [15:0] m_udp_source_port;
wire [15:0] m_udp_dest_port;
wire [15:0] m_udp_length;
wire [15:0] m_udp_checksum;
wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep;
wire m_udp_payload_axis_tvalid;
wire m_udp_payload_axis_tlast;
wire [ID_WIDTH-1:0] m_udp_payload_axis_tid;
wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest;
wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_udp_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_udp_source_port,
s_udp_dest_port,
s_udp_length,
s_udp_checksum,
s_udp_payload_axis_tdata,
s_udp_payload_axis_tkeep,
s_udp_payload_axis_tvalid,
s_udp_payload_axis_tlast,
s_udp_payload_axis_tid,
s_udp_payload_axis_tdest,
s_udp_payload_axis_tuser,
m_udp_hdr_ready,
m_udp_payload_axis_tready
);
$to_myhdl(
s_udp_hdr_ready,
s_udp_payload_axis_tready,
m_udp_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_udp_source_port,
m_udp_dest_port,
m_udp_length,
m_udp_checksum,
m_udp_payload_axis_tdata,
m_udp_payload_axis_tkeep,
m_udp_payload_axis_tvalid,
m_udp_payload_axis_tlast,
m_udp_payload_axis_tid,
m_udp_payload_axis_tdest,
m_udp_payload_axis_tuser
);
// dump file
$dumpfile("test_udp_arb_mux_4.lxt");
$dumpvars(0, test_udp_arb_mux_4);
end
udp_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame inputs
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tid(s_udp_payload_axis_tid),
.s_udp_payload_axis_tdest(s_udp_payload_axis_tdest),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// Ethernet frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tid(m_udp_payload_axis_tid),
.m_udp_payload_axis_tdest(m_udp_payload_axis_tdest),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int MOD = 1e9 + 7; int n, revfact[N << 1], fact[N << 1]; int mul(int, int); int sum(int, int); int pow(int, int); int choose(int, int); int32_t main() { cin >> n; fact[0] = 1; for (int i = 1; i < 2 * n + 3; i++) fact[i] = mul(fact[i - 1], i); for (int i = 0; i < 2 * n + 3; i++) revfact[i] = pow(fact[i], MOD - 2); int res = choose((2 * n) + 2, n + 1) - 1; if (res < 0) res += MOD; cout << res << endl; } int mul(int a, int b) { return 1LL * a * b % MOD; } int sum(int a, int b) { int c = a + b; if (c >= MOD) c -= MOD; return c; } int pow(int n, int md) { int res = 1; for (; md; md /= 2) { if (md % 2 == 1) res = mul(res, n); n = mul(n, n); } return res; } int choose(int m, int k) { return mul(fact[m], mul(revfact[k], revfact[m - k])); }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b) * b); } bool sorta(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } bool sortd(const pair<int, int> &a, const pair<int, int> &b) { return (a.second > b.second); } void printarr(long long arr[], long long n) { for (int i = 0; i < n; i++) cout << arr[i] << ; cout << n ; } string decToBinary(int n) { string s = ; int i = 0; while (n > 0) { s = to_string(n % 2) + s; n = n / 2; i++; } return s; } long long binaryToDecimal(string n) { string num = n; long long dec_value = 0; int base = 1; int len = num.length(); for (int i = len - 1; i >= 0; i--) { if (num[i] == 1 ) dec_value += base; base = base * 2; } return dec_value; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; long long i = 1; while (t--) { long long w, h; cin >> w >> h; long long arr1[4]; for (int i = 0; i < 4; i++) { int k; cin >> k; long long arr[k]; for (int j = 0; j < k; j++) cin >> arr[j]; arr1[i] = arr[k - 1] - arr[0]; } arr1[0] *= h, arr1[1] *= h; arr1[2] *= w, arr1[3] *= w; long long maxan = max({arr1[0], arr1[1], arr1[2], arr1[3]}); cout << maxan << n ; } return 0; }
|
//
// xmtbuf.v -- serial line transmitter buffer
//
module xmtbuf(clk, reset, write, ready, data_in, serial_out);
input clk;
input reset;
input write;
output reg ready;
input [7:0] data_in;
output serial_out;
reg [1:0] state;
reg [7:0] data_hold;
reg load;
wire empty;
xmt xmt1(clk, reset, load, empty, data_hold, serial_out);
always @(posedge clk) begin
if (reset == 1) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else begin
case (state)
2'b00:
begin
if (write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end
end
2'b01:
begin
state <= 2'b10;
ready <= 1;
load <= 0;
end
2'b10:
begin
if (empty == 1 && write == 0) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else
if (empty == 1 && write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end else
if (empty == 0 && write == 1) begin
state <= 2'b11;
data_hold <= data_in;
ready <= 0;
load <= 0;
end
end
2'b11:
begin
if (empty == 1) begin
state <= 2'b01;
ready <= 0;
load <= 1;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_SYMBOL_V
`define SKY130_FD_SC_LP__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
module lvds2lcds (
// avalon-bus
input clk,
input reset,
input avs_slave_write,
input avs_slave_read,
input [7:0]avs_slave_writedata,
output [7:0]avs_slave_readdata,
// lvds2lcds
output reset_n,
output scl,
output sdi,
output sld
);
//
// parameters
//
parameter divider = 50;
//
// regs / wires
//
reg [8:0]clk_counter;
reg div_clk;
reg scl_en;
reg [6:0]shift_buffer;
reg shift_busy;
reg [2:0]shift_counter;
//
// ip
//
assign reset_n = !reset;
assign avs_slave_readdata = shift_busy;
assign scl = scl_en ? div_clk : 1'b0;
assign sld = (!scl_en && shift_busy) ? div_clk : 1'b0;
assign sdi = shift_buffer[6];
always @(posedge clk or posedge reset)
begin
if(reset)
begin
clk_counter <= 9'd1;
div_clk <= 1'b0;
scl_en <= 1'b0;
shift_busy <= 1'b0;
shift_counter <= 3'd0;
end
else
begin // posedge clk
if(shift_busy)
begin
if(clk_counter == (divider/2))
begin
clk_counter <= 9'd1;
div_clk <= !div_clk;
if(div_clk)
begin
if(!scl_en)
begin
shift_busy <= 1'b0;
end
else
begin
if(shift_counter == 3'd6)
begin
scl_en <= 1'b0;
end
else
begin
shift_counter <= shift_counter + 3'd1;
shift_buffer <= shift_buffer << 1;
end
end
end
end
else
begin
clk_counter = clk_counter + 9'd1;
end
end
else
begin
clk_counter <= 9'd1;
shift_counter <= 3'd0;
div_clk <= 1'b0;
if(avs_slave_write)
begin
shift_buffer <= avs_slave_writedata[6:0];
shift_busy <= 1'b1;
scl_en <= 1'b1;
end
end
end
end
endmodule
|
module encoder_test;
reg write_enable;
reg [31:0] my_data;//data to test: 0xe3a02001
reg [7:0] my_ecc;// ecc for this data: 0xf7
reg [39:0] bitflip_mask;
wire [31:0] input_data;
wire [7:0] input_ecc;
wire [31:0] output_data;
wire [7:0] ecc_syndrome;
wire uncorrected;
initial
begin
// Simulation test values.
my_data = 32'he3a02001;
my_ecc = 8'hf7;
write_enable = 1'b0;
bitflip_mask = 40'h1;
end
genvar i;
generate
// Flip my_data bit values using bitflip_mask (only on read operations)
for( i = 8; i < 40; i=i+1) begin
assign input_data[i-8] = my_data[i-8] ^ (bitflip_mask[i] & ~write_enable);
end
for( i = 0; i < 8; i=i+1) begin
assign input_ecc[i] = my_ecc[i] ^ (bitflip_mask[i] & ~write_enable);
end
endgenerate
edc_generator generator (
.o_ecc_syndrome ( ecc_syndrome ), // To Corrector and ECC Memory
.i_write_enabled ( write_enable ),
.i_ecc ( input_ecc ), // From ECC Memory
.i_data ( input_data ) // From multiplexor
);
edc_corrector corrector (
.o_data ( output_data ),
.o_uncorrected_error ( uncorrected ),
.o_error_detected ( ),
.i_syndrome ( generator.o_ecc_syndrome ), // From generator
.i_data ( input_data ) // From "main memory"
);
endmodule
|
#include <bits/stdc++.h> int main() { char s[51]; scanf( %s , s); int i, tf, na = 0, t1 = strlen(s); if (t1 >= 1 && t1 <= 50) { for (i = 0; i < t1; i++) { if (s[i] == a ) { na = na + 1; } } if (2 * na > t1) { tf = t1; } else { tf = (2 * na) - 1; } printf( %d n , tf); } return 0; }
|
`timescale 1ns/100ps
module top;
reg in;
wire [3:0] vec;
wire [4:0] bvec;
wire real r_vec, r_arr, r_io;
initial in <= 1'b0;
// You cannot go to multiple real values (have multiple instances).
vec_to_real u1[1:0](r_vec, in);
// A real port cannot be used in an arrayed instance.
arr_real u2a[1:0](bvec, in);
arr_real u2b[1:0](r_arr, in);
// You cannot connect a real to an inout port.
io_vec_to_real u3(r_io, in);
// You cannot have a inout port declared real.
io_real_to_vec u4(vec, in);
endmodule
module vec_to_real (output wire [3:0] out, input wire in);
reg [3:0] rval = 0;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
module arr_real(output wire real out, input wire in);
real rval;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
module io_vec_to_real(inout wire [3:0] out, input wire in);
reg [3:0] rval = 0;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
module io_real_to_vec(inout wire real out, input wire in);
real rval;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pi = pair<int, int>; using pl = pair<ll, ll>; using pld = pair<ld, ld>; using vi = vector<int>; using vl = vector<ll>; using vb = vector<bool>; using vld = vector<ld>; using vs = vector<string>; using vpi = vector<pi>; using vpl = vector<pl>; using vpld = vector<pld>; int clz(unsigned long long N) { return N ? 63 - __builtin_clzll(N) : -1; } int arr[300010]; int acum[300010]; int n, q; void solvetask() { cin >> n >> q; for (int i = 0; i < n; i++) { char c; cin >> c; if (c == + ) arr[i] = (i & 1) ? -1 : 1; else arr[i] = (i & 1) ? 1 : -1; } for (int i = 1; i <= n; i++) acum[i] = acum[i - 1] + arr[i - 1]; while (q--) { int l, r; cin >> l >> r; int soma = acum[r] - acum[l - 1]; if (soma == 0) cout << 0 n ; else if (abs(soma) % 2 == 1) cout << 1 n ; else cout << 2 n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; cin >> t; while (t--) solvetask(); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int i, n, t, p = INT_MAX, j = 0, x, a = 0, b, l = 0, r = 0, k = 0, e, w = 0; long long sum = 0; string s, m; cin >> n; int ara[n]; int ar[n]; int arr[n]; for (i = 0; i < n; i++) { cin >> ara[i]; ar[j++] = ara[i]; } for (i = 0; i < n; i++) { p = ara[i]; ar[i] = ara[i]; for (j = i + 1; j < n; j++) { if (ara[j] > p) { ar[j] = p; } else { p = ara[j]; ar[j] = ara[j]; } } p = ara[i]; for (k = i - 1; k >= 0; k--) { if (ara[k] > p) { ar[k] = p; } else { p = ara[k]; ar[k] = ara[k]; } } for (int y = 0; y < n; y++) { sum += ar[y]; } if (w <= sum) { w = sum; for (int g = 0; g < n; g++) { arr[g] = ar[g]; } } sum = 0; } for (i = 0; i < n; i++) { cout << arr[i] << ; } return EXIT_SUCCESS; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; a[i] += i; } sort(a.begin(), a.end()); for (int i = 0; i < n; i++) { a[i] -= i; if (i && a[i] < a[i - 1]) { cout << :( << endl; return 0; } } for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << endl; return 0; }
|
module butterfly_8(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [24:0] i_0;
input signed [24:0] i_1;
input signed [24:0] i_2;
input signed [24:0] i_3;
input signed [24:0] i_4;
input signed [24:0] i_5;
input signed [24:0] i_6;
input signed [24:0] i_7;
output signed [25:0] o_0;
output signed [25:0] o_1;
output signed [25:0] o_2;
output signed [25:0] o_3;
output signed [25:0] o_4;
output signed [25:0] o_5;
output signed [25:0] o_6;
output signed [25:0] o_7;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [25:0] b_0;
wire signed [25:0] b_1;
wire signed [25:0] b_2;
wire signed [25:0] b_3;
wire signed [25:0] b_4;
wire signed [25:0] b_5;
wire signed [25:0] b_6;
wire signed [25:0] b_7;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_7;
assign b_1=i_1+i_6;
assign b_2=i_2+i_5;
assign b_3=i_3+i_4;
assign b_4=i_3-i_4;
assign b_5=i_2-i_5;
assign b_6=i_1-i_6;
assign b_7=i_0-i_7;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int t; cin >> t; for (int z = 0; z < t; ++z) { int n; string s; cin >> n >> s; string ans = ; for (int i = 0; i < n; ++i) { if ((s[i] - 0 ) % 2 == 1) ans += s[i]; if (ans.size() == 2) break; } if (ans.size() < 2) { cout << -1 n ; } else { cout << ans << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long Query(long long L, long long R) { cout << L << << R << endl; fflush(stdout); string s; cin >> s; if (L == R && s == Yes ) exit(0); return s == Yes ; } int32_t main() { long long n, k; cin >> n >> k; long long L = 1, R = n; while (true) { if (R - L + 1 <= 4 * k + 7) { long long M = L + rng() % (R - L + 1); if (Query(M, M)) { return 0; } else { L = max(1LL, L - k); R = min(n, R + k); } } else { long long M = L + ((R - L) >> 1); if (Query(L, M)) { L = max(1LL, L - k); R = min(n, M + k); } else { L = max(1LL, M - k); R = min(n, R + k); } } } }
|
#include <bits/stdc++.h> using namespace std; bool vis[105][105]; int main() { int n; scanf( %d , &n); int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { int x; scanf( %d , &x); vis[1][x] = true; } for (int i = 2; i <= n; i++) { int m; scanf( %d , &m); for (int j = 1; j <= m; j++) { int x; scanf( %d , &x); if (vis[i - 1][x]) vis[i][x] = true; } } for (int i = 1; i <= 100; i++) if (vis[n][i]) printf( %d , i); return 0; }
|
`timescale 1 ns / 1 ps
module READ_ROM32 ( input[4:0] ADDR ,output[31:0] DATA_RE,output[31:0] DATA_IM);
reg [31:0] re[0:31];
initial begin
re[0] = 32'h00000000;re[1] = 32'hFFE4CC88;re[2] = 32'h002DA5B3;re[3] = 32'hFFCE9932;
re[4] = 32'h00254173;re[5] = 32'hFFF2E19A;re[6] = 32'hFFF0C26D;re[7] = 32'h0026B1CD;
re[8] = 32'hFFCE4E3A;re[9] = 32'h002CB328;re[10] = 32'hFFE6AE85;re[11] = 32'hFFFDC9B2;
re[12] = 32'h001D07D3;re[13] = 32'hFFD17EA5;re[14] = 32'h00310311;re[15] = 32'hFFDC4195;
re[16] = 32'h000AF8A5;re[17] = 32'h0011551D;re[18] = 32'hFFD7F13F;re[19] = 32'h0031E3D5;
re[20] = 32'hFFD455CB;re[21] = 32'h001762CC;re[22] = 32'h00046B81;re[23] = 32'hFFE13261;
re[24] = 32'h002F45B3;re[25] = 32'hFFCF793E;re[26] = 32'h00222978;re[27] = 32'hFFF7329D;
re[28] = 32'hFFEC9C0A;re[29] = 32'h002957A0;re[30] = 32'hFFCE0320;re[31] = 32'h002A8B5D;
end
reg [31:0] im[0:31];
initial begin
im[0] = 32'h00000000;im[1] = 32'h00000000;im[2] = 32'h00000000;im[3] = 32'h00000000;
im[4] = 32'h00000000;im[5] = 32'h00000000;im[6] = 32'h00000000;im[7] = 32'h00000000;
im[8] = 32'h00000000;im[9] = 32'h00000000;im[10] = 32'h00000000;im[11] = 32'h00000000;
im[12] = 32'h00000000;im[13] = 32'h00000000;im[14] = 32'h00000000;im[15] = 32'h00000000;
im[16] = 32'h00000000;im[17] = 32'h00000000;im[18] = 32'h00000000;im[19] = 32'h00000000;
im[20] = 32'h00000000;im[21] = 32'h00000000;im[22] = 32'h00000000;im[23] = 32'h00000000;
im[24] = 32'h00000000;im[25] = 32'h00000000;im[26] = 32'h00000000;im[27] = 32'h00000000;
im[28] = 32'h00000000;im[29] = 32'h00000000;im[30] = 32'h00000000;im[31] = 32'h00000000;
end
assign DATA_RE = re[ADDR];
assign DATA_IM = im[ADDR];
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-12; const int inf = 2000000000; const long long int infLL = (long long int)1e18; long long int MOD = 1000000007; int MOD1 = 1000000007; int MOD2 = 1000000009; inline bool checkBit(long long int n, long long int i) { return n & (1LL << i); } inline long long int setBit(long long int n, long long int i) { return n | (1LL << i); ; } inline long long int resetBit(long long int n, long long int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long int year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long int &a) { a %= MOD; (a < 0) && (a += MOD); } inline long long int modMul(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a * b) % MOD; } inline long long int modAdd(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a + b) % MOD; } inline long long int modSub(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline long long int modPow(long long int b, long long int p) { long long int r = 1LL; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1LL; } return r; } inline long long int modDiv(long long int a, long long int b) { return modMul(a, modPow(b, MOD - 2)); } bool comp(const pair<long long int, pair<long long int, long long int> > &p1, const pair<long long int, pair<long long int, long long int> > &p2) { return p1.first > p2.first; } bool comp1(const pair<long long int, long long int> &p1, const pair<long long int, long long int> &p2) { if (p1.first == p2.first) { return p1.second > p2.second; } return p1.first < p2.first; } long long int converter(string a) { long long int i, mul = 1LL, r, t, ans = 0LL; if (a.length() == 0) return 0; for (i = a.length() - 1; i >= 0; i--) { t = a[i] - 0 ; r = t % 10; ans += (mul * r); mul = mul * 10; } return ans; } int msb(unsigned x) { union { double a; int b[2]; }; a = x; return (b[1] >> 20) - 1023; } const int MAX = 300005; long long int g[3][MAX], a[MAX]; long long int x, y, z, magic, n; const int ex = 70; const int lim = 1000; int grundy(int a, int b, int c) { set<long long int> s; s.insert(a); s.insert(b); s.insert(c); int val = 0; while (s.find(val) != s.end()) ++val; return val; } void calc() { for (int i = 1; i <= lim; ++i) { long long int cur1 = max(0LL, i - x); long long int cur2 = max(0LL, i - y); long long int cur3 = max(0LL, i - z); g[0][i] = grundy(g[0][cur1], g[1][cur2], g[2][cur3]); g[1][i] = grundy(g[0][cur1], inf, g[2][cur3]); g[2][i] = grundy(g[0][cur1], g[1][cur2], inf); } } void findPeriod() { magic = 0; for (int perLen = 1; !magic; ++perLen) { int f = 1; for (int i = ex; i < ex + perLen && f; ++i) { for (int j = i; j <= lim && f; j += perLen) { if (g[0][i] != g[0][j] || g[1][i] != g[1][j] || g[2][i] != g[2][j]) f = 0; } } if (f) magic = perLen; } } int ask(long long int pile, int state) { pile = max(0LL, pile); if (pile <= lim) return g[state][pile]; else return g[state][(pile - ex) % magic + ex]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout.unsetf(ios::floatfield); cout.precision(20); cout.setf(ios::fixed, ios::floatfield); ; int t; cin >> t; while (t--) { cin >> n >> x >> y >> z; calc(); findPeriod(); if (magic >= 30) { cout << MAgic << magic << n ; return 0; } long long int nimber = 0; for (int i = 1; i <= n; ++i) { cin >> a[i]; nimber ^= ask(a[i], 0); } int ans = 0; for (int i = 1; i <= n; ++i) { long long int save = nimber ^ ask(a[i], 0); long long int temp = save ^ ask(a[i] - x, 0); if (!temp) ans++; temp = save ^ ask(a[i] - y, 1); if (!temp) ans++; temp = save ^ ask(a[i] - z, 2); if (!temp) ans++; } cout << ans << n ; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file constants_mem.v when simulating
// the core, constants_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module constants_mem(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("constants_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; string s; int x = 0, y = 0; cin >> s; for (int i = 0; i < t; i++) { if (s[i] == L ) { x--; } else { y++; } } cout << y - x + 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; if (max((3 * a / 10), a - a / 250 * c) == max((3 * b / 10), b - b / 250 * d)) cout << Tie ; else if (max((3 * a / 10), a - a / 250 * c) > max((3 * b / 10), b - b / 250 * d)) cout << Misha ; else if (max((3 * a / 10), a - a / 250 * c) < max((3 * b / 10), b - b / 250 * d)) cout << Vasya ; return 0; }
|
#include <bits/stdc++.h> using namespace std; char ans[2000005]; vector<int> lis[2000005]; string Str[2000005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int m = 0; for (int i = 0; i < n; i++) { string str; cin >> str; Str[i] = str; int k; cin >> k; while (k--) { int a; cin >> a; lis[a].push_back(i); m = max(m, int(a + str.length() - 1)); } } int r = -1, p = 0, ind = 0; for (int i = 1; i <= m; i++) { for (int j = 0; j < lis[i].size(); j++) { int a = Str[lis[i][j]].size(); int b = r - p; if (a > b) { r = Str[lis[i][j]].length(); p = 0; ind = lis[i][j]; } } if (p < r) { ans[i] = Str[ind][p]; p++; } else { ans[i] = a ; } cout << ans[i]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char _; int num_rectangles; pair<pair<int, int>, pair<int, int> > rectangles[135000], pre[135000], suff[135000]; pair<pair<int, int>, pair<int, int> > intersection( pair<pair<int, int>, pair<int, int> > first, pair<pair<int, int>, pair<int, int> > second) { if (first.first.first == INT_MIN || second.first.first == INT_MIN) return {{INT_MIN, INT_MIN}, {INT_MIN, INT_MIN}}; int tx = max(first.first.first, second.first.first), bx = min(first.second.first, second.second.first); int ty = max(first.first.second, second.first.second), by = min(first.second.second, second.second.second); if (bx < tx || by < ty) return {{INT_MIN, INT_MIN}, {INT_MIN, INT_MIN}}; return {{tx, ty}, {bx, by}}; } int main() { scanf( %d , &num_rectangles); for (int i = 0; i < num_rectangles; i++) scanf( %d %d %d %d , &rectangles[i].first.first, &rectangles[i].first.second, &rectangles[i].second.first, &rectangles[i].second.second); sort(rectangles, rectangles + num_rectangles); pre[0] = rectangles[0]; suff[num_rectangles - 1] = rectangles[num_rectangles - 1]; for (int i = 1; i < num_rectangles; i++) { pre[i] = intersection(pre[i - 1], rectangles[i]); suff[num_rectangles - i - 1] = intersection( suff[num_rectangles - i], rectangles[num_rectangles - i - 1]); } for (int i = 0; i < num_rectangles; i++) { if (i == 0) { if (suff[1].first.first != INT_MIN) { printf( %d %d n , suff[1].first.first, suff[1].first.second); return 0; } } else if (i == num_rectangles - 1) { if (pre[num_rectangles - 2].first.first != INT_MIN) { printf( %d %d n , pre[num_rectangles - 2].first.first, pre[num_rectangles - 2].first.second); return 0; } } else { pair<pair<int, int>, pair<int, int> > first = pre[i - 1], second = suff[i + 1], intersect = intersection(first, second); if (intersect.first.first != INT_MIN) { printf( %d %d n , intersect.first.first, intersect.first.second); return 0; } } } if (pre[num_rectangles - 1].first.first != INT_MIN) { printf( %d %d n , pre[num_rectangles - 1].first.first, pre[num_rectangles - 1].first.second); return 0; } printf( -1 n ); }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_odd_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ODD_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_odd_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_odd_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_odd_parity_psl_logic.v"
`else
`endmodule // ovl_odd_parity
`endif
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.