text
stringlengths 59
71.4k
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XOR3_PP_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_PP_BLACKBOX_V
|
module LUT # (parameter SIZE=8)
(
input wire [SIZE-1:0] A,
input wire [1:0] B,
output reg [SIZE+1:0] Result
);
wire [SIZE+1:0] wD0, wD1, wD2, wD3;
assign wD1 = {2'b0, A};
assign wD0 = wD1 ^ wD1; // Esto siempre es cero, de la longitud adecuada.
assign wD2 = {1'b0, A, 1'b0};
assign wD3 = wD2 + wD1;
always @ (A, B)
begin
case (B)
//-------------------------------------
2'b00:
begin
Result <= wD0;
end
//-------------------------------------
2'b01:
begin
Result <= wD1;
end
//-------------------------------------
2'b10:
begin
Result <= wD2;
end
//-------------------------------------
2'b11:
begin
Result <= wD3;
end
//-------------------------------------
endcase
end
endmodule
module Mult4x4
(
input wire [3:0] A,
input wire [3:0] B,
output wire [7:0] Result
);
wire [5:0] wResInt1,wResInt2;
LUT # ( 4 ) LUT1
(
.A(A),
.B(B[1:0]),
.Result(wResInt1)
);
LUT # ( 4 ) LUT2
(
.A(A),
.B(B[3:2]),
.Result(wResInt2)
);
assign Result = ((wResInt2<<2) + wResInt1);
endmodule
module Mult16x16
(
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Result
);
wire [17:0] wResInt1,wResInt2,wResInt3,wResInt4,wResInt5,wResInt6,wResInt7,wResInt8;
LUT # ( 16 ) LUT1
(
.A(A),
.B(B[1:0]),
.Result(wResInt1)
);
LUT # ( 16 ) LUT2
(
.A(A),
.B(B[3:2]),
.Result(wResInt2)
);
LUT # ( 16 ) LUT3
(
.A(A),
.B(B[5:4]),
.Result(wResInt3)
);
LUT # ( 16 ) LUT4
(
.A(A),
.B(B[7:6]),
.Result(wResInt4)
);
LUT # ( 16 ) LUT5
(
.A(A),
.B(B[9:8]),
.Result(wResInt5)
);
LUT # ( 16 ) LUT6
(
.A(A),
.B(B[11:10]),
.Result(wResInt6)
);
LUT # ( 16 ) LUT7
(
.A(A),
.B(B[13:12]),
.Result(wResInt7)
);
LUT # ( 16 ) LUT8
(
.A(A),
.B(B[15:14]),
.Result(wResInt8)
);
assign Result = ({wResInt8, 14'b0} + {2'b0, wResInt7, 12'b0}
+ {4'b0, wResInt6, 10'b0} + {6'b0, wResInt5, 8'b0}
+ {8'b0, wResInt4, 6'b0} + {8'b0, wResInt3, 4'b0}
+ {10'b0, wResInt2, 2'b0} + {14'b0, wResInt1});
endmodule
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } void ran() { srand(chrono::steady_clock::now().time_since_epoch().count()); } long long get_rand() { long long a = rand(); long long b = rand(); return a * (RAND_MAX + 1ll) + b; } void solve() { int n, m; cin >> n >> m; vector<int> subs[n + 1], inc[n + 1]; int labels[n + 1]; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; subs[a].push_back(b); inc[b].push_back(a); } vector<int> rem; for (int i = 1; i <= n; i++) { int from0 = 0, from1 = 0, from2 = 0, total = 0; for (auto x : inc[i]) { total++; if (labels[x] == 0) { from0++; } else if (labels[x] == 1) { from1++; } else { from2++; } } if (from2 == total) { labels[i] = 0; } else if (from1 == 0) { labels[i] = 1; } else { rem.push_back(i); labels[i] = 2; } } cout << rem.size() << endl; for (auto x : rem) cout << x << ; cout << endl; } signed main() { ran(); fast(); int t = 1; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:400000000 ) int n, t; int H; string s; int ok(int rest, int last) { int time = 0; for (int i = 0; i < (last + 1); i++) { time++; if (time > t) return 0; if (time + (last - i) * 2 <= t) return 1; if (s[i] == S ) rest++; if (s[i] == H ) rest--; if (rest < 0) { int from = i; while (rest < 0) { i++; if (s[i] == S ) rest++; if (s[i] == H ) rest--; } time += (i - from) * 3; } } return time <= t; } int main() { cin >> n >> t >> s; for (int i = 0; i < (n); i++) H += s[i] == H ; int lo = -1, hi = H + 1; while (lo + 1 < hi) { int mi = (lo + hi) / 2; int rest = mi; int last = 0; for (int i = 0; i < (n); i++) { if (s[i] == S ) { if (rest < 0) last = i; rest++; } if (s[i] == H ) { last = i; rest--; } } if (rest < 0) lo = mi; else { if (ok(mi, last)) hi = mi; else lo = mi; } } if (hi == H + 1) cout << -1 << endl; else cout << hi << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_pwrgood_pp$PG$S (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND ,
SLEEP
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
input SLEEP ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_ptp_32;
// Parameters
parameter DATA_WIDTH = 32;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
parameter LOGIC_PTP_PERIOD_NS = 4'h3;
parameter LOGIC_PTP_PERIOD_FNS = 16'h3333;
parameter PTP_PERIOD_NS = 4'h3;
parameter PTP_PERIOD_FNS = 16'h3333;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter TX_PTP_TS_ENABLE = 1;
parameter RX_PTP_TS_ENABLE = 1;
parameter TX_PTP_TS_FIFO_DEPTH = 64;
parameter RX_PTP_TS_FIFO_DEPTH = 64;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TAG_ENABLE = 1;
parameter PTP_TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg ptp_sample_clk = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag = 0;
reg s_axis_tx_ptp_ts_valid = 0;
reg m_axis_tx_ptp_ts_ready = 0;
reg rx_axis_tready = 0;
reg m_axis_rx_ptp_ts_ready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts_96 = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire s_axis_tx_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag;
wire m_axis_tx_ptp_ts_valid;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96;
wire m_axis_rx_ptp_ts_valid;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
ptp_sample_clk,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
s_axis_tx_ptp_ts_tag,
s_axis_tx_ptp_ts_valid,
m_axis_tx_ptp_ts_ready,
rx_axis_tready,
m_axis_rx_ptp_ts_ready,
xgmii_rxd,
xgmii_rxc,
ptp_ts_96,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
s_axis_tx_ptp_ts_ready,
m_axis_tx_ptp_ts_96,
m_axis_tx_ptp_ts_tag,
m_axis_tx_ptp_ts_valid,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
m_axis_rx_ptp_ts_96,
m_axis_rx_ptp_ts_valid,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_ptp_32.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_ptp_32);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.ptp_sample_clk(ptp_sample_clk),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.m_axis_tx_ptp_ts_96(m_axis_tx_ptp_ts_96),
.m_axis_tx_ptp_ts_tag(m_axis_tx_ptp_ts_tag),
.m_axis_tx_ptp_ts_valid(m_axis_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(m_axis_tx_ptp_ts_ready),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.m_axis_rx_ptp_ts_96(m_axis_rx_ptp_ts_96),
.m_axis_rx_ptp_ts_valid(m_axis_rx_ptp_ts_valid),
.m_axis_rx_ptp_ts_ready(m_axis_rx_ptp_ts_ready),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> int main() { int m, n, i, j, c; int coordenadas[3][2]; scanf( %d%d , &n, &m); char ciudad[n][m]; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { scanf( n%c , &ciudad[i][j]); } } c = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (ciudad[i][j] == * ) { coordenadas[c][0] = i; coordenadas[c][1] = j; c++; } } } if (coordenadas[0][0] != coordenadas[1][0] && coordenadas[0][0] != coordenadas[2][0]) printf( %d , coordenadas[0][0] + 1); else if (coordenadas[1][0] != coordenadas[0][0] && coordenadas[1][0] != coordenadas[2][0]) printf( %d , coordenadas[1][0] + 1); else printf( %d , coordenadas[2][0] + 1); printf( ); if (coordenadas[0][1] != coordenadas[1][1] && coordenadas[0][1] != coordenadas[2][1]) printf( %d , coordenadas[0][1] + 1); else if (coordenadas[1][1] != coordenadas[0][1] && coordenadas[1][1] != coordenadas[2][1]) printf( %d , coordenadas[1][1] + 1); else printf( %d , coordenadas[2][1] + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class A, class B> ostream& operator<<(ostream& o, pair<A, B>& p) { return o << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& o, const vector<T>& v) { o << { ; for (typeof((v).begin()) it = (v).begin(); it != (v).end(); it++) o << *it << , ; return o << } ; } struct debugger { ostream& out; bool first; void start() { first = true; } debugger(ostream& out) : out(out) { start(); } void nl() { out << endl; start(); } template <class T> debugger& operator,(T& v) { if (first) first = false; else out << , ; out << v; return *this; } template <class T> debugger& operator,(pair<T*, int> arr) { out << { ; for (typeof((arr.second) - 1) i = (0); i <= ((arr.second) - 1); i++) { out << arr.first[i] << , ; } out << } ; return *this; } } dbg(cerr); long long pyra(long long n) { return (n + 1) * (n + 1); } long long incr(long long n) { return (n * (n + 1)) / 2; } long long f(long long x, long long y, long long step, long long n) { long long ret = 2 * pyra(step) - (2 * step + 1); if (x + step > n) { ret -= pyra(x + step - n - 1); } if (y + step > n) { ret -= pyra(y + step - n - 1); } if (x - step < 1) { ret -= pyra(1 - (x - step) - 1); } if (y - step < 1) { ret -= pyra(1 - (y - step) - 1); } if (step - 1 - (n - x) - (n - y) > 0) { ret += incr(step - 1 - (n - x) - (n - y)); } if (step - 1 - (n - x) - (y - 1) > 0) { ret += incr(step - 1 - (n - x) - (y - 1)); } if (step - 1 - (x - 1) - (y - 1) > 0) { ret += incr(step - 1 - (x - 1) - (y - 1)); } if (step - 1 - (x - 1) - (n - y) > 0) { ret += incr(step - 1 - (x - 1) - (n - y)); } return ret; } int main() { long long n, x, y, c, lo, hi; cin >> n >> x >> y >> c; lo = 0; hi = 1e9 + 10; {} while (lo < hi) { long long mid = (lo + hi) / 2; if (f(x, y, mid, n) < c) lo = mid + 1; else hi = mid; } cout << lo << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:13:33 03/13/2014
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
A,
B,
ALU_operation,
shamt,
res,
zero,
overflow
);
input wire [31: 0] A, B;
input wire [ 3: 0] ALU_operation;
input wire [ 4: 0] shamt;
output reg [31: 0] res;
output wire zero;
output wire overflow;
wire [31: 0] res_and, res_or, res_add, res_sub, res_nor, res_slt,
res_xor, res_srl, res_sll, res_addu, res_subu, res_sltu, res_lh, res_sh, res_sra, res_lhu;
reg [31: 0] mask4 = 32'h0000_ffff;
wire [31: 0] mask;
wire [31: 0] res_tmp;
reg flag = 0;
//assign mask = B[1] ? 32'hffff_0000 : 32'h0000_ffff;
assign mask = res_add[1] ? 32'hffff_0000 : 32'h0000_ffff;
always @(ALU_operation) begin
flag <= res_add[1];
end
assign res_tmp = A & (flag?32'hffff_0000 : 32'h0000_ffff);
//assign res_tmp = A & mask;
always @(posedge ALU_operation[0]) mask4 = mask;
parameter one = 32'h00000001, zero_0 = 32'h00000000;
assign res_and = A & B;
assign res_or = A | B;
assign res_nor = ~(A | B);
assign res_xor = A ^ B;
assign res_srl = B >> shamt;
assign res_sll = B << shamt;
assign res_sra = $signed(B) >>> shamt;
assign res_add = $signed(A) + $signed(B);
assign res_sub = $signed(A) - $signed(B);
assign res_slt = ($signed(A) < $signed(B)) ? one : zero_0;
assign res_addu = $unsigned(A) + $unsigned(B);
assign res_subu = $unsigned(A) - $unsigned(B);
assign res_sltu = ($unsigned(A) < $unsigned(B)) ? one : zero_0;
assign res_lh = flag ? {{16{res_tmp[31]}}, res_tmp[31:16]} : {{16{res_tmp[15]}}, res_tmp[15:0]};
assign res_lhu = flag ? {16'h0, res_tmp[31:16]} : {16'h0, res_tmp[15:0]};
assign res_sh = mask4[0] ? (A&(~mask4) | {16'h0, B[15:0]}) : (A&(~mask4) | {B[15:0], 16'h0});
always @(*)
case (ALU_operation)
4'b0000: res = res_and;
4'b0001: res = res_or;
4'b0010: res = res_add;
4'b0110: res = res_sub;
4'b0100: res = res_nor;
4'b0111: res = res_slt;
4'b0011: res = res_xor;
4'b0101: res = res_srl;
4'b1000: res = res_sll;
4'b1001: res = res_addu;
4'b1010: res = res_subu;
4'b1011: res = res_sltu;
4'b1100: res = res_lh;
4'b1101: res = res_sh;
4'b1110: res = res_sra;
4'b1111: res = res_lhu;
default: res = res_add;
endcase
assign zero = (res == zero_0) ? 1'b1 : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__decap (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; string tostring(int x) { ostringstream o; o << x; return o.str(); } int toint(string s) { istringstream st(s); int i; st >> i; return i; } const int mod = 1e9 + 7; const int N = 1e6 + 10; const int inf = 2e9; const double eps = 1e-7; const long long INF = (long long)1e18; int n; long long h, k; long long a[N]; int main() { cin >> n >> h >> k; for (int i = 0; i < (n); ++i) cin >> a[i]; int i = 0, j = 0; long long sum = 0; long long left = 0; long long ans = 0; while (i < n) { j = i; sum = left; while (j < n && sum + a[j] <= h) { sum += a[j]; j++; } ans += sum / k; left = sum % k; if (j < n && left + a[j] > h) { ans++; left = 0; } i = j; } if (left) ans++; cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, ans; int num[1000010], flag[1000010]; int fa[1000010], vis[1000010]; int Find(int x) { return fa[x] = x == fa[x] ? x : Find(fa[x]); } void Union(int x, int y) { int fx = Find(x); int fy = Find(y); if (fx != fy) fa[fy] = fx; } int main() { int t, C = 1; while (scanf( %d%d , &n, &m) != EOF) { memset(num, 0, sizeof(num)); memset(flag, 0, sizeof(flag)); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) fa[i] = i; int u, v; vis[1] = 1; for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); if (u != v) { num[u]++; num[v]++; vis[u]++; vis[v]++; Union(u, v); } else vis[u]++; } int ans = 0, k = 0, tong = 0; for (int i = 1; i <= n; i++) if (num[i] & 1) flag[Find(i)]++; for (int i = 1; i <= n; i++) if (vis[i] && Find(i) == i) { if (flag[i]) ans += flag[i]; else tong++; k++; } if (k == 1) printf( %d n , ans / 2); else printf( %d n , ans / 2 + tong); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 4e5 + 2, inf = 1e12 + 7; vector<pair<int, int> > vec[N]; pair<int, pair<int, int> > edg[N]; long long int n, dis[N], dis2[N], st[N], ed[N]; long long int T[2 * N], lzy[2 * N], tim; void dfs(int u, int pr) { st[u] = ++tim; for (auto x : vec[u]) { int v = x.first, w = x.second; if (v == pr) continue; dis[v] = dis[u] + w; dfs(v, u); } ed[u] = tim; } void push_down(int nod, int lo, int hi) { T[nod] += lzy[nod]; if (lo != hi) { lzy[2 * nod] += lzy[nod]; lzy[2 * nod + 1] += lzy[nod]; } lzy[nod] = 0; } void updt(int nod, int lo, int hi, int l, int r, int vl) { if (lzy[nod]) push_down(nod, lo, hi); if (hi < l || lo > r || lo > hi) return; if (lo >= l && hi <= r) { T[nod] += vl; if (lo != hi) { lzy[2 * nod] += vl; lzy[2 * nod + 1] += vl; } return; } int md = (lo + hi) >> 1; updt(2 * nod, lo, md, l, r, vl); updt(2 * nod + 1, md + 1, hi, l, r, vl); T[nod] = min(T[2 * nod], T[2 * nod + 1]); } long long int qry(int nod, int lo, int hi, int l, int r) { if (lzy[nod]) push_down(nod, lo, hi); if (hi < l || lo > r || lo > hi) return inf; if (lo >= l && hi <= r) return T[nod]; int md = (lo + hi) >> 1; return min(qry(2 * nod, lo, md, l, r), qry(2 * nod + 1, md + 1, hi, l, r)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc = 1, t = 0; while (tc--) { int q; cin >> n >> q; for (int i = 1; i < n; i++) { int u, v, c; cin >> u >> v >> c; vec[u].push_back(make_pair(v, c)); edg[i] = make_pair(u, make_pair(v, c)); } for (int i = n; i < n + n - 1; i++) { int u, v, c; cin >> u >> v >> c; edg[i] = make_pair(u, make_pair(v, c)); dis2[u] = c; } dfs(1, -1); for (int i = 1; i <= n; i++) updt(1, 1, n, st[i], st[i], dis[i] + dis2[i]); while (q--) { int typ; cin >> typ; if (typ == 1) { int id, w; cin >> id >> w; int u = edg[id].first, v = edg[id].second.first; int c = edg[id].second.second; if (id < n) { updt(1, 1, n, st[v], ed[v], -c); updt(1, 1, n, st[v], ed[v], w); edg[id].second.second = w; } else { updt(1, 1, n, st[u], st[u], -c); updt(1, 1, n, st[u], st[u], w); edg[id].second.second = w; dis2[u] = w; } } else { int u, v; cin >> u >> v; if (st[v] >= st[u] && ed[u] >= ed[v]) { cout << qry(1, 1, n, st[v], st[v]) - qry(1, 1, n, st[u], st[u]) + dis2[u] - dis2[v] << n ; } else { long long int rs = qry(1, 1, n, st[u], ed[u]); rs -= qry(1, 1, n, st[u], st[u]); rs += qry(1, 1, n, st[v], st[v]); rs += dis2[u] - dis2[v]; cout << rs << n ; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1005; template <typename T> void chkmax(T &x, T y) { x = max(x, y); } template <typename T> void chkmin(T &x, T y) { x = min(x, y); } template <typename T> void read(T &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } int n, a[MAXN]; int main() { read(n); vector<pair<int, int>> ans; for (int i = 1; i <= n; i++) read(a[i]); for (int i = 1; i <= n; i++) { vector<int> p; for (int j = i + 1; j <= n; j++) if (a[j] < a[i]) p.push_back(j); sort(p.begin(), p.end(), [&](int x, int y) { if (a[x] != a[y]) return a[x] > a[y]; else return x > y; }); for (auto x : p) ans.emplace_back(i, x); } cout << ans.size() << endl; for (auto x : ans) printf( %d %d n , x.first, x.second); return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// //
// CDC (clock domain crossing) general purpose FIFO with gray counter //
// //
// Copyright (C) 2011 Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This RTL is free hardware: you can redistribute it and/or modify //
// it under the terms of the GNU Lesser General Public License //
// as published by the Free Software Foundation, either //
// version 3 of the License, or (at your option) any later version. //
// //
// This RTL is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// Handshaking protocol: //
// //
// Both the input and the output port employ the same handshaking mechanism. //
// The data source sets the valid signal (*_vld) and the data drain confirms //
// the transfer by setting the ready signal (*_rdy). //
// //
// -------- vld ----------------- vld -------- //
// ) S | ------> | D S | ------> | D ( //
// ( R | | R CDC R | | R ) //
// ) C | <------ | N C | <------ | N ( //
// -------- rdy ----------------- rdy -------- //
// //
////////////////////////////////////////////////////////////////////////////////
module cdc #(
// size parameters
parameter integer DW = 1, // data width
parameter integer FF = 4, // FIFO depth
// implementation parameters
parameter integer SS = 2, // synchronization stages
// interface parameters
parameter RI = 1, // registered input data
parameter RO = 1 // registered output data
)(
// input port
input wire ffi_clk, // clock
input wire ffi_rst, // reset
input wire [DW-1:0] ffi_dat, // data
input wire ffi_vld, // valid
output wire ffi_rdy, // ready
// output port
input wire ffo_clk, // clock
input wire ffo_rst, // reset
output wor [DW-1:0] ffo_dat, // data
output wire ffo_vld, // valid
input wire ffo_rdy // ready
);
`ifdef XC3S250E
// Xilinx ISE used to compile the Spartan 3E device does not support the $clog2 function
function integer clog2 (input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
localparam CW = clog2(FF)+1; // counter width
`else
localparam CW = $clog2(FF)+1; // counter width
`endif
localparam G0 = {1'b1,{CW-1{1'b0}}};
////////////////////////////////////////////////////////////////////////////////
// gray code related functions
////////////////////////////////////////////////////////////////////////////////
// conversion from integer to gray
function [CW-1:0] int2gry (input [CW-1:0] val);
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction
// conversion from gray to integer
function [CW-1:0] gry2int (input [CW-1:0] val);
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction
// gray increment (with conversion into integer and back to gray)
function [CW-1:0] gry_inc (input [CW-1:0] gry_gry);
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// local signals //
////////////////////////////////////////////////////////////////////////////////
// input port
wire ffi_trn; // transfer
wire ffi_end; // counter end
reg [CW-1:0] ffi_ref; // counter gray reference
reg [CW-1:0] ffi_gry; // counter gray
reg [CW-1:0] ffi_syn [SS-1:0]; // synchronization
// CDC FIFO memory
reg [DW-1:0] cdc_mem [0:FF-1];
// output port
wire ffo_trn; // transfer
wire ffo_end; // counter end
reg [CW-1:0] ffo_gry; // counter gray
reg [CW-1:0] ffo_syn [SS-1:0]; // synchronization
// generate loop index
genvar i;
////////////////////////////////////////////////////////////////////////////////
// input port control/status logic //
////////////////////////////////////////////////////////////////////////////////
// transfer
assign ffi_trn = ffi_vld & ffi_rdy;
// synchronization
generate for (i=0; i<SS; i=i+1) begin : ffi_cdc
if (i==0) begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffo_gry;
end else begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffi_syn [i-1];
end
end endgenerate
// counter gray
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_gry <= {CW{1'b0}};
else if (ffi_trn) ffi_gry <= ffi_end ? ffi_gry ^ G0 : gry_inc (ffi_gry);
// counter gray reference
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_ref <= int2gry(-FF);
else if (ffi_trn) ffi_ref <= ffi_end ? ffi_ref ^ G0 : gry_inc (ffi_ref);
// status
assign ffi_rdy = ffi_syn [SS-1] != ffi_ref;
////////////////////////////////////////////////////////////////////////////////
// input port data/memory logic //
////////////////////////////////////////////////////////////////////////////////
// binary counter
reg [CW-2:0] ffi_cnt;
// counter end
assign ffi_end = ffi_cnt == (FF-1);
// counter binary
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_cnt <= 'b0;
else if (ffi_trn) ffi_cnt <= ffi_end ? 'b0 : ffi_cnt + 'b1;
// data memory
always @ (posedge ffi_clk)
if (ffi_trn) cdc_mem [ffi_cnt] <= ffi_dat;
////////////////////////////////////////////////////////////////////////////////
// output port data/memory logic //
////////////////////////////////////////////////////////////////////////////////
// one hot counter
reg [CW-2:0] ffo_cnt;
// counter end
assign ffo_end = ffo_cnt == (FF-1);
// counter one hot
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_cnt <= 'b0;
else if (ffo_trn) ffo_cnt <= ffo_end ? 'b0 : ffo_cnt + 'b1;
// asynchronous output data
assign ffo_dat = cdc_mem [ffo_cnt];
////////////////////////////////////////////////////////////////////////////////
// output port control/status logic //
////////////////////////////////////////////////////////////////////////////////
// transfer
assign ffo_trn = ffo_vld & ffo_rdy;
// synchronization
generate for (i=0; i<SS; i=i+1) begin : ffo_cdc
if (i==0) begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffi_gry;
end else begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffo_syn [i-1];
end
end endgenerate
// counter gray
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_gry <= {CW{1'b0}};
else if (ffo_trn) ffo_gry <= ffo_end ? ffo_gry ^ G0 : gry_inc (ffo_gry);
// status
assign ffo_vld = ffo_syn [SS-1] != ffo_gry;
endmodule
|
#include <bits/stdc++.h> using namespace std; int parent[100000], Size[100000]; void init(int n) { for (int i = 0; i < n; i++) { parent[i] = i; Size[i] = 1; } } int Find(int u) { if (u != parent[u]) parent[u] = Find(parent[u]); return parent[u]; } void Union(int u, int v) { u = Find(u); v = Find(v); if (u != v) { if (Size[u] < Size[v]) swap(u, v); parent[v] = u; Size[u] += Size[v]; } } int qa[100000], qb[100000], big[100000], table[450][100000] = {}; bool visited[100000] = {}, match[100000] = {}; vector<int> bigVertices, temp[100000], appear[100000]; vector<vector<int>> comp; vector<pair<int, int>> edges[100000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; a--, b--, c--; edges[c].emplace_back(a, b); } int q; cin >> q; for (int i = 0; i < q; i++) { cin >> qa[i] >> qb[i]; qa[i]--, qb[i]--; } init(n); for (int c = 0; c < m; c++) { for (auto e : edges[c]) Union(e.first, e.second); for (auto e : edges[c]) { if (!visited[e.first]) { temp[Find(e.first)].push_back(e.first); visited[e.first] = true; } if (!visited[e.second]) { temp[Find(e.second)].push_back(e.second); visited[e.second] = true; } } for (auto e : edges[c]) { if (!temp[e.first].empty()) { comp.push_back(temp[e.first]); temp[e.first].clear(); } if (!temp[e.second].empty()) { comp.push_back(temp[e.second]); temp[e.second].clear(); } visited[e.first] = visited[e.second] = false; parent[e.first] = e.first, parent[e.second] = e.second; Size[e.first] = Size[e.second] = 1; } } for (int i = 0; i < comp.size(); i++) for (int j = 0; j < comp[i].size(); j++) appear[comp[i][j]].push_back(i); for (int i = 0; i < n; i++) { if (appear[i].size() > 450) { big[i] = bigVertices.size(); bigVertices.push_back(i); } else big[i] = -1; } for (int i = 0; i < bigVertices.size(); i++) for (int c : appear[bigVertices[i]]) for (int j : comp[c]) table[i][j]++; for (int i = 0; i < q; i++) { int a = qa[i], b = qb[i]; if (big[a] == -1) swap(a, b); if (big[a] != -1) cout << table[big[a]][b] << n ; else { int ret = 0; for (int c : appear[a]) match[c] = true; for (int c : appear[b]) ret += match[c]; for (int c : appear[a]) match[c] = false; cout << ret << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<int> g[n + 1]; for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } vector<vector<int>> dp(n + 1, vector<int>(k + 1)); int ans = 0; function<void(int, int)> dfs; dfs = [&](int u, int pre) { dp[u][0] = 1; for (auto v : g[u]) { if (v != pre) { dfs(v, u); for (int j = 0; j < k; ++j) { ans += dp[v][j] * dp[u][k - 1 - j]; } for (int j = 1; j <= k; ++j) { dp[u][j] += dp[v][j - 1]; } } } }; dfs(1, 0); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; int a[n]; int b[n]; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == a ) { a[i] = 1; b[i] = 0; } else { a[i] = 0; b[i] = 1; } if (i) { a[i] += a[i - 1]; b[i] += b[i - 1]; } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if ((i == 0 && b[j] == a[j]) || (i != 0 && ((b[j] - b[i - 1]) == (a[j] - a[i - 1])))) { cout << i + 1 << << j + 1 << n ; return; } } } cout << -1 -1 n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); }
|
/*
* Zet processor top level file
* Copyright (c) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet (
// Common signals
input clk_i,
input rst_i,
// Wishbone master interface - fetch
input [15:0] wbf_dat_i,
output [19:1] wbf_adr_o,
output [ 1:0] wbf_sel_o,
output wbf_cyc_o,
output wbf_stb_o,
input wbf_ack_i,
// Wishbone master interface - exec
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
// Interrupt line
input intr, // interrupt request
output inta, // interrupt acknowledge
input [ 3:0] iid, // interrupt id
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [19:0] umie_adr_i;
wire [15:0] umie_dat_o;
wire [15:0] umie_dat_i;
wire umie_we_i;
wire umie_by_i;
wire umie_stb_i;
wire umie_ack_o;
wire umie_tga_i;
// Module instances
zet_core core (
.clk (clk_i),
.rst (rst_i),
.wbf_dat_i(wbf_dat_i),
.wbf_adr_o(wbf_adr_o),
.wbf_sel_o(wbf_sel_o),
.wbf_cyc_o(wbf_cyc_o),
.wbf_stb_o(wbf_stb_o),
.wbf_ack_i(wbf_ack_i),
.umie_adr_o (umie_adr_i),
.umie_dat_i (umie_dat_o),
.umie_dat_o (umie_dat_i),
.umie_we_o (umie_we_i),
.umie_by_o (umie_by_i),
.umie_stb_o (umie_stb_i),
.umie_ack_i (umie_ack_o),
.umie_tga_o (umie_tga_i),
.intr (intr),
.inta (inta),
.iid (iid)
);
zet_wb_master wb_master (
.clk (clk_i),
.rst (rst_i),
.umif_adr_i (16'b0),
.umif_dat_o (),
.umif_stb_i (1'b0),
.umif_by_i (1'b0),
.umif_ack_o (),
.umie_adr_i (umie_adr_i),
.umie_dat_o (umie_dat_o),
.umie_dat_i (umie_dat_i),
.umie_we_i (umie_we_i),
.umie_by_i (umie_by_i),
.umie_stb_i (umie_stb_i),
.umie_ack_o (umie_ack_o),
.umie_tga_i (umie_tga_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Continuous assignments
assign pc = wbf_adr_o;
endmodule
|
#include<iostream> #include<string> using namespace std; int main() { int t; cin>>t; for(int i=0;i<t;i++) { int n; string r,b; cin>>n; cin>>r>>b; int counter1=0,counter2=0; for(int i=0;i<n;i++) { if(r[i]>b[i]) counter1++; else if(r[i]<b[i]) counter2++; } if(counter1>counter2) cout<< RED <<endl; else if(counter1==counter2) cout<< EQUAL <<endl; else cout<< BLUE <<endl; } return 0; }
|
#include <bits/stdc++.h> int main() { int vladik, valera; std::cin >> vladik >> valera; int vladik_rounds = sqrt(vladik); int valera_rounds = valera > vladik_rounds ? sqrt(valera - vladik_rounds) : 0; if (valera_rounds >= vladik_rounds) { std::cout << Vladik n ; } else { std::cout << Valera n ; } return 0; }
|
#include <bits/stdc++.h> using std ::vector; template <typename T> T max(T x, T y) { return (x > y) ? x : y; } template <typename T> T min(T x, T y) { return (x < y) ? x : y; } template <typename T> bool chkmax(T &x, T y) { return (x >= y) ? 0 : (x = y, 1); } template <typename T> bool chkmin(T &x, T y) { return (x <= y) ? 0 : (x = y, 1); } template <typename T> T read(T &in) { in = 0; char ch; T f = 1; while (!isdigit(ch = getchar())) if (ch == - ) f = -1; while (isdigit(ch)) in = in * 10 + ch - 0 , ch = getchar(); return in *= f; } static const int max1 = 100000 + 11; static const int BIT = 16; bool vis[max1]; vector<int> fac[max1]; struct Node { Node *ch[2]; int v; Node() { ch[0] = ch[1] = NULL, v = 100001; } }; struct Trie { Node *root; Trie() { root = new Node; } void Insert(int x) { Node *o = root; chkmin(o->v, x); for (int i = (BIT), ir = (0); i >= (ir); --i) { int c = x >> i & 1; if (!o->ch[c]) o->ch[c] = new Node; o = o->ch[c]; chkmin(o->v, x); } } } T[max1]; void Init(int n = 100000) { for (int i = 1; i <= n; ++i) for (int j = i; j <= n; j += i) fac[j].push_back(i); } void Modify(int x) { if (vis[x]) return; vis[x] = 1; for (vector<int>::iterator i = fac[x].begin(); i != fac[x].end(); ++i) T[*i].Insert(x); } int Query(int x, int k, int s) { if (x % k) return -1; s -= x; int c = 0; Node *o = T[k].root; if (o->v > s) return -1; for (int i = (BIT), ir = (0); i >= (ir); --i) { int w = x >> i & 1; if (s < (1 << i) || o->ch[1] && o->ch[1]->v > s) o = o->ch[0]; else if (!o->ch[0]) o = o->ch[1], c += 1 << i; else if (!o->ch[1]) o = o->ch[0]; else if (w) o = o->ch[0]; else o = o->ch[1], c += 1 << i; } return c; } int main() { int q; read(q); Init(); while (q--) { int o, x, k, s; read(o), read(x); if (o == 1) { Modify(x); } else { read(k), read(s); printf( %d n , Query(x, k, s)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; char a[N], b[N]; int lcp[N][N]; int f[N][N][12]; int main() { int l1, l2, n; scanf( %d%d%d , &l1, &l2, &n); scanf( %s%s , a + 1, b + 1); for (int i = (1); i <= (l1); i++) { for (int j = (1); j <= (l2); j++) { if (a[i] == b[j]) lcp[i][j] = lcp[i - 1][j - 1] + 1; else lcp[i][j] = 0; } } int ans = n; for (int i = (1); i <= (l1); i++) { for (int j = (1); j <= (l2); j++) { for (int k = (1); k <= (n); k++) { int A = lcp[i][j]; f[i][j][k] = max(f[i][j][k], f[i - A][j - A][k - 1] + A); if (f[i][j][k] > f[i + 1][j][k]) f[i + 1][j][k] = f[i][j][k]; if (f[i][j][k] > f[i][j + 1][k]) f[i][j + 1][k] = f[i][j][k]; ans = max(ans, f[i][j][k]); } } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d%d , &n, &k); if ((n * (n - 1)) / 2 < k * n) { printf( -1 n ); return 0; } printf( %d n , n * k); for (int i = 0; i < n; ++i) { for (int j = i + 1, q = 0; q < k; ++q, ++j) { if (j == n) j = 0; printf( %d %d n , i + 1, j + 1); } } return 0; }
|
`timescale 1 us / 1 us
`include "../source/RAM2.v"
module testRAM;
reg[15:0] addr;
reg clk;
reg rst;
reg we;
reg re;
reg[15:0] wdata;
wire[15:0] rdata;
wire ready;
RAM2 mem (
.rst (rst),
.clk (clk),
.we (we),
.re (re),
.addr (addr),
.wdata (wdata),
.rdata (rdata),
.ready (ready)
);
always
#5 clk = !clk;
initial begin
$dumpfile ("../test.vcd");
$dumpvars;
end
initial begin
$display ("\t\ttime,\tclk,\taddr,\twdata,\trdata,\twe");
$monitor ( "%d,\t%b,\t%4h,\t%2h,\t%2h,\t%b",
$time, clk, addr, wdata, rdata, we);
end
initial begin
rst = 1;
clk = 0;
we = 0;
re = 0;
addr = 16'h0000;
wdata = 16'h0000;
#10 rst = 0; re = 1;
#20 wdata = 16'h1212; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'h0001; re = 1;
#20 wdata = 16'h3434; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'hABCD; re = 1;
#20 wdata = 16'h5656; we = 1; re = 0;
#10 we = 0;
#10 addr = 16'h0000; re = 1;
#20 addr = 16'h0001; re = 1;
#20 addr = 16'hABCD; re = 1;
#20 re = 0;
#10 rst = 1;
#10 $finish;
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_mux
*/
module test_axis_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
enable,
select
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_mux_4_64.lxt");
$dumpvars(0, test_axis_mux_4_64);
end
axis_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 18848 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w496,
w527,
w62,
w589,
w18848;
assign w1 = i_data0;
assign w18848 = w589 << 5;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign w496 = w31 << 4;
assign w527 = w31 + w496;
assign w589 = w527 + w62;
assign w62 = w31 << 1;
assign o_data0 = w18848;
//multiplier_block area estimate = 4680.24485393235;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
//
// Author: Steffen Reith ()
//
// Creation Date: Sat May 6 16:32:24 GMT+2 2017
// Module Name: Board_Nexys4 - Behavioral
// Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
//
//
module Board_Nexys4 (nreset,
clk100Mhz,
extInt,
leds,
rgbLeds,
segments_a,
segments_b,
segments_c,
segments_d,
segments_e,
segments_f,
segments_g,
dot,
selector,
pmodA,
sSwitches,
pButtons,
tck,
tms,
tdi,
tdo,
rx,
tx);
// Input ports
input nreset;
input clk100Mhz;
input [0:0] extInt;
input [15:0] sSwitches;
input [4:0] pButtons;
input tck;
input tms;
input tdi;
input rx;
// Output ports
output [15:0] leds;
output [5:0] rgbLeds;
output tdo;
output tx;
output segments_a;
output segments_b;
output segments_c;
output segments_d;
output segments_e;
output segments_f;
output segments_g;
output dot;
output [7:0] selector;
// Bidirectional port
inout [7:0] pmodA;
// Internal reset
wire reset;
// Clock generation
wire boardClk;
wire boardClkLocked;
// Internal wiring
wire [7:0] pmodA_read;
wire [7:0] pmodA_write;
wire [7:0] pmodA_writeEnable;
// Instantiate a PLL/MMCM (makes a 80Mhz clock)
PLL makeClk (.clkIn (clk100Mhz),
.clkOut (boardClk),
.isLocked (boardClkLocked));
// Instantiate the J1SoC core generated by Spinal
J1Nexys4X core (.reset (reset),
.boardClk (boardClk),
.boardClkLocked (boardClkLocked),
.extInt (extInt),
.leds (leds),
.rgbLeds (rgbLeds),
.segments_a (segments_a),
.segments_b (segments_b),
.segments_c (segments_c),
.segments_d (segments_d),
.segments_e (segments_e),
.segments_f (segments_f),
.segments_g (segments_g),
.dot (dot),
.selector (selector),
.pmodA_read (pmodA_read),
.pmodA_write (pmodA_write),
.pmodA_writeEnable (pmodA_writeEnable),
.sSwitches (sSwitches),
.pButtons (pButtons),
.tck (tck),
.tms (tms),
.tdi (tdi),
.tdo (tdo),
.rx (rx),
.tx (tx));
// Make the reset high active
assign reset = !nreset;
// Connect the pmodA read port
assign pmodA_read = pmodA;
// Generate the write port and equip it with tristate functionality
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
assign pmodA[i] = pmodA_writeEnable[i] ? pmodA_write[i] : 1'bZ;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y >= 1) { if (y % 2) res = (res * x) % p; x = ((x % p) * (x % p)) % p; y /= 2; } return res; } void solve() { long long int n, m; cin >> n >> m; cout << power(power(2, m, 1000000007) - 1, n, 1000000007) << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; t = 1; while (t--) { solve(); } }
|
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: cnt_64bit.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cnt_64bit (
aclr,
clock,
cnt_en,
data,
sload,
q);
input aclr;
input clock;
input cnt_en;
input [63:0] data;
input sload;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.data (data),
.sload (sload),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cout (),
.eq (),
.sclr (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "1"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "64"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: sload 0 0 0 0 INPUT NODEFVAL "sload"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @sload 0 0 0 0 sload 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cnt_64bit_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int main() { int n, h, a; vector<int> home, away; cin >> n; vector<int> cnt(100000, 0); vector<int> ans_home(n, 0); vector<int> ans_away(n, 0); for (int i = 0; i < n; i++) { cin >> h >> a; home.push_back(h); away.push_back(a); } for (int i = 0; i < n; i++) cnt[home[i] - 1]++; for (int i = 0; i < n; i++) { ans_home[i] = n - 1 + cnt[away[i] - 1]; ans_away[i] = 2 * (n - 1) - ans_home[i]; } for (int i = 0; i < n; i++) cout << ans_home[i] << << ans_away[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int o[100100]; int ans[6000100]; int main() { int i, j, n; int e = 0; long long x, y; long long m, tmp, st, ed, mid; scanf( %d %I64d , &n, &m); for (i = 1; i <= n; i++) scanf( %d , &o[i]); sort(o + 1, o + n + 1); o[0] = 0; o[n + 1] = 1000000001; for (i = 0; i <= n; i++) { x = o[i] + 1; y = o[i + 1] - 1; if (x <= y) { tmp = ((x + y) * (y - x + 1)) >> 1; if (m - tmp >= 0) { m -= tmp; for (j = x; j <= y; j++) ans[e++] = j; } else { st = x; ed = y; while (st < ed) { mid = (st + ed) >> 1; tmp = ((x + mid) * (mid - x + 1)) >> 1; if (tmp <= m) st = mid + 1; else ed = mid; } st--; tmp = 0; if (x <= st) { tmp = ((x + st) * (st - x + 1)) >> 1; m -= tmp; for (j = x; j <= st; j++) ans[e++] = j; } } } } printf( %d n , e); for (i = 0; i < e; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a / gcd(a, b) * b; } const int mod = 1e9 + 7; long long binpow(long long a, long long b) { long long res = 1; while (b > 0) if (b & 1) { res = (long long)(res * 1ll * a); --b; } else { a = (long long)(a * 1ll * a); b >>= 1; } return (long long)res; } vector<vector<int>> g; vector<bool> used; int pred = -1; int timer = 0; vector<int> tin, tout; void dfs(int v, int p = -1) { used[v] = true; tin[v] = timer; timer++; for (auto to : g[v]) { if (!used[to]) dfs(to); } tout[v] = timer; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; while (q--) { int n, a, b, da, db; cin >> n >> a >> b >> da >> db; vector<vector<int>> g; g.resize(n); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; u--; v--; g[u].push_back(v); g[v].push_back(u); } if (da * 2 >= db) { cout << Alice << endl; continue; } int starta = a - 1; int startb = b - 1; vector<bool> used(n); queue<int> q; used[starta] = true; q.push(starta); vector<int> d(n); while (!q.empty()) { int v = q.front(); q.pop(); for (auto to : g[v]) { if (!used[to]) { used[to] = true; q.push(to); d[to] = d[v] + 1; } } } int ind_max = 0; int maxi = 0; for (int i = 0; i < n; i++) { if (d[i] > maxi) { maxi = d[i]; ind_max = i; } } if (abs(d[startb]) <= da) { cout << Alice << endl; continue; } used.clear(); used.resize(n); used[ind_max] = true; q.push(ind_max); d.clear(); d.resize(n); while (!q.empty()) { int v = q.front(); q.pop(); for (auto to : g[v]) { if (!used[to]) { used[to] = true; q.push(to); d[to] = d[v] + 1; } } } int ans = 0; for (int i = 0; i < n; i++) { ans = max(ans, d[i]); } if (double(ans) / da > 2.0) { cout << Bob << endl; } else { cout << Alice << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace { void Solve(int) { const set<string> bins = { AND , OR , XOR }; int n; cin >> n; vector<string> type(n); vector<int> lef(n, -1), rig(n, -1); for (int i = 0, __i = n; i < __i; ++i) { cin >> type[i] >> lef[i]; if (type[i] != IN ) --lef[i]; if (bins.count(type[i])) { cin >> rig[i]; --rig[i]; } } auto eval = [](const string& t, bool a, bool b) { if (t == AND ) return a and b; else if (t == OR ) return a or b; else return (bool)(a ^ b); }; vector<bool> val(n), flip(n); function<void(int)> dfs1 = [&](int at) { if (type[at] == IN ) { val[at] = lef[at]; } else { dfs1(lef[at]); if (bins.count(type[at])) { dfs1(rig[at]); val[at] = eval(type[at], val[lef[at]], val[rig[at]]); } else { val[at] = !val[lef[at]]; } } }; dfs1(0); function<void(int)> dfs2 = [&](int at) { if (type[at] == IN ) flip[at] = true; else if (type[at] == NOT ) { flip[at] = true; dfs2(lef[at]); } else { if (val[at] != eval(type[at], val[lef[at]] ^ 1, val[rig[at]])) { flip[at] = true; dfs2(lef[at]); } if (val[at] != eval(type[at], val[lef[at]], val[rig[at]] ^ 1)) { flip[at] = true; dfs2(rig[at]); } } }; dfs2(0); for (int i = 0, __i = n; i < __i; ++i) if (type[i] == IN ) cout << (val[0] ^ flip[i]); cout << n ; } void Init() { ios::sync_with_stdio(false); cin.tie(nullptr); } } // namespace int32_t main() { Init(); int tests = 1; for (int test = 1, __test = tests + 1; test < __test; ++test) Solve(test); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> con[100005]; int coun[100005]; void serc(int x, int l) { coun[l]++; for (int i = 0; i < con[x].size(); i++) { serc(con[x][i], l + 1); } return; } int main() { int n; cin >> n; int a; for (int i = 2; i <= n; i++) { cin >> a; con[a].push_back(i); } serc(1, 1); int k = 0; for (int i = 1; i <= n; i++) { k += coun[i] % 2; } printf( %d n , k); }
|
#include <bits/stdc++.h> using namespace std; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcount(s); } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } multiset<string> S; long long n, a[3005]; long long f[3005][3005]; long long F[3005]; void update(int u, long long T) { for (int i = u; i < 3005; i += i & -i) { F[i] = max(F[i], T); } } long long get(int u) { long long res = (1ll << 60); for (int i = u; i >= 0; i--) { res = min(res, F[i]); if (i == 0) break; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<long long> V; cin >> n; for (int i = (1); i <= (n); ++i) { cin >> a[i]; a[i] += n - i; } V.push_back(-1000000005); for (int i = (1); i <= (n); ++i) V.push_back(a[i]); sort((V).begin(), (V).end()); f[0][0] = 0; for (int i = (1); i <= (n); ++i) { long long T = (1ll << 60); for (int j = (0); j <= (n); ++j) { T = min(T, f[i - 1][j]); f[i][j] = T + abs(a[i] - V[j]); } } long long res = (1ll << 60); for (int i = (1); i <= (n); ++i) res = min(res, f[n][i]); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef signed long long ll; #define _P(...) (void)printf(__VA_ARGS__) #define FOR(x,to) for(x=0;x<(to);x++) #define FORR(x,arr) for(auto& x:arr) #define FORR2(x,y,arr) for(auto& [x,y]:arr) #define ALL(a) (a.begin()),(a.end()) #define ZERO(a) memset(a,0,sizeof(a)) #define MINUS(a) memset(a,0xff,sizeof(a)) template<class T> bool chmax(T &a, const T &b) { if(a<b){a=b;return 1;}return 0;} template<class T> bool chmin(T &a, const T &b) { if(a>b){a=b;return 1;}return 0;} //------------------------------------------------------- int T,N,A[5050],S[5050]; ll dp[5050]; void solve() { int i,j,k,l,r,x,y; string s; cin>>T; while(T--) { cin>>N; FOR(i,N) cin>>A[i]; FOR(i,N) cin>>S[i]; FOR(i,N+1) dp[i]=-1LL<<60; ll ret=0; FOR(i,N) { ll ma=0; for(j=i-1;j>=0;j--) if(A[i]!=A[j]) { ll nma=ma+abs(S[i]-S[j]); ma=max(ma,dp[j]+abs(S[i]-S[j])); dp[j]=max(dp[j],nma); } dp[i]=ma; } FOR(i,N) ret=max(ret,dp[i]); cout<<ret<<endl; } } int main(int argc,char** argv){ string s;int i; if(argc==1) ios::sync_with_stdio(false), cin.tie(0); FOR(i,argc-1) s+=argv[i+1],s+= n ; FOR(i,s.size()) ungetc(s[s.size()-1-i],stdin); cout.tie(0); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_1_V
`define SKY130_FD_SC_MS__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_1_V
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Regular sleep controller
* Author: Ye-Sheng Kuo, <>
*
*
* Last modified: 8/11 '14 by Ye-Sheng
*
* Changing log:
* 8/11 '14:
* Renaming ports, adding complementary port
*/
module mbus_regular_sleep_ctrl(
input MBUS_CLKIN,
input RESETn,
input SLEEP_REQ,
output reg MBC_SLEEP,
output MBC_SLEEP_B,
output MBC_CLK_EN,
output reg MBC_CLK_EN_B,
output reg MBC_RESET,
output MBC_RESET_B,
output reg MBC_ISOLATE,
output MBC_ISOLATE_B,
output reg INT_CLR_BUSY
);
assign MBC_SLEEP_B = ~MBC_SLEEP;
assign MBC_CLK_EN = ~MBC_CLK_EN_B;
assign MBC_RESET_B = ~MBC_RESET;
assign MBC_ISOLATE_B = ~MBC_ISOLATE;
`include "include/mbus_def.v"
reg [1:0] fsm_pos, fsm_neg;
parameter HOLD = `IO_HOLD; // During sleep
parameter RELEASE = `IO_RELEASE; // During wake-up
reg POWER_ON_POS, POWER_ON_NEG;
reg RELEASE_CLK_POS, RELEASE_CLK_NEG;
reg RELEASE_RST_POS, RELEASE_RST_NEG;
reg RELEASE_ISO_POS, RELEASE_ISO_NEG;
always @ *
begin
if ((POWER_ON_POS==HOLD)||(POWER_ON_NEG==HOLD))
MBC_SLEEP = HOLD;
else
MBC_SLEEP = RELEASE;
if ((RELEASE_CLK_POS==HOLD)||(RELEASE_CLK_NEG==HOLD))
MBC_CLK_EN_B = HOLD;
else
MBC_CLK_EN_B = RELEASE;
if ((RELEASE_RST_POS==HOLD)||(RELEASE_RST_NEG==HOLD))
MBC_RESET = HOLD;
else
MBC_RESET = RELEASE;
if ((RELEASE_ISO_POS==HOLD)||(RELEASE_ISO_NEG==HOLD))
MBC_ISOLATE = HOLD;
else
MBC_ISOLATE = RELEASE;
end
always @ (posedge MBUS_CLKIN or negedge RESETn)
begin
if (~RESETn)
begin
fsm_pos <= 0;
POWER_ON_POS <= HOLD;
RELEASE_CLK_POS <= RELEASE;
RELEASE_ISO_POS <= HOLD;
RELEASE_RST_POS <= RELEASE;
INT_CLR_BUSY <= 0;
end
else
begin
case (fsm_pos)
0:
begin
POWER_ON_POS <= RELEASE;
RELEASE_CLK_POS <= RELEASE;
fsm_pos <= 1;
INT_CLR_BUSY <= 0;
end
1:
begin
RELEASE_ISO_POS <= RELEASE;
RELEASE_RST_POS <= RELEASE;
fsm_pos <= 2;
end
2:
begin
if (SLEEP_REQ)
begin
RELEASE_ISO_POS <= HOLD;
fsm_pos <= 3;
end
end
3:
begin
fsm_pos <= 0;
RELEASE_RST_POS <= HOLD;
POWER_ON_POS <= HOLD;
RELEASE_CLK_POS <= HOLD;
INT_CLR_BUSY <= 1;
end
endcase
end
end
always @ (negedge MBUS_CLKIN or negedge RESETn)
begin
if (~RESETn)
begin
fsm_neg <= 0;
POWER_ON_NEG <= RELEASE;
RELEASE_CLK_NEG <= HOLD;
RELEASE_ISO_NEG <= RELEASE;
RELEASE_RST_NEG <= HOLD;
end
else
begin
case (fsm_neg)
0:
begin
if (fsm_pos==2'b1)
begin
RELEASE_CLK_NEG <= RELEASE;
fsm_neg <= 1;
end
else
begin
POWER_ON_NEG <= RELEASE;
RELEASE_CLK_NEG <= HOLD;
RELEASE_ISO_NEG <= RELEASE;
RELEASE_RST_NEG <= HOLD;
end
end
1:
begin
RELEASE_RST_NEG <= RELEASE;
fsm_neg <= 2;
end
2:
begin
if (fsm_pos==2'b11)
begin
POWER_ON_NEG <= HOLD;
RELEASE_CLK_NEG <= HOLD;
RELEASE_RST_NEG <= HOLD;
fsm_neg <= 0;
end
end
endcase
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:51:02 2016
/////////////////////////////////////////////////////////////
module GDA_St_N16_M4_P8 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_22_CI, intadd_22_n4, intadd_22_n3, intadd_22_n2, intadd_23_CI,
intadd_23_n3, intadd_23_n2, intadd_23_n1, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77;
CMPR32X2TS intadd_22_U4 ( .A(in1[13]), .B(in2[13]), .C(intadd_22_n4), .CO(
intadd_22_n3), .S(res[13]) );
CMPR32X2TS intadd_23_U3 ( .A(in2[2]), .B(in1[2]), .C(intadd_23_n3), .CO(
intadd_23_n2), .S(res[2]) );
CMPR32X2TS intadd_23_U2 ( .A(in2[3]), .B(in1[3]), .C(intadd_23_n2), .CO(
intadd_23_n1), .S(res[3]) );
CMPR32X2TS intadd_22_U2 ( .A(in1[15]), .B(in2[15]), .C(intadd_22_n2), .CO(
res[16]), .S(res[15]) );
ADDFHX2TS intadd_22_U3 ( .A(in1[14]), .B(in2[14]), .CI(intadd_22_n3), .CO(
intadd_22_n2), .S(res[14]) );
OAI21X2TS U51 ( .A0(in2[8]), .A1(in1[8]), .B0(n56), .Y(n50) );
NAND2X1TS U52 ( .A(in2[10]), .B(in1[10]), .Y(n48) );
NOR2XLTS U53 ( .A(in1[9]), .B(in2[9]), .Y(n49) );
NAND2X4TS U54 ( .A(in2[6]), .B(in1[6]), .Y(n45) );
AOI2BB1XLTS U55 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_23_CI), .Y(res[0])
);
AND2X2TS U56 ( .A(in2[0]), .B(in1[0]), .Y(intadd_23_CI) );
AOI211X2TS U57 ( .A0(n75), .A1(n66), .B0(n74), .C0(n72), .Y(n46) );
OAI22X1TS U58 ( .A0(in1[7]), .A1(in2[7]), .B0(n68), .B1(n46), .Y(n47) );
NOR2X4TS U59 ( .A(in1[5]), .B(in2[5]), .Y(n74) );
NAND2X2TS U60 ( .A(in2[4]), .B(in1[4]), .Y(n66) );
OAI2BB1X2TS U61 ( .A0N(in2[7]), .A1N(in1[7]), .B0(n47), .Y(n56) );
ADDFHX2TS U62 ( .A(in1[12]), .B(in2[12]), .CI(intadd_22_CI), .CO(
intadd_22_n4), .S(res[12]) );
OAI2BB2X1TS U63 ( .B0(n60), .B1(n54), .A0N(n53), .A1N(n52), .Y(n55) );
ADDFHX2TS U64 ( .A(in1[9]), .B(in2[9]), .CI(n65), .CO(n64), .S(res[9]) );
ADDFHX2TS U65 ( .A(in2[8]), .B(in1[8]), .CI(n59), .CO(n65), .S(res[8]) );
OAI21X4TS U66 ( .A0(in2[6]), .A1(in1[6]), .B0(n45), .Y(n72) );
INVX2TS U67 ( .A(n48), .Y(n60) );
AOI22X1TS U68 ( .A0(in2[8]), .A1(in1[8]), .B0(in1[9]), .B1(in2[9]), .Y(n51)
);
INVX2TS U69 ( .A(n45), .Y(n68) );
NAND2X2TS U70 ( .A(in1[5]), .B(in2[5]), .Y(n75) );
OAI21X1TS U71 ( .A0(in2[10]), .A1(in1[10]), .B0(n48), .Y(n63) );
AOI211X1TS U72 ( .A0(n51), .A1(n50), .B0(n49), .C0(n63), .Y(n54) );
INVX2TS U73 ( .A(in1[11]), .Y(n53) );
INVX2TS U74 ( .A(in2[11]), .Y(n52) );
OAI2BB1X1TS U75 ( .A0N(in2[11]), .A1N(in1[11]), .B0(n55), .Y(intadd_22_CI)
);
OAI21X1TS U76 ( .A0(in2[4]), .A1(in1[4]), .B0(n66), .Y(n73) );
XOR2X1TS U77 ( .A(in2[7]), .B(in1[7]), .Y(n70) );
NAND3BX1TS U78 ( .AN(n74), .B(intadd_23_n1), .C(n70), .Y(n58) );
INVX2TS U79 ( .A(n56), .Y(n57) );
OAI31X1TS U80 ( .A0(n72), .A1(n73), .A2(n58), .B0(n57), .Y(n59) );
XOR2X1TS U81 ( .A(in2[11]), .B(in1[11]), .Y(n62) );
OAI22X1TS U82 ( .A0(n64), .A1(n60), .B0(in2[10]), .B1(in1[10]), .Y(n61) );
XNOR2X1TS U83 ( .A(n62), .B(n61), .Y(res[11]) );
XNOR2X1TS U84 ( .A(n64), .B(n63), .Y(res[10]) );
INVX2TS U85 ( .A(n66), .Y(n67) );
OAI22X1TS U86 ( .A0(in2[4]), .A1(in1[4]), .B0(n67), .B1(intadd_23_n1), .Y(
n76) );
OAI21X1TS U87 ( .A0(n74), .A1(n76), .B0(n75), .Y(n71) );
OAI22X1TS U88 ( .A0(n71), .A1(n68), .B0(in2[6]), .B1(in1[6]), .Y(n69) );
XNOR2X1TS U89 ( .A(n70), .B(n69), .Y(res[7]) );
XNOR2X1TS U90 ( .A(n72), .B(n71), .Y(res[6]) );
XNOR2X1TS U91 ( .A(intadd_23_n1), .B(n73), .Y(res[4]) );
NOR2BX1TS U92 ( .AN(n75), .B(n74), .Y(n77) );
XNOR2X1TS U93 ( .A(n77), .B(n76), .Y(res[5]) );
CMPR32X2TS U94 ( .A(in1[1]), .B(in2[1]), .C(intadd_23_CI), .CO(intadd_23_n3),
.S(res[1]) );
initial $sdf_annotate("GDA_St_N16_M4_P8_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; int M = 1000000007; long long n, m; void solve() {} void test() { long long n; cin >> n; vector<int> a(n); int count[101] = { 0, }; for (long long i = 0; i < n; i++) { cin >> a[i]; count[a[i]]++; } bool flag = 1; int ans = 0; for (long long i = 0; i < 101; i++) { if (count[i] == 0 && flag) { cout << 2 * i << endl; return; } if (count[i] == 1 && flag) { ans += i; flag = 0; } if (count[i] == 0 && !flag) { ans += i; cout << ans << endl; return; } } } int main() { long long t; cin >> t; while (t--) test(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, t, f, k, y = 0, w, j = 0, x = 0; cin >> a >> t >> f >> k; w = t; for (;;) { if (x == 0) { if (j % 2 == 1) j++; if (j == k) break; if (w >= f) { x = f; w -= f; } else { cout << -1; return 0; } } else if (x == f) { if (j % 2 == 0) { if (w >= (a - f) * 2) { x = a; w -= (a - f); } else if (w >= a - f) { if (j == k - 1) { x = a; w -= (a - f); } else { w = t; x = a; w -= (a - f); y++; } } else { if (t >= a - f) { w = t; x = a; w -= (a - f); y++; } else { cout << -1; return 0; } } } else { if (w >= f * 2) { x = 0; w -= f; } else if (w >= f) { if (j == k - 1) { x = 0; w -= f; } else { w = t; x = 0; w -= f; y++; } } else { if (t >= f) { w = t; x = 0; w -= f; y++; } else { cout << -1; return 0; } } } } else if (x == a) { if (j % 2 == 0) j++; if (j == k) break; if (w >= a - f) { x = f; w -= (a - f); } else { cout << -1; return 0; } } if (j == k) break; } cout << y; }
|
module main;
reg clk, rst, done;
wire [31:0] x;
reg [3:0] a;
reg [23:0] in, out;
reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[3:0];
// Debug signals to see 'em under signalscan
// -- iverilog generates a warning here
wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0];
// generate a clock
always
#10 clk = ~clk;
// -- iverilog generates a warning here
assign x[31:0] = { 28'hfffffff, (~a[3:0] + 4'd1) };
initial
begin
$display ("\n<< BEGIN >>");
rst = 1'b0;
a[3:0] = 4'b0101;
// -- iverilog internal value is not dealt with correctly (see value
out[23:0] = ( rst ? 24'o7654_3210 : in[23:0] );
casex ( done )
// -- iverilog generate errors - "could not match signal"
1'b1: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = {3'b000,
lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1]};
1'b0: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = { lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1],
lt_fifo_cam_indices[0]};
endcase
$display ("\n<< END >>");
$finish;
end
// Waves definition
// initial
// begin
// $dumpfile("out.dump");
// $dumpvars(0, main);
// end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; const int N = (int)2e5 + 7; const int MOD = (int)1e9 + 7; const int INF = (int)2e7; const long long BIG = 1e18; int a[N], b[N], c[N], d[N]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int n, ans = 0; cin >> n; unordered_map<int, int> cnt; for (int i = 0; i < n; i++) cin >> a[i], cnt[a[i]]++; set<pair<int, int> > q; for (auto x : cnt) q.insert(make_pair(x.second, x.first)); while (int(q.size()) >= 3) { vector<pair<int, int> > del; auto it = q.end(); --it; b[ans] = it->second; del.push_back(*it); --it; c[ans] = it->second; del.push_back(*it); --it; d[ans] = it->second; del.push_back(*it); ++ans; for (auto x : del) { pair<int, int> w = x; q.erase(w); if (w.first != 1) q.insert(make_pair(w.first - 1, w.second)); } } cout << ans << n ; for (int i = 0; i < ans; i++) { vector<int> p = {b[i], c[i], d[i]}; sort(p.begin(), p.end()); cout << p[2] << << p[1] << << p[0] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i; cin >> n; long long int a[n]; for (i = 0; i < n; i = i + 1) { cin >> a[i]; } long long int mn = a[n - 1]; long long int m[n]; for (i = n - 1; i >= 0; i--) { mn = min(mn, a[i]); m[i] = mn; } for (i = 0; i < n; i = i + 1) { long long int low = i; long long int high = n - 1; long long int res = i; while (low <= high) { long long int mid = (low + high) / 2; if (m[mid] >= a[i]) { high = mid - 1; } else if (m[mid] < a[i]) { low = mid + 1; res = max(res, mid); } } cout << res - i - 1 << ; } cout << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, model
);
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
input clk;
// Parameter so we can test for different model error
parameter MODEL_WIDTH = 10;
input [MODEL_WIDTH-1:0] model;
initial $write("Model width = %0d\n", MODEL_WIDTH);
sub sub (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
module sub (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
integer cyc = 0;
reg [127:0] save128;
reg [47:0] save48;
reg [1:0] save2;
reg [255:0] cycdone; // Make sure each cycle executes exactly once
reg [31:0] vec[2:1][2:1];
reg [2:1][2:1][31:0] pvec;
real r;
string s,s2;
string sarr[2:1];
string assoc[string];
string si;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d\n", $time, cyc);
`endif
si = "siimmed";
cyc <= cyc + 1;
if (cycdone[cyc[7:0]]) $stop;
cycdone[cyc[7:0]] <= '1;
if (cyc==0) begin
// Setup
save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e;
save48 <= 48'h4afe43fb79d7;
save2 <= 2'b10;
vec[1][1] <= 32'h0101;
vec[1][2] <= 32'h0102;
vec[2][1] <= 32'h0201;
vec[2][2] <= 32'h0202;
pvec[1][1] <= 32'h10101;
pvec[1][2] <= 32'h10102;
pvec[2][1] <= 32'h10201;
pvec[2][2] <= 32'h10202;
r <= 1.234;
s <= "hello";
sarr[1] <= "sarr[1]";
sarr[2] <= "sarr[2]";
assoc["mapped"] <= "Is mapped";
end
if (cyc==1) begin
if ($test$plusargs("save_restore")!=0) begin
// Don't allow the restored model to run from time 0, it must run from a restore
$write("%%Error: didn't really restore\n");
$stop;
end
end
else if (cyc==99) begin
if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop;
if (save48 !== 48'h4afe43fb79d7) $stop;
if (save2 !== 2'b10) $stop;
if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop;
if (vec[1][1] !== 32'h0101) $stop;
if (vec[1][2] !== 32'h0102) $stop;
if (vec[2][1] !== 32'h0201) $stop;
if (vec[2][2] !== 32'h0202) $stop;
if (pvec[1][1] !== 32'h10101) $stop;
if (pvec[1][2] !== 32'h10102) $stop;
if (pvec[2][1] !== 32'h10201) $stop;
if (pvec[2][2] !== 32'h10202) $stop;
if (r != 1.234) $stop;
$display("%s",s);
$display("%s",sarr[1]);
$display("%s",sarr[2]);
if (assoc["mapped"] != "Is mapped") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int power(int x, int y, int p) { int res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); }; long long k, x = 1; string s = codeforces ; int arr[10] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; cin >> k; while (x < k) { for (int i = 0; i < 10; i++) { long long m = 1; for (int j = 0; j < 10; j++) if (j != i) m *= arr[j]; x += m; arr[i]++; if (x >= k) { break; }; } } for (int i = 0; i < 10; i++) for (int j = 0; j < arr[i]; j++) cout << s[i]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int n; int arr1[10]; int arr2[100005]; pair<int, int> diffs[600005]; int cnts[100005]; int main() { while (scanf( %d , arr1) == 1) { for (int i = 1; i < 6; ++i) { scanf( %d , arr1 + i); } scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , arr2 + i); } int idx = 0; for (int i = 0; i < 6; ++i) { for (int j = 0; j < n; ++j) { diffs[idx].first = arr2[j] - arr1[i]; diffs[idx].second = j; ++idx; } } sort(diffs, diffs + idx); memset(cnts, 0, sizeof(cnts)); int cnt = 0; int j = 0; int ans = INF; for (int i = 0; i < 5 * n; ++i) { if (i && --cnts[diffs[i - 1].second] <= 0) { --cnt; } while (cnt < n && j < 6 * n) { if (cnts[diffs[j].second]++ == 0) { ++cnt; } ++j; } if (cnt >= n) { ans = min(ans, diffs[j - 1].first - diffs[i].first); } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, k, l[N], r[N], f[2][N], q[N]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= k; ++i) scanf( %d%d , &l[i], &r[i]); f[0][0] = 0; for (int i = 1; i <= (n << 1); ++i) f[0][i] = 0x3f3f3f3f; for (int i = 1; i <= k; ++i) { int cur = i & 1, last = !cur; memset(f[cur], 0x3f, sizeof(int) * (n + 1)); int L = 1, R = 0, now = 0; for (int j = min(n, r[i]); j >= 0; --j) { f[cur][j] = f[last][j]; int ql = l[i] - j, qr = min(r[i] - j, n); while (now <= qr) { while (L <= R && f[last][q[R]] > f[last][now]) --R; q[++R] = now; ++now; } while (L <= R && q[L] < ql) ++L; f[cur][j] = min(f[cur][j], f[last][q[L]] + 1); } L = 1, R = 0; now = 0; for (int j = 0; j <= n && j <= r[i]; ++j) { int ql = j + l[i] - r[i], qr = j; while (now <= qr) { while (L <= R && f[last][q[R]] > f[last][now]) --R; q[++R] = now; ++now; } while (L <= R && q[L] < ql) ++L; f[cur][j] = min(f[cur][j], f[last][q[L]] + 2); } } if (f[k & 1][n] == 0x3f3f3f3f) { puts( Hungry ); return 0; } puts( Full ); printf( %d n , f[k & 1][n]); return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_B.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Debounce_B
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_B
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Debounce_B
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S4>/Debouce_Count
assign Debouce_Count_out1 = 8'd25;
// <S4>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule // Debounce_B
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: spi_interface
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: This module is the main interface to the PmodGYRO, it produces
// slave select (SS), master out slave in (MOSI), and serial clock (SCLK)
// signals used in SPI communcation. Data is read on the master in slave out
// (MISO) input. SPI mode 3 is used.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module spi_interface(
send_data,
begin_transmission,
slave_select,
miso,
clk,
rst,
recieved_data,
end_transmission,
mosi,
sclk
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [7:0] send_data;
input begin_transmission;
input slave_select;
input miso;
input clk;
input rst;
output [7:0] recieved_data;
output end_transmission;
output mosi;
output sclk;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
reg [7:0] recieved_data;
reg end_transmission;
reg mosi;
parameter [11:0] SPI_CLK_COUNT_MAX = 12'hFFF;
reg [11:0] spi_clk_count;
reg sclk_buffer;
reg sclk_previous;
parameter [3:0] RX_COUNT_MAX = 4'h8;
reg [3:0] rx_count;
reg [7:0] shift_register;
parameter [1:0] RxTxTYPE_idle = 0,
RxTxTYPE_rx_tx = 1,
RxTxTYPE_hold = 2;
reg [1:0] RxTxSTATE;
// ==============================================================================
// Implementation
// ==============================================================================
//---------------------------------------------------
// FSM
//---------------------------------------------------
always @(posedge clk)
begin: tx_rx_process
begin
if (rst == 1'b1)
begin
mosi <= 1'b1;
RxTxSTATE <= RxTxTYPE_idle;
recieved_data <= {8{1'b0}};
shift_register <= {8{1'b0}};
end
else
case (RxTxSTATE)
// idle
RxTxTYPE_idle :
begin
end_transmission <= 1'b0;
if (begin_transmission == 1'b1)
begin
RxTxSTATE <= RxTxTYPE_rx_tx;
rx_count <= {4{1'b0}};
shift_register <= send_data;
end
end
// rx_tx
RxTxTYPE_rx_tx :
//send bit
if (rx_count < RX_COUNT_MAX)
begin
if (sclk_previous == 1'b1 & sclk_buffer == 1'b0)
mosi <= shift_register[7];
//recieve bit
else if (sclk_previous == 1'b0 & sclk_buffer == 1'b1)
begin
shift_register[7:1] <= shift_register[6:0];
shift_register[0] <= miso;
rx_count <= rx_count + 1'b1;
end
end
else
begin
RxTxSTATE <= RxTxTYPE_hold;
end_transmission <= 1'b1;
recieved_data <= shift_register;
end
// hold
RxTxTYPE_hold :
begin
end_transmission <= 1'b0;
if (slave_select == 1'b1)
begin
mosi <= 1'b1;
RxTxSTATE <= RxTxTYPE_idle;
end
else if (begin_transmission == 1'b1)
begin
RxTxSTATE <= RxTxTYPE_rx_tx;
rx_count <= {4{1'b0}};
shift_register <= send_data;
end
end
endcase
end
end
//---------------------------------------------------
// Serial Clock
//---------------------------------------------------
always @(posedge clk)
begin: spi_clk_generation
begin
if (rst == 1'b1)
begin
sclk_previous <= 1'b1;
sclk_buffer <= 1'b1;
spi_clk_count <= {12{1'b0}};
end
else if (RxTxSTATE == RxTxTYPE_rx_tx)
begin
if (spi_clk_count == SPI_CLK_COUNT_MAX)
begin
sclk_buffer <= (~sclk_buffer);
spi_clk_count <= {12{1'b0}};
end
else
begin
sclk_previous <= sclk_buffer;
spi_clk_count <= spi_clk_count + 1'b1;
end
end
else
sclk_previous <= 1'b1;
end
end
// Assign serial clock output
assign sclk = sclk_previous;
endmodule
|
#include <bits/stdc++.h> long long f[2005][2005]; long long k[2005][2005]; long long C[4005][4005]; int main() { int n, m; scanf( %d %d , &n, &m); for (register int i = 0; i <= n; ++i) for (register int j = 0; j <= m; ++j) { if (i == 0) k[i][j] = 1; else if (j == 0) k[i][j] = 0; else if (i > j) k[i][j] = 0; else k[i][j] = (k[i - 1][j] + k[i][j - 1]) % 998244853; } C[0][0] = C[1][0] = C[1][1] = 1; for (register int i = 2; i <= n + m; ++i) { C[i][0] = 1; for (register int j = 1; j <= i; ++j) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % 998244853; } for (register int i = 0; i <= n; ++i) f[i][0] = i, f[0][i] = 0; for (register int i = 1; i <= n; ++i) for (register int j = 1; j <= m; ++j) f[i][j] = ((f[i - 1][j] + C[i + j - 1][i - 1]) % 998244853 + (f[i][j - 1] - C[i + j - 1][i] + k[i][j - 1] + 998244853) % 998244853) % 998244853; printf( %I64d , f[n][m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; double arr[105]; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lf , &arr[i]); sort(arr, arr + n); reverse(arr, arr + n); double Max = 0; double prev = 0, a = 0, b = 1; for (int i = 0; i < n; i++) { a = (a * (1 - arr[i])) + arr[i] * b; b *= (1 - arr[i]); Max = max(Max, a); } printf( %.10lf n , Max); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct ms { string s; int id; }; bool operator<(const ms &a, const ms &b) { return a.s < b.s; } vector<ms> sv, msv[11]; string s; int n, lenmin = 11, lenmax = 0; bool used[10000] = {false}; int main(void) { int i; cin >> n; sv.reserve(n); for (i = 0; i < n; ++i) { cin >> s; if ((int)s.length() > lenmax) lenmax = s.length(); if ((int)s.length() < lenmin) lenmin = s.length(); ms sid = {s, i}; sv.push_back(sid); msv[s.length()].push_back(sid); } cin >> s; for (i = 0; i < n; ++i) sv[i].s.append(s); sort(sv.begin(), sv.end()); for (i = 1; i <= 10; ++i) { sort(msv[i].begin(), msv[i].end()); reverse(msv[i].begin(), msv[i].end()); } lenmax = lenmax + lenmin; for (i = 0; i < n; ++i) if (!used[sv[i].id]) { cout << sv[i].s; used[sv[i].id] = true; lenmin = lenmax - sv[i].s.length() + 1; while (used[msv[lenmin].back().id]) msv[lenmin].pop_back(); cout << msv[lenmin].back().s << n ; used[msv[lenmin].back().id] = true; msv[lenmin].pop_back(); } return 0; }
|
/*
* PC speaker module without any codec
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module speaker (
// Clocks
input clk,
input rst,
// Wishbone slave interface
input [7:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Timer clock
input timer2,
// Speaker pad signal
output speaker_
);
// Net declarations
wire write;
wire spk;
// Combinatorial logic
// System speaker
assign speaker_ = timer2 & wb_dat_o[1];
// Wishbone signals
assign wb_ack_o = wb_stb_i && wb_cyc_i;
assign write = wb_stb_i && wb_cyc_i && wb_we_i;
// Sequential logic
always @(posedge clk)
wb_dat_o <= rst ? 8'h0 : (write ? wb_dat_i : wb_dat_o);
endmodule
|
#include <bits/stdc++.h> const int N = 200200; using namespace std; int n, k, s, t; int c[N]; int v[N]; vector<int> g; bool f(int x) { long long cnt = s + s; for (int i = 0; i + 1 < g.size(); i++) { if (g[i + 1] - g[i] > x) return false; int l = x - (g[i + 1] - g[i]); cnt -= min(g[i + 1] - g[i], l); } return cnt <= t; } int main() { ios_base::sync_with_stdio(0); scanf( %d%d%d%d , &n, &k, &s, &t); for (int i = 1; i <= n; i++) scanf( %d%d , &c[i], &v[i]); g.push_back(0); g.push_back(s); for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); g.push_back(x); } sort(g.begin(), g.end()); int l = 0, r = 1e9 + 1; while (l < r) { int m = (l + r) / 2; if (f(m)) r = m; else l = m + 1; } int ans = 1e9 + 1; for (int i = 1; i <= n; i++) if (v[i] >= l) ans = min(ans, c[i]); if (ans == 1e9 + 1) ans = -1; printf( %d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_4_V
`define SKY130_FD_SC_LP__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_4_V
|
#include <bits/stdc++.h> using namespace std; int l[10100]; int r[10100]; int per[100100]; int pr(int x) { if (x == per[x]) return x; return per[x] = pr(per[x]); } int main() { ios::sync_with_stdio(0); int n; cin >> n; int t = 0; for (int i = 1; i <= n; i++) { per[i] = i; cin >> l[i]; cin >> r[i]; t += l[i] == 0; } for (int i = 1; i <= n; i++) { if (l[i]) { r[l[i]] = i; per[pr(i)] = pr(l[i]); } if (r[i]) { l[r[i]] = i; per[pr(i)] = pr(r[i]); } } for (int i = 1; i <= n; i++) { if (l[i] == 0) { if (t == 1) continue; for (int j = 1; j <= n; j++) { if (i == j) continue; if (pr(i) == pr(j)) continue; if (r[j] == 0) { r[j] = i; l[i] = j; per[pr(i)] = pr(j); break; } } t--; } } for (int i = 1; i <= n; i++) { cout << l[i] << << r[i] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int mod = 1e9 + 7; const long long inf = 1e18; int d, n, m, x[N], p[N], cur, r[N]; long long ans = inf, carry; pair<int, int> a[N]; int main() { ios_base::sync_with_stdio(0); cin >> d >> n >> m; for (int i = 1; i <= m; i++) cin >> a[i].first >> a[i].second; vector<int> st; sort(a + 1, a + m + 1); for (int i = 1; i <= m; i++) x[i] = a[i].first, p[i] = a[i].second; for (int i = m; i >= 0; i--) { r[i] = i; while (st.size() && p[st.back()] >= p[i]) { r[i] = r[st.back()]; st.pop_back(); } st.push_back(i); } for (int i = 0, j = 0; i <= m; i++) { if (cur < 0) { ans = inf; break; } while (j + 1 <= m && x[j + 1] - x[i] <= n) j++; if (n >= d - x[i]) { long long dist = d - x[i]; long long cost = carry; if (dist > cur) cost += 1ll * (dist - cur) * p[i]; ans = min(ans, cost); } if (j < r[i] + 1) { carry += 1ll * (n - cur) * p[i]; cur = n; } else { long long dist = x[r[i] + 1] - x[i]; if (dist > n) dist = n; if (dist > cur) { carry += 1ll * (dist - cur) * p[i]; cur = dist; } } cur -= (x[i + 1] - x[i]); } if (ans == inf) ans = -1; cout << ans; return 0; }
|
(** * Extraction: Extracting OCaml from Coq *)
(* ################################################################# *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (mostly works), and Scheme (a bit
out of date). *)
Require Coq.extraction.Extraction.
Extraction Language OCaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
From Coq Require Import Arith.Arith.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.EqNat.
From LF Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ################################################################# *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant eqb => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ################################################################# *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we first need
to set up the right correspondence between Coq strings and lists
of OCaml characters. *)
Require Import ExtrOcamlBasic.
Require Import ExtrOcamlString.
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
From LF Require Import Imp.
From LF Require Import ImpParser.
From LF Require Import Maps.
Extraction "imp.ml" empty_st ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ################################################################# *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(* ################################################################# *)
(** * Going Further *)
(** Further details about extraction can be found in the Extract
chapter in _Verified Functional Algorithms_ (_Software
Foundations_ volume 3). *)
(* 2021-08-11 15:08 *)
|
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: counter_f.v
//
// Description: Implements a parameterizable N-bit counter_f
// Up/Down Counter
// Count Enable
// Parallel Load
// Synchronous Reset
// The structural implementation has incremental cost
// of one LUT per bit.
// Precedence of operations when simultaneous:
// reset, load, count
//
// A default inferred-RTL implementation is provided and
// is used if the user explicitly specifies C_FAMILY=nofamily
// or ommits C_FAMILY (allowing it to default to nofamily).
// The default implementation is also used
// if needed primitives are not available in FPGAs of the
// type given by C_FAMILY.
//
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of axi_lite_ipif.
//
// --axi_lite_ipif.v
// --slave_attachment.v
// --address_decoder.v
// --pselect_f.v
// --counter_f.v
//-----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>
//-----------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Entity section
//---------------------------------------------------------------------------
module counter_f (Clk, Rst, Load_In, Count_Enable, Count_Load, Count_Down,
Count_Out, Carry_Out);
parameter C_NUM_BITS = 9;
parameter C_FAMILY = "nofamily";
input Clk;
input Rst;
input[C_NUM_BITS - 1:0] Load_In;
input Count_Enable;
input Count_Load;
input Count_Down;
output[C_NUM_BITS - 1:0] Count_Out;
wire[C_NUM_BITS - 1:0] Count_Out;
output Carry_Out;
wire Carry_Out;
reg[C_NUM_BITS:0] icount_out;
wire[C_NUM_BITS:0] icount_out_x;
wire[C_NUM_BITS:0] load_in_x;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-------------------------------------------------------------------
// Generate Inferred code
//-------------------------------------------------------------------
assign load_in_x = {1'b0, Load_In};
// Mask out carry position to retain legacy self-clear on next enable.
// icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
assign icount_out_x = {1'b0, icount_out[C_NUM_BITS - 1:0]};
//---------------------------------------------------------------
// Process to generate counter with - synchronous reset, load,
// counter enable, count down / up features.
//---------------------------------------------------------------
always @(posedge Clk)
begin : CNTR_PROC
if (Rst == 1'b1)
begin
icount_out <= {C_NUM_BITS-(0)+1{1'b0}} ;
end
else if (Count_Load == 1'b1)
begin
icount_out <= load_in_x ;
end
else if (Count_Down == 1'b1 & Count_Enable == 1'b1)
begin
icount_out <= icount_out_x - 1 ;
end
else if (Count_Enable == 1'b1)
begin
icount_out <= icount_out_x + 1 ;
end
end
assign Carry_Out = icount_out[C_NUM_BITS] ;
assign Count_Out = icount_out[C_NUM_BITS - 1:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 3; int n, m, i, j, k, l, r, s, t, d, u, ii, jj, x, y, z, lz[4 * N], h[N]; char c[100]; pair<pair<int, int>, pair<int, int> > first[4 * N]; void init(int root, int bas, int son) { if (bas == son) { if (h[bas] == 4) first[root].first.first = 1; else first[root].first.second = 1; first[root].second.first = first[root].second.second = 1; return; } init((root + root), bas, (bas + son >> 1)); init(((root + root) + 1), (bas + son >> 1) + 1, son); first[root].first.first = first[(root + root)].first.first + first[((root + root) + 1)].first.first; first[root].first.second = first[(root + root)].first.second + first[((root + root) + 1)].first.second; first[root].second.first = max(first[(root + root)].second.first + first[((root + root) + 1)].first.second, first[(root + root)].first.first + first[((root + root) + 1)].second.first); first[root].second.second = max(first[(root + root)].second.second + first[((root + root) + 1)].first.first, first[(root + root)].first.second + first[((root + root) + 1)].second.second); } void push(int root, int bas, int son) { if (lz[root] and bas != son) { lz[((root + root) + 1)] = 1 - lz[((root + root) + 1)]; lz[(root + root)] = 1 - lz[(root + root)]; swap(first[(root + root)].first.first, first[(root + root)].first.second); swap(first[((root + root) + 1)].first.first, first[((root + root) + 1)].first.second); swap(first[((root + root) + 1)].second.first, first[((root + root) + 1)].second.second); swap(first[(root + root)].second.first, first[(root + root)].second.second); } lz[root] = 0; } void g(int root, int bas, int son) { push(root, bas, son); if (x > son or y < bas) return; if (x <= bas and y >= son) { swap(first[root].first.first, first[root].first.second); swap(first[root].second.first, first[root].second.second); lz[root] = 1; return; } g((root + root), bas, (bas + son >> 1)); g(((root + root) + 1), (bas + son >> 1) + 1, son); first[root].first.first = first[(root + root)].first.first + first[((root + root) + 1)].first.first; first[root].first.second = first[(root + root)].first.second + first[((root + root) + 1)].first.second; first[root].second.first = max(first[(root + root)].second.first + first[((root + root) + 1)].first.second, first[(root + root)].first.first + first[((root + root) + 1)].second.first); first[root].second.second = max(first[(root + root)].second.second + first[((root + root) + 1)].first.first, first[(root + root)].first.second + first[((root + root) + 1)].second.second); } int main() { cin >> n >> m; for (i = 1; i <= n; i++) { scanf( %c , &c[0]); if (c[0] == 4 ) h[i] = 4; } init(1, 1, n); while (m--) { scanf( %s , c); if (c[0] == c ) printf( %d n , first[1].second.first); else { scanf( %d%d , &x, &y); g(1, 1, n); } } }
|
#include <bits/stdc++.h> using namespace std; namespace solve { long long int a[200007], sum[200007], dpDown[200007], dpUp[200007]; vector<int> graph[200007]; void rec(int u, int p) { sum[u] = a[u]; for (int v : graph[u]) { if (v == p) continue; rec(v, u); dpDown[u] += dpDown[v] + sum[v]; sum[u] += sum[v]; } } void dfs(int u, int p) { for (int v : graph[u]) { if (v == p) continue; dpUp[v] = dpDown[u] - dpDown[v] - sum[v] + (sum[1] - sum[v]) + dpUp[u]; dfs(v, u); } } void takeInput() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } rec(1, -1); dfs(1, -1); long long int res = 0; for (int i = 1; i <= n; i++) { res = max(res, dpDown[i] + dpUp[i]); } cout << res << endl; } } // namespace solve int main() { solve::takeInput(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int ans = 1e9; int f[1000010]; int main() { int n, i, j; scanf( %d , &n); for (i = 2; i <= n; i++) { if (!f[i]) { for (j = 2 * i; j <= n; j += i) { f[j] = i; } } f[i] = i - f[i] + 1; } for (i = f[n]; i <= n; i++) { if (f[i] < ans) ans = f[i]; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m; char s[4][12]; char t[12][25][12]; int num[12]; int main() { int i, j; int ans = 0, p = 0; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %s , s[i]); scanf( %d , &m); for (i = 0; i < m; i++) { scanf( %d , &num[i]); for (j = 0; j < num[i]; j++) scanf( %s , t[i][j]); } int mark[4]; int rec[25]; for (int k = 0; k < m; k++) { memset(mark, 0, sizeof(mark)); memset(rec, -1, sizeof(rec)); for (i = 0; i < 4; i++) { for (j = 0; j < num[k]; j++) { if (strcmp(s[i], t[k][j]) == 0) { mark[i] = 1; rec[j] = i; } } } int sum = 0; for (i = 0; i < n; i++) sum += mark[i]; if (sum < n) continue; int id[4] = {0, 1, 2, 3}; do { j = 0; for (i = 0; i < num[k]; i++) { if (rec[i] == id[j]) { j++; if (j == n) break; } } int x = 0; for (i = 0; i < n - 1; i++) for (int tt = i + 1; tt < n; tt++) if (id[i] > id[tt]) x++; if (j == n && n * (n - 1) / 2 - x + 1 > p) { ans = k + 1; p = n * (n - 1) / 2 - x + 1; } } while (next_permutation(id, id + n)); } if (ans == 0) printf( Brand new problem! n ); else { printf( %d n , ans); printf( [: ); for (i = 0; i < p; i++) printf( | ); printf( :] n ); } return 0; }
|
module EX_MEM(input clk,
input reset,
input [1:0] WB_in,
input [1:0] M_in,
input [31:0] ALU_in,
input [4:0] instruction_mux_in,
input [31:0] RDdata2_in,
input hold_i,
output reg MemWrite,
output reg MemRead,
output reg[1:0] WB_out,
output reg[31:0] ALU_out,
output reg[4:0] instruction_mux_out,
output reg[31:0] RDdata2_out);
always@(posedge reset)begin
MemWrite = 0;
MemRead = 0;
WB_out = 0;
ALU_out = 0;
RDdata2_out = 0;
instruction_mux_out = 0;
end
always@(posedge clk)begin
if(hold_i)begin
WB_out <= WB_out;
MemWrite <= MemWrite;
MemRead <= MemRead;
ALU_out <= ALU_out;
RDdata2_out <= RDdata2_out;
instruction_mux_out <= instruction_mux_out;
end
else begin
WB_out <= WB_in;
MemWrite <= M_in[1];
MemRead <= M_in[0];
ALU_out <= ALU_in;
RDdata2_out <= RDdata2_in;
instruction_mux_out <= instruction_mux_in;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.8 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005], f[100005]; int main() { int n, i; long long k; map<int, int> cnt; scanf( %d , &n); cin >> k; k--; for (i = 0; i < n; ++i) scanf( %d , &a[i]), cnt[a[i]]++; sort(a, a + n); f[0] = 0; for (i = 1; i < n; ++i) f[i] = a[i] == a[i - 1] ? f[i - 1] : i; printf( %d , i = a[k / n]); k -= 1LL * n * f[k / n]; printf( %d n , a[k / cnt[i]]); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, q = 0, s = 0, t = 0; cin >> n; for (int k = 1; k <= n; k++) { cin >> q; if (q == 1) { if (t == 1) s++; else { t++; s++; } } else { if (t == 1) { t--; s++; } } } if (t == 0 && s != 0) s--; cout << s; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_SYMBOL_V
`define SKY130_FD_SC_MS__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMD32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM32X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DPO,
output SPO,
input A0,
input A1,
input A2,
input A3,
input A4,
input D,
input DPRA0,
input DPRA1,
input DPRA2,
input DPRA3,
input DPRA4,
input WCLK,
input WE
);
reg [32:0] mem;
wire [4:0] A_dly, A_in;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in, WE_in, D_in;
wire wclk_is_inverted;
reg notifier;
assign SPO = mem[A_in];
assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge(WCLK_in))
if (WE_in == 1'b1)
mem[A_in] <= #100 D_in;
always @(notifier)
mem[A_in] = 1'bx;
`ifndef XIL_TIMING
assign A_dly = {A4, A3, A2, A1, A0};
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign wclk_is_inverted = IS_WCLK_INVERTED;
assign WCLK_in = wclk_is_inverted ^ WCLK_dly;
assign WE_in = WE_dly;
assign A_in = A_dly;
assign D_in = D_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A0 => SPO) = (0:0:0, 0:0:0);
(A1 => SPO) = (0:0:0, 0:0:0);
(A2 => SPO) = (0:0:0, 0:0:0);
(A3 => SPO) = (0:0:0, 0:0:0);
(A4 => SPO) = (0:0:0, 0:0:0);
(DPRA0 => DPO) = (0:0:0, 0:0:0);
(DPRA1 => DPO) = (0:0:0, 0:0:0);
(DPRA2 => DPO) = (0:0:0, 0:0:0);
(DPRA3 => DPO) = (0:0:0, 0:0:0);
(DPRA4 => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
//`include "prog_counter2.v"
`include "program_counter2.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter2();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter2 pc2 (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/program_counter2.sdf",pc2,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#20
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mm = 1e6 + 1; const int mx = 1 << 20; const int N = 3e5 + 10; int a[N], b[N]; int seg_t[mx * 2 + 10], tag[mx * 2 + 10]; void up(int o) { seg_t[o] = max(seg_t[o << 1], seg_t[o << 1 | 1]); } void down(int o) { if (tag[o] == 0) { return; } seg_t[o << 1] += tag[o]; tag[o << 1] += tag[o]; seg_t[o << 1 | 1] += tag[o]; tag[o << 1 | 1] += tag[o]; tag[o] = 0; } void update(int o, int l, int r, int ql, int qr, int v) { if (ql <= l && r <= qr) { seg_t[o] += v; tag[o] += v; return; } down(o); int mid = (l + r) / 2; if (mid >= ql) update(o << 1, l, mid, ql, qr, v); if (mid < qr) update(o << 1 | 1, mid + 1, r, ql, qr, v); up(o); } int query(int o, int l, int r) { if (seg_t[o] <= 0) return -1; if (l == r) return l; down(o); int mid = (l + r) / 2; if (seg_t[o << 1 | 1] > 0) { return query(o << 1 | 1, mid + 1, r); } return query(o << 1, l, mid); } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; update(1, 1, mm, 1, a[i], 1); } for (int i = 0; i < m; i++) { cin >> b[i]; update(1, 1, mm, 1, b[i], -1); } int q; cin >> q; while (q--) { int opt, x, y; cin >> opt >> x >> y; --x; if (opt == 1 && a[x] != y) { update(1, 1, mm, 1, a[x], -1); a[x] = y; update(1, 1, mm, 1, a[x], 1); } else if (opt == 2 && b[x] != y) { update(1, 1, mm, 1, b[x], 1); b[x] = y; update(1, 1, mm, 1, b[x], -1); } cout << query(1, 1, mm) << n ; } return 0; }
|
#include <bits/stdc++.h> const int MAX_N = 1e5 + 1; const long long int MOD = 1e9 + 7; const long long int INF = 1e9; using namespace std; void solve() { int n, max = 0, idx; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; if (v[i] > max) { max = v[i]; idx = i + 1; } } sort(v.begin(), v.end()); cout << idx << << v[v.size() - 2] << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); }
|
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4009 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd1}; //linea de primer retardo
4: oInstruction = { `STO, `R5,16'd0 };
//LOOP2: **** Doble lazo de retardo *****
5: oInstruction = { `LED ,8'b0,`R7,8'b0 }; // imprime en los LEDs
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd1 }; //segundo retardo
//LOOP1: **** Primer lazo de retardo *****
8: oInstruction = { `ADD ,`R1,`R1,`R3 }; // R1++
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 }; // Salta a la direccion 8 y especifica el tiempo
10: oInstruction = { `ADD ,`R5,`R5,`R3 }; // R5++
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `SUB ,`R7,`R7,`R3 }; //R7++
14: oInstruction = { `JMP , 8'd2,16'b0 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, n; void solve() { int n; long long l; cin >> n >> l; long long a[n]; for (i = 0; i < n; i++) cin >> a[i]; ; sort(a, a + n); long long m = 2 * max(a[0], l - a[n - 1]); for (i = 0; i < n - 1; i++) { m = max(m, a[i + 1] - a[i]); } long double d = 1.0 * m / 2; cout << setprecision(9) << d; } int main() { solve(); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:34 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: aurora_lane_gtp.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// AURORA_LANE
//
//
// Description: The AURORA_LANE module provides a full duplex 2-byte aurora
// lane connection using a single GTP. The module handles lane
// initialization, symbol generation and decoding as well as
// error detection. It also decodes some of the channel bonding
// indicator signals needed by the Global logic.
//
// * Supports GTP
//
`timescale 1 ns / 10 ps
module aurora_201_AURORA_LANE
(
// GTP Interface
RX_DATA,
RX_NOT_IN_TABLE,
RX_DISP_ERR,
RX_CHAR_IS_K,
RX_CHAR_IS_COMMA,
RX_STATUS,
RX_BUF_ERR,
TX_BUF_ERR,
RX_REALIGN,
RX_POLARITY,
RX_RESET,
TX_CHAR_IS_K,
TX_DATA,
TX_RESET,
// Comma Detect Phase Align Interface
ENA_COMMA_ALIGN,
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// RX_LL Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
//System Interface
USER_CLK,
RESET
);
//***********************************Port Declarations*******************************
// GTP Interface
input [15:0] RX_DATA; // 2-byte data bus from the GTP.
input [1:0] RX_NOT_IN_TABLE; // Invalid 10-bit code was recieved.
input [1:0] RX_DISP_ERR; // Disparity error detected on RX interface.
input [1:0] RX_CHAR_IS_K; // Indicates which bytes of RX_DATA are control.
input [1:0] RX_CHAR_IS_COMMA; // Comma received on given byte.
input [5:0] RX_STATUS; // Part of GTP status and error bus.
input RX_BUF_ERR; // Overflow/Underflow of RX buffer detected.
input TX_BUF_ERR; // Overflow/Underflow of TX buffer detected.
input RX_REALIGN; // SERDES was realigned because of a new comma.
output RX_POLARITY; // Controls interpreted polarity of serial data inputs.
output RX_RESET; // Reset RX side of GTP logic.
output [1:0] TX_CHAR_IS_K; // TX_DATA byte is a control character.
output [15:0] TX_DATA; // 2-byte data bus to the GTP.
output TX_RESET; // Reset TX side of GTP logic.
// Comma Detect Phase Align Interface
output ENA_COMMA_ALIGN; // Request comma alignment.
// TX_LL Interface
input GEN_SCP; // SCP generation request from TX_LL.
input GEN_ECP; // ECP generation request from TX_LL.
input GEN_PAD; // PAD generation request from TX_LL.
input [0:15] TX_PE_DATA; // Data from TX_LL to send over lane.
input TX_PE_DATA_V; // Indicates TX_PE_DATA is Valid.
input GEN_CC; // CC generation request from TX_LL.
// RX_LL Interface
output RX_PAD; // Indicates lane received PAD.
output [0:15] RX_PE_DATA; // RX data from lane to RX_LL.
output RX_PE_DATA_V; // RX_PE_DATA is data, not control symbol.
output RX_SCP; // Indicates lane received SCP.
output RX_ECP; // Indicates lane received ECP.
// Global Logic Interface
input GEN_A; // 'A character' generation request from Global Logic.
input [0:1] GEN_K; // 'K character' generation request from Global Logic.
input [0:1] GEN_R; // 'R character' generation request from Global Logic.
input [0:1] GEN_V; // Verification data generation request.
output LANE_UP; // Lane is ready for bonding and verification.
output SOFT_ERROR; // Soft error detected.
output HARD_ERROR; // Hard error detected.
output CHANNEL_BOND_LOAD; // Channel Bonding done code recieved.
output [0:1] GOT_A; // Indicates lane recieved 'A character' bytes.
output GOT_V; // Verification symbols received.
// System Interface
input USER_CLK; // System clock for all non-GTP Aurora Logic.
input RESET; // Reset the lane.
//*********************************Wire Declarations**********************************
wire gen_k_i;
wire [0:1] gen_sp_data_i;
wire [0:1] gen_spa_data_i;
wire rx_sp_i;
wire rx_spa_i;
wire rx_neg_i;
wire enable_error_detect_i;
wire do_word_align_i;
wire hard_error_reset_i;
//*********************************Main Body of Code**********************************
// Lane Initialization state machine
aurora_201_LANE_INIT_SM lane_init_sm_i
(
// GTP Interface
.RX_NOT_IN_TABLE(RX_NOT_IN_TABLE),
.RX_DISP_ERR(RX_DISP_ERR),
.RX_CHAR_IS_COMMA(RX_CHAR_IS_COMMA),
.RX_REALIGN(RX_REALIGN),
.RX_RESET(RX_RESET),
.TX_RESET(TX_RESET),
.RX_POLARITY(RX_POLARITY),
// Comma Detect Phase Alignment Interface
.ENA_COMMA_ALIGN(ENA_COMMA_ALIGN),
// Symbol Generator Interface
.GEN_K(gen_k_i),
.GEN_SP_DATA(gen_sp_data_i),
.GEN_SPA_DATA(gen_spa_data_i),
// Symbol Decoder Interface
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
.DO_WORD_ALIGN(do_word_align_i),
// Error Detection Logic Interface
.HARD_ERROR_RESET(hard_error_reset_i),
.ENABLE_ERROR_DETECT(enable_error_detect_i),
// Global Logic Interface
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Channel Bonding Count Decode module
aurora_201_CHBOND_COUNT_DEC chbond_count_dec_i
(
.RX_STATUS(RX_STATUS),
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.USER_CLK(USER_CLK)
);
// Symbol Generation module
aurora_201_SYM_GEN sym_gen_i
(
// TX_LL Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_CC(GEN_CC),
// Global Logic Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// Lane Init SM Interface
.GEN_K_FSM(gen_k_i),
.GEN_SP_DATA(gen_sp_data_i),
.GEN_SPA_DATA(gen_spa_data_i),
// GTP Interface
.TX_CHAR_IS_K({TX_CHAR_IS_K[0],TX_CHAR_IS_K[1]}),
.TX_DATA({TX_DATA[7:0],TX_DATA[15:8]}),
// System Interface
.USER_CLK(USER_CLK)
);
// Symbol Decode module
aurora_201_SYM_DEC sym_dec_i
(
// RX_LL Interface
.RX_PAD(RX_PAD),
.RX_PE_DATA(RX_PE_DATA),
.RX_PE_DATA_V(RX_PE_DATA_V),
.RX_SCP(RX_SCP),
.RX_ECP(RX_ECP),
// Lane Init SM Interface
.DO_WORD_ALIGN(do_word_align_i),
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
// Global Logic Interface
.GOT_A(GOT_A),
.GOT_V(GOT_V),
// GTP Interface
.RX_DATA({RX_DATA[7:0],RX_DATA[15:8]}),
.RX_CHAR_IS_K({RX_CHAR_IS_K[0],RX_CHAR_IS_K[1]}),
.RX_CHAR_IS_COMMA({RX_CHAR_IS_COMMA[0],RX_CHAR_IS_COMMA[1]}),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Error Detection module
aurora_201_ERROR_DETECT error_detect_i
(
// Lane Init SM Interface
.ENABLE_ERROR_DETECT(enable_error_detect_i),
.HARD_ERROR_RESET(hard_error_reset_i),
// Global Logic Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
// GTP Interface
.RX_BUF_ERR(RX_BUF_ERR),
.RX_DISP_ERR({RX_DISP_ERR[0],RX_DISP_ERR[1]}),
.RX_NOT_IN_TABLE({RX_NOT_IN_TABLE[0],RX_NOT_IN_TABLE[1]}),
.TX_BUF_ERR(TX_BUF_ERR),
.RX_REALIGN(RX_REALIGN),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int x{}; cin >> x; if (x % 3 == 0 || x % 7 == 0) { cout << YES << endl; return; } int ms{x / 3}; int ml{x / 7}; for (int i{0}; i <= ms; ++i) { for (int j{0}; j <= ml; ++j) { int chunks{3 * i + 7 * j}; if (chunks == x) { cout << YES << endl; return; } } } cout << NO << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int t{}; cin >> t; while (t > 0) { solve(); t--; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mxN = 52; vector<long long> adj[mxN]; signed main() { long long n; cin >> n; long long x = (n * (n - 1)) / 2; long long a[x - 1][2]; for (long long i = 0; i < x - 1; i++) { cin >> a[i][0] >> a[i][1]; adj[a[i][0]].push_back(a[i][1]); adj[a[i][1]].push_back(a[i][0]); } long long ans1 = -1, ans2 = -1; for (long long i = 1; i <= n; i++) { if (ans1 == -1 && adj[i].size() < n - 1) { ans1 = i; } else if (ans2 == -1 && adj[i].size() < n - 1) { ans2 = i; } } for (long long i = 1; i <= n; i++) { if (i == ans1 || i == ans2) { continue; } else { long long w1 = -1, w2 = -1; for (long long j = 0; j < x - 1; j++) { if (a[j][0] == ans1 && a[j][1] == i) { w1 = ans1; } else if (a[j][0] == i && a[j][1] == ans1) { w1 = i; } else if (a[j][0] == ans2 && a[j][1] == i) { w2 = ans2; } else if (a[j][0] == i && a[j][1] == ans2) { w2 = i; } } if (w1 == ans1 && w2 != ans2) { cout << ans1 << << ans2 << endl; return 0; } else if (w2 == ans2 && w1 != ans1) { cout << ans2 << << ans1 << endl; return 0; } } } cout << ans1 << << ans2 << endl; }
|
(** * Episode 03: Lists *)
(** This command asks Coq to infer ``easy'' type arguments. *)
Set Implicit Arguments.
(** As a result of running [Set Implicit Arguments], sometimes we will apply functions or constructors to fewer arguments than they are defined to take. When you see that, it simply indicates that Coq was able to automatically infer the missing arguments. *)
(* Question: What are some of the tradeoffs of inference? *)
(** A parameterized, recursive type: *)
Inductive llist (T: Type) :=
| lnil : llist T
| lcons : T -> llist T -> llist T.
(** Above we define [list] to be a type parameterized by some other type [T]. Furthermore, we say that there are _exactly_ two ways to build a [llist]: (1) using the [lnil] constructor or (2) using the [lcons] constructor. When the [lnil] constructor is applied to a _type_ [T], it yields a value of type [llist T]:
*)
Check lnil.
(**
<<
lnil
: forall T : Type, llist T
>>
We'll talk a lot more about [forall] throughout the course, but in this case you can think of it as just a fancy [->]. When the [lcons] constructor is applied to a _type_ [T], a _value of type_ [T], and a value of type [llist T], it yields a value of type [llist T]:
*)
Check lcons.
(**
<<
lcons
: forall T : Type, T -> llist T -> llist T
>>
*)
(** Coq will infer the type argument [T] for [lcons], but it will not try to infer the type argument [T] for [lnil], even if it is obvious from context. *)
Print llist.
(** So this will break, even though context forces [T] to be [nat]:
<<
Check (lcons 1 (lcons 2 (lcons 3 lnil))).
>>
But this works:
*)
Check (lcons 1 (lcons 2 (lcons 3 (lnil nat)))).
(** However, we can tell Coq to always try to infer the type argument [T] of [lnil] from context: *)
Arguments lnil [T].
Print llist.
Check (lcons 1 (lcons 2 (lcons 3 lnil))).
(* won't work
Check (lcons 1 (lnil bool)).
*)
(* also won't work
Check (lcons 1 (@lnil bool)).
*)
(** The list type Coq provides is isomorphic to our [llist]. *)
Print list.
(** Get nifty notations for cons, append, etc. *)
Require Import List.
(** We'll use [countdown] to help test our list functions. *)
Fixpoint countdown (n: nat) :=
match n with
| O => nil
| S m => n :: countdown m
end.
Eval cbv in (countdown 5).
(** For polymorphic functions like [length], we must explicitly add a type argument.
If we try to define length without the type argument, like so:
<<
Fixpoint length l :=
match l with
| nil => 0
| x::xs => S (length xs)
end.
>>
we will get an error like:
<<
Error: Cannot infer an internal placeholder of type "Type".
>>
To avoid this problem, just add the type argument and the type for [l]. Coq can infer the rest:
*)
Fixpoint length (A: Type) (l: list A) :=
match l with
| nil => 0
| x::xs => S (length xs)
end.
Eval cbv in (length (1 :: 2 :: 3 :: nil)).
Eval cbv in (length (countdown 5)).
Eval cbv in (length (countdown 3)).
Eval cbv in (length (countdown 1)).
(** In lecture, we noticed a simple relationship between [length] and [countdown]: *)
Lemma length_countdown:
forall n, length (countdown n) = n.
Proof.
(** Consider arbitrary [n]. *)
intro.
(** We can prove property for arbitrary (S n) if we know property is true for n, so use [induction]. *)
induction n.
(** Base case: [n = O] *)
(** Need to prove [length (countdown O) = O], which reflexivity solves by crunching down [countdown 0] to [nil], then [length nil] to [O], which leaves the goal [O = O]. *)
{ reflexivity. }
(** Inductive case: [n = S m] *)
(** Need to prove [length (countdown (S m)) = S m]. First we can cruch [countdown (S m)] down to [S m :: countdown m]. Now we crunch [length (S m :: countdown m)] down to [S (length (countdown m))]. This leaves us with the goal:
<<
S (length (countdown m)) = S m
>>
Now if only we happened to know that [length (countdown m) = m] ... BUT WAIT! That's *exactly* what our induction hypothesis give us! After crunching with simpl, the [firstorder] tactic is smart enought to figure all this out and use the induction hypothesis to finish the proof. *)
{ simpl. firstorder. }
Qed.
(** Append one list to the end of another. *)
Fixpoint append (A: Type) (l1 l2: list A) :=
match l1 with
| nil => l2
| x::xs => x :: append xs l2
end.
Eval cbv in (append (countdown 5) (countdown 2)).
(** Show that length of two lists appended is just the sum of their lengths. *)
Lemma length_append:
forall A (l1 l2: list A),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(** Consider arbitrary lists [l1] and [l2]. *)
intros.
(** We can prove for arbitrary [l1 = x :: xs] if we just know property is true for [xs], so use induction. *)
induction l1.
(** Base case: [l1 = nil]. *)
(** Need to prove [length (append nil l2) = length nil + length l2], which reflexivity solves by crunching down to [length (l2) = O + length l2] and then to [length l2 = length l2]. *)
{ reflexivity. }
(** Inductive case: [l1 = x :: xs] *)
(** Need to prove [length (append (x :: xs) l2) = length (x :: xs) + length l2]. First we can cruch [length (append (x :: xs) l2)] down to [length (x :: append xs l2)] and again to [S (length (append xs l2))]. We can also crunch [length (x :: xs) + length l2] down to [(S (length xs)) + length l2] which crunches down again to [S (length xs + length l2)]. This leaves us with the goal:
<<
S (length (append xs l2)) = S (length xs + length l2)
>>
Now if only we happened to know that [length (append xs l2) = length xs + length l2] ... BUT WAIT! That's *exactly* what our induction hypothesis give us! After a little crunching from [simpl], the [firstorder] tactic is smart enought to figure all this out and use the induction hypothesis to finish the proof. *)
{ simpl. firstorder. }
Qed.
(** Reverse the elements of a list. *)
Fixpoint rev A (l: list A) :=
match l with
| nil => nil
| x::xs =>
(** Note: [++] is just an infix operator for [append], so: *)
rev xs ++ x :: nil
(** is the same as:
<<
append (rev xs) (x :: nil)
>> *)
end.
Eval cbv in (rev (countdown 5)).
(** Note that the above version of [rev] is not efficient. We can do better using a helper function to collect the reversed version of the list as we recurse: *)
Fixpoint rev'_aux A (acc l: list A) :=
match l with
| nil => acc
| x :: xs => rev'_aux (x :: acc) xs
end.
Definition rev' A (l: list A) :=
rev'_aux nil l.
(** While [rev'] is more efficient than [rev], it is a bit trickier to reason about. *)
(** To prove [rev] and [rev'] are equivalent, we'll need a fact about [append]: *)
Lemma append_associative:
forall A (l1 l2 l3: list A),
l1 ++ l2 ++ l3 = (l1 ++ l2) ++ l3.
Proof.
(** It turns out that firstorder already know this one. *)
firstorder.
Qed.
(** Now we need to prove a carefully chosen lemma about rev'_aux. *)
Lemma rev_rev'_aux:
forall A (l acc: list A),
rev'_aux acc l = rev l ++ acc.
Proof.
intro. intro. induction l.
{ reflexivity. }
{ intro. simpl. rewrite -> IHl. rewrite <- append_associative. reflexivity. }
Qed.
(** Now we should be able to prove equivalence. *)
Lemma rev_rev':
forall A (l: list A), rev l = rev' l.
Proof.
(** Note: we have to unfold [rev] first! This allows us to use [rev_rev'_aux]. *)
unfold rev'. intros. rewrite -> rev_rev'_aux. firstorder.
Qed.
(** Question: Why did we need to prove [rev_rev'_aux] separately from [rev_rev']? *)
(** To prove that [rev] preserved length, we'll need to know a little more about arithmetic. *)
Lemma length_rev:
forall A (l: list A), length (rev l) = length l.
(** We get stuck trying to prove:
<<
length l + 1 = S (length l)
>> *)
Abort.
(** Question: Why do we get stuck? *)
Print plus.
(** Coq has a decision procedure for Pressburger arithmetic. It will make short work of our problem. *)
Require Import Omega.
Lemma length_rev:
forall A (l: list A), length (rev l) = length l.
Proof.
intros. induction l.
{ reflexivity. }
{ simpl. rewrite -> length_append. simpl. firstorder. }
Qed.
(** [upto] is another useful function for testing. *)
Definition upto n :=
rev (countdown n).
(** We can prove that [rev (rev l) = l], but we'll need a lemma about [rev] and [append]: *)
Lemma rev_append:
forall A (l1 l2: list A), rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
intro. intro. induction l1.
{ simpl. firstorder. }
{ intro. simpl. rewrite -> IHl1. firstorder. }
Qed.
(** Now for the lemma we really want: *)
Lemma rev_involutive:
forall A (l: list A), rev (rev l) = l.
Proof.
intros. induction l.
{ reflexivity. }
{ simpl. rewrite -> rev_append. simpl. rewrite -> IHl. reflexivity. }
Qed.
(** The famous [map] function provides our first useful example of "higher order functions", which is just a fancy way of saying that [map] is a function which takes another function as an argument (in this case, the argument is named [f]). *)
Fixpoint map A B (f: A -> B) (l: list A) :=
match l with
(** Question: Are these the same nil? *)
| nil => nil
| x::xs => f x :: map f xs
end.
Eval cbv in (map (fun x => S x) (upto 5)).
Lemma length_map:
forall A B (f: A -> B) (l: list A), length (map f l) = length l.
Proof.
intros. induction l.
{ reflexivity. }
{ simpl. rewrite -> IHl. reflexivity. }
Qed.
(** The also famous [fold] function. *)
Fixpoint fold A B (f: A -> B -> B) (l: list A) (b: B) :=
match l with
| nil => b
| x::xs => f x (fold f xs b)
end.
(* fold f l b takes a list of
x1 :: x2 :: x3 :: ... :: xN :: nil
cons x1 (cons x2 ( ... (cons xN nil) ...)))
and computes
f x1 (f x2 (f x3 (... (f xN b) ...)))
*)
(* in class *)
Definition map' A B (f: A -> B) (l: list A) :=
fold (fun x fxs => f x :: fxs) l nil.
Lemma map_map':
forall A B (f: A -> B) (l: list A), map f l = map' f l.
Abort.
Lemma map'_unroll:
forall A B (f: A -> B) (x: A) (xs: list A),
map' f (x :: xs) = f x :: map' f xs.
Proof.
reflexivity.
Qed.
Lemma map_map':
forall A B (f: A -> B) (l: list A), map f l = map' f l.
Proof.
intros. induction l.
{ reflexivity. }
{ simpl. rewrite -> map'_unroll. rewrite -> IHl. reflexivity. }
Qed.
|
#include <bits/stdc++.h> using namespace std; int a[100009]; int b[100009]; int main() { int n; cin >> n; map<int, int> mp; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; } for (int j = 0; j < n; j++) { cin >> b[j]; mp[b[j]]++; } int c = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (mp.find(a[i] xor b[j]) != mp.end()) c++; } } if (c & 1) { cout << Koyomi n ; } else { cout << Karen n ; } }
|
#include <bits/stdc++.h> using namespace std; bool containsr(int x21, int y21, int x22, int y22, int x11, int y11, int x12, int y12) { return x21 >= x11 && y21 >= y11 && x22 <= x12 && y22 <= y12; } int main() { int n; cin >> n; int found = 0; int x11 = -1, y11 = -1, x12 = -1, y12 = -1; int bottom = 1; int left = 1; int top = n; int right = n; int l = bottom, r = top; while (true) { if (l > r) { top = l; break; } int m = (r + l) / 2; cout << ? << left << << bottom << << right << << m << endl; fflush(stdout); int res; cin >> res; if (res >= 1) { r = m - 1; } else { l = m + 1; } } l = bottom, r = top; while (true) { if (l > r) { bottom = r; break; } int m = (r + l) / 2; cout << ? << left << << m << << right << << top << endl; fflush(stdout); int res; cin >> res; if (res >= 1) { l = m + 1; } else { r = m - 1; } } l = left, r = right; while (true) { if (l > r) { right = l; break; } int m = (r + l) / 2; cout << ? << left << << bottom << << m << << top << endl; fflush(stdout); int res; cin >> res; if (res >= 1) { r = m - 1; } else { l = m + 1; } } l = left, r = right; while (true) { if (l > r) { left = r; break; } int m = (r + l) / 2; cout << ? << m << << bottom << << right << << top << endl; fflush(stdout); int res; cin >> res; if (res >= 1) { l = m + 1; } else { r = m - 1; } } x11 = left, y11 = bottom, x12 = right, y12 = top; int x21 = -1, y21 = -1, x22 = -1, y22 = -1; bottom = 1; left = 1; top = n; right = n; l = bottom, r = top; while (true) { if (l > r) { top = l; break; } int m = (r + l) / 2; cout << ? << left << << bottom << << right << << m << endl; fflush(stdout); int res; cin >> res; if (containsr(x11, y11, x12, y12, left, bottom, right, m)) { res--; } if (res >= 1) { r = m - 1; } else { l = m + 1; } } l = bottom, r = top; while (true) { if (l > r) { bottom = r; break; } int m = (r + l) / 2; cout << ? << left << << m << << right << << top << endl; fflush(stdout); int res; cin >> res; if (containsr(x11, y11, x12, y12, left, m, right, top)) { res--; } if (res >= 1) { l = m + 1; } else { r = m - 1; } } l = left, r = right; while (true) { if (l > r) { right = l; break; } int m = (r + l) / 2; cout << ? << left << << bottom << << m << << top << endl; fflush(stdout); int res; cin >> res; if (containsr(x11, y11, x12, y12, left, bottom, m, top)) { res--; } if (res >= 1) { r = m - 1; } else { l = m + 1; } } l = left, r = right; while (true) { if (l > r) { left = r; break; } int m = (r + l) / 2; cout << ? << m << << bottom << << right << << top << endl; fflush(stdout); int res; cin >> res; if (containsr(x11, y11, x12, y12, m, bottom, right, top)) { res--; } if (res >= 1) { l = m + 1; } else { r = m - 1; } } x21 = left, y21 = bottom, x22 = right, y22 = top; cout << ! << x11 << << y11 << << x12 << << y12 << << x21 << << y21 << << x22 << << y22 << endl; }
|
`timescale 1ns/1ns
// This assumes the DUT to has 1 master and 1 slave AXI IF.
// // e.g.
// @AxiMaster()
// var M.a int[16]
//
// @AxiSlave()
// var M.b int[16]
//
// @ThreadEntry()
// def M.t() { ... }
//
// M.compile()
// M.writeHdl("/tmp/a.v")
module axi_tb;
reg clk, rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [7:0] ARLEN;
wire [2:0] ARSIZE;
wire RVALID;
wire [31:0] RDATA;
wire RREADY;
wire RLAST;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [7:0] AWLEN;
wire [2:0] AWSIZE;
wire WVALID;
wire WREADY;
wire [31:0] WDATA;
wire WLAST;
wire BVALID;
wire BREADY;
wire [1:0] BRESP;
initial begin
clk <= 0;
rst <= 1;
#15
rst <= ~rst;
#10000
$finish;
end
always begin
#10 clk = ~clk;
end
main main_inst(.clk(clk), .rst(rst),
.a_ARADDR(ARADDR), .b_ARADDR(ARADDR),
.a_ARVALID(ARVALID),. b_ARVALID(ARVALID),
.a_ARREADY(ARREADY), .b_ARREADY(ARREADY),
.a_ARLEN(ARLEN), .b_ARLEN(ARLEN),
.a_ARSIZE(ARSIZE), .b_ARSIZE(ARSIZE),
.a_RVALID(RVALID), .b_RVALID(RVALID),
.a_RDATA(RDATA), .b_RDATA(RDATA),
.a_RREADY(RREADY), .b_RREADY(RREADY),
.a_RLAST(RLAST), .b_RLAST(RLAST),
.a_AWADDR(AWADDR), .b_AWADDR(AWADDR),
.a_AWVALID(AWVALID), .b_AWVALID(AWVALID),
.a_AWREADY(AWREADY), .b_AWREADY(AWREADY),
.a_AWLEN(AWLEN), .b_AWLEN(AWLEN),
.a_AWSIZE(AWSIZE), .b_AWSIZE(AWSIZE),
.a_WVALID(WVALID), .b_WVALID(WVALID),
.a_WREADY(WREADY), .b_WREADY(WREADY),
.a_WDATA(WDATA), .b_WDATA(WDATA),
.a_WLAST(WLAST), .b_WLAST(WLAST),
.a_BVALID(BVALID), .b_BVALID(BVALID),
.a_BREADY(BREADY), .b_BREADY(BREADY),
.a_BRESP(BRESP), .b_BRESP(BRESP)
);
initial begin
$dumpfile("/tmp/axi.vcd");
$dumpvars(0, main_inst);
end
endmodule // axi_tb
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; long long f[15], all[15]; long long n, k; int solve(int rem) { if (!rem) return 1; return solve(rem - 1) * 2; } long long solve(int i, string& str) { if (i == str.size()) return 1; long long ret = solve(i + 1, str); if (str[i] == 1 ) ret += all[str.size() - i - 1]; return ret; } bool lucky(long long x) { while (x) { if (x % 10 != 4 && x % 10 != 7) return 0; x /= 10; } return 1; } int main() { all[0] = f[0] = 1; for (int i = 1; i < 15; ++i) { f[i] = f[i - 1] * i; all[i] = 2ll * all[i - 1]; } cin >> n >> k; if (n < 15 && f[n] < k) return cout << -1, 0; long long nn = n; int rem = 0; for (int i = 0; i < 14; ++i) if (f[i] < k) rem = i; long long ans = 0; set<long long> rem_num; if (n > rem + 1) { long long m = n - rem - 1; string cur = , s = ; stringstream mycin; mycin << m; mycin >> cur; bool ok = 0, is = 0; int lstseven = -1; for (int i = 0; i < cur.size(); ++i) { int ch = cur[i] - 0 ; if (ok) break; if (ch < 4) { is = 1; break; } else if (ch > 7) ok = 1, lstseven = 1e9 + 5; else if (ch == 7) lstseven = max(lstseven, i); else if (ch > 4) ok = 1; } if (is && lstseven == -1) { int sz = cur.size(); --sz; while (sz--) s += 1 ; } else { ok = 0; for (int i = 0; i < cur.size(); ++i) { int ch = cur[i] - 0 ; if (ok) s += 1 ; else if (is && lstseven == i) s += 0 , ok = 1; else if (ch > 7) ok = 1, s += 1 ; else if (ch == 7) s += 1 ; else if (ch > 4) s += 0 , ok = 1; else s += 0 ; } } if (s.size()) { ans += solve(0, s); for (int i = 1; i < s.size(); ++i) ans += all[i]; } for (int i = n; rem_num.size() <= rem; --i) rem_num.insert(i); n = rem + 1; } else for (int i = 1; i <= n; ++i) rem_num.insert(i); for (int i = nn - n + 1; i <= nn; ++i) { vector<int> v; while (f[nn - i] < k) { k -= f[nn - i]; v.push_back(*rem_num.begin()); rem_num.erase(rem_num.begin()); } int x = *rem_num.begin(); rem_num.erase(rem_num.begin()); for (int j : v) rem_num.insert(j); ans += lucky(i) && lucky(x); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int suma = 0, ans = 0, count = 0; for (int i = n - 1; i >= 0; i--) { if (suma + arr[i] <= k) suma = suma + arr[i]; else { suma = arr[i]; count += 1; } if (count >= m) break; ans += 1; } cout << ans << endl; return 0; }
|
module fast_clock_domain(
input clk,
input rst,
input [15:0] probe,
output [15:0] sample_data,
output sample_data_avail,
input overflow,
input acq_enable,
input [7:0] clock_divisor,
input [15:0] channel_enable,
output stalled
);
wire sample_tick;
reg stalled_d, stalled_q;
clock_divider ckd(clk, rst, acq_enable, clock_divisor, sample_tick);
genvar i;
generate
for (i=0; i<16; i=i+1) begin : CHANNEL
wire probe_synced;
wire [15:0] chandata_parallel;
wire chandata_parallel_ready;
synchronizer probe_sync(clk, probe[i], probe_synced);
serial_to_parallel s2p(.clk(clk), .rst(rst), .tick(sample_tick),
.enable(acq_enable & channel_enable[i]),
.in(probe_synced), .out(chandata_parallel),
.ready(chandata_parallel_ready));
reg [15:0] latch_d, latch_q;
reg valid_d, valid_q;
wire [15:0] latch_chain;
wire valid_chain;
always @(*) begin
if(acq_enable) begin
if (chandata_parallel_ready) begin
latch_d = chandata_parallel;
valid_d = 1'b1;
end else begin
latch_d = latch_chain;
valid_d = valid_chain;
end
end else begin
latch_d = 16'h0000;
valid_d = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
latch_q <= 16'h0000;
valid_q <= 1'b0;
end else begin
latch_q <= latch_d;
valid_q <= valid_d;
end
end
end
endgenerate
generate
for (i=1; i<16; i=i+1) begin : CHAINING
assign CHANNEL[i-1].latch_chain = CHANNEL[i].latch_q;
assign CHANNEL[i-1].valid_chain = CHANNEL[i].valid_q;
end
endgenerate
assign CHANNEL[15].latch_chain = 16'h0000;
assign CHANNEL[15].valid_chain = 1'b0;
// Stall output if overflow detected
always @(*) begin
stalled_d = stalled_q | overflow;
end
always @(posedge clk) begin
if (rst) begin
stalled_q <= 1'b0;
end else begin
stalled_q <= stalled_d;
end
end
assign sample_data = CHANNEL[0].latch_q;
assign sample_data_avail = CHANNEL[0].valid_q && !stalled && !overflow;
assign stalled = stalled_q;
endmodule // fast_clock_domain
|
module memory_tb();
reg clk;
reg rst;
reg[3:0] rd_en, wr_en;
reg[6:0] input_tag;
reg[63:0] wr_mask;
reg[2047:0] addresses;
reg[8191:0] wr_data;
wire ack;
wire[6:0] output_tag;
wire[2047:0] tracemon_addr;
wire[8191:0] rd_data, tracemon_store_data;
memory mem(
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
wr_mask,
rd_data,
output_tag,
ack,
tracemon_addr,
tracemon_store_data,
clk,
rst
);
initial begin
clk = 0;
while (1) begin
#2;
clk = ~clk;
end
end
initial begin
rst = 1;
rd_en = 4'b0000;
wr_en = 4'b0000;
#11;
rst = 0;
#20
input_tag = 1;
addresses = 2048'h00000034_00000024_00000014_00000004;
wr_data = 8192'h00000001_00000002_00000003_00000004_00000005_00000006_00000007_00000008;
wr_en = 4'b0101;
wr_mask = 7;
#4
wr_en = 4'b0000;
#20;
input_tag = 2;
addresses = 2048'h00000034_00000024_00000014_00000004;
rd_en = 4'b0101;
wr_mask = 1;
#4
rd_en = 0;
#10
$finish;
end
always @ (posedge clk) begin
if (!rst) begin
$display ("Time= %g : Ack= %b : Output_tag= %b", $time, ack, output_tag);
if(ack) begin
$display ("Addr: %h Read Data: %h", addresses[31:0], rd_data[127:0]);
$display ("Addr: %h Read Data: %h", addresses[63:32], rd_data[255:128]);
$display ("Addr: %h Read Data: %h", addresses[95:64], rd_data[383:256]);
$display ("Addr: %h Read Data: %h", addresses[127:96], rd_data[511:384]);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename tp> inline void read(tp& x) { x = 0; char tmp; bool key = 0; for (tmp = getchar(); !isdigit(tmp); tmp = getchar()) key = (tmp == - ); for (; isdigit(tmp); tmp = getchar()) x = (x << 3) + (x << 1) + (tmp ^ 0 ); if (key) x = -x; } template <typename tp> inline void ckmn(tp& x, tp y) { x = x < y ? x : y; } template <typename tp> inline void ckmx(tp& x, tp y) { x = x < y ? y : x; } const long long LLINF = (long long)1e18; const int N = 100010, MP = 20; int n, q, sta[N]; long long rec[MP], val[N]; struct node { long long mn; long long rv; long long tag; int rec; } t[N << 2]; void puttag(int x, long long v) { t[x].tag += v; t[x].mn -= v; t[x].rv += v; } void putrec(int x) { t[x].rec = 1; t[x].rv = t[x].mn = LLINF; t[x].tag = 0; } void push_down(int x) { if (t[x].tag) { puttag(x << 1, t[x].tag); puttag(x << 1 | 1, t[x].tag); t[x].tag = 0; } if (t[x].rec) { putrec(x << 1); putrec(x << 1 | 1); t[x].rec = 0; } } void push_up(int x) { t[x].mn = min(t[x << 1].mn, t[x << 1 | 1].mn); t[x].rv = t[x << 1 | 1].rv; if (t[x].rv >= LLINF) t[x].rv = t[x << 1].rv; } long long query(int p, int x = 1, int lp = 1, int rp = n) { if (lp == rp) return t[x].rv; push_down(x); int mid = (lp + rp) >> 1; if (p <= mid) return query(p, x << 1, lp, mid); long long tmp = query(p, x << 1 | 1, mid + 1, rp); if (tmp >= LLINF) return t[x << 1].rv; else return tmp; } long long askmn(int l, int r, int x = 1, int lp = 1, int rp = n) { if (l > rp || lp > r) return LLINF; if (lp >= l && rp <= r) return t[x].mn; int mid = (lp + rp) >> 1; push_down(x); return min(askmn(l, r, x << 1, lp, mid), askmn(l, r, x << 1 | 1, mid + 1, rp)); } void modify(int l, int r, long long v, int x = 1, int lp = 1, int rp = n) { if (l > rp || lp > r) return; if (lp >= l && rp <= r) { puttag(x, v); return; } int mid = (lp + rp) >> 1; push_down(x); modify(l, r, v, x << 1, lp, mid), modify(l, r, v, x << 1 | 1, mid + 1, rp); push_up(x); } void doit(int x = 1, int lp = 1, int rp = n) { if (t[x].mn >= 0) return; if (lp == rp) { while (t[x].mn < 0) { ++sta[lp]; t[x].mn = rec[sta[lp]] - t[x].rv; } return; } int mid = (lp + rp) >> 1; push_down(x); doit(x << 1, lp, mid); doit(x << 1 | 1, mid + 1, rp); push_up(x); } void fill(int l, int r, int x = 1, int lp = 1, int rp = n) { if (l > rp || lp > r) return; if (lp >= l && rp <= r) { putrec(x); return; } int mid = (lp + rp) >> 1; push_down(x); fill(l, r, x << 1, lp, mid); fill(l, r, x << 1 | 1, mid + 1, rp); push_up(x); } void setval(int p, long long v, int x = 1, int lp = 1, int rp = n) { if (lp == rp) { t[x].rv = v; t[x].tag = 0, t[x].rec = 0; t[x].mn = rec[0] - v; sta[lp] = 0; return; } int mid = (lp + rp) >> 1; push_down(x); if (p <= mid) setval(p, v, x << 1, lp, mid); else setval(p, v, x << 1 | 1, mid + 1, rp); push_up(x); } void build(int x = 1, int lp = 1, int rp = n) { t[x].tag = t[x].rec = 0; if (lp == rp) { t[x].rv = val[lp]; t[x].mn = rec[sta[lp]] - val[lp]; return; } int mid = (lp + rp) >> 1; build(x << 1, lp, mid); build(x << 1 | 1, mid + 1, rp); push_up(x); } int main() { int tp, x, y, z; read(n), read(q); for (int i = (1); i <= (n); ++i) read(val[i]); rec[0] = 1; for (int i = 1; rec[i - 1] <= LLINF / 42; ++i) rec[i] = rec[i - 1] * 42; build(); for (int i = (1); i <= (q); ++i) { read(tp); if (tp == 1) { read(x); printf( %lld n , query(x)); } else if (tp == 2) { read(x), read(y), read(z); if (y < n) setval(y + 1, query(y + 1)); setval(x, z); if (x < y) fill(x + 1, y); } else { read(x), read(y), read(z); setval(x, query(x)); if (y < n) setval(y + 1, query(y + 1)); while (true) { modify(x, y, z); doit(); if (askmn(x, y) > 0) break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000; const int dx[4] = {1, 1, -1, -1}; const int dy[4] = {1, -1, -1, 1}; int n, m; int t[MAXN + 2][MAXN + 2]; int dp[4][MAXN + 2][MAXN + 2]; int sol; int main() { ios::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) cin >> t[i][j]; for (int d = 0; d < 4; ++d) for (int i = dy[d] == 1 ? 1 : n; i && i <= n; i += dy[d]) for (int j = dx[d] == 1 ? 1 : m; j && j <= m; j += dx[d]) dp[d][i][j] = max(dp[d][i - dy[d]][j], dp[d][i][j - dx[d]]) + t[i][j]; for (int i = 2; i < n; ++i) for (int j = 2; j < m; ++j) sol = max(sol, max(dp[0][i - 1][j] + dp[1][i][j - 1] + dp[2][i + 1][j] + dp[3][i][j + 1], dp[0][i][j - 1] + dp[1][i + 1][j] + dp[2][i][j + 1] + dp[3][i - 1][j])); cout << sol << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 305000; const int INF = 105000; int main() { long long n, k; cin >> n >> k; long long g = (n / 2) / (k + 1); long long d = g * k; long long ost = n - d - g; cout << g << << d << << ost; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, cnt11 = 0, cnt12 = 0, cnt13 = 0, cnt14 = 0, cnt15 = 0, cnt16 = 0, cnt17 = 0, cnt18 = 0, cnt19 = 0; int cnt21 = 0, cnt22 = 0, cnt23 = 0, cnt24 = 0, cnt25 = 0, cnt26 = 0, cnt27 = 0, cnt28 = 0, cnt29 = 0; cin >> n >> m; int a[n], b[m]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { cin >> b[i]; } sort(a, a + n); sort(b, b + m); for (int i = 0; i < n; i++) { if (a[i] == 1) { cnt11++; } if (a[i] == 2) { cnt12++; } if (a[i] == 3) { cnt13++; } if (a[i] == 4) { cnt14++; } if (a[i] == 5) { cnt15++; } if (a[i] == 6) { cnt16++; } if (a[i] == 7) { cnt17++; } if (a[i] == 8) { cnt18++; } if (a[i] == 9) { cnt19++; } } for (int i = 0; i < m; i++) { if (b[i] == 1) { cnt21++; } if (b[i] == 2) { cnt22++; } if (b[i] == 3) { cnt23++; } if (b[i] == 4) { cnt24++; } if (b[i] == 5) { cnt25++; } if (b[i] == 6) { cnt26++; } if (b[i] == 7) { cnt27++; } if (b[i] == 8) { cnt28++; } if (b[i] == 9) { cnt29++; } } if (cnt11 > 0 && cnt21 > 0) { cout << 1 << endl; } else if (cnt12 > 0 && cnt22 > 0) { cout << 2 << endl; } else if (cnt13 > 0 && cnt23 > 0) { cout << 3 << endl; } else if (cnt14 > 0 && cnt24 > 0) { cout << 4 << endl; } else if (cnt15 > 0 && cnt25 > 0) { cout << 5 << endl; } else if (cnt16 > 0 && cnt26 > 0) { cout << 6 << endl; } else if (cnt17 > 0 && cnt27 > 0) { cout << 7 << endl; } else if (cnt18 > 0 && cnt28 > 0) { cout << 8 << endl; } else if (cnt19 > 0 && cnt29 > 0) { cout << 9 << endl; } else { if (a[0] == b[0]) { cout << a[0] << endl; } if (a[0] > b[0]) { cout << b[0] << a[0] << endl; } if (a[0] < b[0]) { cout << a[0] << b[0] << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_1_V
`define SKY130_FD_SC_HDLL__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_1_V
`define SKY130_FD_SC_LS__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_1_V
|
// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_rx
// ============================================================
// File Name: altera_tse_pma_lvds_rx.v
// Megafunction Name(s):
// altlvds_rx
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Internal Build 97 06/25/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_rx (
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_out,
rx_outclock);
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output [9:0] rx_out;
output rx_outclock;
wire [0:0] sub_wire0;
wire [9:0] sub_wire1;
wire sub_wire2;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire [9:0] rx_out = sub_wire1[9:0];
wire rx_outclock = sub_wire2;
altlvds_rx altlvds_rx_component (
.rx_inclock (rx_inclock),
.rx_reset (rx_reset),
.rx_in (rx_in),
.rx_divfwdclk (sub_wire0),
.rx_out (sub_wire1),
.rx_outclock (sub_wire2),
.pll_areset (1'b0),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_channel_data_align (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_deskew (1'b0),
.rx_dpa_locked (),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_enable (1'b1),
.rx_fifo_reset (1'b0),
.rx_locked (),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_syncclock (1'b0));
defparam
altlvds_rx_component.common_rx_tx_pll = "ON",
altlvds_rx_component.deserialization_factor = 10,
altlvds_rx_component.enable_dpa_mode = "ON",
altlvds_rx_component.enable_soft_cdr_mode = "ON",
altlvds_rx_component.implement_in_les = "OFF",
altlvds_rx_component.inclock_period = 8000,
altlvds_rx_component.input_data_rate = 1250,
altlvds_rx_component.intended_device_family = "Stratix III",
altlvds_rx_component.lpm_type = "altlvds_rx",
altlvds_rx_component.number_of_channels = 1,
altlvds_rx_component.outclock_resource = "AUTO",
altlvds_rx_component.registered_output = "ON",
altlvds_rx_component.use_external_pll = "OFF",
altlvds_rx_component.enable_dpa_align_to_rising_edge_only = "OFF",
altlvds_rx_component.enable_dpa_initial_phase_selection = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Bitslip NUMERIC "4"
// Retrieval info: PRIVATE: Channel_Data_Align_Max NUMERIC "0"
// Retrieval info: PRIVATE: Channel_Data_Align_Reset NUMERIC "0"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "1250"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Dpa_Locked NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Enable NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Hold NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Reset NUMERIC "1"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: Fifo_Reset NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: Int_Device STRING "Stratix III"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "1"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Lose_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Reset_Fifo NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: enable_dpa_align_to_rising_edge_only STRING "OFF"
// Retrieval info: CONSTANT: enable_dpa_initial_phase_selection STRING "OFF"
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL rx_divfwdclk[0..0]
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL rx_in[0..0]
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT_CLK_EXT GND rx_inclock
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL rx_out[9..0]
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL rx_outclock
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT GND rx_reset[0..0]
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int f[100005], b[100005], fn[100005], bn[100005], fm, bm; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d , f + i); ++fn[f[i]]; fm = max(fm, f[i]); } for (int i = 0; i < m; ++i) { scanf( %d , b + i); ++bn[b[i]]; bm = max(bm, b[i]); } if (fm < bm) { printf( Impossible n ); } else { bool ans = true; bool chong = false; for (int i = 1; i <= bm; ++i) { if (bn[i] > 0) { if (fn[i] == 0) { ans = false; } else if (fn[i] > 1) { chong = true; } } } if (!ans) { printf( Impossible n ); } else { if (chong) { printf( Ambiguity n ); } else { printf( Possible n ); for (int i = 0; i < n; ++i) { fn[f[i]] = i + 1; } for (int i = 0; i < m; ++i) { printf( %d , fn[b[i]]); } printf( n ); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int i = -1, j = -1, k = -1, a[n]; for (int l = 0; l < n; l++) { cin >> a[l]; } for (int l = 1; l < n - 1; l++) { j = l; for (int m = j - 1; m >= 0; m--) { if (a[m] < a[j]) { i = m; break; } } for (int p = j + 1; p < n; p++) { if (a[p] < a[j]) { k = p; break; } } if (i != -1 && k != -1) { cout << YES n << i + 1 << << j + 1 << << k + 1 << n ; break; } else { i = -1; k = -1; } } if (i == -1 or k == -1) { cout << NO << n ; } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXM = 500005; const int MAXN = 15; const int N = 12; int w[MAXN]; char query[MAXN]; char s[MAXN]; int n, m, q; int transform(char* s) { int ans = 0; for (int i = 0; i < n; i++) { ans = 2 * ans + (s[i] - 0 ); } return ans; } int cnt_set[(1 << N)]; int dif[(1 << N)][(1 << N)]; int get_dif(int a, int b) { int ans = 0; for (int i = 0; i < n; i++) { if ((a & 1) == (b & 1)) ans += w[i]; a >>= 1; b >>= 1; } return ans; } vector<pair<int, int>> cnt_queries[(1 << N)]; int sol[MAXM]; const int MAXK = 101; int main() { scanf( %d %d %d , &n, &m, &q); for (int i = n - 1; i >= 0; i--) scanf( %d , &w[i]); for (int i = 1; i <= m; i++) { scanf( %s , s); int val = transform(s); cnt_set[val]++; } for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < (1 << n); j++) { dif[i][j] = get_dif(i, j); } } for (int i = 1; i <= q; i++) { scanf( %s , query); int p = transform(query); int k; scanf( %d , &k); cnt_queries[p].push_back({k, i}); } for (int i = 0; i < (1 << n); i++) { vector<int> current(MAXK); for (int i = 0; i < MAXK; i++) current[i] = 0; for (int j = 0; j < (1 << n); j++) { if (dif[i][j] < MAXK) { current[dif[i][j]] += cnt_set[j]; } } for (int i = 1; i < MAXK; i++) current[i] += current[i - 1]; for (auto p : cnt_queries[i]) { sol[p.second] = current[p.first]; } } for (int i = 1; i <= q; i++) printf( %d n , sol[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int up = 1e6 + 6; int n, m, k, pos; int cost[up], p[up], last[up]; int main() { scanf( %d , &n); scanf( %d , &m); scanf( %d , &k); for (int i = 1; i <= m; i++) { scanf( %d , &pos); p[pos] = 1; } if (p[0]) { printf( %d n , -1); return 0; } for (int i = 0; i <= n; i++) { if (!p[i]) last[i] = i; else last[i] = last[i - 1]; } for (int i = 1; i <= k; i++) { scanf( %d , &cost[i]); } long long res = 1ll * up * up; for (int i = 1; i <= k; i++) { int cnt = 1; for (int j = i; j < n; j += i) { if (j - last[j] >= i) { cnt = n + 10; break; } else { j = last[j]; cnt++; } } if (cnt <= n) { res = min(res, 1ll * cnt * cost[i]); } } if (res == 1ll * up * up) { res = -1ll; } printf( %I64d n , res); return 0; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:57:22 08/15/2011
// Design Name:
// Module Name: RCB_FRL_RX_OneDataChannel
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// packet header is 0xF508, packet size is 29 bytes on each channel, no error check
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RX_OneDataChannel(
input CLKDIV,
input RST,
input [7:0] DATA_IN,
// output data_valid,
// output [7:0] data_out
output reg data_valid,
output reg [7:0] data_out
);
// reg [15:0] input_reg1;
// wire [7:0] input_reg1_wire, input_reg1_wire_inv;
//
// assign input_reg1_wire = DATA_IN;
// RCB_FRL_BYTE_Alignment RCB_FRL_BYTE_Alignment_inst (
//// .data_in(input_reg1_wire),
// .data_in(DATA_IN),
// .clk(CLKDIV),
// .enable(~RST),
// .data_out(data_out),
// .data_valid(data_valid)
// );
reg [1:0] frame_decap_state;
localparam IDLE = 2'b00;
localparam HEADER = 2'b01;
localparam DATA_OUT = 2'b10;
reg [7:0] data_reg;
reg [4:0] counter;
always@(posedge CLKDIV) data_reg[7:0] <= DATA_IN[7:0];
always@(posedge CLKDIV) begin
if (RST) begin
counter[4:0] <= 5'h00;
data_valid <= 1'b0;
data_out[7:0] <= 8'h00;
frame_decap_state <= IDLE;
end else begin
case (frame_decap_state)
IDLE: begin
counter[4:0] <= 5'h00;
data_valid <= 1'b0;
data_out[7:0] <= 8'h00;
if ( data_reg[7:0] == 8'hF5 ) // frame detected
frame_decap_state <= HEADER;
else
frame_decap_state <= IDLE;
end
HEADER: begin
counter[4:0] <= 5'h00;
data_valid <= 1'b0;
data_out[7:0] <= 8'h00;
if ( data_reg[7:0] == 8'h1D ) // frame detected
// if ( data_reg[7:0] == 8'h08 ) // frame detected
frame_decap_state <= DATA_OUT;
else if ( data_reg[7:0] == 8'hF5 )
frame_decap_state <= HEADER;
else
frame_decap_state <= IDLE;
end
DATA_OUT: begin
counter[4:0] <= counter[4:0] + 5'h01;
data_valid <= 1'b1;
data_out[7:0] <= data_reg[7:0];
if (counter >= 5'h1C)
frame_decap_state <= IDLE;
else
frame_decap_state <= DATA_OUT;
end
default: begin
counter[4:0] <= 5'h00;
data_valid <= 1'b0;
data_out[7:0] <= 8'h00;
frame_decap_state <= IDLE;
end
endcase
end
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.