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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void Anivia_kid() { long long n; cin >> n; long long res = 1 + 3 * n * (n + 1); cout << res << n ; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q = 1; while (q--) { Anivia_kid(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFSTP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_BLACKBOX_V
|
module csr#(
parameter NUM_CH = 8,
parameter NUM_SPDIF_IN = 3,
parameter NUM_RATE = 5,
parameter VOL_WIDTH = NUM_CH*32,
parameter NKMDDBG_WIDTH = 16*8,
parameter RATE_WIDTH = NUM_SPDIF_IN*NUM_RATE,
parameter UDATA_WIDTH = NUM_SPDIF_IN*192,
parameter CDATA_WIDTH = UDATA_WIDTH
)(
input wire clk,
input wire rst,
// memory if
input wire [11:0] addr_i,
input wire ack_i,
input wire [7:0] data_i,
output wire [7:0] data_o,
// registers access
output wire [(VOL_WIDTH-1):0] vol_o, // addr: 12'h000 ~
output wire nkmd_rst_o, // addr: 12'h400
input wire [(NKMDDBG_WIDTH-1):0] nkmd_dbgout_i, // addr: 12'h500 ~ 12'h50f
output wire [(NKMDDBG_WIDTH-1):0] nkmd_dbgin_o, // addr: 12'h600 ~ 12'h60f
input wire [(RATE_WIDTH-1):0] rate_i, // addr: 12'h800 ~
input wire [(UDATA_WIDTH-1):0] udata_i, // addr: 12'h900 ~
input wire [(CDATA_WIDTH-1):0] cdata_i // addr: 12'ha00 ~
);
reg [7:0] data_o_ff;
reg ack_o_ff;
wire [3:0] addr_tag = addr_i[11:8];
wire [7:0] addr_offset = addr_i[7:0];
reg [(VOL_WIDTH-1):0] vol_ff;
assign vol_o = vol_ff;
reg nkmd_rst_ff;
assign nkmd_rst_o = nkmd_rst_ff;
reg [(NKMDDBG_WIDTH-1):0] nkmd_dbgin_ff;
assign nkmd_dbgin_o = nkmd_dbgin_ff;
integer i;
always @(posedge clk) begin
if(rst) begin
vol_ff <= {(NUM_CH*2){16'h00ff}};
nkmd_rst_ff <= 1'b1;
nkmd_dbgin_ff <= {(NKMDDBG_WIDTH){1'b0}};
end else if(ack_i) begin
case(addr_tag)
4'h0: begin
// ISE bug workaround... :(
for(i = 0; i < 8; i = i + 1)
vol_ff[(addr_offset*8 + i)] <= data_i[i];
end
4'h4: begin
nkmd_rst_ff <= data_i[0];
end
4'h6: begin
// ISE bug workaround... :(
for(i = 0; i < 8; i = i + 1)
nkmd_dbgin_ff[(addr_offset*8 + i)] <= data_i[i];
end
endcase
end
end
always @(posedge clk) begin
case(addr_tag)
4'h0:
data_o_ff <= vol_ff[(addr_offset*8) +: 8];
4'h4:
data_o_ff <= {7'b0000_000, nkmd_rst_ff};
4'h5:
data_o_ff <= nkmd_dbgout_i[(addr_offset*8) +: 8];
4'h6:
data_o_ff <= nkmd_dbgin_ff[(addr_offset*8) +: 8];
4'h8:
data_o_ff <= rate_i[(addr_offset*NUM_RATE) +: NUM_RATE];
4'h9:
data_o_ff <= udata_i[(addr_offset*8) +: 8];
4'ha:
data_o_ff <= cdata_i[(addr_offset*8) +: 8];
default:
data_o_ff <= 0;
endcase
end
assign data_o = data_o_ff;
endmodule
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module sha3_seq
#(
parameter CC=24
)
(
clk,
rst,
g_init,
e_init,
o
);
input clk;
input rst;
input [287:0] g_init;
input [287:0] e_init;
output [1599:0] o;
reg init;
reg [CC-1:0] rc_i; /* select round constant */
reg [24-1:0] rc_j[24/CC-1:0]; /* select round constant */
wire [63:0] rc[24/CC-1:0]; /* round constant */
wire [1599:0] round_in[24/CC-1:0];
wire [1599:0] round_out[24/CC-1:0];
reg [1599:0] round_reg;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
init <= 0;
rc_i <= 0;
round_reg <= {e_init, g_init};
end
else
begin
init <= 1;
rc_i <= {rc_i[CC-2:0], ~init};
round_reg <= round_out[24/CC-1];
end
end
assign round_in[0] = round_reg;
assign o = round_out[24/CC-1];
integer k,t;
always@(*)
begin
for(k=0;k<24/CC;k=k+1)
begin
rc_j[k] = 0;
for(t=0;t<CC;t=t+1)
begin
rc_j[k][(24/CC)*t+k] = rc_i[t];
end
end
end
genvar q;
generate
for(q=1;q<24/CC;q=q+1)
begin:ASSROUND
assign round_in[q] = round_out[q-1];
end
endgenerate
generate
for(q=0;q<24/CC;q=q+1)
begin:RCONST
rconst rconst_
(
.i(rc_j[q]),
.rc(rc[q])
);
end
endgenerate
generate
for(q=0;q<24/CC;q=q+1)
begin:ROUND
round
round_
(
.in(round_in[q]),
.round_const(rc[q]),
.out(round_out[q])
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_4_V
`define SKY130_FD_SC_LP__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, fp = 0; cin >> n; vector<int> p(n); bool nice = false; bool entrou = false; for (int i = 0; i < n; i++) { cin >> p[i]; if (i == p[i]) fp = fp + 1; } for (int i = 0; i < n; i++) { if (p[i] != i) { entrou = true; if (p[p[i]] == i) { fp = fp + 2; nice = true; break; } } } if (!nice && entrou) { fp = fp + 1; } cout << fp << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_2_V
`define SKY130_FD_SC_HS__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_2_V
|
#include <bits/stdc++.h> using namespace std; struct habijabi { long int start_time, end_time; } work[500500]; bool cmp(habijabi a, habijabi b) { if (a.end_time == b.end_time) { return a.start_time < b.start_time; } return a.end_time < b.end_time; } int main() { long int t, n, i, j; scanf( %ld , &n); for (i = 0; i < n; i++) { scanf( %ld %ld , &work[i].start_time, &work[i].end_time); } sort(work, work + n, cmp); int ans = 0, prev_end = -1; for (i = 0; i < n; i++) { if (work[i].start_time > prev_end) { ans++; prev_end = work[i].end_time; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long x, y, p, q; cin >> x >> y >> p >> q; if (p == q && x == y) { printf( 0 n ); continue; } if (p == 0 && x == 0) { printf( 0 n ); continue; } if (p == q || p == 0 || q == 0) { printf( -1 n ); continue; } long long i = max( (x - p * ((y + q - 1) / q) + p - 1) / p, (p * ((y + q - 1) / q) - (x + ((y + q - 1) / q) * q - y) + q - p - 1) / (q - p)); printf( %lld n , i * q + ((y + q - 1) / q) * q - y); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = int(1e9) + 7; const long long int MOD64 = (long long int)(1e18) + 7; const int INF = 0x7fffffff; const long long int INF64 = 0x7fffffffffffffff; const int N = 2e4 + 200; int a[60][N]; int sum[60][N]; int dp[60][N]; int t[4 * N], lazy[4 * N]; void update_lazy(int i, int lo, int hi) { if (lazy[i]) { t[i] += lazy[i]; if (lo != hi) { lazy[i * 2] += lazy[i]; lazy[i * 2 + 1] += lazy[i]; } lazy[i] = 0; } } int update(int i, int lo, int hi, int l, int r, int val) { update_lazy(i, lo, hi); if (lo > r || hi < l) return t[i]; if (l <= lo && hi <= r) { t[i] += val; if (lo != hi) { lazy[i * 2] += val; lazy[i * 2 + 1] += val; } return t[i]; } int mid = (lo + hi) / 2; return t[i] = max(update(i * 2, lo, mid, l, r, val), update(i * 2 + 1, mid + 1, hi, l, r, val)); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m >> k; for (int i = int(1); i < int(n + 1); i++) { for (int j = int(1); j < int(m + 1); j++) { cin >> a[i][j]; sum[i][j] = sum[i][j - 1] + a[i][j]; } } int mm = m - k + 1; for (int i = int(1); i < int(mm + 1); i++) dp[1][i] = sum[1][i + k - 1] - sum[1][i - 1] + sum[2][i + k - 1] - sum[2][i - 1]; for (int i = int(2); i < int(n + 1); i++) { memset(t, 0, sizeof(t)); memset(lazy, 0, sizeof(lazy)); for (int j = int(1); j < int(mm + 1); j++) update(1, 1, mm, j, j, dp[i - 1][j]); for (int j = int(1); j < int(k + 1); j++) update(1, 1, mm, 1, j, -a[i][j]); for (int j = int(1); j < int(mm + 1); j++) { dp[i][j] = t[1] + sum[i][j + k - 1] - sum[i][j - 1] + sum[i + 1][j + k - 1] - sum[i + 1][j - 1]; if (j != mm) { update(1, 1, mm, max(1, j - k + 1), j, a[i][j]); update(1, 1, mm, j + 1, j + k, -a[i][j + k]); } } } cout << *max_element(dp[n] + 1, dp[n] + mm + 1) << endl; return 0; }
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:36 EST 2016
//
// Method conflict info:
// Method: gen_grant_carry
// Conflict-free: gen_grant_carry
//
//
// Ports:
// Name I/O size props
// gen_grant_carry O 2
// gen_grant_carry_c I 1
// gen_grant_carry_r I 1
// gen_grant_carry_p I 1
//
// Combinational paths from inputs to outputs:
// (gen_grant_carry_c, gen_grant_carry_r, gen_grant_carry_p) -> gen_grant_carry
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_gen_grant_carry(gen_grant_carry_c,
gen_grant_carry_r,
gen_grant_carry_p,
gen_grant_carry);
// value method gen_grant_carry
input gen_grant_carry_c;
input gen_grant_carry_r;
input gen_grant_carry_p;
output [1 : 0] gen_grant_carry;
// signals for module outputs
wire [1 : 0] gen_grant_carry;
// value method gen_grant_carry
assign gen_grant_carry =
{ gen_grant_carry_r && (gen_grant_carry_c || gen_grant_carry_p),
!gen_grant_carry_r &&
(gen_grant_carry_c || gen_grant_carry_p) } ;
endmodule // module_gen_grant_carry
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "nios_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 25600,
the_altsyncram.numwords_a = 25600,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:16:42 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_adc/clk_adc_funcsim.v
// Design : clk_adc
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_adc
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire locked;
clk_adcclk_adc_clk_wiz U0
(.clk_250Mhz(clk_250Mhz),
.clk_in1_n(clk_in1_n),
.clk_in1_p(clk_in1_p),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_adc_clk_wiz" *)
module clk_adcclk_adc_clk_wiz
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
wire clk_250Mhz_clk_adc;
wire clk_in1_clk_adc;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire clkfbout_buf_clk_adc;
wire clkfbout_clk_adc;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_adc),
.O(clkfbout_buf_clk_adc));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUFDS #(
.DQS_BIAS("FALSE"),
.IOSTANDARD("DEFAULT"))
clkin1_ibufgds
(.I(clk_in1_p),
.IB(clk_in1_n),
.O(clk_in1_clk_adc));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_250Mhz_clk_adc),
.O(clk_250Mhz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(4.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(4.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(236.250000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_adc),
.CLKFBOUT(clkfbout_clk_adc),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_adc),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_250Mhz_clk_adc),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i; cin >> t; for (i = 0; i < t; i++) { string s; cin >> s; int j = 0, k, l = s.length(), sum = 0; while (j < l) { if (s[j] == 1 ) { k = j; j++; while (s[j] == 0 ) j++; if (j - k > 1 && s[j] == 1 ) sum = sum + j - k - 1; } else j++; } cout << sum << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> T modulo(T x, T p) { if (x >= 0) return x % p; return p + x % p; } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return a * b / gcd(a, b); } int dfs_paths( int u, int prev, vector<vector<pair<long long, long long> > > &G, long long &cur, priority_queue<pair<long long, pair<long long, long long> > > &pqw) { long long paths, total = 0, profit; for (pair<long long, long long> e : G[u]) { if (e.second == prev) continue; paths = dfs_paths(e.second, u, G, cur, pqw); profit = e.first * paths - (e.first / 2) * paths; pqw.push({profit, {e.first, paths}}); cur += e.first * paths; total += paths; } return max(1ll, total); } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { long long n, S; cin >> n >> S; vector<vector<pair<long long, long long> > > G(n); int u, v; long long w; for (int i = 0; i < n - 1; i++) { cin >> u >> v >> w; u--; v--; G[u].push_back({w, v}); G[v].push_back({w, u}); } long long cur = 0; priority_queue<pair<long long, pair<long long, long long> > > pqw; dfs_paths(0, -1, G, cur, pqw); long long moves = 0, mult; pair<long long, pair<long long, long long> > e; while (cur > S) { e = pqw.top(); pqw.pop(); w = e.second.first / 2; mult = e.second.second; cur -= e.first; pqw.push({w * mult - (w / 2) * mult, {w, mult}}); moves++; } cout << moves << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
|
// This tests SystemVerilog packages
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
package p1;
localparam int p1_prmt = 100+10+1;
typedef bit [10+1-1:0] p1_type;
function int p1_func (int x);
p1_func = x+10+1;
endfunction
endpackage
package p2;
localparam int p1_prmt = 100+20+1;
typedef bit [20+1-1:0] p1_type;
function int p1_func (int x);
p1_func = x+20+1;
endfunction
localparam int p2_prmt = 100+20+2;
typedef bit [20+2-1:0] p2_type;
function int p2_func (int x);
p2_func = x+20+2;
endfunction
endpackage
package p3;
localparam int p1_prmt = 100+30+1;
typedef bit [30+1-1:0] p1_type;
function int p1_func (int x);
p1_func = x+30+1;
endfunction
localparam int p2_prmt = 100+30+2;
typedef bit [30+2-1:0] p2_type;
function int p2_func (int x);
p2_func = x+30+2;
endfunction
localparam int p3_prmt = 100+30+3;
typedef bit [30+3-1:0] p3_type;
function int p3_func (int x);
p3_func = x+30+3;
endfunction
endpackage
module test ();
// import all from p1
import p1::*;
// import only p2_* from p2
import p2::p2_prmt;
import p2::p2_type;
import p2::p2_func;
// import nothing from p3
// declare a set of variables
p1_type p1_var;
p2_type p2_var;
p3::p3_type p3_var;
// error counter
bit err = 0;
initial begin
// test parameters
if ( p1_prmt !== 100+10+1) begin $display("FAILED -- p1_prmt = %d != 100+10+1", p1_prmt); err=1; end
if ( p2_prmt !== 100+20+2) begin $display("FAILED -- p2_prmt = %d != 100+20+2", p2_prmt); err=1; end
if (p3::p3_prmt !== 100+30+3) begin $display("FAILED -- p3::p3_prmt = %d != 100+30+3", p3::p3_prmt); err=1; end
// test variable bit sizes
if ($bits(p1_var) !== 10+1) begin $display("FAILED -- lv = %d != 10+1", $bits(p1_var)); err=1; end
if ($bits(p2_var) !== 20+2) begin $display("FAILED -- lv = %d != 20+2", $bits(p2_var)); err=1; end
if ($bits(p3_var) !== 30+3) begin $display("FAILED -- lv = %d != 30+3", $bits(p3_var)); err=1; end
// test functions
if ( p1_func(1000) !== 1000+10+1) begin $display("FAILED -- p1_func(1000) = %d != 1000+10+1", p1_func(1000)); err=1; end
if ( p2_func(1000) !== 1000+20+2) begin $display("FAILED -- p2_func(1000) = %d != 1000+20+2", p2_func(1000)); err=1; end
if (p3::p3_func(1000) !== 1000+30+3) begin $display("FAILED -- p3::p3_func(1000) = %d != 1000+30+3", p3::p3_func(1000)); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/27/2014 11:48:22 PM
// Design Name:
// Module Name: BIN_DEC2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BIN_DEC2(
input [15:0] B2,
output reg [19:0] bcdout2
);
reg [35:0] z;
integer i;
always @(*)
begin
for(i = 0; i <= 35; i = i+1)
z[i] = 0;
z[18:3] = B2; // shift b 3 places left
//for(i = 0; i <= 12; i = i+1)
repeat(13)
begin
if(z[19:16] > 4)
z[19:16] = z[19:16] + 3;
if(z[23:20] > 4)
z[23:20] = z[23:20] + 3;
if(z[27:24] > 4)
z[27:24] = z[27:24] + 3;
if(z[31:28] > 4)
z[31:28] = z[31:28] + 3;
if(z[35:32] > 4)
z[35:32] = z[35:32] + 3;
z[35:1] = z[34:0];
//z[34:2] = z[33:1];
end
bcdout2 = z[35:16];//20 bits
end
endmodule
|
// This is an up-down counter with initial and max values.
// Moreover, it has an parameter for extra bits to be used
// for counter, in case of using for credit counters. Also
// up and down values could be variable, having max threshold
// of max_step_p.
`include "bsg_defines.v"
module bsg_counter_up_down_variable #( parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter `BSG_INV_PARAM(max_step_p )
//localpara
, parameter step_width_lp =
`BSG_WIDTH(max_step_p)
, parameter ptr_width_lp =
`BSG_WIDTH(max_val_p)
)
( input clk_i
, input reset_i
, input [step_width_lp-1:0] up_i
, input [step_width_lp-1:0] down_i
, output logic [ptr_width_lp-1:0] count_o
);
// keeping track of number of entries and updating read and
// write poniteres, and displaying errors in case of overflow
// or underflow
always_ff @(posedge clk_i)
begin
if (reset_i)
count_o <= init_val_p;
else
// It was tested on Design Compiler that using a
// simple minus and plus operation results in smaller
// design, rather than using xor or other ideas
// between down_i and up_i
count_o <= count_o - down_i + up_i;
end
//synopsys translate_off
always_ff @ (posedge clk_i) begin
if ((count_o==max_val_p) & up_i & (reset_i===0))
$display("%m error: counter overflow at time %t", $time);
if ((count_o==0) & down_i & (reset_i===0))
$display("%m error: counter underflow at time %t", $time);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_up_down_variable)
|
#include <bits/stdc++.h> #define ll long long int #define vi vector<int> #define vll vector<long long int> #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b)) #define ABS(x) ((x) < 0 ? -(x) : (x)) #define setpr(x, y) cout << fixed << setprecision(x) << y #define tr(x) cout << (#x) << = << (x) << n ; using namespace std; void solver(void); ll MOD = 1e9 + 7; double pi = 2 * acos(0.0); //vector<vector<ll>> mat( n , vector<ll> (m, 0)); int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) solver(); } void solver(void) { //input ll n; cin >> n; vll v(n); for (ll i = 0; i < n; i++) { v[i] = i + 1; } if (n % 2 == 0) { for (ll i = 0; i < n - 1; i = i + 2) { swap(v[i], v[i + 1]); } } else { for (ll i = 0; i <= n - 3; i = i + 2) { swap(v[i], v[i + 1]); } swap(v[n - 2], v[n - 1]); } for (ll i = 0; i < n; i++) { cout << v[i] << ; } cout << n ; }
|
#include <bits/stdc++.h> int main() { int J, M; float QJ, QM; int i; scanf( %d , &J); scanf( %d , &M); i = 1; while (1) { J = J - i; if (J < 0) { printf( Vladik n ); break; } i++; M = M - i; if (M < 0) { printf( Valera n ); break; } i++; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file obc_upper.v when simulating
// the core, obc_upper. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module obc_upper(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [7 : 0] addra;
input [1 : 0] dina;
output [1 : 0] douta;
input clkb;
input [0 : 0] web;
input [5 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(2),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(2),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// megafunction wizard: %GPIO Lite Intel FPGA IP v18.0%
// GENERATION: XML
// alt_ddr.v
// Generated using ACDS version 18.0 614
`timescale 1 ps / 1 ps
module alt_ddr (
input wire outclock, // outclock.export
input wire [1:0] din, // din.export
output wire [0:0] pad_out // pad_out.export
);
altera_gpio_lite #(
.PIN_TYPE ("output"),
.SIZE (1),
.REGISTER_MODE ("ddr"),
.BUFFER_TYPE ("single-ended"),
.ASYNC_MODE ("none"),
.SYNC_MODE ("none"),
.BUS_HOLD ("false"),
.OPEN_DRAIN_OUTPUT ("false"),
.ENABLE_OE_PORT ("false"),
.ENABLE_NSLEEP_PORT ("false"),
.ENABLE_CLOCK_ENA_PORT ("false"),
.SET_REGISTER_OUTPUTS_HIGH ("false"),
.INVERT_OUTPUT ("false"),
.INVERT_INPUT_CLOCK ("false"),
.USE_ONE_REG_TO_DRIVE_OE ("false"),
.USE_DDIO_REG_TO_DRIVE_OE ("false"),
.USE_ADVANCED_DDR_FEATURES ("false"),
.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
.ENABLE_OE_HALF_CYCLE_DELAY ("true"),
.INVERT_CLKDIV_INPUT_CLOCK ("false"),
.ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
.ENABLE_HR_CLOCK ("false"),
.INVERT_OUTPUT_CLOCK ("false"),
.INVERT_OE_INCLOCK ("false"),
.ENABLE_PHASE_DETECTOR_FOR_CK ("false")
) alt_ddr_inst (
.outclock (outclock), // outclock.export
.din (din), // din.export
.pad_out (pad_out), // pad_out.export
.outclocken (1'b1), // (terminated)
.inclock (1'b0), // (terminated)
.inclocken (1'b0), // (terminated)
.fr_clock (), // (terminated)
.hr_clock (), // (terminated)
.invert_hr_clock (1'b0), // (terminated)
.phy_mem_clock (1'b0), // (terminated)
.mimic_clock (), // (terminated)
.dout (), // (terminated)
.pad_io (), // (terminated)
.pad_io_b (), // (terminated)
.pad_in (1'b0), // (terminated)
.pad_in_b (1'b0), // (terminated)
.pad_out_b (), // (terminated)
.aset (1'b0), // (terminated)
.aclr (1'b0), // (terminated)
.sclr (1'b0), // (terminated)
.nsleep (1'b0), // (terminated)
.oe (1'b0) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_gpio_lite" version="18.0" >
// Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
// Retrieval info: <generic name="PIN_TYPE" value="output" />
// Retrieval info: <generic name="SIZE" value="1" />
// Retrieval info: <generic name="gui_true_diff_buf" value="false" />
// Retrieval info: <generic name="gui_pseudo_diff_buf" value="false" />
// Retrieval info: <generic name="gui_bus_hold" value="false" />
// Retrieval info: <generic name="gui_open_drain" value="false" />
// Retrieval info: <generic name="gui_enable_oe_port" value="false" />
// Retrieval info: <generic name="gui_enable_nsleep_port" value="false" />
// Retrieval info: <generic name="gui_io_reg_mode" value="ddr" />
// Retrieval info: <generic name="gui_enable_aclr_port" value="false" />
// Retrieval info: <generic name="gui_enable_aset_port" value="false" />
// Retrieval info: <generic name="gui_enable_sclr_port" value="false" />
// Retrieval info: <generic name="gui_set_registers_to_power_up_high" value="false" />
// Retrieval info: <generic name="gui_clock_enable" value="false" />
// Retrieval info: <generic name="gui_invert_output" value="false" />
// Retrieval info: <generic name="gui_invert_input_clock" value="false" />
// Retrieval info: <generic name="gui_use_register_to_drive_obuf_oe" value="false" />
// Retrieval info: <generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
// Retrieval info: <generic name="gui_use_advanced_ddr_features" value="false" />
// Retrieval info: <generic name="gui_enable_phase_detector_for_ck" value="false" />
// Retrieval info: <generic name="gui_enable_oe_half_cycle_delay" value="true" />
// Retrieval info: <generic name="gui_enable_hr_clock" value="false" />
// Retrieval info: <generic name="gui_enable_invert_hr_clock_port" value="false" />
// Retrieval info: <generic name="gui_invert_clkdiv_input_clock" value="false" />
// Retrieval info: <generic name="gui_invert_output_clock" value="false" />
// Retrieval info: <generic name="gui_invert_oe_inclock" value="false" />
// Retrieval info: <generic name="gui_use_hardened_ddio_input_registers" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : alt_ddr.vo
// RELATED_FILES: alt_ddr.v, altera_gpio_lite.sv
|
#include <bits/stdc++.h> using namespace std; const int MAX_VALUE = 32768; struct Tokenizer { string input; int at; void tokenize(const string& s) { input = s + @ ; at = 0; token = ; } char nextChar() { return input[at]; } char nextNoneSpace() { while (nextChar() == ) skipChar(); return nextChar(); } void skipChar() { ++at; } string token; string nextToken() { if (!token.empty()) return token; char ch = nextNoneSpace(); if (isdigit(ch)) { while (isdigit(nextChar())) { token += nextChar(); skipChar(); } } else if (isalpha(ch)) { while (isalpha(nextChar())) { token += nextChar(); skipChar(); } } else { token = nextChar(); skipChar(); } return token; } void skipToken() { token = ; } bool hasMoreTokens() { return at < input.size(); } }; Tokenizer tokenizer; vector<string> tokens; string input; int what; int n; void readInput() { cin >> what; string line; input = ; while (getline(cin, line)) input += line; } void tokenizeInput() { tokenizer.tokenize(input); while (tokenizer.hasMoreTokens()) { tokens.push_back(tokenizer.nextToken()); tokenizer.skipToken(); } } int result[MAX_VALUE]; int at; const string& nextToken() { return tokens[at]; } void skipToken() { ++at; } int parseFunction(int); int parseOperatorSequence(); int parseOperator(); int parseLogicalExpr(); int parseArithmExpr(); int parseSum(); int parseProduct(); int parseMultiplier(); int parseNumber(); void eat(const string& s) { skipToken(); } int parseFunction() { eat( int ); eat( f ); eat( ( ); eat( int ); eat( n ); eat( ) ); eat( { ); int e = parseOperatorSequence(); return e; } int parseOperatorSequence() { while (nextToken() != } ) { int e = parseOperator(); if (e != -1) return e; } return -1; } int parseOperator() { if (nextToken() == return ) { skipToken(); return parseArithmExpr(); } else { eat( if ); eat( ( ); int ok = parseLogicalExpr(); eat( ) ); eat( return ); int res = parseArithmExpr(); eat( ; ); if (ok) return res; else return -1; } } int parseLogicalExpr() { int a = parseArithmExpr(); string token = nextToken(); if (token == > ) { eat( > ); int b = parseArithmExpr(); return a > b; } else if (token == < ) { eat( < ); int b = parseArithmExpr(); return a < b; } else { eat( = ); eat( = ); int b = parseArithmExpr(); return a == b; } } inline int moduleAdd(int a, int b) { return (a + b) % MAX_VALUE; } inline int moduleMinus(int a, int b) { a -= b; if (a < 0) a += MAX_VALUE; return a; } inline int moduleMult(int a, int b) { return (a * b) % MAX_VALUE; } inline int moduleDiv(int a, int b) { if (!b) return -1; return a / b; } int parseArithmExpr() { return parseSum(); } int parseSum() { int e = parseProduct(); while (nextToken() == + || nextToken() == - ) { string token = nextToken(); skipToken(); if (token == + ) e = moduleAdd(e, parseProduct()); else e = moduleMinus(e, parseProduct()); } return e; } int parseProduct() { int e = parseMultiplier(); while (nextToken() == * || nextToken() == / ) { string token = nextToken(); skipToken(); if (token == * ) e = moduleMult(e, parseMultiplier()); else e = moduleDiv(e, parseMultiplier()); } return e; } int parseMultiplier() { if (nextToken() == n ) { skipToken(); return n; } else if (nextToken() == f ) { eat( f ); eat( ( ); int arg = parseArithmExpr(); eat( ) ); return result[arg]; } else { istringstream iss(nextToken()); skipToken(); int num; iss >> num; return num; } } int main() { readInput(); tokenizeInput(); int ans = -1; for (int i = 0; i < MAX_VALUE; i++) { at = 0; n = i; result[i] = parseFunction(); if (result[i] == what) ans = i; } printf( %d n , ans); }
|
`define ADDER_WIDTH 032
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = # (mintypmax_expression) boolean_exp ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
# 3; /* Wait till here to verify didn't see 2ns delay! */
if(value1 !== 4'hx)
$display("FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \n");
#12 ;
if(value1 != 4'b1)
$display("FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = # (2:10:17) 1'b1 && 1'b1 ;
endmodule
|
//#############################################################################
//# Function: 5:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux5 #(parameter DW = 1 ) // width of mux
(
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0]);
endmodule // mux5
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int arr[1009]; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &arr[i]); int x1, y1, x2, y2; for (int i = 0; i < n - 1; i++) { x1 = min(arr[i], arr[i + 1]); y1 = max(arr[i], arr[i + 1]); for (int j = i + 1; j < n - 1; j++) { x2 = min(arr[j], arr[j + 1]); y2 = max(arr[j], arr[j + 1]); if ((x1 < x2 && y1 > x2 && y2 > y1) || (x2 < x1 && y2 > x1 && y1 > y2)) { printf( yes n ); return 0; } } } printf( no n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[10010]; int B[10010]; bool check(int st, int ed) { int mx = st; for (int i = st; i <= ed; i++) { if (A[i] > A[mx]) { mx = i; } if (A[i] == A[mx]) { if (st <= i - 1 && A[i - 1] < A[i]) mx = i; if (i + 1 <= ed && A[i + 1] < A[i]) mx = i; } } bool can = false; if (st <= mx - 1 && A[mx - 1] < A[mx]) can = true; if (mx + 1 <= ed && A[mx + 1] < A[mx]) can = true; return can || (st == ed); } void consume(int st, int ed) { int mx = st; for (int i = st; i <= ed; i++) { if (A[i] > A[mx]) { mx = i; } if (A[i] == A[mx]) { if (st <= i - 1 && A[i - 1] < A[i]) mx = i; if (i + 1 <= ed && A[i + 1] < A[i]) mx = i; } } if (mx + 1 <= ed && A[mx + 1] < A[mx]) { for (int i = mx + 1; i <= ed; i++) { printf( %d R n , mx + 1); } for (int j = mx - 1; j >= st; j--) { printf( %d L n , j + 1 + 1); } } else if (st <= mx - 1 && A[mx - 1] < A[mx]) { for (int j = mx - 1; j >= st; j--) { printf( %d L n , j + 1 + 1); } for (int i = mx + 1; i <= ed; i++) { printf( %d R n , st + 1); } } } int main() { for (;;) { int N; if (scanf( %d , &N) == EOF) break; for (int i = 0; i < N; i++) { scanf( %d , &A[i]); } int M; scanf( %d , &M); for (int i = 0; i < M; i++) { scanf( %d , &B[i]); } int j = 0; int sum = 0; bool possible = true; vector<int> part; part.push_back(-1); for (int i = 0; i < N; i++) { sum += A[i]; if (j < M && sum == B[j]) { possible &= check(part.back() + 1, i); part.push_back(i); if (!possible) break; sum = 0; j += 1; } } if (sum > 0 || j < M) possible = false; if (possible) { printf( YES n ); for (int i = part.size() - 2; i >= 0; i--) { consume(part[i] + 1, part[i + 1]); } } else { printf( NO n ); } } }
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#include <bits/stdc++.h> using namespace std; const int N = 1000 * 100 + 10; int par[N], n, m, c; unordered_map<int, int> adj[N]; unordered_set<int> adj1[N]; int getPar(int root) { return par[root] == par[par[root]] ? par[root] : par[root] = getPar(par[root]); } void Union(int v, int u) { v = getPar(v), u = getPar(u); if (v == u) return; if (adj1[v].size() < adj1[u].size()) swap(v, u); par[u] = par[v]; for (auto it : adj1[u]) adj1[v].insert(it); } void add(int v, int u, int c) { if (adj[u][c]) Union(v, adj[u][c]); if (adj[v][c]) Union(u, adj[v][c]); int pv = getPar(v), pu = getPar(u); adj[v][c] = pu, adj[u][c] = pv; adj1[pv].insert(u), adj1[pu].insert(v); } bool check(int v, int u) { int pv = getPar(v), pu = getPar(u); return pv == pu || adj1[pv].count(u); } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int Q; cin >> n >> m >> c >> Q; for (int i = 1; i <= n; i++) par[i] = i; for (int i = 1, v, u, z; i <= m; i++) { cin >> v >> u >> z; add(v, u, z); } while (Q--) { char c; int x, y, z; cin >> c >> x >> y; if (c == ? ) cout << (check(x, y) ? Yes : No ) << n ; else { cin >> z; add(x, y, z); } } return 0; }
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// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Sun Aug 28 08:25:18 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/data_compression/16-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
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#include <bits/stdc++.h> using namespace std; inline long long read() { char ch = getchar(); long long x = 0; int op = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) op = -1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return x * op; } inline void write(long long a) { if (a < 0) putchar( - ), a = -a; if (a >= 10) write(a / 10); putchar( 0 + a % 10); } const int N = 1010; int n, m, k; long long a[N][N], s1[N][N], s2[N][N]; int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) a[i][j] = a[i - 1][j] + a[i][j - 1] - a[i - 1][j - 1] + read(); for (int i = 1; i <= n; i++) for (int j = 0; j <= m; j++) { s1[i][j] = s1[i - 1][j + 1] + a[i][j] - ((i - k >= 0 && j + k <= m) ? a[i - k][j + k] : 0); if (j) s2[i][j] = s2[i - 1][j - 1] + a[i][j] - ((i - k >= 0 && j - k >= 0) ? a[i - k][j - k] : 0); } long long mx = -1, x, y; for (int i = k; i <= n - k + 1; i++) for (int j = k; j <= m - k + 1; j++) { long long tmp = s1[i + k - 1][j] + s1[i - 1][j - k] - s2[i - 1][j + k - 1] - s2[i + k - 1][j - 1]; if (tmp > mx) { mx = tmp; x = i; y = j; } } write(x); putchar( ); write(y); return 0; }
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#include <bits/stdc++.h> using namespace std; int n; char s[50001]; int last[26][50001]; int best[51][50001]; bool prv[51][50001]; void print(int i, int j, int k) { int len = 2 * i + (k != -1 ? 1 : 0); char ans[101]; ans[len] = 0 ; if (k != -1) ans[i] = s[k]; while (j != 0) { if (!prv[i][j]) { --j; continue; } --i, --j; ans[i] = ans[len - i - 1] = s[j]; } printf( %s n , ans); } void run(int casenr) { scanf( %s , s); n = strlen(s); memset(last, -1, sizeof(last)); for (int j = (0); j < (n); ++j) { int x = s[j] - a ; for (int xx = (0); xx < (26); ++xx) last[xx][j + 1] = last[xx][j]; last[x][j + 1] = j; } memset(best, -1, sizeof(best)); best[0][0] = n; prv[0][0] = true; for (int i = (0); i < (50); ++i) for (int j = (0); j < (n); ++j) if (best[i][j] != -1) { if (j + 1 <= best[i][j] && best[i][j] > best[i][j + 1]) { best[i][j + 1] = best[i][j]; prv[i][j + 1] = false; } int x = s[j] - a ; if (last[x][best[i][j]] != -1 && last[x][best[i][j]] >= j + 1 && last[x][best[i][j]] > best[i + 1][j + 1]) { best[i + 1][j + 1] = last[x][best[i][j]]; prv[i + 1][j + 1] = true; } } for (int i = 50; i >= 0; --i) { if (i != 50) for (int j = (0); j < (n); ++j) if (best[i][j] != -1 && j < best[i][j]) { print(i, j, j); return; } for (int j = (0); j < (n); ++j) if (best[i][j] != -1) { print(i, j, -1); return; } } assert(false); } int main() { run(1); return 0; }
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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fast_spi_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 4'b0001
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire SCLK,
input wire SDI,
input wire SEN,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
fast_spi_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER)
) i_fast_spi_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SCLK(SCLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
endmodule
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#include <bits/stdc++.h> const int oo = 1073741819; using namespace std; int f[200][500], n, t[500], w[500]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> t[i] >> w[i]; memset(f, 61, sizeof(f)); f[0][0] = 0; for (int i = 1; i <= n; i++) for (int j = 0; j <= i * 2; j++) { if (j >= t[i]) f[i][j] = min(f[i][j], f[i - 1][j - t[i]]); f[i][j] = min(f[i][j], f[i - 1][j] + w[i]); } int ans = 1073741819; for (int j = 0; j <= n * 2; j++) if (f[n][j] <= j) ans = min(ans, j); cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long m); long long modInverse(long long n, long long m); long long nCr(long long n, long long r, long long m); long long ceiling(long long x, long long y); bool sortbyth(const tuple<long long, int, int>& a, const tuple<long long, int, int>& b) { if (get<0>(a) != get<0>(b)) return get<0>(a) > get<0>(b); else return get<1>(a) < get<1>(b); } int dx[] = {-1, -1, -1, 0, 1, 1, 1, 0}; int dy[] = {-1, 0, 1, 1, 1, 0, -1, -1}; void aksayushx() { string s; cin >> s; int n = s.length(); stack<pair<int, int>> st; for (int i = 0; i < n; i++) { if (s[i] == 0 && (!st.empty() && st.top().first == 1 )) st.pop(); else st.push({s[i], i}); } while (!st.empty()) { s[st.top().second] = 0 ; st.pop(); } cout << s << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) aksayushx(); return 0; } long long power(long long x, long long y, long long m) { long long res = 1; x = x % m; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % m; y = y >> 1; x = (x * x) % m; } return res; } long long modInverse(long long n, long long m) { return power(n, m - 2, m); } long long ceiling(long long x, long long y) { return (x + y - 1) / y; }
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#include <bits/stdc++.h> using namespace std; int main() { long int n, x, y, i, j; long double sum1 = 0, sum2 = 0, mini, maxi, p, z; cin >> n >> x >> y; long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); mini = min(x, y); maxi = max(x, y); p = mini; j = 0; while (mini--) { sum1 = sum1 + a[n - 1 - j]; j++; } z = maxi; while (maxi--) { sum2 = sum2 + a[n - 1 - j]; j++; } cout << fixed << setprecision(12) << sum1 / p + sum2 / z; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { if (i >= (m - n % m)) cout << n / m + 1 << ; else cout << n / m << ; } return 0; }
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//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cabac_cu_binari_intra_luma_mode.v
// Author : chewein
// Created : 2014-9-11
// Description : binarization an cu , cu size is 8x8 , 16x16 , 32x32 64x64
//-----------------------------------------------------------------------------------------------------------------------------
`include"enc_defines.v"
module cabac_cu_binari_intra_luma_mode(
// input
luma_curr_mode_i ,
luma_left_mode_i ,
luma_top_mode_i ,
//output
ctx_pair_luma_mode_0_o ,
ctx_pair_luma_mode_1_o
);
//-----------------------------------------------------------------------------------------------------------------------------
//
// input signals and output signals
//
//-----------------------------------------------------------------------------------------------------------------------------
input [5:0] luma_curr_mode_i ;
input [5:0] luma_left_mode_i ;
input [5:0] luma_top_mode_i ;
output [10:0] ctx_pair_luma_mode_0_o ;
output [10:0] ctx_pair_luma_mode_1_o ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// reg and wire signals declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [5:0] preds_0_r , preds_1_r , preds_2_r ;
reg [1:0] pred_idx_r ;
wire preds_0_le_1_w ,preds_0_le_2_w ,preds_1_le_2_w ;
reg [5:0] preds_0_sort_r ,preds_1_sort_r ,preds_2_sort_r ;
wire [5:0] luma_curr_mode_minus1_w ;
wire [5:0] luma_curr_mode_minus2_w ;
wire [5:0] luma_curr_mode_minus3_w ;
reg [5:0] luma_mode_dir_r ;
// calculation prediction candidates : preds_0_r ,preds_1_r ,preds_2_r
always @* begin
if(luma_top_mode_i == luma_left_mode_i) begin
if(luma_left_mode_i[5:1]) begin // >6'd1
preds_0_r = luma_left_mode_i ;
preds_1_r = ((luma_left_mode_i + 6'd29)&7'd31) + 6'd2 ;
preds_2_r = ((luma_left_mode_i - 6'd1 )&7'd31) + 6'd2 ;
end
else begin
preds_0_r = 6'd0 ;
preds_1_r = 6'd1 ;
preds_2_r = 6'd26 ;
end
end
else begin
if(luma_left_mode_i && luma_top_mode_i) begin
preds_0_r = luma_left_mode_i ;
preds_1_r = luma_top_mode_i ;
preds_2_r = 6'd0 ;
end
else begin
preds_0_r = luma_left_mode_i ;
preds_1_r = luma_top_mode_i ;
preds_2_r = (luma_left_mode_i + luma_top_mode_i)<7'd2 ? 6'd26 :6'd1 ;
end
end
end
// most probably candidates : pred_idx_r
always @* begin
if(luma_curr_mode_i == preds_2_r)
pred_idx_r = 2'd2 ;
else if(luma_curr_mode_i == preds_1_r)
pred_idx_r = 2'd1 ;
else if(luma_curr_mode_i == preds_0_r)
pred_idx_r = 2'd0 ;
else
pred_idx_r = 2'd3 ;
end
// prediction candidates resorting
assign preds_0_le_1_w = preds_0_r < preds_1_r ;
assign preds_0_le_2_w = preds_0_r < preds_2_r ;
assign preds_1_le_2_w = preds_1_r < preds_2_r ;
always @* begin
if(preds_0_le_1_w && preds_0_le_2_w && preds_1_le_2_w) begin
preds_0_sort_r = preds_0_r;
preds_1_sort_r = preds_1_r;
preds_2_sort_r = preds_2_r;
end
else if(preds_0_le_1_w && preds_0_le_2_w && (!preds_1_le_2_w) )begin
preds_0_sort_r = preds_0_r;
preds_1_sort_r = preds_2_r;
preds_2_sort_r = preds_1_r;
end
else if(preds_0_le_1_w && (!preds_0_le_2_w) )begin
preds_0_sort_r = preds_2_r;
preds_1_sort_r = preds_0_r;
preds_2_sort_r = preds_1_r;
end
else if((!preds_0_le_1_w) && preds_0_le_2_w) begin
preds_0_sort_r = preds_1_r;
preds_1_sort_r = preds_0_r;
preds_2_sort_r = preds_2_r;
end
else if( (!preds_0_le_1_w) && (!preds_0_le_2_w) && preds_1_le_2_w) begin
preds_0_sort_r = preds_1_r;
preds_1_sort_r = preds_2_r;
preds_2_sort_r = preds_0_r;
end
else begin
preds_0_sort_r = preds_2_r;
preds_1_sort_r = preds_1_r;
preds_2_sort_r = preds_0_r;
end
end
// calculation luma_mode_dir_r : final modified luma mode
assign luma_curr_mode_minus1_w = luma_curr_mode_i - 6'd1 ;
assign luma_curr_mode_minus2_w = luma_curr_mode_i - 6'd2 ;
assign luma_curr_mode_minus3_w = luma_curr_mode_i - 6'd3 ;
always @* begin
if(luma_curr_mode_i>preds_2_sort_r) begin
if(luma_curr_mode_minus1_w>preds_1_sort_r) begin
if(luma_curr_mode_minus2_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus3_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
end
else begin
if(luma_curr_mode_minus1_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
end
end
else begin
if(luma_curr_mode_i>preds_1_sort_r) begin
if(luma_curr_mode_minus1_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
end
else begin
if(luma_curr_mode_i>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_i ;
end
end
end
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// output signals
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [8:0] bin_string_luma_mode_r ;
always @* begin
case(pred_idx_r)
2'd0: bin_string_luma_mode_r = {3'b001,1'b1,3'b000,1'b0, 1'b0} ; // 2 bins = 1bin regular + 1bypass
2'd1: bin_string_luma_mode_r = {3'b010,1'b1,3'b000,1'b1, 1'b0} ; // 3 bins = 1bin regular + 2bypass
2'd2: bin_string_luma_mode_r = {3'b010,1'b1,3'b000,1'b1, 1'b1} ; // 3 bins = 1bin regular + 2bypass
2'd3: bin_string_luma_mode_r = {3'b101,1'b0, luma_mode_dir_r[4:0]} ; // 6 bins = 1bin regular + 5bypass
default: bin_string_luma_mode_r = 9'd0;
endcase
end
// coding_mode:0:regular mode,1:invalid,2:bypass mode,3:terminal mode
// regular:{2'b01, bin, bank_num,addr_idx} {2,1,3,5}
// bypass :{2'b10,1resverd,bins_num,bin_string} {2,1resverd,3,5}
assign ctx_pair_luma_mode_0_o = {2'b00,bin_string_luma_mode_r[5] ,3'd0, 5'd30};
assign ctx_pair_luma_mode_1_o = {2'b10,1'b0,bin_string_luma_mode_r[8:6],bin_string_luma_mode_r[4:0]};
endmodule
|
/*
Filename: TopModule.v
Author: Duane Niles, Jason Thweatt, Danny Dutton
Date: 1 April 2015
Version: 2
Description: Top-Level module for synthesis.
Updated for use on the DE1-SoC platform.
*/
module TopModule(CLOCK_50, SW, KEY, HEX3, HEX2, HEX1, HEX0);
input CLOCK_50;
input [5:0] SW;
input [1:0] KEY;
output [0:6] HEX3, HEX2, HEX1, HEX0; // 7-segment display driver interface
// READ PAGE 26 OF THE MANUAL TO UNDERSTAND WHY THE VECTOR LOOKS LIKE THIS.
// NO, REALLY. GO READ IT. YOU'LL NEED IT ANYWAY.
wire enable;
wire [15:0] hexDigits;
// The dot notation represents a "named assignment" - the dotted names of the signals in the module declarations
// correspond to the signals in the top-level module that are enclosed in parentheses.
// This notation helps a reader to make clear associations between signals in a module and the ports of an
// instance of some other module.
keypressed K1 (.clock(CLOCK_50), // 50 MHz FPGA Clock
.reset(KEY[0]), // Master Reset - Pushbutton Key 0
.enable_in(KEY[1]), // Enable - Pushbutton Key 1
.enable_out(enable)); // Connect to the enable input port of the counter.
counter16bit C1 (.clock(CLOCK_50), // 50 MHz FPGA Clock
.enable(enable), // Driven by the enable_out port from the keypressed FSM
.clear(KEY[0]), // Master Reset - Pushbutton key 0
.disp(SW[5]), // Disp - DIP switch 5
.dir(SW[4]), // Dir - DIP switch 2
.countValue(SW[3:0]), // countValue - DIP switches (3:0)
.outputValue(hexDigits)); // hexDigits - Connect to the seven-segment displays
// INSTANTIATE FOUR INSTANCES OF YOUR 7-SEGMENT DISPLAY DRIVER.
// EACH ONE SHOULD ACCEPT A FOUR-BIT VALUE THAT CORRESPONDS TO ONE HEX DIGIT OF THE COUNTER VALUE.
// THE OUTPUTS OF THE DISPLAY DRIVERS SHOULD CORRESPOND TO A SET OF DRIVERS FOR THE 7-SEGMENT DISPLAYS.
// FOLLOW THE "NAMED ASSIGNMENT" APPROACH USED IN KEYPRESSED AND COUNTER16BIT.
sevensegdecoder_always S0 (.digit(hexDigits[3:0]),
.drivers(HEX0));
sevensegdecoder_always S1 (.digit(hexDigits[7:4]),
.drivers(HEX1));
sevensegdecoder_always S2 (.digit(hexDigits[11:8]),
.drivers(HEX2));
sevensegdecoder_always S3 (.digit(hexDigits[15:12]),
.drivers(HEX3));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300005, M = 25; const long long p = 998244353ll; inline long long expo(long long a, int b = 998244351) { long long c = 1ll; while (b) { if (b & 1) c = c * a % p; b >>= 1; a = a * a % p; } return c; } long long FAC[N], IFA[N]; inline long long comb(int a, int b) { return (b < 0 || b > a) ? 0ll : (FAC[a] * (IFA[b] * IFA[a - b] % p) % p); } vector<int> L[N], R[N]; int I[N], C[M << 1]; long long E[M], ss; inline void dfs(int m, long long a, int w = 1) { if (m) { dfs(m - 1, a, w); if ((ss & E[m]) == E[m]) dfs(m - 1, a & (~E[m]), -w); } else { C[__builtin_popcountll(a)] += w; } } int main() { int n, m, i, a, b, c = 0, f = 0, c0 = 0, c1 = 0; long long ans = 0ll, s1 = 0ll; vector<int>::iterator d; scanf( %d%d , &n, &m); FAC[0] = 1ll; for (i = (1); i <= (n); ++i) FAC[i] = FAC[i - 1] * i % p; IFA[n] = expo(FAC[n]); for (i = (n); i >= (1); --i) IFA[i - 1] = IFA[i] * i % p; for (i = (1); i <= (n); ++i) { scanf( %d%d , &a, &b); L[a].push_back(i); R[b].push_back(i); } for (i = (1); i <= (m); ++i) { scanf( %d%d , &a, &b); if (!I[a]) I[a] = ++c; if (!I[b]) I[b] = ++c; E[i] = (1ll << I[a]) | (1ll << I[b]); } C[0] = 1; for (i = (1); i <= (n); ++i) { for (d = L[i].begin(); d != L[i].end(); ++d) { a = *d; if (I[a]) { ++c1; f = 1; s1 |= 1ll << I[a]; } ++c0; } if (f) { for (a = (0); a <= (c1); ++a) C[a] = 0; ss = s1; dfs(m, s1); f = 0; } for (a = (0); a <= (c1); ++a) ans = (ans + (C[c1 - a] + p) * comb(c0 - a, i - a)) % p; for (d = R[i].begin(); d != R[i].end(); ++d) { a = *d; if (I[a]) { --c1; f = 1; s1 ^= 1ll << I[a]; } --c0; } } printf( %lld , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_1_V
`define SKY130_FD_SC_MS__SDFBBP_1_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n; cin >> n; pair<long long int, long long int> a[n]; for (long long int i = 0; i < n; i++) cin >> a[i].first >> a[i].second; sort(a, a + n); long long int x1 = -1, y1 = -1, x2 = -1, y2 = -1; for (long long int i = 0; i < n; i++) { long long int x = a[i].first, y = a[i].second; if (x > y1) { x1 = x, y1 = y; continue; } if (x > y2) { x2 = x, y2 = y; continue; } return cout << NO , 0; } cout << YES ; }
|
Require Import Coq.Lists.List.
Require Import Coq.Sets.Ensembles.
Import ListNotations.
From OakIFC Require Import
Lattice
Parameters
GenericMap
Lattice
Events
State.
From RecordUpdate Require Import RecordSet.
Import RecordSetNotations.
(* Ensembles don't have implicit type params and this line fixes that *)
Arguments Ensembles.Empty_set{U}.
(* TODO fix comments to also talk about low projections *)
(*
This file defines "low equivalence relations" over various pieces of state.
These are auxiliary definitions for defining the security condition.
A low-equivalence relation holds for a particular security level ell, and a pair
of state objects s1, s2 whenever they "appear the same" from the perspective of
an observer at the level ell. For example, if the state objects are channels,
an observer with security label "Alice" can see the contents of channels with
label "Alice" (or any other ell s.t. ell flowsTo Alice), so channels with such
labels are related if their contents are equal. By contrast, Alice should not be
able to see channels labeled "Bob", so _any_ pair of channels with this label
are related even if their contents differ.
*)
Definition trace := list (state * event_l).
(*============================================================================
* Low Projections
*===========================================================================*)
Definition low_proj_t {A: Type}: Type := level -> A -> A.
Definition low_proj {A: Type} ell ( labeled_thing: @labeled A) :=
match labeled_thing with
| Labeled _ o ell' => if( ell' <<? ell )
then labeled_thing
else Labeled A None top
end.
(*
Importantly, the label of the secret thing is NOT ell'
but instead the top of the information flow lattice
(secret, untrusted) which means that in this formulation,
labels are not completely public. Instead, an observer at level
ell can see:
- whether the label of an object flows to ell, for any object.
- the precise label of the object if its label does flow to ell.
Putting it another way, the label ell' of a secret object is not observable,
but whether or not (ell' <<L ell) is observable.
This defintion is necessary in order to make the theorem provable while
still supporting dynamic creation of nodes and channels.
Noninterference proofs often rely on theorems that roughly say "when a
secret step is taken, no public state is updated". (In this code, these
theorems often have "unobs" in their names. In the literature these are
sometimes called clearance). To create a node
or channel, a new labeled object appears, which is effectively a "label
change". If labels are public, we can't prove the "unobs" theorems because
because the node/channel creation calls DO create new labels and therefore
do update public state.
By revealing only partial information about labels to an arbitrary
observer, we can show that since secret nodes can only create secret
objects, these label changes in the secret part of the lattice are actually
hidden.
*)
Definition node_low_proj := @low_proj node.
Definition chan_low_proj := @low_proj channel.
Definition event_low_proj := @low_proj event.
Definition node_state_low_proj (ell: level)(ns: node_state): node_state :=
fun id => low_proj ell (ns id).
Definition chan_state_low_proj (ell: level)(cs: chan_state): chan_state :=
fun h => low_proj ell (cs h).
Definition state_low_proj (ell: level)(s: state): state := {|
nodes := node_state_low_proj ell s.(nodes);
chans := chan_state_low_proj ell s.(chans);
|}.
(*============================================================================
* Low Equivalences
*===========================================================================*)
Definition low_eq_t {A: Type}: Type := level -> A -> A -> Prop.
Definition low_eq {A: Type} ell (x: @labeled A) (y: @labeled A) :=
(low_proj ell x) = (low_proj ell y).
Definition node_low_eq := @low_eq node.
Definition chan_low_eq := @low_eq channel.
Definition event_low_eq := @low_eq event.
Definition node_state_low_eq := fun ell ns1 ns2 =>
forall nid, (node_state_low_proj ell ns1) nid = (node_state_low_proj ell ns2) nid.
Definition chan_state_low_eq := fun ell cs1 cs2 =>
forall han, (chan_state_low_proj ell cs1) han = (chan_state_low_proj ell cs2) han.
Definition state_low_eq := fun ell s1 s2 =>
(forall nid, (state_low_proj ell s1).(nodes) nid =
(state_low_proj ell s2).(nodes) nid) /\
(forall han, (state_low_proj ell s1).(chans) han=
(state_low_proj ell s2).(chans) han ).
(*============================================================================
* Trace Low Equivalences
*===========================================================================*)
(* We might need two different definitions of trace low-equivalence
* depending on the top-level security condition *)
(* This is a straightforward definition of trace low-equivalence
Roughly, it says that
t1 =L t2 <-> forall i, t1[i] =L t2[i].
This definition would be useful for a
"possibilistic security condition". A possibilistic security condition
says that two executions look the same from the perspective of an observer
if all _possible behaviors_ look the same if they begin from initial states
that look the same to the observer.
Possibilistic security conditions say that
forall s1 s2 t1,
(s1 =L s2 -> <c, s1> => t1),
exists t2, <c, s2> => t2 /\ t1 =L t2.
In other words there is some way to reach an execution trace
that looks the same beginning from the other state.
Trapeze uses a possibilistic definition of security:
https://pdfs.semanticscholar.org/809b/f2702a765b9e7dba4624a1dbc53af11579db.pdf
See also:
https://www.cs.cornell.edu/andru/papers/csfw03.pdf
and discussion in PossibilisticNI.v
*)
Inductive trace_low_eq: level -> trace -> trace -> Prop :=
| NilEQ ell: trace_low_eq ell [] []
| AddBoth ell xs xe ys ye t1 t2:
trace_low_eq ell t1 t2 ->
event_low_eq ell xe ye ->
state_low_eq ell xs ys ->
trace_low_eq ell ((xs, xe)::t1) ((ys, ye)::t2).
(* An alternative way of specifying security for
concurrent systems is observational determinism, which says
that for any two executions that begin from low-equivalent
initial states, the actual observed behaviors
(by contrast to possibly observed behaviors)
_always_ look the same.
This looks like:
forall s1 s2 t1 t2,
(s1 =L s2) /\
(step_multi s1) => t1 /\
(step_multi s2) => t2 ->
t1 =L t2.
If we write this top-level theorem using the straightforward
definition of trace low-equivalence from above, the security condition
would rule out *some* timing channels that we know our system does not
prevent (so the security condition would not work).
The straightforward security condition would rule out the case where:
- The observer is L
- There is label L' s.t. not (L' flowsTo L)
- A node called Other with Label L' takes more state transitions in one execution to
perform some computation than in the other.
While the "Other" node is executing, it can only affect parts of the system
labeled L' (or higher), so for this part of a single execution, it will
look like a sequence where ... si =L si+1 =L si+2 ... . In other words, the
sub-sequence is low-equivalent. If the observer really can't measure time,
two sequences that differ just in the number of transitions by "Other"
really do look the same.
This definition of trace low-equivalence rules this out by collapsing
adjacent low-equivalent states (called "high stutter") in the traces.
*)
Inductive stut_trace_low_eq: level -> trace -> trace -> Prop :=
| SNilEQ ell: stut_trace_low_eq ell [] []
| SAddBoth ell xs xe ys ye t1 t2:
stut_trace_low_eq ell t1 t2 ->
event_low_eq ell xe ye ->
state_low_eq ell xs ys ->
stut_trace_low_eq ell ((xs, xe)::t1) ((ys, ye)::t2)
| SAddEqR ell xs xe ys ye t1 t2:
stut_trace_low_eq ell t1 ((ys, ye)::t2) ->
event_low_eq ell xe ye ->
state_low_eq ell xs ys ->
stut_trace_low_eq ell t1 ((xs, xe)::(ys, ye)::t2)
| SAddEqL ell xs xe ys ye t1 t2:
stut_trace_low_eq ell ((ys, ye)::t1) t2 ->
event_low_eq ell xe ye ->
state_low_eq ell xs ys ->
stut_trace_low_eq ell ((xs, xe)::t1) ((ys, ye)::t2).
|
module PHYctrl_Slave_MAX10 (
input CLOCK_50_MAX10,
input CLOCK_25_MAX10,
input [3: 0] USER_PB,
output [4: 0] USER_LED,
output [1:0] PMODA_IO,
output ENET_MDC,
inout ENET_MDIO,
// Ethernet A
output ENET0_RESET_N,
output ENET0_GTX_CLK,
input ENET0_TX_CLK,
input ENET0_RX_CLK,
input [3: 0] ENET0_RX_DATA,
input ENET0_RX_DV,
input ENET0_LED_LINK100,
output [3: 0] ENET0_TX_DATA,
output ENET0_TX_EN,
output ENET0_TX_ER,
// Ethernet 1
output ENET1_GTX_CLK,
output ENET1_RESET_N,
input ENET1_TX_CLK,
input ENET1_RX_CLK,
input [3: 0] ENET1_RX_DATA,
input ENET1_RX_DV,
input ENET1_LED_LINK100,
output [3: 0] ENET1_TX_DATA,
output ENET1_TX_EN
);
wire rst;
assign rst = ~USER_PB[3];
assign ENET0_RESET_N = USER_PB[3];
assign ENET1_RESET_N = USER_PB[3];
wire clk_tx0_25;
wire clk_tx1_25;
wire clk_rx0_25;
wire clk_rx1_25;
assign clk_tx0_25 = ENET0_TX_CLK;
assign clk_tx1_25 = ENET1_TX_CLK;
assign clk_rx0_25 = ENET0_RX_CLK;
assign clk_rx1_25 = ENET1_RX_CLK;
/////////////////////////////////////// transmitter mac /////////////////////////////
wire [7:0] TxRamAddr;
wire [7:0] TxData;
//dual port ram for tx, a port for write from higher level, b port for read from txmac
tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins(
//.data_a,
.data_b(TxData),
//.addr_a,
.addr_b(TxRamAddr),
//.we_a,
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(TxData)
);
//////////////////////////////////// receiver mac /////////////////////////////
wire [7:0]RxRamAddr;
wire [7:0]RxData;
wire RxValid;
wire [7:0]readFromRxRam8bit;
//dual port ram for rx, a port for write from rxmac, b port for read from higher level
rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(
.data_a(RxData),
//.data_b,
.addr_a(RxRamAddr),
//.addr_b(SW[7:2]),
.we_a(RxValid),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam8bit)
);
reg [5:0]rx_ram_addr1;
always @ (posedge clk_rx1_25 )
begin
if (rst) begin
rx_ram_addr1 <= 6'b0;
end else if (ENET1_RX_DV)begin
if (rx_ram_addr1 < 6'b111110 )
rx_ram_addr1 <= rx_ram_addr1 + 1'b1;
end
end
wire [3:0]readFromRxRam;
rx_data_ram rx_data_ram_ins(
.data_a(ENET1_RX_DATA),
//.data_b,
.addr_a(rx_ram_addr1),
// .addr_b(SW[7:2]),
.we_a(ENET1_RX_DV),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam)
);
// generatioon of 100MHz clock
wire Clk_100MHz;
pll_25to100MHz delay_measure_clock
(
.inclk0(CLOCK_25_MAX10),
.areset(rst),
.c0(Clk_100MHz)
);
wire [7:0]LastSlaveIDPlus1;
wire [7:0]SlaveID;
wire [3:0]readSlaveID;
wire [7:0]LogicDelay;
wire [7:0]AveSlaveDelay;
fb_slave_mac fb_slave_mac_ins
(
.MRxClk(clk_rx1_25),
.MTxClk(clk_tx0_25),
.Clk_100MHz(Clk_100MHz),
.MRxDV(ENET1_RX_DV),
.MRxD(ENET1_RX_DATA),
.Reset(rst),
.TxData(TxData),
.inSlaveID(8'd1),
.inLastSlaveIDPlus1(8'd2),
.MTxD_sync2(ENET0_TX_DATA),
.MTxEn_sync2(ENET0_TX_EN),
.RxData(RxData),
.RxValid(RxValid),
.RxRamAddr(RxRamAddr),
.TxRamAddr(TxRamAddr),
.SynchSignal(PMODA_IO[0]),
.SlaveID(SlaveID),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.LogicDelay(LogicDelay),
.AveSlaveDelay(AveSlaveDelay)
/*.FrmCrcError
.CrcError,
.StateIdle,
.StateFFS,
.StatePreamble,
.StateNumb,
.StateSlaveID,
.StateDist,
.StateDelay,
.StateDelayMeas,
.StateDelayDist,
.StateData,
.StateSlaveData,
.StateSlaveCrc,
.StateFrmCrc*/
);
assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];
assign USER_LED[1:0] = readSlaveID[1:0];
////////////////////////////////// MI INTERFACE FOR PORT 0 ///////////////////////////////
wire [31:0] command0;
wire [15:0] command_and0;
wire [3: 0] comm_addr0;
wire [15:0] readData0;
wire [15:0] readDataRam0;
phyInital phyInital_ins0 (
.clk(CLOCK_50_MAX10),
.reset(~USER_PB[0]),
.mdc(ENET_MDC),
.md_inout(ENET_MDIO),
.command(command0),
.command_and(command_and0),
.comm_addr(comm_addr0),
//.ram_read_addr(USER_PB[3:0]),
.iniStart(1'b1),
//.iniEnd(USER_LED[0]),
//.stateout(LEDR[12:0]),
.readDataoutRam(readDataRam0)
//.busy(USER_LED[1]),
//.WCtrlDataStartout(USER_LED[2])
);
phyIniCommand0 pyhIniCommands (
.clk(CLOCK_50_MAX10),
.q(command0),
.addr(comm_addr0)
);
phyIniCommand0_and pyhIniCommands_and (
.clk(CLOCK_50_MAX10),
.q(command_and0),
.addr(comm_addr0)
);
assign USER_LED[3] = ENET0_LED_LINK100;
assign USER_LED[4] = ENET1_LED_LINK100;
///////////////////////////////////////////////////end of MI INTERFACE FOR PORT 1 ///////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; int M; const int MAX = 100001; vector<int> _size, marked, _pow, _ipow; vector<pair<int, int> > adjList[MAX + 1]; int getSize(int u, int p = -1) { _size[u] = 1; for (auto [v, w] : adjList[u]) if (v != p && !marked[v]) _size[u] += getSize(v, u); return _size[u]; } int getCentroid(int u, int p, int n) { for (auto [v, w] : adjList[u]) if (v != p && !marked[v] && _size[v] * 2 > n) return getCentroid(v, u, n); return u; } void add(unordered_map<int, int> &aux, int u, int p, int lvl, int rem) { aux[rem]++; for (auto [v, w] : adjList[u]) if (v != p && !marked[v]) add(aux, v, u, lvl + 1, (int(1LL * w * _pow[lvl] % M) + rem) % M); } void remove(unordered_map<int, int> &aux, int u, int p, int lvl, int rem) { aux[rem]--; for (auto [v, w] : adjList[u]) if (v != p && !marked[v]) remove(aux, v, u, lvl + 1, (int(1LL * w * _pow[lvl] % M) + rem) % M); } long long count(unordered_map<int, int> &aux, int u, int p, int lvl, int rem) { int nxt = int(1LL * _ipow[lvl] * (M - rem) % M); long long ans = aux[nxt]; for (auto [v, w] : adjList[u]) if (v != p && !marked[v]) ans += count(aux, v, u, lvl + 1, (rem * 10LL + w) % M); return ans; } long long solve(int u) { int N = getSize(u); u = getCentroid(u, -1, N); marked[u] = 1; unordered_map<int, int> aux; aux[0] = 1; for (auto [v, w] : adjList[u]) if (!marked[v]) add(aux, v, u, 1, w % M); long long ans = aux[0] - 1; for (auto [v, w] : adjList[u]) if (!marked[v]) { remove(aux, v, u, 1, w % M); ans += count(aux, v, u, 1, w % M); add(aux, v, u, 1, w % M); } aux.clear(); for (auto [v, w] : adjList[u]) if (!marked[v]) ans += solve(v); return ans; } int gcd(int a, int b, int &x, int &y) { if (b == 0) { x = 1; y = 0; return a; } int x1, y1; int d = gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } int getInv() { int x, y; int g = gcd(10, M, x, y); assert(g == 1); return (x % M + M) % M; } int main() { ios_base ::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n >> M; _size = vector<int>(n), _pow = vector<int>(n + 1, 1), _ipow = vector<int>(n + 1, 1), marked = vector<int>(n + 1); _ipow[1] = getInv(); _pow[1] = 10; for (int i = 2; i <= n; i++) { _pow[i] = int(1LL * _pow[i - 1] * 10 % M); _ipow[i] = int(1LL * _ipow[i - 1] * _ipow[1] % M); } for (int i = 0; i < n - 1; i++) { int u, v, w; cin >> u >> v >> w; adjList[u].push_back({v, w}); adjList[v].push_back({u, w}); } cout << solve(0) << n ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:33:05 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_stub.v
// Design : mul8_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module mul8_16(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[7:0],B[15:0],P[15:0]" */;
input CLK;
input [7:0]A;
input [15:0]B;
output [15:0]P;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(0); long long n, h, k; cin >> n >> h >> k; vector<long long> mas(n); for (int i = 0; i < n; i++) cin >> mas[i]; long long time = 0, currVolume = 0; bool have = false; for (int i = 0; i < n; i++) { long long top = mas[i]; if (currVolume + top <= h) currVolume += top; else { time += (currVolume / k); if (currVolume < k) { ++time; currVolume = 0; } currVolume = currVolume % k; if (currVolume + top <= h) { currVolume += top; } else { ++time; currVolume = top; } } } if (currVolume % k != 0) ++time; time += currVolume / k; cout << time; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = 1; while (n > 0) { if (n == 3) { cout << x << << x << << 3 * x << ; break; } else { for (int i = 0; i < (n + 1) / 2; i++) { cout << x << ; } x *= 2; n = n - (n + 1) / 2; } } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1005], b[1005]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n; i++) { scanf( %d , &b[i]); } int ans = 0; for (int i = 0; i < n; i++) { int p = 0; int q = 0; for (int j = i; j < n; j++) { p |= a[j]; q |= b[j]; ans = max(ans, p + q); } } printf( %d n , ans); return 0; }
|
/*
* Copyright (c) 2000 Steve Wilson ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This checks bit select from/to vectors with odd bit arrangements.
*/
module test;
reg [4:1] a;
reg [1:4] b;
integer i;
initial begin
a = 4'b1100;
for (i = 1 ; i <= 4 ; i = i + 1)
b[i] = a[i];
$display("a=%b, b=%b", a, b);
if (b !== 4'b0011) begin
$display("FAILED -- b == %b", b);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[4], b[4], n, m; void f1() { a[0] = 0; b[0] = 1; a[1] = 0; b[1] = m; a[2] = 0; b[2] = 0; a[3] = 0; b[3] = m - 1; } void f2() { b[0] = 0; a[0] = 1; b[1] = 0; a[1] = n; b[2] = 0; a[2] = 0; b[3] = 0; a[3] = n - 1; } void f3() { a[0] = n; b[0] = m; a[1] = 0; b[1] = 0; a[2] = 0; b[2] = m; a[3] = n; b[3] = 0; double x = m, y = n; if (2 * sqrt(x * x + (y - 1) * (y - 1)) > x + sqrt(x * x + y * y)) { a[0] = 1; b[0] = 0; a[1] = n; b[1] = m; a[2] = 0; b[2] = 0; a[3] = n - 1; b[3] = m; } } void f4() { a[0] = n; b[0] = m; a[1] = 0; b[1] = 0; a[2] = n; b[2] = 0; a[3] = 0; b[3] = m; double x = n, y = m; if (2 * sqrt(x * x + (y - 1) * (y - 1)) > x + sqrt(x * x + y * y)) { a[0] = 0; b[0] = 1; a[1] = n; b[1] = m; a[2] = 0; b[2] = 0; a[3] = n; b[3] = m - 1; } } int main() { cin >> n >> m; if (n == 0) f1(); else if (m == 0) f2(); else if (n <= m) f3(); else f4(); for (int i = 0; i < 4; i++) cout << a[i] << << b[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; long long a, b; int main() { ios_base::sync_with_stdio(0); cin >> a >> b; while (true) { v.push_back(b); if (b % 10 == 1) { b--; b /= 10; } else if (b % 2 == 0) { b /= 2; } else { cout << NO n ; return 0; } if (b == a) break; else if (b < a) { cout << NO n ; return 0; } } cout << YES n ; cout << v.size() + 1 << n ; cout << a << ; for (long long i = v.size() - 1; i >= 0; i--) { cout << v[i]; cout << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000000 + 20; int used[MAX_N]; int a[MAX_N]; int n, k; int main() { ios::sync_with_stdio(false); cin >> n >> k; for (int i(0); i < int(n); i++) { int x; cin >> x; ++used[x]; } int sum = 0; for (int i = 0; i <= 1000000; i++) { a[i] = sum; sum += used[i]; } int ans = 0; for (int i = 1; i <= 1000000; i++) { int res = 0, p = min(k, i - 1); for (int j = i; j < 1000001; j += i) { int y = min(1000000, j + p); res += a[y] - a[j] + used[y]; } if (res == n) ans = max(ans, i); } cout << ans << endl; return 0; }
|
/*
* This demonstrates a basic dynamic array
*/
module main;
byte foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; char a[200000], b[200000]; int kmp[200000]; int n, m, i, j, first, curr, val[200000], l; int dyn[200000]; int sum[200000]; int MOD = 1000000007; int main(void) { cin >> b >> a; n = strlen(a); m = strlen(b); kmp[0] = 1; if (n == 1) { for (i = 0; i <= m - 1; i++) { if (a[0] == b[i]) { l++; val[l] = i; } } } else { for (i = 1; i <= n - 1; i++) { j = kmp[i - 1]; while (j < i && a[i] != a[i - j]) j += kmp[i - 1 - j]; if (j == i) { if (a[i] == a[0]) kmp[i] = i; else kmp[i] = i + 1; } else kmp[i] = j; } if (a[0] == b[0]) { first = 0; } else { first = 1; } for (i = 1; i <= m - 1; i++) { while (first < i && b[i] != a[i - first]) first += kmp[i - 1 - first]; if (first == i) { if (b[i] == a[0]) first = i; else first = i + 1; } if (i - first == n - 1) { l++; val[l] = first; first += kmp[n - 1]; } } } val[0] = -1; dyn[m] = 0; sum[m] = 1; for (i = m - 1; i >= 0; i--) { while (l > 1 && val[l - 1] >= i) l--; if (val[l] >= i) { dyn[i] = dyn[i + 1] + sum[val[l] + n]; if (dyn[i] >= MOD) dyn[i] -= MOD; sum[i] = sum[i + 1] + dyn[i] + 1; if (sum[i] >= MOD) sum[i] -= MOD; } else { dyn[i] = 0; sum[i] = sum[i + 1] + 1; } } cout << dyn[0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000; int ans[N], l[N], r[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> l[i]; } for (int i = 0; i < n; ++i) { cin >> r[i]; } for (int k = n; k > 0; --k) { for (int i = 0; i < n; ++i) { if (l[i] == 0 && r[i] == 0 && ans[i] == 0) { ans[i] = k; } } int prefix = 0; for (int i = 0; i < n; ++i) { if (ans[i] == k) { ++prefix; } else if (ans[i] == 0) { l[i] -= prefix; } } int suffix = 0; for (int i = n - 1; i >= 0; --i) { if (ans[i] == k) { ++suffix; } else if (ans[i] == 0) { r[i] -= suffix; } } } if (count(ans, ans + n, 0) == 0) { cout << YES n ; for (int i = 0; i < n; ++i) { cout << ans[i] << ; } cout << n ; } else { cout << NO n ; } }
|
`timescale 1ns/1ps
module test_spi_master;
reg clk;
reg spi_tx_rd_en_256;
reg spi_rx_rd_en_256;
reg spi_rd_rst_256;
reg mode_rd_select_256;
wire sm_rd_sck_256;
wire sm_rd_mosi_256;
wire sm_rd_miso_256;
wire sm_rd_cs_n_256;
wire spi_receive_rd_status_256;
spi_ctrl_reduced #(.DATA_LENGTH(256)) spi_ctrl_reduced_instance_256(
.clk(clk),
.rst_n(spi_rd_rst_256),
.sck(sm_rd_sck_256),
.mosi(sm_rd_mosi_256),
.miso(sm_rd_miso_256),
.cs_n(sm_rd_cs_n_256),
.spi_tx_en(spi_tx_rd_en_256),
.spi_rx_en(spi_rx_rd_en_256),
.mode_select(mode_rd_select_256),
.receive_status(spi_receive_rd_status_256)
);
initial
begin
spi_rd_rst_256 = 1'b0;
spi_tx_rd_en_256 = 1'b1;
spi_rx_rd_en_256 = 1'b1;
mode_rd_select_256 = 1'b0;
clk = 0;
#10 spi_rd_rst_256 = 1;
#100000000
$stop;
end
always begin
//50M HZ about 20ns one cycle
#10 clk = ! clk;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_rpt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_rpt(out18 ,in7 ,in0 ,out16 ,in3 ,in2 ,in6 ,out19 ,in8 ,
in9 ,out15 ,out17 ,in1 ,in4 ,in5 ,out13 ,in10 ,in11 ,in12 ,in13 ,
in19 ,in18 ,in17 ,in16 ,in15 ,out6 ,out7 ,out8 ,out9 ,out10 ,out11
,out12 ,out0 ,out1 ,out2 ,out3 ,out4 ,out5 );
output [1:0] out18 ;
output [1:0] out16 ;
output [1:0] out19 ;
output [1:0] out15 ;
output [1:0] out17 ;
output [1:0] out13 ;
output [1:0] out6 ;
output [1:0] out7 ;
output [1:0] out8 ;
output [1:0] out9 ;
output [1:0] out10 ;
output [1:0] out11 ;
output [1:0] out12 ;
output [8:1] out0 ;
output [8:1] out1 ;
output [8:1] out2 ;
output [8:1] out3 ;
output [1:0] out4 ;
output [1:0] out5 ;
input [1:0] in7 ;
input [8:1] in0 ;
input [8:1] in3 ;
input [8:1] in2 ;
input [1:0] in6 ;
input [1:0] in8 ;
input [1:0] in9 ;
input [8:1] in1 ;
input [1:0] in4 ;
input [1:0] in5 ;
input [1:0] in10 ;
input [1:0] in11 ;
input [1:0] in12 ;
input [1:0] in13 ;
input [1:0] in19 ;
input [1:0] in18 ;
input [1:0] in17 ;
input [1:0] in16 ;
input [1:0] in15 ;
bw_u1_buf_15x I40_0_ (
.z (out19[0] ),
.a (in19[0] ) );
bw_u1_buf_15x I44_0_ (
.z (out13[0] ),
.a (in13[0] ) );
bw_u1_buf_15x I46_4_ (
.z (out3[4] ),
.a (in3[4] ) );
bw_u1_buf_15x I48_0_ (
.z (out15[0] ),
.a (in15[0] ) );
bw_u1_buf_15x I52_0_ (
.z (out9[0] ),
.a (in9[0] ) );
bw_u1_buf_15x I56_0_ (
.z (out7[0] ),
.a (in7[0] ) );
bw_u1_buf_15x I38_1_ (
.z (out1[1] ),
.a (in1[1] ) );
bw_u1_buf_15x I37_3_ (
.z (out2[3] ),
.a (in2[3] ) );
bw_u1_buf_15x I39_7_ (
.z (out0[7] ),
.a (in0[7] ) );
bw_u1_buf_15x I40_1_ (
.z (out19[1] ),
.a (in19[1] ) );
bw_u1_buf_15x I44_1_ (
.z (out13[1] ),
.a (in13[1] ) );
bw_u1_buf_15x I46_5_ (
.z (out3[5] ),
.a (in3[5] ) );
bw_u1_buf_15x I48_1_ (
.z (out15[1] ),
.a (in15[1] ) );
bw_u1_buf_15x I52_1_ (
.z (out9[1] ),
.a (in9[1] ) );
bw_u1_buf_15x I56_1_ (
.z (out7[1] ),
.a (in7[1] ) );
bw_u1_buf_15x I38_2_ (
.z (out1[2] ),
.a (in1[2] ) );
bw_u1_buf_15x I37_4_ (
.z (out2[4] ),
.a (in2[4] ) );
bw_u1_buf_15x I39_8_ (
.z (out0[8] ),
.a (in0[8] ) );
bw_u1_buf_15x I41_0_ (
.z (out18[0] ),
.a (in18[0] ) );
bw_u1_buf_15x I45_0_ (
.z (out12[0] ),
.a (in12[0] ) );
bw_u1_buf_15x I46_6_ (
.z (out3[6] ),
.a (in3[6] ) );
bw_u1_buf_15x I49_0_ (
.z (out11[0] ),
.a (in11[0] ) );
bw_u1_buf_15x I53_0_ (
.z (out5[0] ),
.a (in5[0] ) );
bw_u1_buf_15x I39_1_ (
.z (out0[1] ),
.a (in0[1] ) );
bw_u1_buf_15x I38_3_ (
.z (out1[3] ),
.a (in1[3] ) );
bw_u1_buf_15x I37_5_ (
.z (out2[5] ),
.a (in2[5] ) );
bw_u1_buf_15x I41_1_ (
.z (out18[1] ),
.a (in18[1] ) );
bw_u1_buf_15x I45_1_ (
.z (out12[1] ),
.a (in12[1] ) );
bw_u1_buf_15x I46_7_ (
.z (out3[7] ),
.a (in3[7] ) );
bw_u1_buf_15x I49_1_ (
.z (out11[1] ),
.a (in11[1] ) );
bw_u1_buf_15x I53_1_ (
.z (out5[1] ),
.a (in5[1] ) );
bw_u1_buf_15x I39_2_ (
.z (out0[2] ),
.a (in0[2] ) );
bw_u1_buf_15x I38_4_ (
.z (out1[4] ),
.a (in1[4] ) );
bw_u1_buf_15x I37_6_ (
.z (out2[6] ),
.a (in2[6] ) );
bw_u1_buf_15x I42_0_ (
.z (out16[0] ),
.a (in16[0] ) );
bw_u1_buf_15x I46_8_ (
.z (out3[8] ),
.a (in3[8] ) );
bw_u1_buf_15x I50_0_ (
.z (out10[0] ),
.a (in10[0] ) );
bw_u1_buf_15x I54_0_ (
.z (out4[0] ),
.a (in4[0] ) );
bw_u1_buf_15x I39_3_ (
.z (out0[3] ),
.a (in0[3] ) );
bw_u1_buf_15x I38_5_ (
.z (out1[5] ),
.a (in1[5] ) );
bw_u1_buf_15x I37_7_ (
.z (out2[7] ),
.a (in2[7] ) );
bw_u1_buf_15x I42_1_ (
.z (out16[1] ),
.a (in16[1] ) );
bw_u1_buf_15x I46_1_ (
.z (out3[1] ),
.a (in3[1] ) );
bw_u1_buf_15x I50_1_ (
.z (out10[1] ),
.a (in10[1] ) );
bw_u1_buf_15x I54_1_ (
.z (out4[1] ),
.a (in4[1] ) );
bw_u1_buf_15x I39_4_ (
.z (out0[4] ),
.a (in0[4] ) );
bw_u1_buf_15x I38_6_ (
.z (out1[6] ),
.a (in1[6] ) );
bw_u1_buf_15x I37_8_ (
.z (out2[8] ),
.a (in2[8] ) );
bw_u1_buf_15x I43_0_ (
.z (out17[0] ),
.a (in17[0] ) );
bw_u1_buf_15x I46_2_ (
.z (out3[2] ),
.a (in3[2] ) );
bw_u1_buf_15x I51_0_ (
.z (out8[0] ),
.a (in8[0] ) );
bw_u1_buf_15x I55_0_ (
.z (out6[0] ),
.a (in6[0] ) );
bw_u1_buf_15x I37_1_ (
.z (out2[1] ),
.a (in2[1] ) );
bw_u1_buf_15x I39_5_ (
.z (out0[5] ),
.a (in0[5] ) );
bw_u1_buf_15x I38_7_ (
.z (out1[7] ),
.a (in1[7] ) );
bw_u1_buf_15x I43_1_ (
.z (out17[1] ),
.a (in17[1] ) );
bw_u1_buf_15x I46_3_ (
.z (out3[3] ),
.a (in3[3] ) );
bw_u1_buf_15x I51_1_ (
.z (out8[1] ),
.a (in8[1] ) );
bw_u1_buf_15x I55_1_ (
.z (out6[1] ),
.a (in6[1] ) );
bw_u1_buf_15x I37_2_ (
.z (out2[2] ),
.a (in2[2] ) );
bw_u1_buf_15x I39_6_ (
.z (out0[6] ),
.a (in0[6] ) );
bw_u1_buf_15x I38_8_ (
.z (out1[8] ),
.a (in1[8] ) );
endmodule
|
//----------------------------------------------------------------
//-- Inicializador
//-- (c) BQ. August 2015. Written by Juan Gonzalez (obijuan)
//-- GPL license
//----------------------------------------------------------------
//-- Generacion de una señal escalo (0 -> 1) para inicializar
//-- circuitos digitales
//----------------------------------------------------------------
//-- Version optimizada
//-- Entrada: Señal de reloj
//-- Salida: Señal escalón de inicialización
module init(input wire clk, output ini);
//-- Inicializar la salida a 0 (se pone para que funcione en simulación)
//-- En síntesis siempre estará a cero con independencia del valor que pongamos
reg ini = 0;
//-- En cada flanco de subida se saca un "1" por la salida
always @(posedge(clk))
ini <= 1;
endmodule
/*
//-- Implementacion natural
module init(input wire clk, output wire ini);
wire din;
reg dout = 0;
//-- Registro
always @(posedge(clk))
dout <= din;
//-- Entrada conectadad a 1
assign din = 1;
//-- Conectar la salida
assign ini = dout;
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m, a, b, count = 0; ; cin >> n >> m; while (cin >> a >> b) { if (a == 1 || b == 1) { count++; } } cout << count; } signed main() { long long test = 1; while (test--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; double dp[105][105][105]; void solve(int r, int s, int p) { double _r = 0, _s = 0, _p = 0; for (int i = r; i >= 0; i--) { for (int j = s; j >= 0; j--) { for (int k = p; k >= 0; k--) { double tot = i * j + j * k + k * i; if ((i == 0) && (j == 0) && (k > 0)) _p += dp[i][j][k]; if ((k == 0) && (j == 0) && (i > 0)) _r += dp[i][j][k]; if ((i == 0) && (k == 0) && (s > 0)) _s += dp[i][j][k]; if (tot == 0) continue; if (i > 0) { double t = i * k; dp[i - 1][j][k] += (dp[i][j][k] * t / tot); } if (j > 0) { double t = j * i; dp[i][j - 1][k] += (dp[i][j][k] * t / tot); } if (k > 0) { double t = j * k; dp[i][j][k - 1] += (dp[i][j][k] * t / tot); } } } } printf( %0.9f %0.9f %0.9f n , _r, _s, _p); } int main() { int r, s, p; cin >> r >> s >> p; dp[r][s][p] = 1; solve(r, s, p); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 20; int a[105]; int u[105], res[105]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d , &a[i]); } int pos = a[0], ans = 1; while (ans < m) { if (a[ans] > pos) { if (res[pos] == 0) { if (u[a[ans] - pos]) { puts( -1 ); return 0; } res[pos] = a[ans] - pos; } else { if (a[ans] % n != (res[pos] + pos) % n) { puts( -1 ); return 0; } } u[a[ans] - pos] = 1; } else { if (res[pos] == 0) { if (u[a[ans] + n - pos]) { puts( -1 ); return 0; } res[pos] = a[ans] + n - pos; } else { if (a[ans] % n != (res[pos] + pos) % n) { puts( -1 ); return 0; } } u[a[ans] + n - pos] = 1; } pos = a[ans++]; } for (int i = 1; i <= n; i++) { if (res[i] == 0) { for (int j = 1; j <= n; j++) { if (u[j] == 0) { res[i] = j; u[j] = 1; break; } } } printf( %d , res[i]); } }
|
#include <bits/stdc++.h> int main() { int n, i, j, c = 0, p, q, f = 0; scanf( %d , &n); scanf( %d , &p); int a[p]; for (i = 0; i < p; i++) scanf( %d , &a[i]); scanf( %d , &q); int b[q]; for (i = 0; i < q; i++) scanf( %d , &b[i]); for (i = 1; i <= n; i++) { f = 0; for (j = 0; j < p; j++) { if (a[j] == i) { c++; f++; } } if (f == 0) { for (j = 0; j < q; j++) { if (b[j] == i) { c++; } } } } if (n == c) printf( I become the guy. n ); else printf( Oh, my keyboard! n ); return 0; }
|
// Hybrid PWM / Sigma Delta converter
//
// Uses 5-bit PWM, wrapped within a 10-bit Sigma Delta, with the intention of
// increasing the pulse width, since narrower pulses seem to equate to more noise
module hybrid_pwm_sd
(
input clk,
input n_reset,
input [15:0] din,
output dout
);
reg [4:0] pwmcounter;
reg [4:0] pwmthreshold;
reg [33:0] scaledin;
reg [15:0] sigma;
reg out;
assign dout=out;
always @(posedge clk, negedge n_reset) // FIXME reset logic;
begin
if(!n_reset)
begin
sigma<=16'b00000100_00000000;
pwmthreshold<=5'b10000;
pwmcounter<=5'd0;
scaledin<=34'd0;
end
else
begin
pwmcounter<=pwmcounter+1;
if(pwmcounter==pwmthreshold)
out<=1'b0;
if(pwmcounter==5'b11111) // Update threshold when pwmcounter reaches zero
begin
// Pick a new PWM threshold using a Sigma Delta
scaledin<=33'd134217728 // (1<<(16-5))<<16, offset to keep centre aligned.
+({1'b0,din}*61440); // 30<<(16-5)-1;
sigma<=scaledin[31:16]+{5'b000000,sigma[10:0]}; // Will use previous iteration's scaledin value
pwmthreshold<=sigma[15:11]; // Will lag 2 cycles behind, but shouldn't matter.
out<=1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_4_V
`define SKY130_FD_SC_HDLL__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_4_V
|
module iq_comp (
input clk, RESETn,
input freeze_iqcomp, //Should come from Start Signal FSM, freezes W values when on
input [1:0] op_mode,
input [3:0] Ix, Qx,
input signed [12:0] Wr_in, Wj_in, //Externally supplied W, used when op_mode = EXT_W
output reg signed [3:0] Iy, Qy, //Rotated and compensated IQ
//Debugging signals
output wire settled, //Used to tell MCU to store W values
output reg signed [12:0] Wr, Wj
);
//Declare mode parameters
localparam BYPASS = 2'b00;
localparam INT_W = 2'b01;
localparam EXT_W = 2'b10;
localparam CONT_W = 2'b11; //Not yet implemented. Same as Bypass.
//Convert to signed I,Q
wire signed [3:0] Ix_s;
wire signed [3:0] Qx_s;
//Step value
wire [3:0] M;
//Signals for combinational math
wire signed [12:0] Wr_use;
wire signed [12:0] Wj_use;
reg signed [3:0] I_math;
reg signed [3:0] Q_math;
wire signed [12:0] Wr_math;
wire signed [12:0] Wj_math;
wire signed [25:0] I_math_intermediate1;
wire signed [25:0] Q_math_intermediate1;
wire signed [4:0] I_math_intermediate2;
wire signed [4:0] Q_math_intermediate2;
wire signed [25:0] Ix_s_shifted;
wire signed [25:0] Qx_s_shifted;
assign settled = freeze_iqcomp; //Temporary solution
assign M = 4'd9; //log2(512) = 9, divide by 512 -> arithmetic right shift by 9
assign Ix_s = Ix - 4'd8;
assign Qx_s = Qx - 4'd8;
//Choose W used to compensate
assign Wr_use = (op_mode == INT_W) ? Wr : Wr_in;
assign Wj_use = (op_mode == INT_W) ? Wj : Wj_in;
assign Ix_s_shifted = $signed(Ix_s) <<< M;
assign Qx_s_shifted = $signed(Qx_s) <<< M;
assign I_math_intermediate1 = Ix_s_shifted + $signed(((Wr_use * Ix_s) + (Wj_use * Qx_s)));
assign Q_math_intermediate1 = Qx_s_shifted + $signed(((Wj_use * Ix_s) - (Wr_use * Qx_s)));
assign I_math_intermediate2 = $signed(I_math_intermediate1) >>> M;
assign Q_math_intermediate2 = $signed(Q_math_intermediate1) >>> M;
// assign I_math = Ix_s + $signed($signed(((Wr_use * Ix_s) + (Wj_use * Qx_s))) >>> M);
// assign Q_math = Qx_s + $signed($signed(((Wj_use * Ix_s) - (Wr_use * Qx_s))) >>> M);
always @(*) begin
if($signed(I_math_intermediate2) < $signed(0-5'd8)) begin
I_math = $signed(-4'd8);
end
else if($signed(I_math_intermediate2) > $signed(5'd7)) begin
I_math = $signed(4'd7);
end
else begin
I_math = $signed(I_math_intermediate2);
end
if($signed(Q_math_intermediate2) < $signed(0-5'd8)) begin
Q_math = $signed(-4'd8);
end
else if($signed(Q_math_intermediate2) > $signed(5'd7)) begin
Q_math = $signed(4'd7);
end
else begin
Q_math = $signed(Q_math_intermediate2);
end
end
assign Wr_math = $signed(Wr - ((Iy + Qy) * (Iy - Qy)));
assign Wj_math = $signed(Wj - 2 * Iy * Qy);
always @(posedge clk) begin
if(~RESETn) begin
Iy <= 0;
Qy <= 0;
Wr <= 0;
Wj <= 0;
end else begin
case (op_mode)
BYPASS: begin
Iy <= Ix_s;
Qy <= Qx_s;
Wr <= 0;
Wj <= 0;
end
INT_W: begin
Iy <= I_math;
Qy <= Q_math;
if(freeze_iqcomp) begin
Wr <= Wr;
Wj <= Wj;
end else begin
Wr <= Wr_math;
Wj <= Wj_math;
end
end
EXT_W: begin
Iy <= I_math;
Qy <= Q_math;
Wr <= Wr_use; //Output the same W that's fed in
Wj <= Wj_use; //Output the same W that's fed in
end
CONT_W: begin //Same as BYPASS
Iy <= Ix_s;
Qy <= Qx_s;
Wr <= 0;
Wj <= 0;
end
default : /* default */;
endcase
end
end
endmodule // iq_comp
//Combinational logic for compensation calculation
/*wire signed [18:0] product1;
wire signed [18:0] product2;
wire signed [18:0] product3;
wire signed [18:0] product4;
wire signed [18:0] sum1;
wire signed [18:0] sum2;
wire signed [18:0] shifted1;
wire signed [18:0] shifted2;
assign product1 = Wr_use * Ix_s;
assign product2 = Wj_use * Qx_s;
assign product3 = Wj_use * Ix_s;
assign product4 = Wr_use * Qx_s;
assign sum1 = (product1 + product2);
assign sum2 = (product3 - product4);
assign shifted1 = $signed($signed(sum1) >>> M);
assign shifted2 = $signed($signed(sum2) >>> M);
assign I_math = Ix_s + shifted1;
assign Q_math = Qx_s + shifted2;*/
//Combinational logic for W update calculation
/*wire signed [4:0] IplusQ;
wire signed [4:0] IminusQ;
wire signed [12:0] IQprod1;
wire signed [12:0] IQprod2;
assign IplusQ = Iy + Qy;
assign IminusQ = Iy - Qy;
assign IQprod1 = IplusQ * IminusQ;
assign IQprod2 = 2 * Iy * Qy;
assign Wr_math = Wr - IQprod1;
assign Wj_math = Wj - IQprod2;*/
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ip_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ip_ram (
address,
clock,
data,
wren,
q);
input [14:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../vga.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "24000"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../vga.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "24000"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ip_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module rec_sync #(
parameter DSIZE = 10
) (
input wire reset,
input wire datain,
output reg [DSIZE-1:0] data,
input wire WCLK,
input wire FCLK,
output reg rec_sync_ready,
input wire decoder_err
);
wire BITSLIP_FLAG, BITSLIP_FLAG_FCLK;
flag_domain_crossing bitslip_flag_domain_crossing_inst (
.CLK_A(WCLK),
.CLK_B(FCLK),
.FLAG_IN_CLK_A(BITSLIP_FLAG),
.FLAG_OUT_CLK_B(BITSLIP_FLAG_FCLK)
);
reg [DSIZE-1:0] shift_reg;
always @(posedge FCLK)
shift_reg <= {shift_reg[DSIZE-2:0], datain};
reg [DSIZE-1:0] bitslip_cnt;
initial bitslip_cnt = 1;
always @(posedge FCLK)
if(BITSLIP_FLAG_FCLK)
bitslip_cnt <= {bitslip_cnt[DSIZE-3:0],bitslip_cnt[DSIZE-1:DSIZE-2]};
else
bitslip_cnt <= {bitslip_cnt[DSIZE-2:0],bitslip_cnt[DSIZE-1]};
reg [DSIZE-1:0] fdataout;
always @(posedge FCLK)
if(bitslip_cnt[0])
fdataout <= shift_reg;
else
fdataout <= fdataout;
// reg [DSIZE-1:0] old_data;
always @(posedge WCLK) begin
data <= fdataout;
// old_data <= data;
end
integer wait_cnt;
reg [2:0] state, next_state;
localparam START = 0,
WAIT = 1,
CHECK = 2,
BITSHIFT = 3,
IDLE = 4;
localparam K28_1P = 10'b00_1111_1001,
K28_1N = 10'b11_0000_0110;
always @(posedge WCLK) begin
if (reset) state <= START;
else state <= next_state;
end
always @(state or wait_cnt or decoder_err) begin // or data or old_data
case(state)
START:
next_state = WAIT;
WAIT:
if (wait_cnt == 2)
next_state = CHECK;
else
next_state = WAIT;
CHECK:
if (decoder_err == 1'b0)//(data == K28_1P && old_data == K28_1N) || (data == K28_1N && old_data == K28_1P))
next_state = IDLE;
else
next_state = BITSHIFT;
BITSHIFT:
next_state = WAIT;
IDLE:
if(decoder_err==1'b1)
next_state = WAIT;
else
next_state = IDLE;
default : next_state = START;
endcase
end
assign BITSLIP_FLAG = (state==CHECK && next_state==BITSHIFT);
//assign rec_sync_ready = (state==IDLE);
always @(posedge WCLK)
begin
if (reset) // get D-FF
begin
rec_sync_ready <= 1'b0;
wait_cnt <= 0;
end
else
begin
rec_sync_ready <= rec_sync_ready;
wait_cnt <= 0;
case (next_state)
START:
begin
rec_sync_ready <= 1'b0;
end
WAIT:
begin
if(decoder_err==1'b1)
rec_sync_ready <= 1'b0;
else
rec_sync_ready <= 1'b1;
wait_cnt <= wait_cnt+1;
end
CHECK:
begin
wait_cnt <= wait_cnt+1;
end
BITSHIFT:
begin
rec_sync_ready <= 1'b0;
end
IDLE:
begin
if(decoder_err==1'b1)
rec_sync_ready <= 1'b0;
else
rec_sync_ready <= 1'b1;
end
endcase
end
end
`ifdef SYNTHESIS_NOT
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(WCLK),
.TRIG0({lck, eye_size, REC_SYNC_ERROR, data, BITSLIP_FLAG, state, pa_ready_flag, reset, pll_rst})
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100009; vector<int> edges[N]; vector<int> a; int n, m; int main() { while (cin >> n >> m) { a.clear(); for (int i = 1; i <= n; ++i) edges[i].clear(), a.push_back(i); for (int i = 0; i < m; ++i) { int ac, b; cin >> ac >> b; edges[ac].push_back(b); edges[b].push_back(ac); } bool t = true; int u, v; for (int i = 0; i < 500; ++i) { random_shuffle(a.begin(), a.end()); bool flg = true; for (int j = 0; j < m && flg; ++j) { u = a[j]; v = a[(j + 1) % n]; for (int k = 0; k < edges[u].size(); ++k) if (edges[u][k] == v) flg = false; } if (flg) { for (int j = 0; j < m; ++j) cout << a[j] << << a[(j + 1) % n] << endl; t = false; break; } } if (t) cout << -1 << endl; } return 0; }
|
/*
* Next state calculation for fetch FSM
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_nstate (
input [2:0] state,
input prefix,
input need_modrm,
input need_off,
input need_imm,
input end_seq,
input [5:0] ftype,
input of,
input next_in_opco,
input next_in_exec,
input block,
input div_exc,
input tflm,
input intr,
input iflm,
input nmir,
input iflss,
output [2:0] next_state
);
// Net declarations
parameter opcod_st = 3'h0;
parameter modrm_st = 3'h1;
parameter offse_st = 3'h2;
parameter immed_st = 3'h3;
parameter execu_st = 3'h4;
wire into, end_instr, end_into;
wire [2:0] n_state;
wire intr_iflm;
wire intrs_tni;
// Assignments
assign into = (ftype==6'b111_010);
assign end_into = into ? ~of : end_seq;
assign end_instr = !div_exc && !intrs_tni && end_into && !next_in_exec;
assign intr_iflm = intr & iflm;
assign intrs_tni = (tflm | nmir | intr_iflm) & iflss;
assign n_state = (state == opcod_st) ? (prefix ? opcod_st
: (next_in_opco ? opcod_st
: (need_modrm ? modrm_st
: (need_off ? offse_st
: (need_imm ? immed_st : execu_st)))))
: (state == modrm_st) ? (need_off ? offse_st
: (need_imm ? immed_st : execu_st))
: (state == offse_st) ? (need_imm ? immed_st : execu_st)
: (state == immed_st) ? (execu_st)
/* state == execu_st */ : (end_instr ? opcod_st : execu_st);
assign next_state = block ? state : n_state;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long inf; const double eps = 1e-8; const double pi = acos(-1.0); template <class T> long long chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <class T> long long chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <class T> T sqr(T a) { return a * a; } template <class T> T mmin(T a, T b) { return a < b ? a : b; } template <class T> T mmax(T a, T b) { return a > b ? a : b; } template <class T> T aabs(T a) { return a < 0 ? -a : a; } template <class T> long long dcmp(T a, T b) { return a > b; } template <long long *a> long long cmp_a(long long first, long long second) { return a[first] < a[second]; } struct __INIT__ { __INIT__() { memset(&inf, 0x3f, sizeof(inf)); } } __INIT___; namespace io { const long long SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; long long f, qr; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char first) { *oS++ = first; if (oS == oT) flush(); } template <typename A> inline bool read(A &first) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; else if (c == EOF) return 0; for (first = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) first = first * 10 + (c & 15); first *= f; return 1; } inline bool read(char &first) { while ((first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) == || first == n || first == r ) ; return first != EOF; } inline bool read(char *first) { while ((*first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) == n || *first == || *first == r ) ; if (*first == EOF) return 0; while (!(*first == n || *first == || *first == r )) *(++first) = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); *first = 0; return 1; } template <typename A, typename... B> inline bool read(A &first, B &...second) { return read(first) && read(second...); } template <typename A> inline bool write(A first) { if (!first) putc( 0 ); if (first < 0) putc( - ), first = -first; while (first) qu[++qr] = first % 10 + 0 , first /= 10; while (qr) putc(qu[qr--]); return 0; } inline bool write(char first) { putc(first); return 0; } inline bool write(const char *first) { while (*first) { putc(*first); ++first; } return 0; } inline bool write(char *first) { while (*first) { putc(*first); ++first; } return 0; } template <typename A, typename... B> inline bool write(A first, B... second) { return write(first) || write(second...); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io ::putc; using io ::read; using io ::write; long long a[100005], b[100005], f[100005], g[100005]; long long s[100005], t; long long n, k; struct smt { long long amn, bmn, atg; long long ls, rs; smt *l, *r; smt(long long la, long long ra) { amn = inf; bmn = -inf; atg = 0; ls = la; rs = ra; if (ls == rs) { l = r = 0; } else { long long mid = (ls + rs) >> 1; l = new smt(ls, mid); r = new smt(mid + 1, rs); } } void setg(long long first) { if (ls == rs) { amn = bmn = g[first]; return; } if (first <= l->rs) l->setg(first); else r->setg(first); amn = mmin(l->amn, r->amn); bmn = mmin(l->bmn, r->bmn); } void push_down() { l->atg += atg; l->amn += atg; r->atg += atg; r->amn += atg; atg = 0; } void add(long long la, long long ra, long long w) { if (la <= ls && rs <= ra) { atg += w; amn += w; return; } push_down(); if (la <= l->rs) l->add(la, ra, w); if (ra >= r->ls) r->add(la, ra, w); amn = mmin(l->amn, r->amn); } long long query(long long first, long long rm) { if (ls > rm) return 0; if (bmn - k > first) return 0; if (ls == rs) return ls; push_down(); if (mmin(first, l->amn) >= r->bmn - k) { long long ans = r->query(mmin(first, l->amn), rm); if (ans) return ans; } return l->query(first, rm); } }; smt *rt; signed main() { read(n, k); rt = new smt(1, n); for (long long i = 1; i < n; ++i) read(b[i]); for (long long i = 1; i <= n; ++i) read(a[i]); for (long long i = 1; i <= n; ++i) { f[i] = f[i - 1] + a[i - 1] - b[i - 1]; } for (long long i = 1; i <= n; ++i) { g[i] = g[i - 1] + b[i - 1] - a[i]; } long long ans = 0; for (long long i = n; i; --i) { rt->setg(i); while (t && f[s[t]] >= f[i]) { if (t > 1) { rt->add(s[t - 1] - 1, n, f[s[t]] - f[s[t - 1]]); } --t; } s[++t] = i; if (t > 1) assert(f[s[t]] >= f[s[t - 1]]); if (t > 1) { rt->add(s[t - 1] - 1, n, f[s[t - 1]] - f[s[t]]); } s[0] = n + 1; long long l = 1, r = t, mid; while (l <= r) { mid = (l + r) >> 1; if (f[i] - f[s[mid]] <= k) r = mid - 1; else l = mid + 1; } chkmax(ans, rt->query(inf, s[r] - 1) - i + 1); } write(ans, n ); return 0; }
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: disk02.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module disk02 (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: PRIVATE: MIFfilename STRING "disk_02.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "disk_02.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL disk02_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:56:21 04/12/2015
// Design Name:
// Module Name: Voter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Voter #(parameter WIDTH = 1)(
input [(WIDTH-1):0] A, B, C,
output [(WIDTH-1):0] True/*, A_error, B_error, C_error, Bit_error*/
);
//wire [(WIDTH-1):0] AB_error, AC_error, BC_error;
genvar i;
generate
for (i = 0; i < WIDTH; i = i +1) begin : Vote_Bit
// assign AB_error[i] = A[i] ^ B[i];
// assign AC_error[i] = A[i] ^ C[i];
// assign BC_error[i] = B[i] ^ C[i];
// assign A_error[i] = AB_error[i] && AC_error[i];
// assign B_error[i] = AB_error[i] && BC_error[i];
// assign C_error[i] = AC_error[i] && BC_error[i];
assign True[i] = (A[i] && B[i]) || (A[i] && C[i]) || (B[i] && C[i]);
// assign Bit_error[i] = AB_error[i] || AC_error[i] || BC_error[i];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; set<int> nx[1000100]; vector<pair<int, int> > nw; int a[1000100]; vector<pair<int, int> > ans; set<pair<int, int> > order; set<pair<int, int> > lst; int main() { ios_base ::sync_with_stdio(0); cin.tie(); cout.tie(); srand(23095); cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; nx[x].insert(y); nx[y].insert(x); a[x]++; a[y]++; } for (int i = 0; i < n; i++) { a[i] = (a[i] / 2) + (a[i] % 2); order.insert(make_pair(a[i], i)); } while (!order.empty()) { int v = order.begin()->second; order.erase(order.begin()); nw.clear(); for (auto u : nx[v]) { nw.push_back(make_pair(a[u], u)); } sort(nw.rbegin(), nw.rend()); for (int j = 0; a[v] > 0; j++) { a[v]--; if (a[nw[j].second] > 0) { order.erase(make_pair(a[nw[j].second], nw[j].second)); } a[nw[j].second]--; if (a[nw[j].second] > 0) { order.insert(make_pair(a[nw[j].second], nw[j].second)); } ans.push_back(make_pair(v, nw[j].second)); nx[v].erase(nw[j].second); nx[nw[j].second].erase(v); } } cout << ans.size() << n ; for (auto i : ans) { cout << i.first + 1 << << i.second + 1 << n ; } return 0; }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Phase accumulator
*/
module phase_accumulator #
(
parameter WIDTH = 32,
parameter INITIAL_PHASE = 0,
parameter INITIAL_PHASE_STEP = 0
)
(
input wire clk,
input wire rst,
/*
* AXI stream phase input
*/
input wire [WIDTH-1:0] input_phase_tdata,
input wire input_phase_tvalid,
output wire input_phase_tready,
/*
* AXI stream phase step input
*/
input wire [WIDTH-1:0] input_phase_step_tdata,
input wire input_phase_step_tvalid,
output wire input_phase_step_tready,
/*
* AXI stream phase output
*/
output wire [WIDTH-1:0] output_phase_tdata,
output wire output_phase_tvalid,
input wire output_phase_tready
);
reg [WIDTH-1:0] phase_reg = INITIAL_PHASE;
reg [WIDTH-1:0] phase_step_reg = INITIAL_PHASE_STEP;
assign input_phase_tready = output_phase_tready;
assign input_phase_step_tready = 1;
assign output_phase_tdata = phase_reg;
assign output_phase_tvalid = 1;
always @(posedge clk) begin
if (rst) begin
phase_reg <= INITIAL_PHASE;
phase_step_reg <= INITIAL_PHASE_STEP;
end else begin
if (input_phase_tready & input_phase_tvalid) begin
phase_reg <= input_phase_tdata;
end else if (output_phase_tready) begin
phase_reg <= phase_reg + phase_step_reg;
end
if (input_phase_step_tvalid) begin
phase_step_reg <= input_phase_step_tdata;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1.0); const long double EPS = 1e-12; const int MAXN = (int)1e5; const int INF = (int)2e9; int main() { int n, a[100]; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); int ans = INF; for (int i = 0; i < n; ++i) { int sum = 0; for (int j = 0; j < a[i]; ++j) { int num; scanf( %d , &num); sum += num * 5 + 15; } ans = min(ans, sum); } printf( %d , ans); return 0; }
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
#include <bits/stdc++.h> using namespace std; void getre() { int x = 0; printf( %d n , 1 / x); } void gettle() { int res = 1; while (1) res <<= 1; printf( %d n , res); } template <typename T, typename S> inline bool upmin(T &a, const S &b) { return a > b ? a = b, 1 : 0; } template <typename T, typename S> inline bool upmax(T &a, const S &b) { return a < b ? a = b, 1 : 0; } template <typename N, typename PN> inline N flo(N a, PN b) { return a >= 0 ? a / b : -((-a - 1) / b) - 1; } template <typename N, typename PN> inline N cei(N a, PN b) { return a > 0 ? (a - 1) / b + 1 : -(-a / b); } template <typename N> N gcd(N a, N b) { return b ? gcd(b, a % b) : a; } template <typename N> inline int sgn(N a) { return a > 0 ? 1 : (a < 0 ? -1 : 0); } inline void gn(long long &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; c == - ? (sg = -1, x = 0) : (x = c - 0 ); while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } inline void gn(int &x) { long long t; gn(t); x = t; } inline void gn(unsigned long long &x) { long long t; gn(t); x = t; } inline void gn(double &x) { double t; scanf( %lf , &t); x = t; } inline void gn(long double &x) { double t; scanf( %lf , &t); x = t; } inline void gs(char *s) { scanf( %s , s); } inline void gc(char &c) { while ((c = getchar()) > 126 || c < 33) ; } inline void pc(char c) { putchar(c); } inline long long sqr(long long a) { return a * a; } inline double sqrf(double a) { return a * a; } const int inf = 0x3f3f3f3f; const double pi = 3.14159265358979323846264338327950288L; const double eps = 1e-6; const int TREE_MAXV = 100000 + 5; struct edge { int v, next; } e[TREE_MAXV * 2]; int g[TREE_MAXV], etot; int n; void ae(int u, int v) { e[etot].v = v; e[etot].next = g[u]; g[u] = etot++; } int dfn[TREE_MAXV], rig[TREE_MAXV], pre[TREE_MAXV], h[TREE_MAXV]; int seq[TREE_MAXV], up[TREE_MAXV], sz[TREE_MAXV]; void build_hld(int rt) { static int qu[TREE_MAXV], son[TREE_MAXV]; int p = 0, q = 0; qu[q++] = rt; pre[rt] = 0; h[rt] = 0; while (p != q) { int u = qu[p++]; sz[u] = 1, son[u] = 0; for (int i = g[u]; ~i; i = e[i].next) if (e[i].v != pre[u]) qu[q++] = e[i].v, pre[e[i].v] = u, h[e[i].v] = h[u] + 1; } sz[0] = 0; for (int i = q - 1; i >= 1; i--) { sz[pre[qu[i]]] += sz[qu[i]]; if (sz[qu[i]] > sz[son[pre[qu[i]]]]) son[pre[qu[i]]] = qu[i]; } for (int j = 0; j < q; j++) if (!son[qu[j]]) { int s = qu[j]; while (son[pre[s]] == s) s = pre[s]; int t = s; while (t) up[t] = s, t = son[t]; } else { int u = qu[j], v = son[u]; if (e[g[u]].v != v) { for (int i = g[u], j; ~i; j = i, i = e[i].next) if (e[i].v == v) { e[j].next = e[i].next; e[i].next = g[u]; g[u] = i; break; } } } static int stk[TREE_MAXV], cur[TREE_MAXV]; int top = 0, ind = 0; stk[++top] = rt; cur[top] = g[rt]; while (top) { int u = stk[top]; if (cur[top] == g[u]) { dfn[u] = ++ind; seq[ind] = u; } if (cur[top] == -1) { rig[u] = ind; top--; } else { int v = e[cur[top]].v; cur[top] = e[cur[top]].next; if (v == pre[u]) continue; stk[++top] = v; cur[top] = g[v]; } } } void work(int a, int b) { int l1, r1; while (up[a] != up[b]) { if (h[up[a]] < h[up[b]]) swap(a, b); l1 = dfn[up[a]], r1 = dfn[a]; a = pre[up[a]]; } if (h[a] > h[b]) swap(a, b); l1 = dfn[a] + 1, r1 = dfn[b]; if (a != b) { } } int lca(int a, int b) { while (up[a] != up[b]) { if (h[up[a]] < h[up[b]]) swap(a, b); a = pre[up[a]]; } if (h[a] > h[b]) swap(a, b); return a; } void tree_init() { static bool ini = 0; if (!ini) { ini = 1; memset(g, -1, sizeof(g)); } else { for (int i = 0; i <= n; i++) g[i] = -1; } etot = 0; } int rt; void readedge() { for (int i = 1; i <= n; i++) { int x, y; gn(x); gn(y); if (x == 0) rt = y; else ae(x, y); } } int lis[111111]; int ansquer[3333333]; int quetot = 0; struct quer { int l, r; int x; int id; } que1[3333333], que0[3333333]; int que1tot = 0, que0tot = 0; int operator<(const quer &a, const quer &b) { return a.x < b.x; } void addque(int l, int r, int x, int bo) { int id = ++quetot; quer tmp = (quer){l, r, x, id}; if (bo) que1[++que1tot] = tmp; else que0[++que0tot] = tmp; } int poptot = 0; int popque() { int id = ++poptot; return ansquer[id]; } const int SEG_MAXN = 100000 + 5; int seg[SEG_MAXN * 4]; inline void segpu(int x) { seg[x] = max(seg[x << 1], seg[x << 1 | 1]); } void seginit_in(int l, int r, int x) { if (l == r) { seg[x] = -inf; } else { int mid = l + r >> 1; seginit_in(l, mid, x << 1); seginit_in(mid + 1, r, x << 1 | 1); segpu(x); } } int l1, r1, I; int sans; bool ans_bo; int stag; void segupd_in(int l, int r, int x) { if (l == r) { seg[x] = max(seg[x], stag); } else { int mid = l + r >> 1; if (I <= mid) segupd_in(l, mid, x << 1); else segupd_in(mid + 1, r, x << 1 | 1); segpu(x); } } void segque_in(int l, int r, int x) { if (l1 <= l && r <= r1) { if (!ans_bo) ans_bo = 1, sans = seg[x]; else sans = max(sans, seg[x]); } else { int mid = l + r >> 1; if (l1 <= mid) segque_in(l, mid, x << 1); if (r1 > mid) segque_in(mid + 1, r, x << 1 | 1); } } int segn; void segupd(int i, int v) { stag = v, I = i; segupd_in(1, segn, 1); } int segque(int l, int r) { if (l > r) return -inf; ans_bo = 0, l1 = l, r1 = r; segque_in(1, segn, 1); return sans; } void seginit(int n) { segn = n; seginit_in(1, segn, 1); } int ord[111111]; int cmpsz(int i, int j) { return sz[i] < sz[j]; } void gaoxunwen() { sort(que1 + 1, que1 + que1tot + 1); sort(que0 + 1, que0 + que0tot + 1); for (int i = (1), _ed = (n + 1); i < _ed; i++) ord[i] = i; sort(ord + 1, ord + 1 + n, cmpsz); seginit(n); int cur = 1; for (int i = (1), _ed = (que0tot + 1); i < _ed; i++) { int va = que0[i].x; while (cur <= n && sz[ord[cur]] <= va) { segupd(dfn[ord[cur]], sz[ord[cur]]); cur++; } ansquer[que0[i].id] = segque(que0[i].l, que0[i].r); } seginit(n); cur = n; for (int i = (que1tot + 1) - 1, _ed = (1); i >= _ed; i--) { int va = que1[i].x; while (cur >= 1 && sz[ord[cur]] >= va) { segupd(dfn[ord[cur]], -sz[ord[cur]]); cur--; } ansquer[que1[i].id] = -segque(que1[i].l, que1[i].r); } } struct quj { int l, r; } qq[111]; int cmpqj(const quj &a, const quj &b) { return a.l < b.l; } void getque(int nrt, int u, int val, int bo) { if (nrt != rt) { addque(dfn[nrt], rig[nrt], val, bo); } else { int qjtot = 0; int del = sz[u]; qq[++qjtot] = (quj){dfn[u], rig[u]}; int v = pre[u]; while (v) { qq[++qjtot] = (quj){dfn[up[v]], dfn[v]}; v = pre[up[v]]; } sort(qq + 1, qq + 1 + qjtot, cmpqj); qq[0].r = 0, qq[qjtot + 1].l = n + 1; for (int i = (0), _ed = (qjtot + 1); i < _ed; i++) { if (qq[i].r + 1 <= qq[i + 1].l - 1) addque(qq[i].r + 1, qq[i + 1].l - 1, val, bo); } v = pre[u]; while (v) { addque(dfn[up[v]], dfn[v], val + del, bo); v = pre[up[v]]; } } } int gotque(int nrt, int u, int val, int bo) { if (nrt != rt) { return popque(); } else { int ret; if (bo == 0) ret = -inf; else ret = inf; int qjtot = 0; int del = sz[u]; qq[++qjtot] = (quj){dfn[u], rig[u]}; int v = pre[u]; while (v) { qq[++qjtot] = (quj){dfn[up[v]], dfn[v]}; v = pre[up[v]]; } sort(qq + 1, qq + 1 + qjtot, cmpqj); qq[0].r = 0, qq[qjtot + 1].l = n + 1; for (int i = (0), _ed = (qjtot + 1); i < _ed; i++) { if (qq[i].r + 1 <= qq[i + 1].l - 1) { int goo = popque(); if (bo == 0) upmax(ret, goo); else upmin(ret, goo); } } v = pre[u]; while (v) { int goo = popque() - del; if (bo == 0) upmax(ret, goo); else upmin(ret, goo); v = pre[up[v]]; } return ret; } } void prework(int u) { int tot = 0; for (int i = g[u]; ~i; i = e[i].next) lis[++tot] = sz[e[i].v]; if (u != rt) { lis[++tot] = n - sz[u]; } sort(lis + 1, lis + 1 + tot); int masz = lis[tot]; int nrt = rt; for (int i = g[u]; ~i; i = e[i].next) if (sz[e[i].v] == masz) { nrt = e[i].v; } if (tot == 0) return; if (tot == 1) return; if (tot == 2) { int a = lis[1], c = lis[2]; getque(nrt, u, cei(c - a, 2), 1); getque(nrt, u, (c - a) / 2, 0); return; } else { int a = lis[1], b = lis[tot - 1], c = lis[tot]; getque(nrt, u, cei(c - a, 2), 1); getque(nrt, u, (c - a) / 2, 0); getque(nrt, u, c - b, 1); return; } } int work(int u) { int tot = 0; for (int i = g[u]; ~i; i = e[i].next) lis[++tot] = sz[e[i].v]; if (u != rt) { lis[++tot] = n - sz[u]; } sort(lis + 1, lis + 1 + tot); int masz = lis[tot]; int nrt = rt; for (int i = g[u]; ~i; i = e[i].next) if (sz[e[i].v] == masz) { nrt = e[i].v; } if (tot == 0) return 0; if (tot == 1) return lis[1]; if (tot == 2) { int a = lis[1], c = lis[2]; int d1 = gotque(nrt, u, cei(c - a, 2), 1); int d2 = gotque(nrt, u, (c - a) / 2, 0); return min(lis[2], min(max(c - d1, a + d1), max(c - d2, a + d2))); } else { int a = lis[1], b = lis[tot - 1], c = lis[tot]; int d1 = gotque(nrt, u, cei(c - a, 2), 1); int d2 = gotque(nrt, u, (c - a) / 2, 0); int d3 = gotque(nrt, u, c - b, 1); int ans = lis[tot]; upmin(ans, max(max(a + d1, b), c - d1)); upmin(ans, max(max(a + d2, b), c - d2)); upmin(ans, max(max(a + d3, b), c - d3)); return ans; } } int main() { gn(n); tree_init(); readedge(); build_hld(rt); for (int u = (1), _ed = (n + 1); u < _ed; u++) prework(u); gaoxunwen(); for (int u = (1), _ed = (n + 1); u < _ed; u++) printf( %d n , work(u)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_LP_V
`define SKY130_FD_SC_LP__A2111O_LP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_lp (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_lp (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_LP_V
|
#include <bits/stdc++.h> using namespace std; void File() { freopen( output.txt , w , stdout); freopen( input.txt , r , stdin); } void yAsEr_HaFiz() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; int const N = 2e5 + 9, MOD = 1e9 + 7, oo = 1e9 + 7; long long n, m, a, n1, n2; int main() { long long l, r; cin >> l >> r; cout << YES << n ; for (long long i = l; i <= r; i += 2) cout << i << << i + 1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; string s; int dp[510][510]; bool has[510][510][30]; int dfs(int l, int r) { if (l >= r) return 0; int &ans = dp[l][r]; if (ans != 0) return ans; if (!has[l + 1][r][s[l] - a ]) return ans = dfs(l + 1, r); ans = dfs(l + 1, r); for (int i = l + 1; i <= r; i++) if (s[i] == s[l]) ans = max(ans, dfs(l + 1, i) + 1 + dfs(i + 1, r)); return ans; } int main() { cin >> n >> s; for (int i = 0; i < (int)s.size(); i++) for (int j = 0; j < (int)s.size(); j++) for (int k = i; k <= j; k++) has[i][j][s[k] - a ] = 1; cout << (int)s.size() - dfs(0, s.size() - 1) << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_FUNCTIONAL_V
`define SKY130_FD_SC_LP__HA_FUNCTIONAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string x, y; cin >> x >> y; int n, m; n = x.size(), m = y.size(); if (n != m) { cout << NO ; return 0; } if (n == 1) { if (x == y) cout << YES ; else cout << NO ; return 0; } if (x == y) { cout << YES ; return 0; } int cnt = count(x.begin(), x.end(), 0 ); int cnt1 = count(y.begin(), y.end(), 0 ); if (cnt == n || cnt1 == n) cout << NO ; else cout << YES ; }
|
interface my_interface ();
logic [2:0] out2;
logic [2:0] out3;
endinterface: my_interface
module foobar (input [2:0] in2, output [2:0] out2);
endmodule
module foo_autowire_fails (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out2 = out2; // perhaps a namespace collision?
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
module foo_autowire_works (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out3 = out2;
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 5; long long a[N], dp[N]; long long n, k; long long check(long long m) { for (int i = 0; i < n; i++) { dp[i] = i - 1; for (int j = 0; j < i; j++) { if (abs(a[i] - a[j]) <= 1ll * (i - j) * m) { dp[i] = min(dp[i], dp[j] + i - j - 1); } } if (dp[i] + n - i <= k) { return true; } } return false; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } long long l = -1, r = 2e9; while (r - l > 1) { long long mid = (l + r) / 2; if (check(mid)) { r = mid; } else { l = mid; } } cout << r; }
|
#include <bits/stdc++.h> using namespace std; int root, n; vector<int> mp[200605]; int Dfs(int u, int from) { set<int> s; for (int i = 0; i < mp[u].size(); i++) { int v = mp[u][i]; if (v == from) continue; int tmp = Dfs(v, u); if (tmp == -1) return -1; s.insert(tmp + 1); } if (s.size() == 0) return 0; if (s.size() == 1) return *s.begin(); if (s.size() == 2) { if (from == -1) { int sum = 0; for (set<int>::iterator it = s.begin(); it != s.end(); it++) { sum += *it; } return sum; } else { root = u; return -1; } } return -1; } int main() { while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) mp[i].clear(); for (int i = 1; i <= n - 1; i++) { int x, y; scanf( %d%d , &x, &y); mp[x].push_back(y); mp[y].push_back(x); } root = 1; int ans = Dfs(root, -1); if (ans == -1 && root != 1) ans = Dfs(root, -1); while (ans % 2 == 0) ans /= 2; printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; long long n, mod = 1e9 + 7ll, cont, maxi = 1000000000000ll, cont2, val[400005], ans, bestval = 1000000000000ll; pair<long long, long long> dp[400005], num, ft[400005]; pair<int, int> v[400005]; map<int, int> ind; vector<int> opz[400005], tmp; void update(int pos, long long val, long long num) { for (int i = pos; i < 400005; i += (i & (-i))) { if (ft[i].first > val) { ft[i] = {val, num}; } else { if (ft[i].first == val) ft[i].second += num; ft[i].second %= mod; } } } pair<long long, long long> query(int pos) { long long sol = maxi, solnum = 0; for (int i = pos; i > 0; i -= (i & (-i))) { if (ft[i].first < sol) { sol = ft[i].first; solnum = ft[i].second; } else { if (ft[i].first == sol) { solnum += ft[i].second; solnum %= mod; } } } return {sol, solnum}; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; tmp.push_back(v[i].first); tmp.push_back(v[i].second); } sort(tmp.begin(), tmp.end()); cont = 1; for (int i = 0; i < tmp.size(); i++) { if (i == 0 || tmp[i] != tmp[i - 1]) { ind[tmp[i]] = cont; val[cont] = tmp[i]; cont++; } } for (int i = 0; i < n; i++) { opz[ind[v[i].first]].push_back(v[i].second); } for (int i = 0; i < 400005; i++) { sort(opz[i].begin(), opz[i].end()); ft[i] = {maxi, 0}; } update(1, maxi, 1); for (int i = 1; i < cont; i++) { cont2 = 0; if (opz[i].size() == 0) continue; dp[i].first = maxi; dp[i].second = 1; for (int j = 0; j < opz[i].size(); j++) { cont2++; if (j == opz[i].size() - 1 || opz[i][j] != opz[i][j + 1]) { num = query(ind[opz[i][j]]); num.first = num.first - (val[i] - opz[i][j]); num.second *= cont2; num.second %= mod; if (dp[i].first > num.first) { dp[i] = num; } else { if (dp[i].first == num.first) { dp[i].second += num.second; dp[i].second %= mod; } } cont2 = 0; } } update(i, dp[i].first, dp[i].second); } sort(v, v + n); reverse(v, v + n); for (int i = ind[v[0].first]; i > ind[v[0].second]; i--) { if (bestval > (dp[i].first - (maxi - val[i]))) { bestval = (dp[i].first - (maxi - val[i])); ans = dp[i].second; } else { if (bestval == (dp[i].first - (maxi - val[i]))) ans += dp[i].second; ans %= mod; } } cout << max(ans, 1ll) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> t >> s; set<char> b(t.begin(), t.end()); int n; cin >> n; for (int k = 0; k < n; ++k) { cin >> t; int i = 0; int j = 0; while (i < s.size() || j < t.size()) { if (s[i] == ? ) { if (b.find(t[j]) != b.end()) { ++i; ++j; } else { break; } } else if (s[i] == * ) { int x = t.size() - s.size() + 1; if (x < 0) { break; } else if (all_of(t.begin() + i, t.begin() + i + x, [&](char c) { return b.find(c) == b.end(); })) { ++i; j += x; } else { break; } } else { if (s[i] == t[j]) { ++i; ++j; } else { break; } } } if (i == s.size() && j == t.size()) cout << YES n ; else cout << NO n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_1_V
`define SKY130_FD_SC_LS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_TB_V
`define SKY130_FD_SC_MS__NAND4B_TB_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__nand4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_TB_V
|
//==================================================================================================
// Filename : antares_branch_unit.v
// Created On : Fri Sep 4 21:35:54 2015
// Last Modified : Sat Nov 07 11:49:10 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Branch target calculation
//==================================================================================================
`include "antares_defines.v"
module antares_branch_unit (
input [5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, // imm21/Imm16
output reg [31:0] pc_branch_address, // Destination address
output reg id_take_branch // Valid branch
) ;
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire beq;
wire bne;
wire bgez;
wire bgtz;
wire blez;
wire bltz;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [5:0] inst_function;
wire [4:0] op_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign beq = id_data_rs == id_data_rt;
assign bne = ~beq;
assign bgez = ~bltz;
assign bgtz = ~blez;
assign blez = bltz | ~(|id_data_rs);
assign bltz = id_data_rs[31];
assign long_jump = {id_pc_add4[31:28], op_imm26, 2'b00 };
assign short_jump = $signed(id_pc_add4) + $signed( { {14{op_imm26[15]}}, op_imm26[`ANTARES_INSTR_IMM16], 2'b00 } );
assign inst_function = op_imm26[`ANTARES_INSTR_FUNCT];
assign op_rt = op_imm26[`ANTARES_INSTR_RT];
//--------------------------------------------------------------------------
// Get branch address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_BEQ : begin pc_branch_address = short_jump; id_take_branch = beq; end
`OP_BGTZ : begin pc_branch_address = short_jump; id_take_branch = bgtz; end
`OP_BLEZ : begin pc_branch_address = short_jump; id_take_branch = blez; end
`OP_BNE : begin pc_branch_address = short_jump; id_take_branch = bne; end
`OP_J : begin pc_branch_address = long_jump; id_take_branch = 1'b1; end
`OP_JAL : begin pc_branch_address = long_jump; id_take_branch = 1'b1; end
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin pc_branch_address = short_jump; id_take_branch = bgez; end
`RT_OP_BGEZAL : begin pc_branch_address = short_jump; id_take_branch = bgez; end
`RT_OP_BLTZ : begin pc_branch_address = short_jump; id_take_branch = bltz; end
`RT_OP_BLTZAL : begin pc_branch_address = short_jump; id_take_branch = bltz; end
default : begin pc_branch_address = 32'bx; id_take_branch = 1'b0; end
endcase // case (op_rt)
end
`OP_TYPE_R : begin
case(inst_function)
`FUNCTION_OP_JALR : begin pc_branch_address = id_data_rs; id_take_branch = 1'b1; end
`FUNCTION_OP_JR : begin pc_branch_address = id_data_rs; id_take_branch = 1'b1; end
default : begin pc_branch_address = 32'bx; id_take_branch = 1'b0; end
endcase // case (inst_function)
end
default : begin pc_branch_address = 32'bx; id_take_branch = 1'b0; end
endcase // case (opcode)
end // always @ (*)
endmodule // antares_branch_unit
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module memory (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("memory.mif"),
.C_INIT_FILE("memory.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 18.569202 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(16'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n == 1 && m == 1) cout << 1; else if (m + n < 5) cout << -1; else { int x = n * m / 2 + 1, y = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if ((i + j) % 2 == 0) { cout << x << ; x++; } else { cout << y << ; y++; } } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; const long long MAX = 1000004; const long long INF = 1e18L + 5; template <class T, class U> void chmin(T &t, const U &u) { if (t > u) t = u; } template <class T, class U> void chmax(T &t, const U &u) { if (t < u) t = u; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } template <typename Arg1> void pn(Arg1 &&arg1) { cout << arg1 << n ; } template <typename Arg1, typename... Args> void pn(Arg1 &&arg1, Args &&...args) { cout << arg1 << n ; pn(args...); } template <typename Arg1> void ps(Arg1 &&arg1) { cout << arg1 << ; } template <typename Arg1, typename... Args> void ps(Arg1 &&arg1, Args &&...args) { cout << arg1 << ; ps(args...); } template <typename Arg1> void read(Arg1 &&arg1) { cin >> arg1; } template <typename Arg1, typename... Args> void read(Arg1 &&arg1, Args &&...args) { cin >> arg1; read(args...); } long long n, m; char mat[51][51]; long long dx[] = {1, 0, -1, 0}; long long dy[] = {0, 1, 0, -1}; bool valid(long long x, long long y) { if (x >= 0 && y >= 0 && x < n && y < m) return true; return false; } vector<vector<long long>> vis(51, vector<long long>(51, 0)); void dfs(long long x, long long y) { if (mat[x][y] == # ) return; if (mat[x][y] == G ) { mat[x][y] = . ; } if (mat[x][y] == B ) { return; } vis[x][y] = 1; for (long long i = 0; i < 4; ++i) { long long tx = x + dx[i]; long long ty = y + dy[i]; if (valid(tx, ty)) { if (!vis[tx][ty]) dfs(tx, ty); } } } void solve() { read(n, m); bool pos = true; for (long long i = 0; i < n; ++i) for (long long j = 0; j < m; ++j) read(mat[i][j]); for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { if (mat[i][j] == B ) { for (long long k = 0; k < 4; ++k) { long long tx = i + dx[k]; long long ty = j + dy[k]; if (valid(tx, ty)) { if (mat[tx][ty] == G ) { pos = false; } else { if (mat[tx][ty] != B ) mat[tx][ty] = # ; } } } } } } if (pos) { for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { if (mat[i][j] == G ) { for (long long k = 0; k < n; ++k) for (long long l = 0; l < m; ++l) vis[k][l] = 0; dfs(i, j); if (vis[n - 1][m - 1] == 0) { pos = false; } } } } pn(pos ? Yes : No ); } else pn( No ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long tc = 1; cin >> tc; while (tc--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int n, m, OO = 1e8; int dp[100001]; int solve(int x) { if (x <= 0 || x > 1e5) return OO; if (x == m) return 0; int &ret = dp[x]; if (ret != -1) return ret; ret = OO; if (x > m) ret = min(ret, 1 + solve(x - 1)); else { ret = min(ret, 1 + solve(x * 2)); ret = min(ret, 1 + solve(x - 1)); } return ret; } int main() { cin >> n >> m; memset(dp, -1, sizeof(dp)); cout << solve(n) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e6; int q, lstAns, flag; long long m; struct point { long long x, y; point(long long x, long long y) : x(x), y(y) {} inline bool operator<(const point &a) const { if (flag) return y < a.y; return x < a.x; } inline point operator-(const point &a) const { return point(x - a.x, y - a.y); } inline long long cross(const point &a) const { return x * a.y - y * a.x; } }; set<point> mag; inline int addMod(int a, int b) { return (a += b) >= mod ? a - mod : a; } inline long long quickpow(long long base, long long pw) { long long ret = 1; while (pw) { if (pw & 1) ret = ret * base % mod; base = base * base % mod, pw >>= 1; } return ret; } template <class T> inline void read(T &x) { x = 0; char ch = getchar(), w = 0; while (!isdigit(ch)) w = (ch == - ), ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x = w ? -x : x; return; } int main() { int opt, x, y; read(q), read(m); mag.emplace(0, 0); for (register int i = 1; i <= q; ++i) { read(opt), read(x), read(y); x = (x + lstAns) % mod + 1, y = (y + lstAns) % mod + 1; if (opt == 1) { point tmp(y, x); auto r = mag.lower_bound(point(y + 1, 0)), l = prev(r); if (r != mag.end() && (tmp - *l).cross(*r - *l) >= 0) continue; while (l != mag.begin()) { if ((*l - *prev(l)).cross(tmp - *prev(l)) < 0) break; mag.erase(l--); } while (r != mag.end() && r->y <= x) mag.erase(r++); while (r != mag.end() && next(r) != mag.end()) { if ((*r - tmp).cross(*next(r) - tmp) < 0) break; mag.erase(r++); } mag.insert(tmp); } else { flag = 1; auto r = mag.lower_bound(point(0, ceil((double)y / x))), l = prev(r); if (r == mag.end()) { printf( NO n ), flag = 0; continue; } if ((y - l->y * x) * (r->x - l->x) + l->x * (r->y - l->y) * x <= m * (r->y - l->y)) printf( YES n ), lstAns = i; else printf( NO n ); flag = 0; } } return 0; }
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