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//--------------------------------------------------------------------------------
// prescaler.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Shared prescaler for transmitter and receiver timings.
// Used to control the transfer speed.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module prescaler #(
parameter [31:0] SCALE = 28
)(
input wire clock;
input wire reset;
input wire [1:0] div;
output reg scaled;
);
always @ (*)
scaled = 1'b1;
/*
reg [31:0] counter, next_counter;
reg next_scaled;
always @(posedge clock, posedge reset)
if (reset) begin
counter <= 0;
scaled <= 1'b0;
end else begin
counter <= next_counter;
scaled <= next_scaled;
end
always
begin
next_scaled = 1'b0;
case (div)
2'b00 : next_scaled = (counter == (SCALE-1)); // 115200 baud
2'b01 : next_scaled = (counter == (2*SCALE-1)); // 57600 baud
2'b10 : next_scaled = (counter == (3*SCALE-1)); // 38400 baud
2'b11 : next_scaled = (counter == (6*SCALE-1)); // 19200 baud
endcase
next_counter = counter + 1'b1;
if (next_scaled) next_counter = 0;
end
*/
endmodule
|
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
-1
module sync_fifo #(
parameter DEPTH = 3,
parameter DATA_W = 32,
parameter ASSERT_OVERFLOW = 1,
parameter ASSERT_UNDERFLOW = 1,
parameter ENABLE_BYPASS = 0
)
(
input clk,
input rstn,
input [DATA_W-1:0] fifo_data_in,
input fifo_push,
output [DATA_W-1:0] fifo_data_out,
input fifo_pop,
output fifo_full,
output fifo_empty,
input fifo_flush
);
localparam DEPTH_LOG2 = `CLOG2(DEPTH);
reg [DATA_W-1:0] mem [0:DEPTH-1];
reg [DEPTH_LOG2-1:0] head, n_head;
reg [DEPTH_LOG2-1:0] tail, n_tail;
wire empty;
wire full;
reg push_last;
assign fifo_data_out = mem[tail];
assign fifo_full = full;
assign fifo_empty = empty;
always @ (*) begin
if (head < DEPTH-1) begin
n_head = head + 'h1;
end
else begin
n_head = 'h0;
end
end
always @ (*) begin
if (tail < DEPTH-1) begin
n_tail = tail + 'h1;
end
else begin
n_tail = 'h0;
end
end
generate
if (ENABLE_BYPASS) begin
assign full = (push_last && (head == tail) && !fifo_pop) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail) && !fifo_push) ? 1'b1 : 1'b0;
end
else begin
assign full = (push_last && (head == tail)) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail)) ? 1'b1 : 1'b0;
end
endgenerate
generate
if (ASSERT_OVERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_push && full) begin
$display("ERROR: FIFO OVERFLOW");
$finish;
end
end
end
if (ASSERT_UNDERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_pop && empty) begin
$display("ERROR: FIFO UNDERFLOW");
$finish;
end
end
end
endgenerate
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
head <= 'h0;
tail <= 'h0;
push_last <= 'h0;
end
else begin
if (fifo_flush) begin
tail <= 'h0;
head <= 'h0;
push_last <= 'h0;
end
else if (!((full && fifo_push) || (empty && fifo_pop))) begin
if (fifo_push) begin
mem[head] <= fifo_data_in;
head <= n_head;
end
if (fifo_pop) begin
tail <= n_tail;
end
if (fifo_push && !fifo_pop) begin
push_last = 'h1;
end
else if (!fifo_push && fifo_pop) begin
push_last = 'h0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> ans, a; int n, temp; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &temp); a.push_back(temp); } for (int i = 0; i < a.size(); i++) { if (a[i] == 1) { ans.push_back(1); } else { ans[ans.size() - 1]++; } } printf( %d n%d , (int)ans.size(), ans[0]); for (int i = 1; i < ans.size(); i++) { printf( %d , ans[i]); } printf( n ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_2_V
`define SKY130_FD_SC_MS__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, W, i, j, k; cin >> n >> m >> W; long long w[n], b[n]; for (i = 0; i < n; i++) cin >> w[i]; for (i = 0; i < n; i++) cin >> b[i]; vector<long long> G[n]; for (i = 0; i < m; i++) { cin >> j >> k; j--; k--; G[j].push_back(k); G[k].push_back(j); } bool u[n]; memset(u, 0, sizeof(u)); vector<pair<long long, long long> > v; vector<vector<long long> > vl; for (i = 0; i < n; i++) { if (u[i]) continue; queue<long long> q; vector<long long> l; q.push(i); pair<long long, long long> p = pair<long long, long long>(0, 0); while (!q.empty()) { k = q.front(); q.pop(); if (u[k]) continue; u[k] = 1; l.push_back(k); p.first += b[k]; p.second += w[k]; for (j = 0; j < G[k].size(); j++) q.push(G[k][j]); } v.push_back(p); vl.push_back(l); } long long V = v.size(), ans = 0; long long dp[V + 1][W + 1]; memset(dp, 0, sizeof(dp)); for (i = 0; i < V; i++) { for (j = 0; j < W; j++) { dp[i + 1][j] = max(dp[i + 1][j], dp[i][j]); for (k = 0; k < vl[i].size(); k++) { if (j + w[vl[i][k]] > W) continue; dp[i + 1][j + w[vl[i][k]]] = max(dp[i + 1][j + w[vl[i][k]]], dp[i][j] + b[vl[i][k]]); } if (j + v[i].second > W) continue; dp[i + 1][j + v[i].second] = max(dp[i + 1][j + v[i].second], dp[i][j] + v[i].first); } } for (i = 0; i <= V; i++) for (j = 0; j <= W; j++) ans = max(ans, dp[i][j]); cout << ans << endl; return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module spi #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SPI_CLK,
output wire SCLK,
input wire SDO,
output wire SDI,
input wire EXT_START,
output wire SEN,
output wire SLD
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
spi_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES)
) i_spi_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SPI_CLK(SPI_CLK),
.SCLK(SCLK),
.SDO(SDO),
.SDI(SDI),
.EXT_START(EXT_START),
.SEN(SEN),
.SLD(SLD)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, k; long long int i; long long int sum = 0; long long int cheng = 1; long long int ans[200010]; struct xxx { long long int num; long long int id; bool operator<(const struct xxx &node) const { return num > node.num; } } xxx[200010]; int main() { scanf( %lld%lld , &n, &k); for (i = 0; i < n; i++) { xxx[i].id = i; scanf( %lld , &xxx[i].num); } sort(xxx, xxx + n); for (i = 0; i < k; i++) sum = sum + xxx[i].num; for (i = 0; i < k; i++) ans[i] = xxx[i].id; sort(ans, ans + k); for (i = 0; i < k - 1; i++) cheng = cheng * (ans[i + 1] - ans[i]) % 998244353; printf( %lld %lld , sum, cheng); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_fYi_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_fYi_rom.dat", ram0);
$readmemh("./Loop_loop_height_fYi_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_fYi(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_fYi_rom Loop_loop_height_fYi_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFDS_GTE3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 08/28/2013 - Initial model
// 06/02/14 - New simulation library message format.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTE3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input [3:0] I,
input [1:0] RXRECCLK_SEL
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE3_ADV";
reg I_delay;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [4:0] REFCLK_ICNTL_TX_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
tri0 GTS = glbl.GTS;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE3_ADV_dr.v"
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG;
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_EN_TX_PATH_REG !== 1'b0) && (REFCLK_EN_TX_PATH_REG !== 1'b1))) begin
$display("Error: [Unisim %s-101] REFCLK_EN_TX_PATH attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, REFCLK_EN_TX_PATH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_TX_REG < 5'b00000) || (REFCLK_ICNTL_TX_REG > 5'b11111))) begin
$display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
wire t1;
wire t2;
or O1 (t1, GTS, CEB);
or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1);
// =====================
// Generate I_delay
// =====================
always @(*) begin
case (RXRECCLK_SEL)
2'b00: I_delay <= I[0];
2'b01: I_delay <= I[1];
2'b10: I_delay <= I[2];
2'b11: I_delay <= I[3];
default : I_delay <= I[0];
endcase
end
bufif0 B1 (O, I_delay, t2);
notif0 N1 (OB, I_delay, t2);
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; int n, m, h[N], mn[N], par[N], t, num, op, uo, ra; vector<int> adj[N]; set<int> answer, qtr; bool finish, q[N], vis[N]; struct edge { int u, v; } ed[N]; void output() { if ((int)answer.size() == n) { cout << NO << n ; finish = true; return; } cout << YES << n << n - answer.size() << n ; for (int i = 0; i < n; i++) if (!answer.count(i)) cout << i + 1 << ; cout << n ; finish = true; } void haveDeg3() { for (int i = 0; i < n && !finish; i++) if (!(adj[i].size() % 3)) answer.insert(i), output(); } void oneEdge() { for (int i = 0; i < m; i++) { if (adj[ed[i].v].size() % 3 == 1 && adj[ed[i].u].size() % 3 == 1) { answer.insert(ed[i].u), answer.insert(ed[i].v), output(); return; } } } void check(int x) { vector<int> po; for (auto v : adj[x]) if (adj[v].size() % 3 == 1) { q[x] = true; po.push_back(v); } if (po.size() > 1) { answer.insert(po[0]), answer.insert(po[1]), answer.insert(x), output(); return; } } void Vgraph() { for (int i = 0; i < n && !finish; i++) if (adj[i].size() % 3 == 2) check(i); } void findCycle(int x) { vis[x] = true; for (auto v : adj[x]) if (adj[v].size() % 3 == 2 && v != par[x]) { if (!vis[v]) h[v] = h[x] + 1, mn[v] = h[v], par[v] = x; else { if (mn[x] != h[x]) mn[x] = max(mn[x], h[v]); else mn[x] = min(mn[x], h[v]); } } if (mn[x] < h[x] - 1) { int z = mn[x]; while (h[x] != z) { answer.insert(x), x = par[x]; } answer.insert(x), output(); return; } for (auto v : adj[x]) if (!vis[v] && !finish && adj[v].size() % 3 == 2) { findCycle(v); } } void cycle() { for (int i = 0; i < n && !finish; i++) if (adj[i].size() % 3 == 2 && !vis[i]) { findCycle(i); } } void dfs(int x) { if (finish) return; vis[x] = true; if (q[x]) { if (!qtr.count(x)) { for (auto v : adj[x]) if (adj[v].size() % 3 == 1) answer.insert(v); while (x != op) answer.insert(x), x = par[x]; answer.insert(op); output(); } else if (par[x] != op) { vis[x] = false; return; } } for (auto v : adj[x]) if (!vis[v] && adj[v].size() % 3 == 2) par[v] = x, dfs(v); } void dfsqt(int x) { if (finish) return; vis[x] = true; if (q[x] && par[x] != op) { num++; while (x != op) { for (auto v : adj[x]) vis[v] = true; answer.insert(x), x = par[x]; } if (num > 1) { answer.insert(x); output(); } dfsqt(op); } for (auto v : adj[x]) if (!vis[v] && adj[v].size() % 3 == 2) par[v] = x, dfsqt(v); } void another() { num = 0; for (int i = 0; i < n; i++) par[i] = 0, vis[i] = false; for (int i = 0; i < n && !finish; i++) if (adj[i].size() % 3 == 1) { qtr.clear(); for (auto v : adj[i]) qtr.insert(v); dfs(op = i); if (!finish) { for (int i = 0; i < n; i++) par[i] = 0, vis[i] = false; dfsqt(op); } return; } } void readInput() { answer.clear(); finish = false; cin >> n >> m; for (int i = 0; i < n; i++) adj[i].clear(), h[i] = mn[i] = par[i] = 0, vis[i] = q[i] = false; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; ed[i].u = --x, ed[i].v = --y; adj[x].push_back(y); adj[y].push_back(x); } } void solve() { haveDeg3(); if (finish) return; oneEdge(); if (finish) return; Vgraph(); if (finish) return; cycle(); if (finish) return; another(); if (finish) return; cout << NO n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> t; while (t--) readInput(), solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_4_V
`define SKY130_FD_SC_HD__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_4_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = (N-1)*log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
wire [bw-1:0] signal_in;
output [bw-1:0] signal_out;
wire [bw-1:0] signal_out;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
wire clear_me = reset | ~enable;
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
if(clear_me)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable & strobe_out)
begin
if(strobe_in)
integrator[0] <= #1 integrator[0] + pipeline[N-1];
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(clear_me)
begin
for(i=0;i<N;i=i+1)
begin
differentiator[i] <= #1 0;
pipeline[i] <= #1 0;
end
end
else if (enable && strobe_in)
begin
differentiator[0] <= #1 signal_in_ext;
pipeline[0] <= #1 signal_in_ext - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
cic_int_shifter #(bw)
cic_int_shifter(rate,signal_out_unnorm,signal_out);
endmodule // cic_interp
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_missed (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 15: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 15: 0] in_port;
input reset_n;
wire clk_en;
wire [ 15: 0] data_in;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O311AI_BEHAVIORAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_TB_V
`define SKY130_FD_SC_MS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_TB_V
|
// registerfile_io32.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module registerfile_io32 (
input wire clk, // clock.clk
input wire slave_read, // slave.read
input wire slave_write, // .write
input wire [5:0]slave_address, // .address
output wire [31:0] slave_readdata, // .readdata
input wire [31:0] slave_writedata, // .writedata
input wire reset, // reset.reset
output atb_read,
output atb_write,
output [5:0]atb_register,
input [31:0]atb_readdata,
output [31:0]atb_writedata
);
assign atb_read = slave_read;
assign atb_write = slave_write;
assign atb_register = slave_address;
assign atb_writedata = slave_writedata;
assign slave_readdata = atb_readdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, k, m, n, x, y; cin >> n; if (n == 1) { x = 9; y = 8; } if (n == 2) { x = 6; y = 4; } if (n == 3) { x = 9; y = 6; } if ((n != 2) && (n != 1) && (n != 3)) { if (n % 2 == 0) { x = 2 * n; y = n; } else { x = n + 9; y = 9; } } cout << x << << y << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A2111O_PP_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_PP_SYMBOL_V
|
#include <bits/stdc++.h> template <typename T> class IntegerIterator : public std::iterator<std::input_iterator_tag, T, std::ptrdiff_t, T*, T> { public: explicit IntegerIterator(int value) : value(value) {} IntegerIterator& operator++() { ++value; return *this; } IntegerIterator operator++(int) { IntegerIterator copy = *this; ++value; return copy; } IntegerIterator& operator--() { --value; return *this; } IntegerIterator operator--(int) { IntegerIterator copy = *this; --value; return copy; } T operator*() const { return value; } bool operator==(IntegerIterator rhs) { return value == rhs.value; } bool operator!=(IntegerIterator rhs) { return !(*this == rhs); } private: T value; }; template <typename T> class IntegerRange { public: IntegerRange(T begin, T end) : begin_(begin), end_(end) {} IntegerIterator<T> begin() const { return IntegerIterator<T>(begin_); } IntegerIterator<T> end() const { return IntegerIterator<T>(end_); } private: T begin_; T end_; }; template <typename T> class ReversedIntegerRange { public: ReversedIntegerRange(T begin, T end) : begin_(begin), end_(end) {} std::reverse_iterator<IntegerIterator<T>> begin() const { return std::reverse_iterator<IntegerIterator<T>>( IntegerIterator<T>(begin_)); } std::reverse_iterator<IntegerIterator<T>> end() const { return std::reverse_iterator<IntegerIterator<T>>(IntegerIterator<T>(end_)); } private: T begin_; T end_; }; template <typename T> IntegerRange<T> range(T to) { ; return IntegerRange<T>(0, to); } template <typename T> IntegerRange<T> range(T from, T to) { ; return IntegerRange<T>(from, to); } template <typename T> IntegerRange<T> inclusiveRange(T to) { ; return IntegerRange<T>(0, to + 1); } template <typename T> IntegerRange<T> inclusiveRange(T from, T to) { ; return IntegerRange<T>(from, to + 1); } template <typename T> ReversedIntegerRange<T> downrange(T from) { ; return ReversedIntegerRange<T>(from, 0); } template <typename T> ReversedIntegerRange<T> downrange(T from, T to) { ; return ReversedIntegerRange<T>(from, to); } template <typename T> ReversedIntegerRange<T> inclusiveDownrange(T from) { ; return ReversedIntegerRange<T>(from + 1, 0); } template <typename T> ReversedIntegerRange<T> inclusiveDownrange(T from, T to) { ; return ReversedIntegerRange<T>(from + 1, to); } template <typename R> void sort(R& range) { std::sort(range.begin(), range.end()); } template <typename R, typename Comp> void sort(R& range, Comp comp) { std::sort(range.begin(), range.end(), comp); } template <typename R> void reverse(R& range) { std::reverse(range.begin(), range.end()); } template <typename R, typename T> auto lower_bound(const R& range, const T& value) -> decltype(range.begin()) { return std::lower_bound(range.begin(), range.end(), value); } template <typename R, typename T, typename Comp> auto lower_bound(const R& range, const T& value, Comp comp) -> decltype(range.begin()) { return std::lower_bound(range.begin(), range.end(), value, comp); } template <typename R, typename T> auto upper_bound(const R& range, const T& value) -> decltype(range.begin()) { return std::upper_bound(range.begin(), range.end(), value); } template <typename R, typename T, typename Comp> auto upper_bound(const R& range, const T& value, Comp comp) -> decltype(range.begin()) { return std::upper_bound(range.begin(), range.end(), value, comp); } template <typename R> auto min_element(const R& range) -> decltype(range.begin()) { return std::min_element(range.begin(), range.end()); } template <typename R> auto max_element(const R& range) -> decltype(range.begin()) { return std::max_element(range.begin(), range.end()); } template <typename R> bool next_permutation(R& range) { return std::next_permutation(range.begin(), range.end()); } template <typename T> void unique(std::vector<T>& range) { range.erase(std::unique(range.begin(), range.end()), range.end()); } template <typename R> R sorted(R range) { sort(range); return range; } template <typename R, typename Comp> R sorted(R range, Comp comp) { sort(range, comp); return range; } template <typename R> R reversed(R range) { reverse(range); return range; } template <typename T> T gcd(T a, T b) { while (b) { T tmp = a % b; a = b; b = tmp; } return a; } using namespace std; class TaskC { public: void solve(std::istream& in, std::ostream& out) { int n; in >> n; vector<int> v(n); for (int i : range(26)) { in >> v[i]; } auto x = solve(v); out << x.first << n << x.second; } pair<int, string> solve(vector<int> v) { int cntOdd = 0; char odd; for (int i : range(v.size())) { if (v[i] % 2 == 1) { ++cntOdd; odd = a + i; } } if (cntOdd > 1) { return {0, go(v)}; } if (cntOdd == 1) { int g = 0; for (int i : range(v.size())) { g = gcd(g, v[i]); } auto r = go(v, 2 * g); r = r + odd + reversed(r); string res; for (int i = 0; i < g; ++i) { res += r; } return {g, res}; } int g = 0; for (int i : range(v.size())) { g = gcd(g, v[i]); } assert(g % 2 == 0); string r = go(v, g); r = r + reversed(r); string res; for (int i = 0; i < g / 2; ++i) { res += r; } return {g, res}; } string go(vector<int> v, int del = 1) { string res; for (int i : range(v.size())) { res += string(v[i] / del, char( a + i)); } return res; } }; int main() { std::ios_base::sync_with_stdio(false); TaskC solver; std::istream& in(std::cin); std::ostream& out(std::cout); in.tie(0); out << std::fixed; out.precision(20); solver.solve(in, out); return 0; }
|
/*
* CameraOneFrame architecture
*
* Copyright (c) 2014,
* Luca Maggiani <>
* Scuola Superiore Sant'Anna (http://www.sssup.it) and
* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
* (http://www.cnit.it).
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* eshift_reg module
* Created by LMag 2013
*
* Enhanced Shift Register for GradientHW configuration
*
*
* 8Mag13 v1.0 - first release
*
*
*
* TO DO:
*
*/
module eshift_reg (
clk,
clken,
shiftin,
shiftout,
taps,
aclr,
res_config
);
input clk, clken, aclr;
input [7:0] shiftin;
output [7:0] shiftout, taps;
input [7:0] res_config;
parameter WIDTH_64 = 8'd0;
parameter WIDTH_128 = 8'd1;
parameter WIDTH_192 = 8'd2;
parameter WIDTH_256 = 8'd3;
parameter WIDTH_320 = 8'd4;
parameter WIDTH_640 = 8'd5;
parameter WIDTH_960 = 8'd6;
parameter WIDTH_1280 = 8'd7;
/* ############################################# */
/* Power management HDL - work in progress */
/* ############################################# */
wire clken0, clken1, clken2, clken3, clken4, clken5, clken6, clken7;
//reg clken0, clken1, clken2, clken3, clken4;
// testing code
//assign clken0 = clken;
//assign clken1 = (res_config > WIDTH_64) ? clken : 1'b0;
//assign clken2 = (res_config > WIDTH_128) ? clken : 1'b0;
//assign clken3 = (res_config > WIDTH_192) ? clken : 1'b0;
//assign clken4 = (res_config > WIDTH_256) ? clken : 1'b0;
assign clken0 = clken;
assign clken1 = clken;
assign clken2 = clken;
assign clken3 = clken;
assign clken4 = clken;
assign clken5 = clken;
assign clken6 = clken;
assign clken7 = clken;
/* ############################################# */
/* ######## Shift multiplex controller ######### */
/* ############################################# */
wire [7:0] in0, in1, in2, in3, in4, in5, in6, in7;
wire [7:0] out0, out1, out2, out3, out4, out5, out6, out7;
assign in0 = shiftin;
reg [7:0] shiftout;
always@(*)
begin
case(res_config)
WIDTH_64: shiftout = out0;
WIDTH_128: shiftout = out1;
WIDTH_192: shiftout = out2;
WIDTH_256: shiftout = out3;
WIDTH_320: shiftout = out4;
WIDTH_640: shiftout = out5;
WIDTH_960: shiftout = out6;
WIDTH_1280: shiftout = out7;
default:
shiftout = 8'd0;
endcase
end
assign in1 = out0;
assign in2 = out1;
assign in3 = out2;
assign in4 = out3;
assign in5 = out4;
assign in6 = out5;
assign in7 = out6;
/*#############################################*/
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(61),
.width(8)
) altshift_taps_inst_0 (
.clock (clk),
.clken (clken0),
.shiftin (in0),
.shiftout (out0),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(64),
.width(8)
) altshift_taps_inst_1 (
.clock (clk),
.clken (clken1),
.shiftin (in1),
.shiftout (out1),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(64),
.width(8)
) altshift_taps_inst_2 (
.clock (clk),
.clken (clken2),
.shiftin (in2),
.shiftout (out2),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(64),
.width(8)
) altshift_taps_inst_3 (
.clock (clk),
.clken (clken3),
.shiftin (in3),
.shiftout (out3),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(64),
.width(8)
) altshift_taps_inst_4 (
.clock (clk),
.clken (clken4),
.shiftin (in4),
.shiftout (out4),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(320),
.width(8)
) altshift_taps_inst_5 (
.clock (clk),
.clken (clken5),
.shiftin (in5),
.shiftout (out5),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(320),
.width(8)
) altshift_taps_inst_6 (
.clock (clk),
.clken (clken6),
.shiftin (in6),
.shiftout (out6),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
altshift_taps
#(
.lpm_hint("RAM_BLOCK_TYPE=M9K"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(320),
.width(8)
) altshift_taps_inst_7 (
.clock (clk),
.clken (clken7),
.shiftin (in7),
.shiftout (out7),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const double PI = acos(-1.0); long long f[555], n; string g[] = { < , ^ , > , v }; string s, t; int main() { cin >> s >> t; cin >> n; if (n % 2 == 0) { cout << undefined ; return 0; } for (int i = 0; i < 4; i++) if (s == g[i]) { if (g[(i + (n % 4)) % 4] == t) cout << cw ; else cout << ccw ; } }
|
#include <bits/stdc++.h> using namespace std; struct Trie { struct Node { char c; vector<pair<int, int> > n; Node* ch[26]; Node(char ch) { this->c = ch; for (int i = 0; i < 26; i++) this->ch[i] = NULL; } }; Node* root; vector<pair<int, int> > res; int sum; Trie() { root = new Node( ); sum = 0; } void create(string s, int t, int ind) { Node* now = root; for (int i = 0; i < s.size(); i++) { if (now->ch[s[i] - a ] == NULL) now = now->ch[s[i] - a ] = new Node(s[i]); else now = now->ch[s[i] - a ]; } (now->n).push_back(make_pair(ind, t)); } pair<vector<int>, vector<int> > dfs(Node* now, int depth) { vector<int> O, P; for (int i = 0; i < 26; i++) if (now->ch[i] != NULL) { pair<vector<int>, vector<int> > t = dfs(now->ch[i], depth + 1); O.insert(O.end(), t.first.begin(), t.first.end()); P.insert(P.end(), t.second.begin(), t.second.end()); } vector<pair<int, int> > t = now->n; for (int i = 0; i < t.size(); i++) if (t[i].second == 1) O.push_back(t[i].first); else if (t[i].second == 2) P.push_back(t[i].first); while (O.size() && P.size()) { sum += depth; res.push_back(make_pair(O[0], P[0])); O.erase(O.begin()); P.erase(P.begin()); } return make_pair(O, P); } void doit() { dfs(root, 0); printf( %d n , sum); for (int i = 0; i < res.size(); i++) printf( %d %d n , res[i].first, res[i].second); } }; int main() { Trie trie; string s; int n; scanf( %d n , &n); for (int i = 1; i <= 2; i++) for (int j = 1; j <= n; j++) { cin >> s; trie.create(s, i, j); } trie.doit(); }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int maxn = 200000 + 10; inline void read(int &x) { int f = 1; x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } inline void readll(long long &x) { long long f = 1; x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } long long n, q; long long a[maxn], k, Prefix[maxn], last, cur; void BinarySearch() { if (last + k < a[cur]) { last += k; return; } long long l = cur, r = n, ans = 0; while (l <= r) { long long mid = (l + r) >> 1; if (Prefix[mid] - Prefix[cur - 1] - last <= k) ans = mid, l = mid + 1; else r = mid - 1; } if (ans == n) { last = 0; cur = 1; return; } ans++; long long ttt = Prefix[ans] - Prefix[cur - 1] - last - k; last = a[ans] - ttt; cur = ans; } int main() { readll(n), readll(q); for (long long i = 1; i <= n; i++) { readll(a[i]), Prefix[i] = Prefix[i - 1] + a[i]; } last = 0; cur = 1; for (long long i = 1; i <= q; i++) { readll(k); BinarySearch(); printf( %I64d n , n - cur + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1e9; const long long LINF = INF * (long long)INF + 100; const double EPS = 1e-7; const int MAX = 20 * 1000 + 47; const int MAS = 2 * 1e5 + 10; const int MOD = 998244353; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> s(n); for (int i = (0); i < (n); i++) { cin >> s[i]; } vector<vector<int>> g(n); vector<string> s1(n); vector<vector<int>> p(n * m, vector<int>(21)); for (int i = (0); i < (n); i++) { cin >> s1[i]; for (int j = (0); j < (m); j++) { int num = i * m + j; if (s1[i][j] == R ) { p[num][0] = num + 1; } if (s1[i][j] == L ) { p[num][0] = num - 1; } if (s1[i][j] == U ) { p[num][0] = num - m; } if (s1[i][j] == D ) { p[num][0] = num + m; } } } for (int k = (1); k < (21); k++) { for (int i = (0); i < (n * m); i++) { p[i][k] = p[p[i][k - 1]][k - 1]; } } set<int> all; set<int> black; for (int i = (0); i < (n); i++) for (int j = (0); j < (m); j++) { int num = (i * m + j); int p1 = p[num][20]; all.insert(p1); if (s[i][j] == 0 ) { black.insert(p1); } } cout << all.size() << << black.size() << endl; } }
|
#include <bits/stdc++.h> using namespace std; template <typename _T> void read(_T &x) { _T f = 1; x = 0; char s = getchar(); while (s > 9 || s < 0 ) { if (s == - ) f = -1; s = getchar(); } while ( 0 <= s && s <= 9 ) { x = (x << 3) + (x << 1) + (s ^ 48); s = getchar(); } x *= f; } struct ming { long long typ, t, x, id, pos; } a[100010]; long long n, ans[100010], num[100010]; vector<long long> vec; long long cmp1(const ming &a, const ming &b) { return a.t < b.t; } long long cmp2(const ming &a, const ming &b) { return a.id < b.id; } void merge(long long l, long long r) { if (l == r) return; long long mid = l + r >> 1, j = l; merge(l, mid); merge(mid + 1, r); sort(a + l, a + mid + 1, cmp1); sort(a + mid + 1, a + r + 1, cmp1); for (long long i = mid + 1; i <= r; i++) { while (j <= mid && a[j].t <= a[i].t) num[a[j].pos] += a[j].typ, j++; if (!a[i].typ) ans[a[i].id] += num[a[i].pos]; } for (long long i = l; i < j; i++) num[a[i].pos] -= a[i].typ; } signed main() { read(n); for (long long i = 1; i <= n; i++) { read(a[i].typ); read(a[i].t); read(a[i].x); if (a[i].typ == 2) a[i].typ = -1; if (a[i].typ == 3) a[i].typ = 0; a[i].id = i; vec.push_back(a[i].x); } sort(vec.begin(), vec.end()); vec.erase(unique(vec.begin(), vec.end()), vec.end()); for (long long i = 1; i <= n; i++) a[i].pos = lower_bound(vec.begin(), vec.end(), a[i].x) - vec.begin() + 1; merge(1, n); sort(a + 1, a + n + 1, cmp2); for (long long i = 1; i <= n; i++) if (!a[i].typ) printf( %lld n , ans[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e7 + 5; const int M = 25; int A[M], B[M], n, m, x, y, cnt; int dp[M * 4][M * 4]; void Min(int &x, int y) { x = min(x, y); } int main() { cin >> n >> m; for (int i = 0; i < n; ++i) cin >> A[i]; for (int i = 0; i < n; ++i) cin >> B[i]; memset(dp, 0x3f, sizeof(dp)); dp[0][0] = 0; for (int i = 0; i < n * 4; ++i) { for (int j = 0; j <= n + n; ++j) if (dp[i][j] <= 1e9) { Min(dp[i + 1][j + 1], dp[i][j] + A[i % n]); if (j) Min(dp[i + 1][j - 1], dp[i][j] + B[i % n]); } } if (m <= 3) cout << dp[n * m][0] << endl; else cout << dp[n * 4][0] + (m - 4) / 2 * (dp[n * 4][0] - dp[n * 2][0]) << endl; }
|
#include <bits/stdc++.h> using namespace std; string s, v; int ans, p, t; char c; char tr[1000]; int mypow(int k) { int c = 1; for (int i = 1; i <= k; i++) { c *= 2; } return c; } int main() { gets(tr); s = (string)tr; p = 0; for (int i = 0; i < s.length(); i++) { v = ; c = s[i]; int k = 7; ans = 0; while ((c > 0) && (k >= 0)) { if (c % 2 == 1) ans += mypow(k); k--; c /= 2; } t = (p - ans) % 256; if (t < 0) t += 256; cout << t << endl; p = ans; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// ////
//// To Do: ////
//// - add support for other RAM's ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_128x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[31:16]),
.EN(ce),
.WE(we),
.DO(doq[31:16])
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
#include <bits/stdc++.h> using namespace std; const float pi = acos(-1.0); const int maxn = 1e5 + 5; int c[maxn]; long long a[5][maxn], b[maxn]; vector<int> vec[maxn]; void dfs(int u, int fa) { for (auto p : vec[u]) { if (p != fa) { c[p] = 6 - c[u] - c[fa]; dfs(p, u); } } } int main() { int u, v; int t, n; cin >> n; for (int i = 1; i <= 3; i++) for (int j = 1; j <= n; j++) cin >> a[i][j]; int fu, fv; for (int i = 1; i <= n - 1; i++) { cin >> u >> v; vec[u].push_back(v); vec[v].push_back(u); } int cnt = 0, cnt1 = 0; for (int i = 1; i <= n; i++) { if (vec[i].size() == 2) { cnt++; } if (vec[i].size() == 1) { fv = i; cnt1++; } } if (cnt != n - 2 && cnt1 != 2) { puts( -1 ); return 0; } long long res = 1e17, ans = 0; ; for (int i = 1; i <= 3; i++) { for (int j = 1; j <= 3; j++) { if (i == j) continue; fu = vec[fv][0]; c[fu] = i, c[fv] = j; dfs(fu, fv); ans = 0; for (int k = 1; k <= n; k++) ans += a[c[k]][k]; if (ans < res) { res = ans; for (int k = 1; k <= n; k++) { b[k] = c[k]; } } } } printf( %lld n , res); for (int i = 1; i <= n; i++) cout << b[i] << ; cout << endl; }
|
// handles transmission over UART
module uart_tx
(
input wire clk,
input wire reset,
input wire tx_start,
input wire s_tick,
input wire [7:0] din,
output reg tx_done_tick,
output wire tx
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [2:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
reg tx_reg, tx_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
end
// state machine works as follows:
// if it is in idle mode, it waits for a start
// signal to begin, otherwise it continues to send 0s to UART (meaning there is nothing available yet)
// then it goes into start mode once some data has been inputted, it does the write
// starting at START for 8 bits before moving back to idle
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg;
tx_done_tick <= 0;
case (state_reg)
IDLE: begin
tx_next <= 1;
if (tx_start) begin
state_next <= START;
s_next <= 0;
b_next <= din;
end
end
START: begin
tx_next <= 0;
if (s_tick) begin
if (s_reg == 15) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
tx_next <= b_reg[0];
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {1'b0, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
tx_next <= 1;
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
tx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign tx = tx_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int k; int n; int planks[1005]; int g = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> k; for (int t = 0; t < k; t++) { cin >> n; for (int i = 0; i < n; i++) cin >> planks[i]; sort(planks, planks + n, [](int a, int b) { return a > b; }); g = 0; for (int i = 0; i < n; i++) if (planks[i] >= i + 1) g = max(g, i + 1); cout << g << n ; } }
|
#include <bits/stdc++.h> long long A[100000]; using namespace std; int main() { long long n, s = 0, m = -100000, a = 0, p; cin >> n; for (int i = 0; i < n; i++) { cin >> A[i]; if (A[i] % 2 == 0 && A[i] > 0) s += A[i]; } std::sort(A, A + n); for (int i = n - 1; i >= 0; i--) { if (A[i] % 2 != 0 && (A[i] > 0 || (A[i] < 0 && a == 0) || (A[i] < 0 && a % 2 == 0 && A[i] + p > 0))) { a++; p = A[i]; s += p; } } if (a % 2 == 0) s -= p; cout << s; }
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#include <bits/stdc++.h> template <typename _Tp> void read(_Tp &x) { char ch(getchar()); bool f(false); while (!isdigit(ch)) f |= ch == 45, ch = getchar(); x = ch & 15, ch = getchar(); while (isdigit(ch)) x = x * 10 + (ch & 15), ch = getchar(); if (f) x = -x; } template <typename _Tp, typename... Args> void read(_Tp &t, Args &...args) { read(t); read(args...); } const int N = 10000005, mod = 998244353; template <typename _Tp1, typename _Tp2> inline void add(_Tp1 &a, _Tp2 b) { a = a + b >= mod ? a + b - mod : a + b; } template <typename _Tp1, typename _Tp2> inline void sub(_Tp1 &a, _Tp2 b) { a = a - b < 0 ? a - b + mod : a - b; } long long ksm(long long a, long long b = mod - 2) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod, b >>= 1; } return res; } int pw[N], a[N]; void init() { pw[0] = 1; for (int i = 1; i < N; ++i) pw[i] = pw[i - 1], add(pw[i], pw[i - 1]); int mul = 1; for (int i = 1; i < N; ++i) mul = 1ULL * mul * (pw[i] - 1) % mod; a[N - 1] = ksm(mul); for (int i = N - 2; i >= 1; --i) a[i] = 1ULL * a[i + 1] * (pw[i + 1] - 1) % mod; } void MAIN() { int n, k, x; read(n, k, x); if (!x) { if (n > k) return puts( 0 ), void(); int ans = 1; for (int i = 0; i < n; ++i) ans = 1LL * ans * (pw[k] - pw[i] + mod) % mod; printf( %d n , ans); return; } int ans = pw[k] - 1, cur = 1, qwq = ksm(2, n), iq = ksm(2); for (int i = 1, coef = pw[k] - 1; i < k; ++i) { cur = 1ULL * cur * (qwq - 1) % mod, qwq = 1ULL * qwq * iq % mod, coef = 1ULL * coef * (pw[k] - pw[i] + mod) % mod; add(ans, 1ULL * coef * cur % mod * a[i] % mod); } printf( %lld n , ksm(pw[k] - 1) * ans % mod); } int main() { init(); int _; read(_); while (_--) MAIN(); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const long long INF = 1e18; const int maxn = 1e6 + 6; const int mod = 1e9 + 7; const double eps = 1e-9; inline bool read(long long &num) { char in; bool IsN = false; in = getchar(); if (in == EOF) return false; while (in != - && (in < 0 || in > 9 )) in = getchar(); if (in == - ) { IsN = true; num = 0; } else num = in - 0 ; while (in = getchar(), in >= 0 && in <= 9 ) { num *= 10, num += in - 0 ; } if (IsN) num = -num; return true; } long long n, m; struct node { int x, v; bool friend operator<(node a, node b) { return a.x < b.x; } } save[maxn]; vector<int> v; long long a[maxn], b[maxn]; int nn; void update(long long *p, int pos, long long x) { while (pos <= nn) { p[pos] += x; pos += pos & -pos; } } long long GetSum(long long *p, long long x) { long long ans = 0; while (x > 0) { ans += p[x]; x -= x & -x; } return ans; } int getid(long long x) { return lower_bound(v.begin(), v.end(), x) - v.begin() + 1; } int main() { read(n); for (int i = 1; i <= n; i++) scanf( %d , &save[i].x); for (int i = 1; i <= n; i++) { scanf( %d , &save[i].v); v.push_back(save[i].v); } sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); nn = v.size(); sort(save + 1, save + 1 + n); long long ans = 0; for (int i = 1; i <= n; i++) { int id = getid(save[i].v); long long tempx = GetSum(b, id); long long tempy = GetSum(a, id); ans += tempx * save[i].x - tempy; update(b, id, 1); update(a, id, save[i].x); } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j; cin >> n >> m; for (i = 1; i <= n; i++) { int c = i / 2; if (i % 2 != 0) { for (j = 0; j < m; j++) { cout << # ; } cout << endl; } else if (c % 2 == 0) { cout << # ; for (j = 1; j < m; j++) { cout << . ; } cout << endl; } else if (c % 2 != 0) { for (j = 1; j < m; j++) { cout << . ; } cout << # << endl; } } return 0; }
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// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, amazing = 0, maxx, minn, k; cin >> n; cin >> k; maxx = k; minn = k; for (int i = 1; i < n; i++) { cin >> k; if (k > maxx) { maxx = k; amazing++; } else if (k < minn) { minn = k; amazing++; } } cout << amazing << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double PI = acos(-1.0); const long long int mod = 1e9 + 7; const int MAXN = 1e6 + 5; void cp() { int n, k; string s; cin >> n >> k >> s; vector<pair<int, int> > group; int l = 0, r = 0; while (l < n) { while (l < n && s[l] == L ) l++; if (l >= n) break; r = l; while (r + 1 < n && s[r + 1] == W ) r++; group.push_back({l, r}); l = r + 1; } vector<pair<int, int> > diff; for (int i = 0; i < ((int)group.size()) - 1; i++) { int d = group[i + 1].first - group[i].second - 1; diff.push_back({d, i}); } sort(diff.rbegin(), diff.rend()); while (k > 0 && !diff.empty()) { pair<int, int> last = diff.back(); diff.pop_back(); int can = min(last.first, k); k -= can; for (int i = group[last.second].second + 1; i < group[last.second + 1].first && can > 0; i++, can--) s[i] = W ; } if (k > 0) { int pos = -2; for (int i = 0; i < n; i++) if (s[i] == W ) pos = i; pos++; if (pos >= 0 && pos < n) for (int i = pos; i < n && k > 0; i++) if (s[i] == L ) s[i] = W , k--; } if (k > 0 && s[0] == L ) { int pos = n; for (int i = 0; i < n && pos == n; i++) if (s[i] == W ) pos = i; pos--; if (pos >= 0) { for (int i = pos; i >= 0 && k > 0; i--) if (s[i] == L ) s[i] = W , k--; } } int score = 0; for (int i = 0; i < n; i++) { score += (s[i] == W ); if (i - 1 >= 0 && s[i] == W && s[i - 1] == W ) score++; } cout << score << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; t = 1; cin >> t; while (t--) { cp(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = (1e5 + 5) * 2; void Max(int &x, int y) { if (x < y) x = y; } int n, m; int a[MAXN]; int dp[MAXN]; bool chk1(int s, int x) { memset(dp, 0, sizeof(dp)); for (int i = s, iend = s + n - 1; i <= iend; ++i) { int d = a[i + 1] - a[i] - 1; if (dp[i] + x < d) return false; if (dp[i] >= d) Max(dp[i + 1], x); if (dp[i] + x >= a[i + 2] - a[i] - 1) Max(dp[i + 2], x - (a[i + 2] - a[i + 1])); } int t = s + n - 1, d = a[s] - a[s - 1] - 1; if (dp[t] + x < d) return false; else return true; } bool chk2(int s, int x) { memset(dp, 0, sizeof(dp)); if (x < a[s + 1] - a[s] - 1) return false; Max(dp[s + 1], x - (a[s + 1] - a[s])); for (int i = s + 1, iend = s + n - 1; i <= iend; ++i) { int d = a[i + 1] - a[i] - 1; if (dp[i] + x < d) return false; if (dp[i] >= d) Max(dp[i + 1], x); if (dp[i] + x >= a[i + 2] - a[i] - 1) Max(dp[i + 2], x - (a[i + 2] - a[i + 1])); } int t = s + n - 1, d = a[s + 1] - a[s - 1] - 1; if (dp[t] + x < d) return false; else return true; } bool check(int x) { int s = -1; for (int i = 1, iend = n; i <= iend; ++i) { if (a[i + 1] - a[i] > x + 1) s = i + 1; } if (s == -1) return true; else return chk1(s, x) || chk2(s, x); } int main() { cin >> m >> n; for (int i = 1, iend = n; i <= iend; ++i) scanf( %d , &a[i]); for (int i = 1, iend = n; i <= iend; ++i) a[i + n] = m + a[i]; if (n == 1) { cout << m - 1 << endl; return 0; } int l = 0, r = m, res; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) res = mid, r = mid - 1; else l = mid + 1; } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 110000; int n, q; map<pair<int, int>, int> M; int u[maxn], v[maxn]; int s[maxn], e[maxn]; vector<int> V[maxn << 4]; struct DSU { int fa[maxn], col[maxn], sz[maxn]; stack<pair<pair<int *, int>, int>> stk; int findfa(int x, int &val) { val ^= col[x]; return x == fa[x] ? x : findfa(fa[x], val); } void init() { for (int i = 1; i <= n; i++) fa[i] = i, col[i] = 0, sz[i] = 1; } bool dsunion(int x, int y, int t) { int cx = 0, cy = 0; int fx = findfa(x, cx), fy = findfa(y, cy); if (fx == fy) return cx ^ cy; if (sz[fx] > sz[fy]) swap(fx, fy); stk.push({{&fa[fx], fa[fx]}, t}); fa[fx] = fy; stk.push({{&sz[fy], sz[fy]}, t}); sz[fy] += sz[fx]; stk.push({{&col[fx], col[fx]}, t}); col[fx] = cx ^ cy ^ 1; return 1; } void goback(int t) { while (!stk.empty()) { if (stk.top().second != t) break; (*stk.top().first.first) = stk.top().first.second; stk.pop(); } } } dsu; void Add(int L, int R, int val, int l, int r, int rt) { if (L <= l && R >= r) { V[rt].push_back(val); return; } int m = (l + r) >> 1; if (L <= m) Add(L, R, val, l, m, rt << 1); if (R > m) Add(L, R, val, m + 1, r, rt << 1 | 1); } void solve(int l, int r, int rt) { for (int i = 0; i < V[rt].size(); i++) { int _ = V[rt][i]; if (!dsu.dsunion(u[_], v[_], rt)) { for (int j = l; j <= r; j++) puts( NO ); dsu.goback(rt); return; } } if (l == r) puts( YES ); else { int m = (l + r) >> 1; solve(l, m, rt << 1); solve(m + 1, r, rt << 1 | 1); } dsu.goback(rt); } int main() { int cnt = 0; scanf( %d%d , &n, &q); dsu.init(); for (int i = 1; i <= q; i++) { int uu, vv; scanf( %d%d , &uu, &vv); if (!M.count({uu, vv})) { ++cnt; u[cnt] = uu, v[cnt] = vv; M[{uu, vv}] = cnt; s[cnt] = i; } else { e[M[{uu, vv}]] = i - 1; M.erase({uu, vv}); } } for (auto it = M.begin(); it != M.end(); it++) e[it->second] = q; for (int i = 1; i <= cnt; i++) Add(s[i], e[i], i, 1, q, 1); solve(1, q, 1); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; vector<int> a[100010]; int x; int now; void print() { cout << YES << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << a[i][j] << ; cout << endl; } } int main() { cin >> n >> m; now = 1; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { a[i].push_back(now); now += 1; } if (n == 1 && m == 1) { cout << YES << endl; cout << 1; return 0; } if (n * m == 2) { cout << NO ; return 0; } if (n * m == 3) { cout << NO ; return 0; } if (n == 2 && m == 2) { cout << NO ; return 0; } if (n * m == 6 && min(n, m) == 2) { cout << NO ; return 0; } if (n == 3 && m == 3) { cout << YES << endl; cout << 6 1 8 << endl; cout << 7 5 3 << endl; cout << 2 9 4 << endl; return 0; } if (n == 1 && m >= 4) { now = 0; for (int i = 2; i <= m; i += 2) { a[0][now] = i; now += 1; } for (int i = 1; i <= m; i += 2) { a[0][now] = i; now += 1; } print(); return 0; } if (m == 1 && n >= 4) { now = 0; for (int i = 2; i <= n; i += 2) { a[now][0] = i; now += 1; } for (int i = 1; i <= n; i += 2) { a[now][0] = i; now += 1; } print(); return 0; } if (m >= 4) { for (int i = 0; i < n; i++) if (i % 2 == 0) { int tmp0 = a[i][m - 2]; int tmp1 = a[i][m - 1]; for (int j = m - 1; j >= 2; j--) a[i][j] = a[i][j - 2]; a[i][1] = tmp1; a[i][0] = tmp0; } for (int i = 0; i < m; i++) if (i % 2 == 0) { int tmp0 = a[0][i]; for (int j = 0; j < n - 1; j++) a[j][i] = a[j + 1][i]; a[n - 1][i] = tmp0; } print(); return 0; } if (n >= 4) { for (int i = 0; i < m; i++) if (i % 2 == 0) { int tmp0 = a[n - 2][i]; int tmp1 = a[n - 1][i]; for (int j = n - 1; j >= 2; j--) a[j][i] = a[j - 2][i]; a[1][i] = tmp1; a[0][i] = tmp0; } for (int i = 0; i < n; i++) if (i % 2 == 0) { int tmp0 = a[i][0]; for (int j = 0; j < m - 1; j++) a[i][j] = a[i][j + 1]; a[i][m - 1] = tmp0; } print(); return 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; int l[100000], r[100000], u[100000], d[100000]; int dp[2], dp2[2]; int main() { int i; int n, m, q; char c; scanf( %d %d %d , &n, &m, &q); for (i = 0; i < n; i++) scanf( %c , &c), l[i] = (c == B ); for (i = 0; i < n; i++) scanf( %c , &c), r[i] = (c == B ); for (i = 0; i < m; i++) scanf( %c , &c), u[i] = (c == B ); for (i = 0; i < m; i++) scanf( %c , &c), d[i] = (c == B ); for (i = 0; i < n; i++) dp[!l[i]]++; dp[!u[0]]++, dp[!d[0]]++; for (i = 1; i < m; i++) { dp2[0] = min(dp[0], dp[1] + n) + u[i] + d[i]; dp2[1] = min(dp[1], dp[0] + n) + !u[i] + !d[i]; swap(dp, dp2); } for (i = 0; i < n; i++) dp[!r[i]]++; int ans = min(dp[0], dp[1]); dp[0] = dp[1] = 0; for (i = 0; i < m; i++) dp[!u[i]]++; dp[!l[0]]++, dp[!r[0]]++; for (i = 1; i < n; i++) { dp2[0] = min(dp[0], dp[1] + m) + l[i] + r[i]; dp2[1] = min(dp[1], dp[0] + m) + !l[i] + !r[i]; swap(dp, dp2); } for (i = 0; i < m; i++) dp[!d[i]]++; ans = min(ans, min(dp[0], dp[1])); printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A211O_BEHAVIORAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(const T& a) { return a * a; } const long double EPS = 1e-9; const long double PI = 2 * acos(0.0); const int N = 100000; int counts[N]; int xors[N]; vector<int> g[N]; queue<int> qq; vector<pair<int, int> > ans; inline void Add(int x, int y) { ans.push_back({x, y}); g[x].push_back(y); g[y].push_back(x); if (int(g[x].size()) + 1 == counts[x]) qq.push(x); if (int(g[y].size()) + 1 == counts[y]) qq.push(y); } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &counts[i], &xors[i]); if (counts[i] == 1) qq.push(i); } while (!qq.empty()) { int x = qq.front(); qq.pop(); assert(counts[x] >= int(g[x].size())); if (counts[x] != 1 + int(g[x].size())) continue; int s = 0; for (int to : g[x]) { s ^= to; } Add(x, xors[x] ^ s); } printf( %d n , int(ans.size())); for (pair<int, int>& p : ans) printf( %d %d n , p.first, p.second); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007, inf = 1000000000; const int N = 100010; inline int read() { char ch; while (!isdigit(ch = getchar())) ; int x = ch - 0 ; while (isdigit(ch = getchar())) x = (x << 1) + (x << 3) + ch - 0 ; return x; } int n, cnt; int a[N], last[N]; long long f[N][2]; struct edge { int to, next; } e[N << 1]; void insert(int u, int v) { e[++cnt].to = v; e[cnt].next = last[u]; last[u] = cnt; e[++cnt].to = u; e[cnt].next = last[v]; last[v] = cnt; } void dfs(int x, int fa) { long long t1, t2; if (a[x] == 1) f[x][1] = 1; f[x][0] = f[x][1] ^ 1; for (int i = last[x]; i; i = e[i].next) if (e[i].to != fa) { int y = e[i].to; dfs(y, x); t1 = f[x][0] * (f[y][0] + f[y][1]); t2 = (f[x][1] * (f[y][0] + f[y][1]) + f[x][0] * f[y][1]); f[x][0] = t1 % mod; f[x][1] = t2 % mod; } } int main() { n = read(); for (int i = 1; i < n; i++) insert(read(), i); for (int i = 0; i < n; i++) a[i] = read(); dfs(0, 0); cout << f[0][1] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n < 4) printf( NO n ); else if (n % 2) { printf( YES n ); printf( 1 + 5 = 6 n3 - 2 = 1 n4 * 6 = 24 n24 * 1 = 24 n ); for (int j = n; j > 6; j -= 2) { printf( %d - %d = 1 n , j, j - 1); printf( 24 * 1 = 24 n ); } } else { printf( YES n ); printf( 1 * 2 = 2 n2 * 3 = 6 n6 * 4 = 24 n ); for (int j = n; j > 5; j -= 2) { printf( %d - %d = 1 n , j, j - 1); printf( 24 * 1 = 24 n ); } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR2_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int main(void) { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> ans1, ans2; string a, b; cin >> a >> b; a = a + 0 ; b = b + 0 ; for (int i = 0; i < n; i++) { if (a[i] != a[i + 1]) ans1.push_back(i); } for (int i = 0; i < n; i++) { if (b[i] != b[i + 1]) ans2.push_back(i); } cout << ans1.size() + ans2.size() << ; for (int i = 0; i < ans1.size(); i++) cout << ans1[i] + 1 << ; for (int i = ans2.size() - 1; i >= 0; i--) cout << ans2[i] + 1 << ; cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, a = 0, b = 0; int t; for (int i = 0; i < 3; ++i) { cin >> t; a += t; } a = (a + 4) / 5; for (int i = 0; i < 3; ++i) { cin >> t; b += t; } b = (b + 9) / 10; cin >> n; if (a + b > n) printf( NO ); else printf( YES ); return 0; }
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#include <bits/stdc++.h> using namespace std; void getmax(int &a, const int b) { if (b > a) a = b; } struct Segment { int l, r; Segment() {} Segment(const int _l, const int _r) : l(_l), r(_r) {} bool operator<(const Segment &s) const { return l != s.l ? l < s.l : r > s.r; } }; vector<Segment> SEG[100][100]; int N; void RemoveCovering(vector<Segment> &s) { sort(s.begin(), s.end()); vector<Segment> ans; for (int i = 0, j; i < (int)s.size();) { ans.push_back(s[i]); for (j = i + 1; j < (int)s.size() && s[j].r <= s[i].r; j++) ; i = j; } s.clear(), ans.swap(s); } void Insert(vector<Segment> &ans, const vector<Segment> &ls, const vector<Segment> &rs) { for (const Segment &s : ls) ans.push_back(s); for (const Segment &s : rs) ans.push_back(s); if (ls.empty() || rs.empty()) return; for (int i = 0, j = 0; i < (int)ls.size(); i++) { while (j + 1 < (int)rs.size() && rs[j + 1].l <= ls[i].r) j++; if (rs[j].l <= ls[i].r && rs[j].r >= ls[i].l) ans.push_back(Segment(ls[i].l, rs[j].r)); } } int M; int DP[101][301]; vector<int> VALS; int Id(const int v) { return lower_bound(VALS.begin(), VALS.end(), v) - VALS.begin(); } int main() { while (scanf( %d , &N) == 1) { if (true) { vector<Segment> tmp; for (int i = 0; i < N; i++) { static Segment s; scanf( %d%d , &s.l, &s.r); tmp.push_back(s); } sort(tmp.begin(), tmp.end()); for (int i = 0; i < N; i++) for (int j = i; j < N; j++) SEG[i][j].clear(); VALS.clear(); for (int i = 0; i < N; i++) { const int a = tmp[i].l, l = tmp[i].r; SEG[i][i].push_back(Segment(a - l, a)); SEG[i][i].push_back(Segment(a, a + l)); VALS.push_back(a - l), VALS.push_back(a), VALS.push_back(a + l); } tmp.clear(), vector<Segment>().swap(tmp); } if (true) { auto &s = VALS; sort(s.begin(), s.end()), s.resize(unique(s.begin(), s.end()) - s.begin()); M = s.size(); } for (int gap = 1; gap < N; gap++) { for (int i = 0; i + gap < N; i++) { const int j = i + gap; for (int k = i; k < j; k++) { Insert(SEG[i][j], SEG[i][k], SEG[k + 1][j]); Insert(SEG[i][j], SEG[k + 1][j], SEG[i][k]); } RemoveCovering(SEG[i][j]); } } for (int i = 0; i <= M; i++) DP[0][i] = 0; for (int i = 1; i <= N; i++) { for (int j = 0; j <= M; j++) DP[i][j] = DP[i - 1][j]; for (int j = 1; j <= i; j++) for (const auto &s : SEG[j - 1][i - 1]) { const int l = Id(s.l) + 1; for (int k = Id(s.r) + 1; k <= M; k++) getmax(DP[i][k], DP[j - 1][l - 1] + (s.r - s.l)); } } const int ans = DP[N][M]; printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 300010; long long p, q, b; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } bool ok() { long long m = gcd(p, q); q /= m; m = b; while (q != 1) { m = gcd(q, m); q /= m; if (m == 1) break; } if (q == 1) return true; return false; } int main() { int t; scanf( %d , &t); while (t--) { scanf( %I64d%I64d%I64d , &p, &q, &b); if (!p || ok()) printf( Finite n ); else printf( Infinite n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int base = 13331; const int MOD = 1e9 + 7; const int MOD1 = 998244353; const int mod = 65536; const long long INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; const int N = 1e6 + 10, M = 20000010; const int NN = 3e5 + 10; inline long long read() { char ch = getchar(); long long f = 1, x = 0; while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, k, idx = 0; int c[N], ex[N], ey[N]; bool vis[N]; map<pair<int, int>, int> mp; vector<int> ve[N]; struct Undo_Dsu { stack<pair<int, int> > st; int fa[N], siz[N]; void init() { while (!st.empty()) st.pop(); for (int i = 1; i <= 2 * n + 1; i++) fa[i] = i, siz[i] = 1; } int getrt(int x) { return x == fa[x] ? x : getrt(fa[x]); } bool merge(int u, int v) { int fax = getrt(u), fay = getrt(v); if (fax == fay) return false; if (siz[fax] > siz[fay]) swap(fax, fay), swap(u, v); fa[fax] = fay, siz[fay] += siz[fax]; st.push({fax, fay}); return true; } void undo() { pair<int, int> no = st.top(); fa[no.first] = no.first; siz[no.second] -= siz[no.first]; st.pop(); } } dsu; int main() { n = read(), m = read(), k = read(); dsu.init(); for (int i = 1; i <= n; i++) c[i] = read(); int u, v; long long cnt = k; for (int i = 1; i <= m; i++) { u = read(), v = read(); ex[i] = u, ey[i] = v; if (c[u] == c[v]) { int fx = dsu.getrt(u); int fy = dsu.getrt(v); if (fx == fy) { if (!vis[c[u]]) { vis[c[u]] = 1; --cnt; } } else dsu.merge(u, v + n), dsu.merge(v, u + n); } } long long ans = cnt * (cnt - 1) / 2; for (int i = 1; i <= m; i++) { if (c[ex[i]] != c[ey[i]] && !vis[c[ex[i]]] && !vis[c[ey[i]]]) { int lc = c[ex[i]], rc = c[ey[i]]; if (lc > rc) swap(lc, rc); int id = mp[make_pair(lc, rc)]; if (!id) id = mp[make_pair(lc, rc)] = ++idx; ve[id].push_back(i); } } for (auto in : mp) { int w = in.second; int now = dsu.st.size(); for (auto v : ve[w]) { int uid = ex[v], vid = ey[v]; int fu = dsu.getrt(uid), fv = dsu.getrt(vid); if (fu == fv) { --ans; break; } dsu.merge(uid, vid + n); dsu.merge(vid, uid + n); } while (dsu.st.size() > now) dsu.undo(); } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); if ((a + b) == c || (c + b) == a || (a + c) == b) { printf( 1 ); } else { if ((a + b) < c) { printf( %d , (c - b - a + 1)); } else if (b + c < a) { printf( %d , (a - b - c + 1)); } else if (c + a < b) { printf( %d , (b - c - a + 1)); } else { printf( 0 ); } } return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:10000000 ) using namespace std; template <typename T> inline T abs(T a) { return ((a < 0) ? -a : a); } template <typename T> inline T sqr(T a) { return a * a; } const int INF = (int)1E9 + 7; const long double EPS = 1E-9; const long double PI = 3.1415926535897932384626433832795; const int NMAX = 200 * 1000; int a[NMAX], sza; int t[NMAX * 4], cnt[NMAX * 4]; long long sum[NMAX * 4][5]; char buf[300]; void upd(int pos, int idx, int lf, int rg) { if (lf == rg) { t[idx] ^= 1; memset(sum[idx], 0, sizeof sum[idx]); sum[idx][0] = t[idx] * 1LL * a[pos]; cnt[idx] = t[idx]; return; } int mid = (lf + rg) >> 1; if (pos <= mid) upd(pos, 2 * idx + 1, lf, mid); else upd(pos, 2 * idx + 2, mid + 1, rg); cnt[idx] = cnt[2 * idx + 1] + cnt[2 * idx + 2]; for (int i = 0; i < int(5); ++i) { long long& ans = sum[idx][i]; int f = (cnt[2 * idx + 1]) % 5; f = (i - f + 5) % 5; ans = sum[2 * idx + 1][i] + sum[2 * idx + 2][f]; } } void change(int val) { int pos = lower_bound(a, a + sza, val) - a; upd(pos, 0, 0, sza - 1); } inline long long getSum() { return sum[0][2]; } int main() { int n; scanf( %d , &n); gets(buf); vector<pair<int, int> > q; for (int i = 0; i < int(n); ++i) { gets(buf); if (buf[0] == a ) { int val; sscanf(buf, add %d , &val); q.push_back(make_pair(1, val)); a[sza++] = val; } if (buf[0] == d ) { int val; sscanf(buf, del %d , &val); q.push_back(make_pair(-1, val)); a[sza++] = val; } if (buf[0] == s ) { q.push_back(make_pair(-1, -1)); } } sort(a, a + sza); sza = unique(a, a + sza) - a; for (int i = 0; i < int(n); ++i) { if (q[i] == pair<int, int>(-1, -1)) { printf( %I64d n , getSum()); continue; } if (q[i].first == 1) { change(q[i].second); } else { change(q[i].second); } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int s1[n]; int s2[n]; for (int i = 0; i < n; i++) cin >> s1[i]; for (int i = 0; i < n; i++) cin >> s2[i]; for (int i = 0; i < n; i++) s1[i]--, s2[i]--; int arr[n]; for (int i = 0; i < n; i++) { arr[s2[i]] = i; } for (int i = 0; i < n - 1; i++) { if (arr[s1[i]] > arr[s1[i + 1]]) { cout << n - 1 - i << n ; return 0; } } cout << 0 n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (a == 0 && b == 0) { cout << NO ; return 0; } if (abs(a - b) <= 1) cout << YES ; else cout << NO ; }
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#include <bits/stdc++.h> using namespace std; int main() { string s, p = ; cin >> s; int i, j = 0, f = 0, start, end; for (i = s.size() - 1; i >= 0 && f == 0; i--) { if (s[i] != 0 ) { end = i; f = 1; } } f = 0; for (i = 0; i < s.size() && f == 0; i++) { if (s[i] != 0 ) { start = i; f = 1; } } j = 0; for (i = end; i >= start; i--) { p[j] = s[i]; j++; } j = 0; f = 0; for (i = start; i <= end && f == 0; i++) { if (p[j] != s[i]) f = 1; else j++; } if (f) cout << NO << endl; else cout << YES << endl; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
c <= a | b;
// verilator lint_on COMBDLY
end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
parameter CONSTANT = 1;
always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
f = e;
end
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
a <= 32'hfeed0000;
b <= 32'h0000face;
end
if (cyc==2) begin
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
if (g != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
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/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming decoder
*/
module ham_15_11_decoder (c,q);
// Output signals representing the 11-bit decoded vector
output reg [10:0] q;
// Input signals representing the 15-bit input
input [14:0] c;
// Declare "reg" signals...
// Parity bits for Hamming decoding - P's (P primes)
reg [3:0] pb;
// Syndrome bits for Hamming decoding
reg [3:0] s;
// Temporary variable to contain the conversion from binary to decimal
//real temp;
reg [3:0] temp;
// Temporary storage for inputs
reg [14:0] inputs;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
/*
* Determine for each parity prime bit, what code bits
* is it made of
*/
pb[0]=c[2]^c[4]^c[6]^c[8]^c[10]^c[12]^c[14];
pb[1]=c[2]^c[5]^c[6]^c[9]^c[10]^c[13]^c[14];
pb[2]=c[4]^c[5]^c[6]^c[11]^c[12]^c[13]^c[14];
pb[3]=c[8]^c[9]^c[10]^c[11]^c[12]^c[13]^c[14];
// assign p[0]=d[0];
//p{0}=d{0};
//p(0)=d(0);
// Determine S from pb and p
s[0] = c[0]^pb[0];
s[1] = c[1]^pb[1];
s[2] = c[3]^pb[2];
s[3] = c[7]^pb[3];
// Temporary store the values into a temp variable
inputs=c;
// Flip the decode bit with the detected error to correct it
/*
temp[0]=s[0]*1;
temp[1]=s[1]*2;
temp[2]=s[2]*4;
temp[3]=s[3]*8;
*/
temp=s[0]*1;
temp=temp+s[1]*2;
temp=temp+s[2]*4;
temp=temp+s[3]*8-1;
//temp=$bitstoreal(s);
//c[temp]=c[temp]^1; // Compiling error
//q[temp]=c[temp]^1; // I/P index != output index
inputs[temp]=c[temp]^1;
// Assign the decoded signal bits to syndrome bits...
q[0]=inputs[2];
q[1]=inputs[4];
q[2]=inputs[5];
q[3]=inputs[6];
q[4]=inputs[8];
q[5]=inputs[9];
q[6]=inputs[10];
q[7]=inputs[11];
q[8]=inputs[12];
q[9]=inputs[13];
q[10]=inputs[14];
end
endmodule
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/*
* Copyright (c) 2015 Steven Stallion
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
`timescale 1ns / 10ps
module addr_decode(input [3:0] addr,
output r, s, t, x, y, z);
assign x = !(addr <= 4'b0111); // X 0x0000 0x7FFF RAM
assign t = !(addr == 4'b1010); // T 0xA000 0xAFFF
assign s = !(addr == 4'b1011); // S 0xB000 0xBFFF
assign r = !(addr == 4'b1100); // R 0xC000 0xCFFF
assign z = !(addr == 4'b1101); // Z 0xD000 0xDFFF PIA
assign y = !(addr >= 4'b1110); // Y 0xE000 0xFFFF EEPROM
endmodule
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//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: raminfr.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:39:01 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:44:14 2011 tractp1
// UART in test bench to send/receive ASCII bytes with FPGA UART and
// command processing task in firmware
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5; int vis[N][N][N]; int l[N], r[N]; double get_frac(int x, int y) { return (1.0 * x) / (1.0 * y); } double dfs(vector<vector<vector<double>>> &dp, int b, int cur, int g, int e, int n) { if (cur == n) { if (g == 0) return (e > 1) ? 1.0 : 0.0; else if (g == 1) return (e > 0) ? 1.0 : 0.0; return 0.0; } if (vis[cur][g][e] == -1) { vis[cur][g][e] = 0; double p = 0; if (g == 0 && r[cur] > b) p += get_frac(r[cur] - max(b, l[cur] - 1), r[cur] - l[cur] + 1) * dfs(dp, b, cur + 1, g + 1, e, n); if (l[cur] <= b && r[cur] >= b) p += get_frac(1, r[cur] - l[cur] + 1) * dfs(dp, b, cur + 1, g, e + 1, n); if (l[cur] < b) p += get_frac(min(r[cur] + 1, b) - l[cur], r[cur] - l[cur] + 1) * dfs(dp, b, cur + 1, g, e, n); dp[cur][g][e] = p; } return dp[cur][g][e]; } double solve() { int n, mn = 1e4 + 5, mx = 0; double res = 0, sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; mn = min(mn, l[i]); mx = max(mx, r[i]); } for (int i = mn; i <= mx; i++) { memset(vis, -1, sizeof(vis)); vector<vector<vector<double>>> dp( n, vector<vector<double>>(n, vector<double>(n))); res += 1.0 * i * dfs(dp, i, 0, 0, 0, n); } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << fixed << setprecision(12); cout << solve() << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_TB_V
`define SKY130_FD_SC_LP__DFRTN_TB_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrtn.v"
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__dfrtn dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_TB_V
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#include <bits/stdc++.h> using namespace std; long long n, W, B, X, dp[1001][10001], c[1001], cum[1001], cost[1001]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n >> W >> B >> X; for (int i = 0; i < n; i++) { cin >> c[i]; if (i == 0) cum[i] = c[i]; else cum[i] = cum[i - 1] + c[i]; } for (int i = 0; i < n; i++) cin >> cost[i]; for (int i = 0; i < 1001; i++) for (int j = 0; j < 10001; j++) dp[i][j] = 10000000000; dp[0][0] = W; for (int i = 0; i <= c[0]; i++) { if (W >= i * cost[0]) dp[0][i] = W - i * cost[0]; } for (int i = 1; i < n; i++) { for (int j = 0; j <= cum[i]; j++) { for (int k = 0; k <= min((long long)j, c[i]); k++) { if (dp[i - 1][j - k] != 10000000000) { if (min(dp[i - 1][j - k] + X, W + (j - k) * B) - k * cost[i] >= 0) { dp[i][j] = max((dp[i][j] == 10000000000 ? 0 : dp[i][j]), min(dp[i - 1][j - k] + X, W + (j - k) * B) - k * cost[i]); } } } } } for (int i = cum[n - 1]; i >= 0; i--) { if (dp[n - 1][i] != 10000000000) return cout << i, 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; const int N2 = 2e6 + 5; long long cs[N2], csn[N2]; int main() { int n, x, y; scanf( %d%d%d , &n, &x, &y); int mx = 0; for (int i = 0, a; i < n; i++) { scanf( %d , &a); cs[a]++; mx = max(mx, a); } long long temp = 0; int am = 0; for (int i = 1; i < N2; i++) { if (cs[i]) am += cs[i]; cs[i] += cs[i - 1]; csn[i] = temp; temp += am; } int d = x / y; for (int i = d - 2; i <= d + 2; i++) { if (1LL * i * y < x) d = i; } long long ans = 1e18; for (int i = 2; i < N2; i++) { int h = min(d, i - 1), g = 0; long long s = 0; for (int j = i; j < N2; j += i) { g += cs[j] - cs[max(j - h - 1, 0)]; s += csn[j] - csn[max(j - h - 1, 0)] - cs[max(j - h - 1, 0)] * 1LL * (h + 1); } ans = min(ans, y * s + x * 1LL * (n - g)); } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d, e, f, g, h, i, j, k, l, n, v, t; cin >> n >> k; long long m[k]; for (i = 0; i < k; i++) cin >> m[i]; if (n % 2 == 0) { a = m[k - 1]; if (a & 1) cout << odd n ; else cout << even n ; } else { a = 0; for (i = 0; i < k; i++) { if (m[i] & 1) a++; } if (a & 1) cout << odd n ; else cout << even n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; long long tot = n * (n + 1) / 2, zr = n - m, gr = m + 1; long long k = zr / gr, ans = 0; if (zr % gr == 0) { ans = tot - (k * (k + 1) / 2) * gr; } else { ans = tot - (zr % gr) * ((k + 1) * (k + 2) / 2) - (gr - (zr % gr)) * (k * (k + 1) / 2); } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int MAX = 200005; long long modexp(long long x, long long n) { if (n == 0) return 1LL; if (n % 2 == 0) { long long y = modexp(x, n / 2) % mod; return (y * y) % mod; } return (x * modexp(x, n - 1) % mod) % mod; } long long powr(long long x, long long n) { long long ans = 1; for (int i = 1; i <= n; i++) ans = ans * x; return ans; } int main() { int n; scanf( %d , &n); int a[n]; int dp[n]; pair<int, int> aux[n]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); dp[i] = mod; aux[i] = make_pair(a[i], i); } sort(aux, aux + n); sort(a, a + n); dp[2] = a[2] - a[0]; dp[3] = a[3] - a[0]; dp[4] = a[4] - a[0]; int idx[n]; for (int i = 0; i < 5; i++) idx[i] = 0; for (int i = 5; i < n; i++) { vector<pair<int, int> > p; if (i - 2 >= 3) p.push_back(make_pair(dp[i - 3] + a[i] - a[i - 2], i - 2)); if (i - 3 >= 3) p.push_back(make_pair(dp[i - 4] + a[i] - a[i - 3], i - 3)); if (i - 4 >= 3) p.push_back(make_pair(dp[i - 5] + a[i] - a[i - 4], i - 4)); sort(p.begin(), p.end()); dp[i] = p[0].first; idx[i] = p[0].second; } int color[n]; int team = 0; for (int i = n - 1; i > 0; i--) { team++; int x = idx[i]; for (int j = x; j <= i; j++) { color[j] = team; } i = x; } printf( %d %d n , dp[n - 1], team); int ans[n]; for (int i = 0; i < n; i++) { ans[aux[i].second] = color[i]; } for (int i = 0; i < n; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod, n, m, a[200005], b[200005], kq, vt1, vt2, l, r, mid, mn[200005]; map<int, bool> mp; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; mod = 998244353; for (int i = 1; i <= n; ++i) { cin >> a[i]; mp[a[i]] = true; } for (int i = 1; i <= m; ++i) { cin >> b[i]; if (!mp[b[i]]) { cout << 0; return 0; } } for (int i = 1; i <= n; ++i) { if (a[i] < b[1]) { cout << 0; return 0; } if (a[i] == b[m]) vt1 = i; } for (int i = n; i > vt1; --i) if (a[i] < b[m]) { cout << 0; return 0; } mn[n] = a[n]; for (int i = n - 1; i > 0; --i) mn[i] = min(a[i], mn[i + 1]); kq = 1; for (int i = 1; i < m; ++i) { l = 1; r = n - 1; while (l <= r) { mid = (l + r) / 2; if (mn[mid + 1] >= b[i + 1]) { vt1 = mid; r = mid - 1; } else l = mid + 1; } l = 1; r = n - 1; while (l <= r) { mid = (l + r) / 2; if (mn[mid + 1] > b[i + 1]) r = mid - 1; else { vt2 = mid; l = mid + 1; } } kq = kq * max(0LL, vt2 - vt1 + 1) % mod; ; } cout << kq; return 0; }
|
#include <bits/stdc++.h> long long i, j, r, c, fre[1000], ans; char na, name1[1000][1000]; using namespace std; int main() { scanf( %lld %lld %c , &r, &c, &na); for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { scanf( %c , &name1[i][j]); } } for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { if (name1[i][j] == na) { if (i - 1 >= 0) { fre[(int)name1[i - 1][j]]++; } if (i + 1 < r) { fre[(int)name1[i + 1][j]]++; } if (j + 1 < c) { fre[(int)name1[i][j + 1]]++; } if (j - 1 >= 0) { fre[(int)name1[i][j - 1]]++; } } } } for (i = 65; i <= 90; i++) { if (fre[i] > 0) { ans++; } } if (fre[(int)na] > 0) { ans--; } printf( %lld n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7002 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w8,
w9,
w144,
w1167,
w4668,
w3501,
w7002;
assign w1 = i_data0;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w1167 = w1023 + w144;
assign w144 = w9 << 4;
assign w3501 = w4668 - w1167;
assign w4668 = w1167 << 2;
assign w7002 = w3501 << 1;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign o_data0 = w7002;
//multiplier_block area estimate = 6795.83517920735;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int getFldsFromLine(char *line, std::vector<char *> &res, const char *sep = t n v f r ); int main(int argc, char **argv) { FILE *infile = stdin; char *line; line = (char *)calloc(5000000, sizeof(char)); if (line == NULL) { fprintf(stderr, Couldn t allocate space for %s nBye! n , line ); exit(-1); }; std::vector<char *> flds; int numFlds, numCases, caseNum = 0; fgets(line, 5000000, infile); numFlds = getFldsFromLine(line, flds); numCases = atoi(flds[0]); bool isGood = false; for (caseNum = 1; caseNum <= numCases; ++caseNum) { fgets(line, 5000000, infile); numFlds = getFldsFromLine(line, flds); int num1 = atoi(flds[1]), num2 = atoi(flds[2]); if ((num1 >= 2400) && (num2 > num1)) isGood = true; } if (isGood) printf( YES n ); else printf( NO n ); return (0); } int getFldsFromLine(char *line, std::vector<char *> &res, const char *sep) { res.clear(); char *tok = strtok(line, sep); while (tok) { res.push_back(tok); tok = strtok(0, sep); } return res.size(); }
|
#include <bits/stdc++.h> using namespace std; long long arr[200005], sh[200005], sp[200005]; int main() { long long i, j, k, n, m, p, q, t, cnt = 0, mn; scanf( %lld , &n); scanf( %lld , &k); for (i = 0; i < n; i++) { scanf( %lld , &arr[i]); ; } sort(arr, arr + n); for (i = 0; i < n; i++) { cnt = 0; while (1) { sh[arr[i]]++; if (sh[arr[i]] <= k) sp[arr[i]] += cnt; if (!arr[i]) break; arr[i] /= 2; cnt++; } } mn = sp[0]; for (i = 0; i <= 200005; i++) { if (sh[i] >= k && sp[i] < mn) mn = sp[i]; } cout << mn << endl; return 0; }
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module SyncReset0 (
IN_RST,
OUT_RST
);
input IN_RST ;
output OUT_RST ;
assign OUT_RST = IN_RST ;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not FALSE");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = (test_expr == 1'b1);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
wire fire_cover = 1'b0;
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 15326 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w511,
w8176,
w8175,
w7663,
w15326;
assign w1 = i_data0;
assign w15326 = w7663 << 1;
assign w511 = w512 - w1;
assign w512 = w1 << 9;
assign w7663 = w8175 - w512;
assign w8175 = w8176 - w1;
assign w8176 = w511 << 4;
assign o_data0 = w15326;
//multiplier_block area estimate = 5006.23186995147;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int l, r; cin >> l >> r; for (int i = l; i < r + 1; i++) { vector<int> cnts(10); int x = i; while (x > 0) { cnts[x % 10]++; x /= 10; } bool good = true; for (int j = 0; j < 10; j++) { if (cnts[j] > 1) { good = false; } } if (good) { cout << i << endl; return 0; } } cout << -1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e6 + 200, RANGE = 1e6 + 20; const long long INF = 0x3f3f3f3f3f3f3f3f; int n, m, p; long long pre_min[MAX_N], nodes[MAX_N << 2], tag[MAX_N << 2]; pair<int, int> ai[MAX_N], bi[MAX_N]; struct tup { int x, y, z; bool operator<(const tup &rhs) const { return x < rhs.x || (x == rhs.x && y < rhs.y); } } tups[MAX_N]; void pushdown(int p) { if (tag[p] != 0) { tag[(p << 1)] += tag[p], tag[((p << 1) | 1)] += tag[p]; nodes[(p << 1)] += tag[p], nodes[((p << 1) | 1)] += tag[p]; tag[p] = 0; } } void pushup(int p) { nodes[p] = max(nodes[(p << 1)], nodes[((p << 1) | 1)]); } void update(int ql, int qr, int l, int r, int p, long long val) { if (ql <= l && r <= qr) return (void)(nodes[p] += val, tag[p] += val); pushdown(p); if (ql <= ((l + r) >> 1)) update(ql, qr, l, ((l + r) >> 1), (p << 1), val); if (((l + r) >> 1) < qr) update(ql, qr, ((l + r) >> 1) + 1, r, ((p << 1) | 1), val); pushup(p); } int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; i++) scanf( %d%d , &ai[i].first, &ai[i].second); for (int i = 1; i <= m; i++) scanf( %d%d , &bi[i].first, &bi[i].second); for (int i = 1; i <= p; i++) scanf( %d%d%d , &tups[i].x, &tups[i].y, &tups[i].z), tups[i].y++, tups[i].x++; sort(ai + 1, ai + 1 + n), sort(bi + 1, bi + 1 + m), sort(tups + 1, tups + 1 + p); pre_min[m + 1] = INF; for (int i = m; i >= 1; i--) pre_min[i] = min(pre_min[i + 1], 1LL * bi[i].second); int last_pos = 1; for (int i = 1; i <= m; i++) update(last_pos, bi[i].first, 1, RANGE, 1, -pre_min[i]), last_pos = bi[i].first + 1; update(last_pos, RANGE, 1, RANGE, 1, -INF); long long ans = -INF; for (int i = 1, ptr = 1; i <= n; i++) { int pos = ai[i].first, cost = ai[i].second; while (ptr <= p && tups[ptr].x <= pos) update(tups[ptr].y, RANGE, 1, RANGE, 1, tups[ptr].z), ptr++; ans = max(ans, nodes[1] - cost); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int n; long long x, m, ans; long long f() { long long a, b, q; q = (x - 1) % 4; a = q == 0 ? x - 1 : q == 1 ? 1 : q == 2 ? x : 0; q = (x + m - 1) % 4; b = q == 0 ? x + m - 1 : q == 1 ? 1 : q == 2 ? x + m : 0; return a ^ b; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %lld %lld , &x, &m); ans ^= f(); } if (ans) puts( tolik ); else puts( bolik ); return 0; }
|
module check (input unsigned [103:0] a, c);
wire [103:0] int_AB;
assign int_AB = ~a;
always @(a, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A);
parameter S = 2000;
int unsigned i;
initial begin
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a;
wire unsigned [103:0] r;
stimulus stim (.A(a));
not104 duv (.a_i(a), .c_o(r) );
check check (.a(a), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Andrew Bardsley.
// bug1071
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];
reg [3:0] array_3 [3:1];
reg [3:0] elem;
reg array_1_ne_array_2;
reg array_1_eq_array_2;
reg array_1_ne_array_3;
reg array_1_eq_array_3;
initial begin
array_1[0] = 4'b1000;
array_1[1] = 4'b1000;
array_1[2] = 4'b1000;
array_2[0] = 4'b1000;
array_2[1] = 4'b1000;
array_2[2] = 4'b1000;
array_3[1] = 4'b1000;
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
//Not legal: array_rxor = ^ array_1;
//Not legal: array_rxnor = ^~ array_1;
//Not legal: array_ror = | array_1;
//Not legal: array_rand = & array_1;
`ifdef TEST_VERBOSE
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
`endif
if (array_1_ne_array_2 !== 0) $stop;
if (array_1_eq_array_2 !== 1) $stop;
if (array_1_ne_array_3 !== 1) $stop;
if (array_1_eq_array_3 !== 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_SYMBOL_V
`define SKY130_FD_SC_HD__O32A_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int i, j, k, l, x, y, z, m, n, a, b, ans, p, q, r; int numbers[800000]; int gcd(int x, int y) { if (y == 0) return x; else return gcd(y, x % y); } int main() { scanf( %d %d %d , &a, &b, &n); ans = gcd(a, b); m = sqrt(ans); for (i = 1, k = 0; i <= m; i++) { if (ans % i == 0) { p = ans / i; numbers[k] = p; k++; numbers[k] = i; k++; } } sort(numbers, numbers + k); p = 0; q = 0; for (i = 1; i <= n; i++) { scanf( %d %d , &x, &y); if (x > ans) { printf( -1 n ); continue; } p = lower_bound(numbers, numbers + k, (x)) - numbers; q = lower_bound(numbers, numbers + k, (y)) - numbers; r = 0; for (j = q + 1; j >= p - 1; j--) { if (numbers[j] >= x && numbers[j] <= y) { printf( %d n , numbers[j]); r = 1; break; } } if (!r) printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; long long sum = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } if (sum % 2 != 0) { sum++; } long long sum1 = 0; for (int i = 0; i < n; i++) { sum1 += arr[i]; if (sum1 >= (sum / 2)) { cout << i + 1 << endl; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, i; cin >> n >> m; i = n / 2 + (n & 1); i = (m >= i) ? 0 : n - 2 * m; cout << i << ; if (!m) { cout << n; return 0; } for (i = 1; ((i * (i - 1)) / 2) < m; i++) ; cout << n - i; return 0; }
|
/*******************************************************************************
* Module: simul_axi_master_wdata
* Date:2014-03-24
* Author: Andrey Filippov
* Description: Simulation model for AXI write data channel
*
* Copyright (c) 2014 Elphel, Inc..
* simul_axi_master_wdata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_master_wdata.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_master_wdata#(
parameter integer ID_WIDTH=12,
parameter integer DATA_WIDTH=32,
parameter integer WSTB_WIDTH= 4,
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
parameter DATA_DELAY = 3.5,
parameter VALID_DELAY = 4.0
)(
input clk,
input reset,
input [ID_WIDTH-1:0] wid_in,
input [DATA_WIDTH-1:0] wdata_in,
input [WSTB_WIDTH-1:0] wstrb_in,
input wlast_in,
output [ID_WIDTH-1:0] wid,
output [DATA_WIDTH-1:0] wdata,
output [WSTB_WIDTH-1:0] wstrb,
output wlast,
output wvalid,
input wready,
input set_cmd, // latch all other input data at posedge of clock
output ready // command/data FIFO can accept command
);
wire [ID_WIDTH-1:0] wid_out;
wire [DATA_WIDTH-1:0] wdata_out;
wire [WSTB_WIDTH-1:0] wstrb_out;
wire wlast_out;
wire wvalid_out;
assign #(DATA_DELAY) wid= wid_out;
assign #(DATA_DELAY) wdata= wdata_out;
assign #(DATA_DELAY) wstrb= wstrb_out;
assign #(DATA_DELAY) wlast= wlast_out;
assign #(VALID_DELAY) wvalid= wvalid_out;
simul_axi_fifo
#(
.WIDTH(ID_WIDTH+DATA_WIDTH+WSTB_WIDTH+1), // total number of output bits
.LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(DEPTH) // maximal number of commands in FIFO
) simul_axi_fifo_i (
.clk(clk), // input clk,
.reset(reset), // input reset,
.data_in({wid_in, wdata_in, wstrb_in, wlast_in}), // input [WIDTH-1:0] data_in,
.load(set_cmd), // input load,
.input_ready(ready), // output input_ready,
.data_out({wid_out, wdata_out, wstrb_out, wlast_out}), // output [WIDTH-1:0] data_out,
.valid(wvalid_out), // output valid,
.ready(wready)); // input ready);
endmodule
|
#include <bits/stdc++.h> using ll = long long int; using namespace std; int main() { int n; cin >> n; string s; cin >> s; int cnt = 0; int negative = -1; int ans = 0; for (int i = 0; i < n; ++i) { if (s[i] == ) ) --cnt; else if (s[i] == ( ) ++cnt; if (cnt < 0 && negative == -1) negative = i; if (cnt == 0 && negative != -1) { ans += i - negative + 1; negative = -1; } } if (cnt != 0) { cout << -1 << endl; } else { cout << ans << endl; } }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Synthesized Netlist Wrapper
// This file is provided to wrap around the synthesized netlist (if appropriate)
// Interfaces:
// CLK.ACLK
// AXI4 Interconnect Clock Input
// RST.ARESETN
// AXI4 Interconnect Reset Input
// AXI_SLAVE_S_AXI
// AXI_SLAVE
// AXILite_SLAVE_S_AXI
// AXILite_SLAVE
// BRAM_PORTA
// BRAM_PORTA
// BRAM_PORTB
// BRAM_PORTB
module ram_16x1k_sp (
clka,
ena,
wea,
addra,
dina,
douta
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100008; int a[N]; int b[N]; int main() { int n = 0; int x = 0; scanf( %d %d , &n, &x); for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } for (int i = 1; i <= n; ++i) { scanf( %d , b + i); } sort(a + 1, a + n + 1); sort(b + 1, b + n + 1); int cnt = 0; int j = 1; for (int i = n; i > 0; --i) { while (j <= n && a[j] + b[i] < x) ++j; if (j <= n) ++cnt; else break; ++j; } printf( %d %d n , 1, cnt); return 0; }
|
// Library - static, Cell - th54w22, View - schematic
// LAST TIME SAVED: May 23 18:03:43 2014
// NETLIST TIME: May 23 18:07:14 2014
`timescale 1ns / 1ns
module th54w22 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th54w22";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N14 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net017), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net037), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net017), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net017), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net037), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(net017), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(net036), .d(net32));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net036), .d(net32));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net34));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(a), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
#include <bits/stdc++.h> using namespace std; void mul(unsigned long long int F[2][2], unsigned long long int M[2][2]) { unsigned long long int x = F[0][0] * M[0][0] % 1000000007 + F[0][1] * M[1][0] % 1000000007; unsigned long long int y = F[0][0] * M[0][1] % 1000000007 + F[0][1] * M[1][1] % 1000000007; unsigned long long int z = F[1][0] * M[0][0] % 1000000007 + F[1][1] * M[1][0] % 1000000007; unsigned long long int o = F[1][0] * M[0][1] % 1000000007 + F[1][1] * M[1][1] % 1000000007; F[0][0] = x % 1000000007; F[0][1] = y % 1000000007; F[1][0] = z % 1000000007; F[1][1] = o % 1000000007; } void power(unsigned long long int F[2][2], unsigned long long int n) { if (n == 0 || n == 1) return; unsigned long long int N[2][2] = {{3, 1}, {1, 3}}; power(F, n / 2); mul(F, F); if (n % 2 != 0) mul(F, N); } int main() { unsigned long long int n, F[2][2] = {{3, 1}, {1, 3}}; cin >> n; if (n == 0) cout << 1 << endl; else { power(F, n); cout << F[0][0] % 1000000007 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 6; vector<pair<int, int> > G[maxn]; int out, m, d[maxn], ans[maxn][3], leaf[maxn][2]; void add_m(int u, int v, int d) { ans[++m][0] = u, ans[m][1] = v, ans[m][2] = d; } void add_link(int u, int l, int d) { if (u == out) { add_m(u, l, d); return; } int a = l, b = leaf[u][0] == l ? leaf[u][1] : leaf[u][0], c = out; add_m(a, c, d / 2), add_m(a, b, d / 2), add_m(b, c, -d / 2); } void dfs(int u, int f, int l) { if (G[u].size() == 1 && f) { leaf[u][0] = u; return; } for (int i = 0; i < G[u].size(); ++i) { int v = G[u][i].first; if (v != f) { dfs(v, u, l); if (leaf[u][0]) leaf[u][1] = leaf[v][0]; else leaf[u][0] = leaf[v][0]; } } for (int i = 0; i < G[u].size(); ++i) { int v = G[u][i].first; if (v != f) { int d = G[u][i].second; if (G[v].size() == 1) add_link(u, v, G[u][i].second); else { add_link(u, leaf[v][0], G[u][i].second); add_link(v, leaf[v][0], -G[u][i].second); } } } } int main() { int n; cin >> n; for (int i = 1; i < n; ++i) { int u, v, c; cin >> u >> v >> c; G[u].push_back(make_pair(v, c)); G[v].push_back(make_pair(u, c)); ++d[u], ++d[v]; } for (int i = 1; i <= n; ++i) if (d[i] == 2) { cout << NO << endl; return 0; } for (int i = 1; i <= n; ++i) if (G[i].size() == 1) { out = i, dfs(i, 0, i); break; } cout << YES << endl; cout << m << endl; for (int i = 1; i <= m; ++i) cout << ans[i][0] << << ans[i][1] << << ans[i][2] << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long p, d; while (scanf( %I64d%I64d , &p, &d) != EOF) { long long ans = ++p; for (long long i = 10;; i *= 10) { if (p % i > d) break; ans = p - p % i; } printf( %I64d n , ans - 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[10010], leftx[10010], rightx[10010], l[5010], r[5010]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, x; cin >> n >> x; vector<int> ry; for (int i = 0; i < n; i++) { int a, b; cin >> a >> b; l[i] = a; r[i] = b; ry.push_back(a); ry.push_back(b); } ry.push_back(x); sort(ry.begin(), ry.end()); set<int> rt; for (auto val : ry) { rt.insert(val); } ry.clear(); for (auto val : rt) { ry.push_back(val); } int ind = -1; for (int i = 0; i < ry.size(); i++) { if (ry[i] == x) ind = i; } for (int i = 0; i < ry.size(); i++) dp[i] = 1e18; for (int i = 0; i < ry.size(); i++) { if (ry[i] == x) dp[i] = 0; } for (int i = 0; i <= n; i++) { if (i) { for (int j = 0; j < ry.size(); j++) { long long val = 0; if (ry[j] < l[i - 1] || ry[j] > r[i - 1]) val = min(abs(l[i - 1] - ry[j]), abs(r[i - 1] - ry[j])); dp[j] = min(leftx[j] + ry[j] + val, rightx[j] - ry[j] + val); } } leftx[0] = dp[0] - ry[0]; for (int j = 1; j < ry.size(); j++) leftx[j] = min(leftx[j - 1], dp[j] - ry[j]); rightx[ry.size() - 1] = dp[ry.size() - 1] + ry[ry.size() - 1]; for (int j = (int)ry.size() - 2; j >= 0; j--) rightx[j] = min(rightx[j + 1], dp[j] + ry[j]); } long long mini = 1e18; for (int j = 0; j < ry.size(); j++) mini = min(mini, dp[j]); cout << mini << n ; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compount ifdef test with 2 defines
//
`define DOUBLE
`define NOCODE
module ifdef2;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 0;
#20;
end
`endif // NOCODE
`endif // DOUBLE
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
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