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#include <bits/stdc++.h> using namespace std; char arr[300]; int main() { ios::sync_with_stdio(false); string s, t; cin >> s >> t; int n = s.size(); memset(arr, A , sizeof(arr)); if (n != t.size()) { cout << -1; return 0; } for (int i = 0; i < n; i++) { if (arr[t[i]] != A ) { if (arr[t[i]] != s[i]) { cout << -1; return 0; } continue; } if (arr[s[i]] == A ) { arr[s[i]] = t[i]; arr[t[i]] = s[i]; } if (arr[s[i]] != t[i]) { cout << -1; return 0; } } vector<pair<char, char> > v; for (int i = 0; i < 300; i++) { if (arr[i] != A ) { if (i == arr[i]) continue; v.push_back(make_pair((char)i, arr[i])); arr[arr[i]] = A ; arr[i] = A ; } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << endl; return 0; }
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/* Title: eight_bit_counter.v
* Author: Sergiy Kolodyazhnyy <>
* Date: May 2nd, 2017
* Purpose: Behavioral module for simple 8-bit binary counter
* Developed on: Ubuntu 16.04 LTS , Quartus Prime Lite 16.1
* Tested on: DE1-SoC , Cyclone V , 5CSEMA5F31
*/
module eight_bit_counter(count_out,enable,clock,clear);
input enable,clock,clear;
output [7:0] count_out;
wire [6:0] temp;
// Use counter_clock for RTL simulation, clk_1hz for hardware test
wire counter_clock;
//assign counter_clock = clock;
frequency_divider clk_1hz(counter_clock,clock);
// module t_ff(q_out,t_in,clock,clear);
t_ff tff0(count_out[0],enable,counter_clock,clear);
assign temp[0] = count_out[0] & enable;
t_ff tff1(count_out[1],temp[0],counter_clock,clear);
assign temp[1] = temp[0] & count_out[1];
t_ff tff2(count_out[2],temp[1],counter_clock,clear);
assign temp[2] = temp[1] & count_out[2];
t_ff tff3(count_out[3],temp[2],counter_clock,clear);
assign temp[3] = temp[2] & count_out[3];
t_ff tff4(count_out[4],temp[3],counter_clock,clear);
assign temp[4] = temp[3] & count_out[4];
t_ff tff5(count_out[5],temp[4],counter_clock,clear);
assign temp[5] = temp[4] & count_out[5];
t_ff tff6(count_out[6],temp[5],counter_clock,clear);
assign temp[6] = temp[5] & count_out[6];
t_ff tff7(count_out[7],temp[6],counter_clock,clear);
endmodule
module frequency_divider(clock_out,clock_in);
input clock_in;
output reg clock_out;
/*
* Frequency divider should be 1 cycle per second,
* which means it toggles twice in 1 second.
* 50000000 cycles is 1 second, and half of that is
* 25000000. To represent that we need
* log_2 (25000000) = 24.57 or 25 bit wide vector
*/
reg [24:0] counter;
initial
begin
counter = 0;
clock_out = 0;
end
always @(posedge clock_in)
begin
if(counter == 0)
begin
counter <= 24999999;
clock_out <= ~clock_out;
end
else
counter <= counter - 1;
end
endmodule
/* T Flip Flop, uses characteristic equation and
* behavioral modeling
*/
module t_ff(q_out,t_in,clock,clear);
input t_in,clock,clear;
output reg q_out;
always @(posedge clock or negedge clear)
begin
if(~clear)
q_out <= 1'b0;
else
//if(t_in)
q_out <= t_in ^ q_out;
end
endmodule
module stimulus_counter;
reg clear, enable, clock;
wire [7:0] count_out;
// Instantiate the eight-bit synchronous counter
// module eight_bit_counter(count_out,enable,clock,clear);
eight_bit_counter s1(count_out,enable,clock,clear);
initial
begin
$monitor("At time",$time," clear = %b, enable = %b, and count = %h\n",clear,enable,count_out);
#2700 $finish;
end
// Initialize the inputs clear and enable
initial
begin
clear = 0;
enable = 0;
#10 clear = 1;
#20 enable = 1;
#2600 clear = 0;
end
// We'll make a counter that counts from 00000000 to 11111111.
// In order to do that, we'll need a clock.
initial
clock = 1'b0;
always
#5 clock = ~clock; // Toggle clock every 5 time units.
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[200005]; int main() { memset(x, 0, sizeof(x)); int n = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &x[i]); } sort(x, x + n); double eps = 1e-10, l = 0.0, r = (double)(x[n - 1] - x[0]) / 6.0; int p1 = 0, p2 = 0; while (r - l > eps) { double mid = l + (r - l) / 2.0; p1 = upper_bound(x, x + n, x[0] + 2 * mid) - x; if (p1 == n) { r = mid; continue; } p2 = upper_bound(x, x + n, x[p1] + 2 * mid) - x; if (p2 == n || (double)(x[n - 1] - x[p2]) <= 2 * mid - eps) { r = mid; } else { l = mid; } } double tmp = x[0] + 2 * l; int idx = lower_bound(x, x + n, (int)(tmp - 1)) - x; for (; idx < n; ++idx) { if (x[idx] > x[0] + (int)(2 * l + 0.1)) { break; } } printf( %.6lf n , l); printf( %.6lf %.6lf %.6lf , (double)x[0] + l, (double)x[idx] + l, (double)x[n - 1] - l); return 0; }
|
#include <bits/stdc++.h> using namespace std; string b[51]; bool check(pair<int, int> f, pair<int, int> s) { bool r1 = true, r2 = true, c1 = true, c2 = true; for (int i = f.first; i <= s.first; i++) { if (b[i][f.second] == W ) c1 = false; if (b[i][s.second] == W ) c2 = false; } for (int i = s.first; i <= f.first; i++) { if (b[i][f.second] == W ) c1 = false; if (b[i][s.second] == W ) c2 = false; } for (int i = f.second; i <= s.second; i++) { if (b[f.first][i] == W ) r1 = false; if (b[s.first][i] == W ) r2 = false; } for (int i = s.second; i <= f.second; i++) { if (b[f.first][i] == W ) r1 = false; if (b[s.first][i] == W ) r2 = false; } return (c1 && r2) || (c2 && r1); } vector<pair<int, int> > v; int main() { int r, c; cin.tie(0); cin >> r >> c; for (int i = 0; i < r; i++) { cin >> b[i]; for (int j = 0; j < c; j++) if (b[i][j] == B ) v.push_back({i, j}); } int sz = v.size(); for (int i = 0; i < sz; i++) for (int j = i + 1; j < sz; j++) { if (!check(v[i], v[j])) { cout << NO ; return 0; }; } cout << YES ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct Node { int ancestor; vector<int> children; }; class TarjanOLCA { enum Color { WHITE = 0, BLACK = 1, }; public: TarjanOLCA(const vector<Node>& tree, int root, const vector<pair<int, int> >& query) : m_tree(tree), m_root(root), m_size(tree.size()), m_rank(m_size, -1), m_parent(m_size, -1), m_color(m_size, WHITE) { for (vector<pair<int, int> >::const_iterator it = query.begin(); it != query.end(); ++it) { int u = it->first; int v = it->second; if (m_query.count(u) == 0) { m_query[u] = set<int>(); } if (m_query.count(v) == 0) { m_query[v] = set<int>(); } m_query[u].insert(v); m_query[v].insert(u); } solve(); } const map<pair<int, int>, int> getLCA() const { return m_lca; } private: vector<Node> m_tree; int m_root; map<int, set<int> > m_query; map<pair<int, int>, int> m_lca; const int m_size; vector<int> m_rank; vector<int> m_parent; vector<Color> m_color; void makeSet(int k) { assert(0 <= k && k < m_size); m_color[k] = WHITE; m_parent[k] = k; m_rank[k] = 0; } int find(int k) { if (m_parent[k] != k) { m_parent[k] = find(m_parent[k]); } return m_parent[k]; } void link(int u, int v) { if (m_rank[u] > m_rank[v]) { m_parent[v] = u; } else { m_parent[u] = v; if (m_rank[u] == m_rank[v]) { m_rank[v]++; } } } void join(int u, int v) { link(find(u), find(v)); } void lca(int u) { makeSet(u); m_tree[u].ancestor = u; for (int i = 0; i < (int)m_tree[u].children.size(); i++) { int v = m_tree[u].children[i]; lca(v); join(u, v); m_tree[find(u)].ancestor = u; } m_color[u] = BLACK; if (m_query.count(u) > 0) { for (set<int>::const_iterator it = m_query[u].begin(); it != m_query[u].end(); ++it) { int v = *it; if (m_color[v] == BLACK) { m_lca[make_pair(v, u)] = m_lca[make_pair(u, v)] = m_tree[find(v)].ancestor; } } } } void solve() { lca(m_root); } }; struct Fence { int r; int x; int y; Fence(int r_, int x_, int y_) : r(r_), x(x_), y(y_) {} bool operator<(const Fence& other) const { if (r < other.r) return true; else if (r > other.r) return false; else if (x < other.x) return true; else if (x > other.x) return false; else return y < other.y; } }; struct CP { int x; int y; CP(int x_, int y_) : x(x_), y(y_) {} }; class Solution { public: Solution() { int n, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { int kx, ky; cin >> kx >> ky; cp.push_back(CP(kx, ky)); } for (int i = 0; i < m; i++) { int r, cx, cy; cin >> r >> cx >> cy; fence.push_back(Fence(r, cx, cy)); } sort(fence.begin(), fence.end()); for (int i = 0; i < k; i++) { int a, b; cin >> a >> b; query.push_back(make_pair(a - 1, b - 1)); } makeTree(); height.resize(m + 1); buildHeight(m, 0); cpPos.resize(n); buildCpPos(); transformQuery(); processQuery(); } private: int m; vector<CP> cp; vector<Fence> fence; vector<Node> tree; vector<pair<int, int> > query; vector<int> height; vector<int> cpPos; bool pointInside(int i, int j) const { int64_t xi = cp[i].x; int64_t yi = cp[i].y; int64_t xj = fence[j].x; int64_t yj = fence[j].y; int64_t rj = fence[j].r; return rj * rj > (xi - xj) * (xi - xj) + (yi - yj) * (yi - yj); } bool fenceInside(int i, int j) const { int64_t xi = fence[i].x; int64_t yi = fence[i].y; int64_t ri = fence[i].r; int64_t xj = fence[j].x; int64_t yj = fence[j].y; int64_t rj = fence[j].r; return (rj - ri) * (rj - ri) > (xi - xj) * (xi - xj) + (yi - yj) * (yi - yj); } void makeTree() { tree.resize(m + 1); for (int i = 0; i <= m; i++) { tree[i].ancestor = i; } for (int i = 0; i < m - 1; i++) { for (int j = i + 1; j < m; j++) { if (fenceInside(i, j)) { tree[i].ancestor = j; tree[j].children.push_back(i); break; } } } for (int i = 0; i < m; i++) { if (tree[i].ancestor == i) { tree[i].ancestor = m; tree[m].children.push_back(i); } } } void buildHeight(int u, int h) { height[u] = h; for (int i = 0; i < (int)tree[u].children.size(); i++) { int v = tree[u].children[i]; buildHeight(v, h + 1); } } void buildCpPos() { for (int i = 0; i < (int)cp.size(); i++) { int j = 0; for (; j < m; j++) { if (pointInside(i, j)) { break; } } cpPos[i] = j; } } void transformQuery() { for (int i = 0; i < (int)query.size(); i++) { int a = query[i].first; int b = query[i].second; int u = cpPos[a]; int v = cpPos[b]; query[i] = make_pair(u, v); } } void processQuery() { TarjanOLCA olca(tree, m, query); map<pair<int, int>, int> result = olca.getLCA(); for (int i = 0; i < (int)query.size(); i++) { int u = query[i].first; int v = query[i].second; assert(result.count(make_pair(u, v)) > 0); int w = result[make_pair(u, v)]; cout << height[u] + height[v] - 2 * height[w] << endl; } } }; int main() { Solution s; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top RAT_slice_17_13_0 -prefix
// RAT_slice_17_13_0_ RAT_slice_17_13_0_sim_netlist.v
// Design : RAT_slice_17_13_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_slice_17_13_0,xlslice,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlslice,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_slice_17_13_0
(Din,
Dout);
input [17:0]Din;
output [1:0]Dout;
wire [17:0]Din;
assign Dout[1:0] = Din[1:0];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long C = 1000000007; long long pow1(long long x, long long y, long long z) { if (y == 0) { return 1; } if (y % 2 == 0) { return pow1(x * x % z, y / 2, z); } return pow1(x, y - 1, z) * x % z; } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long n, k, t = 0, r = 0; cin >> n >> k; for (long long q = 0; q < n; q++) { long long w; cin >> w; if (w == 50) { t++; } else { r++; } } long long c[51][51]; for (long long q = 0; q <= 50; q++) { c[0][q] = 1; for (long long q1 = 1; q1 <= q; q1++) { c[q1][q] = c[q1 - 1][q] * (q - q1 + 1) % C * pow1(q1, C - 2, C) % C; } } long long d[5 * n + 2][t + 1][r + 1]; for (long long q = 0; q < 5 * n + 2; q++) { for (long long q1 = 0; q1 <= t; q1++) { fill(d[q][q1], d[q][q1] + r + 1, 0); } } d[0][0][0] = 1; bool flag = true; for (long long q = 0; q <= 5 * n; q++) { if (q % 2 == 1) { for (long long q1 = 0; q1 <= t; q1++) { for (long long q2 = 0; q2 <= r; q2++) { d[q][q1][q2] %= C; for (long long q3 = 0; q3 <= q1; q3++) { for (long long q4 = 0; q4 <= q2; q4++) { if ((q1 - q3) * 50 + (q2 - q4) * 100 <= k && q1 - q3 + q2 - q4) { d[q + 1][q3][q4] += d[q][q1][q2] * c[q1 - q3][q1] % C * c[q2 - q4][q2] % C; } } } } } } else { for (long long q1 = 0; q1 <= t; q1++) { for (long long q2 = 0; q2 <= r; q2++) { d[q][q1][q2] %= C; for (long long q3 = q1; q3 <= t; q3++) { for (long long q4 = q2; q4 <= r; q4++) { if ((q3 - q1) * 50 + (q4 - q2) * 100 <= k && q3 - q1 + q4 - q2) { d[q + 1][q3][q4] += d[q][q1][q2] * c[q3 - q1][t - q1] % C * c[q4 - q2][r - q2] % C; } } } } } } if (d[q][t][r] > 0) { cout << q << n << d[q][t][r] << n ; flag = false; break; } } if (flag) { cout << -1 << n << 0 << n ; } return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read and write data to the 16x2 Character LCD on the DE2 *
* Board. *
* *
******************************************************************************/
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for minimum wait between consecutive communications
// if using a 50MHz Clk
parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns
parameter IC = 7; // Number of bits for idle counter
parameter IDLE_COUNTER_INCREMENT = 7'h01;
parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns
parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns
parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns
parameter SC = 4; // Number of bits for states counter
parameter COUNTER_INCREMENT = 4'h1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input rs;
input rw;
input enable;
input display_on;
input back_light_on;
// Bidirectionals
inout [ 7: 0] LCD_DATA;
// Outputs
output reg LCD_ON;
output reg LCD_BLON;
output reg LCD_EN;
output reg LCD_RS;
output reg LCD_RW;
output reg [ 7: 0] data_out; // Stores data read from the LCD
output reg transfer_complete; // Indicates the end of the transfer
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter LCD_STATE_4_IDLE = 3'h4,
LCD_STATE_0_OPERATION = 3'h0,
LCD_STATE_1_ENABLE = 3'h1,
LCD_STATE_2_HOLD = 3'h2,
LCD_STATE_3_END = 3'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [ 7: 0] data_to_lcd;
reg [IC: 1] idle_counter;
reg [SC: 1] state_0_counter;
reg [SC: 1] state_1_counter;
reg [SC: 1] state_2_counter;
// State Machine Registers
reg [ 2: 0] ns_lcd;
reg [ 2: 0] s_lcd;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd <= LCD_STATE_4_IDLE;
else
s_lcd <= ns_lcd;
end
always @(*)
begin
ns_lcd = LCD_STATE_4_IDLE;
case (s_lcd)
LCD_STATE_4_IDLE:
begin
if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable)
ns_lcd = LCD_STATE_0_OPERATION;
else
ns_lcd = LCD_STATE_4_IDLE;
end
LCD_STATE_0_OPERATION:
begin
if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE)
ns_lcd = LCD_STATE_1_ENABLE;
else
ns_lcd = LCD_STATE_0_OPERATION;
end
LCD_STATE_1_ENABLE:
begin
if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE)
ns_lcd = LCD_STATE_2_HOLD;
else
ns_lcd = LCD_STATE_1_ENABLE;
end
LCD_STATE_2_HOLD:
begin
if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE)
ns_lcd = LCD_STATE_3_END;
else
ns_lcd = LCD_STATE_2_HOLD;
end
LCD_STATE_3_END:
begin
if (enable == 1'b0)
ns_lcd = LCD_STATE_4_IDLE;
else
ns_lcd = LCD_STATE_3_END;
end
default:
begin
ns_lcd = LCD_STATE_4_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
LCD_ON <= 1'b0;
LCD_BLON <= 1'b0;
end
else
begin
LCD_ON <= display_on;
LCD_BLON <= back_light_on;
end
end
always @(posedge clk)
begin
if (reset)
begin
LCD_EN <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
data_out <= 8'h00;
transfer_complete <= 1'b0;
end
else
begin
if (s_lcd == LCD_STATE_1_ENABLE)
LCD_EN <= 1'b1;
else
LCD_EN <= 1'b0;
if (s_lcd == LCD_STATE_4_IDLE)
begin
LCD_RS <= rs;
LCD_RW <= rw;
data_to_lcd <= data_in;
end
if (s_lcd == LCD_STATE_1_ENABLE)
data_out <= LCD_DATA;
if (s_lcd == LCD_STATE_3_END)
transfer_complete <= 1'b1;
else
transfer_complete <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
idle_counter <= {IC{1'b0}};
else if (s_lcd == LCD_STATE_4_IDLE)
idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT;
else
idle_counter <= {IC{1'b0}};
end
always @(posedge clk)
begin
if (reset)
begin
state_0_counter <= {SC{1'b0}};
state_1_counter <= {SC{1'b0}};
state_2_counter <= {SC{1'b0}};
end
else
begin
if (s_lcd == LCD_STATE_0_OPERATION)
state_0_counter <= state_0_counter + COUNTER_INCREMENT;
else
state_0_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_1_ENABLE)
state_1_counter <= state_1_counter + COUNTER_INCREMENT;
else
state_1_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_2_HOLD)
state_2_counter <= state_2_counter + COUNTER_INCREMENT;
else
state_2_counter <= {SC{1'b0}};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign LCD_DATA =
(((s_lcd == LCD_STATE_1_ENABLE) ||
(s_lcd == LCD_STATE_2_HOLD)) &&
(LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 233, mxzt = (1 << 20) + 23; int f[21][mxzt], tmp[2][mxzt][20]; int stv[maxn]; int i, j, k, n, m; char s[maxn]; int ra, fh; char rx; inline int read() { rx = getchar(), ra = 0, fh = 1; while (rx < 48) rx == - && (fh = -1), rx = getchar(); while (rx > 47) ra = ra * 10 + rx - 48, rx = getchar(); return ra * fh; } inline int getnum1(int x) { int n = 0; while (x) n += x & 1, x >>= 1; return n; } inline int min(int a, int b) { return a < b ? a : b; } int main() { n = read(), m = read(); int mx = 1 << n; for (i = 1; i <= n; i++) { scanf( %s , s + 1); for (j = 1; j <= m; j++) stv[j] = stv[j] << 1 | (s[j] - 48); } for (i = 1; i <= m; i++) f[0][stv[i]]++; int zt, p, nf; bool now = 1, pre = 0; int *nt; for (i = 1; i <= n; i++, swap(now, pre)) { for (zt = 0; zt < mx; zt++) { for (nf = p = 0, nt = tmp[now][zt]; p < n; p++, nt++) nf += (*nt = f[i - 1][zt ^ (1 << p)] - tmp[pre][zt ^ (1 << p)][p]); f[i][zt] = nf / i; } } int ans = 1e9; for (zt = 0; zt < mx; zt++) { k = 0; for (j = 0; j <= n && k < ans; j++) k += min(j, n - j) * f[j][zt]; if (j > n) ans = k; } printf( %d n , ans); }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_31ns_38_3_Mul3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[7 - 1 : 0] a; // synthesis attribute keep a "true"
input[31 - 1 : 0] b; // synthesis attribute keep b "true"
output[38 - 1 : 0] p;
reg [7 - 1 : 0] a_reg0;
reg [31 - 1 : 0] b_reg0;
wire [38 - 1 : 0] tmp_product;
reg [38 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_31ns_38_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
feedforward_mul_7ns_31ns_38_3_Mul3S_0 feedforward_mul_7ns_31ns_38_3_Mul3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , &s); } for (int i = 0; i < 10; i++) cout << ?? << i << >> << i << ?? n ; cout << ??>>? n ; for (int i = 0; i < 9; i++) { cout << i << ?<> << i + 1 << n ; } cout << 9?>>?0 n ; cout << ?<>1 n ; cout << >>?? n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, d = 0, count = 0, maxCount = 0; cin >> n >> d; string s = ; for (int i = 0; i < d; i++) { cin >> s; int res = 1; for (int j = 0; j < s.size(); j++) { res &= (s[j] - 0 ); } if (res == 1) { maxCount = max(count, maxCount); count = 0; } else { count++; } } maxCount = max(count, maxCount); cout << maxCount; return 0; }
|
#include <bits/stdc++.h> int n, a[1000][1000]; int main() { for (int i = 1; i <= 100; i++) for (int j = 1; j <= 100; j++) a[i][j] = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { int t, v; scanf( %d , &t); for (int j = 1; j <= t; j++) { scanf( %d , &v); a[i][v] = 1; } } bool f1; for (int i = 1; i <= n; i++) { f1 = true; bool f; for (int j = 1; j <= n; j++) if (i != j) { f = false; for (int k = 1; k <= 100; k++) if (a[j][k] == 1 && a[i][k] == 0) { f = true; break; } if (f == false) { f1 = false; break; } } if (f1 == true) printf( YES ); else printf( NO ); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int hcf(long long a, long long b) { if (b == 0) return a; return hcf(b, a % b); } void solve() { long long n; cin >> n; long long x = hcf(n + 1, 4 * n); long long lcm = ((4 * n) * (n + 1)) / x; cout << lcm / (n + 1) + 1; } int main() { int t = 1; cin >> t; while (t--) { solve(); cout << n ; } return 0; }
|
/*
Author: Joe Krachey
Date: 01/03/2017
*/
module ece453(
// signals to connect to an Avalon clock source interface
clk,
reset,
// signals to connect to an Avalon-MM slave interface
slave_address,
slave_read,
slave_write,
slave_readdata,
slave_writedata,
slave_byteenable,
gpio_inputs,
gpio_outputs,
irq_out
);
// most of the set values will only be used by the component .tcl file. The DATA_WIDTH and MODE_X = 3 influence the hardware created.
// ENABLE_SYNC_SIGNALS isn't used by this hardware at all but it provided anyway so that it can be exposed in the component .tcl file
// to control the stubbing of certain signals.
//parameter ENABLE_SYNC_SIGNAL S = 0; // only used by the component .tcl file, 1 to expose user_chipselect/write/read, 0 to stub them
//*******************************************************************
// Module Interface
//*******************************************************************
input clk;
input reset;
// slave interface
input [3:0] slave_address;
input slave_read;
input slave_write;
output wire [31:0] slave_readdata;
input [31:0] slave_writedata;
input [3:0] slave_byteenable;
input [31:0] gpio_inputs;
output [31:0] gpio_outputs;
output wire irq_out;
`include "ece453.vh"
//*******************************************************************
// Register Set
//*******************************************************************
reg [31:0] dev_id_r;
reg [31:0] gpio_in_r;
reg [31:0] gpio_out_r;
//*******************************************************************
// Wires/Reg
//*******************************************************************
wire [31:0] gpio_in;
wire [31:0] gpio_out;
//*******************************************************************
// Register Read Assignments
//*******************************************************************
assign slave_readdata = ( (slave_address == DEV_ID_ADDR ) && slave_read ) ? dev_id_r :
( (slave_address == GPIO_IN_ADDR ) && slave_read ) ? gpio_in_r :
( (slave_address == GPIO_OUT_ADDR ) && slave_read ) ? gpio_out_r : 32'h00000000;
//*******************************************************************
// Output Assignments
//*******************************************************************
// IRQ indicating that an interrupt is active
assign irq_out = 0;
assign gpio_outputs = gpio_out_r;
//*******************************************************************
// Register Input Equations
//*******************************************************************
// Input signals for registers
assign gpio_in = gpio_inputs;
assign gpio_out = ( (slave_address == GPIO_OUT_ADDR ) && slave_write ) ? slave_writedata : gpio_out_r;
//*******************************************************************
// Registers
//*******************************************************************
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
dev_id_r <= 32'hECE45300;
gpio_in_r <= 32'h00000000;
gpio_out_r <= 32'h00000000;
end
else
begin
dev_id_r <= 32'hECE45300;
gpio_in_r <= gpio_in;
gpio_out_r <= gpio_out;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_4_V
`define SKY130_FD_SC_HDLL__O21BA_4_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_NEW_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_REFGEN_NEW_PP_BLACKBOX_V
/**
* top_refgen_new: The REFGEN block (sky130_fd_io__top_refgen) is used
* to provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen_new (
VINREF ,
VOUTREF ,
REFLEAK_BIAS ,
AMUXBUS_A ,
AMUXBUS_B ,
DFT_REFGEN ,
HLD_H_N ,
IBUF_SEL ,
ENABLE_H ,
ENABLE_VDDA_H,
VOH_SEL ,
VOHREF ,
VREF_SEL ,
VREG_EN ,
VTRIP_SEL ,
VOUTREF_DFT ,
VINREF_DFT ,
VCCD ,
VCCHIB ,
VDDA ,
VDDIO ,
VDDIO_Q ,
VSSD ,
VSSIO ,
VSSIO_Q ,
VSWITCH ,
VSSA
);
output VINREF ;
output VOUTREF ;
inout REFLEAK_BIAS ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
input DFT_REFGEN ;
input HLD_H_N ;
input IBUF_SEL ;
input ENABLE_H ;
input ENABLE_VDDA_H;
input [2:0] VOH_SEL ;
input VOHREF ;
input [1:0] VREF_SEL ;
input VREG_EN ;
input VTRIP_SEL ;
inout VOUTREF_DFT ;
inout VINREF_DFT ;
inout VCCD ;
inout VCCHIB ;
inout VDDA ;
inout VDDIO ;
inout VDDIO_Q ;
inout VSSD ;
inout VSSIO ;
inout VSSIO_Q ;
inout VSWITCH ;
inout VSSA ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_NEW_PP_BLACKBOX_V
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; const long long inf = 1000000000000000000LL; int a[N]; long long prefix_cost[N], cost[N], suffix_cost[N]; set<int> factors; set<int>::iterator it; void pf(int x) { for (int j = x - 1; j <= x + 1; j++) { int d = j; for (int i = 2; i * i <= j; i++) { if (d % i == 0) { factors.insert(i); while (d % i == 0) d /= i; } } if (d != 1) factors.insert(d); } } int main() { int n, p, A, B; scanf( %d %d %d , &n, &A, &B); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); if (n == 1) { printf( 0 n ); return 0; } pf(a[1]); pf(a[n]); long long ans = inf; for (it = factors.begin(); it != factors.end(); ++it) { prefix_cost[0] = 0LL; p = *it; for (int i = 1; i <= n; i++) { if (a[i] % p == 0) cost[i] = 0LL; else if ((a[i] + 1) % p == 0 || (a[i] - 1) % p == 0) cost[i] = (long long)B; else cost[i] = inf; prefix_cost[i] = prefix_cost[i - 1] + cost[i]; if (prefix_cost[i] > inf) prefix_cost[i] = inf; } prefix_cost[0] = inf; suffix_cost[n + 1] = 0LL; long long suffix_sum = 0LL; for (int i = n; i > 0; i--) { suffix_sum += cost[i]; if (suffix_sum > inf) suffix_sum = inf; suffix_cost[i] = min(A + suffix_cost[i + 1], suffix_sum); } ans = min(ans, suffix_cost[1]); for (int i = 2; i <= n; i++) ans = min(ans, prefix_cost[i - 1] + suffix_cost[i]); } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 5, inf = 1e16; long long a[N], p[N], b[N], seg[N << 2], m; void shift(long long id) { if (seg[id] == 0) return; seg[id << 1] += seg[id], seg[id << 1 | 1] += seg[id]; seg[id] = 0; } void add(long long l, long long r, long long val, long long L = 0, long long R = m + 1, long long id = 1) { if (r <= L || R <= l) return; if (l <= L && R <= r) { seg[id] += val; return; } shift(id); long long mid = (L + R) >> 1; add(l, r, val, L, mid, id << 1); add(l, r, val, mid, R, id << 1 | 1); return; } long long get(long long l, long long L = 0, long long R = m + 1, long long id = 1) { if (R - L == 1) return seg[id]; shift(id); long long mid = (L + R) >> 1; if (l < mid) return get(l, L, mid, id << 1); else return get(l, mid, R, id << 1 | 1); } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n; cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) cin >> p[i]; cin >> m; for (long long i = 1; i <= m; i++) cin >> b[i]; add(1, m + 1, inf); for (long long i = 0; i < n; i++) { long long x = lower_bound(b, b + m + 1, a[i]) - b, val = inf * 10; if (a[i] == b[x]) val = get(x - 1); if (p[i] < 0) add(0, m + 1, p[i]); else add(0, x, p[i]); if (val < get(x)) add(x, x + 1, val - get(x)); } if (get(m) > 1e15) return cout << NO n , 0; cout << YES n << get(m) << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long a[n]; for (int i = 0, ggdem = n; i < ggdem; ++i) cin >> a[i]; long long yo = -1; for (int i = 0, ggdem = n; i < ggdem; ++i) { if (a[i] == -1) { yo = i; } } for (int i = 0, ggdem = yo + 1; i < ggdem; ++i) { a[i] = 0; } long long res = 0; for (long long i = 20; i >= 0; i--) { if ((1 << i) > n) continue; long long mini = 1e18, minid = -1; for (int j = (1 << i) - 1, ggdem = n; j < ggdem; ++j) { if (a[j] <= mini) { mini = a[j]; minid = j; } } res += mini; a[minid] = 1e18; } cout << res; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire GCLK_b ;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b , m0n, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( ( GATE_delayed === 1'b0 ) & awake );
assign GATE_awake = ( ( SCE_delayed === 1'b0 ) & awake );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } string s[105]; long long tot(long long i, long long j) { long long ans = 0; if (s[i][j] == 1 ) ans++; if (s[i + 1][j] == 1 ) ans++; if (s[i][j + 1] == 1 ) ans++; if (s[i + 1][j + 1] == 1 ) ans++; return ans; } vector<long long> calc(long long i, long long j, long long cnt) { vector<pair<long long, long long> > st1, st0; vector<long long> res; if (s[i][j] == 1 ) st1.push_back({i, j}); else st0.push_back({i, j}); if (s[i + 1][j] == 1 ) st1.push_back({i + 1, j}); else st0.push_back({i + 1, j}); if (s[i][j + 1] == 1 ) st1.push_back({i, j + 1}); else st0.push_back({i, j + 1}); if (s[i + 1][j + 1] == 1 ) st1.push_back({i + 1, j + 1}); else st0.push_back({i + 1, j + 1}); if (cnt == 1 || cnt == 2) { for (long long k = 0; k < 1; k++) { long long x = st1[k].first; long long y = st1[k].second; res.push_back(x); res.push_back(y); s[x][y] = 0 ; } for (long long k = 0; k < 2; k++) { long long x = st0[k].first; long long y = st0[k].second; res.push_back(x); res.push_back(y); s[x][y] = 1 ; } } else if (cnt == 3 || cnt == 4) { for (long long k = 0; k < 3; k++) { long long x = st1[k].first; long long y = st1[k].second; res.push_back(x); res.push_back(y); s[x][y] = 0 ; } } return res; } void solve() { long long n, m; cin >> n >> m; for (long long i = 0; i < n; i++) cin >> s[i]; vector<vector<long long> > ans; if (n & 1) { for (long long i = 0; i < m; i += 2) { long long x = (n - 1), y = i; if (i == (m - 1)) y = (i - 1); vector<long long> res; if (s[x][y] == 1 || s[x][y + 1] == 1 ) { if (s[x][y] == 1 && s[x][y + 1] == 1 ) { res.push_back(x); res.push_back(y); s[x][y] = 0 ; res.push_back(x); res.push_back(y + 1); s[x][y + 1] = 0 ; res.push_back(x - 1); res.push_back(y); s[x - 1][y] = (!(s[x - 1][y] - 0 )) + 0 ; } else if (s[x][y] == 1 ) { res.push_back(x); res.push_back(y); s[x][y] = 0 ; res.push_back(x - 1); res.push_back(y); s[x - 1][y] = (!(s[x - 1][y] - 0 )) + 0 ; res.push_back(x - 1); res.push_back(y + 1); s[x - 1][y + 1] = (!(s[x - 1][y + 1] - 0 )) + 0 ; } else if (s[x][y + 1] == 1 ) { res.push_back(x); res.push_back(y + 1); s[x][y + 1] = 0 ; res.push_back(x - 1); res.push_back(y); s[x - 1][y] = (!(s[x - 1][y] - 0 )) + 0 ; res.push_back(x - 1); res.push_back(y + 1); s[x - 1][y + 1] = (!(s[x - 1][y + 1] - 0 )) + 0 ; } } if (res.size() > 0) ans.push_back(res); } n--; } if (m & 1) { for (long long i = 0; i < n; i += 2) { long long x = i, y = (m - 1); if (i == (n - 1)) x = (i - 1); vector<long long> res; if (s[x][y] == 1 || s[x + 1][y] == 1 ) { if (s[x][y] == 1 && s[x + 1][y] == 1 ) { res.push_back(x); res.push_back(y); s[x][y] = 0 ; res.push_back(x + 1); res.push_back(y); s[x + 1][y] = 0 ; res.push_back(x); res.push_back(y - 1); s[x][y - 1] = (!(s[x][y - 1] - 0 )) + 0 ; } else if (s[x][y] == 1 ) { res.push_back(x); res.push_back(y); s[x][y] = 0 ; res.push_back(x); res.push_back(y - 1); s[x][y - 1] = (!(s[x][y - 1] - 0 )) + 0 ; res.push_back(x + 1); res.push_back(y - 1); s[x + 1][y - 1] = (!(s[x + 1][y - 1] - 0 )) + 0 ; } else if (s[x + 1][y] == 1 ) { res.push_back(x + 1); res.push_back(y); s[x + 1][y] = 0 ; res.push_back(x); res.push_back(y - 1); s[x][y - 1] = (!(s[x][y - 1] - 0 )) + 0 ; res.push_back(x + 1); res.push_back(y - 1); s[x + 1][y - 1] = (!(s[x + 1][y - 1] - 0 )) + 0 ; } } if (res.size() > 0) ans.push_back(res); } m--; } for (long long i = 0; i < (n); i += 2) { for (long long j = 0; j < (m); j += 2) { long long cnt = tot(i, j); while (cnt > 0) { vector<long long> res = calc(i, j, cnt); cnt = tot(i, j); ans.push_back(res); } } } cout << ans.size() << endl; for (long long i = 0; i < ans.size(); i++) { for (long long j = 0; j < 6; j++) { cout << ans[i][j] + 1 << ; } cout << endl; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; for (long long i = 0; i < t; i++) { solve(); } }
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSHIFT_TAPS
// ============================================================
// File Name: SHIFTREGRAM.v
// Megafunction Name(s):
// ALTSHIFT_TAPS
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SHIFTREGRAM (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [12:0] shiftin;
output [12:0] shiftout;
output [168:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [12:0] sub_wire0;
wire [168:0] sub_wire1;
wire [12:0] shiftout = sub_wire0[12:0];
wire [168:0] taps = sub_wire1[168:0];
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.clken (clken),
.shiftin (shiftin),
.shiftout (sub_wire0),
.taps (sub_wire1)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone II",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 13,
ALTSHIFT_TAPS_component.tap_distance = 5,
ALTSHIFT_TAPS_component.width = 13;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "13"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "5"
// Retrieval info: PRIVATE: WIDTH NUMERIC "13"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "13"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH NUMERIC "13"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: shiftin 0 0 13 0 INPUT NODEFVAL "shiftin[12..0]"
// Retrieval info: USED_PORT: shiftout 0 0 13 0 OUTPUT NODEFVAL "shiftout[12..0]"
// Retrieval info: USED_PORT: taps 0 0 169 0 OUTPUT NODEFVAL "taps[168..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @shiftin 0 0 13 0 shiftin 0 0 13 0
// Retrieval info: CONNECT: shiftout 0 0 13 0 @shiftout 0 0 13 0
// Retrieval info: CONNECT: taps 0 0 169 0 @taps 0 0 169 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; void err() { cout << n ; } template <class T, class... Ts> void err(const T& arg, const Ts&... args) { cout << arg << ; err(args...); } inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } void run() { int n = read(); long long sum = 0; long long ans = 0; while (n--) { int a = read(); sum += a; ans = ((ans) < (sum) ? (ans) : (sum)); } cout << -ans << n ; } int main() { int _T = read(); while (_T--) run(); return 0; }
|
(*
* Copyright © 2013 http://io7m.com
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*)
(** The archive handler, mapping file types to archive implementations. *)
Require Archive.
Require Error.
Require FilesystemOp.
Require PathReal.
Require PathVirtual.
(** Abbreviations. *)
Module E := Error.
Open Scope list_scope.
(** An archive handler takes the name of an archive and returns an archive
implementation for the name iff there is an archive implementation that can
handle archives of that type. *)
Record t := ArchiveHandler {
(** Returns [true] iff the handler can handle the type of the archive at [p]. Note
that this test is purely based on file names. *)
can_handle : forall (p : PathReal.t), bool;
(** Load the archive at [p] using mount point [m]. *)
load : forall (p : PathReal.t) (m : PathVirtual.t), FilesystemOp.t Archive.t;
(** The [load] function always sets the correct mount point. *)
load_path_correct : forall (p : PathReal.t) (m : PathVirtual.t) (r : Archive.t),
load p m = E.Success r -> (Archive.mount_path r) = m
}.
(** The list of known archive handlers is immutable. *)
Parameter handlers : list t.
(** Given a list of archive handlers, the first handler that can handle an
archive is one that is used to load the archive. *)
Fixpoint handle
(handlers : list t)
(p : PathReal.t)
(m : PathVirtual.t)
: FilesystemOp.t Archive.t :=
match handlers with
| nil => Error.Failure FilesystemOp.Error_Unsupported_Archive
| h :: hs =>
if (can_handle h) p
then (load h) p m
else handle hs p m
end.
|
#include <bits/stdc++.h> using namespace std; int n, k; int c[5005], h[11], f[505]; int cnt[100005]; int fcnt[100005]; int cache[5005][505]; int solve(int idx1, int idx2) { if (idx1 == 0 || idx2 == 0) return 0; int &ret = cache[idx1][idx2]; if (ret != -1) return ret; ret = 0; for (int i = 0; i <= k && i <= idx1; i++) ret = max(ret, solve(idx1 - i, idx2 - 1) + h[i]); return ret; } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n * k; i++) { scanf( %d , &c[i]); cnt[c[i]]++; } for (int i = 0; i < n; i++) { scanf( %d , &f[i]); fcnt[f[i]]++; } for (int i = 1; i <= k; i++) scanf( %d , &h[i]); int ans = 0; for (int i = 0; i < 100005; i++) { if (fcnt[i]) { memset(cache, -1, sizeof(cache)); ans += solve(cnt[i], fcnt[i]); } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace Flandre_Scarlet { long long mod; class Matrix { private: long long a[5][5]; public: long long n; Matrix() { memset(a, 0, sizeof(a)); n = 0; } Matrix(long long _n) { memset(a, 0, sizeof(a)); n = _n; } Matrix(long long _n, long long _x) { _x %= mod; n = _n; for (long long i = 0; i < 5; ++i) { for (long long j = 0; j < 5; ++j) { a[i][j] = _x; } } } long long* operator[](long long i) { return *(a + i); } void Set(long long x) { x %= mod; for (long long i = 0; i < 5; ++i) { for (long long j = 0; j < 5; ++j) { a[i][j] = x; } } } void Identity() { memset(a, 0, sizeof(a)); for (long long i = 0; i < 5; ++i) { a[i][i] = 1; } } }; Matrix operator*(Matrix x, Matrix y) { Matrix ans(x.n, 0); long long n = ans.n; for (long long i = 1; i <= n; ++i) { for (long long j = 1; j <= n; ++j) { for (long long k = 1; k <= n; ++k) { ans[i][j] += x[i][k] * y[k][j]; ans[i][j] %= mod; } } } return ans; } Matrix operator^(Matrix x, long long p) { Matrix ans(x.n, 1); ans.Identity(); while (p) { if (p & 1) ans = ans * x; x = x * x, p >>= 1; } return ans; } long long Fib(long long x) { Matrix Init(2, 0); Init[1][1] = 0, Init[1][2] = 1; Matrix Trans(2, 1); Trans[1][1] = 0; Matrix Ans = Init * (Trans ^ x); return Ans[1][1]; } long long l, r, k; void R1(long long& x) { x = 0; char c = getchar(); long long f = 1; while (c < 0 or c > 9 ) f = (c == - ) ? -1 : 1, c = getchar(); while (c >= 0 and c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); x = (f == 1) ? x : -x; } void Input() { R1(mod); R1(l), R1(r), R1(k); } bool cxk(long long x) { return (r / x - (l - 1) / x) >= k; } void Soviet() { long long ans = -0x3f3f3f3f; for (long long i = 1; i * i <= r; ++i) { if (cxk(i)) ans = max(ans, i); if (cxk(r / i)) ans = max(ans, r / i); } printf( %lld n , Fib(ans)); } void IsMyWife() { Input(); Soviet(); } } // namespace Flandre_Scarlet int main() { Flandre_Scarlet::IsMyWife(); getchar(); getchar(); return 0; }
|
//==================================================================================================
// Filename : Mux_3x1_b.v
// Created On : 2016-10-03 16:53:16
// Last Modified : 2016-10-04 10:27:42
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Mux_3x1_bv2 #(parameter W=32)
(
//Input Signals
input wire [1:0] select,
input wire [W-1:0] ch_0,
input wire [W-1:0] ch_1,
input wire [W-1:0] ch_2,
//Output Signals
output reg [W-1:0] data_out
);
always @*
begin
case(select)
2'b00: data_out <= {W{1'b0}};
2'b01: data_out <= ch_0;
2'b10: data_out <= ch_1;
2'b11: data_out <= ch_2;
default : data_out <= ch_0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, y = 0; cin >> a >> b; while (a <= b) { a *= 3; b *= 2; y++; } cout << y; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; long long fact[100001]; vector<long long> vec[100001]; long long vis[100001], win[100001], flag[100001]; long long power(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = (res * x) % mod; x = (x * x) % mod; y >>= 1; } return res; } long long nCr(long long n, long long r) { if (r > n) return 0; else if (r < 0) return 0; else if (r == 0 || r == n) return 1; long long ans = fact[n]; ans = (ans * power(fact[n - r], mod - 2)) % mod; ans = (ans * power(fact[r], mod - 2)) % mod; return ans; } void dfs(long long x) { vis[x] = 1; for (long long i = 0; i < vec[x].size(); i++) { long long node = vec[x][i]; if (vis[node] == -1) dfs(node); if (win[node] == 0) flag[x] = 1; } if (flag[x] == 1) win[x] = 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; long long a[n + 1]; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 1; i <= n; i++) { for (long long j = i; j > 0; j -= a[i]) { if (a[j] > a[i]) vec[a[i]].push_back(a[j]); } for (long long j = i; j <= n; j += a[i]) { if (a[j] > a[i]) vec[a[i]].push_back(a[j]); } } for (long long i = 1; i <= n; i++) { vis[i] = -1; win[i] = 0; flag[i] = 0; } dfs(1); string s; for (long long i = 1; i <= n; i++) { if (win[a[i]] == 1) s += A ; else s += B ; } cout << s << endl; for (long long i = 1; i <= n; i++) vec[i].clear(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; t = 1; while (t--) { long long n, a[8] = {0}, k; cin >> n; for (int i = 0; i <= n - 1; i++) { cin >> k; a[k]++; } if (a[5] > 0 || a[7] > 0 || a[1] != n / 3 || a[3] > a[6] || a[4] > a[2] || ((a[3] + a[2]) != n / 3) || ((a[4] + a[6]) != n / 3)) { cout << -1; return 0; } while (a[4]) { cout << 1 2 4 << n ; a[4]--; a[2]--; } while (a[2]) { cout << 1 2 6 << n ; a[2]--; } while (a[3]) { cout << 1 3 6 << n ; a[3]--; } } cerr << Time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; }
|
#include <bits/stdc++.h> int main() { char s[512]; scanf( %s , s); int length = strlen(s); int i; int alpha_cnt = 0; for (i = 0; i < length; i++) { if (s[i] - a > alpha_cnt) { puts( NO ); return 0; } if (s[i] - a == alpha_cnt) { alpha_cnt++; } } puts( YES ); return 0; }
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#include <bits/stdc++.h> using namespace std; int N; int A[3][30]; int p3[30]; map<pair<int, int>, pair<int, signed long long> > M[2]; void solve() { int i, j, k, l, r, x, y; string s; cin >> N; p3[0] = 1; for (i = 0; i < N; i++) p3[i + 1] = p3[i] * 3; for (i = 0; i < N; i++) cin >> A[0][i] >> A[1][i] >> A[2][i]; for (signed long long mask = 0; mask < p3[min(N, 13)]; mask++) { int t[3] = {}, tm = mask; for (i = 0; i < min(N, 13); i++) { x = tm % 3, tm /= 3; if (x == 0) t[0] += A[0][i], t[1] += A[1][i]; if (x == 1) t[0] += A[0][i], t[2] += A[2][i]; if (x == 2) t[1] += A[1][i], t[2] += A[2][i]; } M[0][{t[0] - t[1], t[0] - t[2]}] = max(M[0][{t[0] - t[1], t[0] - t[2]}], {t[0] + (1LL << 29), mask}); } for (signed long long mask = 0; mask < p3[max(0, N - 13)]; mask++) { int t[3] = {}, tm = mask; for (i = 0; i < max(0, N - 13); i++) { x = tm % 3, tm /= 3; if (x == 0) t[0] += A[0][13 + i], t[1] += A[1][13 + i]; if (x == 1) t[0] += A[0][13 + i], t[2] += A[2][13 + i]; if (x == 2) t[1] += A[1][13 + i], t[2] += A[2][13 + i]; } M[1][{t[1] - t[0], t[2] - t[0]}] = max(M[1][{t[1] - t[0], t[2] - t[0]}], {t[0] + (1LL << 29), mask * p3[13]}); } signed long long co = -1LL << 40; signed long long best = -1; for (auto& r : M[1]) if (M[0].count(r.first) && r.second.first + M[0][r.first].first > co) { co = r.second.first + M[0][r.first].first; best = r.second.second + M[0][r.first].second; } if (best == -1) (void)printf( Impossible n ); else { for (i = 0; i < N; i++) { x = best % 3; best /= 3; if (x == 0) (void)printf( LM n ); if (x == 1) (void)printf( LW n ); if (x == 2) (void)printf( MW n ); } } } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false); for (i = 0; i < argc - 1; i++) s += argv[i + 1], s += n ; for (i = 0; i < s.size(); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
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///2016/8/6
///ShaoMin Zhai
///module function: used to debug core
`include "define.v"
module top_level(
clk,
rst
);
input clk;
input rst;
wire [31:0] pc;
wire [31:0] mem_data;
wire [31:0] mem_addr;
wire [3:0] mem_head;
wire v_mem;
wire v_pc;
wire [31:0] data;
wire v_data;
wire [31:0] inst;
wire v_inst;
core core_du(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_data),
.data(data),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
instmem instmem_du(
.clk(clk),
.rst(rst),
.pc(pc),
.read(v_pc),
.inst(inst),
.v_inst(v_inst)
);
datamem datamem_du(
.clk(clk),
.rst(rst),
.addr(mem_addr),
.data_in(mem_data),
.r_w(mem_head[3]),
.v_cmd(v_mem),
.data_out(data),
.v_data_out(v_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LNF = 0x3f3f3f3f3f3f3f3f; const int MOD = 1000000007; const double EPS = 1e-8; const long double EUL = 2.71828182845904523536; const long double PII = 3.14159265358979323846; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, d; while (cin >> n >> m >> d) { int coffee[n]; int ans[n]; set<pair<int, int> > timeline; for (int i = 0; i < n; i++) { cin >> coffee[i]; timeline.insert({coffee[i], i}); } int day = 0; while (!timeline.empty()) { day++; int x = timeline.begin()->second; ans[x] = day; timeline.erase(timeline.begin()); while (1) { auto it = timeline.lower_bound({coffee[x] + d + 1, -1}); if (it == timeline.end()) break; x = it->second; ans[x] = day; timeline.erase(it); } } cout << day << endl; for (int i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } cerr << Time : << 1000 * (long double)clock() / (long double)CLOCKS_PER_SEC << ms n ; return 0; }
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
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#include <bits/stdc++.h> bool isvowel(char s) { if (s == a || s == A || s == e || s == E || s == i || s == I || s == o || s == O || s == u || s == U ) return true; else return false; } long long fact(long long n) { long long mul = 1; for (long long i = 1; i <= n; i++) mul = mul * i; return mul; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b % 1000000007, (a % b) % 1000000007); } using namespace std; int main() { int n; cin >> n; if (n & 1) cout << -1 << n ; else { for (int i = 1; i <= n; i += 2) { cout << i + 1 << << i << ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 2e18; const double PI = acos(-1.0); const double E = exp(1); const double EPS = 1e-8; const long long mod = 1e4 + 7; const int maxn = 3e5 + 5; void pre() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } struct node { long long l, r; bool operator<(const node &q) const { return l > q.l; } } arr[maxn]; priority_queue<long long, vector<long long>, greater<long long> > que; int num; long long k1, k2; int www; int main(void) { cin >> num; scanf( %I64d%I64d , &arr[0].l, &arr[0].r); k1 = arr[0].l, k2 = arr[0].r; for (int i = (1); i < (num); i++) { scanf( %I64d%I64d , &arr[i].l, &arr[i].r); } sort(arr, arr + num); int rk = 0; int nxt = 0; for (int i = 0; i < (num); i++) { if (arr[i].l == k1 && arr[i].r == k2) { www = i; if (rk == 0) rk = i + 1; break; } else if (arr[i].l == k1) { if (rk == 0) rk = i + 1; } que.push(arr[i].r - arr[i].l + 1); } nxt = rk; int pos = rk; while (!que.empty()) { long long cur = que.top(); if (cur <= k1) k1 -= cur; else break; que.pop(); pos--; for (int i = (nxt); i < (num); i++) { if (i == www) continue; if (k1 < arr[i].l) { que.push(arr[i].r - arr[i].l + 1); pos++; nxt++; } else { break; } } rk = min(rk, pos); } cout << rk << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f[100]; int s[100]; long long dp[100][2]; int main() { f[0] = f[1] = 1; for (int i = 2; i < 100; i++) { f[i] = f[i - 1] + f[i - 2]; } int cas; cin >> cas; while (cas--) { long long n; cin >> n; int cnt = 0; for (int i = 90; i >= 1; i--) { if (n >= f[i]) { n -= f[i]; s[++cnt] = i; } } reverse(s + 1, s + cnt + 1); dp[0][0] = 1; dp[0][1] = 0; for (int i = 1; i <= cnt; i++) { dp[i][0] = dp[i - 1][0] + dp[i - 1][1]; dp[i][1] = dp[i - 1][0] * ((s[i] - s[i - 1] - 1) / 2) + dp[i - 1][1] * ((s[i] - s[i - 1]) / 2); } cout << dp[cnt][0] + dp[cnt][1] << endl; } return 0; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// web: http://www.latticesemi.com/
// email:
//
// =============================================================================
// REVISION HISTORY
// Version : 7.2
// Changes Made : Initial Creation
// Baudrate Generation is modified.
// RX and TX path of the UART is updated to faster clock
// 16 word deep FIFO is implemented when FIFO option is
// selected
// ============================================================================
`ifndef TXFIFO_FILE
`define TXFIFO_FILE
`include "system_conf.v"
module txcver_fifo (Data, Clock, WrEn, RdEn, Reset, Q, Empty, Full,
AlmostEmpty, AlmostFull);
input [7:0] Data;
input Clock;
input WrEn;
input RdEn;
input Reset;
output [7:0] Q;
output Empty;
output Full;
output AlmostEmpty;
output AlmostFull;
parameter lat_family = `LATTICE_FAMILY;
generate
if (lat_family == "SC" || lat_family == "SCM") begin
pmi_fifo_dc #(.pmi_data_width_w(8),
.pmi_data_width_r(8),
.pmi_data_depth_w(16),
.pmi_data_depth_r(16),
.pmi_full_flag(16),
.pmi_empty_flag(0),
.pmi_almost_full_flag(8),
.pmi_almost_empty_flag(4),
.pmi_regmode("noreg"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_fifo_dc"),
.pmi_implementation("LUT"))
tx_fifo_inst_dc (
.Data(Data),
.WrClock(Clock),
.RdClock(Clock),
.WrEn (WrEn),
.RdEn (RdEn),
.Reset (Reset),
.RPReset(Reset),
.Q (Q),
.Empty (Empty),
.Full (Full),
.AlmostEmpty (AlmostEmpty),
.AlmostFull (AlmostFull));
end else begin
pmi_fifo #(
.pmi_data_width(8),
.pmi_data_depth(16),
.pmi_full_flag(16),
.pmi_empty_flag(0),
.pmi_almost_full_flag(8),
.pmi_almost_empty_flag(4),
.pmi_regmode("noreg"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_fifo"),
.pmi_implementation("LUT"))
tx_fifo_inst
(.Data(Data),
.Clock(Clock),
.WrEn(WrEn),
.RdEn(RdEn),
.Reset(Reset),
.Q(Q),
.Empty(Empty),
.Full(Full),
.AlmostEmpty(AlmostEmpty),
.AlmostFull(AlmostFull));
end
endgenerate
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int maxn = 31; const int mod = 1000000007; struct ma { long long a[maxn][maxn]; int n; ma(int m = 0) { n = m; memset(a, 0, sizeof(a)); for (int i = 0; i < n; i++) a[i][i] = 1; } ma(const ma& nn) { n = nn.n; memcpy(a, nn.a, sizeof(a)); } ma operator*(const ma& nn) { ma ret(n); memset(ret.a, 0, sizeof(ret.a)); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { for (int k = 0; k < n; k++) ret.a[i][j] += a[i][k] * nn.a[k][j] % mod; ret.a[i][j] %= mod; } return ret; } }; ma mypow(ma a, long long n) { ma ret(a.n); while (n) { if (n & 1) ret = ret * a; n >>= 1; a = a * a; } return ret; } ma m1[100], m2[100]; int main() { long long n; int k, i, j; cin >> n >> k; n--; m1[1].n = k + 1; for (i = 0; i <= k; i++) m1[1].a[i][i] = 1; for (i = 1; i < 99; i++) { int tmp = ((-i - 1) % k + k) % k + 1; tmp = k - tmp; memcpy(m2[i].a[0], m1[i].a[k], sizeof(m1[i].a[k])); for (j = 1; j <= k; j++) { for (int c = 0; c <= k; c++) m2[i].a[j][c] = ((m2[i].a[j - 1][c] * 2 - m1[i].a[tmp][c]) % mod + mod) % mod; tmp++; if (tmp >= k) tmp = 0; } m2[i].n = k + 1; m1[i + 1] = m1[i] * mypow(m2[i], k - 1); } ma ans(k + 1); int ind = 1, sheng = n % k; n /= k; while (n) { ans = ans * mypow(m2[ind], n % k); ind++, n /= k; } long long ret = 0; for (i = 0; i <= k; i++) ret = (ret + ans.a[sheng + 1][i] * (1ll << i)) % mod; cout << ret << endl; }
|
module BufferIn(
input wire Clk,
input wire InputBuffer,
output reg [17:0] oBufferIn,
output reg EndOfFile
);
reg [17:0] tmpChar;
integer i;
initial
begin
i = $fopen("original.txt");
EndOfFile = 1'b0;
end
always @ (posedge Clk)
begin
if(InputBuffer)
begin
tmpChar = $fgetc(i);
if($feof(i))
EndOfFile = 1'b1;
else
oBufferIn = tmpChar;
end
end
endmodule
module BufferOut(
input wire Clk,
input wire OutputBuffer,
input wire CloseBuffer,
input wire [11:0] iBufferOut
);
integer f;
initial
f = $fopen("compressed.txt");
always @ (posedge Clk)
begin
if(OutputBuffer)
$fwrite(f,"%b", iBufferOut);
if(CloseBuffer)
begin
$fflush(f);
$fclose(f);
$finish;
end
end
endmodule
module RAMBuffer(
input wire RAMread,
input wire RAMZeroData,
input wire InitRAMCode,
input wire WriteString,
input wire [7:0] ramCode,
input wire [15:0] ramString,
input wire [17:0] ramDicPointer,
output reg [15:0] oRAMBuffer
);
reg [15:0] RAM [262143:0];
always @ (*)
begin
if(RAMZeroData)
RAM[ramDicPointer] = 16'b0;
else if(InitRAMCode)
RAM[ramDicPointer] = {8'b0, ramCode};
else if(WriteString)
RAM[ramDicPointer] = ramString;
else if(RAMread)
oRAMBuffer = RAM[ramDicPointer];
end
endmodule
|
module RegBank
#(
parameter WORD_SIZE = 32,
parameter MAX_NUMBER = 32'hffffffff,
parameter PC_REGISTER = 15,
parameter SP_REGISTER = 14,
parameter SPECREG_LENGTH = 4,
parameter KERNEL_STACK = 7167,
parameter USER_STACK = 8191,
parameter OS_START = 3072,
parameter SP_KEEPER_REGISTER = 6,
parameter SYSTEM_CALL_REGISTER = 7,
parameter PC_KEEPER_REGISTER = 13
)(
input enable, reset, slow_clock, fast_clock,
input [2:0] control,
input [3:0] register_source_A, register_source_B, register_Dest,
input [(WORD_SIZE - 1) : 0] ALU_result, data_from_memory,
input [(WORD_SIZE - 1) : 0] new_SP, new_PC,
output reg [(WORD_SIZE - 1) : 0] read_data_A, read_data_B,
output reg [(WORD_SIZE - 1) : 0] current_PC, current_SP, memory_output,
input [(SPECREG_LENGTH - 1) : 0] special_register
);
reg [(WORD_SIZE - 1) : 0] Bank [15:0];
wire RD_isnt_special;
assign RD_isnt_special = register_Dest != PC_REGISTER && register_Dest!= 14;
always @ (posedge fast_clock) begin
read_data_A <= Bank[register_source_A];
read_data_B <= Bank[register_source_B];
current_PC <= Bank[PC_REGISTER];
current_SP <= Bank[SP_REGISTER];
memory_output <= Bank[register_Dest];
end
always @ (posedge slow_clock) begin
if (reset) begin
Bank[SP_REGISTER] <= USER_STACK;
Bank[PC_REGISTER] <= 0;
end else begin
if (enable) begin
case (control)
1:begin //RD=ALU_result
if(RD_isnt_special) begin
Bank[register_Dest] <= ALU_result;
end
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
2:begin //RD=data_from_memory
if(RD_isnt_special)begin
Bank[register_Dest] <= data_from_memory;
end
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
3:begin //Enter privileged mode
Bank[SP_KEEPER_REGISTER] <= Bank[SP_REGISTER];
Bank[PC_KEEPER_REGISTER] <= Bank[PC_REGISTER];
Bank[PC_REGISTER] <= OS_START;
Bank[SP_REGISTER] <= KERNEL_STACK;
Bank[SYSTEM_CALL_REGISTER] <= ALU_result;
end
4:begin //Exit privileged mode
Bank[SP_REGISTER] <= Bank[SP_KEEPER_REGISTER];
Bank[PC_REGISTER] <= Bank[PC_KEEPER_REGISTER];
end
5:begin // CPXR COPY SPECIAL REGISTER
if(RD_isnt_special)
Bank[register_Dest] <= special_register;
Bank[PC_REGISTER] <= new_PC;
Bank[SP_REGISTER] <= new_SP;
end
default:begin
Bank[SP_REGISTER] <= new_SP;
Bank[PC_REGISTER] <= new_PC;
end
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; const long long MOD = 1e9 + 7; long long n, a[55]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (a[0] == a[n / 2]) cout << Bob ; else cout << Alice ; }
|
//-----------------------------------------------------
// Design Name : rrab_t
// File Name : rrab_t.v
// Function : Testing rrab.v design.
// Coder : hydai
//-----------------------------------------------------
module rrab_t;
reg reset_n, clk;
reg [1:0] request;
wire [1:0] grant;
rrab rrab_instance(
grant,
request,
clk,
reset_n
);
initial begin
$monitor("%t request = %b grant = %b", $time, request, grant);
#0 reset_n = 1'b0; clk = 0;
#45 reset_n = 1'b1; request = 2'b00;
#25 request = 2'b00;
#25 request = 2'b01;
#25 request = 2'b10;
#25 request = 2'b11;
#45 request = 2'b00;
#55 request = 2'b01;
#65 request = 2'b10;
#75 request = 2'b11;
#25 request = 2'b00;
#35 request = 2'b01;
#45 request = 2'b10;
#55 request = 2'b11;
#75 request = 2'b00;
#65 request = 2'b01;
#55 request = 2'b10;
#45 request = 2'b11;
#55 request = 2'b00;
#45 request = 2'b01;
#35 request = 2'b10;
#25 request = 2'b11;
#100 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$dumpfile("rrab.vcd");
$dumpvars;
end
endmodule // End of rrab_t
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000009; int n, m, k; class Mat { public: long long e[2][2]; Mat mul(Mat u) { Mat s; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { s.e[i][j] = 0; for (int k = 0; k < 2; k++) { s.e[i][j] += e[i][k] * u.e[k][j]; s.e[i][j] %= mod; } } } return s; } Mat powMat(Mat u, int k) { Mat mat; memset(mat.e, 0, sizeof(mat.e)); mat.e[0][0] = 1; mat.e[1][1] = 1; while (k) { if (k & 1) { mat = mat.mul(u); } u = u.mul(u); k = (k >> 1); } return mat; } }; bool good(int mid) { int n1 = n - mid * k; int m1 = m - mid * k; int ans = n1 / k * (k - 1) + n1 % k; if (ans >= m1) return true; return false; } int main() { scanf( %d%d%d , &n, &m, &k); int l = 0, r = m / k; int mid; while (l < r) { mid = (l + r) / 2; if (good(mid)) r = mid; else l = mid + 1; } Mat u; u.e[0][0] = (long long)k; u.e[0][1] = 1L; u.e[1][0] = 0; u.e[1][1] = 0; Mat v; v.e[0][0] = 2L; v.e[0][1] = 0; v.e[1][0] = (long long)k; v.e[1][1] = 1L; u = u.mul(v.powMat(v, l)); long long ans = (u.e[0][0] - k + (m - l * k) + mod) % mod; cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_1_V
`define SKY130_FD_SC_HD__A21BOI_1_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; long long a[N]; struct t { int lval, rval, mval; } tr[N * 4]; int sign(long long x) { if (x > 0) return 1; if (x < 0) return -1; return 0; } inline void cal(int cur, int l, int r) { int m = (l + r) / 2; int dcur = cur + cur, u = dcur, v = u + 1; tr[cur].mval = max(tr[u].mval, tr[v].mval); tr[cur].lval = tr[u].lval; tr[cur].rval = tr[v].rval; if (!(!a[m] || !a[m + 1] || sign(a[m]) < sign(a[m + 1]))) { tr[cur].mval = max(tr[cur].mval, tr[u].rval + tr[v].lval); if (tr[dcur].mval == m - l + 1) { tr[cur].lval = tr[u].lval + tr[v].lval; } if (tr[dcur + 1].mval == r - m) { tr[cur].rval = tr[v].rval + tr[u].rval; } } } void build(int pos, int l, int r) { if (l == r) { int x = !!a[l]; tr[pos].lval = tr[pos].rval = tr[pos].mval = x; return; } int mid = (l + r) >> 1; build(pos * 2, l, mid); build(pos * 2 + 1, mid + 1, r); cal(pos, l, r); } void update(int pos, int l, int r, int k, int d) { int mid = (l + r) >> 1; if (l == r) { a[l] += d; int x = !!a[l]; tr[pos].lval = tr[pos].rval = tr[pos].mval = x; return; } else { int mid = (l + r) >> 1; if (k <= mid) update(pos * 2, l, mid, k, d); else update(pos * 2 + 1, mid + 1, r, k, d); cal(pos, l, r); } } int main() { int u, v, n, i, m, l, r, d; cin >> n; cin >> u; for (i = 1; i < n; ++i) scanf( %d , &v), a[i - 1] = v - u, u = v; if (n > 1) build(1, 0, n - 2); cin >> m; while (m--) { scanf( %d%d%d , &l, &r, &u); if (n == 1) { printf( 1 n ); } else { if (l > 1) update(1, 0, n - 2, l - 2, u); if (r < n) update(1, 0, n - 2, r - 1, -u); printf( %d n , tr[1].mval + 1); } } }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_lvt_1ht.v: Multiported-RAM based on onehot-coded LVT //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_lvt_1ht
#( parameter MEMD = 16, // memory depth
parameter DATAW = 8 , // data width
parameter nRPORTS = 7 , // number of reading ports
parameter nWPORTS = 11, // number of writing ports
parameter WAW = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAW = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDW = 0 , // new data for Read-During-Write
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nWPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output reg [DATAW *nRPORTS-1:0] RData); // read data - packed from nRPORTS read ports
localparam ADDRW = `log2(MEMD ); // address width
//localparam LVTW = `log2(nWPORTS); // LVT width
// unpacked/pack addresses/data
reg [ADDRW -1:0] WAddr2D [nWPORTS-1:0] ; // write addresses / 2D
reg [DATAW -1:0] WData2D [nWPORTS-1:0] ; // write data / 2D
wire [DATAW*nRPORTS -1:0] RData2Di [nWPORTS-1:0] ; // read data / internal / 2D
reg [DATAW -1:0] RData3Di [nWPORTS-1:0][nRPORTS-1:0]; // read data / internal / 3D
reg [DATAW -1:0] RData3Dz [nWPORTS-1:0][nRPORTS-1:0]; // read data / high-z / 3D
wire [DATAW -1:0] RData2D [nRPORTS-1:0] ; // read data / output / 2D
wire [nWPORTS*nRPORTS-1:0] RBank ; // read bank selector / 1D
reg [nWPORTS -1:0] RBank2D [nRPORTS-1:0] ; // read bank selector / 2D
`ARRINIT;
always @* begin
`ARR1D2D(nWPORTS, ADDRW,WAddr ,WAddr2D );
`ARR1D2D(nWPORTS, DATAW,WData ,WData2D );
`ARR2D3D(nWPORTS,nRPORTS,DATAW,RData2Di,RData3Di);
`ARR2D1D(nRPORTS, DATAW,RData2D ,RData );
`ARR1D2D(nRPORTS,nWPORTS ,RBank ,RBank2D );
end
// instantiate LVT
lvt_1ht #( .MEMD (MEMD ), // memory depth
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.WAW (WAW ), // allow Write-After-Write (need to bypass feedback ram)
.RAW (RAW ), // new data for Read-after-Write (need to bypass output ram)
.RDW (RDW ), // new data for Read-During-Write
.IZERO (IFILE!=""), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE ("" )) // initialization file, optional
lvt_1ht_ins ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPORTS-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - in : [ADDRW *nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [ADDRW *nRPORTS-1:0]
.RBank (RBank )); // 1hot bank selector - packed from nRPORTS read ports - out: [nWPORTS*nRPORTS-1:0]
// generate and instantiate mulriread RAM blocks
genvar wpi,rpi;
generate
for (wpi=0 ; wpi<nWPORTS ; wpi=wpi+1) begin: WPORTram
// ram_multiread instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.BYPASS (RDW ), // bypass? 0:none; 1:single-stage; 2:two-stages
.IZERO (0 ), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE (wpi?"":IFILE )) // initialization file, optional
mrram_ins ( .clk (clk ), // clock - in
.WEnb (WEnb[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D[wpi] ), // write address (1 port) - in : [ADDRW -1:0]
.WData (WData2D[wpi] ), // write data (1 port) - in : [DATAW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [ADDRW*nRPORTS-1:0]
.RData (RData2Di[wpi])); // read data - packed from nRPORTS read ports - out: [DATAW*nRPORTS-1:0]
end
// infer tri-state buffers and connect busses
for (rpi=0 ; rpi<nRPORTS ; rpi=rpi+1) begin: RPORTbus
for (wpi=0 ; wpi<nWPORTS ; wpi=wpi+1) begin: WPORTbus
assign RData2D[rpi] = RBank2D[rpi][wpi] ? RData3Di[wpi][rpi] : {DATAW{1'bz}};
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_gt_common.v
// Version : 4.1
`timescale 1ns / 1ps
module pcie3_7x_0_gt_common #(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device
parameter PCIE_USE_MODE = "2.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)
(
input PIPE_CLK,
input QPLL_QPLLPD,
input QPLL_QPLLRESET,
input QPLL_DRP_CLK,
input QPLL_DRP_RST_N,
input QPLL_DRP_OVRD,
input QPLL_DRP_GEN3,
input QPLL_DRP_START,
output [5:0] QPLL_DRP_CRSCODE,
output [8:0] QPLL_DRP_FSM,
output QPLL_DRP_DONE,
output QPLL_DRP_RESET,
output QPLL_QPLLLOCK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK
);
//---------- QPLL DRP Module Output --------------------
wire [7:0] qpll_drp_addr;
wire qpll_drp_en;
wire [15:0] qpll_drp_di;
wire qpll_drp_we;
//---------- QPLL Wrapper Output -----------------------
wire [15:0] qpll_drp_do;
wire qpll_drp_rdy;
//---------- QPLL Resets -----------------------
//---------- QPLL DRP Module ---------------------------------------
pcie3_7x_0_qpll_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_drp_i
(
//---------- Input -------------------------
.DRP_CLK (QPLL_DRP_CLK),
.DRP_RST_N (!QPLL_DRP_RST_N),
.DRP_OVRD (QPLL_DRP_OVRD),
.DRP_GEN3 (&QPLL_DRP_GEN3),
.DRP_QPLLLOCK (QPLL_QPLLLOCK),
.DRP_START (QPLL_DRP_START),
.DRP_DO (qpll_drp_do),
.DRP_RDY (qpll_drp_rdy),
//---------- Output ------------------------
.DRP_ADDR (qpll_drp_addr),
.DRP_EN (qpll_drp_en),
.DRP_DI (qpll_drp_di),
.DRP_WE (qpll_drp_we),
.DRP_DONE (QPLL_DRP_DONE),
.DRP_QPLLRESET (QPLL_DRP_RESET),
.DRP_CRSCODE (QPLL_DRP_CRSCODE),
.DRP_FSM (QPLL_DRP_FSM)
);
//---------- QPLL Wrapper ------------------------------------------
pcie3_7x_0_qpll_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_wrapper_i
(
//---------- QPLL Clock Ports --------------
.QPLL_GTGREFCLK (PIPE_CLK),
.QPLL_QPLLLOCKDETCLK (1'd0),
.QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK),
.QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK),
.QPLL_QPLLLOCK (QPLL_QPLLLOCK),
//---------- QPLL Reset Ports --------------
.QPLL_QPLLPD (QPLL_QPLLPD),
.QPLL_QPLLRESET (QPLL_QPLLRESET),
//---------- QPLL DRP Ports ----------------
.QPLL_DRPCLK (QPLL_DRP_CLK),
.QPLL_DRPADDR (qpll_drp_addr),
.QPLL_DRPEN (qpll_drp_en),
.QPLL_DRPDI (qpll_drp_di),
.QPLL_DRPWE (qpll_drp_we),
.QPLL_DRPDO (qpll_drp_do),
.QPLL_DRPRDY (qpll_drp_rdy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ii = pair<int, int>; using vi = vector<int>; using vvi = vector<vi>; using vii = vector<ii>; using vb = vector<bool>; using ll = long long; template <typename A, typename B> istream &operator>>(istream &in, pair<A, B> &p) { in >> p.first >> p.second; return in; } template <typename T> istream &operator>>(ifstream &in, vector<T> &v) { for (int i = 0; i < (int)v.size(); ++i) { in >> v[i]; } return in; } int main() { int n, k; cin >> n >> k; vector<set<int>> times(n); for (int i = 0; i < k; ++i) { int x; cin >> x; x--; times[x].insert(i); } int res = 0; for (int x = 0; x < n; ++x) { if (times[x].empty()) { res += 3; if (x == 0) res--; if (x == n - 1) res--; } else { int t = *times[x].begin(); if (x != n - 1 && times[x + 1].lower_bound(t) == times[x + 1].end()) res++; if (x != 0 && times[x - 1].lower_bound(t) == times[x - 1].end()) res++; } } cout << res << endl; }
|
`timescale 1ns / 1ps
module keyed_permutation_tb();
localparam UNIT_WIDTH = 1;//MAX is 16
localparam NUNITS = 16;
localparam INDEX_WIDTH = 4;
localparam KEY_WIDTH = 49;
reg i_clk;
reg [NUNITS*UNIT_WIDTH-1:0] i_dat;
reg [NUNITS*UNIT_WIDTH-1:0] i_dat_d1;
reg [NUNITS*UNIT_WIDTH-1:0] i_dat_d2;
reg [KEY_WIDTH-1:0] i_key;
reg [KEY_WIDTH-1:0] i_key_d1;
wire [NUNITS*UNIT_WIDTH-1:0] o_dat;
wire [NUNITS*UNIT_WIDTH-1:0] unpermuted;
always @(posedge i_clk) {i_key_d1,i_dat_d2,i_dat_d1} <= {i_key,i_dat_d1,i_dat};
keyed_permutation dut(
.i_clk(i_clk),
.i_dat(i_dat),
.i_key(i_key),
.i_inverse(1'b0),
.o_dat(o_dat)
);
keyed_permutation checker(
.i_clk(i_clk),
.i_dat(o_dat),
.i_key(i_key_d1),
.i_inverse(1'b1),
.o_dat(unpermuted)
);
integer i,j;
integer cnt;
wire error = cnt>3 ? unpermuted !== i_dat_d2 : 0;
initial begin
cnt=0;
for(i=0;i<10;i=i+1) begin
i_key = {$random,$random};
for(j=0;j<10;j=j+1) begin
i_dat = {$random,$random,$random,$random,$random,$random,$random,$random,$random};
@(negedge i_clk);
cnt=cnt+1;
end
end
@(negedge i_clk);
@(negedge i_clk);
@(negedge i_clk);
end
initial begin
i_clk = 0;
forever i_clk = #10 ~i_clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 501; int n, vis[maxn][maxn], a[maxn][maxn], x, y, s, cnt; char p[3000010]; int d[4][2] = {0, 1, 1, 0, -1, 0, 0, -1}; bool J(int x, int y, int i) { while (true) { x += d[i][0]; y += d[i][1]; if (!x || !y || x > n || y > n) return 0; if (vis[x][y]) return 0; if (a[x][y]) return 1; } } void dfs(int x, int y) { if (!a[x][y]) p[cnt++] = 1 , s++; vis[x][y] = 1; for (int i = 0; i < 4; i++) if (J(x, y, i)) { p[cnt++] = (!i ? R : i == 1 ? D : i == 2 ? U : L ); dfs(x + d[i][0], y + d[i][1]); p[cnt++] = (!i ? L : i == 1 ? U : i == 2 ? D : R ); } p[cnt++] = 2 , s--; } int main() { scanf( %d%d%d , &n, &x, &y); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]), s += a[i][j]; dfs(x, y); p[cnt++] = 0; if (s) printf( NO n ); else printf( YES n%s n , p); return 0; }
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#include <bits/stdc++.h> using namespace std; inline int two(int n) { return 1 << n; } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } int dr[] = {-1, 0, 0, 1}, dc[] = {0, -1, 1, 0}; const int md = 1000000007; int dcmp(double a, double b) { return fabs(a - b) <= 1e-9 ? 0 : (a > b) ? 1 : -1; } int arr[1009], tmp[1009] = {0}; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, r, sum = 0; cin >> n >> r; for (int i = 1; i <= n; ++i) { cin >> arr[i]; sum += arr[i]; if (arr[i] == 1) { for (int j = i - r + 1; j <= i + r - 1; ++j) { if (j >= 1 && j <= n) tmp[j]++; } } } int cnt = 0; for (int i = 1; i <= n; ++i) { if (tmp[i] < 1) return cout << -1, 0; } for (int i = 1; i <= n; ++i) { bool ok = false; if (arr[i] == 1) { for (int j = i - r + 1; j <= i + r - 1; ++j) { if (j >= 1 && j <= n) if (tmp[j] == 1) { ok = true; break; } } if (!ok) { cnt++; for (int j = i - r + 1; j <= i + r - 1; ++j) { if (j >= 1 && j <= n) tmp[j]--; } } } } cout << sum - cnt; }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T x = 0, f = 0; char c = getchar(); while (!isdigit(c)) f = c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 48, c = getchar(); return f ? -x : x; } namespace run { const long long N = 2e5 + 9; map<long long, long long> mp; long long n, a[N], ans; long long main() { n = read<long long>(); for (long long i = 1; i <= n; i++) a[i] = read<long long>(); mp[0] = 1; for (long long i = 1, sum = 0, las = 0; i <= n; i++) { sum += a[i]; las = max(las, mp[sum]); ans += i - las; mp[sum] = i + 1; } printf( %lld n , ans); return 0; } } // namespace run int main() { return run::main(); }
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#include <bits/stdc++.h> namespace mem { namespace stdval { using i32 = int; using i64 = long long int; using u32 = unsigned int; using u64 = unsigned long long int; using f32 = float; using f64 = double; using f96 = long double; using i128 = __int128_t; using u128 = __uint128_t; } // namespace stdval namespace utils { using std::accumulate; using std::cerr; using std::cin; using std::cout; using std::endl; using std::function; using std::get; using std::lower_bound; using std::make_pair; using std::make_tuple; using std::max_element; using std::min_element; using std::reverse; using std::shuffle; using std::sort; using std::swap; using std::tie; using std::unique; using std::upper_bound; } // namespace utils namespace random { const int LuckyNumber = 20040726; std::mt19937 rng(LuckyNumber ^ std::chrono::steady_clock::now().time_since_epoch().count()); std::mt19937_64 rng64( LuckyNumber ^ std::chrono::steady_clock::now().time_since_epoch().count()); template <class T> inline T rand(T l, T r) { return std::uniform_int_distribution<T>(l, r)(rng); } template <class T> inline T rand64(T l, T r) { return std::uniform_int_distribution<T>(l, r)(rng); } } // namespace random namespace modint { template <const int mod> struct Z { int x; inline Z() { x = 0; } inline Z(int t) { x = t; } inline void operator-=(Z a) { (x -= a.x) < 0 && (x += mod); } inline void operator+=(Z a) { (x += a.x) >= mod && (x -= mod); } inline void operator*=(Z a) { x = (long long)x * a.x % mod; } friend inline Z operator*(Z a, Z b) { return (long long)a.x * b.x % mod; } friend inline Z operator-(Z a, Z b) { return ((a.x -= b.x) < 0 && (a.x += mod)), a; } friend inline Z operator+(Z a, Z b) { return ((a.x += b.x) >= mod && (a.x -= mod)), a; } }; template <const int mod> inline Z<mod> finv(Z<mod> x) { if (x.x < 2) return x; return (mod - mod / x.x) * finv(mod % x.x); } template <const int mod> inline Z<mod> fpow(Z<mod> a, int b) { Z<mod> s = 1; for (; b; b >>= 1, a = a * a) if (b & 1) s = s * a; return s; } template <const int mod> inline void init_inverse(int n, Z<mod> *inv) { inv[0] = inv[1] = 1; for (int i = 2; i < n; i++) inv[i] = (mod - mod / i) * inv[mod % i]; } template <const int mod> inline void init_factorial(int n, Z<mod> *fac, Z<mod> *ifac) { fac[0] = 1, init_inverse(n, ifac); for (int i = 1; i < n; i++) fac[i] = fac[i - 1] * i, ifac[i] = ifac[i - 1] * ifac[i]; } } // namespace modint namespace io { template <const int mod> inline void read(modint::Z<mod> &x) { read(x.x); } template <const int mod> inline void print(modint::Z<mod> x) { print(x.x); } } // namespace io namespace math { using std::max; using std::min; template <class T> inline T abs(T x) { return x < 0 ? -x : x; } template <class T> inline T gcd(T n, T m) { return m ? gcd(m, n % m) : n; } template <class T> inline T lcm(T n, T m) { return n / gcd(n, m) * m; } template <const stdval::u64 p> struct FastDiv { stdval::u64 t, i; inline FastDiv() : t(stdval::u64(-1) / p), i(mul_inv(p)) {} inline bool divide(stdval::u64 n) { return n * i <= t; } inline bool divide(stdval::i64 n) { return stdval::u64(n < 0 ? -n : n) * i <= t; } inline stdval::u64 mul_inv(stdval::u64 n) { stdval::u64 x = n; for (int i = 0; i < 5; ++i) x *= 2 - n * x; return x; } }; template <const stdval::u64 b> struct FastMod { stdval::u64 m; inline FastMod() : m(stdval::u64((stdval::u128(1) << 64) / b)) {} inline stdval::u64 reduce(stdval::u64 a) { stdval::u64 q = (stdval::u64)((stdval::u128(m) * a) >> 64); stdval::u64 r = a - q * b; return r >= b ? r - b : r; } }; } // namespace math namespace container { using std::get; using std::make_pair; using std::make_tuple; using std::map; using std::pair; using std::priority_queue; using std::queue; using std::set; using std::stack; using std::tie; using std::tuple; using std::unordered_map; using std::unordered_set; template <class T> struct vector : std::vector<T> { using std::vector<T>::vector; vector() : std::vector<T>() {} vector(const std::vector<T> &plain) : std::vector<T>(plain) {} inline void sort() { std::sort(this->begin(), this->end()); } inline void concat(const vector &rhs) { this->insert(this->end(), rhs.begin(), rhs.end()); } inline bool includes(const T &x) const { return std::find(this->begin(), this->end(), x) != this->end(); } template <class Function> inline void forEach(Function func) { for (const auto &it : *this) func(it); } inline vector slice(int l, int r) const { if (l > r) return {}; if (r < this->size()) return vector(this->begin() + l, this->begin() + r); vector<int> rsp = (this->begin() + l, this->end()); return rsp.resize(r - l), rsp; } inline void from(const std::set<T> &src) { this->resize(src.size()); auto it = this->begin(); for (const T e : src) *it++ = e; } template <class R, class Function> inline vector<R> _map(Function func) const { vector<R> res(this->size()); for (size_t i = 0; i < this->size(); i++) res[i] = func(this->operator[](i)); return res; } template <class R> inline vector<R> map(R func(T)) const { return this->_map<R>(func); } template <class R> inline vector<R> map(const std::function<R(T)> &func) const { return this->_map<R>(func); } }; struct string : std::string { using std::string::string; string() : std::string( ) {} string(const std::string &plain) : std::string(plain) {} template <class T> inline string join(const vector<T> &vet) const; vector<string> split(const string &dim) const { if (this->empty()) return {}; char *src = new char[this->length() + 1]; strcpy(src, this->c_str()); char *tar = new char[dim.length() + 1]; strcpy(tar, dim.c_str()); vector<string> rsp; for (char *pos = strtok(src, tar); pos; pos = strtok(nullptr, tar)) rsp.push_back(string(pos)); delete[] src; delete[] tar; return rsp; } template <class... Args> static inline string format(const char *fm, Args... args) { int len = snprintf(nullptr, 0, fm, args...); char *buf = new char[len + 1]; snprintf(buf, len + 1, fm, args...); string str(buf); delete[] buf; return str; } template <class... Args> static inline string format(const string &fm, Args... args) { return format(fm.c_str(), args...); } }; inline string to_string(const float &x) { return std::to_string(x); } inline string to_string(const double &x) { return std::to_string(x); } inline string to_string(const long double &x) { return std::to_string(x); } inline string to_string(const int &x) { return std::to_string(x); } inline string to_string(const unsigned int &x) { return std::to_string(x); } inline string to_string(const long long int &x) { return std::to_string(x); } inline string to_string(const unsigned long long int &x) { return std::to_string(x); } inline string to_string(const string &s) { return s; } inline string to_string(const char *s) { return string(s); } inline string to_string(const std::string &s) { return string(s); } template <const int mod> inline string to_string(const mem::modint::Z<mod> &v) { return std::to_string(v.x); } template <class T> inline string to_string(const vector<T> &ctn) { return [ + string( , ).join(ctn) + ] ; } template <class T> inline string to_string(const set<T> &ctn) { string result = { ; bool flag = false; for (const auto &it : ctn) { if (flag) result += , ; flag = true; result += to_string(it); } return result + } ; } template <class T1, class T2> inline string to_string(const map<T1, T2> &ctn) { string result = { ; bool flag = false; for (const auto &it : ctn) { if (flag) result += , ; flag = true; result += to_string(it.first) + : + to_string(it.second); } return result + } ; } template <class T> inline string string::join(const vector<T> &vet) const { if (!vet.size()) return ; string res = to_string(vet[0]); for (size_t i = 1; i < vet.size(); i++) { res += *this; res += to_string(vet[i]); } return res; } inline string operator _s(const char *s) { return string(s); } inline string operator _s(const char *s, size_t len) { return string(s, len); } inline string operator _s(long double x) { return to_string(x); } inline string operator _s(unsigned long long int x) { return to_string(x); } } // namespace container namespace io { namespace fastio { const int BUFFER = 1 << 18; char ibuf[BUFFER], *iS, *iT; inline int getc() { if (iS == iT) { iT = (iS = ibuf) + fread(ibuf, 1, BUFFER, stdin); return iS == iT ? EOF : *iS++; } else { return *iS++; } } char obuf[BUFFER], *oS = obuf, *oT = oS + BUFFER - 1; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(int x) { *oS++ = x; if (oS == oT) flush(); } struct Flusher { ~Flusher() { flush(); } } flusher; } // namespace fastio using fastio::getc; using fastio::putc; template <class T> inline void readDigit(T &x) { x = getc(); while (!isdigit(x)) x = getc(); } inline int readDigit() { int x; readDigit(x); return x; } template <class T> inline void readAlpha(T &x) { x = getc(); while (!isalpha(x)) x = getc(); } inline int readAlpha() { int x; readAlpha(x); return x; } inline void read(int &x) { x = 0; bool f = 0; char c = getc(); while (!isdigit(c)) f ^= c == - , c = getc(); while (isdigit(c)) x = x * 10 + c - 0 , c = getc(); if (f) x = -x; } inline void read(unsigned int &x) { x = 0; bool f = 0; char c = getc(); while (!isdigit(c)) f ^= c == - , c = getc(); while (isdigit(c)) x = x * 10 + c - 0 , c = getc(); if (f) x = -x; } inline void read(long long int &x) { x = 0; bool f = 0; char c = getc(); while (!isdigit(c)) f ^= c == - , c = getc(); while (isdigit(c)) x = x * 10 + c - 0 , c = getc(); if (f) x = -x; } inline void read(unsigned long long int &x) { x = 0; bool f = 0; char c = getc(); while (!isdigit(c)) f ^= c == - , c = getc(); while (isdigit(c)) x = x * 10 + c - 0 , c = getc(); if (f) x = -x; } inline void read(char &x) { x = getc(); } inline void read(char *s) { char c = getc(); while (~c && !isspace(c)) *s++ = c, c = getc(); *s++ = 0 ; } inline void read(container::string &s) { char c = getc(); s = ; while (~c && !isspace(c)) s += c, c = getc(); } template <class T = int> inline T read() { T x; read(x); return x; } template <class T, class... Args> inline void read(T &x, Args &...args) { read(x), read(args...); } inline void print(int x) { if (x < 0) putc( - ), x = -x; if (x > 9) print(x / 10); putc( 0 + x % 10); } inline void print(unsigned int x) { if (x < 0) putc( - ), x = -x; if (x > 9) print(x / 10); putc( 0 + x % 10); } inline void print(long long int x) { if (x < 0) putc( - ), x = -x; if (x > 9) print(x / 10); putc( 0 + x % 10); } inline void print(unsigned long long int x) { if (x < 0) putc( - ), x = -x; if (x > 9) print(x / 10); putc( 0 + x % 10); } inline void print(char x) { putc(x); } inline void print(const char *s) { int len = strlen(s); for (int i = 0; i < len; i++) putc(s[i]); } inline void print(const container::string &s) { for (int i = 0; i < s.length(); i++) putc(s[i]); } template <class T, class... Args> inline void print(const T &x, Args... args) { print(x), print(args...); } template <class... Args> inline void println(Args... args) { print(args...), putc( n ); } template <class... Args> inline void printfm(const char *formatter, Args... arguments) { print(container::string().format(formatter, arguments...)); } template <class... Args> inline void printfm(const container::string &formatter, Args... arguments) { print(container::string().format(formatter, arguments...)); } } // namespace io namespace logger { enum ConsoleColor { NOPE = -1, BLACK, RED, GREEN, YELLOW, BLUE, PURPLE, DEEPBLUE }; template <const ConsoleColor color = NOPE, class... Args> inline void log(const char *formatter, Args... args) { if (~color) { fprintf(stderr, 033[%dm , 30 + color); fprintf(stderr, formatter, args...); fprintf(stderr, 033[0m ); } else { fprintf(stderr, formatter, args...); } } template <const ConsoleColor color = NOPE, class... Args> inline void logln(const char *formatter, Args... args) { if (~color) { fprintf(stderr, 033[%dm , 30 + color); fprintf(stderr, formatter, args...); fprintf(stderr, 033[0m n ); } else { fprintf(stderr, formatter, args...); fprintf(stderr, n ); } } template <class T> inline void logs(const T &x) { fprintf(stderr, container::to_string(x).c_str()); } template <class T, class... Args> inline void logs(const T &x, Args... args) { logs(x), logs(args...); } template <class... Args> inline void logsln(Args... args) { logs(args...); fprintf(stderr, n ); } } // namespace logger using namespace io; using namespace math; using namespace utils; using namespace modint; using namespace random; using namespace stdval; using namespace logger; using namespace container; } // namespace mem using namespace mem; const int N = 1e6 + 10; const long long inf = 1e18; int k, q, f[6], stk[N << 1]; long long dp[6][N]; inline int weight(int k) { return k % 3 == 0 ? k / 3 : 0; } inline long long calc(int s) { if ((s + 8) / 9 > k) { return -inf; } int t = s / 9; s -= t * 9; if (t + 2 > k) { return t * 3 + weight(s); } else { return t * 3 + s / 3; } } inline vector<long long> transform(vector<long long> dp, int val) { vector<vector<long long>> g(3, vector<long long>(dp.size(), -inf)); for (int r = 0; r < 9; r++) for (int cas = 0; cas < 3; cas++) { int u = 1, v = 0; for (int j = r, l = 0; j < dp.size(); j += 9, l++) { while (u <= v && dp[j] - 3ll * l * val > dp[stk[v] * 9 + r] - 3ll * stk[v] * val) --v; stk[++v] = l; while (u <= v && k - cas < l - stk[u]) ++u; if (u <= v) { g[cas][j] = 3ll * l * val + dp[stk[u] * 9 + r] - 3ll * val * stk[u]; } } } for (int i = 0; i < dp.size(); i++) { dp[i] = max(dp[i], g[0][i]); for (int j = i; j >= max<int>(0, i - 9); j--) { dp[i] = max(dp[i], g[1][j] + (long long)weight(i - j) * val); } for (int j = i; j >= max<int>(0, i - 9); j--) { dp[i] = max(dp[i], g[2][j] + (long long)(i - j) / 3 * val); } } return dp; } int32_t main() { read(k); for (int i = 0; i < 6; i++) { read(f[i]); } for (int i = 0; i < 1000000; i++) { long long t = calc(i); if (t < 0) { dp[0][i] = -inf; } else { dp[0][i] = (long long)t * f[0]; } } int w = 10; for (int k = 1; k < 6; k++, w *= 10) { for (int r = 0; r < w; r++) { vector<long long> src; for (int i = r; i < 1000000; i += w) { src.push_back(dp[k - 1][i]); } vector<long long> rsp = transform(src, f[k]); for (int i = r, j = 0; i < 1000000; i += w, j++) { dp[k][i] = rsp[j]; } } } read(q); while (q-- > 0) { int x; read(x); print(dp[5][x], n ); } }
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#include <bits/stdc++.h> using namespace std; int main() { int k, n1, n2, n3, t1, t2, t3; cin >> k >> n1 >> n2 >> n3 >> t1 >> t2 >> t3; multiset<int> A, B, C; for (int i = 0; i < n1; ++i) A.insert(0); for (int i = 0; i < n2; ++i) B.insert(0); for (int i = 0; i < n3; ++i) C.insert(0); for (int i = 0; i < k; ++i) { int a = *A.begin(); int b = *B.begin(); int c = *C.begin(); int t = max(a, max(b - t1, c - t1 - t2)); A.erase(A.begin()); A.insert(t + t1); B.erase(B.begin()); B.insert(t + t1 + t2); C.erase(C.begin()); C.insert(t + t1 + t2 + t3); } int ret = *max_element(C.begin(), C.end()); cout << ret; return 0; }
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// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: async_fifo_256x72_to_36.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module async_fifo_256x72_to_36 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull);
input aclr;
input [71:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "36"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "36"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_256x72_to_36_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
/* verilator lint_off COMBDLY */
module arithbox (arithop,calc_sz,ci,co,af,ai,sa,sb,opa,opb,resa,cmp);
input [3:0] arithop;
input [3:0] calc_sz;
input [31:0] opa,opb;
output reg [31:0] resa;
input ci,ai;
output reg co,af,sa,sb,cmp;
wire [4:0] af2,af3,af4,af5;
assign af2 = opa[3:0]+opb[3:0];
assign af3 = opa[3:0]+opb[3:0]+ci;
assign af4 = opa[3:0]-opb[3:0];
assign af5 = opa[3:0]-opb[3:0]-ci;
always @(*)
case (arithop)
4'b0000 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0]; sa<=opa[31]; sb<=opb[31]; af <= af2[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0]; sa<=opa[15]; sb<=opb[15]; af <= af2[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0]; sa<=opa[ 7]; sb<=opb[ 7]; af <= af2[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // add
4'b0001 : begin resa[31:0] <= opa[31:0] | opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <=0; end // or
4'b0010 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0] + ci; sa<=opa[31]; sb<=opb[31]; af <= af3[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0] + ci; sa<=opa[15]; sb<=opb[15]; af <= af3[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0] + ci; sa<=opa[ 7]; sb<=opb[ 7]; af <= af3[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // adc
4'b0011 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0] - ci; sa<=opa[31]; sb<=~opb[31];af <= af5[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0] - ci; sa<=opa[15]; sb<=~opb[15];af <= af5[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0] - ci; sa<=opa[ 7]; sb<=~opb[ 7];af <= af5[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // sbc & cmp
4'b0100 : begin resa[31:0] <= opa[31:0] & opb[31:0]; sa<=1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <= 0; end // and
4'b0111 : begin
if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=1; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=1; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=1; resa[31: 8] <= opa[31: 8]; end // sub
end
4'b0101 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=0; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=0; resa[31: 8] <= opa[31: 8]; end // sub
4'b0110 : begin resa[31:0] <= opa[31:0] ^ opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai; co <= 0; cmp <=0; end // xor
default : begin resa[31:0] <= opa[31:0] ; sa <= 0 ; sb<= 0 ; af <= ai; co <= ci; cmp <=1; end
endcase
endmodule
|
module WordOpcodeBufferTest;
`include "Framework.v"
reg reset;
reg clk;
always #10 clk = ~clk;
reg [31:0] addrA;
wire [31:0] addrB;
reg writeEnable = 0;
reg [31:0] dataIn;
reg requestA;
wire requestB;
wire [31:0] outA;
wire [31:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu #(.BUS_WIDTH(32))mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
reg [31:0] ip;
wire busy;
wire [31:0] opcode;
reg startLoading;
WordOpcodeBuffer ob(clk, reset, ip, startLoading, outB, busyB, busy, opcode, addrB, requestB);
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu,ob);
reset = 1;
clk = 0;
#20 reset = 0;
ip = 0;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
#10 startLoading = 0;
ip = 4;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
ip = 8;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V
|
`timescale 1 ns / 10 ps
module dpram (clock,
address_a, byteena_a, wrdata_a, wren_a, rddata_a,
address_b, byteena_b, wrdata_b, wren_b, rddata_b);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "dummy"; // This is ignored right now
input clock;
input [ADDR_WIDTH-1:0] address_a;
input [DATA_WIDTH/8-1:0] byteena_a;
input [DATA_WIDTH-1:0] wrdata_a;
input wren_a;
output [DATA_WIDTH-1:0] rddata_a;
input [ADDR_WIDTH-1:0] address_b;
input [DATA_WIDTH-1:0] wrdata_b;
input [DATA_WIDTH/8-1:0] byteena_b;
input wren_b;
output [DATA_WIDTH-1:0] rddata_b;
dpram_simple s0(clock,
address_a, wrdata_a[ 7: 0], byteena_a[0] & wren_a, rddata_a[ 7: 0],
address_b, wrdata_b[ 7: 0], byteena_b[0] & wren_b, rddata_b[ 7: 0]);
defparam s0.DATA_WIDTH = DATA_WIDTH / 4,
s0.DATA_WIDTH = DATA_WIDTH;
dpram_simple s1(clock,
address_a, wrdata_a[15: 8], byteena_a[1] & wren_a, rddata_a[15: 8],
address_b, wrdata_b[15: 8], byteena_b[1] & wren_b, rddata_b[15: 8]);
defparam s1.DATA_WIDTH = DATA_WIDTH / 4,
s1.DATA_WIDTH = DATA_WIDTH;
dpram_simple s2(clock,
address_a, wrdata_a[23:16], byteena_a[2] & wren_a, rddata_a[23:16],
address_b, wrdata_b[23:16], byteena_b[2] & wren_b, rddata_b[23:16]);
defparam s2.DATA_WIDTH = DATA_WIDTH / 4,
s2.DATA_WIDTH = DATA_WIDTH;
dpram_simple s3(clock,
address_a, wrdata_a[31:24], byteena_a[3] & wren_a, rddata_a[31:24],
address_b, wrdata_b[31:24], byteena_b[3] & wren_b, rddata_b[31:24]);
defparam s3.DATA_WIDTH = DATA_WIDTH / 4,
s3.DATA_WIDTH = DATA_WIDTH;
endmodule
|
`include "../../network_params.h"
module np_matrix_mult_ctrl(
input clock,
input reset,
input start,
output reg [`FM_ADDR_BITWIDTH:0] addr,
output reg [`RAM_SELECT_BITWIDTH:0] ram_select,
output reg mult_en,
output reg product_rdy
);
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
addr <= `FM_ADDR_WIDTH'd0;
ram_select <= `RAM_SELECT_WIDTH'd0;
end else begin
if (start) begin
addr <= `FM_ADDR_WIDTH'd0;
ram_select <= `RAM_SELECT_WIDTH'd0;
end else if( addr == `ADDR_MAX - 1) begin
ram_select <= ram_select + `RAM_SELECT_WIDTH'd1;
addr <= `FM_ADDR_WIDTH'd0;
end else begin
addr <= addr + `FM_ADDR_WIDTH'd1;
ram_select <= ram_select;
end
end // reset
end // always
// ready signal logic
always@(posedge clock or negedge reset) begin
if(reset == 1'b0) begin
product_rdy <= 1'b0;
end else begin
if(ram_select == `NUM_KERNELS - 1 & addr == `ADDR_MAX - 2 & mult_en) begin
product_rdy <= 1'b1;
end else begin
product_rdy <= 1'b0;
end // select max
end // reset
end // always
// enable signal logic multipler module
always@(posedge clock or negedge reset) begin
if (reset == 1'b0)
mult_en <= 1'b0;
else if (start)
mult_en <= 1'b1;
else if (ram_select == `NUM_KERNELS -1 & addr == `ADDR_MAX - 1)
mult_en <= 1'b0;
else
mult_en <= mult_en;
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5 + 5; int lover[maxN], unlover[maxN]; int speak[maxN]; int N, M; bool iscrime[maxN]; int totnocommit, totcommit; int main() { scanf( %d%d , &N, &M); for (int i = (1), _ = (N); i <= _; ++i) { scanf( %d , &speak[i]); if (speak[i] < 0) { totnocommit++; unlover[-speak[i]]++; } else { totcommit++; lover[speak[i]]++; } } int totcrime = 0; for (int i = (1), _ = (N); i <= _; ++i) { int toldtruth = lover[i] + totnocommit - unlover[i]; if (toldtruth == M) { ++totcrime; iscrime[i] = true; } } for (int i = (1), _ = (N); i <= _; ++i) if (speak[i] < 0) { int who = abs(speak[i]); if (iscrime[who] == true) if (totcrime == 1) puts( Lie ); else puts( Not defined ); else puts( Truth ); } else { int who = abs(speak[i]); if (iscrime[who] == true) if (totcrime == 1) puts( Truth ); else puts( Not defined ); else puts( Lie ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0; cin >> n; n++; for (int i = 1; i < n - 2; i++) { for (int j = i; j < n - 1; j++) { int k = (int)(i ^ j); if (k < n && k > j) { if (!(i ^ j ^ k)) { double p = (i + j + k) / 2; double s = sqrt(p * (p - i) * (p - j) * (p - k)); if (s > 0) { sum++; } } } } } cout << sum; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconstant_0_1/RAT_xlconstant_0_1_sim_netlist.v
// Design : RAT_xlconstant_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module RAT_xlconstant_0_1
(dout);
output [1:0]dout;
wire \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; multiset<long long int> s; map<string, int> mp; while (t--) { char ch; long long int x; cin >> ch >> x; string str(18, 0 ); string temp = to_string(x); int j = 17; for (int i = ((int)(temp).size()) - 1; i >= 0; i--) { if ((temp[i] - 0 ) % 2 != 0) { str[j] = 1 ; } j--; } if (ch == + ) { mp[str]++; } else if (ch == - ) { mp[str]--; } else { cout << mp[str] << n ; } } }
|
// -*- Mode: Verilog -*-
// Filename : wb_daq_data_aggregation.v
// Description : WB Data Acquisition Aggregation
// Author : Philip Tracton
// Created On : Wed Dec 16 13:02:29 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 16 13:02:29 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_daq_data_aggregation (/*AUTOARG*/
// Outputs
data_out, fifo_push,
// Inputs
wb_clk, wb_rst, data_ready, data_width, adc_data_in
) ;
parameter dw = 32;
parameter adc_dw = 8;
input wb_clk;
input wb_rst;
input data_ready;
input [1:0] data_width;
input [adc_dw-1:0] adc_data_in;
output reg [dw-1:0] data_out;
output reg fifo_push;
reg [1:0] byte_location;
always @(posedge wb_clk)
if (wb_rst) begin
data_out <= 0;
byte_location <= 0;
fifo_push <= 0;
end else begin
if (data_ready) begin
if (data_width == 0) begin
// 8 bits from ADC to 32 bits to FIFO
case (byte_location)
0: data_out[07:00] <= adc_data_in;
1: data_out[15:08] <= adc_data_in;
2: data_out[23:16] <= adc_data_in;
3: data_out[31:24] <= adc_data_in;
default: data_out <= 0;
endcase // case (byte_location)
byte_location <= byte_location + 1;
if (byte_location == 3) begin
fifo_push <= 1;
byte_location <= 0;
end
end else if (data_width == 1) begin // if (data_width == 0)
// 16 bits from ADC to 32 bits to FIFO
case (byte_location)
0: data_out[15:00] <= adc_data_in;
1: data_out[31:16] <= adc_data_in;
default: data_out <= 0;
endcase // case (byte_location)
byte_location <= byte_location + 1;
if (byte_location == 1) begin
fifo_push <= 1 & !fifo_push;
byte_location <= 0;
end
end else if (data_width == 2) begin // if (data_width == 1)
data_out <= adc_data_in;
fifo_push <= 1;
end
end else begin
fifo_push <= 1'b0;
end // else: !if(aggregate_data)
end // else: !if(wb_rst)
endmodule // wb_daq_data_aggregation
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const double PI = acos(-1.0); const double epsilon = PI / 180.0; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int N = 3e3 + 10, M = 1e6 + 10; int n; int a[N]; long long num[N][N], f[N][N]; int main() { int _; cin >> _; while (_--) { memset(num, 0, sizeof num); memset(f, 0, sizeof f); cin >> n; for (int i = 1; i < n + 1; i++) cin >> a[i]; for (int i = 1; i < n + 1; i++) { for (int j = n + 1 - 1; j >= i + 1; j--) { num[i][j] = num[i][j + 1]; if (a[i] == a[j]) num[i][j]++; } } for (int k = 1; k < n + 1; k++) { for (int i = 1; i < k + 1; i++) { f[i][k] = f[i - 1][k] + num[i][k + 1]; } } long long ans = 0; for (int i = 1; i < n + 1; i++) { for (int j = i + 1; j < n + 1; j++) { if (a[i] != a[j]) continue; ans += (f[j - 1][j] - f[i][j]); } } cout << ans << n ; } return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*
* NAME
* ----
*
* mem_ctl - memory control
*
*
* DESCRIPTION
* -----------
*
* Module for interfacing an Alliance AS6C1008 128x8 RAM chip
* on to an 8-bit data bus and a 7-bit address bus.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <>
*
*/
module mem_ctl(
input read_n,
write_n,
ce_n,
input [6:0] address_bus,
inout [7:0] data_bus,
inout [7:0] mem_data,
output [16:0] mem_address,
output wire ceh_n,
ce2,
we_n,
oe_n);
// tie unused address bits low
assign mem_address[16:7] = 0;
assign mem_address[6:0] = address_bus;
// if read enabled, drive current data, otherwise go hi Z
// for READ
assign data_bus = (~(ce_n | read_n | ~write_n)) ? mem_data : 8'bz;
// The following line is used to test read cycle, see mem_ctl-test.v
// Comment out the one above when using it.
//assign data_bus = (~(ce_n | read_n | ~write_n)) ? 8'hee : 8'bz;
// for WRITE
assign mem_data = (~(ce_n | write_n | ~read_n)) ? data_bus : 8'bz;
// No "timing" is required for the control lines.
// This just follows the truth table given on page 3 of
// the Alliance RAM data sheet.
assign ceh_n = 1'b0;
assign ce2 = 1'b1;
// for READ
assign oe_n = (~(ce_n | read_n)) ? 1'b0 : 1'b1;
// for WRITE
assign we_n = (~(ce_n | write_n | ~read_n)) ? 1'b0 : 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, cnt; int A[10]; long long FE(long long n, long long m) { if (!m) return 1; long long t = FE(n, m >> 1); t = (t * t) % (1000000007); if (m & 1) t = (t * n) % (1000000007); return t % (1000000007); } bool ctrl() { bool H[10] = {0}; int s = k - 1; if (!s) return true; for (int i = 2; i <= k; i++) { if (A[i] == 1) { H[i] = 1; s--; if (!s) return true; } } bool flag; while (1) { flag = 0; for (int i = 2; i <= k; i++) { if (!H[i] && H[A[i]]) { H[i] = 1; s--; flag = 1; if (!s) return true; } } if (!flag) return false; } } void solve(int x) { if (x == k + 1) { if (ctrl()) { cnt++; cnt %= (1000000007); } return; } for (int i = 1; i <= k; i++) { A[x] = i; solve(x + 1); } } int main() { scanf( %lld %lld , &n, &k); solve(2); long long res = 1; if (n - k > 0) res *= FE(n - k, n - k); cout << ((cnt * k) % (1000000007) * res) % (1000000007) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[100020], b[100020]; int main() { int m, n; scanf( %d%d , &m, &n); long long sum1 = 0, sum2 = 0, s1 = 0, s2 = 0, Max1 = 0, Max2 = 0; for (int i = 1; i <= m; i++) { scanf( %I64d , &a[i]); sum1 += a[i]; if (a[i] > Max1) { Max1 = a[i]; s1 = i; } } for (int i = 1; i <= n; i++) { scanf( %I64d , &b[i]); sum2 += b[i]; if (b[i] > Max2) { Max2 = b[i]; s2 = i; } } long long ans1 = sum1 * n, ans2 = sum2 * m; for (int i = 1; i <= m; i++) { if (i != s1 && a[i] < sum2) ans2 = ans2 - sum2 + a[i]; } for (int i = 1; i <= n; i++) { if (i != s2 && b[i] < sum1) ans1 = ans1 - sum1 + b[i]; } if (ans1 > ans2) printf( %I64d n , ans2); else printf( %I64d n , ans1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } int last = 0; int ans = 0; string s = ; int l = 0, r = n - 1; while (1) { int k = INT_MAX; if (arr[l] > last) { k = arr[l]; } if (arr[r] > last) { k = min(k, arr[r]); } if (k != arr[l] && k != arr[r]) { break; } ans++; last = k; if (k == arr[r] && k == arr[l]) { int c1 = 0, c2 = 0; for (int i = l + 1; i < r; i++) { if (arr[i] > arr[i - 1]) { c1++; } else { break; } } c1++; c2++; for (int i = r - 1; i > l; i--) { if (arr[i] > arr[i + 1]) { c2++; } else { break; } } ans += max(c1, c2); cout << ans - 1 << endl; cout << s; if (c1 >= c2) { for (int i = 0; i < c1; i++) { cout << L ; } } else { for (int i = 0; i < c2; i++) { cout << R ; } } return 0; } else if (k == arr[r]) { r--; s += R ; } else { l++; s += L ; } if (l > r) { break; } } cout << ans << endl; cout << s; }
|
#include <bits/stdc++.h> using namespace std; bool checkThree(char cc, char lc, char nc) { return (cc != lc && cc != nc); } int main() { int t; cin >> t; while (t--) { string s, t; cin >> s >> t; for (int i = 0; i < s.length(); i++) { int x = t.find(s[i]); if (x < t.length()) { cout << YES << endl; goto label; } } cout << NO << endl; label:; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 1; vector<int> s[N], e[N]; int n, m, l[N], r[N], x[N], res[N]; bool vis[N]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { scanf( %d%d%d , &l[i], &r[i], &x[i]); s[l[i]].push_back(i); e[r[i]].push_back(i); } priority_queue<int> qu; vector<int> w; for (int i = 1; i <= n; ++i) { for (size_t j = 0; j < s[i].size(); ++j) qu.push(-s[i][j]); bool can = false; while (!qu.empty()) { int v = -qu.top(); if (!vis[v]) { can = true; break; } qu.pop(); } if (!can) continue; w.clear(); while (!qu.empty()) { int v = -qu.top(); if (x[v] == i || i < l[v] || i > r[v]) { qu.pop(); w.push_back(v); continue; } res[i] = x[v]; break; } for (size_t j = 0; j < w.size(); ++j) qu.push(-w[j]); for (size_t j = 0; j < e[i].size(); ++j) vis[e[i][j]] = true; } for (int i = 1; i <= n; ++i) printf( %s%d , i > 1 ? : , res[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; long long int n, k, mx, sum, a[N]; int main() { cin >> n >> k; sum++; for (int i = 0; i < n; i++) { cin >> a[i]; if (i) { if (a[i] != a[i - 1]) { sum++; mx = max(mx, sum); } else { sum = 1; } } } mx = max(sum, mx); cout << mx; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long w, m; cin >> w >> m; vector<int> a; long long z = m; while (z) { a.push_back(z % w); z /= w; } a.push_back(0); int flag = 1; for (int i = 0; i < a.size(); i++) { if (a[i] == w || a[i] == w - 1) { a[i] -= w; a[i + 1] += 1; } } for (int i = 0; i < a.size(); i++) if (a[i] != 0 && a[i] != 1 && a[i] != -1) { flag = 0; break; } if (flag) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 11; const int MAXN = 1e5 + 5; const int LG = 20; const int INF = 1e9; using ll = long long int; using ull = unsigned long long int; const ll MOD2 = 998244353; const ll MOD1 = 1e9 + 7LL; vector<int> g[MAXN], cg[MAXN]; vector<int> cpar(MAXN); vector<int> ans(MAXN); int n, m; struct CDMP { vector<bool> dead; vector<int> par; int oneCentroid(int root) { static vector<int> sub(MAXN); function<void(int, int)> dfs = [&](int u, int p) { sub[u] = 1; for (int v : g[u]) { if (v == p || dead[v]) continue; dfs(v, u); sub[u] += sub[v]; } }; dfs(root, -1); int N = sub[root]; function<int(int, int)> findcenter = [&](int u, int p) { for (int v : g[u]) { if (v == p || dead[v]) continue; if (2 * sub[v] > N) return findcenter(v, u); } return u; }; return findcenter(root, -1); } void traverse(int u, int p, int d = 0) { par[u] = p; for (int v : cg[u]) { if (v != p) { traverse(v, u, d + 1); } } } vector<int> &decomposeTree() { par = vector<int>(MAXN, -1); dead = vector<bool>(MAXN, false); function<int(int)> rec = [&](int u) { int c = oneCentroid(u); dead[c] = true; for (int v : g[c]) if (!dead[v]) { int cv = rec(v); cg[c].push_back(cv); cg[cv].push_back(c); } return c; }; int r = rec(1); traverse(r, -1); return par; } } cdmp; struct computeLCA { int level[MAXN]; int par[MAXN][LG]; int findlca(int u, int v) { if (level[u] < level[v]) swap(u, v); int lg = 0; for (; (1 << lg) <= level[u]; ++lg) ; --lg; for (int i = lg; i >= 0; --i) if (level[u] - (1 << i) >= level[v]) u = par[u][i]; if (u == v) return u; for (int i = lg; i >= 0; --i) if (par[u][i] != -1 && par[u][i] != par[v][i]) u = par[u][i], v = par[v][i]; return par[u][0]; } int dist(int u, int v) { return level[u] + level[v] - 2 * level[findlca(u, v)]; } void dfs(int u, int p) { level[u] = 1 + level[p]; par[u][0] = p; for (int v : g[u]) if (v != p) { dfs(v, u); } } void build() { level[1] = 0; for (int i = 0; i <= n; ++i) for (int j = 0; j < LG; ++j) par[i][j] = -1; dfs(1, 1); for (int l = 1; l < LG; ++l) for (int i = 1; i <= n; ++i) if (par[i][l - 1] != -1) { par[i][l] = par[par[i][l - 1]][l - 1]; } } } lca; void update(int x) { int node = x; while (node > 0) { ans[node] = min(ans[node], lca.dist(node, x)); node = cpar[node]; } } int query(int x) { int node = x; int ret = INF; while (node > 0) { ret = min(ret, lca.dist(node, x) + ans[node]); node = cpar[node]; } return ret; } int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d , &u); scanf( %d , &v); g[u].push_back(v); g[v].push_back(u); } for (int i = 0; i <= n; ++i) ans[i] = INF; cpar = cdmp.decomposeTree(); lca.build(); update(1); while (m--) { int t, x; scanf( %d , &t); scanf( %d , &x); if (t == 1) { update(x); } else { printf( %d , query(x)); printf( n ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_1_V
`define SKY130_FD_SC_LP__INVKAPWR_1_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog wrapper for invkapwr with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_1 (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invkapwr_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 1) { cout << -1; } else cout << n << << n + 1 << << n * (n + 1); }
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> ways[400], a[400], num[400]; vector<int> ans; struct edge { int a, b; }; vector<edge> gr; bool dfs(int v, int f, int pr) { if (v == f) return true; for (int i = 0; i < a[v].size(); i++) { if (a[v][i] != pr) if (dfs(a[v][i], f, v)) return true; } return false; } void findway(int v, int f, int j) { if (v == f) { ways[j].push_back(v); return; } for (int i = 0; i < a[v].size(); i++) { if (dfs(a[v][i], f, v)) { ways[j].push_back(v); findway(a[v][i], f, j); return; } } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int z, l; cin >> z >> l; a[l].push_back(z); a[z].push_back(l); num[l].push_back(i + 1); num[z].push_back(i + 1); } int num = 0; int k; while (cin >> k) { findway(1, k, num); num++; } for (int i = 0; i < ways[0].size(); i++) { ans.push_back(ways[0][i]); } for (int i = 1; i < num; i++) { int j = 0; while (ways[i - 1][j] == ways[i][j]) j++; j--; for (int z = ways[i - 1].size() - 2; z >= j; z--) { ans.push_back(ways[i - 1][z]); } for (int z = j + 1; z < ways[i].size(); z++) { ans.push_back(ways[i][z]); } } for (int i = ways[num - 1].size() - 2; i >= 0; i--) { ans.push_back(ways[num - 1][i]); } if (ans.size() != 2 * n - 1) cout << -1; else { for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; #define int unsigned long long const int N = 100010; int n, a[N]; signed main(void) { ios::sync_with_stdio(false); map <int, int> mp; int T; cin >> T; while(T--) { mp.clear(); int res = 0; int n; cin >> n; for(int i = 1; i <= n; i++) { cin >> a[i]; res += mp[a[i]] * (n - i + 1); mp[a[i]] += i; } cout << res << endl; } return 0; } /* ———————————————— 版权声明：本文为CSDN博主「zhbbbb！」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。 原文链接：https://blog.csdn.net/zhbbbbbb/article/details/117330722*/
|
#include <bits/stdc++.h> using namespace std; long long n, m, l, r, p, span, t, lwr, upr; long pr[200000]; vector<long> vec[200000]; long calc[200000]; long long res, nmoves[200000]; long long check[200000]; long long temp; long long answ; long long gcd(long long a, long long b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } long long solve1(long long x, long long lim) { long long res = 0; for (int mask = 0; mask < (1 << (vec[x].size())); mask++) { temp = 1; for (int j = 0; j < vec[x].size(); j++) if (mask & (1 << j)) temp *= vec[x][j]; if (calc[mask] % 2) res -= lim / temp; else res += lim / temp; } return res; } long long solve(long long x, long long lim) { long long res = 0; long long ts = 0; long long q, qsum; for (int mask = 0; mask < (1 << (vec[x].size())); mask++) { temp = 1; for (int j = 0; j < vec[x].size(); j++) if (mask & (1 << j)) temp *= vec[x][j]; q = lim / temp; qsum = q * (q + 1) / 2; qsum *= temp; if (calc[mask] % 2) res -= qsum; else res += qsum; } return res; } long long gett(long long g, long long x, long long lim) { if (lim <= 0) return 0; long long tsum = (g + 1) * solve1(x, lim); tsum -= solve(x, lim); return tsum; } int main() { ios_base::sync_with_stdio(0); pr[1] = 1; for (int i = 2; i <= 100000; i++) if (pr[i] == 0) for (int j = i * 2; j <= 100000; j += i) { pr[j] = 1; vec[j].push_back(i); } for (int i = 2; i <= 100000; i++) if (pr[i] == 0) vec[i].push_back(i); calc[0] = 0; for (int i = 1; i <= (1 << 15); i++) { t = i; for (int j = 0; j < 15; j++) if (t & (1 << j)) ++calc[i]; } long long a, b; cin >> n >> m; cin >> l >> r >> p; l *= l; r *= r; for (long long span = 2; span <= 100000 && span <= n; span++) { if (span * span > r) continue; t = l - span * span; if (t <= 0) lwr = 0; else lwr = sqrt(t - 0.5) + 1; t = r - span * span; upr = sqrt(t + 0.5); if (upr >= span) upr = span - 1; if (upr > m) upr = m; if (upr < lwr) continue; res = (gett(m, span, upr) - gett(m, span, lwr - 1)) * (n - span + 1) * 2; answ = answ + res; answ %= p; } swap(n, m); for (long long span = 2; span <= 100000 && span <= n; span++) { if (span * span > r) continue; t = l - span * span; if (t <= 0) lwr = 0; else lwr = sqrt(t - 0.5) + 1; t = r - span * span; upr = sqrt(t + 0.5); if (upr >= span) upr = span - 1; if (upr > m) upr = m; if (upr < lwr) continue; res = (gett(m, span, upr) - gett(m, span, lwr - 1)) * (n - span + 1) * 2; answ = answ + res; answ %= p; } if (1 >= l && 1 <= r) answ += n * (m + 1), answ += m * (n + 1); if (2 >= l && 2 <= r) answ += 2 * n * m; cout << answ % p << endl; cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[50][50], n, m; bool can(int k) { int total = 0; for (int i = 0; i < m; i++) if (a[k][i] != i + 1) total++; if (total <= 2) return 1; return 0; } bool ok() { for (int i = 1; i <= n; i++) if (!can(i)) return 0; return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); if (ok()) { printf( YES n ); return 0; } for (int i = 0; i < m - 1; i++) for (int j = i + 1; j < m; j++) { for (int k = 1; k <= n; k++) swap(a[k][i], a[k][j]); if (ok()) { printf( YES n ); return 0; } for (int k = 1; k <= n; k++) swap(a[k][i], a[k][j]); } printf( NO n ); return 0; }
|
`timescale 1 ns / 1 ps
module PWM_Analyzer_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire pwm,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
PWM_Analyzer_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) PWM_Analyzer_v1_0_S00_AXI_inst (
.pwm(pwm),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
//`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="fib,hls_ip_2016_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z045ffg900-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.800000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=161,HLS_SYN_LUT=266}" *)
module fib (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
n,
ap_return
);
parameter ap_ST_fsm_state1 = 2'b1;
parameter ap_ST_fsm_state2 = 2'b10;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv64_1 = 64'b1;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv31_0 = 31'b0000000000000000000000000000000;
parameter ap_const_lv31_1 = 31'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] n;
output [63:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire [0:0] ap_CS_fsm_state1;
wire [30:0] i_1_fu_68_p2;
wire [0:0] ap_CS_fsm_state2;
wire [63:0] next_fu_74_p2;
wire [0:0] tmp_fu_63_p2;
reg [63:0] curr_reg_24;
reg [63:0] prev_reg_36;
reg [30:0] i_reg_48;
wire [31:0] i_cast_fu_59_p1;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'b1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state2) & ~(tmp_fu_63_p2 == 1'b0))) begin
curr_reg_24 <= next_fu_74_p2;
end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0))) begin
curr_reg_24 <= ap_const_lv64_1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state2) & ~(tmp_fu_63_p2 == 1'b0))) begin
i_reg_48 <= i_1_fu_68_p2;
end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0))) begin
i_reg_48 <= ap_const_lv31_0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state2) & ~(tmp_fu_63_p2 == 1'b0))) begin
prev_reg_36 <= curr_reg_24;
end else if (((ap_CS_fsm_state1 == 1'b1) & ~(ap_start == 1'b0))) begin
prev_reg_36 <= ap_const_lv64_0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_63_p2 == 1'b0))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_63_p2 == 1'b0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (~(ap_start == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if ((tmp_fu_63_p2 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];
assign ap_CS_fsm_state2 = ap_CS_fsm[ap_const_lv32_1];
assign ap_return = prev_reg_36;
assign i_1_fu_68_p2 = (i_reg_48 + ap_const_lv31_1);
assign i_cast_fu_59_p1 = i_reg_48;
assign next_fu_74_p2 = (prev_reg_36 + curr_reg_24);
assign tmp_fu_63_p2 = (($signed(i_cast_fu_59_p1) < $signed(n)) ? 1'b1 : 1'b0);
endmodule //fib
|
/* opa: Open Processor Architecture
* Copyright (C) 2014-2016 Wesley W. Terpstra
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* To apply the GPL to my VHDL, please follow these definitions:
* Program - The entire collection of VHDL in this project and any
* netlist or floorplan derived from it.
* System Library - Any macro that translates directly to hardware
* e.g. registers, IO pins, or memory blocks
*
* My intent is that if you include OPA into your project, all of the HDL
* and other design files that go into the same physical chip must also
* be released under the GPL. If this does not cover your usage, then you
* must consult me directly to receive the code under a different license.
*/
`timescale 1ns/10ps
module pll(
input wire refclk,
input wire rst,
output wire outclk_0,
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int V[200010]; char vowel[] = aeiouAEIOU ; int v(int a, int k) { if (k == 0) return 0; int x = V[a + k - 1]; if (a > 0) x -= V[a - 1]; return x; } int f(int a, int k) { return 2 * k - 3 * v(a, k); } int g(int k) { return f(0, k); } bool Good(int a, int k) { return f(a, k) >= 0; } bool is_vowel(char c) { for (int i = 0; i < 10; i++) { if (vowel[i] == c) return true; } return false; } bool sf(const int& a, const int& b) { if (g(a) < g(b)) return true; if (g(a) > g(b)) return false; return a < b; } int Q[200010]; vector<int> P; int R[200010]; int my_bin_search(int s, string S) { int a = 0; int b = P.size() - 1; while (a <= b) { int k = (a + b) / 2; if (P[k] == s) return k; else if (sf(P[k], s)) a = k + 1; else b = k - 1; } throw element not found ; } void create_data(string S) { int N = S.length(); for (int a = 0; a <= N; a++) { P.push_back(a); } sort(P.begin(), P.end(), sf); for (int x = 0; x < P.size(); x++) { R[P[x]] = x; } Q[0] = P[0]; for (unsigned int x = 1; x < P.size(); x++) { Q[x] = min(Q[x - 1], P[x]); } } int main() { string S; cin >> S; int N = S.length(); V[0] = 0; for (unsigned int i = 0; i < S.length(); i++) { if (i > 0) V[i] = V[i - 1]; if (is_vowel(S[i])) V[i]++; } create_data(S); int bestk = 0; for (int a = 0; a <= N; a++) { int x = R[a]; int b = Q[x]; bestk = max(bestk, a - b); } if (bestk == 0) { cout << No solution << endl; return 0; } int found = 0; for (int a = 0; (a + bestk) <= N; a++) { if (Good(a, bestk)) { found++; } } cout << bestk << << found << endl; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, a[1000500]; map<pair<int, long long>, bool> dp; bool found = false; void solve(int idx, long long sum, bool take) { if (found) return; if (take && sum % m == 0) { found = true; return; } if (idx >= n) return; bool &ret = dp[{idx, sum}]; if (ret) return; ret = true; solve(idx + 1, sum + a[idx], take + 1); if (found) return; solve(idx + 1, sum, take); if (found) return; } int main() { scanf( %lld%lld , &n, &m); bool z = false; for (int i = 0; i < n; ++i) scanf( %lld , &a[i]), z |= (a[i] == 0); solve(0, 0, 0); if (z || found) return puts( YES ); puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int power(int a, int n, int m) { if (n <= 0) return 1; if (n % 2 == 1) { return ((int)(((long long)power(a, n - 1, m) * a) % m)); } else { int k = power(a, n / 2, m); return ((int)(((long long)k * k) % m)); } } int main() { long long n, m; cin >> n >> m; long long ans = (power(3, n, m) - 1) % m; if (ans < 0) ans += m; cout << ans; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input play,
input reset,
output sdout,
output lrck,
output mclk,
output DAC_STATUS
);
reg[8:0] dac_address_r;
wire[8:0] dac_address = dac_address_r;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[7:0] vol_reg;
reg[7:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
reg [25:0] interpol_count;
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [8:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
assign mclk = cnt[2]; // mclk = clk/8
assign lrck = cnt[8]; // lrck = mclk/128
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] lrck_sreg;
reg [2:0] sclk_sreg;
wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg [1:0] reset_sreg;
wire reset_rising = (reset_sreg[1:0] == 2'b01);
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 10'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 8'h0;
vol_target_reg = 8'hff;
samples <= 2'b00;
end
always @(posedge clkin) begin
if(reset_rising) begin
dac_address_r <= 0;
interpol_count <= 0;
end else if(sysclk_rising) begin
if(interpol_count > 59378938) begin
interpol_count <= interpol_count + 122500 - 59501439;
dac_address_r <= dac_address_r + play_r;
end else begin
interpol_count <= interpol_count + 122500;
end
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
end
// ramp volume only every 4 samples
always @(posedge clkin) begin
if (lrck_rising && &samples[1:0]) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
always @(posedge clkin) begin
if (lrck_rising) begin // right channel
smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
samples <= samples + 1;
end else if (lrck_falling) begin // left channel
smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
end else begin
if (sclk_rising) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> inline int read() { int data = 0, w = 1; char ch = getchar(); while (ch != - && !std::isdigit(ch)) ch = getchar(); if (ch == - ) w = -1, ch = getchar(); while (std::isdigit(ch)) data = data * 10 + (ch ^ 48), ch = getchar(); return data * w; } const int N(1e5 + 10); std::vector<int> G[N]; int n, m, val[N], fa[N], size[N], heavy[N]; int dfn[N], pos[N], bel[N], bot[N], cnt, ans; void dfs(int x) { size[x] = 1; for (auto i : G[x]) { dfs(i), size[x] += size[i]; if (size[heavy[x]] < size[i]) heavy[x] = i; } } void dfs(int x, int c) { pos[dfn[x] = ++cnt] = x, bel[x] = c, bot[bel[x]] = x; if (heavy[x]) dfs(heavy[x], c); for (auto i : G[x]) if (i != heavy[x]) dfs(i, i); } struct Chain { int L, B, cnt; std::vector<int> tag, bel, v, bl, br, vis; std::vector<std::vector<int>> t; void build(int l, int r) { L = r - l + 1, B = std::sqrt(L), cnt = (L - 1) / B + 1; tag.resize(cnt + 1), bel.resize(L + 1), vis.resize(L + 1); bl.resize(cnt + 1), br.resize(cnt + 1), v.resize(L + 1); for (int i = 1; i <= L; i++) bel[i] = (i - 1) / B + 1; for (int i = 1; i <= L; i++) br[bel[i]] = i; for (int i = L; i >= 1; i--) bl[bel[i]] = i; t.assign(cnt + 1, std::vector<int>(B << 1 | 1)); for (int i = 1; i <= L; i++) v[i] = val[pos[i + l - 1]]; for (int i = 1; i <= L; i++) if ((-B <= (v[i]) && (v[i]) <= B)) ++t[bel[i]][v[i] + B]; } void rebuild(int x) { for (int i = bl[x]; i <= br[x]; i++) v[i] -= tag[x]; tag[x] = 0, t[x].assign(B << 1 | 1, 0); for (int i = bl[x]; i <= br[x]; i++) if (!vis[i]) { if ((-B <= (v[i]) && (v[i]) <= B)) ++t[x][v[i] + B]; if (v[i] <= tag[x]) ++ans; } } void Brute_Modify(int x, int l, int r, int d) { for (int i = l; i <= r; i++) if (!vis[i]) { if ((-B <= (v[i]) && (v[i]) <= B)) --t[x][v[i] + B]; if (v[i] <= tag[x]) --ans; } for (int i = l; i <= r; i++) v[i] += d; for (int i = l; i <= r; i++) if (!vis[i]) { if ((-B <= (v[i]) && (v[i]) <= B)) ++t[x][v[i] + B]; if (v[i] <= tag[x]) ++ans; } } void Modify(int l, int r, int d) { if (bel[l] == bel[r]) return Brute_Modify(bel[l], l, r, -d); for (int i = bel[l] + 1; i < bel[r]; i++) { tag[i] += d; if (!(-B <= (tag[i]) && (tag[i]) <= B)) { for (int j = bl[i]; j <= br[i]; j++) if (!vis[j] && v[j] <= tag[i] - d) --ans; rebuild(i); } else if (d == 1) ans += t[i][tag[i] + B]; else ans -= t[i][tag[i] + B + 1]; } Brute_Modify(bel[l], l, br[bel[l]], -d); Brute_Modify(bel[r], bl[bel[r]], r, -d); } void recol(int x, int d) { int b = bel[x]; vis[x] = (d == 1); if ((-B <= (v[x]) && (v[x]) <= B)) t[b][v[x] + B] -= d; if (v[x] <= tag[b]) ans -= d; } } b[N]; int main() { n = read(), m = read(); for (int i = 2; i <= n; i++) G[fa[i] = read()].push_back(i); for (int i = 1; i <= n; i++) val[i] = read() + 1; dfs(1), dfs(1, 1); for (int i = 1; i <= n; i++) if (bel[i] == i) b[i].build(dfn[i], dfn[bot[i]]); for (int i = 1, x, o; i <= m; printf( %d , ans), i++) { x = read(), o = 1; if (x < 0) o = -1, x = -x; b[bel[x]].recol(dfn[x] - dfn[bel[x]] + 1, o); for (; x; b[bel[x]].Modify(1, dfn[x] - dfn[bel[x]] + 1, o), x = fa[bel[x]]) ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n; int mx = 0; for (int i = 0; i < n; i++) { cin >> x >> y; mx = max(mx, (x + y)); } cout << mx << endl; }
|
module erx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, emesh_access_in, emesh_packet_in, remap_mode, remap_sel,
remap_pattern, remap_base
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//Clock/reset
input clk;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
//Configuration
input [1:0] remap_mode; //00=none,01=static,02=continuity
input [11:0] remap_sel; //number of bits to remap
input [11:0] remap_pattern; //static pattern to map to
input [31:0] remap_base; //remap offset
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
wire [31:0] static_remap;
wire [31:0] dynamic_remap;
wire [31:0] remap_mux;
wire [31:0] addr_in;
wire [31:0] addr_out;
wire remap_en;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
//TODO:FIX!??
parameter[5:0] colid = ID[5:0];
//parsing packet
assign addr_in[31:0] = emesh_packet_in[39:8];
//simple static remap
assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
(~remap_sel[11:0] & addr_in[31:20]);
assign static_remap[19:0] = addr_in[19:0];
//more complex compresssed map
assign dynamic_remap[31:0] = addr_in[31:0] //input
- (colid << 20) //subtracing elink (start at 0)
+ remap_base[31:0] //adding back base
- (addr_in[31:26]<<$clog2(colid));
//Static, dynamic, or no remap
assign remap_mux[31:0] = (addr_in[31:20]==ID) ? addr_in[31:0] : //for write to mailbox
(remap_mode[1:0]==2'b00) ? addr_in[31:0] :
(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
dynamic_remap[31:0];
//Access pipeline
always @ (posedge clk)
emesh_access_out <= emesh_access_in;
//Packet Remapping
always @ (posedge clk)
emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
remap_mux[31:0],
emesh_packet_in[7:0]
};
endmodule // etx_mux
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, r[1000], c[1000], min[1000], sum = 0; cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> r[i] >> c[i]; min[i] = 9999999999; } for (int i = 0; i < n; i++) if (min[r[i] - 1] > c[i]) min[r[i] - 1] = c[i]; for (int i = 0; i < m; i++) sum += min[i]; if (sum > k) cout << k; else cout << sum; }
|
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