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#include <bits/stdc++.h> using namespace std; using ii = pair<int, int>; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc; cin >> tc; while (tc--) { int n, mx = 0, mn; cin >> n; vector<int> v(n); for (int &vi : v) { cin >> vi; mx = max(mx, vi); } set<ii> ans; mn = n - mx; vector<bool> sL(mn + 1, false), sR(mx + 1, false); bool can = true; for (int i = 0; i < n; ++i) { if (i < mn) { if (v[i] > mn) { can = false; break; } else if (sL[v[i]]) { can = false; break; } sL[v[i]] = true; } else { if (sR[v[i]]) { can = false; break; } sR[v[i]] = true; } } if (can && mn) ans.insert({mn, mx}); vector<bool> SL(mx + 1, false), SR(mn + 1, false); can = true; for (int i = 0; i < n; ++i) { if (i >= mx) { if (v[i] > mn) { can = false; break; } else if (SR[v[i]]) { can = false; break; } SR[v[i]] = true; } else { if (SL[v[i]]) { can = false; break; } SL[v[i]] = true; } } if (can && mn) ans.insert({mx, mn}); cout << ans.size() << n ; for (const auto &x : ans) cout << x.first << << x.second << n ; } return 0; }
|
`timescale 1ns/1ns
module ddr2_interface2um(
fpga_resetn, //system reset,active low
sysclk_100m, //system clk=100MHz LVCOMS
ddr2_ck, //DDR2 System Clock Pos
ddr2_ck_n, //DDR2 System Clock Neg
//Address
ddr2_addr, //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_bank_addr, //only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_ras_n, //Row address select
ddr2_cas_n, //Column address select
ddr2_we_n, //Write enable
//command and control
ddr2_cs_n, //Chip Select
ddr2_cke, //Clock Enable
ddr2_odt, //On-die termination enable
//Data Bus
ddr2_dq, //Data
ddr2_dqs, //Strobe Pos
ddr2_dqs_n, //Strobe Neg
ddr2_dm, //Byte write mask
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty
);
input sysclk_100m; //system clk=100MHz LVCOMS
input fpga_resetn; //system reset,active low
//////ddr2 interface/////////////////
inout ddr2_ck; //DDR2 System Clock Pos
inout ddr2_ck_n; //DDR2 System Clock Neg
//Address
output [15:0] ddr2_addr; //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output [2:0] ddr2_bank_addr;
//only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output ddr2_ras_n; //Row address select
output ddr2_cas_n; //Column address select
output ddr2_we_n; //Write enable
//command and control
output ddr2_cs_n; //Chip Select
output ddr2_cke; //Clock Enable
output ddr2_odt; //On-die termination enable
//Data Bus
inout [15:0] ddr2_dq; //Data
inout [1:0] ddr2_dqs; //Strobe Pos
inout [1:0] ddr2_dqs_n; //Strobe Neg
inout [1:0] ddr2_dm; //Byte write mask
///um interface //////////////
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
wire local_ready;
wire [31:0] local_rdata;
wire local_rdata_valid;
wire local_init_done;
wire[23:0] local_address;
wire local_write_req;
wire local_read_req;
wire local_burstbegin;
wire[31:0] local_wdata;
wire[3:0] local_be;
wire[3:0] local_size;
wire phy_clk;
assign ddr2_addr[15:13] = 3'b0;
assign ddr2_bank_addr[2] = 1'b0;
ddr2 ddr2_ctrl_hp_inst
(
.pll_ref_clk(sysclk_100m) , // input pll_ref_clk_sig
.global_reset_n(fpga_resetn) , // input global_reset_n_sig
.soft_reset_n(fpga_resetn) , // input soft_reset_n_sig
.local_address(local_address) , // input [25:0] local_address_sig //by cyj
.local_write_req(local_write_req) , // input local_write_req_sig
.local_wdata_req() , // output local_wdata_req_sig
.local_wdata(local_wdata) , // input [127:0] Write data in fourth
.local_read_req(local_read_req) , // input local_read_req_sig
.local_be(local_be) , // input [15:0] local_be_sig
.local_size(local_size) , // input [1:0] local_size_sig //only 1bits
.local_ready(local_ready) , // output local_ready_sig
.local_rdata(local_rdata) , // output [127:0] local_rdata_sig output 256bits data by cyj
.local_rdata_valid(local_rdata_valid) , // output local_rdata_valid_sig
.local_init_done(local_init_done) , // output local_init_done_sig -- Not used
.local_burstbegin(local_burstbegin),
.reset_request_n() , // output reset_request_n_sig -- Not used
.mem_odt(ddr2_odt) , // output [0:0] mem_odt_sig
.mem_cs_n(ddr2_cs_n) , // output [0:0] mem_cs_n_sig
.mem_cke(ddr2_cke) , // output [0:0] mem_cke_sig
.mem_addr(ddr2_addr[12:0]) , // output [13:0] mem_addr_sig
.mem_ba(ddr2_bank_addr[1:0]) , // output [1:0] mem_ba_sig //by cyj 3 signals
.mem_ras_n(ddr2_ras_n) , // output mem_ras_n_sig
.mem_cas_n(ddr2_cas_n) , // output mem_cas_n_sig
.mem_we_n(ddr2_we_n) , // output mem_we_n_sig
.mem_dm(ddr2_dm) , // output [7:0] mem_dm_sig
.local_refresh_ack() , // output local_refresh_ack_sig -- Not used
.reset_phy_clk_n() , // output reset_phy_clk_n_sig -- Not used
.dll_reference_clk() , // output dll_reference_clk_sig -- Not used
.dqs_delay_ctrl_export() , // output [5:0] dqs_delay_ctrl_export_sig -- Not used
.local_powerdn_ack(), //by cyj
.phy_clk(phy_clk) , // output phy_clk_sig
.aux_full_rate_clk() , // output aux_full_rate_clk_sig -- Not used
.aux_half_rate_clk() , // output aux_half_rate_clk_sig -- Not used
.mem_clk(ddr2_ck) , // inout [1:0] mem_clk_sig
.mem_clk_n(ddr2_ck_n) , // inout [1:0] mem_clk_n_sig
.mem_dq(ddr2_dq) , // inout [63:0] mem_dq_sig
.mem_dqs(ddr2_dqs), // inout [7:0] mem_dqs_sig
.mem_dqsn(ddr2_dqs_n) //by cyj
);
ddr2_ctrl ddr2_ctrl(
.sys_rst_n(fpga_resetn),
.ddr2_clk(phy_clk),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_address(local_address),
.local_read_req(local_read_req),
.local_write_req(local_write_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_burstbegin(local_burstbegin),
.um2ddr_wrclk(um2ddr_wrclk),
.um2ddr_wrreq(um2ddr_wrreq),
.um2ddr_data(um2ddr_data),
.um2ddr_ready(um2ddr_ready),
.um2ddr_command_wrreq(um2ddr_command_wrreq),
.um2ddr_command(um2ddr_command),
.ddr2um_rdclk(ddr2um_rdclk),
.ddr2um_rdreq(ddr2um_rdreq),
.ddr2um_rdata(ddr2um_rdata),
.ddr2um_valid_rdreq(ddr2um_valid_rdreq),
.ddr2um_valid_rdata(ddr2um_valid_rdata),
.ddr2um_valid_empty(ddr2um_valid_empty)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_1_V
`define SKY130_FD_SC_MS__A311OI_1_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_1_V
|
#include <bits/stdc++.h> using namespace std; template <class T, class V> ostream &operator<<(ostream &s, pair<T, V> a) { s << a.first << << a.second; return s; } struct NTT { long long int MD, M = 1, R; vector<int> r; vector<long long int> w[2]; long long int bigmod(long long int a, long long int p, long long int m) { long long int res = 1, x = a; while (p) { if (p & 1) res = (res * x) % m; x = (x * x) % m; p >>= 1; } return res; } long long int primitive_root(int n) { int p = n - 1; vector<int> d; for (int i = 2; i * i <= p; i++) { if (p % i == 0) { d.push_back(i); while (p % i == 0) p /= i; } } if (p > 1) d.push_back(p); for (int i = 2; i <= n; i++) { bool ok = true; for (auto x : d) ok &= (bigmod(i, (n - 1) / x, n) != 1); if (ok) return i; } assert(false); } NTT(long long int n, long long int _MD) : MD(_MD) { int u = 0; while (M < n) M <<= 1, u++; r.resize(M); w[0].resize(M, 1); w[1].resize(M, 1); R = 3; w[0][1] = bigmod(R, (MD - 1) / M, MD); w[1][1] = bigmod(w[0][1], MD - 2, MD); for (int i = 1; i < M; i++) { int l = __builtin_ctz(i); r[i] = r[i ^ (1 << l)] | (1 << (u - l - 1)); w[0][i] = w[0][i - 1] * w[0][1] % MD; w[1][i] = w[1][i - 1] * w[1][1] % MD; } } void fft(vector<long long int> &a, bool inv = false) { for (int i = 0; i < M; i++) if (i < r[i]) swap(a[i], a[r[i]]); for (int len = 2; len <= M; len <<= 1) { for (int i = 0, inc = M / len; i < M; i += len) { for (int j = 0, l = 0; j < (len >> 1); j++, l += inc) { long long int u = a[i + j], v = a[i + j + (len >> 1)] * w[inv][l] % MD; a[i + j] = (u + v >= MD ? u + v - MD : u + v); a[i + j + (len >> 1)] = (u < v ? u - v + MD : u - v); } } } if (inv) { long long int r = bigmod(M, MD - 2, MD); for (auto &x : a) x = x * r % MD; } } vector<long long int> multiply(vector<long long int> &a, vector<long long int> &b) { vector<long long int> v1(M), v2(M); for (int i = 0; i < a.size(); i++) v1[i] = a[i]; for (int i = 0; i < b.size(); i++) v2[i] = b[i]; fft(v1); fft(v2); for (int i = 0; i < M; i++) v1[i] = v1[i] * v2[i] % MD; fft(v1, 1); return v1; } vector<long long int> POWER(vector<long long int> &a, long long int n) { vector<long long int> v1(M); for (int i = 0; i < a.size(); i++) v1[i] = a[i]; fft(v1); for (int i = 0; i < M; i++) v1[i] = bigmod(v1[i], n, MD); fft(v1, 1); return v1; } }; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int T = 1; for (int qq = 1; qq <= T; qq++) { int n, k; cin >> n >> k; vector<long long int> v(10); while (k--) { long long int x; cin >> x; v[x] = 1; } long long int u = n / 2; NTT nt(1 << 20, (998244353)); v = nt.POWER(v, u); long long int a = 0; for (int i = 0; i < v.size(); i++) a = (v[i] * v[i] + a) % (998244353); cout << a << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_1_V
`define SKY130_FD_SC_LP__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, q; int arr[110][110], r[10010], c[10010], v[10010], t[10010]; int main() { scanf( %d , &n), scanf( %d , &m), scanf( %d , &q); for (int z = 0; z < q; ++z) { scanf( %d , &t[z]); if (t[z] == 1) scanf( %d , &r[z]); if (t[z] == 2) scanf( %d , &c[z]); if (t[z] == 3) scanf( %d , &r[z]), scanf( %d , &c[z]), scanf( %d , &v[z]); } reverse(t, t + q); reverse(c, c + q); reverse(r, r + q); reverse(v, v + q); for (int z = 0; z < q; ++z) { if (t[z] == 1) { --r[z]; v[z] = arr[r[z]][m - 1]; for (int j = m - 1; j > 0; --j) arr[r[z]][j] = arr[r[z]][j - 1]; arr[r[z]][0] = v[z]; } else if (t[z] == 2) { --c[z]; v[z] = arr[n - 1][c[z]]; for (int i = n - 1; i > 0; --i) arr[i][c[z]] = arr[i - 1][c[z]]; arr[0][c[z]] = v[z]; } else { arr[r[z] - 1][c[z] - 1] = v[z]; } } for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) printf( %d%c , arr[i][j], n [j == m - 1]); }
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
`timescale 100ps/100ps
module serializer #(
parameter LOG_DWIDTH=7,
parameter DWIDTH=64
)
(
input wire clk,
input wire fast_clk,
input wire [DWIDTH-1:0] data_in,
output wire data_out
);
reg [DWIDTH-1:0] buffer;
// SEQUENTIAL PROCESS
always @ (posedge clk)
begin
buffer <= data_in;
end
reg [LOG_DWIDTH-1:0] curr_bit = 'h0;
reg clk_d1;
always @ (posedge fast_clk)
begin
curr_bit <= curr_bit + 1;
clk_d1 <= clk;
if (!clk_d1 && clk)
curr_bit <= 0;
end
assign data_out = buffer[curr_bit];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> string toString(T x) { if (x == 0) return 0 ; bool negative = x < 0; string res; while (x) { res.push_back( 0 + x % 10); x /= 10; } if (negative) res.push_back( - ); reverse(res.begin(), res.end()); return res; } template <typename T> T gcd(T a, T b) { return a == 0 ? b : gcd(b % a, a); } template <typename T> T lcm(T a, T b) { return a / gcd(a, b) * b; } int main() { string s; cin >> s; vector<int> a(s.length() / 2); int m; cin >> m; for (int i = 0; i < m; i++) { int t; cin >> t; t--; a[t]++; } int l = s.length() / 2; vector<bool> r(l); int carry = 0; for (int i = 0; i < l; i++) { int t = a[i] + carry; carry = t % 2; r[i] = carry; } for (int i = 0; i < l; i++) { if (r[i]) { cout << s[s.length() - 1 - i]; } else { cout << s[i]; } } if (s.length() % 2 == 1) { cout << s[l]; l++; } for (int i = (s.length() + 1) / 2; i < s.length(); i++) { if (r[s.length() - 1 - i]) { cout << s[s.length() - 1 - i]; } else { cout << s[i]; } } return 0; }
|
// $Id: c_prio_enc.v 1734 2009-12-15 03:27:19Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// priority encoder (port 0 has highest priority)
module c_prio_enc
(data_in, data_out);
`include "c_functions.v"
// number of input ports (i.e., decoded width)
parameter num_ports = 8;
localparam width = clogb(num_ports);
// one-hot input data
input [0:num_ports-1] data_in;
// binary encoded output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [(width+1)*num_ports-1] masks;
assign masks[0:num_ports-1] = {num_ports{1'b1}};
generate
genvar level;
for(level = 0; level < width; level = level + 1)
begin:levels
wire sel;
wire [0:num_ports-1] mask_in;
assign mask_in = masks[level*num_ports:(level+1)*num_ports-1];
wire [0:num_ports-1] bits;
wire value;
wire [0:num_ports-1] mask_out;
genvar position;
for(position = 0; position < num_ports; position = position + 1)
begin:positions
if(position & (1 << level))
begin
assign bits[position]
= data_in[position] & mask_in[position];
assign mask_out[position]
= mask_in[position] & value;
end
else
begin
assign bits[position] = 1'b0;
assign mask_out[position]
= mask_in[position] & ~value;
end
end
assign value = |bits;
assign data_out[(width-1)-level] = value;
assign mask_out[(level+1)*num_ports:(level+2)*num_ports-1]
= mask_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 5; int n, a[N]; int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (fopen( main.in , r )) freopen( main.in , r , stdin); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int cnt = 0; for (int i = 2; i < n; i++) if (a[i - 1] == 1 && a[i + 1] == 1 && a[i] == 0) a[i + 1] = 0, cnt++; cout << cnt; return 0; }
|
module main;
string foo;
int error_count;
task check_char(input int idx, input [7:0] val);
if (foo[idx] !== val) begin
$display("FAILED: foo[%0d]==%02h, expecting %02h",
idx, foo[idx], val);
error_count = error_count+1;
end
endtask // check_char
initial begin
// These are the special charasters in strings as defined by
// IEEE Std 1800-2017: 5.9.1 Special characters in strings.
// The string assignment is governed by:
// IEEE Std 1800-2017: 6.16 String data type
foo = "abc\n\t\\\"\v\f\a\001\002\x03\x04";
error_count = 0;
check_char(0, 8'h61); // 'a'
check_char(1, 8'h62); // 'b'
check_char(2, 8'h63); // 'c'
check_char(3, 8'h0a); // '\n'
check_char(4, 8'h09); // '\t'
check_char(5, 8'h5c); // '\\'
check_char(6, 8'h22); // '\"'
check_char(7, 8'h0b); // '\v'
check_char(8, 8'h0c); // '\f'
check_char(9, 8'h07); // '\a'
check_char(10, 8'h01); // '\001'
check_char(11, 8'h02); // '\002'
check_char(12, 8'h03); // '\x03'
check_char(13, 8'h04); // '\x04'
if (foo.len() !== 14) begin
$display("FAILED: foo.len() == %0d, should be 14", foo.len());
error_count = error_count+1;
end
if (error_count == 0) $display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int n, l[10], r[10], t = 1; double ans = 0, o = 1; cin >> n; for (int i = 0; i < n; i++) { t *= 2; cin >> l[i] >> r[i]; o *= r[i] - l[i] + 1; } if (n == 1) { cout << setprecision(10) << fixed << (r[0] + l[0]) / 2.0 << endl; return 0; } for (int i = 1; i <= 10000; i++) { for (int g = 0; g < n; g++) { if (r[g] <= i) continue; for (int j = 1; j < t; j++) { int a[10] = {}, t2 = j, o = 0; while (t2) { a[o++] = t2 % 2; t2 /= 2; } if (a[g]) continue; double k = 1; bool ch = 0; for (int h = 0; h < n; h++) { if (h == g) continue; if (a[h] && (r[h] < i || l[h] > i)) { ch = 1; h = n; } if (!a[h] && l[h] >= i) { ch = 1; h = n; } if (!a[h]) k *= min(i - 1, r[h]) - l[h] + 1; } if (ch) continue; k *= r[g] - max(i + 1, l[g]) + 1; ans += k * i; } } } for (int i = 1; i <= 10000; i++) { for (int j = 1; j < t; j++) { int a[10] = {}, t2 = j, o = 0, d = 0; while (t2) { a[o++] = t2 % 2; if (a[o - 1]) d++; t2 /= 2; } double k = 1; if (d == 1) continue; bool ch = 0; for (int h = 0; h < n; h++) { if (a[h] && (r[h] < i || l[h] > i)) { ch = 1; h = n; } if (!a[h] && l[h] >= i) { ch = 1; h = n; } if (!a[h]) k *= min(i - 1, r[h]) - l[h] + 1; } if (ch) continue; ans += k * i; } } cout << setprecision(10) << fixed << ans / o << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> constexpr string_view gtype() { string_view s = __PRETTY_FUNCTION__; return string_view(s.data() + 45, s.find( ; , 45) - 45); } const int MAXN = 10000; int arr[MAXN]; int best[MAXN]; int cur[MAXN]; int n; const long long MOD = 1000000009; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int n; cin >> n; vector<pair<int, int> > vv(n); for (int i = 0; i < n; i++) { int x; cin >> x; vv[i] = {x, i + 1}; } vector<int> sim; sim.push_back(-1); sort(((vv).begin()), ((vv).end())); for (int i = 0; i < int((vv).size()) - 1; i++) if (vv[i].first == vv[i + 1].first) sim.push_back(i); if (int((sim).size()) <= 2) cout << NO n ; else { cout << YES n ; for (int j = 0; j < 3; ++j) { for (int i = 0; i < int((vv).size()); i++) { if (i == sim[j]) { cout << vv[i + 1].second << << vv[i].second << ; i++; } else cout << vv[i].second << ; } cout << endl; } } return 0; }
|
//----------------------------------------------------------------------
// Title : Vector Configuration Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : configuration_tb.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: Management
//
// This testbench will control the speed settings of the
// EMAC block (if required) by driving the Tie-off vector.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module configuration_tb
(
reset,
//----------------------------------------------------------------
// Host interface: host_clk is always required
//----------------------------------------------------------------
host_clk,
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
configuration_busy,
monitor_finished_1g,
monitor_finished_100m,
monitor_finished_10m,
monitor_error
);
// Port declarations
output reg reset;
output reg host_clk;
output reg configuration_busy;
input monitor_finished_1g;
input monitor_finished_100m;
input monitor_finished_10m;
input monitor_error;
//--------------------------------------------------------------------
// HOSTCLK driver
//--------------------------------------------------------------------
// Drive HOSTCLK at one third the frequency of GTX_CLK
initial
begin
host_clk <= 1'b0;
#2000;
forever
begin
host_clk <= 1'b1;
#12000;
host_clk <= 1'b0;
#12000;
end
end
//------------------------------------------------------------------
// Testbench configuration
//------------------------------------------------------------------
initial
begin : tb_configuration
reset <= 1'b1;
// test bench semaphores
configuration_busy <= 0;
#200000
configuration_busy <= 1;
// Reset the core
$display("Resetting the design...");
$display("Timing checks are not valid");
reset <= 1'b1;
#;
reset <= 1'b0;
#200000;
$display("Timing checks are valid");
#15000000
#100000
configuration_busy <= 0;
// Wait for 1Gb/s frames to complete
wait (monitor_finished_1g == 1);
#100000
if (monitor_error == 1'b1)
begin
$display("*************************");
$display("ERROR: Simulation Failed.");
$display("*************************");
end
else begin
$display("****************************");
$display("PASS: Simulation Successful.");
$display("****************************");
end
// Our work here is done
$display("Simulation Complete.");
$stop;
end // tb_configuration
//------------------------------------------------------------------
// If the simulation is still going after 2 ms
// then something has gone wrong
//------------------------------------------------------------------
initial
begin : p_end_simulation
#
$display("ERROR - Testbench timed out");
$stop;
end // p_end_simulation
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> len(n); vector<string> s(n); for (int i = 0; i < n; i++) { cin >> s[i]; len[i] = s[i].length(); } const int all = n - 1 + accumulate(len.begin(), len.end(), 0); vector<vector<bool>> eq(n, vector<bool>(n, false)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (s[i] == s[j]) eq[i][j] = true; } } vector<vector<int>> dp(n, vector<int>(n, 0)); for (int i = n - 1; i >= 0; i--) { for (int j = n - 1; j >= 0; j--) if (eq[i][j]) { if (i + 1 < n and j + 1 < n) dp[i][j] = dp[i + 1][j + 1] + 1; else dp[i][j] = 1; } } int ans = all; for (int i = 0; i < n; i++) { int sum = 0; for (int d = 0; i + d < n; d++) { int cnt = 1; sum += len[i + d]; for (int pos = i + d + 1; pos < n; pos++) { if (dp[i][pos] > d) { cnt++; pos += d; } } int res = all - sum * cnt + cnt; if (cnt > 1 and ans > res) ans = res; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; pair<int, int> mmx[3]; for (int i = 0; i < 3; i++) cin >> mmx[i].first >> mmx[i].second; int a, b, c; a = min(n - mmx[1].first - mmx[2].first, mmx[0].second); b = min(n - a - mmx[2].first, mmx[1].second); c = n - a - b; cout << a << << b << << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx8[8] = {-1, -1, 0, 1, 1, 1, 0, -1}, dx4[4] = {-1, 0, 1, 0}; int dy8[8] = {0, -1, -1, -1, 0, 1, 1, 1}, dy4[4] = {0, -1, 0, 1}; inline void open(string name) { freopen((name + .in ).c_str(), r , stdin); freopen((name + .out ).c_str(), w , stdout); } inline void close() { fclose(stdin); fclose(stdout); } inline int io() { register char c; while (1) { c = getchar_unlocked(); if (c != n && c != ) break; } int res = 0, sign = 1; if (c == - ) sign = -1; else res = c - 0 ; while (1) { c = getchar_unlocked(); if (c == || c == n || c == EOF) break; res = (res << 3) + (res << 1) + c - 0 ; } return res * sign; } const int N = 100005; struct Bullet { int x; int y; int idx; Bullet() {} bool operator<(Bullet other) const { if (x == other.x) { if (y == other.y) return idx < other.idx; else return y < other.y; } else return x < other.x; } }; Bullet origin[N], arr[N]; struct Node { vector<pair<int, int> > bullet_list; vector<int> RMQ; Node() { bullet_list.clear(); RMQ.clear(); } void Build() { RMQ.resize(4 * bullet_list.size()); Build(1, 0, bullet_list.size() - 1); } void Build(int id, int l, int r) { if (l == r) RMQ[id] = bullet_list[l].second; else { int chld = id << 1, m = (l + r) >> 1; Build(chld, l, m); Build(chld + 1, m + 1, r); RMQ[id] = min(RMQ[chld], RMQ[chld + 1]); } } int Query(int ya, int yb) { int st = lower_bound(bullet_list.begin(), bullet_list.end(), make_pair(ya, 0)) - bullet_list.begin(); int en = upper_bound(bullet_list.begin(), bullet_list.end(), make_pair(yb, 1000000000)) - bullet_list.begin(); en--; if (st > en) return 1000000000; else return Query(1, 0, bullet_list.size() - 1, st, en); } int Query(int id, int l, int r, int x, int y) { if (x <= l && r <= y) return RMQ[id]; else { int chld = (id << 1), m = (l + r) >> 1; int res = 1000000000; if (x <= m) res = min(res, Query(chld, l, m, x, y)); if (y > m) res = min(res, Query(chld + 1, m + 1, r, x, y)); return res; } } void Del(int id) { int ya = origin[id].y; int st = lower_bound(bullet_list.begin(), bullet_list.end(), make_pair(ya, id)) - bullet_list.begin(); Del(1, 0, bullet_list.size() - 1, st); } void Del(int id, int l, int r, int x) { if (l == r) { RMQ[id] = 1000000000; } else { int chld = id << 1, m = (l + r) >> 1; if (x <= m) Del(chld, l, m, x); else Del(chld + 1, m + 1, r, x); RMQ[id] = min(RMQ[chld], RMQ[chld + 1]); } } }; Node rtree[4 * N]; vector<int> X; int n, q; int ans[N]; void BuildRangeTree(int id, int l, int r) { if (l == r) { rtree[id].bullet_list.push_back(make_pair(arr[l].y, arr[l].idx)); } else { int chld = id << 1, m = (l + r) >> 1; BuildRangeTree(chld, l, m); BuildRangeTree(chld + 1, m + 1, r); int i = 0, j = 0; while (i < rtree[chld].bullet_list.size() && j < rtree[chld + 1].bullet_list.size()) { if (rtree[chld].bullet_list[i] < rtree[chld + 1].bullet_list[j]) rtree[id].bullet_list.push_back(rtree[chld].bullet_list[i++]); else rtree[id].bullet_list.push_back(rtree[chld + 1].bullet_list[j++]); } while (i < rtree[chld].bullet_list.size()) rtree[id].bullet_list.push_back(rtree[chld].bullet_list[i++]); while (j < rtree[chld + 1].bullet_list.size()) rtree[id].bullet_list.push_back(rtree[chld + 1].bullet_list[j++]); } rtree[id].Build(); } void UpdateRangeTree(int pos) { int idpos = lower_bound(arr, arr + q, origin[pos]) - arr; int id = 1, l = 0, r = q - 1; while (1) { rtree[id].Del(pos); if (l == r) break; int chld = id << 1, m = (l + r) >> 1; if (idpos <= m) r = m, id = chld; else l = m + 1, id = chld + 1; } } int QueryRangeTree(int id, int l, int r, int x, int y, int ya, int yb) { int res = 1000000000; if (x <= l && r <= y) res = rtree[id].Query(ya, yb); else { int chld = (id << 1), m = (l + r) >> 1; res = 1000000000; if (x <= m) res = min(res, QueryRangeTree(chld, l, m, x, y, ya, yb)); if (y > m) res = min(res, QueryRangeTree(chld + 1, m + 1, r, x, y, ya, yb)); } return res; } struct Target { int xa; int ya; int xb; int yb; int z; int idx; Target() {} bool operator<(Target other) const { if (z == other.z) return idx < other.idx; return z < other.z; } }; Target arr2[N]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d %d %d %d , &arr2[i].xa, &arr2[i].xb, &arr2[i].ya, &arr2[i].yb, &arr2[i].z); arr2[i].idx = i; } sort(arr2, arr2 + n); scanf( %d , &q); for (int i = 0; i < q; i++) { scanf( %d %d , &origin[i].x, &origin[i].y); origin[i].idx = i; X.push_back(origin[i].x); arr[i] = origin[i]; } sort(arr, arr + q); sort(X.begin(), X.end()); BuildRangeTree(1, 0, q - 1); memset(ans, -1, sizeof ans); for (int i = 0; i < n; i++) { int x1 = lower_bound(X.begin(), X.end(), arr2[i].xa) - X.begin(); int x2 = upper_bound(X.begin(), X.end(), arr2[i].xb) - X.begin(); x2--; if (x1 <= x2) { int res = QueryRangeTree(1, 0, q - 1, x1, x2, arr2[i].ya, arr2[i].yb); if (res != 1000000000) { ans[res] = arr2[i].idx; UpdateRangeTree(res); } } } for (int i = 0; i < q; i++) printf( %d n , ans[i] + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, i, tmp, res, a[10000]; bool kt; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); kt = true; for (i = 3; i <= n; i++) if (a[i] - a[i - 1] != a[i - 1] - a[i - 2]) kt = false; if (kt == false) { printf( %d , a[n]); return 0; } tmp = a[1] - a[2]; res = a[n] - tmp; printf( %d , res); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Josh Redford.
interface my_if;
logic valid;
logic [7:0] data ;
modport slave_mp (
input valid,
input data
);
modport master_mp (
output valid,
output data
);
endinterface
module t
(
input wire in_valid,
input wire [7:0] in_data
);
my_if in_i ();
my_if out1_i ();
my_if out2_i ();
my_if out3_i ();
assign in_i.valid = in_valid;
assign in_i.data = in_data ;
my_module1 my_module1_i (
.in_i (in_i ),
.out_i (out1_i)
);
my_module2 my_module2_i (
.in_i (in_i ),
.out_i (out2_i)
);
my_module3 my_module3_i (
.in_i (in_i ),
.out_i (out3_i)
);
endmodule
module my_module1 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Gives ALWCOMBORDER warning
always_comb
begin
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
endmodule
module my_module2 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you initialise to non-interface signal first
always_comb
begin
out_i.valid = '0;
out_i.data = 'X;
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
endmodule
module my_module3 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you use assign signal
assign out_i.valid = in_i.valid;
assign out_i.data = in_i.data ;
endmodule
|
#include <bits/stdc++.h> const int oo = 2139063143; const int N = 101000; const int P = 1000000007; using namespace std; inline void sc(int &x) { x = 0; static int p; p = 1; static char c; c = getchar(); while (!isdigit(c)) { if (c == - ) p = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c - 48); c = getchar(); } x *= p; } inline void print(int x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) print(x / 10); putchar(x % 10 + 0 ); } inline void pr(int x) { print(x), putchar( n ); } int n, k; int vis[N], cl = 1, cr = 0, ans = 0; int a[N]; void add(int w, int d) { if (!vis[w] && d == 1) ++ans; else if (vis[w] == 1 && d == -1) --ans; vis[w] += d; } int calc(int l, int r) { while (cr < r) ++cr, add(a[cr], 1); while (cl > l) --cl, add(a[cl], 1); while (cr > r) add(a[cr], -1), --cr; while (cl < l) add(a[cl], -1), ++cl; return ans; } int f[N], g[N]; void solve(int wl, int wr, int l, int r) { int mid = (l + r) >> 1, pos = 0; f[mid] = 0; for (int i = wl; i <= min(wr, mid - 1); i++) { int sb = g[i] + calc(i + 1, mid); if (sb > f[mid]) f[mid] = sb, pos = i; } if (l == r) return; if (l < mid) solve(wl, pos, l, mid - 1); if (r > mid) solve(pos, wr, mid + 1, r); } int las[N]; int main() { sc(n), sc(k); for (int i = 1; i <= n; i++) sc(a[i]); for (int i = 1; i <= k; i++) { solve(0, n, 1, n); memcpy(g, f, sizeof(int) * (n + 1)); } pr(f[n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, spr; vector<string> valer; cin >> s; char h; int k = (int)s.size(); valer.push_back(s); for (int i = 1; i < k; i++) { h = s[k - 1]; for (int j = k - 1; j > 0; j--) { s[j] = s[j - 1]; } s[0] = h; spr = s; bool t = true; for (int r = 0; r < (int)valer.size(); r++) { if (spr == valer[r]) t = false; } if (t == true) { valer.push_back(spr); } } cout << (int)valer.size() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[200]; int n, x; vector<pair<int, int> > res; int main() { int sum = 0; cin >> n; cin >> a[0].first; a[0].second = 0; sum += a[0].first; for (int i = 1; i < n; i++) { cin >> a[i].first; a[i].second = i; sum += a[i].first; } if (a[0].first == 0 || sum < n - 1) { cout << -1; return 0; } sort(a + 1, a + n); reverse(a + 1, a + n); int x = 0; int y = 1; cout << n - 1 << endl; while (y < n) { cout << a[x].second + 1 << << a[y].second + 1 << endl; y++; a[x].first--; if (a[x].first == 0) x++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char st[100000]; int n, t, a[26], minn, maxx; int main() { scanf( %d%d , &n, &t); scanf( %s , st); minn = 25; maxx = 0; for (int i = 0; i < n; i++) { if (st[i] - 97 < minn) minn = st[i] - 97; if (st[i] - 97 > maxx) maxx = st[i] - 97; a[st[i] - 97] = 1; } if (t > n) { printf( %s , st); for (int i = n + 1; i <= t; i++) printf( %c , minn + 97); } else { int wei = t - 1; while (st[wei] - 97 == maxx) { st[wei] = minn + 97; wei--; } st[wei]++; while (a[st[wei] - 97] == 0) st[wei]++; for (int i = 0; i < t; i++) printf( %c , st[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n == 0) cout << 1; else { n %= 4; if (n == 0) n = 4; n = pow(8, n); cout << n % 10; } }
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.2
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/05/27 14:30:47 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR3 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
assign A = A_r;
assign B = B_r;
always@(*)
if((B == 'b1) || (B == 'b0))
B_inv <= #0 ~B ;
else
B_inv <= #0 'bz ;
// B_inv = (B == 1'bz) ? 1'bz : ~B;
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, gxx; pair<int, int> a[411111]; int p[411111]; int Gxx[411111], bb[411111]; int degree[411111]; int h, t; void make_ans(int x, int y, int tot) { int now_x = degree[x] - 1 - tot; int need_x = max(h - now_x, 0); int now_y = degree[y] - 1 - tot; int need_y = max(t - now_y, 0); for (int i = p[x]; i < p[x + 1]; i++) Gxx[a[i].second] = 1; for (int i = p[y]; i < p[y + 1]; i++) if (Gxx[a[i].second] == 1) bb[a[i].second] = 1; printf( YES n ); printf( %d %d n , x, y); bool bo = false; for (int i = p[x]; i < p[x + 1]; i++) if ((bb[a[i].second] == 0 || need_x) && a[i].second != y && h) { h--; if (bb[a[i].second]) { bb[a[i].second] = -1; need_x--; } if (bo) printf( ); bo = true; printf( %d , a[i].second); } printf( n ); bo = false; for (int i = p[y]; i < p[y + 1]; i++) if ((bb[a[i].second] == 0 || need_y) && a[i].second != x && t && bb[a[i].second] != -1) { t--; if (bb[a[i].second]) need_y--; if (bo) printf( ); bo = true; printf( %d , a[i].second); } printf( n ); } int find(int x, int y) { int ans = 0; for (int i = p[x]; i < p[x + 1]; i++) if (a[i].second != y) { int t = lower_bound(a + p[y], a + p[y + 1], make_pair(y, a[i].second)) - a; if (a[t].second == a[i].second) ans++; } return ans; } int main() { scanf( %d%d%d%d , &n, &m, &h, &t); for (int i = 1; i <= m; i++) { scanf( %d%d , &a[i].first, &a[i].second); degree[a[i].first]++; degree[a[i].second]++; a[i + m].second = a[i].first; a[i + m].first = a[i].second; } int M = m * 2; sort(a + 1, a + M + 1); a[0].first = 0; a[M + 1].first = n + 1; int now = 0; for (int i = 1; i <= M + 1; i++) while (now != a[i].first) { now++; p[now] = i; } p[0] = 0; for (int i = 1; i <= M; i++) if (degree[a[i].first] > h && degree[a[i].second] > t) { int t1 = a[i].first; int t2 = a[i].second; int tot = 0; if (t1 < t2) tot = find(t1, t2); else tot = find(t2, t1); if (degree[t1] + degree[t2] - 2 - tot >= h + t) { make_ans(t1, t2, tot); return 0; } } printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; long long int sum[N << 2][11], sum2[11], a[N]; int lazy[N << 2][11], vis[11]; void pushdown(int rt) { for (int i = 0; i < 10; i++) vis[i] = lazy[rt << 1][i], sum2[i] = sum[rt << 1][i]; for (int i = 0; i < 10; i++) if (lazy[rt][i] != i) { for (int j = 0; j < 10; j++) if (lazy[rt << 1][j] == i) vis[j] = lazy[rt][i]; sum2[lazy[rt][i]] += sum[rt << 1][i]; sum2[i] -= sum[rt << 1][i]; } for (int i = 0; i < 10; i++) sum[rt << 1][i] = sum2[i], lazy[rt << 1][i] = vis[i]; for (int i = 0; i < 10; i++) vis[i] = lazy[rt << 1 | 1][i], sum2[i] = sum[rt << 1 | 1][i]; for (int i = 0; i < 10; i++) if (lazy[rt][i] != i) { for (int j = 0; j < 10; j++) if (lazy[rt << 1 | 1][j] == i) vis[j] = lazy[rt][i]; sum2[lazy[rt][i]] += sum[rt << 1 | 1][i]; sum2[i] -= sum[rt << 1 | 1][i]; } for (int i = 0; i < 10; i++) sum[rt << 1 | 1][i] = sum2[i], lazy[rt << 1 | 1][i] = vis[i]; for (int i = 0; i < 10; i++) lazy[rt][i] = i; } void pushup(int rt) { for (int i = 0; i < 10; i++) sum[rt][i] = sum[rt << 1][i] + sum[rt << 1 | 1][i]; } void build(int rt, int l, int r) { for (int i = 0; i < 10; i++) sum[rt][i] = 0; for (int i = 0; i < 10; i++) lazy[rt][i] = i; if (l == r) { for (long long int t = 1; a[l]; a[l] /= 10, t *= 10) sum[rt][a[l] % 10] += t; return; } int m = r + l >> 1; build(rt << 1, l, m); build(rt << 1 | 1, m + 1, r); pushup(rt); } void update(int rt, int l, int r, int L, int R, int x, int y) { if (L <= l && r <= R) { for (int i = 0; i < 10; i++) if (lazy[rt][i] == x) { sum[rt][y] += sum[rt][x]; sum[rt][x] = 0; lazy[rt][i] = y; } return; } pushdown(rt); int m = r + l >> 1; if (L <= m) update(rt << 1, l, m, L, R, x, y); if (R > m) update(rt << 1 | 1, m + 1, r, L, R, x, y); pushup(rt); } long long int query(int rt, int l, int r, int L, int R) { if (L <= l && r <= R) { long long int ans = 0; for (long long int i = 1; i < 10; i++) ans += sum[rt][i] * i; return ans; } pushdown(rt); int m = r + l >> 1; long long int ans = 0; if (L <= m) ans += query(rt << 1, l, m, L, R); if (R > m) ans += query(rt << 1 | 1, m + 1, r, L, R); pushup(rt); return ans; } int n, m; int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); build(1, 1, n); int op, l, r, x, y; for (int i = 1; i <= m; i++) { scanf( %d%d%d , &op, &l, &r); if (1 == op) { scanf( %d%d , &x, &y); if (x == y) continue; update(1, 1, n, l, r, x, y); } else printf( %lld n , query(1, 1, n, l, r)); } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N8_M8_P5
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P5(
input [7:0] in1,
input [7:0] in2,
output [8:0] res
);
wire [2:0] temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;
wire p0,p1,p2,p3,p4,p5,p6,g0,g1,g2,g3,g4,g5,g6,c1,c2,c3,c4,c5,c6,c7;
wire p1c1,p2c2,p3c3,p4c4,p5c5,p6c6,p2p1c1,p3p2c2,p4p3c3,p5p4c4,p6p5c5,p3p2p1c1,p4p3p2c2,p4p3p2p1c1,p5p4p3c3,p5p4p3p2c2;
wire p6p5p4c4,p6p5p4p3c3;
wire carry_pred_1,carry_pred_2,carry_pred_3,carry_pred_4,carry_pred_5,carry_pred_6;
wire carry_pred_2_1;
wire carry_pred_3_1,carry_pred_3_2;
wire carry_pred_4_1,carry_pred_4_2,carry_pred_4_3;
wire carry_pred_5_2,carry_pred_5_3,carry_pred_5_4;
wire carry_pred_6_3,carry_pred_6_4,carry_pred_6_5;
and and_0(g0,in1[0],in2[0]);
and and_1(g1,in1[1],in2[1]);
and and_2(g2,in1[2],in2[2]);
and and_3(g3,in1[3],in2[3]);
and and_4(g4,in1[4],in2[4]);
and and_5(g5,in1[5],in2[5]);
and and_6(g6,in1[6],in2[6]);
xor xor_0(p0,in1[0],in2[0]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_4(p4,in1[4],in2[4]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_6(p6,in1[6],in2[6]);
assign c1 = g0;
assign c2 = g1;
and and_7(p1c1,p1,c1);
or or_0(carry_pred_1,c2,p1c1);
assign c3 = g2;
and and_8(p2c2,p2,c2);
and and_9(p2p1c1,p2,p1c1);
or or_1(carry_pred_2_1,p2c2,p2p1c1);
or or_2(carry_pred_2,c3,carry_pred_2_1);
assign c4 = g3;
and and_10(p3c3,p3,c3);
and and_11(p3p2c2,p3,p2c2);
and and_12(p3p2p1c1,p3,p2p1c1);
or or_3(carry_pred_3_1,p3p2c2,p3p2p1c1);
or or_4(carry_pred_3_2,p3c3,carry_pred_3_1);
or or_5(carry_pred_3,c4,carry_pred_3_2);
assign c5 = g4;
and and_13(p4c4,p4,c4);
and and_14(p4p3c3,p4,p3c3);
and and_15(p4p3p2c2,p4,p3p2c2);
and and_16(p4p3p2p1c1,p4,p3p2p1c1);
or or_6(carry_pred_4_1,p4p3p2c2,p4p3p2p1c1);
or or_7(carry_pred_4_2,p4p3c3,carry_pred_4_1);
or or_8(carry_pred_4_3,p4c4,carry_pred_4_2);
or or_9(carry_pred_4,c5,carry_pred_4_3);
assign c6 = g5;
and and_17(p5c5,p5,c5);
and and_18(p5p4c4,p5,p4c4);
and and_19(p5p4p3c3,p5,p4p3c3);
and and_20(p5p4p3p2c2,p5,p4p3p2c2);
or or_11(carry_pred_5_2,p5p4p3c3,p5p4p3p2c2);
or or_12(carry_pred_5_3,p5p4c4,carry_pred_5_2);
or or_13(carry_pred_5_4,p5c5,carry_pred_5_3);
or or_14(carry_pred_5,c6,carry_pred_5_4);
assign c7 = g6;
and and_22(p6c6,p6,c6);
and and_23(p6p5c5,p6,p5c5);
and and_24(p6p5p4c4,p6,p5p4c4);
and and_25(p6p5p4p3c3,p6,p5p4p3c3);
or or_17(carry_pred_6_3,p6p5p4c4,p6p5p4p3c3);
or or_18(carry_pred_6_4,p6p5c5,carry_pred_6_3);
or or_19(carry_pred_6_5,p6c6,carry_pred_6_4);
or or_20(carry_pred_6,c7,carry_pred_6_5);
// Results
assign temp1[1:0] = in1[0] + in2[0];
assign temp2[1:0] = in1[1] + in2[1] + c1;
assign temp3[1:0] = in1[2] + in2[2] + carry_pred_1;
assign temp4[1:0] = in1[3] + in2[3] + carry_pred_2;
assign temp5[1:0] = in1[4] + in2[4] + carry_pred_3;
assign temp6[1:0] = in1[5] + in2[5] + carry_pred_4;
assign temp7[1:0] = in1[6] + in2[6] + carry_pred_5;
assign temp8[1:0] = in1[7] + in2[7] + carry_pred_6;
assign res[8:0] = {temp8[1:0],temp7[0],temp6[0],temp5[0],temp4[0],temp3[0],temp2[0],temp1[0]};
endmodule
|
/* Description of an 8-bit data 8-bit address rom. */
module rom(en,rwb,addr,data);
input[7:0] addr;
output reg [7:0] data;
always @ (*)
begin
case(addr)
0: data <= 0;
1: data <= 1;
2: data <= 2;
3: data <= 3;
4: data <= 4;
5: data <= 5;
6: data <= 6;
7: data <= 7;
8: data <= 8;
9: data <= 9;
10: data <= 10;
11: data <= 11;
12: data <= 12;
13: data <= 13;
14: data <= 14;
15: data <= 15;
16: data <= 16;
17: data <= 17;
18: data <= 18;
19: data <= 19;
20: data <= 20;
21: data <= 21;
22: data <= 22;
23: data <= 23;
24: data <= 16;
25: data <= 25;
26: data <= 26;
27: data <= 27;
28: data <= 28;
29: data <= 29;
30: data <= 30;
31: data <= 31;
32: data <= 32;
33: data <= 33;
34: data <= 34;
35: data <= 35;
36: data <= 36;
37: data <= 37;
38: data <= 38;
39: data <= 39;
40: data <= 40;
41: data <= 41;
42: data <= 42;
43: data <= 43;
44: data <= 44;
45: data <= 45;
46: data <= 46;
47: data <= 47;
48: data <= 48;
49: data <= 49;
50: data <= 50;
51: data <= 51;
52: data <= 52;
53: data <= 53;
54: data <= 54;
55: data <= 55;
56: data <= 48;
57: data <= 57;
58: data <= 58;
59: data <= 59;
60: data <= 60;
61: data <= 61;
62: data <= 62;
63: data <= 63;
64: data <= 64;
65: data <= 65;
66: data <= 66;
67: data <= 67;
68: data <= 68;
69: data <= 69;
70: data <= 70;
71: data <= 71;
72: data <= 72;
73: data <= 73;
74: data <= 74;
75: data <= 75;
76: data <= 76;
77: data <= 77;
78: data <= 78;
79: data <= 79;
80: data <= 80;
81: data <= 81;
82: data <= 82;
83: data <= 83;
84: data <= 84;
85: data <= 85;
86: data <= 86;
87: data <= 87;
88: data <= 80;
89: data <= 89;
90: data <= 90;
91: data <= 91;
92: data <= 92;
93: data <= 93;
94: data <= 94;
95: data <= 95;
96: data <= 96;
97: data <= 97;
98: data <= 98;
99: data <= 99;
100: data <= 100;
101: data <= 101;
102: data <= 102;
103: data <= 103;
104: data <= 104;
105: data <= 105;
106: data <= 106;
107: data <= 107;
108: data <= 108;
109: data <= 109;
110: data <= 110;
111: data <= 111;
112: data <= 112;
113: data <= 113;
114: data <= 114;
115: data <= 115;
116: data <= 116;
117: data <= 117;
118: data <= 118;
119: data <= 119;
120: data <= 112;
121: data <= 121;
122: data <= 122;
123: data <= 123;
124: data <= 124;
125: data <= 125;
126: data <= 126;
127: data <= 127;
128: data <= 128;
129: data <= 129;
130: data <= 130;
131: data <= 131;
132: data <= 132;
133: data <= 133;
134: data <= 134;
135: data <= 135;
136: data <= 136;
137: data <= 137;
138: data <= 138;
139: data <= 139;
140: data <= 140;
141: data <= 141;
142: data <= 142;
143: data <= 143;
144: data <= 144;
145: data <= 145;
146: data <= 146;
147: data <= 147;
148: data <= 148;
149: data <= 149;
150: data <= 150;
151: data <= 151;
152: data <= 144;
153: data <= 153;
154: data <= 154;
155: data <= 155;
156: data <= 156;
157: data <= 157;
158: data <= 158;
159: data <= 159;
160: data <= 160;
161: data <= 161;
162: data <= 162;
163: data <= 163;
164: data <= 164;
165: data <= 165;
166: data <= 166;
167: data <= 167;
168: data <= 168;
169: data <= 169;
170: data <= 170;
171: data <= 171;
172: data <= 172;
173: data <= 173;
174: data <= 174;
175: data <= 175;
176: data <= 176;
177: data <= 177;
178: data <= 178;
179: data <= 179;
180: data <= 180;
181: data <= 181;
182: data <= 182;
183: data <= 183;
184: data <= 176;
185: data <= 185;
186: data <= 186;
187: data <= 187;
188: data <= 188;
189: data <= 189;
190: data <= 190;
191: data <= 191;
192: data <= 192;
193: data <= 193;
194: data <= 194;
195: data <= 195;
196: data <= 196;
197: data <= 197;
198: data <= 198;
199: data <= 199;
200: data <= 200;
201: data <= 201;
202: data <= 202;
203: data <= 203;
204: data <= 204;
205: data <= 205;
206: data <= 206;
207: data <= 207;
208: data <= 208;
209: data <= 209;
210: data <= 210;
211: data <= 211;
212: data <= 212;
213: data <= 213;
214: data <= 214;
215: data <= 215;
216: data <= 208;
217: data <= 217;
218: data <= 218;
219: data <= 219;
220: data <= 220;
221: data <= 221;
222: data <= 222;
223: data <= 223;
224: data <= 224;
225: data <= 225;
226: data <= 226;
227: data <= 227;
228: data <= 228;
229: data <= 229;
230: data <= 230;
231: data <= 231;
232: data <= 232;
233: data <= 233;
234: data <= 234;
235: data <= 235;
236: data <= 236;
237: data <= 237;
238: data <= 238;
239: data <= 239;
240: data <= 240;
241: data <= 241;
242: data <= 242;
243: data <= 243;
244: data <= 244;
245: data <= 245;
246: data <= 246;
247: data <= 247;
248: data <= 240;
249: data <= 249;
250: data <= 250;
251: data <= 251;
252: data <= 252;
253: data <= 253;
254: data <= 254;
255: data <= 255;
endcase
end
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: I2C_CCD_Config
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module I2C_CCD_Config ( // Host Side
iCLK,
iRST_N,
iZOOM_MODE_SW,
iEXPOSURE_ADJ,
iEXPOSURE_DEC_p,
// I2C Side
I2C_SCLK,
I2C_SDAT
);
// Host Side
input iCLK;
input iRST_N;
input iZOOM_MODE_SW;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [31:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [23:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
////////////// CMOS sensor registers setting //////////////////////
input iEXPOSURE_ADJ;
input iEXPOSURE_DEC_p;
// parameter default_exposure = 16'h07c0;
parameter default_exposure = 16'h0797;
parameter exposure_change_value = 16'd50;
reg [24:0] combo_cnt;
wire combo_pulse;
reg [1:0] izoom_mode_sw_delay;
reg [3:0] iexposure_adj_delay;
wire exposure_adj_set;
wire exposure_adj_reset;
reg [15:0] senosr_exposure;
wire [17:0] senosr_exposure_temp;
wire [23:0] sensor_start_row;
wire [23:0] sensor_start_column;
wire [23:0] sensor_row_size;
wire [23:0] sensor_column_size;
wire [23:0] sensor_row_mode;
wire [23:0] sensor_column_mode;
//assign sensor_start_row = iZOOM_MODE_SW ? 24'h01029A : 24'h010132;
//assign sensor_start_column = iZOOM_MODE_SW ? 24'h0202A0 : 24'h020020;
assign sensor_start_row = iZOOM_MODE_SW ? 24'h010036 : 24'h010000;
assign sensor_start_column = iZOOM_MODE_SW ? 24'h020210 : 24'h020000;
assign sensor_row_size = iZOOM_MODE_SW ? 24'h0303BF : 24'h03077F;
assign sensor_column_size = iZOOM_MODE_SW ? 24'h0404FF : 24'h0409FF;
assign sensor_row_mode = iZOOM_MODE_SW ? 24'h220000 : 24'h220011;
assign sensor_column_mode = iZOOM_MODE_SW ? 24'h230000 : 24'h230011;
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
begin
iexposure_adj_delay <= 0;
end
else
begin
iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};
end
end
assign exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
assign exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;
assign senosr_exposure_temp = iEXPOSURE_DEC_p ? (senosr_exposure - exposure_change_value) : (senosr_exposure + exposure_change_value);
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
senosr_exposure <= default_exposure;
else if (exposure_adj_set|combo_pulse)
if (senosr_exposure_temp[17])
senosr_exposure <= 0;
else if (senosr_exposure_temp[16])
senosr_exposure <= 16'hffff;
else
senosr_exposure <= senosr_exposure_temp[15:0];
end
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
combo_cnt <= 0;
else if (!iexposure_adj_delay[3])
combo_cnt <= combo_cnt + 1;
else
combo_cnt <= 0;
end
assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;
wire i2c_reset;
assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
/////////////////////////////////////////////////////////////////////
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 25;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(i2c_reset)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'hBA,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
0 : LUT_DATA <= 24'h000000;
1 : LUT_DATA <= 24'h20c000; // Mirror Row and Columns
2 : LUT_DATA <= {8'h09,senosr_exposure};// Exposure
3 : LUT_DATA <= 24'h050000; // H_Blanking
4 : LUT_DATA <= 24'h060019; // V_Blanking
5 : LUT_DATA <= 24'h0A8000; // change latch
// 6 : LUT_DATA <= 24'h2B0013; // Green 1 Gain
6 : LUT_DATA <= 24'h2B000B; // Green 1 Gain
// 7 : LUT_DATA <= 24'h2C001A; // Blue Gain
7 : LUT_DATA <= 24'h2C0010; // Blue Gain
// 8 : LUT_DATA <= 24'h2D011C; // Red Gain
8 : LUT_DATA <= 24'h2D000C; // Red Gain
// 9 : LUT_DATA <= 24'h2E0013; // Green 2 Gain
9 : LUT_DATA <= 24'h2E000B; // Green 2 Gain
10 : LUT_DATA <= 24'h100051; // set up PLL power on
11 : LUT_DATA <= 24'h111805; // PLL_m_Factor<<8+PLL_n_Divider
12 : LUT_DATA <= 24'h120003; // PLL_p1_Divider
13 : LUT_DATA <= 24'h100053; // set USE PLL
14 : LUT_DATA <= 24'h980000; // disble calibration
15 : LUT_DATA <= 24'hA00000; // Test pattern control
16 : LUT_DATA <= 24'hA10000; // Test green pattern value
17 : LUT_DATA <= 24'hA20FFF; // Test red pattern value
18 : LUT_DATA <= sensor_start_row ; // set start row
19 : LUT_DATA <= sensor_start_column ; // set start column
20 : LUT_DATA <= sensor_row_size; // set row size
21 : LUT_DATA <= sensor_column_size; // set column size
22 : LUT_DATA <= sensor_row_mode; // set row mode in bin mode
23 : LUT_DATA <= sensor_column_mode; // set column mode in bin mode
24 : LUT_DATA <= 24'h4901A8; // row black target
default:LUT_DATA <= 24'h000000;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long i, j, k; int n; cin >> n; vector<int> arr(n); int f, l; f = 1; l = n; int sz = 0; while (sz < n) { if (sz % 2 == 0) { arr[sz] = f; sz++; f++; } else { arr[sz] = l; sz++; l--; } } for (auto it : arr) { cout << it << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void pr(vector<T> &v) { for (int i = 0; i < (int)(v).size(); i++) cout << v[i] << ; cout << n ; ; } template <typename T> void pr(vector<vector<T>> &v) { for (int i = 0; i < (int)(v).size(); i++) { pr(v[i]); } } template <typename T> void re(T &x) { cin >> x; } template <typename T> void re(vector<T> &a) { for (int i = 0; i < (int)(a).size(); i++) re(a[i]); } template <class Arg, class... Args> void re(Arg &first, Args &...rest) { re(first); re(rest...); } template <typename T> void pr(T x) { cout << x << n ; ; } template <class Arg, class... Args> void pr(const Arg &first, const Args &...rest) { cout << first << ; pr(rest...); cout << n ; ; } void ps() { cout << n ; ; } template <class T, class... Ts> void ps(const T &t, const Ts &...ts) { cout << t; if (sizeof...(ts)) cout << ; ps(ts...); } const long long MOD = 998244353; long double PI = 4 * atan(1); long double eps = 1e-12; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, A, cf, cm, m; cin >> n >> A >> cf >> cm >> m; vector<pair<long long, int>> a(n + 1); for (int i = 1; i < n + 1; i++) { cin >> a[i].first; a[i].second = i; } vector<long long> pre(n + 1); vector<long long> pre2(n + 1); sort(a.begin(), a.end()); vector<long long> ac(n); long long minv = MOD; for (int i = 0; i < n; i++) { ac[i] = a[i + 1].first; minv = min(minv, ac[i]); } pre[0] = 0; pre2[0] = 0; for (int i = 1; i < n + 1; i++) { pre[i] = a[n - i + 1].first + pre[i - 1]; pre2[i] = a[i].first + pre2[i - 1]; } long long ans = cm * minv; long long ind = 0; long long besti = 0; long long bestm = 0; for (int i = 0; i < n + 1; i++) { long long cost = (i)*A - pre[i]; if (cost > m) { break; } long long lo = 0; long long hi = A; while (lo != hi) { long long mid = (lo + hi + 1) / 2; vector<long long>::iterator high = upper_bound(ac.begin(), ac.begin() + n - i, mid); long long ntm = high - ac.begin(); long long cost2 = cost + (mid * ntm - pre2[ntm]); if (cost2 <= m) { if (i * cf + cm * mid > ans) { ans = i * cf + cm * mid; besti = i; bestm = mid; } lo = mid; } else { hi = mid - 1; } } } for (int i = 0; i < besti; i++) { a[n - i].first = A; } for (int i = 1; i < n + 1; i++) { if (a[i].first < bestm) a[i].first = bestm; } vector<long long> out(n + 1); for (int i = 1; i < n + 1; i++) { out[a[i].second] = a[i].first; } cout << ans << n ; ; for (int i = 1; i < n + 1; i++) { cout << out[i] << ; } cout << n ; ; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_144x128.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_144x128 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [143:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [143:0] sub_wire3;
wire sub_wire4;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [143:0] q = sub_wire3[143:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 56,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "56"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "56"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL "data[143..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL "q[143..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL "usedw[6..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x128_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int dx[4] = {1, -1, 0, 0}; const int dy[4] = {0, 0, 1, -1}; int read() { int s = 0; char c = getchar(), lc = + ; while (c < 0 || 9 < c) lc = c, c = getchar(); while ( 0 <= c && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return lc == - ? -s : s; } void write(int x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 0 ); else write(x / 10), putchar(x % 10 + 0 ); } void print(int x, char c = n ) { write(x); putchar(c); } void error() { puts( -1 ), exit(0); } pair<int, int> q[N]; int dis[N], tot[N], tt, a[N]; int id(int n, int m, int x, int y) { return (x - 1) * m + y; } void check(int n, int m, int x, int y) { if (x > n || y > m) return; for (int i = 1; i <= tt; i++) dis[i] = -1, tot[i] = 0; dis[id(n, m, x, y)] = 0; int h = 1, t = 1; q[1] = make_pair(x, y); while (h <= t) { int x = q[h].first, y = q[h++].second; for (int i = 0; i < 4; i++) if (1 <= x + dx[i] && x + dx[i] <= n) if (1 <= y + dy[i] && y + dy[i] <= m) if (!~dis[id(n, m, x + dx[i], y + dy[i])]) { dis[id(n, m, x + dx[i], y + dy[i])] = dis[id(n, m, x, y)] + 1; q[++t] = make_pair(x + dx[i], y + dy[i]); } } for (int i = 1; i <= tt; i++) tot[dis[i]]++; for (int i = 1; i <= tt; i++) if (tot[i] != a[i]) return; print(n, ), print(m); print(x, ), print(y); exit(0); } signed main(signed Recall, char *_902_[]) { (void)Recall, (void)_902_; tt = read(); for (int i = 1; i <= tt; i++) a[read()]++; int x = 0, mx = 0; for (int i = 0; i <= tt; i++) if (a[i]) mx = i; for (int i = 0; i <= tt; i++) { if (a[i] > i * 4 + !i) error(); if (a[i] < i * 4 + !i) { x = i; break; } } if (x == 0) error(); for (int i = 1; i <= tt; i++) if (tt % i == 0) check(i, tt / i, x, i + tt / i - x - mx); puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[105], b[105], c[105], tot, ans; char s[105]; int main() { scanf( %d , &n); scanf( %s , s + 1); for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i], &b[i]); c[i] = s[i] - 0 ; if (c[i] == 1) tot++; } ans = tot; for (int i = 1; i <= 125; i++) { for (int j = 1; j <= n; j++) { if (i < b[j]) continue; int k = i - b[j]; if (k % a[j] != 0) continue; tot -= c[j]; c[j] ^= 1; tot += c[j]; } ans = max(ans, tot); } printf( %d n , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_ground_hvc_wpad ( G_PAD, AMUXBUS_A, AMUXBUS_B
);
inout G_PAD;
inout AMUXBUS_A;
inout AMUXBUS_B;
supply1 ogc_hvc;
supply1 drn_hvc;
supply0 src_bdy_hvc;
supply0 g_core;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply1 vpb;
supply1 vpbhib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
assign g_core = G_PAD;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int count = 1; a[0] = 0; a[1] = 2; for (int i = 2; i < n; i++) { count++; a[i] = a[i - 1] + count; if (a[i] > n) { int rem = a[i] - n; a[i] = a[0] + rem; } } for (int i = 1; i < n; i++) cout << a[i] << ; return 0; }
|
module aaa (/*AUTOARG*/
// Outputs
y1, y0,
// Inputs
y3, y2
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output y0; // From bbb of bbb.v
output y1; // From bbb of bbb.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input y2; // To bbb of bbb.v
input y3; // To bbb of bbb.v
// End of automatics
/*AUTOWIRE*/
wire u0, u1, z0, z1;
/*
bbb AUTO_TEMPLATE (
.xo0 ({(u0), y0}),
.xo1 ({y1, (u1)}),
.xi0 ({(z0), y2}),
.xi1 ({y3, (z1)}),
);
*/
bbb bbb (/*AUTOINST*/
// Outputs
.xo0 ({(u0), y0}), // Templated
.xo1 ({y1, (u1)}), // Templated
// Inputs
.xi0 ({(z0), y2}), // Templated
.xi1 ({y3, (z1)})); // Templated
endmodule // aaa
module bbb (/*AUTOARG*/
// Outputs
xo0, xo1,
// Inputs
xi0, xi1
);
output [1:0] xo0, xo1;
input [1:0] xi0, xi1;
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire [1:0] xo0 = 2'h0;
wire [1:0] xo1 = 2'h0;
// End of automatics
endmodule // bbb
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5, INF = -1e9; long long down[N], mx[N], up[N], dp[N], sum[N]; unordered_map<long long, vector<long long>> mp[N]; long long n, m, pre[N], suf[N], ans[N]; vector<pair<long long, long long>> adj[N]; bool mark[N]; void dfs_down(long long u, long long par) { down[u] = up[u] = mark[u] ? 0 : INF; for (auto x : adj[u]) { long long v = x.first, w = x.second; if (v == par) continue; dfs_down(v, u); mp[u][down[v] + w].push_back(v); down[u] = max(down[u], down[v] + w); } pre[0] = suf[adj[u].size() - 1] = INF; for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i].first, w = adj[u][i].second; pre[i + 1] = v ^ par ? max(pre[i], down[v] + w) : pre[i]; } for (long long i = adj[u].size() - 1; i; i--) { long long v = adj[u][i].first, w = adj[u][i].second; suf[i - 1] = v ^ par ? max(suf[i], down[v] + w) : suf[i]; } for (long long i = 0; i < adj[u].size(); i++) if (adj[u][i].first ^ par) mx[adj[u][i].first] = max(suf[i], pre[i]); } void dfs_up(long long u, long long par) { for (auto x : adj[u]) { long long v = x.first, w = x.second; if (v == par) continue; up[v] = max(up[v], max(up[u], mx[v]) + w); dfs_up(v, u); } } void dfs1(long long u, long long par) { if (mark[u] && up[u] > down[u]) dp[u]++; for (auto x : adj[u]) { long long v = x.first, w = x.second; if (v == par) continue; dfs1(v, u); ans[u] += dp[v]; if (up[u] > mx[v]) dp[u] += dp[v]; if (up[u] < mx[v]) { long long sz = mp[u][mx[v]].size(); if (down[v] + w == mx[v]) sz--; if (sz ^ 1) continue; for (long long s : mp[u][mx[v]]) if (s ^ v) sum[s] += dp[v]; } } } void dfs2(long long u, long long par) { if (mark[u] && down[u] > up[u]) sum[u]++; if (mp[u][down[u]].size() == 1) sum[mp[u][down[u]][0]] += sum[u]; for (auto x : adj[u]) if (x.first ^ par) dfs2(x.first, u); ans[u] += sum[u]; } inline void read_input() { cin >> n >> m; for (long long i = 0; i < m; i++) { long long v; cin >> v; mark[--v] = true; } for (long long i = 1; i < n; i++) { long long u, v, w; cin >> u >> v >> w; adj[--u].push_back({--v, w}); adj[v].push_back({u, w}); } } inline void solve() { dfs_down(0, 0); dfs_up(0, 0); dfs1(0, 0); dfs2(0, 0); } inline void write_output() { long long mx = 0, cnt = 0; for (long long u = 0; u < n; u++) { if (mark[u]) continue; if (mx < ans[u]) { mx = ans[u]; cnt = 0; } if (mx == ans[u]) cnt++; } cout << mx << << cnt << endl; } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); read_input(), solve(), write_output(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; vector<int> w, cn, c, d, p; vector<bool> used; int find(int x) { return (p[x] == x ? x : p[x] = find(p[x])); } void un(int x, int y) { x = find(x); y = find(y); if (rand() & 1) p[x] = y; else p[y] = x; } int main() { int n, m; scanf( %d %d , &n, &m); used.resize(n, false); cn.resize(n + 1, 0); p.resize(n); for (int i = 0; i < n; ++i) p[i] = i; int a, b, comp = n; for (int i = 0; i < m; ++i) { scanf( %d%d , &a, &b); a--; b--; if (find(a) != find(b)) un(a, b), comp--; } for (int i = 0; i < n; ++i) cn[find(p[i])]++; for (int i = 0; i < n; ++i) if (cn[i] > 0) c.push_back(cn[i]); cn.assign(n + 1, 0); for (int i = 0; i < c.size(); ++i) ++cn[c[i]]; c.clear(); for (int i = 0; i < cn.size(); ++i) if (cn[i] > 0) { int st = 1; while (cn[i] >= st) { c.push_back(st); w.push_back(st * i); cn[i] -= st; st *= 2; } if (cn[i] > 0) { c.push_back(cn[i]); w.push_back(cn[i] * i); } } int N = c.size(); d.resize(n + 1, INF); d[0] = 0; for (int i = 1; i <= N; ++i) for (int j = n; j >= w[i - 1]; --j) if (d[j - w[i - 1]] + c[i - 1] < d[j]) d[j] = d[j - w[i - 1]] + c[i - 1]; int ans = INF, tmp; for (int i = 4; i <= n; ++i) { if (ans <= d[i]) continue; tmp = i; bool good = true; while (tmp > 0 && good) { if (!(tmp % 10 == 4 || tmp % 10 == 7)) good = false; tmp /= 10; } if (good) ans = d[i]; } printf( %d , (ans < INF ? ans - 1 : -1)); return 0; }
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_descramble
*/
module test_lfsr_descramble;
// Parameters
parameter LFSR_WIDTH = 58;
parameter LFSR_POLY = 58'h8000000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 1;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_descramble.lxt");
$dumpvars(0, test_lfsr_descramble);
end
lfsr_descramble #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int M = 1e9 + 7; int n; double v, v2, a[N], b[N]; double x, y; int id = 1; int main() { ios_base ::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> v >> v2; for (int i = 0; i < n; ++i) { cin >> b[i]; a[i] = 1.0 * b[i] / v; } cin >> x >> y; for (int i = 1; i < n; ++i) { a[i] = a[i] + sqrt((b[i] - x) * (b[i] - x) + y * y) / v2; if (a[i] <= a[id]) { id = i; } } cout << id + 1 << n ; return 0; }
|
#include <bits/stdc++.h> const int mo = 1000000007, x[9][9] = {{0, 0, 0, 0, 1, 1, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 1, 1, 1}, {0, 0, 0, 0, 1, 1, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 1, 1, 1}, {1, 0, 0, 0, 0, 0, 0, 0, 1}, {0, 0, 1, 1, 0, 0, 0, 0, 1}, {0, 1, 0, 0, 0, 0, 0, 0, 1}, {0, 0, 1, 1, 0, 0, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 0, 0, 1}}; int a[9], t[9], b[9][9], c[9][9], l, r, ans; void mul(int a[][9], int b[][9], int c[][9]) { int i, j, k; for (i = 0; i <= 8; ++i) for (j = 0; j <= 8; ++j) { c[i][j] = 0; for (k = 0; k <= 8; ++k) c[i][j] = (c[i][j] + (long long)a[i][k] * b[k][j]) % mo; } } int calc(int n) { if (!n) return 0; int i, j, v; for (i = 0; i <= 8; ++i) a[i] = 1; a[8] = 4; memcpy(b, x, sizeof x); --n; while (n) { if (n % 2) { for (i = 0; i <= 8; ++i) { t[i] = 0; for (j = 0; j <= 8; ++j) t[i] = (t[i] + (long long)a[j] * b[j][i]) % mo; } memcpy(a, t, sizeof t); } mul(b, b, c); memcpy(b, c, sizeof c); memcpy(c, t, sizeof t); n /= 2; } return a[8]; } int query(int n) { return (calc(n) + calc((n + 1) / 2)) % mo; } int main() { scanf( %d%d , &l, &r); ans = ((long long)(query(r) - query(l - 1)) * ((mo + 1) / 2) % mo + mo) % mo; printf( %d n , ans); return 0; }
|
module spwm
#(parameter cwidth=32,
parameter kwidth=10)
(input clk,
input rstn,
input [cwidth-1:0] d_init,
input [cwidth-1:0] d_delta,
input [cwidth-1:0] d_pwm,
input [kwidth-1:0] k_max,
input updown,
input d0_level,
input clr_it,
output reg io,
output it);
reg [kwidth-1:0] k_curr;
wire [kwidth-1:0] k_next;
wire [cwidth-1:0] d_curr;
reg [cwidth-1:0] d0;
wire [cwidth-1:0] d0_next;
wire [cwidth-1:0] d0_prev;
reg up;
wire up_next;
wire d1_level;
assign k_next = k_curr + {{kwidth-1{1'b0}}, 1'b1};
assign d0_next = d0 + d_delta;
assign d0_prev = d0 - d_delta;
assign d1_level = d0_level ^ 1'b1;
assign up_next = up ^ updown;
cnt #(.width(cwidth)) cntD(.clk(clk),
.top(d_pwm), .rstn(rstn), .clr_it(clr_it), .start(1'b1), .freerun(1'b1),
.cnt(d_curr),
.it(it));
always @(posedge clk, negedge rstn) begin
if (~rstn) begin
io <= d0_level;
d0 <= d_init;
k_curr <= 0;
up <= 1;
end else begin
if (d_curr == d0)
io <= d1_level;
if (d_curr == d_pwm) begin
io <= d0_level;
if (k_curr == k_max) begin
if (up_next)
d0 <= d_init;
else
d0 <= d0_prev;
up <= up_next;
k_curr <= 0;
end else begin
if (up)
d0 <= d0_next;
else
d0 <= d0_prev;
k_curr <= k_next;
end
end
end
end
endmodule
module spwm_de0nano(sys_clk, rstn, leds);
input sys_clk;
input rstn;
output [7:0] leds;
assign leds[7:6] = 2'd0;
localparam d_init = 32'd0;
localparam d_delta = 32'd2500;
localparam d_pwm = 32'd500000;
localparam k_max = 32'd200;
spwm spwmI0(.clk(sys_clk),
.rstn(rstn),
.d_init(d_init),
.d_delta(d_delta),
.d_pwm(d_pwm),
.k_max(k_max),
.updown(1'b0),
.d0_level(1'b0),
.io(leds[0]),
.clr_it(rstn));
spwm spwmI1(.clk(sys_clk),
.rstn(rstn),
.d_init(d_init),
.d_delta(d_delta),
.d_pwm(d_pwm),
.k_max(k_max),
.updown(1'b0),
.d0_level(1'b1),
.io(leds[1]),
.clr_it(rstn));
spwm spwmI2(.clk(sys_clk),
.rstn(rstn),
.d_init(d_init),
.d_delta(d_delta),
.d_pwm(d_pwm),
.k_max(k_max),
.updown(1'b1),
.d0_level(1'b0),
.io(leds[2]),
.clr_it(rstn));
spwm spwmI3(.clk(sys_clk),
.rstn(rstn),
.d_init(32'd25000000),
.d_delta(32'd0),
.d_pwm(32'd50000000),
.k_max(32'd1),
.updown(1'b0),
.d0_level(1'b0),
.io(leds[3]),
.clr_it(rstn));
spwm spwmI4(.clk(sys_clk),
.rstn(rstn),
.d_init(32'd1000),
.d_delta(32'd0),
.d_pwm(32'd5000),
.k_max(32'd1),
.updown(1'b0),
.d0_level(1'b1),
.io(leds[4]),
.clr_it(rstn));
spwm spwmI5(.clk(sys_clk),
.rstn(rstn),
.d_init(32'd3000),
.d_delta(32'd0),
.d_pwm(32'd5000),
.k_max(32'd1),
.updown(1'b0),
.d0_level(1'b1),
.io(leds[5]),
.clr_it(rstn));
endmodule
module spwm_sim;
wire sys_clk;
sim_clk simClk(sys_clk);
reg rstn;
initial begin
rstn = 0;
#2 rstn = 1;
end
wire [1:0] leds;
localparam d_init = 0;
localparam d_delta = 5;
localparam d_pwm = 50;
localparam k_max = 10;
localparam updown = 1'b1;
localparam d0_level = 0;
spwm spwmI0(.clk(sys_clk),
.rstn(rstn),
.d_init(d_init),
.d_delta(d_delta),
.d_pwm(d_pwm),
.k_max(k_max),
.updown(updown),
.d0_level(d0_level),
.io(leds[0]));
spwm spwmI1(.clk(sys_clk),
.rstn(rstn),
.d_init(50),
.d_delta(0),
.d_pwm(100),
.k_max(1),
.updown(1'b0),
.d0_level(d0_level),
.io(leds[1]));
initial begin
$dumpfile(`VCD_PATH);
$dumpvars();
// $monitor("T=%t, i=%0d", $time, clk);
#5000 $finish;
end
endmodule
|
/*
* File: pippo_div64x32.v
* Project: pippo
* Designer:
* Mainteiner:
* Checker:
* Description: implmentation of 32/32 divider
Currently, the implementation signed-extend the 32-bit divident to 64 bit, then divide
using non-restoring algorithm: Detailed algorithm see [Computer Arithmetic - Algorithms and Hardware designs] chapter 13
* Task.I
[TBD]the overflow definition of powerpc divide instructions?
currently, the overflow defined by textbooks can't happen - just signed-extend of the 32-bit divident
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module pippo_div64x32 (
clk, ena,
z, d, q, s,
ovf, div0
);
//
// parameters
//
parameter z_width = 64;
parameter d_width = z_width /2;
//
// i/o
//
input clk;
input ena;
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width :0] s; // remainder
output ovf;
output div0;
//
// regs & wires
//
reg [d_width:0] q, s;
reg ovf, div0;
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] szpipe, sdpipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// rtl
//
// check sign bit, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= ~z +1'h1;
else
iz <= z;
always @(posedge clk)
if (ena)
if (d[d_width-1])
id <= ~d +1'h1;
else
id <= d;
pippo_div_uu #(z_width, d_width) divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
//
// adjust sign bit of results
// [TBD] to eliminate the redundant pipelined register for sign bit
// generate szpipe (z sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
szpipe[0] <= z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
szpipe[n] <= szpipe[n-1];
end
// generate sdpipe (d sign bit pipe)
integer m;
always @(posedge clk)
if(ena)
begin
sdpipe[0] <= d[d_width-1];
for(m=1; m <= d_width+1; m=m+1)
sdpipe[m] <= sdpipe[m-1];
end
always @(posedge clk) begin
if(ena)
begin
q <= (szpipe[d_width+1]^sdpipe[d_width+1]) ?
((~iq) + 1'h1) : ({1'b0, iq});
s <= (szpipe[d_width+1]) ?
((~is) + 1'h1) : ({1'b0, is});
end
end
// delay flags same as results
always @(posedge clk) begin
if(ena)
begin
ovf <= iovf;
div0 <= idiv0;
end
end
endmodule
|
// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $
//
// AEMB BRANCH PROGRAMME COUNTER UNIT
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_bpcu.v,v $
// Revision 1.4 2007/11/14 22:14:34 sybreon
// Changed interrupt handling system (reported by M. Ettus).
//
// Revision 1.3 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
//
// Revision 1.1 2007/11/02 03:25:39 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
module aeMB_bpcu (/*AUTOARG*/
// Outputs
iwb_adr_o, rPC, rPCLNK, rBRA, rDLY,
// Inputs
rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena
);
parameter IW = 24;
// INST WISHBONE
output [IW-1:2] iwb_adr_o;
// INTERNAL
output [31:2] rPC, rPCLNK;
output rBRA;
output rDLY;
//output [1:0] rATOM;
//output [1:0] xATOM;
input [1:0] rMXALT;
input [5:0] rOPC;
input [4:0] rRD, rRA;
input [31:0] rRESULT; // ALU
input [31:0] rDWBDI; // RAM
input [31:0] rREGA;
//input [1:0] rXCE;
// SYSTEM
input gclk, grst, gena;
// --- BRANCH CONTROL --------------------------------------------
// Controls the branch and delay flags
wire fRTD = (rOPC == 6'o55);
wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
wire [31:0] wREGA;
assign wREGA = (rMXALT == 2'o2) ? rDWBDI :
(rMXALT == 2'o1) ? rRESULT :
rREGA;
wire wBEQ = (wREGA == 32'd0);
wire wBNE = ~wBEQ;
wire wBLT = wREGA[31];
wire wBLE = wBLT | wBEQ;
wire wBGE = ~wBLT;
wire wBGT = ~wBLE;
reg xXCC;
always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT
or wBNE)
case (rRD[2:0])
3'o0: xXCC <= wBEQ;
3'o1: xXCC <= wBNE;
3'o2: xXCC <= wBLT;
3'o3: xXCC <= wBLE;
3'o4: xXCC <= wBGT;
3'o5: xXCC <= wBGE;
default: xXCC <= 1'bX;
endcase // case (rRD[2:0])
reg rBRA, xBRA;
reg rDLY, xDLY;
wire fSKIP = rBRA & !rDLY;
always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
or xXCC)
//if (rBRA | |rXCE) begin
if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xBRA <= 1'h0;
xDLY <= 1'h0;
// End of automatics
end else begin
xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;
xBRA <= (fRTD | fBRU) ? 1'b1 :
(fBCC) ? xXCC :
1'b0;
end
// --- PC PIPELINE ------------------------------------------------
// PC and related changes
reg [31:2] rIPC, xIPC;
reg [31:2] rPC, xPC;
reg [31:2] rPCLNK, xPCLNK;
assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB
always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin
//xPCLNK <= (^rATOM) ? rPC : rPC;
xPCLNK <= rPC;
//xPC <= (^rATOM) ? rIPC : rRESULT[31:2];
xPC <= rIPC;
//xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
/*
case (rXCE)
2'o1: xIPC <= 30'h2;
2'o2: xIPC <= 30'h4;
2'o3: xIPC <= 30'h6;
default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
endcase // case (rXCE)
*/
xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
end
// --- ATOMIC CONTROL ---------------------------------------------
// This is used to indicate 'safe' instruction borders.
wire wIMM = (rOPC == 6'o54) & !fSKIP;
wire wRTD = (rOPC == 6'o55) & !fSKIP;
wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP;
wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP;
wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA);
reg [1:0] rATOM, xATOM;
always @(/*AUTOSENSE*/fATOM or rATOM)
xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)};
// --- SYNC PIPELINE ----------------------------------------------
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rATOM <= 2'h0;
rBRA <= 1'h0;
rDLY <= 1'h0;
// rIPC <= 30'h0;
rIPC <= 30'h3fffffff; // DWORD aligned address
rPC <= 30'h0;
rPCLNK <= 30'h0;
// End of automatics
end else if (gena) begin
rIPC <= #1 xIPC;
rBRA <= #1 xBRA;
rPC <= #1 xPC;
rPCLNK <= #1 xPCLNK;
rDLY <= #1 xDLY;
rATOM <= #1 xATOM;
end
endmodule // aeMB_bpcu
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int inf = 2e9 + 5; const int N = 1e5; int cost[26]; map<long long, long long> m[26]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); for (int i = 0; i < 26; i++) cin >> cost[i]; string s; cin >> s; long long n = s.length(), sum = 0; long long ans = 0; for (int i = 0; i < n; i++) { ans += m[s[i] - a ][sum]; sum += cost[s[i] - a ]; m[s[i] - a ][sum] += 1; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, x, sum; vector<long long> my, temp; int main() { ios::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; for (long long i = 0; i < n; i++) { cin >> x; my.push_back(x); temp.push_back(x); } for (long long i = 0; i < n; i++) my.push_back(temp[i]); long long maxi = 0; for (long long i = 0; i < my.size(); i++) { if (my[i] == 1) { sum++; maxi = max(maxi, sum); } else sum = 0; } cout << maxi << endl; return 0; }
|
`include "assert.vh"
module genrom_tb();
parameter AW = 4;
parameter DW = 8;
parameter EXTRA = 4;
reg clk = 0;
logic[ AW:0] addr;
logic[ EXTRA-1:0] extra;
logic[ AW:0] lower_bound=0;
logic[ AW:0] upper_bound=9;
wire [DW*2**EXTRA-1:0] data;
wire error;
genrom #(
.AW(AW),
.DW(DW),
.ROMFILE("genrom.hex")
)
dut(
.clk(clk),
.addr(addr),
.extra(extra),
.lower_bound(lower_bound),
.upper_bound(upper_bound),
.data(data),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("genrom_tb.vcd");
$dumpvars(0, genrom_tb);
addr <= 0;
extra <= 0;
#2
`assert(error, 0);
`assert(data , 128'h81);
addr <= 1;
extra <= 1;
#2
`assert(error, 0);
`assert(data , 128'h0082);
addr <= 3;
extra <= 3;
#2
`assert(error, 0);
`assert(data , 128'h00840088);
addr <= 0;
extra <= 4;
#2
`assert(error, 0);
`assert(data , 128'h8100820084);
addr <= 0;
extra <= 7;
#2
`assert(error, 0);
`assert(data , 128'h8100820084008800);
addr <= 0;
extra <= 15;
#2
`assert(error, 0);
`assert(data , 128'h81008200840088008140xxxxxxxxxxxx);
addr <= 9;
extra <= 0;
#2
`assert(error, 0);
addr <= 10;
extra <= 0;
#2
`assert(error, 1);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v1; int status[(100000007 / 32) + 10]; bool check1(int n, int pos) { return (bool)(n & (1 << pos)); } int set1(int n, int pos) { return n = n | (1 << pos); } void sieve() { int i, j, k; k = int(sqrt(100000007)); for (i = 3; i <= k; i += 2) { if (check1(status[i / 32], i % 32) == 0) { for (j = i * i; j <= 100000007; j += 2 * i) { status[j / 32] = set1(status[j / 32], j % 32); } } } v1.push_back(2); for (i = 3; i < 100000007; i += 2) { if (check1(status[i / 32], i % 32) == 0) v1.push_back(i); } } vector<long long int> v2; void factor(long long int k) { long long int i, a; v2.clear(); for (i = 0; i < v1.size(); i++) { if (k == 1) break; a = v1[i]; while (k % a == 0) { if (k == 1) break; v2.push_back(a); k /= a; } } if (k != 1) v2.push_back(k); } int main() { sieve(); long long int a, b, c, d, i, j, k, l, m, n; cin >> n; factor(n); if (v2.size() == 1 || v2.size() == 0) { cout << 1 << endl; cout << 0 << endl; return 0; } if (v2.size() == 2) { cout << 2 << endl; return 0; } cout << 1 << endl; cout << v2[0] * v2[1] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; struct Sync_stdio { Sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } } _sync_stdio; struct FAIL { FAIL() { cout << CHANGE!!! << n ; } }; string go(int iter, long long a, long long b, long long x) { string res; vector<int> used(26); for (int l = (0); l < (iter); ++l) { int j = 0; for (int i = (0); i < (a); ++i) { while (used[j]) { ++j; } res += a + j; ++j; } char sym = res[res.size() - x]; for (int i = (0); i < (b); ++i) { res += sym; } for (int i = (0); i < (26); ++i) { used[i] = 0; } for (int i = (0); i < (a); ++i) { used[res[res.size() - 1 - i] - a ] = 1; } } return res; } int solve(int a, int b, int l, int r, int x) { string s1 = go(10, a, b, x + 1); set<char> ss; for (int i = (l); i < (r + 1); ++i) { ss.insert(s1[i]); } return ss.size(); } int main() { long long a, b, l, r; cin >> a >> b >> l >> r; --l, --r; long long start = l / (a + b); long long end = r / (a + b); if (r - l > 6 * (a + b)) { cout << max(a + 1LL, a + a - b) << n ; return 0; } l -= start * (a + b); r -= start * (a + b); int res = INT_MAX; for (int i = (0); i < (a); ++i) { res = min(res, solve(a, b, l, r, i)); } cout << res; }
|
#include <bits/stdc++.h> const int N = 5e4 + 5; struct Point { int x, y, z, id; void input() { scanf( %d%d%d , &x, &y, &z); } } a[N]; int main() { std::map<std::pair<int, int>, std::vector<Point> > f; std::map<int, std::vector<Point> > g; std::vector<Point> h; int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { a[i].input(); a[i].id = i; f[std::pair<int, int>(a[i].x, a[i].y)].push_back(a[i]); } for (auto &p : f) { auto &v = p.second; std::sort(v.begin(), v.end(), [](const Point &a, const Point &b) { return a.z < b.z; }); if (v.size() & 1) g[v.back().x].push_back(v.back()), v.pop_back(); for (int i = 0; i < v.size(); i += 2) printf( %d %d n , v[i].id, v[i + 1].id); } for (auto &p : g) { auto &v = p.second; std::sort(v.begin(), v.end(), [](const Point &a, const Point &b) { return a.y < b.y; }); if (v.size() & 1) h.push_back(v.back()), v.pop_back(); for (int i = 0; i < v.size(); i += 2) printf( %d %d n , v[i].id, v[i + 1].id); } for (int i = 0; i < h.size(); i += 2) printf( %d %d n , h[i].id, h[i + 1].id); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } signed main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long maxai = 0; multiset<long long> a; for (long long i = 0; i < n; i++) { long long ai; cin >> ai; a.insert(ai); if (ai > maxai) maxai = ai; } while (maxai != 1 && a.size()) { long long br = 0; for (long long i = 1; i <= maxai / 2; i++) { if (maxai % i != 0) continue; for (long long k = 1; k < 1010; k++) { if (k * maxai / i > 1010) break; long long count = a.count(k * maxai / i); if (count) { br = 1; for (long long j = 0; j < count; j++) cout << k * maxai / i << ; a.erase(k * maxai / i); maxai = gcd(maxai, k * maxai / i); break; } } if (br) break; } if (!br) break; } for (multiset<long long>::iterator i = a.begin(); i != a.end(); i++) cout << *i << ; cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_2_V
`define SKY130_FD_SC_MS__O211AI_2_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int n, m, ROOT, head; bool vis[MAXN]; int depth[MAXN], deg[MAXN]; vector<int> adj[MAXN]; vector<int> c; stack<int> stk; pair<bool, vector<int> > independentSet() { set<pair<int, int> > s; vector<int> v; for (auto i = 0; i < (n); i++) s.insert(make_pair(deg[i], i)); while (!s.empty()) { int node = s.begin()->second; s.erase(s.begin()); if (vis[node]) continue; v.push_back(node); vis[node] = true; for (auto u : adj[node]) { if (vis[u]) continue; vis[u] = true; for (auto v : adj[u]) { if (v == u) continue; --deg[v]; s.insert(make_pair(deg[v], v)); } } } if (v.size() >= ROOT) return make_pair(true, v); else return make_pair(false, vector<int>{}); } void simpleCycle() { while (!stk.empty() && stk.top() != head) { c.push_back(stk.top()); stk.pop(); } c.push_back(head); reverse(c.begin(), c.end()); cout << 2 n << c.size() << n ; for (auto u : c) cout << u + 1 << ; exit(0); } void dfs(int node, int d) { if (depth[node] > 0) { if (d - depth[node] == ROOT) { head = node; simpleCycle(); } return; } depth[node] = d; stk.push(node); for (auto u : adj[node]) { dfs(u, d + 1); } stk.pop(); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (auto i = 0; i < (m); i++) { int u, v; cin >> u >> v; --u; --v; adj[u].push_back(v); adj[v].push_back(u); ++deg[u]; ++deg[v]; } ROOT = (int)sqrt(n); if (ROOT * ROOT < n) ++ROOT; auto is = independentSet(); if (is.first) { cout << 1 n ; for (auto i = 0; i < (ROOT); i++) cout << is.second[i] + 1 << ; exit(0); } else { dfs(0, 1); } }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:55:12 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_stub.v
// Design : ip_design_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[4:0],gpio2_io_i[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [4:0]gpio_io_i;
input [7:0]gpio2_io_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long mpow(long long x, long long y) { if (y == 0) return 1; if (y % 2) return x * mpow(x, y - 1) % MOD; long long h = mpow(x, y / 2); return h * h % MOD; } long long arr[111111]; int main() { int k; scanf( %d , &k); for (int i = 0; i < k; i++) scanf( %lld , arr + i); long long p = 2; for (int i = 0; i < k; i++) p = mpow(p, arr[i]); p = p * mpow(2, MOD - 2) % MOD; long long q = p; if (all_of(arr, arr + k, [&](long long i) { return i % 2; })) p = (p - 1 + MOD) % MOD; else p = (p + 1) % MOD; p = p * mpow(3, MOD - 2) % MOD; printf( %lld/%lld , p, q); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; char A[MAXN]; char B[MAXN]; int n; void open() { freopen( B.in , r , stdin); freopen( B.out , w , stdout); } void close() { fclose(stdin); fclose(stdout); } void init() { scanf( %s , A + 1); scanf( %s , B + 1); } bool equal(int l1, int r1, int l2, int r2) { int flag = 1; for (int i = 0, END = r1 - l1; i <= END; i++) if (A[i + l1] != B[i + l2]) { flag = 0; break; } if (flag) return true; else if ((r1 - l1 + 1) & 1) return false; int mid1 = (l1 + r1) / 2, mid2 = (l2 + r2) / 2; if (equal(l1, mid1, l2, mid2)) { if (equal(mid1 + 1, r1, mid2 + 1, r2)) return true; } if (equal(mid1 + 1, r1, l2, mid2)) { if (equal(l1, mid1, mid2 + 1, r2)) return true; } } int main() { init(); int n1 = strlen(A + 1), n2 = strlen(B + 1); if (n1 != n2) { printf( NO n ); } else { if (equal(1, n1, 1, n2)) printf( YES n ); else printf( NO n ); } close(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int S = 100009; vector<int> in[S]; vector<int> out[S]; bool viz[S]; int moa[S]; vector<int> topol; vector<int> rang[S]; void dfs(int a) { if (viz[a]) return; viz[a] = 1; for (auto u : out[a]) dfs(u); topol.push_back(a); } void sfd(int a, int c) { if (moa[a] != -1) return; moa[a] = c; for (auto u : in[a]) sfd(u, c); } int main() { memset(moa, -1, sizeof moa); int n, v; cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { scanf( %i , &v); if (v != 0) { in[i].push_back(j); out[j].push_back(i); } } } for (int i = 1; i <= n; i++) dfs(i); int r = 0, u; for (int i = n - 1; i > -1; i--) { u = topol[i]; if (moa[u] == -1) { sfd(u, r); r++; } } for (int i = 1; i <= n; i++) { if (moa[i] != moa[1]) { printf( NO ); return 0; } } printf( YES ); }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m; cin >> n >> m; ; int a[n + 1]; memset(a, 0, sizeof(a)); for (long long i = 0; i < m; i++) { long long t; cin >> t; ; for (long long j = t; j < n + 1; j++) { if (a[j] == 0) a[j] = t; } } for (long long i = 1; i < n + 1; i++) { cout << a[i] << ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_transition_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_transition_psl_logic.v"
`else
`endmodule // ovl_no_transition
`endif
|
#include <bits/stdc++.h> using namespace std; int N, K, A, B, Q, x, y, t, ans; int data[200010]; class segleaf { public: int s[2]; } seg[2000010]; void change(int x, int l, int r, int t, int delta) { if (l == r) { data[t] += delta; seg[x].s[0] = min(data[t], B); seg[x].s[1] = min(data[t], A); return; } int mid = (l + r) >> 1; if (t <= mid) change(x << 1, l, mid, t, delta); else change((x << 1) + 1, mid + 1, r, t, delta); seg[x].s[0] = seg[x << 1].s[0] + seg[(x << 1) + 1].s[0]; seg[x].s[1] = seg[x << 1].s[1] + seg[(x << 1) + 1].s[1]; } int ask(int x, int l, int r, int ll, int rr, int tt) { if (l == ll && r == rr) return seg[x].s[tt]; int mid = (l + r) >> 1; if (rr <= mid) return ask(x << 1, l, mid, ll, rr, tt); else if (ll > mid) return ask((x << 1) + 1, mid + 1, r, ll, rr, tt); else return ask(x << 1, l, mid, ll, mid, tt) + ask((x << 1) + 1, mid + 1, r, mid + 1, rr, tt); } int main() { scanf( %d%d%d%d%d , &N, &K, &A, &B, &Q); for (int i = 1; i <= Q; i++) { scanf( %d , &t); if (t == 1) { scanf( %d%d , &x, &y); change(1, 1, N, x, y); } else { scanf( %d , &x); ans = 0; if (x > 1) ans += ask(1, 1, N, 1, x - 1, 0); if (x + K <= N) ans += ask(1, 1, N, x + K, N, 1); printf( %d n , ans); } } }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline istream &operator>>(istream &s, vector<T> &v) { for (T &t : v) { s >> t; } return s; } template <typename T> inline ostream &operator<<(ostream &s, const vector<T> &v) { for (int i = 0; i < int(v.size()); ++i) { s << ( + !i) << v[i]; } return s; } template <typename T> inline T fromString(const string &s) { T res; istringstream iss(s); iss >> res; return res; }; template <typename T> inline string toString(const T &a) { ostringstream oss; oss << a; return oss.str(); }; const long long mod = 1000000007; const long long INF = 1e18; int main() { long long t; t = 1; cin >> t; while (t--) { long long n; cin >> n; char s[2][n]; for (int i = (0); i < (2); i++) { for (int j = (0); j < (n); j++) { cin >> s[i][j]; } } long long f = 0; for (int i = (0); i < (1); i++) { for (int j = (0); j < (n); j++) { if (s[i][j] == 1 && s[i + 1][j] == 1 ) { f = 1; } } } if (f) { cout << NO << n ; } else { cout << YES << n ; } } }
|
#include <bits/stdc++.h> using namespace std; long long a[105], ans, n; int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); ans += a[i] * i; } printf( %lld n , ans); return 0; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC
*/
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet[0])
);
assign tx_start_packet[1] = 1'b0;
end
endgenerate
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_1_V
`define SKY130_FD_SC_HDLL__NAND2_1_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_1_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010, mod = 998244353; inline int read() { int x = 0, f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= ch == - , ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return f ? -x : x; } int n, fa[maxn], dep[maxn], last = 1, chg, ans[maxn], al, seq[maxn], sl; set<int> s[maxn]; int main() { n = read(); for (int i = (2); i <= (n); i++) { dep[i] = dep[fa[i] = read() + 1] + 1; s[fa[i]].insert(i); if (dep[i] > dep[last]) last = i; } chg = last; while (chg != 1) { while (chg != 1 && s[fa[chg]].size() == 1) chg = fa[chg]; if (chg != 1) { int was = fa[chg]; set<int>::iterator hhh = s[was].find(chg); for (set<int>::iterator it = s[was].begin(); it != s[was].end(); it++) { int f = *it; if (f == chg) continue; s[f].insert(chg); fa[chg] = f; ans[++al] = chg - 1; s[was].erase(hhh); break; } } } for (int i = last; i; i = fa[i]) seq[++sl] = i - 1; for (int i = (n); i >= (1); i--) printf( %d , seq[i]); printf( n%d n , al); for (int i = (al); i >= (1); i--) printf( %d , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int cnt[N]; int n, k; int cut[N]; vector<pair<int, int> > arr; struct Sub { bool operator()(pair<int, pair<int, int> > a, pair<int, pair<int, int> > b) { if (a.first != b.first) return a.first < b.first; else return (cnt[a.second.second] / (a.second.first + 1)) < (cnt[b.second.second] / (b.second.first + 1)); } }; bool ForSort(pair<int, int> a, pair<int, int> b) { return a.first > b.first; } int main() { scanf( %d%d , &n, &k); int tx; for (int i = 1; i <= n; i++) scanf( %d , &tx), cnt[tx]++; for (int i = 1; i <= 200000; i++) if (cnt[i] > 0) arr.push_back({cnt[i], i}); sort(arr.begin(), arr.end(), ForSort); priority_queue<pair<int, pair<int, int> >, vector<pair<int, pair<int, int> > >, Sub> pq; int len = 1, ex = arr[0].first; cut[arr[0].second] = 1; cout << arr[0].second << ; pq.push(pair<int, pair<int, int> >(arr[0].first, pair<int, int>(1, arr[0].second))); int i = 1; pair<int, pair<int, int> > u = pair<int, pair<int, int> >(2, pair<int, int>(10, 1)); pair<int, pair<int, int> > v = pair<int, pair<int, int> >(2, pair<int, int>(4, 2)); while (len < k) { pair<int, pair<int, int> > u = pq.top(); if (i >= arr.size()) { if (cut[u.second.second] + 1 <= cnt[u.second.second]) { len++; cut[u.second.second] = u.second.first + 1; pq.pop(); cout << u.second.second << ; pq.push(pair<int, pair<int, int> >( cnt[u.second.second] / (u.second.first + 1), pair<int, int>(u.second.first + 1, u.second.second))); } else pq.pop(); } else { if (u.second.first + 1 <= cnt[u.second.second] && cnt[u.second.second] / (u.second.first + 1) > arr[i].first) { cut[u.second.second] = u.second.first + 1; cout << u.second.second << ; len++; pq.pop(); pq.push(pair<int, pair<int, int> >( cnt[u.second.second] / (u.second.first + 1), pair<int, int>(u.second.first + 1, u.second.second))); } else { ex = min(ex, arr[i].first); cut[arr[i].second] = 1; cout << arr[i].second << ; len++; pq.push(pair<int, pair<int, int> >(arr[i].first, pair<int, int>(1, arr[i].second))); i++; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.141592653589793238; const double EPS = 1e-6; void solve() { long long r, g, b, w; cin >> r >> g >> b >> w; long long total = r + g + b + w; long long odd = 0; odd = r % 2 + g % 2 + b % 2 + w % 2; long long col = r && g && b; if (odd <= 1 || odd == 4 || (odd == 3 && col)) cout << YES << endl; else cout << NO << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long tc; cin >> tc; while (tc--) { solve(); } return 0; }
|
/*
Module: snes_controller
Description: Fetches snes controller buttons
and returns them as an array of 12 stored in buttons.
A FSM is implemented to fetch data,
also taking into account the correct
clock speed by scaling down the clock
slow enough for the controller to read
the pulses.
Author: Sergio M, Randy T, Omar T, Hector D, Kevin M
Date: 8/9/14 (Rev2)
*/
module snes_controller(
LATCH, // GPIO[x]
DATA, // GPIO[x]
PULSE, // GPIO[x]
CLOCK, // eg. CLOCK_50 (50MHz)
BUTTONS // Array of buttons
);
//=======================================================
// PORT declarations
//=======================================================
input DATA;
input CLOCK;
output LATCH;
output PULSE;
output [12:0] BUTTONS;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [12:0] buttons; // Holds the buttons to be pressed
reg latch; // snes latch pin
reg pulse; // snes pulse pin
reg snes_clock; // Oscillates slower for snes
reg [17:0] prescaler; // For scaling down clock rate
// FSM
reg [5:0] states; // Keeps track of current state
//=======================================================
// Constant Variables
//=======================================================
//Constant variables named accordingly to the states
//35 states total
//1 Init state
parameter SNES_Init = 1;
//Latch
//2 states for the Latch (A button)
parameter Latch_ON_1 = 2;
parameter Latch_ON_2 = 3;
//Pulses
//24 states for the pulses (B, Select, Start, Up, Down, Left, Right)
parameter ButtonB_ON = 4;
parameter ButtonB_OFF = 5;
parameter ButtonY_ON = 6;
parameter ButtonY_OFF = 7;
parameter ButtonSelect_ON = 8;
parameter ButtonSelect_OFF = 9;
parameter ButtonStart_ON = 10;
parameter ButtonStart_OFF = 11;
parameter ButtonUp_ON = 12;
parameter ButtonUp_OFF = 13;
parameter ButtonDown_ON = 14;
parameter ButtonDown_OFF = 15;
parameter ButtonLeft_ON = 16;
parameter ButtonLeft_OFF = 17;
parameter ButtonRight_ON = 18;
parameter ButtonRight_OFF = 19;
parameter ButtonA_ON = 20;
parameter ButtonA_OFF = 21;
parameter ButtonX_ON = 22;
parameter ButtonX_OFF = 23;
parameter ButtonTriggerLeft_ON = 24;
parameter ButtonTriggerLeft_OFF = 25;
parameter ButtonTriggerRight_ON = 26;
parameter ButtonTriggerRight_OFF = 27;
//Idle states
//8 states for the rest of the 16 bit controller, ticks until all bits are checked
//even though the remaining 4 bits are nothing.
parameter ButtonIdleON_1 = 28;
parameter ButtonIdleOFF_1 = 29;
parameter ButtonIdleON_2 = 30;
parameter ButtonIdleOFF_2 = 31;
parameter ButtonIdleON_3 = 32;
parameter ButtonIdleOFF_3 = 33;
parameter ButtonIdleON_4 = 34;
parameter ButtonIdleON_5 = 35;
// For slowing down the clock by a certain factor
// TODO: Still need to check for optimal timing
parameter To_Tick = 12'h0A2;
//=======================================================
// Structural coding
//=======================================================
assign LATCH = latch;
assign PULSE = pulse;
assign BUTTONS = buttons;
//Initialize variables
initial begin
prescaler <= 0;
snes_clock <= 0;
latch <= 0;
//For SNES controllers, pulse starts at 1
pulse <= 1;
states <= SNES_Init;
end
// Prescales CLOCK_50 to appropriate Hz for controller
always @ (posedge CLOCK)
begin
// Slow down the clock by a certain factor
// Still need to check for optimal timing
if(prescaler < To_Tick)
prescaler <= prescaler + 1;
else
prescaler <= 0;
// Once prescaler reached count, oscillate clk
if(prescaler == 0)
begin
snes_clock <= ~snes_clock;
end
end
/*
* Runs whenever snes_clock ticks which would be counted by the prescaler loop above.
* Summary: State machine first latches and pulse on (1) for one full pulse period. After another tick,
latch turns off (0) and pulse begins oscillating. This is different than the NES controller as
pulse oscillates a tick after latch is 0. Adjusted the bits so that 1 meant the button would be
the buttons pressed. After every off, take in DATA to see if each button is pressed or not pressed
Order of checks:(B, Y, Select, Start, Up, Down, Left, Right, A, X, Lefttrigger, Righttrigger)
Each button has 2 states (On and Off).
* Output: 12 bit register buttons stored with all the buttons
buttons[0] = B
buttons[1] = Y
buttons[2] = Select
buttons[3] = Start
buttons[4] = Up
buttons[5] = Down
buttons[6] = Left
buttons[7] = Right
buttons[8] = A
buttons[9] = X
buttons[10] = TriggerLeft
buttons[11] = TriggerRight
Example: b110010010100 - TriggerRight, Trigger Left, Right, Up, and Select are pressed.
*/
always @ (posedge snes_clock)
begin
//Transitions
case(states)
SNES_Init :
states <= Latch_ON_1;
//Latch starts
//Latch stays on for 2 states as it needs to keep the latch on for twice as longer than one pulse
//Diagram shown on the notes
Latch_ON_1 :
states <= Latch_ON_2;
Latch_ON_2 :
states <= ButtonB_ON;
//Pulses
ButtonB_ON :
states <= ButtonB_OFF;
ButtonB_OFF :
states <= ButtonY_ON;
ButtonY_ON :
states <= ButtonY_OFF;
ButtonY_OFF :
states <= ButtonSelect_ON;
ButtonSelect_ON :
states <= ButtonSelect_OFF;
ButtonSelect_OFF :
states <= ButtonStart_ON;
ButtonStart_ON :
states <= ButtonStart_OFF;
ButtonStart_OFF :
states <= ButtonUp_ON;
ButtonUp_ON :
states <= ButtonUp_OFF;
ButtonUp_OFF :
states <= ButtonDown_ON;
ButtonDown_ON :
states <= ButtonDown_OFF;
ButtonDown_OFF :
states <= ButtonLeft_ON;
ButtonLeft_ON :
states <= ButtonLeft_OFF;
ButtonLeft_OFF :
states <= ButtonRight_ON;
ButtonRight_ON :
states <= ButtonRight_OFF;
ButtonRight_OFF :
states <= ButtonA_ON;
ButtonA_ON :
states <= ButtonA_OFF;
ButtonA_OFF :
states <= ButtonX_ON;
ButtonX_ON :
states <= ButtonX_OFF;
ButtonX_OFF :
states <= ButtonTriggerLeft_ON;
ButtonTriggerLeft_ON :
states <= ButtonTriggerLeft_OFF;
ButtonTriggerLeft_OFF :
states <= ButtonTriggerRight_ON;
ButtonTriggerRight_ON :
states <= ButtonTriggerRight_OFF;
ButtonTriggerRight_OFF :
states <= ButtonIdleON_1;
//Idle states
ButtonIdleON_1 :
states <= ButtonIdleOFF_1;
ButtonIdleOFF_1 :
states <= ButtonIdleON_2;
ButtonIdleON_2 :
states <= ButtonIdleOFF_2;
ButtonIdleOFF_2 :
states <= ButtonIdleON_3;
ButtonIdleON_3 :
states <= ButtonIdleOFF_3;
ButtonIdleOFF_3 :
states <= ButtonIdleON_4;
ButtonIdleON_4 :
states <= ButtonIdleON_5;
ButtonIdleON_5 :
states <= Latch_ON_1;
endcase
//Actions
case(states)
SNES_Init : begin
latch <= 0;
//SNES requires pulse to be 1 in the beginning, different than NES controller
pulse <= 1;
end
//Latch starts
//Latch stays on for 2 states as it needs to keep the latch on for twice as longer than one pulse
//Diagram shown on the notes
Latch_ON_1 : begin
latch <= 1;
pulse <= 1;
end
Latch_ON_2 : begin
latch <= 1;
pulse <= 1;
end
//Pulses
ButtonB_ON : begin
latch <= 0;
pulse <= 1;
end
ButtonB_OFF : begin
pulse <= 0;
buttons[0] <= ~DATA;
end
//At this point, latch can just stay 0 until the state machine repeats
ButtonY_ON :
pulse <= 1;
ButtonY_OFF : begin
pulse <= 0;
buttons[1] <= ~DATA;
end
ButtonSelect_ON :
pulse <= 1;
ButtonSelect_OFF : begin
pulse <= 0;
buttons[2] <= ~DATA;
end
ButtonStart_ON :
pulse <= 1;
ButtonStart_OFF : begin
pulse <= 0;
buttons[3] <= ~DATA;
end
ButtonUp_ON :
pulse <= 1;
ButtonUp_OFF : begin
pulse <= 0;
buttons[4] <= ~DATA;
end
ButtonDown_ON :
pulse <= 1;
ButtonDown_OFF : begin
pulse <= 0;
buttons[5] <= ~DATA;
end
ButtonLeft_ON :
pulse <= 1;
ButtonLeft_OFF : begin
pulse <= 0;
buttons[6] <= ~DATA;
end
ButtonRight_ON :
pulse <= 1;
ButtonRight_OFF : begin
pulse <= 0;
buttons[7] <= ~DATA;
end
ButtonA_ON :
pulse <= 1;
ButtonA_OFF : begin
pulse <= 0;
buttons[8] <= ~DATA;
end
ButtonX_ON :
pulse <= 1;
ButtonX_OFF : begin
pulse <= 0;
buttons[9] <= ~DATA;
end
ButtonTriggerLeft_ON :
pulse <= 1;
ButtonTriggerLeft_OFF : begin
pulse <= 0;
buttons[10] <= ~DATA;
end
ButtonTriggerRight_ON :
pulse <= 1;
ButtonTriggerRight_OFF : begin
pulse <= 0;
buttons[11] <= ~DATA;
end
//Idle states
//pulses on and off without sending any data
//Does this to account for the controller being 16 bits while only 12 bits are used.
ButtonIdleON_1 :
pulse <= 1;
ButtonIdleOFF_1 :
pulse <= 0;
ButtonIdleON_2 :
pulse <= 1;
ButtonIdleOFF_2 :
pulse <= 0;
ButtonIdleON_3 :
pulse <= 1;
ButtonIdleOFF_3 :
pulse <= 0;
ButtonIdleON_4 :
pulse <= 1;
ButtonIdleON_5 :
pulse <= 1;
endcase
end
endmodule // END snes_controller
|
#include <bits/stdc++.h> using namespace std; int n, ans; void boost() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { boost(); cin >> n; for (int a = 0; a <= 1; a++) { for (int b = 0; b <= 1; b++) { for (int c = 0; c <= 1; c++) { for (int d = 0; d <= 1; d++) { for (int e = 0; e <= 1; e++) { for (int first = 0; first <= 1; first++) { for (int g = 0; g <= 1; g++) { for (int h = 0; h <= 1; h++) { for (int i = 0; i <= 1; i++) { for (int j = 0; j <= 1; j++) { if (a == 1 || b == 1 || c == 1 || d == 1 || e == 1 || first == 1 || g == 1 || h == 1 || i == 1 || j == 1) { if (a * 1000000000 + b * 100000000 + c * 10000000 + d * 1000000 + e * 100000 + first * 10000 + g * 1000 + h * 100 + i * 10 + j <= n) { ans++; } } } } } } } } } } } } cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_PP_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SET ;
wire mux_out ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int fastMax(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ y; } int fastMin(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ x; } const long long int MAXN = 1e5 + 3; long long int dp[20][2][10][10]; vector<long long int> digits; void convert_to_digits(long long int n) { digits.clear(); if (n == 0) digits.push_back(0); while (n > 0) { digits.push_back(n % 10); n = n / 10; } } long long int recursion(long long int idx, bool flag, long long int first, long long int last) { if (idx == -1) { if (first == last && first != 0) return 1; return 0; } if (dp[idx][flag][first][last] != -1) return dp[idx][flag][first][last]; long long int ans = 0; long long int n = (flag) ? digits[idx] : 9; for (int i = (0); i <= (n); ++i) { bool nflag = (i == n) ? flag : 0; long long int nfirst = (first == 0 and i != 0) ? i : first; long long int nlast = i; ans = ans + recursion(idx - 1, nflag, nfirst, nlast); } return dp[idx][flag][first][last] = ans; } void solve() { long long int l, r; cin >> l >> r; memset(dp, -1, sizeof(dp)); convert_to_digits(r); long long int ans = recursion(digits.size() - 1, 1, 0, 0); memset(dp, -1, sizeof(dp)); if (l > 1) { convert_to_digits(l - 1); ans -= recursion(digits.size() - 1, 1, 0, 0); } cout << ans << endl; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int t; t = 1; while (t--) { solve(); } }
|
//*******************************************************************************************************************************************************/
// Module Name: stack
// Module Type: Last in First Out (LIFO) Stack Register
// Author: Shreyas Vinod
// Purpose: Stack for Neptune I v3.0
// Description: A synchronous Last in Firt Out (LIFO) Stack Register specifically designed for Neptune I.
//*******************************************************************************************************************************************************/
module stack(clk, rst, pop, push, wr, mem_fault, rd);
// Parameter Definitions
parameter width = 'd16; // Stack Data Width
parameter depth = 'd256; // Stack Depth
parameter add_width = 'd8; // Stack Addressing Width
// Inputs
input wire clk /* System Clock */, rst /* System Reset, Resets stack location. */; // Management Interfaces
input wire pop /* Stack Pop Enable */, push /* Stack Push Enable */; // Control Interfaces
input wire [width-1:0] wr /* Write Port */;
// Outputs
output reg mem_fault /* Memory Fault */;
output reg [width-1:0] rd /* Read Port */;
// Internal
reg [add_width-1:0] stk_loc /* Stack Location Register */;
reg [width-1:0] rd_out /* Storage Register for Read */;
reg [width-1:0] mem_arr [0:depth-1] /* Two-Dimensional Memory Array (Width-Depth Matrix) */;
// Stack Location Controller
always@(posedge clk) begin
if(rst) begin
mem_fault <= 1'b0; // Resets the mem_fault flag if rst is true.
stk_loc [add_width-1] <= {width{1'b0}};
end else if(push && !pop) stk_loc <= stk_loc + 1'b1; // Pushes the stack forward.
else if(pop && !push) stk_loc <= stk_loc - 1'b1; // Pulls the stack backward.
else if ((push && pop) && (stk_loc == 8'b0) || (push && (stk_loc = 8'b11111111))) mem_fault <= 1'b1; // Memory Fault instates itself on push-pop collision.
end
// Memory Read Block
always@(posedge clk) begin
rd [width-1:0] <= mem_arr[stk_loc] [width-1:0]; // Reads the contents of memory at every positive clock edge.
end
// Memory Write Block
always@(posedge clk) begin
if(push) mem_arr[stk_loc] [width-1:0] <= wr [width-1:0]; // Writes the value at wr to memory if push is true.
end
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2008 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: control_interface
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision
// --------------------------------------------------------------------
module control_interface(
CLK,
RESET_N,
CMD,
ADDR,
REF_ACK,
INIT_ACK,
CM_ACK,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
SADDR,
REF_REQ,
INIT_REQ,
CMD_ACK
);
`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [2:0] CMD; // Command input
input [`ASIZE-1:0] ADDR; // Address
input REF_ACK; // Refresh request acknowledge
input INIT_ACK; // Initial request acknowledge
input CM_ACK; // Command acknowledge
output NOP; // Decoded NOP command
output READA; // Decoded READA command
output WRITEA; // Decoded WRITEA command
output REFRESH; // Decoded REFRESH command
output PRECHARGE; // Decoded PRECHARGE command
output LOAD_MODE; // Decoded LOAD_MODE command
output [`ASIZE-1:0] SADDR; // Registered version of ADDR
output REF_REQ; // Hidden refresh request
output INIT_REQ; // Hidden initial request
output CMD_ACK; // Command acknowledge
reg NOP;
reg READA;
reg WRITEA;
reg REFRESH;
reg PRECHARGE;
reg LOAD_MODE;
reg [`ASIZE-1:0] SADDR;
reg REF_REQ;
reg INIT_REQ;
reg CMD_ACK;
// Internal signals
reg [15:0] timer;
reg [15:0] init_timer;
// Command decode and ADDR register
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
NOP <= 0;
READA <= 0;
WRITEA <= 0;
SADDR <= 0;
end
else
begin
SADDR <= ADDR; // register the address to keep proper
// alignment with the command
if (CMD == 3'b000) // NOP command
NOP <= 1;
else
NOP <= 0;
if (CMD == 3'b001) // READA command
READA <= 1;
else
READA <= 0;
if (CMD == 3'b010) // WRITEA command
WRITEA <= 1;
else
WRITEA <= 0;
end
end
// Generate CMD_ACK
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
CMD_ACK <= 0;
else
if ((CM_ACK == 1) & (CMD_ACK == 0))
CMD_ACK <= 1;
else
CMD_ACK <= 0;
end
// refresh timer
always @(posedge CLK or negedge RESET_N) begin
if (RESET_N == 0)
begin
timer <= 0;
REF_REQ <= 0;
end
else
begin
if (REF_ACK == 1)
begin
timer <= REF_PER;
REF_REQ <=0;
end
else if (INIT_REQ == 1)
begin
timer <= REF_PER+200;
REF_REQ <=0;
end
else
timer <= timer - 1'b1;
if (timer==0)
REF_REQ <= 1;
end
end
// initial timer
always @(posedge CLK or negedge RESET_N) begin
if (RESET_N == 0)
begin
init_timer <= 0;
REFRESH <= 0;
PRECHARGE <= 0;
LOAD_MODE <= 0;
INIT_REQ <= 0;
end
else
begin
if (init_timer < (INIT_PER+201))
init_timer <= init_timer+1;
if (init_timer < INIT_PER)
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=1;
end
else if(init_timer == (INIT_PER+20))
begin
REFRESH <=0;
PRECHARGE <=1;
LOAD_MODE <=0;
INIT_REQ <=0;
end
else if( (init_timer == (INIT_PER+40)) ||
(init_timer == (INIT_PER+60)) ||
(init_timer == (INIT_PER+80)) ||
(init_timer == (INIT_PER+100)) ||
(init_timer == (INIT_PER+120)) ||
(init_timer == (INIT_PER+140)) ||
(init_timer == (INIT_PER+160)) ||
(init_timer == (INIT_PER+180)) )
begin
REFRESH <=1;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=0;
end
else if(init_timer == (INIT_PER+200))
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=1;
INIT_REQ <=0;
end
else
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void out(T x) { cout << x << endl; exit(0); } const int maxn = 1e6 + 5; int n, m; int a[maxn]; vector<int> g[maxn]; vector<pair<int, pair<int, int>>> edges; int par[maxn], siz[maxn]; int f(int x) { return par[x] == x ? x : par[x] = f(par[x]); } void join(int x, int y) { x = f(x); y = f(y); if (x == y) return; if (siz[x] < siz[y]) swap(x, y); siz[x] += siz[y]; par[y] = x; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a[i]; par[i] = i; siz[i] = 1; } for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); edges.push_back({min(a[u], a[v]), {u, v}}); } auto cmp = [](pair<int, pair<int, int>> p1, pair<int, pair<int, int>> p2) { return p1.first > p2.first; }; long double num = 0; long double den = 0; sort(edges.begin(), edges.end(), cmp); for (auto p : edges) { int wei = p.first; int u = f(p.second.first); int v = f(p.second.second); if (u == v) continue; long double paths = 1LL * siz[u] * siz[v]; den += paths; num += 1.0 * wei * paths; join(u, v); } long double ans = num / den; cout << fixed << setprecision(9) << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, p, q, r; cin >> n >> p >> q >> r; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } long long dp[n][3]; dp[0][0] = 1ll * p * a[0]; for (int i = 1; i < n; i++) { dp[i][0] = max(dp[i - 1][0], 1ll * p * a[i]); } dp[0][1] = dp[0][0] + 1ll * q * a[0]; for (int i = 1; i < n; i++) { dp[i][1] = max(dp[i - 1][1], dp[i][0] + 1ll * q * a[i]); } dp[0][2] = dp[0][1] + 1ll * r * a[0]; for (int i = 1; i < n; i++) { dp[i][2] = max(dp[i - 1][2], dp[i][1] + 1ll * r * a[i]); } cout << dp[n - 1][2] << n ; }
|
`timescale 1ns / 1ps
module ADC_interface_AXI_XADC (
//----general--input----
input CLK,
input RST,
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output reg axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output reg axi_rvalid,
input axi_rready,
output reg [32-1:0] axi_rdata,
//----Ignorable data----
output [7:0] ALM,
output OT,
output XADC_EOC,
output XADC_EOS/*,
// ANALOG data
input [3:0] VAUXP,
input [3:0] VAUXN,
input VP,
input VN*/);
wire EOS, EOC;
wire busy;
wire [4:0] CHANNEL;
wire drdy;
reg [6:0] daddr;
reg [15:0] di_drp;
wire [15:0] do_drp;
//reg [15:0] vauxp_active;
//reg [15:0] vauxn_active;
reg [1:0] den_reg;
reg [1:0] dwe_reg;
wire RESET_IN;
assign RESET_IN = ~RST;
// AXI-4 Auxiliar
reg [31:0] waddr, raddr;
reg [31:0] wdata;
reg [3:0] wstrb;
reg [1:0] wassert;
reg rassert;
// AXI-4 immediate responses
assign axi_awready = 1'b1;
assign axi_arready = 1'b1;
assign axi_wready = 1'b1;
// AXI-4 Single shot response and saving
always @(posedge CLK)
begin : SINGLE_SHOT
if(RST == 1'b0) begin
waddr <= 0;
raddr <= 0;
wdata <= 0;
wstrb <= 0;
wassert <= 2'b00;
rassert <= 1'b0;
end else begin
if(axi_bvalid) begin // bvalid indicates wterm sig
waddr <= waddr;
wassert[0] <= 1'b0;
end else if(axi_awvalid) begin
waddr <= axi_awaddr;
wassert[0] <= 1'b1;
end else begin
waddr <= waddr;
wassert[0] <= wassert[0];
end
if(axi_bvalid) begin // bvalid indicates wterm sig
wdata <= wdata;
wstrb <= wstrb;
wassert[1] <= 1'b0;
end else if(axi_wvalid) begin
wdata <= axi_wdata;
wstrb <= axi_wstrb;
wassert[1] <= 1'b1;
end else begin
wdata <= wdata;
wstrb <= wstrb;
wassert[1] <= wassert[1];
end
if(axi_rvalid) begin // rvalid indicates rterm sig
raddr <= raddr;
rassert <= 1'b0;
end else if(axi_arvalid) begin
raddr <= axi_araddr;
rassert <= 1'b1;
end else begin
raddr <= raddr;
rassert <= rassert;
end
end
end
parameter init_read = 8'h00,
read_waitdrdy = 8'h01,
write_waitdrdy = 8'h03,
st_idle = 8'h04,
read_reg = 8'h05,
rreg_waitdrdy = 8'h06,
write_reg = 8'h07,
wreg_waitdrdy = 8'h08,
axi_waitrready = 8'h09,
axi_waitbready = 8'h0A;
reg [7:0] state;
//reg [7:0] ret_state;
always @(posedge CLK)
if (RST == 1'b0) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
daddr <= 0;
//vauxp_active <= 0;
//vauxn_active <= 0;
axi_rdata <= 0;
axi_bvalid <= 1'b0;
axi_rvalid <= 1'b0;
end else case (state)
init_read : begin
daddr <= 7'h40; // READ CONFIG REGISTER 1
den_reg <= 2'h2; // performing read
if (busy == 0 ) state <= read_waitdrdy;
end
read_waitdrdy :
if (drdy ==1) begin
di_drp <= do_drp & 16'h03_FF; //Clearing AVG bits for Configreg0
daddr <= 7'h40;
den_reg <= 2'h2;
dwe_reg <= 2'h2; // performing write
state <= write_waitdrdy;
end else begin
den_reg <= { 1'b0, den_reg[1] } ;
dwe_reg <= { 1'b0, dwe_reg[1] } ;
state <= state;
end
write_waitdrdy :
if (drdy ==1) begin
state <= st_idle;
end else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state <= state;
end
st_idle :
if (rassert) begin
state <= read_reg;
end else if(wassert == 2'b11) begin
/*if(waddr[8:2] == 7'h00) begin // This registers cannot be written, but we can use it
vauxn_active <= wdata[15:0];
axi_bvalid <= 1'b1;
state <= wreg_waitdrdy;
end else if (waddr[8:2] == 7'h01) begin
vauxp_active <= wdata[15:0];
axi_bvalid <= 1'b1;
state <= wreg_waitdrdy;
end else begin */
state <= write_reg;
//end
end else begin
state <= state;
end
read_reg : begin
daddr = raddr[8:2];
den_reg = 2'h2; // performing read
if (EOC == 1) state <=rreg_waitdrdy;
end
rreg_waitdrdy :
if (drdy ==1) begin
axi_rdata <= {15'd0, do_drp};
axi_rvalid <= 1'b1;
state <= axi_waitrready;
end else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state <= state;
end
axi_waitrready :
if (axi_rready ==1) begin
axi_rvalid <= 1'b0;
state <= st_idle;
end else begin
state <= state;
end
write_reg : begin
di_drp <= wdata[15:0];
daddr <= waddr[8:2];
den_reg <= 2'h2;
dwe_reg <= 2'h2; // performing write
state <= wreg_waitdrdy;
end
wreg_waitdrdy :
if (drdy ==1) begin
axi_bvalid <= 1'b1;
state <= axi_waitbready;
end else begin
den_reg <= { 1'b0, den_reg[1] } ;
dwe_reg <= { 1'b0, dwe_reg[1] } ;
state <= state;
end
axi_waitbready :
if (axi_bready ==1) begin
axi_bvalid <= 1'b0;
state <= st_idle;
end else begin
state <= state;
end
default: begin
state <= init_read; end
endcase
wire [15:0] vauxp_active;
wire [15:0] vauxn_active;
assign vauxp_active = 16'h0000;//= {12'h000, VAUXP[3:0]};
assign vauxn_active = 16'h0000;//= {12'h000, VAUXN[3:0]};
XADC #(
.INIT_40(16'h9000),// averaging of 16 selected for external CHANNELs
.INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration
.INIT_42(16'h0400),// Set DCLK divides
.INIT_48(16'h4701),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
.INIT_49(16'h000f),// CHSEL2 - enable aux analog CHANNELs 0 - 3
.INIT_4A(16'h0000),// SEQAVG1 disabled
.INIT_4B(16'h0000),// SEQAVG2 disabled
.INIT_4C(16'h0000),// SEQINMODE0
.INIT_4D(16'h0000),// SEQINMODE1
.INIT_4E(16'h0000),// SEQACQ0
.INIT_4F(16'h0000),// SEQACQ1
.INIT_50(16'hb5ed),// Temp upper alarm trigger 85°C
.INIT_51(16'h5999),// Vccint upper alarm limit 1.05V
.INIT_52(16'hA147),// Vccaux upper alarm limit 1.89V
.INIT_53(16'hdddd),// OT upper alarm limit 125°C - see Thermal Management
.INIT_54(16'ha93a),// Temp lower alarm reset 60°C
.INIT_55(16'h5111),// Vccint lower alarm limit 0.95V
.INIT_56(16'h91Eb),// Vccaux lower alarm limit 1.71V
.INIT_57(16'hae4e),// OT lower alarm reset 70°C - see Thermal Management
.INIT_58(16'h5999),// VCCBRAM upper alarm limit 1.05V
.SIM_MONITOR_FILE("design.txt")// Analog Stimulus file for simulation
)
XADC_INST ( // Connect up instance IO. See UG480 for port descriptions
// General ports
.RESET(RESET_IN),
.DCLK(CLK),
// DRP (Dynamic Reconfiguration Port)
.DADDR (daddr),
.DEN (den_reg[0]),
.DI (di_drp),
.DWE (dwe_reg[0]),
.DO (do_drp),
.DRDY (drdy),
.VAUXN (vauxn_active ),
.VAUXP (vauxp_active ),
.ALM (ALM),
.BUSY (busy),
.CHANNEL(CHANNEL),
.EOC (EOC),
.EOS (EOS),
// JTAG Arbritator (Not used)
.JTAGBUSY (),// not used
.JTAGLOCKED (),// not used
.JTAGMODIFIED (),// not used
.OT (OT),
.MUXADDR (),// not used
.VP (VP),
.VN (VN)
);
assign XADC_EOC = EOC;
assign XADC_EOS = EOS;
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {+1, -1, +0, +0}; int dy[] = {+0, +0, +1, -1}; int fx[] = {+0, +0, +1, -1, -1, +1, -1, +1}; int fy[] = {-1, +1, +0, +0, +1, +1, -1, -1}; int hr[] = {-2, -2, -1, +1, +2, +2, -1, +1}; int hc[] = {+1, -1, +2, +2, -1, +1, -2, -2}; const int MAXN = 1e5 + 9; int main() { int i, j, k, l, m, n, tc, t, mx, ans, total = 0; cin >> n >> m; mx = -9999; ans = -1; for (int i = 0; i < (int)n; i++) { cin >> k; t = k / m; if (k % m) t++; if (t >= mx) { mx = t; ans = i + 1; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-8; const int INF = 1E9; const int MAXN = 11111; int n, maxc; int l[MAXN], r[MAXN], b[MAXN]; int _less[MAXN]; int id[MAXN], mx; double ans, dp[11][MAXN], sum[11][MAXN]; double p[11]; int main() { cin >> n; for (int i = 0; i < (int)(n); i++) { cin >> l[i] >> r[i]; p[i] = 1.0 / (r[i] - l[i] + 1); } for (int i = 0; i < (int)(n); i++) id[i] = i; ans = 0; while (true) { maxc = 1 << (n - 1); for (int mask = 0; mask < (int)(maxc); mask++) { for (int i = 0; i < (int)(n - 1); i++) _less[i] = (mask >> i) & 1; bool ok = 1; for (int i = 0; i < (int)(n - 1); i++) if (_less[i] == 1 && id[i] > id[i + 1]) { ok = 0; break; } if (!ok) continue; memset(dp, 0, sizeof(dp)); for (int i = l[id[n - 2]]; i <= r[id[n - 2]]; i++) { dp[n - 2][i] = 1.0 * i; if (_less[n - 2]) dp[n - 2][i] *= (l[id[n - 1]] <= i && i <= r[id[n - 1]] ? 1 : 0); else dp[n - 2][i] *= (i + 1 <= r[id[n - 1]] ? (r[id[n - 1]] - max(l[id[n - 1]], i + 1) + 1) : 0); } mx = r[id[n - 2]]; sum[n - 2][MAXN - 1] = dp[n - 2][MAXN - 1]; for (int i = (int)(MAXN - 1) - 1; i >= 0; i--) sum[n - 2][i] = sum[n - 2][i + 1] + dp[n - 2][i]; for (int i = n - 3; i >= 0; i--) { for (int j = l[id[i]]; j <= r[id[i]]; j++) { if (_less[i]) dp[i][j] = dp[i + 1][j]; else { dp[i][j] = sum[i + 1][j + 1]; } } sum[i][MAXN - 1] = dp[i][MAXN - 1]; for (int j = (int)(MAXN - 1) - 1; j >= 0; j--) sum[i][j] = sum[i][j + 1] + dp[i][j]; } ans += sum[0][0]; } if (!next_permutation(id, id + n)) break; } cout.precision(40); for (int i = 0; i < (int)(n); i++) ans *= p[i]; cout << ans; return 0; }
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module cpu_if
(
// General - Clocking & Reset
input clk_i,
input rst_i,
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
output [31:0] imem0_addr_o,
input [31:0] imem0_data_i,
output [3:0] imem0_sel_o,
output imem0_stb_o,
output imem0_cyc_o,
output [2:0] imem0_cti_o,
input imem0_ack_i,
input imem0_stall_i,
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
output [31:0] dmem0_addr_o,
output [31:0] dmem0_data_o,
input [31:0] dmem0_data_i,
output [3:0] dmem0_sel_o,
output dmem0_we_o,
output dmem0_stb_o,
output dmem0_cyc_o,
output [2:0] dmem0_cti_o,
input dmem0_ack_i,
input dmem0_stall_i,
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
output [31:0] dmem1_addr_o,
output [31:0] dmem1_data_o,
input [31:0] dmem1_data_i,
output [3:0] dmem1_sel_o,
output dmem1_we_o,
output dmem1_stb_o,
output dmem1_cyc_o,
output [2:0] dmem1_cti_o,
input dmem1_ack_i,
input dmem1_stall_i,
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
output [31:0] dmem2_addr_o,
output [31:0] dmem2_data_o,
input [31:0] dmem2_data_i,
output [3:0] dmem2_sel_o,
output dmem2_we_o,
output dmem2_stb_o,
output dmem2_cyc_o,
output [2:0] dmem2_cti_o,
input dmem2_ack_i,
input dmem2_stall_i,
output fault_o,
output break_o,
input intr_i,
input nmi_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 12288;
parameter ENABLE_ICACHE = "ENABLED";
parameter ENABLE_DCACHE = "ENABLED";
parameter BOOT_VECTOR = 0;
parameter ISR_VECTOR = 0;
parameter REGISTER_FILE_TYPE = "SIMULATION";
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire [31:0] dmem_addr;
wire [31:0] dmem_data_w;
wire [31:0] dmem_data_r;
wire [3:0] dmem_sel;
wire [2:0] dmem_cti;
wire dmem_cyc;
wire dmem_we;
wire dmem_stb;
wire dmem_stall;
wire dmem_ack;
wire [31:0] imem_address;
wire [31:0] imem_data;
wire [2:0] imem_cti;
wire imem_cyc;
wire imem_stb;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// CPU core
//-----------------------------------------------------------------
cpu
#(
.BOOT_VECTOR(BOOT_VECTOR),
.ISR_VECTOR(ISR_VECTOR),
.REGISTER_FILE_TYPE(REGISTER_FILE_TYPE),
.ENABLE_ICACHE(ENABLE_ICACHE),
.ENABLE_DCACHE(ENABLE_DCACHE)
)
u1_cpu
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_i(intr_i),
.nmi_i(nmi_i),
// Status
.fault_o(fault_o),
.break_o(break_o),
// Instruction memory
.imem_addr_o(imem_address),
.imem_dat_i(imem_data),
.imem_cti_o(imem_cti),
.imem_cyc_o(imem_cyc),
.imem_stb_o(imem_stb),
.imem_stall_i(imem_stall),
.imem_ack_i(imem_ack),
// Data memory
.dmem_addr_o(dmem_addr),
.dmem_dat_o(dmem_data_w),
.dmem_dat_i(dmem_data_r),
.dmem_sel_o(dmem_sel),
.dmem_cti_o(dmem_cti),
.dmem_cyc_o(dmem_cyc),
.dmem_we_o(dmem_we),
.dmem_stb_o(dmem_stb),
.dmem_stall_i(dmem_stall),
.dmem_ack_i(dmem_ack)
);
//-----------------------------------------------------------------
// Instruction Memory MUX
//-----------------------------------------------------------------
assign imem0_addr_o = imem_address;
assign imem0_sel_o = 4'b1111;
assign imem0_stb_o = imem_stb;
assign imem0_cyc_o = imem_cyc;
assign imem0_cti_o = imem_cti;
assign imem_data = imem0_data_i;
assign imem_stall = imem0_stall_i;
assign imem_ack = imem0_ack_i;
//-----------------------------------------------------------------
// Data Memory MUX
//-----------------------------------------------------------------
dmem_mux3
#(
.ADDR_MUX_START(24)
)
u_dmux
(
// Outputs
// 0x10000000 - 0x10FFFFFF
.out0_addr_o(dmem0_addr_o),
.out0_data_o(dmem0_data_o),
.out0_data_i(dmem0_data_i),
.out0_sel_o(dmem0_sel_o),
.out0_we_o(dmem0_we_o),
.out0_stb_o(dmem0_stb_o),
.out0_cyc_o(dmem0_cyc_o),
.out0_cti_o(dmem0_cti_o),
.out0_ack_i(dmem0_ack_i),
.out0_stall_i(dmem0_stall_i),
// 0x11000000 - 0x11FFFFFF
.out1_addr_o(dmem1_addr_o),
.out1_data_o(dmem1_data_o),
.out1_data_i(dmem1_data_i),
.out1_sel_o(dmem1_sel_o),
.out1_we_o(dmem1_we_o),
.out1_stb_o(dmem1_stb_o),
.out1_cyc_o(dmem1_cyc_o),
.out1_cti_o(dmem1_cti_o),
.out1_ack_i(dmem1_ack_i),
.out1_stall_i(dmem1_stall_i),
// 0x12000000 - 0x12FFFFFF
.out2_addr_o(dmem2_addr_o),
.out2_data_o(dmem2_data_o),
.out2_data_i(dmem2_data_i),
.out2_sel_o(dmem2_sel_o),
.out2_we_o(dmem2_we_o),
.out2_stb_o(dmem2_stb_o),
.out2_cyc_o(dmem2_cyc_o),
.out2_cti_o(dmem2_cti_o),
.out2_ack_i(dmem2_ack_i),
.out2_stall_i(dmem2_stall_i),
// Input - CPU core bus
.mem_addr_i(dmem_addr),
.mem_data_i(dmem_data_w),
.mem_data_o(dmem_data_r),
.mem_sel_i(dmem_sel),
.mem_we_i(dmem_we),
.mem_stb_i(dmem_stb),
.mem_cyc_i(dmem_cyc),
.mem_cti_i(dmem_cti),
.mem_ack_o(dmem_ack),
.mem_stall_o(dmem_stall)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_4_V
`define SKY130_FD_SC_HDLL__A32O_4_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_4_V
|
#include <bits/stdc++.h> #pragma clang diagnostic push #pragma clang diagnostic ignored -Wunused-const-variable using namespace std; template <typename T> class Modular { public: using Type = typename decay<decltype(T::value)>::type; constexpr Modular() : value() {} template <typename U> Modular(const U& x) { value = normalize(x); } static Type inverse(Type a, Type mod) { Type b = mod, x = 0, y = 1; while (a != 0) { Type t = b / a; b -= a * t; x -= t * y; swap(a, b); swap(x, y); } if (x < 0) x += mod; return x; } template <typename U> static Type normalize(const U& x) { Type v; if (-mod() <= x && x < mod()) v = static_cast<Type>(x); else v = static_cast<Type>(x % mod()); if (v < 0) v += mod(); return v; } const Type& operator()() const { return value; } template <typename U> explicit operator U() const { return static_cast<U>(value); } constexpr static Type mod() { return T::value; } Modular& operator+=(const Modular& other) { if ((value += other.value) >= mod()) value -= mod(); return *this; } Modular& operator-=(const Modular& other) { if ((value -= other.value) < 0) value += mod(); return *this; } template <typename U> Modular& operator+=(const U& other) { return *this += Modular(other); } template <typename U> Modular& operator-=(const U& other) { return *this -= Modular(other); } Modular& operator++() { return *this += 1; } Modular& operator--() { return *this -= 1; } Modular operator++(int) { Modular result(*this); *this += 1; return result; } Modular operator--(int) { Modular result(*this); *this -= 1; return result; } Modular operator-() const { return Modular(-value); } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(static_cast<int64_t>(value) * static_cast<int64_t>(rhs.value)); return *this; } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int64_t>::value, Modular>::type& operator*=(const Modular& rhs) { int64_t q = static_cast<int64_t>(static_cast<long double>(value) * rhs.value / mod()); value = normalize(value * rhs.value - q * mod()); return *this; } template <typename U = T> typename enable_if<!is_integral<typename Modular<U>::Type>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(value * rhs.value); return *this; } Modular& operator/=(const Modular& other) { return *this *= Modular(inverse(other.value, mod())); } template <typename U> friend const Modular<U>& abs(const Modular<U>& v) { return v; } template <typename U> friend bool operator==(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend bool operator<(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend std::istream& operator>>(std::istream& stream, Modular<U>& number); private: Type value; }; template <typename T> bool operator==(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value == rhs.value; } template <typename T, typename U> bool operator==(const Modular<T>& lhs, U rhs) { return lhs == Modular<T>(rhs); } template <typename T, typename U> bool operator==(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) == rhs; } template <typename T> bool operator!=(const Modular<T>& lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(const Modular<T>& lhs, U rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(U lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T> bool operator<(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value < rhs.value; } template <typename T> Modular<T> operator+(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T> Modular<T> operator-(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T> Modular<T> operator*(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T> Modular<T> operator/(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> power(const Modular<T>& a, const U& b) { assert(b >= 0); Modular<T> x = a, res = 1; U p = b; while (p > 0) { if (p & 1) res *= x; x *= x; p >>= 1; } return res; } template <typename T> bool IsZero(const Modular<T>& number) { return number() == 0; } template <typename T> string to_string(const Modular<T>& number) { return to_string(number()); } template <typename T> std::ostream& operator<<(std::ostream& stream, const Modular<T>& number) { return stream << number(); } template <typename T> std::istream& operator>>(std::istream& stream, Modular<T>& number) { typename common_type<typename Modular<T>::Type, int64_t>::type x; stream >> x; number.value = Modular<T>::normalize(x); return stream; } const int md = 1e9 + 7; using Mint = Modular<std::integral_constant<decay<decltype(md)>::type, md>>; long long sqr(long long x) { return x * x; } int mysqrt(long long x) { int l = 0, r = 1e9 + 1; while (r - l > 1) { int m = (l + r) / 2; if (m * (long long)m <= x) l = m; else r = m; } return l; } mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); mt19937_64 rndll( chrono::high_resolution_clock::now().time_since_epoch().count()); template <typename T> T gcd(T a, T b) { return a ? gcd(b % a, a) : b; } int gcdex(int a, int b, int& x, int& y) { if (a == 0) { x = 0; y = 1; return b; } int x1, y1; int ret = gcdex(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return ret; } void setmin(int& x, int y) { x = min(x, y); } void setmax(int& x, int y) { x = max(x, y); } void setmin(long long& x, long long y) { x = min(x, y); } void setmax(long long& x, long long y) { x = max(x, y); } const long long llinf = 4e18 + 100; const long double eps = 1e-9, PI = atan2(0, -1); const int maxn = 2e5 + 100, maxw = 1e4 + 100, inf = 1e9 + 100, sq = 450, LG = 18, mod = 1e9 + 933; int tp[maxn], h[maxn], n; vector<int> e[maxn]; long long q[maxn][2]; void dfs(int v, int par) { int X = 0, Y = 0; vector<long long> g; long long cur = 0; for (int i : e[v]) if (i != par) { dfs(i, v); if (h[i] == h[v]) { g.push_back(q[i][1] - q[i][0]); cur += q[i][0]; X++; } else if (h[i] < h[v]) { X++; cur += q[i][0]; } else { Y++; cur += q[i][1]; } } sort(g.begin(), g.end()); q[v][0] = q[v][1] = llinf; auto upd = [&](int t, int x, int y) { setmin(q[v][t], max(x, y) * (long long)tp[v] + cur); }; for (int i = 0; i <= g.size(); i++) { if (par == -1) upd(0, X, Y); else { upd(0, X, Y + 1); upd(1, X + 1, Y); } if (i < g.size()) { cur += g[i]; X--; Y++; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> tp[i]; for (int i = 0; i < n; i++) cin >> h[i]; for (int i = 1; i < n; i++) { int v, u; cin >> v >> u; v--; u--; e[v].push_back(u); e[u].push_back(v); } dfs(0, -1); cout << q[0][0] << n ; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100100; const long long oo = 1e18; int N; long long P[MAX], D[MAX]; int L[MAX], R[MAX]; void init_L() { stack<int> S; for (int i = 0; i <= N + 1; ++i) { while (S.size() >= 2) { int x = S.top(); S.pop(); if (D[x] >= P[i] - P[S.top()]) { S.push(x); break; } } if (!S.empty()) L[i] = S.top(); S.push(i); } } void init_R() { stack<int> S; for (int i = N + 1; i >= 0; --i) { while (S.size() >= 2) { int x = S.top(); S.pop(); if (D[x] >= P[S.top()] - P[i]) { S.push(x); break; } } if (!S.empty()) R[i] = S.top(); S.push(i); } } template <class T> struct MinQ { deque<T> D, Q; T top() { return D.front(); } void push(T x) { while (!D.empty() && x < D.back()) D.pop_back(); D.push_back(x); Q.push_back(x); } void pop() { if (D.front() == Q.front()) D.pop_front(); Q.pop_front(); } T front() { return Q.front(); } T empty() { return Q.empty(); } T size() { return Q.size(); } }; long long low(int x) { if (x == N + 1) return -1e10; long long ret = P[R[x]] - D[x]; return ret < P[x] ? ret : +oo; } long long high(int x) { if (x == 0) return +1e10; long long ret = P[L[x]] + D[x]; return ret > P[x] ? ret : -oo; } bool check(long long W) { MinQ<long long> Q; for (int a = 0, b = 0; a <= N; ++a) { for (; b <= N + 1 && P[b] - P[a] <= W; ++b) Q.push(low(b)); Q.pop(); if (!Q.empty() && high(a) >= Q.top()) return true; } return false; } int main() { scanf( %d , &N); for (int i = 0; i <= N + 1; ++i) scanf( %lld , P + i); for (int i = 1; i <= N; ++i) scanf( %lld , D + i), D[i] *= 2; D[0] = D[N + 1] = oo; init_L(); init_R(); if (R[0] != N + 1) { puts( 0 ); return 0; } long long lo = 1, hi = 1e10; while (lo < hi) { long long mid = (lo + hi) / 2; check(mid) ? hi = mid : lo = mid + 1; } printf( %.1lf n , lo / 2.0); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`include "verilated.v"
`define STRINGIFY(x) `"x`"
module t;
integer infile, outfile;
integer count, a;
initial begin
infile = $fopen("t/t_sys_file_scan_input.dat", "r");
outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w");
count = 1234;
`ifdef TEST_VERBOSE
$display("-count == %0d, infile %d, outfile %d", count, infile, outfile);
`endif
count = $fscanf(infile, "%d\n", a);
`ifdef TEST_VERBOSE
// Ifdefing this out gave bug248
$display("-count == %0d, infile %d, outfile %d", count, infile, outfile);
`endif
if (count == 0) $stop;
$fwrite(outfile, "# a\n");
$fwrite(outfile, "%d\n", a);
$fclose(infile);
$fclose(outfile);
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
endmodule
|
//
// Copyright (c) 1999 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Test the divide (/) operator
module top () ;
reg [7:0] a, b, result;
wire [7:0] wa, wb, wresult;
assign wa = a;
assign wb = b;
assign wresult = wa / wb;
always @(a or b)
result = a / b;
initial begin
#1 a = 0; b = 1;
# 1;
if( result !== 8'b0)
begin
$display("FAILED - Divide 0/1 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'b0)
begin
$display("FAILED - Divide 0/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1;
#1 if( result !== 8'b1)
begin
$display("FAILED - Divide 1/1 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'b1)
begin
$display("FAILED - Divide 1/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 5; b = 2;
#1 if( result !== 8'd2)
begin
$display("FAILED - Divide 5/2 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'd2)
begin
$display("FAILED - Divide 5/2 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 8'd255; b = 5;
#1 if( result !== 51)
begin
$display("FAILED - Divide 255/5 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 51)
begin
$display("FAILED - Divide 255/5 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1'bx; b = 3;
#1 if( result !== 8'bxxxx_xxxx)
begin
$display("FAILED - Divide x/3 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'hxxxx_xxxx)
begin
$display("FAILED - Divide x/3 wire assign failed - is %b",wresult);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char board[n][n]; bool even = true; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> board[i][j]; for (int i = 0; i < n; i++) { int c = 0; for (int j = 0; j < n; j++) { if (i - 1 >= 0 and board[i - 1][j] == o ) c++; if (i + 1 < n and board[i + 1][j] == o ) c++; if (j - 1 >= 0 and board[i][j - 1] == o ) c++; if (j + 1 < n and board[i][j + 1] == o ) c++; if (c % 2 == 1) even = false; } } if (even) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string gen[100]; string merge(string s1, string s2) { int e = s1.size() - 1; for (int i = 0; i < s2.size(); i++) { if (s1[0] == s2[i]) { int k = s2.size() - i; if (k <= s1.size()) { s1.erase(0, k); return s2 + s1; } return s2; } if (s1[e] == s2[i]) { if (e - i >= 0) { s1.erase(e - i, i + 1); return s1 + s2; } return s2; } } return 0 ; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> gen[i]; } bool f = true; for (int k = 0; k < n; k++) { f = true; while (f && gen[k] != ) { f = false; for (int i = k + 1; i < n; i++) { if (gen[i] != ) { string s; if (gen[i].length() < gen[k].length()) { s = merge(gen[i], gen[k]); } else { s = merge(gen[k], gen[i]); } if (s != 0 ) { gen[k] = s; gen[i] = ; f = true; break; } } } } } string s3; for (int i = 0; i < n; i++) { s3 += gen[i]; } cout << s3; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; int count = 0; int min = a; if (b < a) { min = b; } int x = c / min; for (int i = 0; i <= x; i++) { for (int j = 0; j <= x; j++) { if (count != 0) { break; } if (a * i + b * j == c) { count++; cout << Yes ; } } } if (count == 0) { cout << No ; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 9223372036854775807; const long long MOD = 1000000007; const long double PI = acos(-1); inline long long power(long long a, long long b, long long z = MOD) { long long res = 1; a = (a % z); while (b) { if (b & 1) res = (res * a) % z; a = (a * a) % z; b = b >> 1; } return res; } inline long long inverse(long long a, long long z = MOD) { return power(a, z - 2, z); } long long extend(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long g = extend(b, a % b, x1, y1); x = y1; y = x1 - (a / b) * y1; return g; } inline long long mat_power(long long a, long long b, long long c, long long d, long long n, long long z = MOD) { long long a0 = 1, b0 = 0, c0 = 0, d0 = 1; while (n) { if (n & 1) { long long a1 = a0, b1 = b0, c1 = c0, d1 = d0; a0 = (a1 * a + b1 * c) % z; b0 = (a1 * b + b1 * d) % z; c0 = (c1 * a + d1 * c) % z; d0 = (c1 * b + d1 * d) % z; } long long a1 = a, b1 = b, c1 = c, d1 = d; a = (a1 * a1 + b1 * c1) % z; b = (a1 * b1 + b1 * d1) % z; c = (c1 * a1 + d1 * c1) % z; d = (c1 * b1 + d1 * d1) % z; n = n >> 1; } return c0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; int aray[n][m], arr[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> aray[i][j]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> arr[i][j]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (aray[i][j] > arr[i][j]) swap(aray[i][j], arr[i][j]); } } for (int i = 0; i < n; i++) { for (int j = 1; j < m; j++) { if (aray[i][j] <= aray[i][j - 1] || arr[i][j] <= arr[i][j - 1]) { cout << Impossible n ; return 0; } } } for (int j = 0; j < m; j++) { for (int i = 1; i < n; i++) { if (aray[i][j] <= aray[i - 1][j] || arr[i][j] <= arr[i - 1][j]) { cout << Impossible n ; return 0; } } } cout << Possible n ; return 0; }
|
// USED ONLY TO SELECT PL BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 4;
parameter WB = 4;
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
genvar i,j;
wire [WA*WB-1:0] selected;
generate
for (i=0; i<WA; i=i+1) begin:ol
for (j=0; j<WB; j=j+1) begin:il
assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
end
end
endgenerate
assign selected_bit=|selected;
endmodule // unary_select_pair
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O31A_PP_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__decap (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_4_V
`define SKY130_FD_SC_HVL__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_4_V
|
// ----------------------------------------------------------------------------------
// -- Company: The Most Awesome Mad Scientist Ever
// -- Engineer: Rongcui Dong
// --
// -- Create Date: 06/29/2017 07:16:10 PM
// -- Design Name:
// -- Module Name: BRAM
// -- Project Name:
// -- Target Devices:
// -- Tool Versions:
// -- Description:
// --
// -- Dependencies:
// --
// -- Revision:
// -- Revision 0.01 - File Created
// -- Additional Comments:
// -- This is a single port BRAM
// ----------------------------------------------------------------------------------
module BRAM_sp(
clk, we, en, addr, data_in, data_out
);
parameter WIDTH = 8, DEPTH = 1024, DEPTH_LOG = 10;
input wire clk;
input wire we;
input wire en;
input wire [WIDTH-1:0] data_in;
output reg [WIDTH-1:0] data_out;
// Internal storage
reg [WIDTH-1:0] data [0:DEPTH-1];
always @ (posedge clk) begin
if (en) begin
if (we) begin
data[addr] <= data_in;
data_out <= di;
end
else begin
data_out <= data[addr];
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; int flag = 1; int st; char c = s[0]; for (int i = 1; i < n; i++) { if (s[i] == c) continue; else { st = i; flag = 0; break; } } if (flag == 1) { cout << (n + 2) / 3 << endl; continue; } int ans = 0; int m = 1; c = s[st]; int val = (st + 1) % n; for (int i = val; i != st; i = ((i + 1) % n)) { if (s[i] == c) { m++; } else { if (m >= 3) ans += (m) / 3; c = s[i]; m = 1; } } if (m >= 3) ans += (m / 3); cout << ans << endl; } return 0; }
|
`timescale 1ns/1ps
`include "../global.v"
module FPU_top_int2fp_tb();
reg clk, reset;
reg [3:0] opCode;
reg [1:0] roundingMode;
reg [31:0] A;
reg [31:0] B;
reg [31:0] ER; //expected result
wire resultReady;
wire [31:0] result;
wire invalidOperation, divisionByZero, overflow, underflow, inexact;
integer file;
//instantiate DUT
FPU_top DUT(clk, reset, opCode, roundingMode, A, B, resultReady, result,
invalidOperation, divisionByZero, overflow, underflow, inexact);
//clock
parameter HCP = 10;
initial forever begin
#HCP clk = ~clk;
end
initial begin
clk = 1'b0;
reset = 1'b1;
$display("---------------- Int->Float automatic testbench ----------------");
B = 32'h00000000;//don't care
$display("UI2FP");
opCode = `FPU_INSTR_UI2FP;
roundingMode = `ROUNDING_MODE_TRUNCATE;
file = $fopen("test/ui2fp/trunc/ui2fp-vectors.txt", "r"); runSingleFile(file, 30);
$display("SI2FP");
opCode = `FPU_INSTR_SI2FP;
roundingMode = `ROUNDING_MODE_TRUNCATE;
//file = $fopen("test/si2fp/trunc/si2fp-vectors.txt", "r"); runSingleFile(file, 30);
#20 $finish;
end
task runSingleFile;
input integer file;
input integer vectorCount;
integer status, cnt, errorCount;
begin
cnt = 0;
errorCount = 0;
while (cnt < vectorCount) begin
status = $fscanf(file, "%x\t%x\n", A[31:0], ER[31:0]);
#(2*HCP) reset = 1'b0;
@(posedge resultReady) #1;
if (ER !== result) begin
$display("Vector %d: Wrong result!", cnt);
$display("A: %d\n", A);
$display("ER: %b\t%x\t%b\n", ER[31], ER[30:23], ER[22:0]);
$display("R: %b\t%x\t%b\n", result[31], result[30:23], result[22:0]);
errorCount = errorCount + 1;
end else begin
/*$display("Vector %d: Correct result", cnt);
$display("A: %d\n", A);
$display("ER: %b\t%x\t%b (%x)\n", ER[31], ER[30:23], ER[22:0], ER);
$display("R: %b\t%x\t%b (%x)\n", result[31], result[30:23], result[22:0], result);*/
end
reset = 1'b1;
cnt = cnt + 1;
end
$display("Finished, %d vectors simulated, %d error(s)", cnt, errorCount);
$fclose(file);
end
endtask
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 17 14:34:16 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_a_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_d_o = ctrl_a_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
NAND3X1TS U4 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NOR3X1TS U5 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NOR2X1TS U6 ( .A(n16), .B(state_reg[3]), .Y(n51) );
AOI21X1TS U7 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
NOR3BX1TS U8 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NAND3X1TS U9 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U10 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U11 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND2X1TS U12 ( .A(n43), .B(n27), .Y(load_5_o) );
NOR2BX1TS U13 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U14 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
INVX2TS U15 ( .A(n43), .Y(ctrl_c_o) );
INVX2TS U16 ( .A(n20), .Y(ready) );
OAI21X1TS U17 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
INVX2TS U18 ( .A(n40), .Y(load_2_o) );
INVX2TS U19 ( .A(n22), .Y(n10) );
INVX2TS U20 ( .A(n32), .Y(n8) );
NAND2X1TS U21 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U22 ( .A(n50), .B(n51), .Y(n27) );
INVX2TS U23 ( .A(n41), .Y(n4) );
INVX2TS U24 ( .A(n29), .Y(n7) );
INVX2TS U25 ( .A(n39), .Y(rst_int) );
INVX2TS U26 ( .A(n44), .Y(load_6_o) );
NOR4XLTS U27 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
NAND2X1TS U28 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U29 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
AOI211X1TS U30 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND2X1TS U31 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND4X1TS U32 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
OAI21X1TS U33 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
OAI2BB1X1TS U34 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U35 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
INVX2TS U36 ( .A(n28), .Y(ctrl_a_o) );
OAI22X1TS U37 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U38 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U39 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U40 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35) );
INVX2TS U41 ( .A(round_i), .Y(n19) );
NAND4X1TS U42 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U43 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U44 ( .A(n31), .Y(n11) );
NOR2X1TS U45 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NAND3X1TS U46 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U47 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U48 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
NAND3X1TS U49 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
AOI31X1TS U50 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
INVX2TS U51 ( .A(n36), .Y(n2) );
AOI2BB1X1TS U52 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
NOR3X1TS U53 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AND2X2TS U54 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
NOR2X1TS U55 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U56 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U57 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52)
);
NAND3X1TS U58 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U59 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U60 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U61 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U62 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U63 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U64 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND2X1TS U65 ( .A(round_i), .B(n25), .Y(n28) );
INVX2TS U66 ( .A(norm_iteration_i), .Y(n18) );
endmodule
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5_FSM_Add_Subtract (
clk, rst, beg_FSM, ack_FSM, Data_X, Data_Y, add_subt, r_mode,
overflow_flag, underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
FSM_Add_Subtract FS_Module ( .clk(clk), .rst(rst), .rst_FSM(ack_FSM),
.beg_FSM(beg_FSM), .zero_flag_i(1'b0), .norm_iteration_i(1'b0),
.add_overflow_i(1'b0), .round_i(1'b0), .ready(ready) );
endmodule
|
#include <bits/stdc++.h> using namespace std; long long modpow(long long b, long long e, long long mod) { long long ans = 1; for (; e; b = b * b % mod, e /= 2) if (e & 1) ans = ans * b % mod; return ans; } const int N = 5050; int dp[N][N][2], c[N], n; bool vis[N][N][2]; int solve(int x, int y, int z) { if (x < 0 || y > n || x > y) return (int)1e9; if (x == 1 && y == n) return 0; if (vis[x][y][z]) return dp[x][y][z]; vis[x][y][z] = true; return dp[x][y][z] = min(solve(x - 1, y, 0) + (c[z ? y : x] == c[x - 1] ? 0 : 1), solve(x, y + 1, 1) + (c[z ? y : x] == c[y + 1] ? 0 : 1)); } int32_t main() { cin >> n; for (int i = 0; i < (n); ++i) cin >> c[i + 1]; int ans = (int)1e9; for (int i = 0; i < (n); ++i) ans = min(ans, solve(i + 1, i + 1, 0)); cout << ans << endl; }
|
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