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#include <bits/stdc++.h> using namespace std; int a[100010]; inline int read() { char c = getchar(); int x = 0, flag = 1; while (!isdigit(c)) { if (c == - ) flag = -1; c = getchar(); } while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); return x * flag; } int main() { int n = read(), k = read(), lst = 1, ans = 0; for (int i = 1; i <= n; i++) { a[i] = read(); if (a[i] == a[i - 1]) lst = i; ans = max(ans, i - lst + 1); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Node { int d; struct Node *left, *right; }; int p[1000][1000] = {0}; string s, t; void dp(int i, int j) { if (j - i + 1 == t.size()) { int f = 1; for (int z = 0; z < t.size(); z++) { if (s[i + z] != t[z]) { f = 0; break; } } if (f == 1) p[i][j] = 1; } else if (j - i + 1 < t.size()) return; else if (j - i + 1 > t.size()) { int maxm = 0, l = t.size(); for (int x = i; x <= j - l + 1; x++) { if (p[x][x + l - 1] > 0) p[i][j]++; } } return; } int main() { int n, m, q; cin >> n >> m >> q; int a[q][2]; getchar(); cin >> s; getchar(); cin >> t; for (int i = 0; i <= q - 1; i++) { cin >> a[i][0] >> a[i][1]; } int l = t.size(); for (int si = l; si <= n; si++) { for (int j = 0; j <= n - si; j++) dp(j, j + si - 1); } for (int i = 0; i <= q - 1; i++) cout << p[a[i][0] - 1][a[i][1] - 1] << n ; }
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#include <bits/stdc++.h> int a[100005]; inline int max(int x, int y) { return x > y ? x : y; } int main() { int ans = 0, n, Max, Min, Maxpos, Minpos; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int l = 1, r = 1; while (r <= n && a[r] == a[1]) r++; if (r == n + 1) return !printf( %d , n); if (a[r] > a[1]) Max = a[r], Maxpos = r, Min = a[1], Minpos = r - 1; else Max = a[1], Maxpos = r - 1, Min = a[r], Minpos = r; while (l <= r && r <= n) { while (r < n && a[r + 1] >= Min && a[r + 1] <= Max) { r++; if (a[r] == Max) Maxpos = r; else Minpos = r; } r++; ans = max(ans, r - l); if (r > n) break; if (a[r] > Max) { l = Minpos + 1; Min = Max, Minpos = Maxpos; Max = a[r], Maxpos = r; } if (a[r] < Min) { l = Maxpos + 1; Max = Min, Maxpos = Minpos; Min = a[r], Minpos = r; } } printf( %d , ans); }
|
//local memory controller
module lmcnt
(
input CLK,
input RESET_X,
//cpu
input SOFT_RESET,
input START,
output reg FINISH,
input [1:0] MSEL_INPUTA_SEL,
input [1:0] MSEL_INPUTB_SEL,
input [1:0] MSEL_OUTPUTC_SEL,
input [9:0] M1POS,
input [9:0] M1SIZE,
input [9:0] M2POS,
input [9:0] M3POS,
//local mem
input [7:0] M0_RDATA,
output M1_WR,
output [9:0] M1_WADR,
output [7:0] M1_WDATA,
output [9:0] M1_RADR,
input [7:0] M1_RDATA,
output M2_WR,
output [9:0] M2_WADR,
output [7:0] M2_WDATA,
output [9:0] M2_RADR,
input [7:0] M2_RDATA,
output M3_WR,
output [9:0] M3_WADR,
output [7:0] M3_WDATA,
output [9:0] M3_RADR,
input [7:0] M3_RDATA,
//npu
output reg NPU_EN,
output reg [7:0] A_RDATA,
output reg [7:0] B_RDATA,
input LM_EN,
input [7:0] C_WDATA
);
wire rst_x;
assign rst_x = RESET_X & ~SOFT_RESET;
reg npu_en_r;
wire npu_en_w;
assign npu_en_w = START | npu_en_r;
reg [9:0] rcnt;
reg [9:0] wcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
rcnt <= 0;
end else begin
if ((rcnt == 0) && (START == 1))begin
rcnt <= 1;
end else if((rcnt != 0) && (rcnt != 10'h3FF))begin
rcnt <= rcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
NPU_EN <= 0;
npu_en_r <= 0;
end else begin
NPU_EN <= npu_en_w;
if (START == 1)begin
npu_en_r <= 1;
end else if(rcnt == 10'h3FF)begin
npu_en_r <= 0;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
wcnt <= 0;
end else begin
if(LM_EN)begin
wcnt <= wcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
FINISH <= 0;
end else begin
if(wcnt == 10'h3FF)begin
FINISH <= 1;
end
end
end
//read
assign M1_RADR = rcnt;
assign M2_RADR = rcnt;
assign M3_RADR = rcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
A_RDATA <= 0;
end else begin
case (MSEL_INPUTA_SEL)
2'b00: A_RDATA <= M0_RDATA;
2'b01: A_RDATA <= M1_RDATA;
2'b10: A_RDATA <= M2_RDATA;
2'b11: A_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTA_SEL)
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
B_RDATA <= 0;
end else begin
case (MSEL_INPUTB_SEL)
2'b00: B_RDATA <= M0_RDATA;
2'b01: B_RDATA <= M1_RDATA;
2'b10: B_RDATA <= M2_RDATA;
2'b11: B_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTB_SEL)
end
end
//write
assign M1_WR = (MSEL_OUTPUTC_SEL == 2'b01) ? LM_EN : 0;
assign M2_WR = (MSEL_OUTPUTC_SEL == 2'b10) ? LM_EN : 0;
assign M3_WR = (MSEL_OUTPUTC_SEL == 2'b11) ? LM_EN : 0;
assign M1_WADR = wcnt;
assign M2_WADR = wcnt;
assign M3_WADR = wcnt;
assign M1_WDATA = C_WDATA;
assign M2_WDATA = C_WDATA;
assign M3_WDATA = C_WDATA;
endmodule // lmcnt
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; a = abs(a - b); b = a / 2; a = a / 2 + (a & 1); cout << (a * a + a) / 2 + (b * b + b) / 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[1003]; int main() { int n, x, ans, sum, t, ck; cin >> t; while (t--) { cin >> n >> x; for (int i = 1; i <= n; i++) cin >> arr[i]; sort(arr + 1, arr + n + 1); ck = 0; for (int i = 1; i <= n; i++) { if (arr[i] == x) ck = 1; } sum = 0; for (int i = 1; i <= n; i++) sum += (arr[i] - x); if (arr[1] == arr[n] && arr[n] == x) ans = 0; else if (sum == 0 || ck) ans = 1; else ans = 2; cout << ans << endl; } return 0; }
|
`include "rv32_opcodes.vh"
`include "constants.vh"
`default_nettype none
module src_a_mux(
input wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] rs1,
output reg [`DATA_LEN-1:0] alu_src_a
);
always @(*) begin
case (src_a_sel)
`SRC_A_RS1 : alu_src_a = rs1;
`SRC_A_PC : alu_src_a = pc;
default : alu_src_a = 0;
endcase // case (src_a_sel)
end
endmodule // src_a_mux
module src_b_mux(
input wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel,
input wire [`DATA_LEN-1:0] imm,
input wire [`DATA_LEN-1:0] rs2,
output reg [`DATA_LEN-1:0] alu_src_b
);
always @(*) begin
case (src_b_sel)
`SRC_B_RS2 : alu_src_b = rs2;
`SRC_B_IMM : alu_src_b = imm;
`SRC_B_FOUR : alu_src_b = 4;
default : alu_src_b = 0;
endcase // case (src_b_sel)
end
endmodule // src_b_mux
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; long long dp[100003][3], ara[100003], mod = 1000000007, n, m; long long solve(long long idx, long long sta) { if (idx == n) { if (sta == 0 || sta == 2) return 1; else { return 0; } } else if (dp[idx][sta] != -1) return dp[idx][sta]; else { long long p = 0, q = 0, r = 0, t, x, y, z; if (sta == 0) { p = solve(idx + 1, 0); x = 1; z = idx + 1; if (ara[idx] == 1) { x = 2; z = idx + m; } q = solve(z, x); } else if (sta == 1) { x = 1; z = idx + 1; if (ara[idx] == 1) { x = 2; z = idx + m; } q = solve(z, x); } else { p = solve(idx, 0); q = solve(idx + 1, sta); } t = (p + q) % mod; dp[idx][sta] = t; return dp[idx][sta]; } } int main() { long long i, k, ans = 1, sc = 1; string str, ttr, ntr; cin >> str; cin >> ttr; n = str.size(); m = ttr.size(); if (n >= m) { for (i = 0; i <= n - m; i++) { if (str[i] == ttr[0]) { ntr = str.substr(i, m); if (ntr == ttr) { ara[i] = 1; } } dp[i][0] = -1; dp[i][1] = -1; dp[i][2] = -1; } } if (n >= m) { for (i = n - m; i <= n; i++) { dp[i][0] = -1; dp[i][1] = -1; dp[i][2] = -1; } ans = solve(0, 0); } if (ans >= sc) k = ans - sc; else { k = (mod - sc) + ans; } printf( %lld n , k); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h98967;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 35175;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 9;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, l = -1, j, p, m; long k; cin >> n >> k; long long a[k]; for (long i = 0; i < k; i++) { cin >> a[i]; j = n / a[i]; if ((j * a[i]) > l) { l = j * a[i]; p = i + 1; m = j; } } cout << p << << m << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define IOS ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #define int long long #define line cout<< [At <<__LINE__<< ] <<endl; #define size(x) ((int)x.size()) namespace Debug{ void __print(signed x){cout << x;} void __print(long x){cout << x;} void __print(long long x){cout << x;} void __print(unsigned x){cout << x;} void __print(unsigned long x){cout << x;} void __print(unsigned long long x){cout << x;} void __print(float x){cout << x;} void __print(double x){cout << x;} void __print(long double x){cout << x;} void __print(char x){cout << << x << ;} void __print(const char *x){cout << << x << ;} void __print(const string &x){cout << << x << ;} void __print(bool x){cout << (x ? true : false );} template<typename T, typename V> void __print(const pair<T, V> &x){cout << { ;__print(x.first);cout << , ;__print(x.second);cout << } ;} template<typename T> void __print(const T &x){int f = 0;cout << { ;for (auto &i : x) cout << (f++ ? , : ), __print(i);cout << } ;} void _print(){cout << ] <<endl;} template <typename T, typename... V> void _print(T t, V... v){__print(t);if (sizeof...(v)) cout << , ;_print(v...);} #define debug(x...) cout << Line: <<__LINE__<< [ << #x << ] = [ ; _print(x); #define deb(x...) cout << [ << #x << ] = [ ; _print(x); }using namespace Debug; const int mod = (int)1e9 + 7ll; int dp[2000][2000][2], n; int shoot(int plane, int k, int dir){ if(plane > n || plane < 1 || k == 1) return 1l; if(dp[plane][k][dir] != -1) return dp[plane][k][dir]; int res = 0l; if(dir == 0){ res = shoot(plane + 1, k, dir); res += shoot(plane - 1, k - 1, 1 - dir); } else{ res = shoot(plane - 1, k, dir); res += shoot(plane + 1, k - 1, 1 - dir); } res %= mod; return dp[plane][k][dir] = res; } void process(){ int k; cin >> n >> k; cout << shoot(1, k, 0) << n ; } signed main() { IOS; int t = 1; cin >> t; while(t--){ memset(dp, -1, sizeof(dp)); process(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_s.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__srsdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
wire kapwr ;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s `UNIT_DELAY dff0 (buf_Q , mux_out, CLK_N, RESET, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; inline long long Getint() { char ch = getchar(); long long x = 0, fh = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) fh = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { (x *= 10) += ch ^ 48; ch = getchar(); } return x * fh; } const long long mod = 998244353; const int N = 400005; inline long long Inc(long long x, long long y) { return (x += y) >= mod ? x - mod : x; } inline long long Dec(long long x, long long y) { return (x -= y) < 0 ? x + mod : x; } inline long long Ksm(long long x, long long y) { long long tmp = 1; while (y) { if (y & 1) tmp = tmp * x % mod; y >>= 1; if (y) x = x * x % mod; } return tmp; } long long K, n, fc[N], fiv[N], inv[N]; vector<int> G[N]; int lst, rev[N]; long long pwi[2][25], wn[N]; inline void initpw() { for (int i = 1, k = 0; i < N; i <<= 1, k++) { pwi[0][k] = Ksm(3, (mod - 1) / (i << 1)); pwi[1][k] = Ksm(3, -(mod - 1) / (i << 1) + mod - 1); } } inline int Make(int len) { return 1 << int(ceil(log2(len))); } inline int Trans(int len) { int l = ceil(log2(len)); len = 1 << l; for (int i = 0; i <= len - 1; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << l - 1); return lst = len; } inline void NTT(vector<long long> &F, int fir, int len, int f) { if (lst != len) Trans(len); if (f == 1) F.resize(len); for (int i = 0; i <= len - 1; i++) if (rev[i] < i) swap(F[rev[i]], F[i]); for (int i = 1, k = 0; i < len; i <<= 1, k++) { long long wi = f == 1 ? pwi[0][k] : pwi[1][k]; wn[0] = 1; for (int j = 1; j <= i - 1; j++) wn[j] = wn[j - 1] * wi % mod; for (int j = 0; j < len; j += i << 1) { for (int k = 0; k < i; k++) { long long x = F[j + k], y = F[i + j + k] * wn[k] % mod; F[j + k] = Inc(x, y); F[i + j + k] = Dec(x, y); } } } if (f == 1) return; long long iv = inv[len]; for (int i = 0; i <= fir - 1; i++) F[i] = F[i] * iv % mod; F.resize(fir); } inline vector<long long> operator*(vector<long long> A, vector<long long> B) { if (A.size() == 0) return A; if (B.size() == 0) return B; int len = A.size() + B.size() - 1, l = Make(len); NTT(A, A.size(), l, 1); NTT(B, B.size(), l, 1); for (int i = 0; i <= l - 1; i++) A[i] = A[i] * B[i] % mod; NTT(A, len, l, -1); return A; } vector<long long> F[N], Lt; map<int, long long> mp[N]; inline long long Div(int u, int sz) { if (mp[u].count(sz)) return mp[u][sz]; vector<long long> A = F[u]; vector<long long> C(A.size() - 1); long long iv = inv[sz]; for (int i = int(A.size()) - 1; i >= 1; i--) { C[i - 1] = A[i] * iv % mod; A[i - 1] = Dec(A[i - 1], C[i - 1]); } long long tmp = 0; for (int i = 0; i <= int(C.size()) - 1; i++) { if (i > K) break; (tmp += C[i] * fiv[K - i]) %= mod; } return mp[u][sz] = tmp; } inline vector<long long> CDQ1(int l = 0, int r = int(Lt.size()) - 1) { if (r < l) { vector<long long> t(1); t[0] = 1; return t; } else if (l == r) { vector<long long> t(2); t[1] = Lt[l]; t[0] = 1; return t; } int mid = l + r >> 1; return CDQ1(l, mid) * CDQ1(mid + 1, r); } int sz[N]; long long dp[N]; void Dfs1(int u, int fa) { sz[u] = 1; dp[u] = 0; for (int v : G[u]) { if (v == fa) continue; Dfs1(v, u); sz[u] += sz[v]; dp[u] = Inc(dp[u], dp[v]); } Lt.clear(); for (int v : G[u]) { if (v == fa) continue; Lt.push_back(sz[v]); } if (fa) Lt.push_back(n - sz[u]); F[u] = CDQ1(); if (fa) { dp[u] = Inc(dp[u], Div(u, n - sz[u])); } else { for (int i = 0; i <= int(F[u].size()) - 1; i++) { if (i > K) break; (dp[u] += F[u][i] * fiv[K - i]) %= mod; } } } long long Ans = 0; void Dfs2(int u, int fa) { long long su = 0; for (int v : G[u]) { if (v == fa) continue; Dfs2(v, u); (Ans += su * dp[v]) %= mod; su = Inc(su, dp[v]); } for (int v : G[u]) { if (v == fa) continue; long long val = Div(u, sz[v]); (Ans += val * dp[v]) %= mod; } } int main() { int x, y, z; fc[0] = fc[1] = inv[0] = inv[1] = fiv[0] = fiv[1] = 1; for (int i = 2; i <= N - 1; i++) { fc[i] = fc[i - 1] * i % mod; inv[i] = (mod - mod / i) * inv[mod % i] % mod; fiv[i] = fiv[i - 1] * inv[i] % mod; } initpw(); n = Getint(); K = Getint(); for (int i = 2; i <= n; i++) { x = Getint(); y = Getint(); G[x].push_back(y); G[y].push_back(x); } if (K == 1) { cout << n * (n - 1) / 2 % mod << n ; return 0; } Dfs1(1, 0); Dfs2(1, 0); Ans = Ans % mod * Ksm(fc[K], 2) % mod; cout << (Ans % mod + mod) % mod << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x7fffffff; long long a[510][510], n; int main() { while (~scanf( %I64d , &n)) { if (n == 1) { scanf( %I64d , &n); printf( 1 n ); continue; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) scanf( %I64d , &a[i][j]); } int zr = 0, zc; for (int i = 1; i <= n && !zr; ++i) { for (int j = 1; j <= n && !zr; ++j) { if (a[i][j] == 0) { zr = i; zc = j; } } } long long zv, sum = 0, zsum = 0; for (int i = 1; i <= n; ++i) zsum += a[zr][i]; if (zr == 1) { for (int i = 1; i <= n; ++i) sum += a[n][i]; zv = sum - zsum; } else { for (int i = 1; i <= n; ++i) sum += a[1][i]; zv = sum - zsum; } if (zv <= 0) { printf( -1 n ); continue; } a[zr][zc] = zv; bool ok = true; for (int i = 1; i <= n; ++i) { long long tmpsum = 0; for (int j = 1; j <= n; ++j) tmpsum += a[i][j]; if (tmpsum != sum) { ok = false; break; } tmpsum = 0; for (int j = 1; j <= n; ++j) tmpsum += a[j][i]; if (tmpsum != sum) { ok = false; break; } } long long tmpsum = 0; for (int i = 1; i <= n; ++i) tmpsum += a[i][i]; if (tmpsum != sum) ok = false; tmpsum = 0; for (int i = n; i >= 1; --i) tmpsum += a[i][n + 1 - i]; if (tmpsum != sum) ok = false; if (ok) { printf( %I64d n , zv); } else printf( -1 n ); } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ddr2um_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr2um_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [127:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire [127:0] q = sub_wire0[127:0];
wire rdempty = sub_wire1;
wire [9:0] wrusedw = sub_wire2[9:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrusedw (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "128"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long rand_seed() { long long a = rng(); return a; } int t; int n; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> t; for (; t; --t) { cin >> n; cin >> s; bool ok = 0; for (int i = 0; i + 10 < n; ++i) if (s[i] == 8 ) ok = 1; if (ok) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, n; cin >> a >> n; int tilln = (1LL * n * (n - 1) / 2) % 1000000007, tilla = (1LL * a * (a + 1) / 2) % 1000000007; cout << ((((((1LL * tilln) % 1000000007) * tilla) % 1000000007) * n) % 1000000007 + (1LL * a * tilln) % 1000000007) % 1000000007 << endl; return 0; }
|
#include <bits/stdc++.h> int main(void) { char s[30], t[30], s1[30], s2[30]; scanf( %s %s , s, t); int i = 0, c1 = 0, c2 = 0, c3 = 0; while (s[i] != | ) { s1[c1++] = s[i]; i++; } i++; while (s[i] != 0 ) { s2[c2++] = s[i]; i++; } i = 0; while (t[i++] != 0 ) c3++; if ((c1 + c2 + c3) % 2 == 1) printf( Impossible ); else { i = 0; while (t[i] != 0 ) { if (c1 > c2) { s2[c2++] = t[i++]; } if (c1 <= c2 && t[i] != 0 ) s1[c1++] = t[i++]; } if (c1 != c2) printf( Impossible ); else { s1[c1] = 0 ; s2[c2] = 0 ; printf( %s|%s , s1, s2); } } return 0; }
|
`timescale 1ns / 1ps
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
Jose Tejada Dec 2014:
Added parity and error signal
Modified to work at 230400 bps with 50MHz clock
230400 does not work on the implemented device. Both RX and TX seem to be failing
The reason could be electrical: signal loss through the cable. But I have not verified it
Jose Tejada June 2016
Parity removed.
*/
module uart_transceiver(
input sys_rst,
input sys_clk,
input uart_rx,
output reg uart_tx, // serial signal to transmit. High when idle
input [4:0] uart_divider, /* number of divisions of the UART bit period */
input [4:0] clk_divider, /* Division of the system clock
For a 50MHz system clock use:
clk_divider = 28, uart_divider = 30 -> 57kbps, 0.01% timing error
clk_divider = 14, uart_divider = 30 -> 115kbps, 0.01% timing error
clk_divider = 7, uart_divider = 30 -> 230kbps, 0.01% timing error
*/
output reg [7:0] rx_data,
output reg rx_done,
output reg rx_error,
output reg [7:0] rx_error_count,
input [7:0] tx_data,
input tx_wr,
output reg tx_done
);
//-----------------------------------------------------------------
// slow_clk generator... this is actually a 32-module counter
//-----------------------------------------------------------------
reg [4:0] clk_counter;
wire slow_clk;
assign slow_clk = !clk_counter;
always @(posedge sys_clk or posedge sys_rst) begin : clock_divider
if(sys_rst)
clk_counter <= clk_divider - 4'b1;
else begin
clk_counter <= clk_counter - 4'd1;
if(slow_clk)
clk_counter <= clk_divider - 4'b1;
end
end
//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;
always @(posedge sys_clk) begin : synchronizer
uart_rx1 <= uart_rx;
uart_rx2 <= uart_rx1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [4:0] rx_divcount;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;
always @(posedge sys_clk or posedge sys_rst) begin : error_count
if( sys_rst ) begin
rx_error_count <= 8'd0;
end
else begin
if( rx_done && rx_error ) rx_error_count <= rx_error_count + 1'd1;
end
end
always @(posedge sys_clk or posedge sys_rst) begin : rx_logic
if(sys_rst) begin
rx_done <= 1'b0;
rx_busy <= 1'b0;
rx_divcount <= 5'd0;
rx_bitcount <= 4'd0;
rx_data <= 8'd0;
rx_reg <= 8'd0;
rx_error <= 1'b0;
end else begin
rx_done <= 1'b0;
if(slow_clk) begin
if(~rx_busy) begin // look for start bit
if(~uart_rx2) begin // start bit found
rx_busy <= 1'b1;
rx_divcount <= { 1'b0, uart_divider[4:1] }; // middle bit period
rx_bitcount <= 4'd0;
rx_reg <= 8'h0;
end
end else begin
if( !rx_divcount ) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
rx_divcount <= uart_divider; // start to count down from top again
rx_error <= 1'b0;
case( rx_bitcount )
4'd0: // verify startbit
if(uart_rx2)
rx_busy <= 1'b0;
4'd9: begin // stop bit
rx_busy <= 1'b0;
if(uart_rx2) begin // stop bit ok
rx_data <= rx_reg;
rx_done <= 1'b1;
end else begin // RX error
rx_done <= 1'b1;
rx_error <= 1'b1;
end
end
default: // shift data in
rx_reg <= {uart_rx2, rx_reg[7:1]};
endcase
end
else rx_divcount <= rx_divcount - 1'b1;
end
end
end
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [4:0] tx_divcount;
reg [7:0] tx_reg;
always @(posedge sys_clk or posedge sys_rst) begin :tx_logic
if(sys_rst) begin
tx_done <= 1'b0;
tx_busy <= 1'b0;
uart_tx <= 1'b1;
end else begin
tx_done <= 1'b0;
if(tx_wr) begin
tx_reg <= tx_data;
tx_bitcount <= 4'd0;
tx_divcount <= uart_divider;
tx_busy <= 1'b1;
uart_tx <= 1'b0;
`ifdef SIMULATION
// $display("UART: send%c", tx_data);
`endif
end else if(slow_clk && tx_busy) begin
if( !tx_divcount ) begin
tx_bitcount <= tx_bitcount + 4'd1;
tx_divcount <= uart_divider; // start to count down from top again
if( tx_bitcount < 4'd8 ) begin
uart_tx <= tx_reg[0];
tx_reg <= {1'b0, tx_reg[7:1]};
end
else begin
uart_tx <= 1'b1; // 8 bits sent, now 1 or more stop bits
if( tx_bitcount==4'd10 ) begin
tx_busy <= 1'b0;
tx_done <= 1'b1;
end
end
end
else tx_divcount <= tx_divcount - 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const bool ready = []() { ios_base::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(12); return true; }(); const double PI = acos(-1); using ll = long long; using pii = pair<ll, ll>; using pdd = pair<double, double>; using vd = vector<double>; using vb = vector<bool>; using vi = vector<ll>; using vvi = vector<vi>; using vs = vector<string>; void solve() { ll n; cin >> n; ; ll m; cin >> m; ; vb sx(n + 1); vb sy(n + 1); for (ll i = 0; i < m; i++) { ll x; cin >> x; ; ll y; cin >> y; ; sx[x] = true; sy[y] = true; } ll ans = 0; for (ll i = 2; i < n / 2 + 1; i++) { if (!sy[n - i + 1]) ans++; if (!sy[i]) ans++; if (!sx[n - i + 1]) ans++; if (!sx[i]) ans++; } if (n & 1) { if ((!sx[n / 2 + 1]) || (!sy[n / 2 + 1])) ans++; } cout << ans << endl; } signed main() { solve(); }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_async_fifo
*/
module test_axis_async_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
async_rst,
s_clk,
m_clk,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_async_fifo.lxt");
$dumpvars(0, test_axis_async_fifo);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return a ? gcd(b % a, a) : b; } int main() { string s; cin >> s; int a[26] = {0}; for (int i = 0; i < s.length(); i++) a[s[i] - a ]++; string ans = s; for (int i = 0; i < s.length(); i++) ans[i] = # ; for (int i = 1; i < s.length(); i++) { if (ans[i] != # ) continue; int m = 0; for (int j = 1; j < 26; j++) if (a[j] > a[m]) m = j; for (int j = 0; j < s.length(); j++) if (ans[j] != # && gcd(i + 1, j + 1) != 1) m = ans[j] - a ; for (int j = 0; j < s.length(); j++) if (ans[j] == # && gcd(i + 1, j + 1) != 1) if (a[m] > 0) { ans[j] = char(m + a ); a[m]--; } else { cout << NO ; return 0; } } for (int j = 0; j < 26; j++) if (a[j]) ans[0] = char(j + a ); cout << YES n + ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int Q; cin >> Q; while (Q-- > 0) { int n; cin >> n; vector<int> dp(2001, inf); dp[0] = 0; for (int i = 0; i < n; ++i) { int a; cin >> a; vector<int> aux(dp); fill(dp.begin(), dp.end(), inf); for (int j = 0; j < 2001; ++j) { if (aux[j] != inf) { dp[max(0, j - a)] = min(dp[max(0, j - a)], aux[j] + a); if (j + a < 2001) { dp[j + a] = min(dp[j + a], max(0, aux[j] - a)); } } } } int res = inf; for (int i = 0; i <= 2000; ++i) { if (dp[i] != inf) { res = min(res, i + dp[i]); } } cout << res << n ; } return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: gsu_umult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_umult (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); const double EPS = 1e-9; const int MOD = 1000003; const int INF = 1000000000; const long long LINF = 1000000000000000000LL; vector<string> vs; bool row[500010], col[500010]; int main() { int n, m, ret = 1; cin >> n >> m; string str; for (int i = int(0); i <= int(n - 1); i++) { cin >> str, vs.push_back(str); for (int j = int(0); j <= int(m - 1); j++) if (vs[i][j] != . ) row[i] = col[j] = true; } bool val = true, par; for (int i = int(0); i <= int(n - 1); i++) { if (!row[i]) ret = 2 * ret % MOD; else { for (int j = int(0); j <= int(m - 1); j++) if (vs[i][j] != . ) par = (vs[i][j] < 3 && j % 2 == 0) || (vs[i][j] >= 3 && j % 2); for (int j = int(0); j <= int(m - 1); j++) if (vs[i][j] != . ) { if (j % 2) val &= par ? vs[i][j] >= 3 : vs[i][j] < 3 ; else val &= par ? vs[i][j] < 3 : vs[i][j] >= 3 ; } } } for (int j = int(0); j <= int(m - 1); j++) { if (!col[j]) ret = 2 * ret % MOD; else { for (int i = int(0); i <= int(n - 1); i++) if (vs[i][j] != . ) par = ((vs[i][j] == 1 || vs[i][j] == 4 ) && i % 2 == 0) || (!(vs[i][j] == 1 || vs[i][j] == 4 ) && i % 2); for (int i = int(0); i <= int(n - 1); i++) if (vs[i][j] != . ) { if (i % 2) val &= par ? !(vs[i][j] == 1 || vs[i][j] == 4 ) : (vs[i][j] == 1 || vs[i][j] == 4 ); else val &= par ? (vs[i][j] == 1 || vs[i][j] == 4 ) : !(vs[i][j] == 1 || vs[i][j] == 4 ); } } } if (!val) ret = 0; printf( %d n , ret); return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// or1200_fpu_intfloat_conv_except ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// Modified by Julius Baxter, July, 2010 ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module or1200_fpu_intfloat_conv_except
(
clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn
);
input clk;
input [31:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other
// special number
//
always @(posedge clk)
expa_ff <= &expa;
always @(posedge clk)
expb_ff <= &expb;
always @(posedge clk)
infa_f_r <= !(|fracta);
always @(posedge clk)
infb_f_r <= !(|fractb);
always @(posedge clk)
qnan_r_a <= fracta[22];
always @(posedge clk)
snan_r_a <= !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= fractb[22];
always @(posedge clk)
snan_r_b <= !fractb[22]; // & |fractb[21:0];
always @(posedge clk)
ind <= (expa_ff & infa_f_r); // & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= (expa_ff & infa_f_r); // | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= (expa_ff & snan_r_a); // | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= !(|expa);
always @(posedge clk)
expb_00 <= !(|expb);
always @(posedge clk)
fracta_00 <= !(|fracta);
always @(posedge clk)
fractb_00 <= !(|fractb);
always @(posedge clk)
opa_00 <= expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= expa_00;
always @(posedge clk)
opb_dn <= expb_00;
endmodule // or1200_fpu_intfloat_conv_except
|
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart3_rx #(parameter real CLK_FREQ = 357e6, parameter real BAUD = 9600, parameter WIDTH = 8, parameter PARITY = 0, parameter STOP_BITS = 1) (
//input reset,
input clk,
input uld_rx_data,
output reg [WIDTH-1:0] rx_data = {WIDTH{1'b0}},
//input rx_enable,
input rx_in,
output reg byte_rdy = 1'b0
);
//Variable/custom Baud rate little-endian 8N1 UART-RX
`include "bits_to_fit.v"
//`ifdef ML505 localparam real CLK_FREQ = 100e6;
//`else localparam real CLK_FREQ = 40e6;
//`endif
localparam CLK16X_CNT_SIZE = bits_to_fit(CLK_FREQ/(16*BAUD));
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+PARITY+STOP_BITS+1);
localparam [CLK16X_CNT_SIZE-1:0] CLK16X_WIDTH = CLK_FREQ/(16*BAUD);
//localparam [BAUD_CNT_SIZE-1:0] FRAME_MIDPOINT = FRAME_WIDTH/2;
// Internal registers
reg [WIDTH-1:0] rx_reg = {WIDTH{1'b0}};
reg [CLK16X_CNT_SIZE-1:0] rx_sample_cnt = {CLK16X_CNT_SIZE{1'b0}};
reg [BIT_CNT_SIZE-1:0] rx_cnt = {BIT_CNT_SIZE{1'b0}};
reg [3:0] Baud_ctr = 4'd0;
(* ASYNC_REG = "true" *) reg rx_da = 1'b1, rx_db = 1'b1;
reg rx_busy = 1'b0;
// UART RX Logic - with 16X Baud Clock
always @ (posedge clk) begin
// Synchronize the asynch signal
rx_da <= rx_in;
rx_db <= rx_da;
// drive the ouptut register when requested
rx_data <= (uld_rx_data) ? rx_reg : rx_data;
/*if (reset) begin
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= {BIT_CNT_SIZE{1'b0}};
byte_rdy <= 1'b0;
rx_busy <= 1'b0;
end else begin // if (~reset)*/
if (rx_busy) begin //drive logic, counters etc
if (rx_sample_cnt == CLK16X_WIDTH) begin
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= Baud_ctr + 1'b1;
rx_cnt <= (Baud_ctr == 4'd15) ? rx_cnt + 1'b1 : rx_cnt;
if (Baud_ctr == 4'd7)
case(rx_cnt)
{BIT_CNT_SIZE{1'b0}}: begin
rx_busy <= ~rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
WIDTH+PARITY+STOP_BITS: begin
rx_busy <= 1'b0;
byte_rdy <= rx_db;
end
default: begin
rx_reg[rx_cnt - 1'b1] <= rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
endcase
else /*if (Baud_ctr!=7) */ byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end else begin // if (rx_sample_cnt != CLK16X_WIDTH)
rx_sample_cnt <= rx_sample_cnt + 1'b1;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
end else begin //if (~rx_busy)
rx_busy <= ~rx_db; //detect space on line as start of START bit
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= 4'd0;
rx_cnt <= 1'b0;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end // if (~rx_busy)
//end //if (~reset)
end //always
endmodule
|
#include <bits/stdc++.h> using namespace std; char str[1000005]; int main() { while (scanf( %s , str) != EOF) { int i, len = strlen(str); long long m, l = 0, r = 0; for (i = 0; i < len; i++) if (str[i] == ^ ) m = i; for (i = 0; i < len; i++) if (str[i] >= 1 && str[i] <= 9 ) { if (i < m) l += (m - i) * (str[i] - 0 ); else r += (i - m) * (str[i] - 0 ); } if (l > r) printf( left n ); else if (r > l) printf( right n ); else printf( balance n ); } }
|
// file: mmcm_mkid_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module mmcm_mkid_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.812*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (7.812*1*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise4;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", /period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
mmcm_mkid_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, c, b; cin >> n >> c >> b; int a[n]; for (int i = 0; i < n; i++) { a[i] = i + 1; } if (n - 2 < c + b || abs(c - b) > 1) { cout << -1 ; } else { if (c == b) { for (int i = 1; i <= 2 * c; i += 2) { swap(a[i], a[i + 1]); } } else if (c < b) { int j = b; for (int i = 0; j > 0; i += 2) { swap(a[i], a[i + 1]); j--; } } else if (c > b) { int j = c; for (int i = n - 1; j > 0; i = i - 2) { swap(a[i], a[i - 1]); j--; } } for (int i = 0; i < n; i++) { cout << a[i] << ; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long M = 4e5 + 10; long long t, n, k, p, a[M], dp[M], s[M], ans; long long bs(long long r, long long rem) { long long l = 0, mid; r++; while (r - l > 1) { mid = (r + l) / 2; if (s[mid] > rem) r = mid; else l = mid; } return l; } int32_t main() { cin >> t; while (t--) { scanf( %lld%lld%lld , &n, &p, &k); for (long long i = 1; i <= n; i++) { scanf( %lld , a + i); } sort(a + 1, a + n + 1); fill(s, s + n + 1, 0); fill(dp, dp + n + 1, 0); ans = 0; for (long long i = 1; i <= n; i++) s[i] = s[i - 1] + a[i]; for (long long i = k; i < k + k; i++) dp[i] = a[i]; for (long long i = k + k; i <= n; i++) dp[i] = dp[i - k] + a[i]; for (long long i = n; i >= k; i--) if (dp[i] <= p) ans = max(ans, i - (i % k) + bs(i % k, p - dp[i])); ans = max(ans, bs(k - 1, p)); cout << ans << endl; } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple parameterized shift register.
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
module shiftreg
#(parameter C_DEPTH=10,
parameter C_WIDTH=32,
parameter C_VALUE=0
)
(input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
wire [(C_DEPTH+1)*C_WIDTH-1:0] wDataShift;
reg [C_WIDTH-1:0] rDataShift[C_DEPTH:0];
assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
always @(posedge CLK) begin
rDataShift[0] <= WR_DATA;
end
genvar i;
generate
for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
always @(posedge CLK) begin
if(RST_IN)
rDataShift[i] <= C_VALUE;
else
rDataShift[i] <= rDataShift[i-1];
end
end
endgenerate
assign RD_DATA = wDataShift;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's reg2mem aligner ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Aligns register data to memory alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_reg2mem.v,v $
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// Internal regs and wires
//
reg [7:0] memdata_hh;
reg [7:0] memdata_hl;
reg [7:0] memdata_lh;
reg [7:0] memdata_ll;
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(regdata)
memdata_ll = regdata[7:0];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - TMDS serial stream phase aligner
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : phasealigner.v
//
// Description : This module determines whether the Spartan-6 IOSERDES
// has validate the incoming TMDS data stream
//
//
// Note:
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2006 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ns / 1ps
module phsaligner # (
parameter OPENEYE_CNT_WD = 3, // valid open eye counter width
parameter CTKNCNTWD = 7, // Control Token Counter Width
parameter SRCHTIMERWD = 12 // Idle Timer Width
)
(
input wire rst,
input wire clk,
input wire [9:0] training,
input wire [9:0] sdata, // 10 bit serial stream sync. to clk
output reg flipgear,
output reg bitslip,
output reg psaligned // FSM output
);
///////////////////////////////////////////////////////
// Control Token Detection
///////////////////////////////////////////////////////
reg rcvd_ctkn, rcvd_ctkn_q;
reg blnkbgn; //blank period begins
always @ (posedge clk) begin
rcvd_ctkn <=#1 (sdata == training);
rcvd_ctkn_q <=#1 rcvd_ctkn;
blnkbgn <=#1 !rcvd_ctkn_q & rcvd_ctkn;
end
/////////////////////////////////////////////////////
// Control Token Search Timer
//
// DVI 1.0 Spec. says periodic blanking should start
// no less than every 50ms or 20HZ
// 2^24 of 74.25MHZ cycles is about 200ms
/////////////////////////////////////////////////////
reg [(SRCHTIMERWD-1):0] ctkn_srh_timer;
reg ctkn_srh_rst; //FSM output
always @ (posedge clk) begin
if (ctkn_srh_rst)
ctkn_srh_timer <=#1 {SRCHTIMERWD{1'b0}};
else
ctkn_srh_timer <=#1 ctkn_srh_timer + 1'b1;
end
reg ctkn_srh_tout;
always @ (posedge clk) begin
ctkn_srh_tout <=#1 (ctkn_srh_timer == {SRCHTIMERWD{1'b1}});
end
/////////////////////////////////////////////////////
// Contorl Token Event Counter
//
// DVI 1.0 Spec. says the minimal blanking period
// is at least 128 pixels long in order to achieve
// synchronization
//
// HDMI reduces this to as little as 8
/////////////////////////////////////////////////////
reg [(CTKNCNTWD-1):0] ctkn_counter;
reg ctkn_cnt_rst; //FSM output
always @ (posedge clk) begin
if(ctkn_cnt_rst)
ctkn_counter <=#1 {CTKNCNTWD{1'b0}};
else
ctkn_counter <=#1 ctkn_counter + 1'b1;
end
reg ctkn_cnt_tout;
always @ (posedge clk) begin
ctkn_cnt_tout <=#1 (ctkn_counter == {CTKNCNTWD{1'b1}});
end
//////////////////////////////////////////////////////////
// Below starts the phase alignment state machine
//////////////////////////////////////////////////////////
parameter INIT = 6'b1 << 0;
parameter SEARCH = 6'b1 << 1; // Searching for control tokens
parameter BITSLIP = 6'b1 << 2;
parameter RCVDCTKN = 6'b1 << 3; // Received at one Control Token and check for more
parameter BLNKPRD = 6'b1 << 4;
parameter PSALGND = 6'b1 << 5; // Phase alignment achieved
parameter nSTATES = 6;
reg [(nSTATES-1):0] cstate = {{(nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(nSTATES-1):0] nstate;
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] state_ascii = "INIT ";
always @(cstate) begin
if (cstate == INIT ) state_ascii <= "INIT ";
else if (cstate == SEARCH ) state_ascii <= "SEARCH ";
else if (cstate == BITSLIP ) state_ascii <= "BITSLIP ";
else if (cstate == RCVDCTKN ) state_ascii <= "RCVDCTKN ";
else if (cstate == BLNKPRD ) state_ascii <= "BLNKPRD ";
else state_ascii <= "PSALGND ";
end
// synthesis translate_on
`endif
always @ (posedge clk or posedge rst) begin
if (rst)
cstate <= INIT;
else
cstate <=#1 nstate;
end
//////////////////////////////////////////////////////////
// Counter counts number of blank period detected
// in order to qualify the bitslip position
//////////////////////////////////////////////////////////
parameter BLNKPRD_CNT_WD = 1;
reg [(BLNKPRD_CNT_WD-1):0] blnkprd_cnt = {BLNKPRD_CNT_WD{1'b0}};
always @ (*) begin
case (cstate) //synthesis parallel_case full_case
INIT: begin
nstate = (ctkn_srh_tout) ? SEARCH : INIT;
end
SEARCH: begin
if(blnkbgn)
nstate = RCVDCTKN;
else
nstate = (ctkn_srh_tout) ? BITSLIP : SEARCH;
end
BITSLIP: begin
nstate = SEARCH;
end
RCVDCTKN: begin
if(rcvd_ctkn)
nstate = (ctkn_cnt_tout) ? BLNKPRD : RCVDCTKN;
else
nstate = SEARCH;
end
BLNKPRD: begin
nstate = (blnkprd_cnt == {BLNKPRD_CNT_WD{1'b1}}) ? PSALGND : SEARCH;
end
PSALGND: begin
nstate = PSALGND; // Phase aligned so hang around here
end
endcase
end
reg [2:0] bitslip_cnt;
always @ (posedge clk or posedge rst) begin
if(rst) begin
psaligned <=#1 1'b0; //phase alignment success flag
bitslip <=#1 1'b0;
ctkn_srh_rst <=#1 1'b1; //control token search timer reset
ctkn_cnt_rst <=#1 1'b1; //control token counter reset
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end else begin
case (cstate) // synthesis parallel_case full_case
INIT: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end
SEARCH: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
end
BITSLIP: begin
ctkn_srh_rst <=#1 1'b1;
bitslip <=#1 1'b1;
bitslip_cnt <=#1 bitslip_cnt + 1'b1;
flipgear <=#1 bitslip_cnt[2]; //bitslip has toggled for 4 times
end
RCVDCTKN: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b0;
end
BLNKPRD: begin
blnkprd_cnt <=#1 blnkprd_cnt + 1'b1;
end
PSALGND: begin
psaligned <=#1 1'b1;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ppl, s = 0, maxn = 0; cin >> ppl; int wel[ppl]; for (int j = 0; j < ppl; j++) { cin >> wel[j]; if (maxn < wel[j]) { maxn = wel[j]; } } for (int i = 0; i < ppl; i++) { s = s + maxn - wel[i]; } cout << s; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2123456789; int a, b, c; int n, m, k; int x, y; string s; int start[500]; int target[500]; vector<pair<int, int> > ops; int calendar[] = {0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; int search(int base, int val) { for (int i = base; i <= n; i++) if (start[i] == val) return i; } int rotate(int s, int e) { int rotations = 0; if (s == e) return 0; for (int i = s; i < e; i++) { rotations++; ops.push_back(make_pair(i, i + 1)); int tmp = start[i]; start[i] = start[i + 1]; start[i + 1] = tmp; } for (int i = e - 1; i > s; i--) { rotations++; ops.push_back(make_pair(i - 1, i)); int tmp = start[i - 1]; start[i - 1] = start[i]; start[i] = tmp; } return rotations; } int main() { cin >> n; int ans = 0; for (int i = 1; i <= n; i++) cin >> target[i]; for (int i = 1; i <= n; i++) cin >> start[i]; for (int i = 1; i <= n; i++) { int pos = search(i, target[i]); ans += rotate(i, pos); } cout << ans << endl; for (int i = 0; i < ops.size(); i++) cout << ops[i].first << << ops[i].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 9223372036854775807LL; const long double PI = acos(-1); const int MAX_N = 1e+6; const string digits = 0123456789 ; const string alph = abcdefghijklmnopqrstuvwxyz ; void solve() { long long n, root, answer; cin >> n; for (long long i = 1; i * i <= n; i++) root = i; if (n == 1) { answer = 2; } else { if (root * root == n) { answer = 2LL * root; } else { if (root * root + root >= n) { answer = 2LL * root + 1LL; } else { answer = 2LL * (root + 1LL); } } } cout << answer << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int INF = (int)1e9 + 7; const long long linf = (long long)1e16 + 7; struct pnt { double x, y; pnt(double x, double y) : y(y), x(x) {} pnt() = default; }; int cmp(double a, double b) { if (abs(a - b) < eps) return 0; if (a > b) return 1; return -1; } int main() { int n; cin >> n; int ans = 0; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; vector<int> cnt0(n + 1); vector<int> cnt1(n + 1); for (int i = 0; i < n; ++i) { if (a[i] == 0) cnt0[i]++; if (i) cnt0[i] += cnt0[i - 1]; } for (int i = n - 1; i >= 0; --i) { if (a[i] == 1) cnt1[i]++; if (i != n - 1) cnt1[i] += cnt1[i + 1]; } for (int i = 0; i < n; ++i) { ans = max(ans, cnt0[i] + cnt1[i + 1]); ans = max(ans, cnt1[i]); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int start; int tail; int head[150500], to[150500], nxt[150500], wei[150500], cost[150500], tot = 1; int dis[5050], pre[5050], pres[5050]; bool vis[5050]; queue<int> que; int n, sum, k; int used, flow; char str[105]; int numstr[30], numstr1[105][30], num[105]; void add(int x, int y, int z, int w) { tot++, to[tot] = y, nxt[tot] = head[x], head[x] = tot, cost[tot] = w, wei[tot] = z; tot++, to[tot] = x, nxt[tot] = head[y], head[y] = tot, cost[tot] = -w, wei[tot] = 0; } bool spfa() { memset(dis, inf, sizeof(dis)); memset(vis, 0, sizeof(vis)); dis[start] = 0; que.push(start); int now; do { now = que.front(); vis[now] = 0; que.pop(); for (int i = head[now]; i; i = nxt[i]) { if (dis[to[i]] > dis[now] + cost[i] && wei[i]) { dis[to[i]] = dis[now] + cost[i]; pre[to[i]] = now; pres[to[i]] = i; if (!vis[to[i]]) { que.push(to[i]); vis[to[i]] = 1; } } } } while (!que.empty()); return dis[tail] != inf; } void f() { int now = tail; int low = inf; while (now != start) { low = min(low, wei[pres[now]]); now = pre[now]; } used += low * dis[tail]; flow += low; now = tail; while (now != start) { wei[pres[now]] -= low; wei[pres[now] ^ 1] += low; now = pre[now]; } } int main() { int len; cin >> str; len = strlen(str); for (int i = 0; i < strlen(str); i++) { numstr[str[i] - a + 1]++; } cin >> k; start = 0, tail = 30; for (int i = 1; i <= k; i++) { cin >> str >> num[i]; for (int j = 0; j < strlen(str); j++) { numstr1[i][str[j] - a + 1]++; } } for (int i = 1; i <= 26; i++) { if (!numstr[i]) continue; add(start, i, numstr[i], 0); for (int j = 1; j <= k; j++) { if (!numstr1[j][i]) continue; add(i, j + 30, numstr1[j][i], j); } } for (int i = 1; i <= k; i++) { add(i + 30, tail, num[i], 0); } while (spfa()) { f(); } if (flow != len) { cout << -1 << endl; } else { cout << used << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; set<int> s; for (int i = 0; i < n; i++) { int temp; cin >> temp; s.insert(temp); } if (s.size() != n) cout << YES n ; else cout << NO << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)(1000000007); const double eps = 1e-9; const double pi = 3.1415926535897932384626; long long gcd(long long a, long long b) { return (b ? gcd(b, a % b) : a); } bool isprime(int n) { if (n == 1) return false; for (long long i = 2; i <= sqrt(n); i++) { if (n % i == 0) return false; } return true; } int modExp(int b, int e, int m) { int x = 1; while (e != 0) { if (e % 2 == 1) x = (x * b) % m; b = (b * b) % m; e = e / 2; } return x; } unsigned long long fact(unsigned long long n) { unsigned long long ret = 1; for (long long i = 1; i <= n; i++) { ret *= i; } return ret; } int ans = 0; int main() { long long n; cin >> n; vector<pair<long long, long long> > vp; for (long long i = 0; i <= n - 1; i++) { int a, b; cin >> a >> b; vp.push_back(make_pair(a, b)); } sort(vp.begin(), vp.end()); ans = vp[0].second; for (long long i = 1; i <= n - 1; i++) { if (vp[i].second >= ans) ans = vp[i].second; else ans = vp[i].first; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; int A[100005]; int main(int argc, char *argv[]) { scanf( %d , &N); for (int i = (1), _n = (N); i <= _n; i++) scanf( %d , &A[i]); int hi = -1; for (int i = (1), _n = (N); i <= _n; i++) hi = max(hi, A[i]); bool done[100005] = {false}; int ans = 1; for (int i = (1), _n = (N); i <= _n; i++) if (A[i] == hi && done[i] == false) { int tans = 0; for (int j = (i), _n = (N); j <= _n; j++) if (A[j] == hi) done[j] = true, tans++; else break; ans = max(ans, tans); } printf( %d n , ans); return 0; }
|
module Forward(
input EX2MEM_RegWrite,
input MEM2WB_RegWrite,
input [4:0] EX2MEM_Rd, // !!! AddrC i.e. EX2MEM_Rd
MEM2WB_Rd, // !!! AddrC i.e. MEM2WB_Rd
ID2EX_Rs,
IF2ID_Rs,
ID2EX_Rt,
IF2ID_Rt,
ID2EX_Rd,
output reg[1:0] ForwardA,
ForwardB,
output reg ForwardC,
ForwardD
);
// ForwardX: 2->ALUOut, 1->wdata, 0->DataBusA
// 2->last, 1->last last, 0->normal
always @(*) begin
if((EX2MEM_RegWrite)&&(EX2MEM_Rd!=5'h0)&&(EX2MEM_Rd==ID2EX_Rs))
ForwardA <= 2'h2;
else if( (MEM2WB_RegWrite) & (|MEM2WB_Rd) & (MEM2WB_Rd==ID2EX_Rs) & ~(EX2MEM_Rd==ID2EX_Rs&&EX2MEM_RegWrite))
ForwardA <= 2'h1;
else
ForwardA <= 2'h0;
end
always @(*) begin
if((EX2MEM_RegWrite)&(|EX2MEM_Rd)&(EX2MEM_Rd==ID2EX_Rt))
ForwardB <= 2'h2;
else if((MEM2WB_RegWrite) & (|MEM2WB_Rd) & (MEM2WB_Rd==ID2EX_Rt) & ~(EX2MEM_Rd==ID2EX_Rt&&EX2MEM_RegWrite) )
ForwardB <= 2'h1;
else
ForwardB <= 2'h0;
end
always @ (*)
if(MEM2WB_RegWrite & (|MEM2WB_Rd) & (MEM2WB_Rd == IF2ID_Rs)) // Rd ie AddrC to be written
ForwardC = 1'b1;
else
ForwardC = 1'b0;
always @ (*)
if(MEM2WB_RegWrite & (|MEM2WB_Rd) & (MEM2WB_Rd == IF2ID_Rt)) // Rd ie AddrC to be written
ForwardD = 1'b1;
else
ForwardD = 1'b0;
endmodule
// no IF2ID_Rs & IF2ID_Rt
// directly connect from `instruction` outside this module
//为产生气泡，对寄存器进行清除，产生气泡可以延后时钟周期方便转发
//jump为第二阶段，branch为第三阶段，清除寄存器延后时钟周期
module Hazard(
input ID2EX_MemRead,
Branch,
Jump,
input[4:0] ID2EX_Rt,
IF2ID_Rs,
IF2ID_Rt,
output reg PCWrite,
IF2ID_flush,
IF2ID_write,
ID2EX_flush
);
//
always @(*) begin
if(ID2EX_MemRead&((ID2EX_Rt==IF2ID_Rs)|(ID2EX_Rt==IF2ID_Rt))) begin
PCWrite = 1'b0;
IF2ID_flush = 1'b0;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b1;
end else if(Jump) begin
PCWrite = 1'b1;
IF2ID_flush = 1'b1;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b0;
end else if(Branch) begin
PCWrite = 1'b1;
IF2ID_flush = 1'b1;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b1;
end else begin
PCWrite = 1'b1;
IF2ID_flush = 1'b0;
IF2ID_write = 1'b1;
ID2EX_flush = 1'b0;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sdrdrum_arty_tb;
reg clk = 1'b0;
reg eth_clk = 1'b0;
reg rstn = 1'b0;
sdrdrum_arty dut (
.clk_in(clk),
.rstn_in(rstn),
.adc_a_data(1'b0),
.adc_b_data(1'b0),
.adc_c_data(1'b0),
.adc_d_data(1'b0),
// Ethernet
.eth_phy_rxd(4'b0),
.eth_phy_rx_clk(1'b0),
.eth_phy_rx_dv(1'b0),
.eth_phy_rx_er(1'b0),
.eth_phy_tx_clk(eth_clk),
.eth_phy_crs(1'b0),
.eth_phy_col(1'b0),
// IO
.switches(4'b0),
.buttons(4'b0)
);
initial begin
#500 rstn = 1'b1;
end
always begin
#20 eth_clk = ~eth_clk;
end
always begin
#5 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int an[101][21][21], n, k, md = 1e9 + 7, t[21][21]; vector<int> tr[101]; void go(int v = 1, int p = 0) { an[v][0][1] = an[v][1][0] = 1; for (int i = 0; i < (int)(tr[v].size()); ++i) { int u = tr[v][i]; if (u == p) continue; go(u, v); for (int i = 0; i < (int)(21); ++i) for (int j = 0; j < (int)(21); ++j) for (int w = 0; w < (int)(21); ++w) for (int z = 0; z < (int)(21); ++z) { int a = i; if (w && (w + 1 < a || !a)) a = w + 1; if (a > 20) a = 0; int b = 0; if (!i && z) b = z + 1; else if (i && z && k - i + 1 < z) b = z + 1; if (!w) b = max(b, j); else if (j && k - w + 1 < j) b = max(b, j); if (b > 20) continue; t[a][b] = ((long long)an[v][i][j] * an[u][w][z] + t[a][b]) % md; } for (int i = 0; i < (int)(21); ++i) for (int j = 0; j < (int)(21); ++j) an[v][i][j] = t[i][j], t[i][j] = 0; } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i < (int)(n); ++i) { int a, b; scanf( %d%d , &a, &b); tr[a].push_back(b); tr[b].push_back(a); } go(); int a = 0; for (int i = 0; i < (int)(21); ++i) if ((a += an[1][i][0]) >= md) a -= md; printf( %d n , a); }
|
#include <bits/stdc++.h> using namespace std; string S; signed long long mo = 1000000007; int N; string qs[100005]; signed long long memo[20][100005]; signed long long dig[20][100005]; void solve() { int i, j, k, l, r, x, y; string s; cin >> qs[0]; cin >> N; N++; qs[0] = 0-> + qs[0]; for (i = 1; i < N; i++) cin >> qs[i]; for (i = 0; i < 10; i++) memo[i][N] = i, dig[i][N] = 10; for (i = N - 1; i >= 0; i--) { for (j = 0; j < 10; j++) memo[j][i] = memo[j][i + 1], dig[j][i] = dig[j][i + 1]; int from = qs[i][0] - 0 ; memo[from][i] = 0; dig[from][i] = 1; for (j = qs[i].size() - 1; j >= 3; j--) { int nn = qs[i][j] - 0 ; memo[from][i] = (memo[from][i] + memo[nn][i + 1] * dig[from][i]) % mo; dig[from][i] = (dig[from][i] * dig[nn][i + 1]) % mo; } } cout << memo[0][0] << endl; } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false); for (i = 0; i < argc - 1; i++) s += argv[i + 1], s += n ; for (i = 0; i < s.size(); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i; cin >> n; long long int a[n], p, b[100000], sum = 0, r = 0, c[n]; for (i = 0; i < n; i = i + 1) { cin >> a[i]; p = a[i]; b[p] = 0; c[i] = 1; } for (i = 0; i < n; i = i + 1) { p = a[i]; b[p] = b[p] + 1; if (b[p] > 1) { c[i] = 0; } else { r = r + 1; } } for (i = 0; i < n; i = i + 1) { p = a[i]; if (c[i] != 0) { p = a[i]; if (b[p] > 1) { sum = sum + r; b[p] = b[p] - 1; } else if (b[p] > 0) { r = r - 1; sum = sum + r; b[p] = b[p] - 1; } } else { b[p] = b[p] - 1; if (b[p] == 0) { r = r - 1; } } } printf( %lld n , sum); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { int a, b; cin >> a >> b; int sum = 0; int h; for (int i = 1; i < a; i++) { sum += i; if (sum >= b) { sum -= i; h = i - 1; break; } } int s = a - h - 1; int sb = a - (b - sum) + 1; for (int i = 1; i <= a; i++) { if (i == s || i == sb) cout << b ; else cout << a ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, k; cin >> n >> k; vector<int> v(n); long long sum = 0; for (int i = 0; i < n; i++) { cin >> v[i]; sum += v[i]; } if (sum % k != 0) cout << No n ; else { int num = sum / k; for (int i = 1; i < n; i++) { v[i] += v[i - 1]; } int cnt = 0; vector<int> res; int q = 0; for (int i = 0; i < n; i++) { q++; if (v[i] % num == 0) { cnt++; res.push_back(q); q = 0; } } if (cnt == k) { cout << Yes n ; for (int i = 0; i < k; i++) cout << res[i] << ; } else cout << No n ; } return 0; }
|
// bug637
module submod_a
(
//Inputs
input wire signed [15:0] serial_in,
//Outputs
output wire signed [15:0] parallel_out [0:7]
);
endmodule
module submod_b
(
//Inputs
input wire signed [15:0] parallel_out [0:7],
//Outputs
output wire signed [15:0] final_out [0:7]
);
endmodule
module top
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic signed [15:0] serial_in, // To a_inst of submod_a.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic signed [15:0] final_out [0:7] // From b_inst of submod_b.v
// End of automatics
);
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic signed [15:0] parallel_out [0:7]; // From a_inst of submod_a.v
// End of automatics
submod_a a_inst
(/*AUTOINST*/
// Outputs
.parallel_out (parallel_out/*[15:0].[0:7]*/),
// Inputs
.serial_in (serial_in[15:0]));
submod_b b_inst
(/*AUTOINST*/
// Outputs
.final_out (final_out/*[15:0].[0:7]*/),
// Inputs
.parallel_out (parallel_out/*[15:0].[0:7]*/));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const int infinity = (int)1e9 + 42; const int64_t llInfinity = (int64_t)1e18 + 256; const int module = (int)1e9 + 7; const long double eps = 1e-8; mt19937_64 randGen(system_clock().now().time_since_epoch().count()); inline void raiseError(string errorCode) { cerr << Error : << errorCode << endl; exit(42); } inline int readAns(int req) { cout << req << endl; int q; cin >> q; if (q == 0) { exit(0); } return q; } signed main() { ios_base::sync_with_stdio(false); int m, n; cin >> m >> n; vector<int> v(n); for (int i = 0; i < n; i++) { v[i] = readAns(m) * -1; } int l = 1, r = m - 1; int p = 0; while (l != r) { int m = (l + r) / 2; int ans = readAns(m) * v[p]; p++; p %= n; if (ans < 0) { r = m - 1; } else { l = m + 1; } } readAns(l); assert(false); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; vector<vector<pair<long long, long long>>> adj; vector<long long> dist; vector<bool> visited; void djikstra(long long src) { priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, greater<pair<long long, long long>>> s; s.push({0, src}); while (!s.empty()) { long long u = s.top().second; long long d_u = dist[u]; s.pop(); if (visited[u]) continue; else visited[u] = true; for (auto x : adj[u]) { long long v = x.first; long long w = x.second; if (dist[v] > (dist[u] + w)) { dist[v] = dist[u] + w; s.push({dist[v], v}); } } } } void solve() { long long n, m; cin >> n >> m; adj.resize(n + 1); dist.resize(n + 1, LLONG_MAX); visited.resize(n + 1, false); for (long long i = 0; i < m; ++i) { long long u, v, w; cin >> u >> v >> w; adj[u].push_back({v, 2 * w}); adj[v].push_back({u, 2 * w}); } for (long long i = 0; i < n; ++i) { long long temp; cin >> temp; adj[0].push_back({i + 1, temp}); } dist[0] = 0; djikstra(0); for (long long i = 1; i <= n; ++i) { cout << dist[i] << ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; long long i, j; while (t--) { solve(); } return 0; }
|
module data_receiver(iClock, iReset, iRxDone, iReceivedData, oResultData, oDoneReceiving);
parameter IDLE = 3'b000,
FETCH_FIRST_VALUE = 3'b001,
CHECK_VALUE = 3'b010,
RECEIVE_DATA = 3'b011,
EMIT_DONE_RECEIVING = 3'b100,
RECEIVING_DATA = 3'b101,
FETCH_VALUE_INC_COUNTER = 3'b110,
INPUT_MESSAGE = 2'b00,
CIRCUIT_MESSAGE = 2'b01;
input iClock;
input iReset;
input iRxDone;
input [7:0] iReceivedData;
output reg [7:0] oResultData[199:0];
output oDoneReceiving;
reg [2:0] state = IDLE;
reg [7:0] receive_counter = 8'b0;
reg [7:0] incoming_message_size = 8'b0;
wire [2:0] next_state;
assign next_state = next_state_fun(state, iRxDone,
receive_counter, incoming_message_size);
function [2:0] next_state_fun(input [2:0] current_state, input rx_done,
input [7:0] counter, input [7:0] message_size);
case(current_state)
IDLE:
if (rx_done) begin
next_state_fun = FETCH_FIRST_VALUE;
end else begin
next_state_fun = IDLE;
end
FETCH_FIRST_VALUE:
next_state_fun = CHECK_VALUE;
CHECK_VALUE:
next_state_fun = RECEIVE_DATA;
RECEIVE_DATA:
if (counter < message_size) begin
next_state_fun = RECEIVING_DATA;
end else begin
next_state_fun = EMIT_DONE_RECEIVING;
end
RECEIVING_DATA:
if (rx_done) begin
next_state_fun = FETCH_VALUE_INC_COUNTER;
end else begin
next_state_fun = RECEIVING_DATA;
end
FETCH_VALUE_INC_COUNTER:
next_state_fun = RECEIVE_DATA;
EMIT_DONE_RECEIVING:
next_state_fun = IDLE;
default:
next_state_fun = IDLE;
endcase
endfunction
always@ (posedge iClock) begin
if (iReset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always@ (posedge iClock) begin
oDoneReceiving <= 0;
if (iReset) begin
end else begin
case(state)
IDLE: begin
receive_counter <= 0;
end
FETCH_FIRST_VALUE: begin
oResultData[receive_counter] <= iReceivedData;
receive_counter <= receive_counter + 8'b1;
end
CHECK_VALUE: begin
if (oResultData[0] == INPUT_MESSAGE) begin
incoming_message_size = 8'b1 + 8'b1;
end else begin
incoming_message_size = 8'd29 + 8'b1;
end
end
FETCH_VALUE_INC_COUNTER: begin
oResultData[receive_counter] <= iReceivedData;
receive_counter <= receive_counter + 8'b1;
end
EMIT_DONE_RECEIVING: begin
oDoneReceiving <= 1;
end
default: begin
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> g[200001], rg[200001]; bool vis[200001]; long long int par[200001]; long long int sz[200001], dnom[200001]; long long int ans = 0, no = 0; long long int n, m, S; deque<long long int> top; void dfs(long long int x) { vis[x] = 1; for (auto v : g[x]) { if (!vis[v]) dfs(v); } top.push_front(x); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> S; S--; vector<pair<long long int, long long int> > g1[n]; long long int dis[n]; for (int i = 0; i < n; i++) { dis[i] = LLONG_MAX / 2; } for (int i = 0; i < m; i++) { long long int u, v, w; cin >> u >> v >> w; u--; v--; g1[u].push_back({v, w}); g1[v].push_back({u, w}); } set<pair<long long int, long long int> > second; second.insert({0, S}); dis[S] = 0; while (!second.empty()) { pair<long long int, long long int> p = *second.begin(); second.erase(second.begin()); if (vis[p.second]) continue; vis[p.second] = 1; long long int cd = p.first, u = p.second; for (auto v : g1[u]) { if (cd == dis[v.first] + v.second) { g[v.first].push_back(u); rg[u].push_back(v.first); } if (dis[v.first] > cd + v.second) { dis[v.first] = cd + v.second; second.insert({dis[v.first], v.first}); } } } memset(vis, 0, sizeof(vis)); dfs(S); long long int ans = 0; dnom[top[0]] = -1; for (int i = 1; i < top.size(); i++) { long long int u = top[i]; long long int x = dnom[rg[u][0]]; bool flag = 1; for (auto par : rg[u]) { if (dnom[par] != x) { flag = 0; break; } } if (!flag || x == -1) dnom[u] = u; else dnom[u] = x; sz[dnom[u]]++; ans = max(ans, sz[dnom[u]]); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; long long dp[N], f[N], ok[N], p[N]; vector<long long> node[N]; long long cur, now; void dfs(long long u, long long p) { for (auto j : node[u]) { if (j == p) continue; dfs(j, u); if (f[j]) { dp[u] += dp[j] + 1; f[u] = 1; } } if (ok[u]) f[u] = 1; } void find_dia(long long u, long long p, long long dis) { if (dis >= cur && ok[u]) { if (dis > cur) now = u; else now = min(now, u); cur = dis; } for (auto j : node[u]) { if (j == p) continue; find_dia(j, u, dis + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); if (fopen( A.INP , r )) { freopen( A.INP , r , stdin); freopen( A.OUT , w , stdout); } long long n, m; cin >> n >> m; for (int i = 1; i < n; i++) { long long u, v; cin >> u >> v; node[u].push_back(v); node[v].push_back(u); } for (int i = 1; i <= m; i++) cin >> p[i], ok[p[i]] = 1; dfs(p[1], p[1]); long long ans = dp[p[1]] * 2; cur = 0; now = 1e9; find_dia(p[1], p[1], 0); cur = 0; long long f = now; now = 1e9; find_dia(f, f, 0); cout << min(f, now) << n ; cout << ans - cur; }
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#include <bits/stdc++.h> using namespace std; bool cmp(int a, int b) { return a > b; } int main() { string s; cin >> s; vector<int> a, b; vector<int> dec1, dec2; int sum1 = s[0] - 0 + (s[1] - 0 ) + (s[2] - 0 ); int sum2 = (s[3] - 0 ) + (s[4] - 0 ) + (s[5] - 0 ); if (sum1 == sum2) { cout << 0 << endl; return 0; } else if (sum1 > sum2) for (int i = 0; i < 6; ++i) { if (i < 3) dec1.push_back((s[i] - 0 )); else dec2.push_back(9 - (s[i] - 0 )); } else { for (int i = 0; i < 6; ++i) { if (i < 3) dec1.push_back(9 - (s[i] - 0 )); else dec2.push_back(s[i] - 0 ); } } sort(dec1.begin(), dec1.end()); sort(dec2.begin(), dec2.end()); int x = abs(sum1 - sum2); int cnt = 0, i = 2, j = 2; while (x > 0) { if (dec1[i] > dec2[j]) { x -= dec1[i]; cnt++; i--; } else { x -= dec2[j]; cnt++; j--; } } cout << cnt << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/13/2017 04:41:05 PM
// Design Name:
// Module Name: top_sr_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_sr_tb #(parameter WIDTH=170,
parameter CNT_WIDTH=8,
parameter DIV_WIDTH=6,
parameter SHIFT_DIRECTION=1,
parameter READ_TRIG_SRC=0,
parameter READ_DELAY=0)();
reg clk_in;
reg rst;
reg start;
reg [WIDTH-1:0] din;
reg data_in_p;
reg data_in_n;
reg [DIV_WIDTH-1:0] div;
wire clk_sr_p, clk_sr_n;
wire data_out_p, data_out_n;
wire load_sr_p,load_sr_n;
wire [WIDTH-1:0] dout;
wire clk;
wire valid;
top_new #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .DIV_WIDTH(DIV_WIDTH),.SHIFT_DIRECTION(SHIFT_DIRECTION),.READ_TRIG_SRC(READ_TRIG_SRC),.READ_DELAY(READ_DELAY))
DUT4(
.clk_in(clk_in),
.rst(rst),
.pulse_in(start),
.din(din),
.div(div),
.data_in_p(data_in_p),
.data_in_n(data_in_n),
.clk_sr_p(clk_sr_p),
.clk_sr_n(clk_sr_n),
.data_out_p(data_out_p),
.data_out_n(data_out_n),
.load_sr_p(load_sr_p),
.load_sr_n(load_sr_n),
.dout(dout),
.clk(clk),
.valid(valid)
);
initial begin
$dumpfile("top_sr.dump");
$dumpvars(0, Top_SR);
end
initial begin
clk_in=0;
forever #25 clk_in=~clk_in;
end
initial begin
rst=0;
#100 rst=1;
#100 rst=0;
end
initial begin
din={1'b1,169'b1011};
div=6'b1;
start=0;
#675 start=1;
#50 start=0;
#19500 start=1;
#50 start=0;
end
initial begin
data_in_p=0;
data_in_n=1;
#1125
data_in_p=1;
data_in_n=0;
#200
data_in_p=0;
data_in_n=1;
#200
data_in_p=1;
data_in_n=0;
end
endmodule
|
#include <bits/stdc++.h> long double pi = acos(-1); long long z = 1000000007; long long power(long long a, long long b) { if (b == 0) return 1; long long c = power(a, b / 2); if (b % 2 == 0) return c * c; else return c * c * a; } using namespace std; const int N = 1e6 + 7; void solve() { long long n; cin >> n; long long k; cin >> k; map<long long, long long> m; for (long long i = 0; i < n; i++) { long long x; cin >> x; m[x]++; } if (m.size() <= k) cout << 1 << endl; else if (k == 1 && m.size() > 1) cout << -1 << endl; else { long long ans = (m.size() - k) / (k - 1) + 1; if ((m.size() - k) % (k - 1) != 0) ans++; cout << ans << endl; } } int main() { long long t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) using namespace std; const double inf = 1e121; const double eps = 1e-10; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long randint(long long l, long long r) { long long out = rng() % (r - l + 1) + l; return out >= l ? out : out + r - l + 1; } template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (long long i = 0; i < static_cast<long long>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } template <typename A, typename B, typename C, typename D, typename E> string to_string(tuple<A, B, C, D, E> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + , + to_string(get<4>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T> struct is_pair { static const bool value = false; }; template <typename T, typename U> struct is_pair<std::pair<T, U>> { static const bool value = true; }; const long long INF = 0x3f3f3f3f3f3f3f3fll; template <typename T> typename enable_if<!is_integral<T>::value && !is_pair<T>::value, void>::type read(T& x) { cin >> x; } long long read() { char c; long long out = 0, f = 1; for (c = getchar(); !isdigit(c) && c != - ; c = getchar()) { } if (c == - ) { f = -1; c = getchar(); } for (; isdigit(c); c = getchar()) out = (out << 3) + (out << 1) + c - 0 ; return out * f; } template <typename T> typename enable_if<is_integral<T>::value, T>::type read(T& x) { char c; T f = 1; x = 0; for (c = getchar(); !isdigit(c) && c != - ; c = getchar()) { } if (c == - ) { f = -1; c = getchar(); } for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + c - 0 ; return x *= f; } char read(char& x) { for (x = getchar(); isspace(x); x = getchar()) { } return x; } double read(double& x) { scanf( %lf , &x); return x; } template <typename T> typename enable_if<!is_integral<T>::value && !is_pair<T>::value, void>::type write(const T& x) { cout << x; } template <typename T> typename enable_if<is_integral<T>::value, void>::type write(const T& x) { if (x < 0) { putchar( - ); write(-x); return; } if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } void write(const char& x) { putchar(x); } void write(const double& x) { printf( %.10lf , x); } template <typename T> typename enable_if<is_pair<T>::value, void>::type read(T& x) { read(x.first); read(x.second); } template <typename T> typename enable_if<is_pair<T>::value, void>::type write(const T& x) { write(x.first); putchar( ); write(x.second); } template <typename T, typename... Args> void read(T& x, Args&... args) { read(x); read(args...); } template < typename OutputIt, typename = typename enable_if< is_same<output_iterator_tag, typename iterator_traits<OutputIt>::iterator_category>::value || (is_base_of<forward_iterator_tag, typename iterator_traits<OutputIt>:: iterator_category>::value && !is_const<OutputIt>::value)>::type> void read(OutputIt __first, OutputIt __last) { for (; __first != __last; ++__first) read(*__first); } template < typename InputIt, typename = typename enable_if<is_base_of< input_iterator_tag, typename iterator_traits<InputIt>::iterator_category>::value>::type> void wts(InputIt __first, InputIt __last) { bool isFirst = true; for (; __first != __last; ++__first) { if (isFirst) isFirst = false; else putchar( ); write(*__first); } putchar( n ); } template < typename InputIt, typename = typename enable_if<is_base_of< input_iterator_tag, typename iterator_traits<InputIt>::iterator_category>::value>::type> void wtb(InputIt __first, InputIt __last) { for (; __first != __last; ++__first) { write(*__first); putchar( n ); } } template <typename T> void wts(const T& x) { write(x); putchar( ); } template <typename T> void wtb(const T& x) { write(x); putchar( n ); } template <typename T> void wte(const T& x) { write(x); exit(0); } template <typename T, typename... Args> void wts(const T& x, Args... args) { wts(x); wts(args...); } template <typename T, typename... Args> void wtb(const T& x, Args... args) { wts(x); wtb(args...); } template <typename T, typename... Args> void wte(const T& x, Args... args) { wts(x); wte(args...); } template <typename T1, typename T2> inline bool up(T1& x, const T2& y) { return x < y ? x = y, 1 : 0; } template <typename T1, typename T2> inline bool dn(T1& x, const T2& y) { return y < x ? x = y, 1 : 0; } template <typename T1, typename T2, typename T3> inline bool inRange(const T1& x, const T2& l, const T3& r) { return !(x < l) && !(r < x); } template <typename T1, typename T2> inline auto minOfDifferentTypes(const T1& x, const T2& y) -> decltype(x < y ? x : y) { return x < y ? x : y; } template <typename T1, typename T2> inline auto maxOfDifferentTypes(const T1& x, const T2& y) -> decltype(x < y ? y : x) { return x < y ? y : x; } template <typename T1, typename T2, typename T3> inline T1& madd(T1& x, const T2& y, const T3& modulo) { return x = (long long)(x + y + modulo) % modulo; } template <typename T1, typename T2, typename T3> inline T1& mmul(T1& x, const T2& y, const T3& modulo) { return x = (long long)x * y % modulo; } template <typename T1, typename T2, typename T3> inline long long modadd(long long x, long long y, long long modulo) { return (x += y) >= modulo ? x - modulo : x; } inline long long isinf(long long x) { return x < INF ? x : -1; } inline void yesno(bool x) { wtb(x ? Yes : No ); } signed main() { long long t = read(); while (t--) { long long n = read(); long long k = read(); if (n >= k && ((n - (k - 1)) & 1)) { wtb( YES ); for (long long i = (1), iend = (k - 1); i <= iend; ++i) wts(1); wtb(n - k + 1); } else if (n >= 2 * k && !(n & 1)) { wtb( YES ); for (long long i = (1), iend = (k - 1); i <= iend; ++i) wts(2); wtb(n - 2 * k + 2); } else wtb( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int v[100005], u[100005], w[100005], dist[100005]; vector<pair<int, int> > edges[100005]; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > pq; int main() { int n, m, s, l; while (cin >> n >> m >> s) { for (int i = 0; i < m; ++i) { cin >> v[i] >> u[i] >> w[i]; edges[v[i]].push_back(make_pair(u[i], w[i])); edges[u[i]].push_back(make_pair(v[i], w[i])); } cin >> l; pq.push(make_pair(0, s)); memset(dist, 0x3f, sizeof(dist)); dist[s] = 0; int c, d, nxt; while (pq.size()) { c = pq.top().second; pq.pop(); for (int i = 0; i < edges[c].size(); ++i) { nxt = edges[c][i].first; if (dist[nxt] > dist[c] + edges[c][i].second) { dist[nxt] = dist[c] + edges[c][i].second; pq.push(make_pair(dist[nxt], nxt)); } } } int tmp; int cnt = 0; for (int i = 1; i <= n; ++i) if (dist[i] == l) ++cnt; for (int i = 0; i < m; ++i) { if (dist[u[i]] < l && dist[u[i]] + w[i] > l) { tmp = dist[u[i]] + w[i]; if (dist[v[i]] + tmp - l >= l) ++cnt; } if (dist[v[i]] < l && dist[v[i]] + w[i] > l) { tmp = dist[v[i]] + w[i]; if (dist[u[i]] + tmp - l > l) ++cnt; } } cout << cnt << n ; for (int i = 1; i <= n; ++i) edges[i].clear(); while (pq.size()) pq.pop(); } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module v5icap_wb
(input clk, input reset,
input cyc_i, input stb_i, input we_i, output ack_o,
input [31:0] dat_i, output [31:0] dat_o);
wire BUSY, CE, WRITE;
reg [2:0] icap_state;
localparam ICAP_IDLE = 0;
localparam ICAP_WR0 = 1;
localparam ICAP_WR1 = 2;
localparam ICAP_RD0 = 3;
localparam ICAP_RD1 = 4;
always @(posedge clk)
if(reset)
icap_state <= ICAP_IDLE;
else
case(icap_state)
ICAP_IDLE :
begin
if(stb_i & cyc_i)
if(we_i)
icap_state <= ICAP_WR0;
else
icap_state <= ICAP_RD0;
end
ICAP_WR0 :
icap_state <= ICAP_WR1;
ICAP_WR1 :
icap_state <= ICAP_IDLE;
ICAP_RD0 :
icap_state <= ICAP_RD1;
ICAP_RD1 :
icap_state <= ICAP_IDLE;
endcase // case (icap_state)
assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst
(.BUSY(BUSY), // Busy output
.O(dat_o), // 32-bit data output
.CE(~CE), // Clock enable input
.CLK(clk), // Clock input
.I(dat_i), // 32-bit data input
.WRITE(~WRITE) // Write input
);
endmodule // v5icap_wb
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Crop
:Function
Cropping images, depending on your top, bottom, left and right coordinate.
Give the first output after 1 cycle while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module Crop(
clk,
rst_n,
top,
bottom,
left,
right,
in_enable,
in_data,
in_count_x,
in_count_y,
out_ready,
out_data,
out_count_x,
out_count_y);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Top of the rang you want to crop.
::range
Depend on height of image, 0 - im_height-1.
*/
input[im_width_bits - 1 : 0] top;
/*
::description
Bottom of the rang you want to crop.
::range
Depend on height of image, 0 - im_height-1.
*/
input[im_width_bits - 1 : 0] bottom;
/*
::description
Left of the rang you want to crop.
::range
Depend on height of image, 0 - im_width-1.
*/
input[im_width_bits - 1 : 0] left;
/*
::description
Right of the rang you want to crop.
::range
Depend on height of image, 0 - im_width-1.
*/
input[im_width_bits - 1 : 0] right;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Output pixel count for height.
*/
output[im_width_bits - 1 : 0] out_count_x;
/*
::description
Output pixel count for height.
*/
output[im_width_bits - 1 : 0] out_count_y;
generate
reg[im_width_bits - 1 : 0] reg_out_count_x;
reg[im_width_bits - 1 : 0] reg_out_count_y;
reg[data_width - 1 : 0] reg_out_data;
reg reg_out_ready;
reg in_range_t, in_range_b, in_range_l, in_range_r;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_out_ready <= 0;
else
reg_out_ready <= 1;
end
assign out_ready = reg_out_ready;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
in_range_t <= 0;
in_range_b <= 0;
in_range_l <= 0;
in_range_r <= 0;
end else begin
in_range_t <= in_count_y >= top ? 1 : 0;
in_range_b <= in_count_y <= bottom ? 1 : 0;
in_range_l <= in_count_x >= left ? 1 : 0;
in_range_r <= in_count_x <= right ? 1 : 0;
end
end
if(work_mode == 0) begin
always @(posedge clk) begin
reg_out_count_x <= in_count_x;
reg_out_count_y <= in_count_y;
reg_out_data <= in_data;
end
end else begin
always @(posedge in_enable) begin
reg_out_count_x <= in_count_x;
reg_out_count_y <= in_count_y;
reg_out_data <= in_data;
end
end
assign out_count_x = reg_out_count_x;
assign out_count_y = reg_out_count_y;
assign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_out_data : 0;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string rows[1000]; int dist[1000][1000]; bool disc[1000][1000]; int r, c; void bfs(int row, int col) { queue<pair<int, int> > q; q.push(make_pair(row, col)); while (!q.empty()) { pair<int, int> cur = q.front(); disc[cur.first][cur.second] = true; q.pop(); if (cur.first > 0 && !disc[cur.first - 1][cur.second] && rows[cur.first - 1][cur.second] != T ) { dist[cur.first - 1][cur.second] = dist[cur.first][cur.second] + 1; disc[cur.first - 1][cur.second] = true; q.push(make_pair(cur.first - 1, cur.second)); } if (cur.first < r - 1 && !disc[cur.first + 1][cur.second] && rows[cur.first + 1][cur.second] != T ) { dist[cur.first + 1][cur.second] = dist[cur.first][cur.second] + 1; disc[cur.first + 1][cur.second] = true; q.push(make_pair(cur.first + 1, cur.second)); } if (cur.second < c - 1 && !disc[cur.first][cur.second + 1] && rows[cur.first][cur.second + 1] != T ) { dist[cur.first][cur.second + 1] = dist[cur.first][cur.second] + 1; disc[cur.first][cur.second + 1] = true; q.push(make_pair(cur.first, cur.second + 1)); } if (cur.second > 0 && !disc[cur.first][cur.second - 1] && rows[cur.first][cur.second - 1] != T ) { dist[cur.first][cur.second - 1] = dist[cur.first][cur.second] + 1; disc[cur.first][cur.second - 1] = true; q.push(make_pair(cur.first, cur.second - 1)); } } } int main(void) { cin >> r >> c; for (int i = 0; i < r; i++) cin >> rows[i]; memset(disc, 0, sizeof(disc)); for (int i = 0; i < r; i++) for (int j = 0; j < c; j++) if (rows[i][j] == E ) bfs(i, j); pair<int, int> start; for (int i = 0; i < r; i++) { for (int j = 0; j < c; j++) { if (rows[i][j] == S ) { start.first = i; start.second = j; } } } int kiek = 0; for (int i = 0; i < r; i++) { for (int j = 0; j < c; j++) { if (isdigit(rows[i][j]) && dist[i][j] <= dist[start.first][start.second] && disc[i][j]) { kiek += int(rows[i][j] - 0 ); } } } cout << kiek << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int r1, c1, r2, c2; char s[505][505]; bool dfs(int i, int j) { if (r2 == i && c2 == j && s[r2][c2] != . ) return 1; if (s[i][j] != . ) return 0; s[i][j] = X ; return dfs(i + 1, j) || dfs(i - 1, j) || dfs(i, j + 1) || dfs(i, j - 1); } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> s[i][j]; cin >> r1 >> c1 >> r2 >> c2; s[r1][c1] = . ; if (dfs(r1, c1)) cout << YES << endl; else cout << NO << endl; return 0; }
|
/*
`include "arbitor.v"
module test_arbitor_cell();
reg [2:0] priority;
reg [3:0] rmatrix0, rmatrix1, rmatrix2, rmatrix3, rmatrix4;
reg valid0, valid1, valid2, valid3, valid4;
reg [4:0] amatrix_o;
reg [14:0] rco;
wire [4:0] amatrix_n;
wire [14:0] rcn;
arbitor_cell ac(priority, rmatrix0, rmatrix1, rmatrix2, rmatrix3, rmatrix4,
valid0, valid1, valid2, valid3, valid4,
amatrix_o, rco, amatrix_n, rcn);
initial begin
$monitor("Priority: %d\n |N|S|E|W|R|V|\nrmatrix0: |%b|%b|%b|%b| |%b|\nrmatrix1: |%b|%b|%b|%b| |%b|\nrmatrix2: |%b|%b|%b|%b| |%b|\nrmatrix3: |%b|%b|%b|%b| |%b|\nrmatrix4: |%b|%b|%b|%b| |%b|\namatrix_o: |%b|%b|%b|%b|%b|\namatrix_n: |%b|%b|%b|%b|%b|\nrco: |%b|%b|%b|%b|%b|\nrcn: |%b|%b|%b|%b|%b|\n",
priority, rmatrix0[0], rmatrix0[1], rmatrix0[2], rmatrix0[3], valid0,
rmatrix1[0], rmatrix1[1], rmatrix1[2], rmatrix1[3], valid1,
rmatrix2[0], rmatrix2[1], rmatrix2[2], rmatrix2[3], valid2,
rmatrix3[0], rmatrix3[1], rmatrix3[2], rmatrix3[3], valid3,
rmatrix4[0], rmatrix4[1], rmatrix4[2], rmatrix4[3], valid4,
amatrix_o[0], amatrix_o[1], amatrix_o[2], amatrix_o[3],
amatrix_o[4], amatrix_n[0], amatrix_n[1], amatrix_n[2],
amatrix_n[3], amatrix_n[4], rco[14:12], rco[11:9], rco[8:6],
rco[5:3], rco[2:0], rcn[14:12], rcn[11:9], rcn[8:6], rcn[5:3],
rcn[2:0]);
$display("Output to port 1 from port 0");
priority = 3'b000;
rmatrix0 = 4'b1010;
rmatrix1 = 4'b1010;
rmatrix2 = 4'b1010;
rmatrix3 = 4'b1010;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b00000;
rco = 14'd0;
#10;
$display("Output to port 0 from port 3");
priority = 3'b011;
rmatrix0 = 4'b0101;
rmatrix1 = 4'b0101;
rmatrix2 = 4'b0101;
rmatrix3 = 4'b0101;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b00000;
rco = 14'd0;
#10;
$display("Output to port 3 from port 1");
priority = 3'b001;
rmatrix0 = 4'b0100;
rmatrix1 = 4'b1100;
rmatrix2 = 4'b0100;
rmatrix3 = 4'b0100;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b00100;
rco = 14'd0;
#10;
$display("Output to port 3 from port 2");
priority = 3'b010;
rmatrix0 = 4'b0100;
rmatrix1 = 4'b1100;
rmatrix2 = 4'b1111;
rmatrix3 = 4'b0100;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b10111;
rco = 14'd0;
#10;
$display("Invalid");
priority = 3'b111;
rmatrix0 = 4'b0100;
rmatrix1 = 4'b1100;
rmatrix2 = 4'b1111;
rmatrix3 = 4'b0100;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b10101;
rco = 14'h0aaa;
#10;
$display("Misroute");
priority = 3'b010;
rmatrix0 = 4'b0100;
rmatrix1 = 4'b1100;
rmatrix2 = 4'b0001;
rmatrix3 = 4'b0100;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b1;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b00001;
rco = 14'd0;
#10;
$display("Invalid Line");
priority = 3'b010;
rmatrix0 = 4'b0100;
rmatrix1 = 4'b1100;
rmatrix2 = 4'b0001;
rmatrix3 = 4'b0100;
rmatrix4 = 4'b1010;
valid0 = 1'b1;
valid1 = 1'b1;
valid2 = 1'b0;
valid3 = 1'b1;
valid4 = 1'b1;
amatrix_o = 5'b00010;
rco = 14'd0;
#10;
end
endmodule
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_2_V
`define SKY130_FD_SC_HS__SDFBBN_2_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_2_V
|
/**
* Hydra - An open source strand lighting controller
* (c) 2013-2014 Jon Evans <>
* Released under the MIT License -- see LICENSE.txt for details.
*
* strand_driver_tb.v - Testbench for WS2801/WS2811 driver state machine
*/
`timescale 1ns / 1ps
module strand_driver_tb;
parameter MEM_DATA_WIDTH = 24;
parameter STRAND_PARAM_WIDTH = 16;
reg clk = 0;
reg rst_n = 1;
reg ws2811_mode = 0;
reg start_frame = 0;
reg [STRAND_PARAM_WIDTH-1:0] strand_length = 160;
wire [STRAND_PARAM_WIDTH-1:0] current_idx;
reg [MEM_DATA_WIDTH-1:0] mem_data = 24'b101011001110000110101110;
wire busy;
wire done;
wire strand_clk;
wire strand_data;
// UUT
strand_driver sd_inst (
.clk(clk),
.rst_n(rst_n),
.ws2811_mode(ws2811_mode),
.strand_length(strand_length),
.current_idx(current_idx),
.mem_data(mem_data),
.start_frame(start_frame),
.busy(busy),
.done(done),
.strand_clk(strand_clk),
.strand_data(strand_data)
);
// Clock process
always #10 clk = !clk;
// Test process
initial begin
$dumpfile("strand_driver_tb.vcd");
$dumpvars(0, strand_driver_tb);
rst_n = 0;
#20 rst_n = 1;
#20 start_frame = 1;
#20 start_frame = 0;
#300000 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e4 + 10; struct Edge { int from, to, l, r, nxt; } e[N << 2]; int head[N], cnt = 0; int n, m, k, s1, s2, f, book[N]; long long d1[N], d2[N]; void add(int u, int v, int l, int r) { e[++cnt] = (Edge){u, v, l, r, head[u]}; head[u] = cnt; } void spfa1(int s) { memset(d1, 38, sizeof(d1)); memset(book, 0, sizeof(book)); book[s] = 1; d1[s] = 0; queue<int> q; while (!q.empty()) q.pop(); q.push(s); while (!q.empty()) { int x = q.front(); q.pop(); book[x] = 0; for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].to; if (d1[v] > d1[x] + e[i].r) { d1[v] = d1[x] + e[i].r; if (!book[v]) book[v] = 1, q.push(v); } } } } void spfa2(int s) { memset(d2, 38, sizeof(d2)); memset(book, 0, sizeof(book)); book[s] = 1; d2[s] = 0; queue<int> q; while (!q.empty()) q.pop(); q.push(s); while (!q.empty()) { int x = q.front(); q.pop(); book[x] = 0; for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].to; if (d2[v] > d2[x] + e[i].r) { d2[v] = d2[x] + e[i].r; if (!book[v]) book[v] = 1, q.push(v); } } } } bool check(int fff) { int fl = 1; while (fl) { fl = 0; spfa1(s1), spfa2(s2); for (int i = m + 1; i <= m + k; i++) if (d1[e[i].from] < d2[e[i].from] && (e[i].l != e[i].r)) e[i].r = e[i].l, fl = 1; if (d1[f] < d2[f] + fff) { puts(fff ? DRAW : WIN ); for (int i = m + 1; i <= m + k; i++) cout << e[i].r << ; return 1; } } return 0; } int main() { cin >> n >> m >> k; cin >> s1 >> s2 >> f; for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); add(u, v, w, w); } for (int i = 1; i <= k; i++) { int u, v, l1, l2; scanf( %d%d%d%d , &u, &v, &l1, &l2); add(u, v, l1, l2); } if (!check(0) && !check(1)) puts( LOSE ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; struct pt { int x, y; pt() {} pt(int x, int y) : x(x), y(y) {} }; int get_pos(int i, int n) { if (i >= n) i -= n; return ((i >= 0) ? i : n - i - 1); } void solve() { int n; cin >> n; vector<pt> v(n); for (int i = 0; i < n; ++i) { cin >> v[i].x >> v[i].y; } if (n & 1) { cout << NO ; return; } for (int i = 0; i < n; ++i) { pt a = v[get_pos(i, n)], b = v[get_pos(i + 1, n)]; pt c = v[get_pos(i + n / 2, n)], d = v[get_pos(i + n / 2 + 1, n)]; int A1 = b.y - a.y, B1 = b.x - a.x; int A2 = c.y - d.y, B2 = c.x - d.x; if (!(A1 == A2 && B1 == B2)) { cout << No << endl; return; } } cout << YES ; } int main() { int t = 1; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_1_V
`define SKY130_FD_SC_MS__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This test demonstrates an issue with sign extension.
// Assigning to localparms larger than 32 bits broke in 3.862
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Mike Thyer.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;
localparam [ 2:0] one3_lp = 1;
localparam [ 3:0] one4_lp = 1;
localparam [ 4:0] one5_lp = 1;
localparam [ 5:0] one6_lp = 1;
localparam [ 6:0] one7_lp = 1;
localparam [ 7:0] one8_lp = 1;
localparam [ 8:0] one9_lp = 1;
localparam [ 9:0] one10_lp = 1;
localparam [19:0] one20_lp = 1;
localparam [29:0] one30_lp = 1;
localparam [30:0] one31_lp = 1;
localparam [31:0] one32_lp = 1;
localparam [32:0] one33_lp = 1;
localparam [33:0] one34_lp = 1;
localparam [34:0] one35_lp = 1;
localparam [35:0] one36_lp = 1;
localparam [36:0] one37_lp = 1;
localparam [37:0] one38_lp = 1;
localparam [38:0] one39_lp = 1;
localparam [39:0] one40_lp = 1;
localparam [49:0] one50_lp = 1;
localparam [59:0] one60_lp = 1;
localparam [60:0] one61_lp = 1;
localparam [61:0] one62_lp = 1;
localparam [62:0] one63_lp = 1;
localparam [63:0] one64_lp = 1;
localparam [64:0] one65_lp = 1;
localparam [65:0] one66_lp = 1;
localparam [66:0] one67_lp = 1;
localparam [67:0] one68_lp = 1;
localparam [68:0] one69_lp = 1;
localparam [69:0] one70_lp = 1;
bit all_ok = 1;
initial begin
`ifdef TEST_VERBOSE
$display("one1_lp : %x %d", one1_lp, one1_lp==1);
$display("one2_lp : %x %d", one2_lp, one2_lp==1);
$display("one3_lp : %x %d", one3_lp, one3_lp==1);
$display("one4_lp : %x %d", one4_lp, one4_lp==1);
$display("one5_lp : %x %d", one5_lp, one5_lp==1);
$display("one6_lp : %x %d", one6_lp, one6_lp==1);
$display("one7_lp : %x %d", one7_lp, one7_lp==1);
$display("one8_lp : %x %d", one8_lp, one8_lp==1);
$display("one9_lp : %x %d", one9_lp, one9_lp==1);
$display("one10_lp: %x %d", one10_lp, one10_lp==1);
$display("one20_lp: %x %d", one20_lp, one20_lp==1);
$display("one30_lp: %x %d", one30_lp, one30_lp==1);
$display("one31_lp: %x %d", one31_lp, one31_lp==1);
$display("one32_lp: %x %d", one32_lp, one32_lp==1);
$display("one33_lp: %x %d", one33_lp, one33_lp==1);
$display("one34_lp: %x %d", one34_lp, one34_lp==1);
$display("one35_lp: %x %d", one35_lp, one35_lp==1);
$display("one36_lp: %x %d", one36_lp, one36_lp==1);
$display("one37_lp: %x %d", one37_lp, one37_lp==1);
$display("one38_lp: %x %d", one38_lp, one38_lp==1);
$display("one39_lp: %x %d", one39_lp, one39_lp==1);
$display("one40_lp: %x %d", one40_lp, one40_lp==1);
$display("one50_lp: %x %d", one50_lp, one50_lp==1);
$display("one60_lp: %x %d", one60_lp, one60_lp==1);
$display("one61_lp: %x %d", one61_lp, one61_lp==1);
$display("one62_lp: %x %d", one62_lp, one62_lp==1);
$display("one63_lp: %x %d", one63_lp, one63_lp==1);
$display("one64_lp: %x %d", one64_lp, one64_lp==1);
$display("one65_lp: %x %d", one65_lp, one65_lp==1);
$display("one66_lp: %x %d", one66_lp, one66_lp==1);
$display("one67_lp: %x %d", one67_lp, one67_lp==1);
$display("one68_lp: %x %d", one68_lp, one68_lp==1);
$display("one69_lp: %x %d", one69_lp, one69_lp==1);
$display("one70_lp: %x %d", one70_lp, one70_lp==1);
`endif
all_ok &= one1_lp == 1;
all_ok &= one2_lp == 1;
all_ok &= one3_lp == 1;
all_ok &= one4_lp == 1;
all_ok &= one5_lp == 1;
all_ok &= one6_lp == 1;
all_ok &= one7_lp == 1;
all_ok &= one8_lp == 1;
all_ok &= one9_lp == 1;
all_ok &= one10_lp == 1;
all_ok &= one20_lp == 1;
all_ok &= one30_lp == 1;
all_ok &= one31_lp == 1;
all_ok &= one32_lp == 1;
all_ok &= one33_lp == 1;
all_ok &= one34_lp == 1;
all_ok &= one35_lp == 1;
all_ok &= one36_lp == 1;
all_ok &= one37_lp == 1;
all_ok &= one38_lp == 1;
all_ok &= one39_lp == 1;
all_ok &= one40_lp == 1;
all_ok &= one50_lp == 1;
all_ok &= one60_lp == 1;
all_ok &= one61_lp == 1;
all_ok &= one62_lp == 1;
all_ok &= one63_lp == 1;
all_ok &= one64_lp == 1;
all_ok &= one65_lp == 1;
all_ok &= one66_lp == 1;
all_ok &= one67_lp == 1;
all_ok &= one68_lp == 1;
all_ok &= one69_lp == 1;
all_ok &= one70_lp == 1;
if (!all_ok) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, r, an; cin >> n >> r; if (r < n) an = (r) * (r + 1) / 2; else { an = (n) * (n - 1) / 2; an++; } cout << an; cout << n ; } }
|
#include <bits/stdc++.h> #define int long long #define boost ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL) using namespace std; #define MOD 1000000007 #define nline n #define pb push_back #define mp make_pair #define fi first #define se second #define yes cout<< YES n #define no cout<< NO n #define vi vector<int> #define pii pair<int,int> #define sz(v) v.size() #define lcm(a,b) (a*b)/(__gcd(a,b)) #define deb(x) cout<<#x<< = <<x<<endl; #define deb2(x,y) cout<<#x<< = <<x<< <<#y<< = <<y<<endl; #define deb3(x,y,z) cout<<#x<< = <<x<< <<#y<< = <<y<< <<#z<< = <<z<<endl; #define PR(a,n) cout<<#a<< = ;for(int _=0;_<n;_++)cout<<a[_]<< ;cout<<endl; #define all(v) v.begin(),v.end() #define sortv(v) sort(all(v)); #define sortrev(v) sort(all(v),greater<int>()) #define maxHeap priority_queue<int> #define minHeap priority_queue<int, vector<int>, greater<int>> int pow(int a, int b, int m){ int ans = 1; while(b){ if (b&1) ans = (ans*a) % m; b /= 2; a = (a*a) % m; } return ans; } int SumOfDigits(int x) { if (x < 0)return -1; int s = 0; while(x) { s += x%10; x /= 10; } return s; } //lower_bound = first element >= val, end otherwise //upper_bound = first element > val, end otherwise //remember 2 pointer , binary search , bits method //always look for the edges i.e max value ad min value possible inline void solve() { int k,n,m; cin>>k>>n>>m; int a[n],b[m]; int cnt1 = 0,cnt2=0; vi x,y; for(int i=0;i<n;i++) { cin>>a[i]; } for(int i=0;i<m;i++) { cin>>b[i]; } vi ans; int i=0,j=0; int total = k; while(1) { if(sz(ans)==n+m) break; if(a[i]==0 && i<n) { ans.pb(0); total++; i++; continue; } else if(b[j]==0 && j<m) { ans.pb(0); total++; j++; continue; } if(( a[i]<b[j] && (i<n && j<m) ) || (i<n && j>=m)) { if(total>=a[i]) { ans.pb(a[i]); i++; } else { cout<<-1<<nline; return; } } else if( (a[i]>=b[j] && (j<m && i<n)) || (j<m && i>=n) ) { if(total>=b[j]) { ans.pb(b[j]); j++; } else { cout<<-1<<nline; return; } } } if(sz(ans)==n+m) { for(auto x:ans) cout<<x<< ; cout<<nline; } else cout<<-1<<nline; return; } signed main() { boost; int t=1; cin>>t; for(int tt=1;tt<=t;tt++) { // cout<< Case # <<tt<< : ; solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, -1, 0, 1}; inline int read() { int ans = 0; bool f = 1; char ch = getchar(); while (!isdigit(ch)) f ^= ch == - , ch = getchar(); while (isdigit(ch)) ans = ((ans << 2) + ans << 1) + (ch ^ 48), ch = getchar(); return f ? ans : -ans; } long long n, m; bool CanMove(long long x, long long y) { return (x >= 0 && x < n && y >= 0 && y < m); } long long DFS1(long long x, long long y, long long sx, long long sy) { x--, y--; sx--, sy--; long long val[n][m]; queue<pair<long long, long long> > q; for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) val[i][j] = 0; q.push(make_pair(x, y)); val[x][y] = 1; while (!q.empty()) { pair<long long, long long> p = q.front(); q.pop(); long long X = p.first, Y = p.second; if (CanMove(X + 1, Y + 2) && val[X + 1][Y + 2] == 0) { q.push(make_pair(X + 1, Y + 2)); val[X + 1][Y + 2] = val[X][Y] + 1; } if (CanMove(X + 1, Y - 2) && val[X + 1][Y - 2] == 0) { q.push(make_pair(X + 1, Y - 2)); val[X + 1][Y - 2] = val[X][Y] + 1; } if (CanMove(X - 1, Y + 2) && val[X - 1][Y + 2] == 0) { q.push(make_pair(X - 1, Y + 2)); val[X - 1][Y + 2] = val[X][Y] + 1; } if (CanMove(X - 1, Y - 2) && val[X - 1][Y - 2] == 0) { q.push(make_pair(X - 1, Y - 2)); val[X - 1][Y - 2] = val[X][Y] + 1; } if (CanMove(X + 2, Y + 1) && val[X + 2][Y + 1] == 0) { q.push(make_pair(X + 2, Y + 1)); val[X + 2][Y + 1] = val[X][Y] + 1; } if (CanMove(X + 2, Y - 1) && val[X + 2][Y - 1] == 0) { q.push(make_pair(X + 2, Y - 1)); val[X + 2][Y - 1] = val[X][Y] + 1; } if (CanMove(X - 2, Y + 1) && val[X - 2][Y + 1] == 0) { q.push(make_pair(X - 2, Y + 1)); val[X - 2][Y + 1] = val[X][Y] + 1; } if (CanMove(X - 2, Y - 1) && val[X - 2][Y - 1] == 0) { q.push(make_pair(X - 2, Y - 1)); val[X - 2][Y - 1] = val[X][Y] + 1; } } return val[sx][sy]; } vector<pair<long long, long long> > DFS2(long long x, long long y, long long sx, long long sy) { x--, y--; sx--, sy--; long long val[n][m]; pair<long long, long long> pre[n][m]; for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) val[i][j] = 0; vector<pair<long long, long long> > v; v.clear(); queue<pair<long long, long long> > q; q.push(make_pair(x, y)); val[x][y] = 1; while (!q.empty()) { pair<long long, long long> pp = q.front(); q.pop(); long long X = pp.first, Y = pp.second; if (CanMove(X + 1, Y + 2) && val[X + 1][Y + 2] == 0) { q.push(make_pair(X + 1, Y + 2)); val[X + 1][Y + 2] = val[X][Y] + 1; pre[X + 1][Y + 2] = make_pair(X, Y); } if (CanMove(X + 1, Y - 2) && val[X + 1][Y - 2] == 0) { q.push(make_pair(X + 1, Y - 2)); val[X + 1][Y - 2] = val[X][Y] + 1; pre[X + 1][Y - 2] = make_pair(X, Y); } if (CanMove(X - 1, Y + 2) && val[X - 1][Y + 2] == 0) { q.push(make_pair(X - 1, Y + 2)); val[X - 1][Y + 2] = val[X][Y] + 1; pre[X - 1][Y + 2] = make_pair(X, Y); } if (CanMove(X - 1, Y - 2) && val[X - 1][Y - 2] == 0) { q.push(make_pair(X - 1, Y - 2)); val[X - 1][Y - 2] = val[X][Y] + 1; pre[X - 1][Y - 2] = make_pair(X, Y); } if (CanMove(X + 2, Y + 1) && val[X + 2][Y + 1] == 0) { q.push(make_pair(X + 2, Y + 1)); val[X + 2][Y + 1] = val[X][Y] + 1; pre[X + 2][Y + 1] = make_pair(X, Y); } if (CanMove(X + 2, Y - 1) && val[X + 2][Y - 1] == 0) { q.push(make_pair(X + 2, Y - 1)); val[X + 2][Y - 1] = val[X][Y] + 1; pre[X + 2][Y - 1] = make_pair(X, Y); } if (CanMove(X - 2, Y + 1) && val[X - 2][Y + 1] == 0) { q.push(make_pair(X - 2, Y + 1)); val[X - 2][Y + 1] = val[X][Y] + 1; pre[X - 2][Y + 1] = make_pair(X, Y); } if (CanMove(X - 2, Y - 1) && val[X - 2][Y - 1] == 0) { q.push(make_pair(X - 2, Y - 1)); val[X - 2][Y - 1] = val[X][Y] + 1; pre[X - 2][Y - 1] = make_pair(X, Y); } } while (sx != x || sy != y) { v.push_back(make_pair(sx + 1, sy + 1)); pair<long long, long long> pp = pre[sx][sy]; sx = pp.first, sy = pp.second; } return v; } vector<pair<long long, long long> > v; long long x, y, sx, sy; long long fl1, fl2; int main(int argc, char const *argv[]) { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> x >> y >> sx >> sy; fl1 = ((x + y) % 2 != (sx + sy) % 2); long long aa = DFS1(x, y, n / 2, m / 2); long long bb = DFS1(sx, sy, n / 2, m / 2); long long cc = DFS1(x, y, n / 2 + 1, m / 2); long long dd = DFS1(sx, sy, n / 2 + 1, m / 2); if (fl1 == 0) fl2 = ((dd < aa) || (bb <= aa)); else fl2 = (!((aa <= dd) || ((cc - 1) <= dd))); cout << (fl2 ? BLACK : WHITE ) << endl; if (fl2) { if (fl1) { v = DFS2(sx, sy, n / 2 + 1, m / 2); for (long long i = (long long)v.size() - 1; i >= 0; i--) { long long a, b; cin >> a >> b; cout << v[i].first << << v[i].second << endl; } } else { if (dd < aa) { v = DFS2(sx, sy, n / 2 + 1, m / 2); for (long long i = (long long)v.size() - 1; i >= 0; i--) { long long a, b; cin >> a >> b; cout << v[i].first << << v[i].second << endl; if ((a == v[i].first) && (b == v[i].second)) return 0; } } else { v = DFS2(sx, sy, n / 2, m / 2); for (long long i = (long long)v.size() - 1; i >= 0; i--) { long long a, b; cin >> a >> b; long long c, d; c = abs(sx - a); d = abs(sy - b); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << a << << b << endl; return 0; } else { cout << v[i].first << << v[i].second << endl; sx = v[i].first, sy = v[i].second; } } long long a, b; cin >> a >> b; long long c, d; c = abs(sx - a); d = abs(sy - b); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << a << << b << endl; return 0; } else { sx++, sy += 2; cout << sx << << sy << endl; cin >> a >> b; c = abs(sx - a); d = abs(sy - b); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << a << << b << endl; return 0; } else { sx -= 2; sy--; cout << sx << << sy << endl; sx += 2; sy--; cin >> a >> b; cout << sx << << sy << endl; } } } } } else { if (!fl1) { v = DFS2(x, y, n / 2, m / 2); cout << v[v.size() - 1].first << << v[v.size() - 1].second << endl; for (long long i = (long long)v.size() - 2; i >= 0; i--) { long long a, b; cin >> a >> b; cout << v[i].first << << v[i].second << endl; } } else { if (aa <= dd) { v = DFS2(x, y, n / 2, m / 2); cout << v[v.size() - 1].first << << v[v.size() - 1].second << endl; if (v[v.size() - 1].first == x && v[v.size() - 1].second == y) return 0; for (long long i = (long long)v.size() - 2; i >= 0; i--) { long long a, b; cin >> a >> b; cout << v[i].first << << v[i].second << endl; if (v[i].first == x && v[i].second == y) return 0; } } else { v = DFS2(x, y, n / 2 + 1, m / 2); long long P = sx, Q = sy; long long X = x, Y = y; for (long long i = (long long)v.size() - 1; i >= 0; i--) { long long c, d; c = abs(X - P); d = abs(Y - Q); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << P << << Q << endl; return 0; } else { cout << v[i].first << << v[i].second << endl; cin >> P >> Q; X = v[i].first; Y = v[i].second; } } long long c, d; c = abs(X - P); d = abs(Y - Q); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << P << << Q << endl; return 0; } else { X -= 2, Y++; cout << X << << Y << endl; cin >> P >> Q; c = abs(X - P); d = abs(Y - Q); if ((c == 1 && d == 2) || (c == 2 && d == 1)) { cout << P << << Q << endl; return 0; } else { X += 2, Y++; cout << X << << Y << endl; cin >> P >> Q; X--, Y -= 2; cout << X << << Y << endl; return 0; } } } } } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; const ll INF = 1e18; const ll MOD = 1e9 + 7; const ld EPS = 1e-10; const ld PI = acos(-1); vector<ll> po[2]; ll n, k; pair<ll, ll> CountHash(ll x, ll ind, ll q) { ll h1 = 0, h2 = 0; for (ll i = 2; i * i <= x; ++i) { if (x % i == 0) { ll a = 0; while (x % i == 0) { ++a; x /= i; } a %= k; ll b = (k - a) % k; h1 += a * po[ind][i] % q; h2 += b * po[ind][i] % q; h1 %= q; h2 %= q; } } if (x > 1) { h1 += 1 * po[ind][x] % q; h2 += (k - 1) * po[ind][x] % q; h1 %= q; h2 %= q; } return {h1, h2}; } void solve() { cin >> n >> k; map<pair<ll, ll>, ll> cnt; ll P1 = 239; ll Q1 = 1e9 + 7; ll P2 = 41; ll Q2 = 1e9 + 9; po[0].resize(100000); po[1].resize(100000); po[0][0] = 1; po[1][0] = 1; for (int i = 1; i < 100000; ++i) { po[0][i] = po[0][i - 1] * P1 % Q1; po[1][i] = po[1][i - 1] * P2 % Q2; } ll ans = 0; for (int i = 0; i < n; ++i) { ll x; cin >> x; auto h1 = CountHash(x, 0, Q1); auto h2 = CountHash(x, 1, Q2); ans += cnt[{h1.second, h2.second}]; ++cnt[{h1.first, h2.first}]; } cout << ans << n ; } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { int x1, y1; } ar[500101]; bool cmp(node &b1, node &b2) { if (b1.x1 == b2.x1) return b1.y1 < b2.y1; return b1.x1 < b2.x1; } int main() { long long q, i, j, k, v, c = 0, p1, p2, t, n, x, y, p; cin >> n; for (i = 0; i < n; i++) { cin >> ar[i].x1 >> ar[i].y1; } sort(ar, ar + n, cmp); for (i = 0; i < n; i++) { if (i == 0) { p = min(ar[i].x1, ar[i].y1); } else { p1 = min(ar[i].x1, ar[i].y1); if (p1 >= p) { p = p1; } else if (ar[i].x1 > ar[i].y1) { p = ar[i].x1; } else { p = ar[i].y1; } } } cout << p << endl; return 0; }
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`include "hrfp_defs.vh"
module hrfp_mult_detect_round_overflow(input wire clk,
input wire [53:0] mantissa,
input wire [`EXPONENTBITS-1+1:0] precalculated_exponent4,
output reg [`MANTISSABITS-1:0] new_mantissa,
output reg [`EXPONENTBITS-1:0] new_exponent,
output reg rounding_overflowed);
reg [53:0] mask;
reg true_overflow_happened;
reg overflow_to_msb_part_happened;
// Note: For this variant we don't need to take into account anything larger than 63,
// as we can never get an overflow in that case.
// Proof:
// Maximum mantissa in radix 16 is 111111111111111111111111000.
// 111111111111111111111111000 * 111111111111111111111111000 =
// 111111111111111111111110000000000000000000000001000000 (mantissa before rounding)
// 111111111111111111111110 (mantissa after rounding)
// However, for the case where the result is 00001111111111111111111111111xxxxxxx
// an overflow _can_ happen. (See below)
//// reg [53:0] mask1;
//// always @* begin : CHECK_TRUE_OVERFLOW
//// // FIXME - figure out how many ones are needed in mask1...
//// // The mask is set so that overflow can never happen for this case...
//// mask1 <= 54'b111111111111111111111111111110000000000000000000000000;
//// casez(precalculated_exponent+1)
//// 63: mask1 <= 54'b111111111111111111111100000000000000000000000000000000;
//// 62: mask1 <= 54'b111111111111111111000000000000000000000000000000000000;
//// 61: mask1 <= 54'b111111111111110000000000000000000000000000000000000000;
//// 60: mask1 <= 54'b111111111100000000000000000000000000000000000000000000;
//// 59: mask1 <= 54'b111111000000000000000000000000000000000000000000000000;
//// 58: mask1 <= 54'b110000000000000000000000000000000000000000000000000000;
//// endcase
//// end
reg [53:0] mask3;
always @(posedge clk) begin : CHECK_TRUE_OVERFLOW_PIPED
// FIXME - figure out how many ones are needed in mask1...
// The mask is set so that overflow can never happen for this case...
mask3 <= 54'b111111111111111111111111111110000000000000000000000000;
`ifdef MULT_SUBNORMALS
casez(precalculated_exponent4+1)
63: mask3 <= 54'b111111111111111111111100000000000000000000000000000000;
62: mask3 <= 54'b111111111111111111000000000000000000000000000000000000;
61: mask3 <= 54'b111111111111110000000000000000000000000000000000000000;
60: mask3 <= 54'b111111111100000000000000000000000000000000000000000000;
59: mask3 <= 54'b111111000000000000000000000000000000000000000000000000;
58: mask3 <= 54'b110000000000000000000000000000000000000000000000000000;
endcase
`endif
end
always @* begin
true_overflow_happened = 0;
if(mask3 == (mantissa & mask3)) begin
true_overflow_happened = 1;
end
end
// reg [53:0] mask2;
// always @* begin : CHECK_OVERFLOW_TO_MSB_PART
//
// mask2 <= 54'b000011111111111111111111111110000000000000000000000000;
// casez(precalculated_exponent)
// 63: mask2 <= 54'b000011111111111111111111110000000000000000000000000000;
// 62: mask2 <= 54'b000011111111111111111100000000000000000000000000000000;
// 61: mask2 <= 54'b000011111111111111000000000000000000000000000000000000;
// 60: mask2 <= 54'b000011111111110000000000000000000000000000000000000000;
// 59: mask2 <= 54'b000011111100000000000000000000000000000000000000000000;
// 58: mask2 <= 54'b000011000000000000000000000000000000000000000000000000;
// endcase
// end
reg [53:0] mask4;
always @(posedge clk) begin : CHECK_OVERFLOW_TO_MSB_PART_PIPED
mask4 <= 54'b000011111111111111111111111110000000000000000000000000;
`ifdef MULT_SUBNORMALS
casez(precalculated_exponent4)
63: mask4 <= 54'b000011111111111111111111110000000000000000000000000000;
62: mask4 <= 54'b000011111111111111111100000000000000000000000000000000;
61: mask4 <= 54'b000011111111111111000000000000000000000000000000000000;
60: mask4 <= 54'b000011111111110000000000000000000000000000000000000000;
59: mask4 <= 54'b000011111100000000000000000000000000000000000000000000;
58: mask4 <= 54'b000011000000000000000000000000000000000000000000000000;
endcase
`endif
end
always @* begin
overflow_to_msb_part_happened = 0;
if(mask4 == (mantissa & mask4)) begin
if(!mantissa[53:50]) begin
overflow_to_msb_part_happened = 1;
end
end
end
reg [`EXPONENTBITS -1:0] precalculated_exponent_plus1,precalculated_exponent_plus2;
always @(posedge clk) begin
precalculated_exponent_plus1 <= precalculated_exponent4 + 1;
precalculated_exponent_plus2 <= precalculated_exponent4 + 2;
end
always @* begin
new_mantissa = 27'b0;
new_exponent = 0;
rounding_overflowed = 0;
if(true_overflow_happened) begin
new_mantissa = 27'b000100000000000000000000000;
new_exponent = precalculated_exponent_plus2;
rounding_overflowed = 1;
end
if(overflow_to_msb_part_happened) begin
new_mantissa = 27'b000100000000000000000000000;
new_exponent = precalculated_exponent_plus1;
rounding_overflowed = 1;
end
end
`ifdef DEBUG
integer first = 10;
always @(posedge clk) begin
// $display("Mask 1: %b", mask1);
// $display("Mask 2: %b", mask2);
$display("Mask 3: %b", mask3);
$display("Mask 4: %b", mask4);
$display("Mantissa: %b", mantissa);
$display("mantissa & mask1: %b", mantissa & mask3);
$display("mantissa & mask2: %b", mantissa & mask4);
$display("OVERFLOW %b %b", true_overflow_happened, overflow_to_msb_part_happened);
// if(!first) begin
// if(mask1 !== mask3) begin
// $display("mask1 !== mask3!!! %b %b", mask1, mask3);
// $stop;
// end
// if(mask2 !== mask4) begin
// $display("mask2 !== mask4!!! %b %b", mask2, mask4);
// $stop;
// end
// end
// if(first) first = first - 1;
// if(true_overflow_happened || overflow_to_msb_part_happened) begin
// $stop;
// end
end
`endif
endmodule
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_ceil(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] datain;
wire is_fifo_in_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(datain), .valid_in(i_datain_valid),
.valid_out( is_fifo_in_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_in_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_stall) | !(is_fifo_in_valid);
acl_fp_ceil ceil_unit(.resetn(resetn),
.enable(~is_stalled), .clock(clock), .dataa(datain), .result(o_dataout));
assign o_dataout_valid = shift_reg_valid[0];
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m, q; long long ans, in[N], out[N]; vector<int> f[N]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) { int x, y; scanf( %d%d , &x, &y); if (x > y) swap(x, y); f[x].push_back(y); in[y]++, out[x]++; } for (int i = 1; i <= n; ++i) ans += in[i] * out[i]; printf( %lld n , ans); scanf( %d , &q); while (q--) { int x; scanf( %d , &x); ans -= in[x] * out[x]; in[x] += out[x], out[x] = 0; for (int i = 0; i < f[x].size(); ++i) { int y = f[x][i]; ans -= in[y] * out[y]; out[y]++, in[y]--; ans += in[y] * out[y]; f[y].push_back(x); } f[x].clear(); printf( %lld n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd1 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, ans = 0; vector<int> a[100005]; int main() { cin >> n; for (int i = 1; i <= n; i++) { int k, x; cin >> k; while (k--) { cin >> x; a[i].push_back(x); } sort(a[i].begin(), a[i].end()); } a[0] = a[n]; a[n + 1] = a[1]; for (int i = 1; i <= n; i++) { for (int j = 1; j < a[i].size(); j++) { if (upper_bound(a[i - 1].begin(), a[i - 1].end(), a[i][j]) - lower_bound(a[i - 1].begin(), a[i - 1].end(), a[i][j - 1]) != upper_bound(a[i + 1].begin(), a[i + 1].end(), a[i][j]) - lower_bound(a[i + 1].begin(), a[i + 1].end(), a[i][j - 1])) ans++; } } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int N, M; int arr[MAXN]; int dp[MAXN]; int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> N >> M; int prv; cin >> prv; int lft = 1; for (int a = 2; a <= N; a++) { int cur; cin >> cur; if (prv <= cur) { } else { lft = a; } if (prv >= cur) { dp[a] = min(dp[a - 1], lft); } else { dp[a] = lft; } prv = cur; } while (M--) { int l, r; cin >> l >> r; if (l >= dp[r]) { cout << Yes n ; } else { cout << No n ; } } }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_databuf_pa.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_databuf_pa(/*AUTOARG*/
// Outputs
spc_pcx_data_buf_pa, spc_pcx_data_buf_rdy,
// Inputs
spc_pcx_data_pa, spc_pcx_data_rdy
);
output [123:0]spc_pcx_data_buf_pa;
output spc_pcx_data_buf_rdy;
input [123:0]spc_pcx_data_pa;
input spc_pcx_data_rdy;
assign spc_pcx_data_buf_pa = spc_pcx_data_pa;
assign spc_pcx_data_buf_rdy = spc_pcx_data_rdy;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2019 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.7
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila.v
// /___/ /\ Timestamp : Mon Jan 21 22:21:47 Mitteleuropäische Zeit 2019
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_ila(
CONTROL,
CLK,
TRIG0,
TRIG1,
TRIG2,
TRIG3,
TRIG4) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL;
input CLK;
input [7 : 0] TRIG0;
input [31 : 0] TRIG1;
input [39 : 0] TRIG2;
input [3 : 0] TRIG3;
input [25 : 0] TRIG4;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int L = 2e5 + 7; long long out[L], a[L], counter[1000001], szs = 900; struct node { long long l, r, q; }; bool comp(node x, node y) { long long xx = x.l / szs, yy = y.l / szs; if (xx == yy) return x.r < y.r; return x.l < y.l; } long long ans = 0; void add(int idx) { counter[a[idx]]++; ans += ((counter[a[idx]]) * (counter[a[idx]]) * a[idx] - (counter[a[idx]] - 1) * (counter[a[idx]] - 1) * a[idx]); } void remove(int idx) { counter[a[idx]]--; ans += ((counter[a[idx]]) * (counter[a[idx]]) * a[idx] - (counter[a[idx]] + 1) * (counter[a[idx]] + 1) * a[idx]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int curl, curr, n, m, cur = 0, l, r, b, k; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> a[i]; std::vector<node> v(m); node temp; for (int i = 0; i < m; ++i) { cin >> l >> r; l--, r--; v[i].l = l, v[i].r = r, v[i].q = i; } sort(v.begin(), v.end(), comp); l = 0, r = -1; for (int i = 0; i < m; ++i) { curl = v[i].l, curr = v[i].r; while (r < curr) { ++r; add(r); } while (r > curr) { remove(r); --r; } while (l < curl) { remove(l); l++; } while (l > curl) { --l; add(l); } out[v[i].q] = ans; } for (int i = 0; i < m; ++i) cout << out[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; ifstream in; ofstream out; const long long kk = 1000; const long long ml = kk * kk; const long long mod = ml * kk + 7; const long long inf = ml * ml * ml + 7; long long n, i, j; vector<long long> m; vector<pair<long long, long long> > x; bool viv = false; map<pair<long long, long long>, bool> was; pair<long long, string> ans; string ll_to_str(long long v) { string s = ; if (v == 0) return 0 ; bool obr = false; if (v < 0) obr = true; v = abs(v); while (v > 0) { short e = v % 10; s += char( 0 + e); v /= 10; } reverse(s.begin(), s.end()); if (obr) s = - + s; return s; } void write(pair<long long, long long> a) { if (was[a]) return; was[a] = true; ans.first++; ans.second += ll_to_str(a.first); ans.second += ; ans.second += ll_to_str(a.second); ans.second += n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); x.assign(3, {0, 0}); for (long long i = 0; i < 3; i++) cin >> x[i].first >> x[i].second; sort(x.begin(), x.end()); pair<long long, long long> cur = x[0]; while (cur.first < x[1].first) { write(cur); cur.first++; } while (cur.second < x[1].second) { write(cur); cur.second++; } while (cur.second > x[1].second) { write(cur); cur.second--; } while (cur.second < x[2].second) { write(cur); cur.second++; } while (cur.second > x[2].second) { write(cur); cur.second--; } while (cur.first < x[2].first) { write(cur); cur.first++; } write(cur); cout << ans.first << endl; cout << ans.second << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_8_V
`define SKY130_FD_SC_LS__NOR2_8_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A31O_BEHAVIORAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:47:35 03/24/2015
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: DIV min is 2, don't do 1 or 0
//
//////////////////////////////////////////////////////////////////////////////////
module clk_divider #(
parameter DIV = 2
)(
input rst,
input clk,
output div_clk
);
parameter CTR_SIZE = $clog2(DIV);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg div_clk_d, div_clk_q;
assign div_clk = div_clk_q;
always @(*) begin
div_clk_d = div_clk_q;
ctr_d = ctr_q + 1;
//Div clk goes high at 0, and lasts period of clk
if (ctr_q == 0) begin
div_clk_d = 1;
end else begin
div_clk_d = 0;
end
//Restart when reach DIV cnts
if(ctr_q == DIV-1) begin
ctr_d = 0;
end
end
always @(posedge clk) begin
if (rst) begin
div_clk_q <= 0;
ctr_q <= 0;
end else begin
div_clk_q <= div_clk_d;
ctr_q <= ctr_d;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_TB_V
`define SKY130_FD_SC_LS__O2BB2AI_TB_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2ai.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ls__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_TB_V
|
`default_nettype none
// ============================================================================
module transmitter #
(
parameter WIDTH = 8,
parameter MODE = "SDR"
)
(
// Input clock and reset
input wire CLK,
input wire RST,
// Data for comparison
output wire O_STB,
output wire [WIDTH-1:0] O_DAT,
// Serialized clock and data
output wire S_CLK,
output wire S_CE,
output wire S_DAT
);
// ============================================================================
// ROM
wire s_clk;
wire s_ce;
wire s_dat;
wire [WIDTH-1:0] rom_dat;
wire rom_rd;
rom rom
(
.CLK (CLK),
.RST (RST),
.RD (rom_rd & s_ce),
.O (rom_dat) // Truncate bits if WIDTH < 8 here.
);
// ============================================================================
// Serializer
serializer #
(
.WIDTH (WIDTH),
.MODE (MODE)
)
serializer
(
.CLK (CLK),
.RST (RST),
.I (rom_dat),
.RD (rom_rd),
.CE (s_ce),
.O_CLK (s_clk),
.O_DAT (s_dat)
);
assign S_CLK = s_clk;
assign S_CE = s_ce;
assign S_DAT = s_dat;
// ============================================================================
// Parallel output (for later comparison)
reg o_stb;
always @(posedge CLK)
if (RST) o_stb <= 1'b0;
else if (!o_stb && s_ce && rom_rd) o_stb <= 1'b1;
else if ( o_stb) o_stb <= 1'd0;
assign O_STB = o_stb;
assign O_DAT = rom_dat;
// ============================================================================
endmodule
|
//Fake CPU
/* verilator lint_off MULTIDRIVEN */
module CPU (
input reset,
input clk_neg,
input clk_pos,
input ce_n,
input ce_p,
output [15:0] cpu_addr,
output [7:0] cpu_dout,
input [7:0] cpu_din,
output reg nMREQ,
output reg nIORQ,
input nINT,
output reg nRD,
output reg nWR,
output reg nM1,
output reg nRFSH
);
reg [2:0] MCycle, MCycles;
reg [2:0] TState, TStates;
reg [15:0] A;
assign cpu_addr = A;
always @(posedge clk_pos, posedge reset) begin
if (reset) begin
MCycle <= 5;
MCycles <= 5;
TState <= 1;
TStates <= 4;
A <= 16'h0000;
nMREQ <= 1;
nIORQ <= 1;
nRD <= 1;
nWR <= 1;
nM1 <= 0;
nRFSH <= 1;
end else if (ce_p) begin
if (TState == TStates) begin
TState <= 1;
if (MCycle == MCycles)
MCycle <= 1;
else
MCycle <= MCycle + 1'd1;
end else begin
TState <= TState + 1'd1;
end
case (MCycle)
1: // contented M1
case (TState)
2: begin {nMREQ, nRD, nM1} <= 3'b111; nRFSH <= 0; A<=16'h6000; end
4: begin nRFSH <= 1; A<=16'hFFFF; TStates <= 6; end
default: ;
endcase
2:
case (TState)
6: begin A<=16'h00FE; TStates <= 4; end
default: ;
endcase
3: // contented IO
case (TState)
1: begin nIORQ <= 0; nRD <= 0; end
4: begin A<=16'hFFFF; TStates <= 5; end
default: ;
endcase
4:
case (TState)
5: TStates <= 4;
default: ;
endcase
5:
case (TState)
4: begin A<=16'h4000; TStates <= 4; end
default: ;
endcase
default: ;
endcase
end
end
// M1 cycle
always @(posedge clk_neg) begin
if (ce_n) case (MCycle)
1:
case (TState)
1: {nMREQ, nRD} <= 0;
3: nMREQ <= 0;
4: nMREQ <= 1;
default: ;
endcase
2: ;
3:
case (TState)
4: {nIORQ, nRD} <= 2'b11;
default: ;
endcase
4: ;
5: ;
default: ;
endcase
end
/* verilator lint_on MULTIDRIVEN */
endmodule
|
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