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#include <bits/stdc++.h> using namespace std; const int M = 7002; const int N = 100010; int n, q; bitset<M> num[M]; bitset<M> sq[M]; bitset<M> a[N]; vector<int> squareFree; int main() { cin >> n >> q; for (int i = 1; i < M; ++i) { int good = 1; for (int j = 2; j * j <= i; ++j) { if (i % (j * j) == 0) { good = 0; break; } } if (good) squareFree.push_back(i); } for (int i = 1; i < M; ++i) { for (int j = 1; j * j <= i; ++j) { if (i % j == 0) { num[i][j] = num[i][i / j] = 1; } } } for (int i = 1; i < M; ++i) { for (int j : squareFree) { if (i * j > 7000) break; sq[i][i * j] = 1; } } while (q--) { int cmd, x, y, z, v; scanf( %d %d , &cmd, &x); if (cmd == 1) { scanf( %d , &v); a[x] = num[v]; } else if (cmd == 2) { scanf( %d %d , &y, &z); a[x] = a[y] ^ a[z]; } else if (cmd == 3) { scanf( %d %d , &y, &z); a[x] = a[y] & a[z]; } else { scanf( %d , &v); int ans = (sq[v] & a[x]).count() % 2; printf( %d , ans); } } puts( ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 10000 + 10; int n, m; int second[200], a[200]; bool vis[200]; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) scanf( %d , &second[i]); for (int i = 0; i < m; i++) second[i]--; bool win = true; for (int i = 0; i < m - 1; i++) { int next = second[i + 1]; if (next <= second[i]) next += n; if (a[second[i]] == 0 || a[second[i]] != 0 && a[second[i]] == next - second[i]) a[second[i]] = next - second[i]; else win = false; } for (int i = 0; i < n; i++) { if (vis[a[i]] && a[i] != 0) win = false; vis[a[i]] = true; } if (win) { int ind = 1; for (int i = 0; i < n; i++) { if (a[i] == 0) { while (vis[ind]) ind++; a[i] = ind; vis[ind] = true; } } for (int i = 0; i < n; i++) { if (i > 0) printf( ); printf( %d , a[i]); } printf( n ); } else printf( -1 n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ls__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="adders_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.728000,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=302,HLS_SYN_LUT=154}" *)
module adders_io (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
in1,
in1_ap_vld,
in2,
in2_ap_ack,
in_out1_i,
in_out1_i_ap_vld,
in_out1_i_ap_ack,
in_out1_o,
in_out1_o_ap_vld,
in_out1_o_ap_ack
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] in1;
input in1_ap_vld;
input [31:0] in2;
output in2_ap_ack;
input [31:0] in_out1_i;
input in_out1_i_ap_vld;
output in_out1_i_ap_ack;
output [31:0] in_out1_o;
output in_out1_o_ap_vld;
input in_out1_o_ap_ack;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg in2_ap_ack;
reg in_out1_i_ap_ack;
reg in_out1_o_ap_vld;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] in1_preg;
reg [31:0] in1_in_sig;
reg in1_ap_vld_preg;
reg in1_ap_vld_in_sig;
reg in1_blk_n;
reg in_out1_i_blk_n;
reg in_out1_o_blk_n;
wire ap_CS_fsm_state2;
reg [31:0] in_out1_read_reg_68;
reg ap_block_state1;
wire [31:0] tmp1_fu_57_p2;
reg [31:0] tmp1_reg_73;
reg ap_reg_ioackin_in_out1_o_ap_ack;
reg ap_sig_ioackin_in_out1_o_ap_ack;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 in1_preg = 32'd0;
#0 in1_ap_vld_preg = 1'b0;
#0 ap_reg_ioackin_in_out1_o_ap_ack = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b0;
end else begin
if ((1'b1 == ap_CS_fsm_state2)) begin
if ((ap_sig_ioackin_in_out1_o_ap_ack == 1'b1)) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b0;
end else if ((1'b1 == in_out1_o_ap_ack)) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b1;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
in1_ap_vld_preg <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
in1_ap_vld_preg <= 1'b0;
end else if (((1'b1 == in1_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
in1_ap_vld_preg <= in1_ap_vld;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
in1_preg <= 32'd0;
end else begin
if (((1'b1 == in1_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
in1_preg <= in1;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in_out1_read_reg_68 <= in_out1_i;
tmp1_reg_73 <= tmp1_fu_57_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b0 == ap_reg_ioackin_in_out1_o_ap_ack)) begin
ap_sig_ioackin_in_out1_o_ap_ack = in_out1_o_ap_ack;
end else begin
ap_sig_ioackin_in_out1_o_ap_ack = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == in1_ap_vld)) begin
in1_ap_vld_in_sig = in1_ap_vld;
end else begin
in1_ap_vld_in_sig = in1_ap_vld_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
in1_blk_n = in1_ap_vld;
end else begin
in1_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == in1_ap_vld)) begin
in1_in_sig = in1;
end else begin
in1_in_sig = in1_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in2_ap_ack = 1'b1;
end else begin
in2_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in_out1_i_ap_ack = 1'b1;
end else begin
in_out1_i_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
in_out1_i_blk_n = in_out1_i_ap_vld;
end else begin
in_out1_i_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (1'b0 == ap_reg_ioackin_in_out1_o_ap_ack))) begin
in_out1_o_ap_vld = 1'b1;
end else begin
in_out1_o_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
in_out1_o_blk_n = in_out1_o_ap_ack;
end else begin
in_out1_o_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
always @ (*) begin
ap_block_state1 = ((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld));
end
assign in_out1_o = (tmp1_reg_73 + in_out1_read_reg_68);
assign tmp1_fu_57_p2 = (in2 + in1_in_sig);
endmodule //adders_io
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { long long ax, ay, bx, by, cx, cy, ab, bc; double slopeAB, slopeBC; cin >> ax >> ay >> bx >> by >> cx >> cy; if (ax == cx && ay == cy) { cout << Yes n ; } else { ab = (ax - bx) * (ax - bx) + (ay - by) * (ay - by); bc = (cx - bx) * (cx - bx) + (cy - by) * (cy - by); slopeAB = (double)(ay - by) / (double)(ax - bx); slopeBC = (double)(by - cy) / (double)(bx - cx); if (ab == bc && slopeAB != slopeBC) { cout << Yes n ; } else { cout << No n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string intial, code; cin >> intial >> code; int res = 0; for (int i = 0; i < n; i++) { int a = (((intial[i] - 0 ) - (code[i] - 0 )) + 10) % 10; int b = (((code[i] - 0 ) - (intial[i] - 0 )) + 10) % 10; res += min(a, b); } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int h, l, i; cin >> h >> l; long double x; x = (long double)(l * l - h * h) / (long double)(2 * h); std::cout << std::setprecision(9) << x << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_4_V
`define SKY130_FD_SC_LS__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( unroll-loops ) using namespace std; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long n, m, p; cin >> n >> m >> p; vector<long long> a(n); for (long long i = 0; i < n; ++i) cin >> a[i]; vector<long long> b(m); for (long long i = 0; i < m; ++i) cin >> b[i]; for (long long i = 0; i < n; ++i) { bool flag = false; if (a[i] % p != 0) { for (long long j = 0; j < m; ++j) { if (b[j] % p != 0) { flag = true; cout << i + j; break; } } if (flag) { break; } } } return 0; }
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module scalable_proc #
(
parameter NUM_PROCESSING_UNITS = 2, // Number of processing units
parameter UART_PRESCALER = 868 // UART prescaler
)
(
// Closk & reset
input wire CLK,
input wire RST,
// UART
input wire UART_RX,
output wire UART_TX
);
// ============================================================================
// ROM
wire rom_i_stb;
reg [31:0] rom_i_adr; // Fixed to 32-bit. The ROM size must be a power of 2 less than 32
wire rom_o_stb;
wire [31:0] rom_o_dat;
rom rom
(
.CLK (CLK),
.RST (RST),
.I_STB (rom_i_stb),
.I_ADR (rom_i_adr),
.O_STB (rom_o_stb),
.O_DAT (rom_o_dat)
);
// UART transmitt interval
localparam UART_TX_INTERVAL = UART_PRESCALER * 11; // Wait for 10-bits + 1 extra
// ============================================================================
// Input shift register
localparam SREG_BITS = 32 * NUM_PROCESSING_UNITS;
reg [SREG_BITS-1:0] inp_sreg;
wire inp_sreg_i_stb = rom_o_stb;
wire [31:0] inp_sreg_i_dat = rom_o_dat;
reg inp_sreg_o_stb;
always @(posedge CLK)
if (inp_sreg_i_stb) inp_sreg <= (NUM_PROCESSING_UNITS > 1) ? {inp_sreg[SREG_BITS-32-1:0], inp_sreg_i_dat} : inp_sreg_i_dat;
else inp_sreg <= inp_sreg;
always @(posedge CLK or posedge RST)
if (RST) inp_sreg_o_stb <= 1'd0;
else inp_sreg_o_stb <= inp_sreg_i_stb;
// ============================================================================
// Processing units
reg proc_i_stb;
wire [NUM_PROCESSING_UNITS-1:0] proc_o_stb;
wire [SREG_BITS-1:0] proc_o_dat;
genvar i;
generate for(i=0; i<NUM_PROCESSING_UNITS; i=i+1) begin
processing_unit unit
(
.CLK (CLK),
.RST (RST),
.I_STB (proc_i_stb),
.I_DAT (inp_sreg[(i+1)*32-1 : i*32]),
.O_STB (proc_o_stb[i]),
.O_DAT (proc_o_dat[(i+1)*32-1 : i*32])
);
end endgenerate
// ============================================================================
// Output shift register
reg [SREG_BITS-1:0] out_sreg;
wire out_sreg_i_ld = proc_o_stb[0];
wire [SREG_BITS-1:0] out_sreg_i_dat = proc_o_dat;
wire out_sreg_i_sh;
reg out_sreg_o_stb;
wire [3:0] out_sreg_o_dat;
always @(posedge CLK)
if (out_sreg_i_ld) out_sreg <= out_sreg_i_dat;
else if (out_sreg_i_sh) out_sreg <= out_sreg << 4;
else out_sreg <= out_sreg;
assign out_sreg_o_dat = out_sreg[SREG_BITS-1:SREG_BITS-4];
// DEBUG
always @(posedge CLK)
if (proc_o_stb) $display("%X", {4'dx, proc_o_dat});
// ============================================================================
// Control FSM
localparam STATE_INIT = 0;
localparam STATE_LOAD_START = 10;
localparam STATE_LOAD_SHIFT = 11;
localparam STATE_PROC_START = 20;
localparam STATE_PROC_WAIT = 21;
localparam STATE_SEND_START = 30;
localparam STATE_SEND_WAIT = 31;
localparam STATE_SEND_DELIM = 32;
integer fsm;
reg [32:0] fsm_cnt;
wire fsm_pulse;
reg [32:0] fsm_pulse_cnt;
// fsm
always @(posedge CLK or posedge RST)
if (RST) fsm <= STATE_INIT;
else case(fsm)
STATE_INIT: fsm <= STATE_LOAD_START;
STATE_LOAD_START: fsm <= STATE_LOAD_SHIFT;
STATE_LOAD_SHIFT: fsm <= (fsm_cnt[32]) ? STATE_PROC_START : fsm;
STATE_PROC_START: fsm <= STATE_PROC_WAIT;
STATE_PROC_WAIT: fsm <= (proc_o_stb[0]) ? STATE_SEND_START : fsm;
STATE_SEND_START: fsm <= STATE_SEND_WAIT;
STATE_SEND_WAIT: if (fsm_pulse) fsm <= (fsm_cnt[32]) ? STATE_SEND_DELIM : fsm;
STATE_SEND_DELIM: if (fsm_pulse) fsm <= STATE_INIT;
endcase
// fsm_cnt
always @(posedge CLK)
case (fsm)
STATE_LOAD_START: fsm_cnt <= NUM_PROCESSING_UNITS - 2; // 32-bits per shift
STATE_SEND_START: fsm_cnt <= NUM_PROCESSING_UNITS * (32 / 4) - 2; // 4-bits per shift
STATE_SEND_WAIT: if (fsm_pulse) fsm_cnt <= (fsm_cnt[32]) ? fsm_cnt : (fsm_cnt - 1);
default: fsm_cnt <= (fsm_cnt[32]) ? fsm_cnt : (fsm_cnt - 1);
endcase
// fsm_pulse_cnt
always @(posedge CLK or posedge RST)
if (RST) fsm_pulse_cnt <= UART_TX_INTERVAL - 2;
else fsm_pulse_cnt <= (fsm_pulse_cnt[31]) ? UART_TX_INTERVAL - 2 : fsm_pulse_cnt - 1;
assign fsm_pulse = fsm_pulse_cnt[31];
// ============================================================================
// Control signals
wire uart_i_stb;
wire [4:0] uart_i_dat;
assign rom_i_stb = (fsm == STATE_LOAD_SHIFT);
always @(posedge CLK or posedge RST)
if (RST) rom_i_adr <= 0;
else case(fsm)
STATE_LOAD_SHIFT: rom_i_adr <= rom_i_adr + 1;
default: rom_i_adr <= rom_i_adr;
endcase
always @(posedge CLK or posedge RST)
if (RST) proc_i_stb <= 0;
else proc_i_stb <= (fsm == STATE_PROC_START);
assign out_sreg_i_sh = (fsm == STATE_SEND_WAIT) && fsm_pulse;
assign uart_i_stb = fsm_pulse && ((fsm == STATE_SEND_WAIT) ||
(fsm == STATE_SEND_DELIM));
assign uart_i_dat = (fsm == STATE_SEND_WAIT) ? {1'd0, out_sreg_o_dat} :
(fsm == STATE_SEND_DELIM) ? {1'd1, 4'd0} :
{1'd1, 4'd0};
// ============================================================================
// UART string generator
reg uart_x_stb;
reg [7:0] uart_x_dat;
always @(posedge CLK)
case (uart_i_dat)
5'h00: uart_x_dat <= "0";
5'h01: uart_x_dat <= "1";
5'h02: uart_x_dat <= "2";
5'h03: uart_x_dat <= "3";
5'h04: uart_x_dat <= "4";
5'h05: uart_x_dat <= "5";
5'h06: uart_x_dat <= "6";
5'h07: uart_x_dat <= "7";
5'h08: uart_x_dat <= "8";
5'h09: uart_x_dat <= "9";
5'h0A: uart_x_dat <= "A";
5'h0B: uart_x_dat <= "B";
5'h0C: uart_x_dat <= "C";
5'h0D: uart_x_dat <= "D";
5'h0E: uart_x_dat <= "E";
5'h0F: uart_x_dat <= "F";
5'h10: uart_x_dat <= "\n";
default: uart_x_dat <= " ";
endcase
always @(posedge CLK or posedge RST)
if (RST) uart_x_stb <= 1'd0;
else uart_x_stb <= uart_i_stb;
// ============================================================================
// UART
// Baudrate prescaler initializer
reg [7:0] reg_div_we_sr;
wire reg_div_we;
always @(posedge CLK or posedge RST)
if (RST) reg_div_we_sr <= 8'h01;
else reg_div_we_sr <= {reg_div_we_sr[6:0], 1'd0};
assign reg_div_we = reg_div_we_sr[7];
// The UART
simpleuart uart
(
.clk (CLK),
.resetn (!RST),
.ser_rx (UART_RX),
.ser_tx (UART_TX),
.reg_div_we ({reg_div_we, reg_div_we, reg_div_we, reg_div_we}),
.reg_div_di (UART_PRESCALER),
.reg_div_do (),
.reg_dat_we (uart_x_stb),
.reg_dat_re (1'd0),
.reg_dat_di ({24'd0, uart_x_dat}),
.reg_dat_do (),
.reg_dat_wait ()
);
// Debug
always @(posedge CLK)
if (uart_x_stb)
$display("%c", uart_x_dat);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; long double a[maxn]; int main() { int n, s; long long k, b; while (~scanf( %d , &n)) { s = 0; for (int i = 0; i < n; i++) { scanf( %I64d %I64d , &k, &b); if (k != 0) { a[s++] = -(double)(b * 1.0) / (k * 1.0); } } sort(a, a + s); int count = 0; for (int i = 1; i < s; i++) { if (fabs(a[i] - a[i - 1]) > 0) { count++; } } if (s > 0) { count++; } printf( %d n , count); } return 0; }
|
`timescale 1ns / 1ps
`define NUM_CH 2
`define NUM_CH_LOG2 1
// `define TEST_32_48
// `define TEST_96192
`define PRELOAD
`define NODUMP
module resampler_t;
parameter DATALEN = 100000;
reg [15:0] testdata [DATALEN-1:0];
reg [16:0] testdata_iter;
wire [15:0] testdata_curr = testdata[testdata_iter];
wire [23:0] testdata_curr_exp = {testdata_curr, 8'b0}; //{{8{testdata_curr[15]}}, testdata_curr};
reg [23:0] simple_increment_ff;
parameter TCLK = 10; // 98.304Mhz ~ 100Mhz
reg clk;
reg rst;
wire [(`NUM_CH-1):0] rst_ch = 2'b00;
reg [(`NUM_CH-1):0] ack_i;
reg [(24*`NUM_CH-1):0] data_i;
reg [(24*`NUM_CH-1):0] data_i2;
reg [(`NUM_CH-1):0] pop_i;
wire [23:0] bank_data;
`ifdef TEST_32_48
wire [5:0] bank_addr;
rom_firbank_32_48 bank_32_48(.clk(clk), .addr(bank_addr), .data(bank_data));
ringbuffered_resampler #(
.NUM_CH(`NUM_CH), .NUM_CH_LOG2(`NUM_CH_LOG2),
.HALFDEPTH(16), .HALFDEPTH_LOG2(4),
.NUM_FIR(3), .NUM_FIR_LOG2(2), .DECIM(2),
.TIMESLICE(64), .TIMESLICE_LOG2(6))
`elsif TEST_96192
wire [3:0] bank_addr;
rom_firbank_96_192 bank(.clk(clk), .addr(bank_addr), .data(bank_data));
ringbuffered_resampler #(
.NUM_CH(`NUM_CH), .NUM_CH_LOG2(`NUM_CH_LOG2),
.HALFDEPTH(8), .HALFDEPTH_LOG2(3),
.NUM_FIR(2), .NUM_FIR_LOG2(1), .DECIM(1),
.TIMESLICE(32), .TIMESLICE_LOG2(5))
`else
wire [11:0] bank_addr;
rom_firbank_441_480 bank(.clk(clk), .addr(bank_addr), .data(bank_data));
ringbuffered_resampler #(.NUM_CH(`NUM_CH), .NUM_CH_LOG2(`NUM_CH_LOG2))
`endif
uut(
.clk(clk), .rst(rst), .rst_ch(rst_ch),
.bank_addr_o(bank_addr), .bank_data_i(bank_data),
.ack_i(ack_i), .data_i(data_i),
.pop_i(pop_i)
);
integer i;
initial begin
`ifndef NODUMP
$dumpfile("resampler_t.lxt");
$dumpvars(0, resampler_t);
`endif
$readmemh("testdata/damashie.hex", testdata);
testdata_iter = 0;
simple_increment_ff = 0;
clk = 1'b0;
data_i = 24'h0;
rst = 1'b0;
#(TCLK);
rst = 1'b1;
#TCLK;
rst = 1'b0;
#TCLK;
`ifdef PRELOAD
for (i = 0; i < 64; i = i + 1) begin
#(TCLK);
data_i = {simple_increment_ff, testdata_curr_exp};
testdata_iter = testdata_iter + 1;
simple_increment_ff = simple_increment_ff + 1;
ack_i = 2'b11;
end
ack_i = 2'b00;
`endif
`ifndef NODUMP
#3_000;
$finish(2);
`endif
end
always #(TCLK/2) clk = ~clk;
always begin
pop_i = 2'b11;
#(TCLK);
pop_i = 2'b00;
#(TCLK*63);
end
always @(posedge uut.pop_o[0]) begin
#(TCLK);
data_i = {24'h0, testdata_curr_exp};
testdata_iter = testdata_iter+1;
if (testdata_iter == 256)
$finish(2);
ack_i[0] = 1;
#(TCLK);
ack_i[0] = 0;
end
always @(posedge uut.pop_o[1]) begin
#(TCLK);
data_i = {simple_increment_ff, 24'h0};
simple_increment_ff = simple_increment_ff + 1;
ack_i[1] = 1;
#(TCLK);
ack_i[1] = 0;
end
always @(posedge uut.ack_o[1]) begin
$display("%d", $signed(uut.data_o));
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max interp rate of 128
// NOTE signal "rate" is EQUAL TO the actual rate (no more -1 BS)
module cic_int_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases
8'd1 : bitgain = 0;
8'd2 : bitgain = 3;
8'd4 : bitgain = 6;
8'd8 : bitgain = 9;
8'd16 : bitgain = 12;
8'd32 : bitgain = 15;
8'd64 : bitgain = 18;
8'd128 : bitgain = 21;
// Nearest without overflow
8'd3 : bitgain = 5;
8'd5 : bitgain = 7;
8'd6 : bitgain = 8;
8'd7 : bitgain = 9;
8'd9,8'd10 : bitgain = 10;
8'd11,8'd12 : bitgain = 11;
8'd13,8'd14,8'd15 : bitgain = 12;
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
default : bitgain = 21;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd0 : signal_out = signal_in[0+bw-1:0];
5'd3 : signal_out = signal_in[3+bw-1:3];
5'd6 : signal_out = signal_in[6+bw-1:6];
5'd9 : signal_out = signal_in[9+bw-1:9];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd5 : signal_out = signal_in[5+bw-1:5];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
default : signal_out = signal_in[21+bw-1:21];
endcase // case(shift)
endmodule // cic_int_shifter
|
`include "../defined.vh"
module Bus_Mux
(
imm_in,
reg_source,
a_mux,
a_out,
reg_target,
b_mux,
b_out,
c_bus,
c_memory,
c_pc,
c_pc_plus4,
c_mux,
reg_dest_out,
branch_func,
take_branch
);
input [15:0] imm_in;
input [31:0] reg_source;
input [1:0] a_mux;
output [31:0] a_out;
reg [31:0] a_out;
input [31:0] reg_target;
input [1:0] b_mux;
output [31:0] b_out;
reg [31:0] b_out;
input [31:0] c_bus;
input [31:0] c_memory;
input [31:2] c_pc;
input [31:2] c_pc_plus4;
input [2:0] c_mux;
output [31:0] reg_dest_out;
reg [31:0] reg_dest_out;
input [2:0] branch_func;
output take_branch;
reg take_branch;
always@(*)
begin
a_out<=32'b0;
b_out<=32'b0;
reg_dest_out<=32'b0;
take_branch<=0;
case(a_mux)
`A_FROM_REG_SOURCE:
a_out<=reg_source;
`A_FROM_IMM10_6:
a_out<={27'b0,imm_in[10:6]};
`A_FROM_PC:
a_out<={c_pc,2'b0};
default:
a_out<=32'b0;
endcase
case(b_mux)
`B_FROM_REG_TARGET:
b_out<=reg_target;
`B_FROM_IMM:
b_out<={16'b0,imm_in};
`B_FROM_SIGNED_IMM:
b_out<={{16{imm_in[15]}},imm_in};
`B_FROM_IMMX4:
b_out<={14'b0,imm_in,2'b0};
default:
b_out<=32'b0;
endcase
case(c_mux)
`C_FROM_NULL:
reg_dest_out<=32'b0;
`C_FROM_ALU:
reg_dest_out<=c_bus;
`C_FROM_SHIFT:
reg_dest_out<=c_bus;
`C_FROM_MULT:
reg_dest_out<=c_bus;
`C_FROM_MEMORY:
reg_dest_out<=c_memory;
`C_FROM_PC:
reg_dest_out<={c_pc,2'b0};
`C_FROM_PC_PLUS4:
reg_dest_out<={c_pc_plus4,2'b0};
`C_FROM_IMM_SHIFT16:
reg_dest_out<={imm_in,16'b0};
`C_FROM_REG_SOURCEN:
reg_dest_out<=reg_source;
default:
reg_dest_out<=32'b0;
endcase
case(branch_func)
`BRANCH_LTZ:
take_branch<=(c_bus[31])?1:0;
`BRANCH_LEZ:
take_branch<=(c_bus[31])?1:(c_bus==32'b0)?1:0;
`BRANCH_EQ:
take_branch<=(c_bus==32'b0)?1:0;
`BRANCH_NE:
take_branch<=(c_bus==32'b0)?0:1;
`BRANCH_GEZ:
take_branch<=(c_bus[31])?0:1;
`BRANCH_GTZ:
take_branch<=(c_bus[31])?0:(c_bus==32'b0)?0:1;
`BRANCH_YES:
take_branch<=1;
`BRANCH_NO:
take_branch<=0;
default:
take_branch<=0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using P = pair<int, int>; constexpr ll INF = (1LL << 30) - 1LL; constexpr ll LINF = (1LL << 60) - 1LL; constexpr ll MOD = 1e9 + 7; template <typename T> void chmin(T &a, T b) { a = min(a, b); } template <typename T> void chmax(T &a, T b) { a = max(a, b); } template <typename T> struct Median { priority_queue<T> smq; priority_queue<T, vector<T>, greater<T>> lgq; void push(T x) { if (smq.empty()) { smq.push(x); return; } T t = smq.top(); if (smq.size() > lgq.size()) { if (t <= x) { lgq.push(x); } else { lgq.push(t); smq.pop(); smq.push(x); } } else { if (t >= x) { smq.push(x); } else { lgq.push(x); smq.push(lgq.top()); lgq.pop(); } } } inline T get() { return smq.top(); } }; template <typename T> struct BinaryIndexedTree { vector<T> node; int n; BinaryIndexedTree(int n) : n(n) { node.assign(++n, 0); } void add(int k, T x) { for (++k; k < n; k += k & -k) { node[k] += x; } } T sum(int k) { if (k < 0) { return 0; } T res = 0; for (++k; k > 0; k -= k & -k) { res += node[k]; } return res; } }; int main() { cin.tie(0); ios::sync_with_stdio(false); int n; cin >> n; vector<int> p(n), pos(n + 1); for (int i = 0; i < n; i++) { cin >> p[i]; pos[p[i]] = i; } BinaryIndexedTree<ll> bit(n + 1), bit2(n + 1); for (int i = 0; i < n; i++) { bit2.add(i, 1); } ll res = 0; Median<ll> med; for (int k = 1; k <= n; k++) { res += bit.sum(n - 1) - bit.sum(pos[k]); res -= min(bit.sum(pos[k] - 1), bit.sum(n - 1) - bit.sum(pos[k])); bit.add(pos[k], 1); bit2.add(pos[k], -1); int t; if (k % 2 > 0) { med.push(pos[k]); } if (k > 1) { t = med.get(); if (t < pos[k]) { res += bit2.sum(pos[k]) - bit2.sum(t - 1); } else { res += bit2.sum(t) - bit2.sum(pos[k] - 1); } if (k % 2 == 0) { med.push(pos[k]); } } cout << res; if (k < n) { cout << ; } else { cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t) { t--; long long int n, k; cin >> n >> k; long long int a[k]; map<long long int, long long int> m; for (int i = 0; i < k; ++i) { cin >> a[i]; m[a[i]]++; } long long int pow = 1, f = 0, ans = 0; while (n) { if (n % 2 == 1) { if (m[pow] == 0) { long long int x = 0; for (long long int i = pow; i < 1000000000; i *= 2) { if (m[i] != 0) { x = i; break; } } m[x]--; while (x != pow && x != 0) { x /= 2; m[x] += 1; ans += 1; } if (x == 0) { f = 1; break; } } else { m[pow]--; } } m[2 * pow] += m[pow] / (2); m[pow] = 0; n /= 2; pow *= 2; } if (f) { cout << -1 << n ; } else { cout << ans << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, last; struct rec { int s, t; } da[50100]; bool cmp(rec a, rec b) { if (a.s < b.s) return true; if (a.s > b.s) return false; if (a.t < b.t) return true; return false; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &da[i].s, &da[i].t); sort(da + 1, da + n + 1, cmp); for (int i = 1; i <= n; i++) if (da[i].t >= last) { last = da[i].t; } else last = da[i].s; printf( %d , last); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_SYMBOL_V
`define SKY130_FD_SC_HS__MUX4_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux4 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:52:26 09/08/2014
// Design Name: lab5dpath
// Module Name: C:/ece4743/projects/lab5_solution/tb_lab5dpath.v
// Project Name: lab5_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab5dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab5dpath;
// Inputs
reg reset;
reg clk;
reg irdy;
reg [9:0] din;
// Outputs
wire ordy;
wire [9:0] dout;
// Instantiate the Unit Under Test (UUT)
lab5dpath uut (
.reset(reset),
.clk(clk),
.irdy(irdy),
.ordy(ordy),
.din(din),
.dout(dout)
);
reg[8*100:1] aline;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
initial begin
clk = 0;
#100 //reset delay
forever #25 clk = ~clk;
end
initial begin
// Initialize Inputs
// Initialize Inputs
#1
reset = 1;
clk = 0;
irdy = 0;
din = 0;
count = 0;
fd = $fopen("multadd_vectors.txt","r");
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
count = count + 1;
din = i_a;
irdy = 1;
@(negedge clk);
irdy = 0;
din = i_b;
@(negedge clk);
din = i_c;
@(negedge clk);
@(negedge clk);
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
@(negedge clk);
//ensure output is still valid
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
@(negedge clk); //wait few clocks
if (ordy != 1) begin
$display("FAIL: ORDY is not asserted\n");
end else begin
if (dout == i_result)
$display("%d PASS, a: %d, b: %d, c: %d, dout: %d\n",count,i_a,i_b,i_c,dout);
else
$display("%d FAIL, a: %d, b: %d, c: %d, y (actual): %d, dout (expected): %d\n",count,i_a,i_b,i_c,dout,i_result);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5001; int n, tmp[N]; vector<int> g[N]; bool vst[N]; void dfs(int c, int p) { bool dp[N]; fill(dp, dp + n + 1, false); dp[0] = true; tmp[c] = 1; for (int ch : g[c]) { if (ch != p) { dfs(ch, c); tmp[c] += tmp[ch]; for (int i = n - 1; i >= 0; --i) { if (dp[i]) { dp[i + tmp[ch]] = true; } } } } for (int i = 1; i <= n; ++i) { dp[n - i - 1] |= dp[i]; } for (int i = 1; i <= n; ++i) { vst[i] |= dp[i]; } } int main() { scanf( %d , &n); for (int i = (1), _i = (n - 1); i <= _i; ++i) { int u, v; scanf( %d %d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1, 1); int cnt = 0; for (int i = (1), _i = (n - 1 - 1); i <= _i; ++i) { if (vst[i]) { cnt += 1; } } printf( %d n , cnt); for (int i = (1), _i = (n - 1 - 1); i <= _i; ++i) { if (vst[i]) { printf( %d %d n , i, n - i - 1); } } }
|
#include <bits/stdc++.h> int main() { int x, y, z; while (scanf( %d%d , &x, &y) == 2) { z = abs(x) + abs(y); if (x > 0) { if (y > 0) printf( 0 %d %d 0 n , z, z); else printf( 0 -%d %d 0 n , z, z); } else { if (y > 0) printf( -%d 0 0 %d n , z, z); else printf( -%d 0 0 -%d n , z, z); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_SYMBOL_V
`define SKY130_FD_SC_LS__OR2B_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_keys (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> factors(long long int n) { vector<long long int> v; for (long long int i = 1; i * i <= n; i++) { if (n % i == 0) { if (i * i == n) v.push_back(i); else { v.push_back(i); v.push_back(n / i); } } } sort(v.begin(), v.end()); return v; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { std::ios_base::sync_with_stdio(false); long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n], i, j; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); map<long long int, long long int> m; long long int temp = a[n - 1]; vector<long long int> sol; m[n - 1] = 1; sol.push_back(temp); long long int ans = temp, index; for (i = 0; i < n; i++) { long long int temp_gcd = INT_MIN; for (j = 0; j < n; j++) { if (m[j] == 0) { long long int temp = gcd(ans, a[j]); if (temp > temp_gcd) { temp_gcd = temp; index = j; } } } m[index] = 1; sol.push_back(a[index]); ans = temp_gcd; } for (i = 0; i < n; i++) { cout << sol[i] << ; } cout << n ; } return 0; }
|
`timescale 1ns / 1ps
module ControlUnit (clk,OPCODE,BOpCode,Zero,BSelector,MemRD,MemWD,RegWrite,RegSelector,PCSelect,Enable1,Enable2,Enable3,Enable4);
input wire clk;
input [4:0] OPCODE;
input [0:0] Zero;
input [4:0] BOpCode;
output reg[0:0] BSelector;
output reg[0:0] MemRD;
output reg[0:0] MemWD;
output reg[0:0] RegWrite;
output reg[1:0] RegSelector;
output reg[0:0] PCSelect;
output reg[0:0] Enable1;
output reg[0:0] Enable2;
output reg[0:0] Enable3;
output reg[0:0] Enable4;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
initial begin
BSelector = 1'd0;
PCSelect= 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
Enable1 = 1'd1;
Enable2 = 1'd1;
Enable3 = 1'd1;
Enable4 = 1'd1;
end
always @ (posedge clk) begin
case(OPCODE)
ADD:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
SUB:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd0 ;
end
ADDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SUBI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
MLT:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
MLTI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
AND:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
OR:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
ANDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
ORI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SLR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd1;
end
SLL:
begin
BSelector = 1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
LDR:
begin
BSelector =1'd1;
MemRD = 1'd1;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
STR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd1;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
BNE:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
BEQ:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
J:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
CMP:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD =1'd0 ;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
NOP:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
default:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
endcase
end
always @ (Zero,BOpCode) begin
if (BOpCode==BNE && !Zero) PCSelect=1'd1;
else if (BOpCode==BEQ && Zero) PCSelect=1'd1;
else PCSelect=1'd0;
end
endmodule
|
`include "SVGA_DEFINES.v"
module CLOCK_GEN
(
SYSTEM_CLOCK,
system_clock_buffered,
pixel_clock,
reset
);
input SYSTEM_CLOCK; // 100MHz LVTTL SYSTEM CLOCK
output system_clock_buffered; // buffered SYSTEM_CLOCK
output pixel_clock; // adjusted SYSTEM_CLOCK
output reset; // reset asserted when DCMs are NOT LOCKED
wire low = 1'b0;
wire high = 1'b1;
// signals associated with the system clock DCM
wire system_dcm_reset;
wire system_dcm_locked;
wire system_clock_in;
wire system_clock_unbuffered;
wire pixel_clock_unbuffered;
wire system_clock_buffered;
wire pixel_clock;
IBUFG SYSTEM_CLOCK_BUF (
.O (system_clock_in),
.I (SYSTEM_CLOCK)
);
// instantiate the clock input buffers for the internal clocks
BUFG SYS_CLOCK_BUF (
.O (system_clock_buffered),
.I (system_clock_unbuffered)
);
BUFG PIXEL_CLOCK_BUF (
.O (pixel_clock),
.I (pixel_clock_unbuffered)
);
assign reset = !system_dcm_locked;
DCM SYSTEM_DCM (
.CLKFB (system_clock_buffered),
.CLKIN (system_clock_in),
.DSSEN (low),
.PSCLK (low),
.PSEN (low),
.PSINCDEC (low),
.RST (system_dcm_reset),
.CLK0 (system_clock_unbuffered),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKDV (),
.CLKFX (pixel_clock_unbuffered),
.CLKFX180 (),
.LOCKED (system_dcm_locked),
.PSDONE (),
.STATUS ()
);
defparam SYSTEM_DCM.CLKDV_DIVIDE = 2.0; // divide the system clock (50 MHz) by 2.0 to determine CLKDV (25 MHz)
defparam SYSTEM_DCM.CLKFX_DIVIDE = `CLK_DIVIDE; // the denominator of the clock multiplier used to determine CLKFX
defparam SYSTEM_DCM.CLKFX_MULTIPLY = `CLK_MULTIPLY; // the numerator of the clock multiplier used to determine CLKFX
defparam SYSTEM_DCM.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam SYSTEM_DCM.CLKIN_PERIOD = 20.0; // period of input clock in ns
defparam SYSTEM_DCM.CLKOUT_PHASE_SHIFT = "NONE"; // phase shift of NONE
defparam SYSTEM_DCM.CLK_FEEDBACK = "1X"; // feedback of NONE, 1X
defparam SYSTEM_DCM.DFS_FREQUENCY_MODE = "LOW"; // LOW frequency mode for frequency synthesis
defparam SYSTEM_DCM.DLL_FREQUENCY_MODE = "LOW"; // LOW frequency mode for DLL
defparam SYSTEM_DCM.DUTY_CYCLE_CORRECTION = "TRUE"; // Duty cycle correction, TRUE
defparam SYSTEM_DCM.PHASE_SHIFT = 0; // Amount of fixed phase shift from -255 to 255
defparam SYSTEM_DCM.STARTUP_WAIT = "FALSE"; // Delay configuration DONE until DCM LOCK FALSE
SRL16 RESET_SYSTEM_DCM (
.Q (system_dcm_reset),
.CLK (system_clock_in),
.D (low),
.A0 (high),
.A1 (high),
.A2 (high),
.A3 (high)
);
defparam RESET_SYSTEM_DCM.INIT = "000F";
endmodule //CLOCK_GEN
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl)
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int sum = 0, n, a[120], x, y, i; cin >> n; for (i = 0; i < n - 1; ++i) { cin >> a[i]; } cin >> x >> y; for (i = x - 1; i < y - 1; ++i) { sum += a[i]; } cout << sum << n ; }
|
#include <bits/stdc++.h> using namespace std; struct node { long long x; bool s; node(long long a, bool b) { x = a, s = b; } }; bool operator<(node a, node b) { return a.x > b.x; } priority_queue<node> pq; int main() { int n; long long temp; cin >> n; long long ans = 0; for (int i = 1; i <= n; i++) { cin >> temp; if (pq.empty() || pq.top().x > temp) { pq.push(node(temp, 0)); } else { long long now = pq.top().x; bool se = pq.top().s; pq.pop(); if (se) pq.push(node(now, 0)); ans += temp - now, pq.push(node(temp, 1)); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> #define FAST ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define ll long long int #define pb push_back #define pob pop_back #define ub upper_bound #define lb lower_bound #define mp make_pair #define f0(i,n) for(i=0;i<n;i++) #define rf0(i,n) for(i=n-1;i>=0;i--) #define f2(i,n) for(i=1;i<n;i++) #define f1(i,n) for(i=1;i<=n;i++) #define fab(i,a,b) for(i=a;i<=b;i++) #define shr ll t;cin>>t; while(t--) #define fi first #define sc second #define pll pair<ll,ll> #define vll vector<ll> #define vpll vector<pll> #define all(v) v.begin(),v.end() #define mod 1000000007 #define dev(a) for(auto it:a)cout<<it<< #define prec(nm,prc) cout<<fixed << setprecision(nm)<<prc #define print(a) cout<<a<<endl; #define nl n using namespace std; bool comp(pll &a,pll &b) { return (a.sc<b.sc); } ll power(ll n,ll p) { if(p==0) return 1; else { ll ans=power(n,p/2)%mod; ans=(ans*ans)%mod; if(p%2==0) return ans; else return ans=(ans*n)%mod; } } bool isPrime(ll n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (ll i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } /********************HAR HAR MAHADEV***********JAI BAJRANG BALI************************/ int main() { FAST; /* ifstream cin; cin.open( input.txt ); ofstream cout; cout.open( output.txt ); */ shr { ll i,j,n,a,b,c,c1,d,m,sum=0,temp,k,k2,k1,ans=0,cnt=0,r=0,e=0,f; string str,stri,om,s; map<ll,ll>mp,mp1; set<ll>st; vector<vll> v; cin>>n>>k; ll x[n][2]; f0(i,n) { cin>>x[i][0]>>x[i][1]; } f0(i,n) { vll vk; f0(j,n) { if(i!=j) { vk.pb(abs(x[i][0]-x[j][0])+abs(x[i][1]-x[j][1])); } } v.pb(vk); r++; } f0(i,v.size()) { ll p=*max_element(all(v[i])); if(p<=k){e=1;break;} } if(e==1)cout<<1; else cout<<-1; cout<<endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_BEHAVIORAL_V
|
//See README and tcl for more info
`include "defines.v"
module roi(input clk,
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter DIN_N = `DIN_N;
parameter DOUT_N = `DOUT_N;
wire div_clk;
wire clk_IBUF_BUFG;
BUFR #(
.BUFR_DIVIDE(2)
) clock_divider (
.I(clk),
.O(div_clk),
.CE(1),
.CLR(0)
);
BUFG clock_buffer (
.I(div_clk),
.O(clk_IBUF_BUFG)
);
genvar i;
generate
//CLK
(* KEEP, DONT_TOUCH *)
reg clk_reg;
always @(posedge clk_IBUF_BUFG) begin
clk_reg <= clk_reg;
end
//DIN
for (i = 0; i < DIN_N; i = i+1) begin:ins
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b01)
) lut (
.I0(din[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O());
end
//DOUT
for (i = 0; i < DOUT_N; i = i+1) begin:outs
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b01)
) lut (
.I0(1'b0),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(dout[i]));
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_mult();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Multiplication_Function #(
.W(W),
.EW(EW),
.SW(SW)
) inst_FPU_Multiplication_Function (
.clk (clk),
.rst (rst),
.beg_FSM (beg_FSM),
.ack_FSM (ack_FSM),
.Data_MX (Data_X),
.Data_MY (Data_Y),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
//Abre el archivo testbench
// FileSaveData = $fopen("vector/add_single/ResultadoXilinxFLM.txt","w");
// $readmemh("vector/add_single/Hexadecimal_A.txt", Array_IN_1);
// $readmemh("vector/add_single/Hexadecimal_B.txt", Array_IN_2);
add_subt = 0;
FileSaveData = $fopen("ResultadoXilinxFLM_MULT.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
beg_FSM = 0;
ack_FSM = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_X = Array_IN_1[contador];
Data_Y = Array_IN_2[contador];
#(PERIOD/4) beg_FSM = 1;
//Wait for the operation ready
@(posedge ready) begin
#(PERIOD+2);
ack_FSM = 1;
#4;
$fwrite(FDataO,"%h\n",final_result_ieee);
end
@(negedge clk) begin
ack_FSM = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
#include<bits/stdc++.h> #define ll long long #define R return #define pb push_back #define SI size() using namespace std; long long t,n,a[100030],ans,w[5030]; int main(){ cin >> t; while(t--){ ans = 0; memset(w,0,sizeof w); cin >> n; for(int i=0;i<n;i++) cin >> a[i]; for(int i=0;i<n;i++){ if(a[i] - w[i] > 1) ans += a[i] - w[i] - 1; if(a[i] - w[i] < 1) w[i+1] += 1 - a[i] + w[i]; if(a[i] > 1) for(int j=i+2;j<=min(i+a[i],n);j++) w[j]++; } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int abs(int x) { return x >= 0 ? x : -x; } int main() { int n; cin >> n; while (n--) { vector<int> x; vector<int> y; char tmp; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { cin >> tmp; if (tmp == K ) { x.push_back(i); y.push_back(j); } } } int tx, ty; tx = abs(x[0] - x[1]); ty = abs(y[0] - y[1]); if ((tx % 4 == 0) && (ty % 4 == 0) && ((tx + ty) % 4 == 0)) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> months = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; const int MAX = 1e5 + 55; const int inf = 1e9 + 77; const int MOD = 1e9 + 7; const double PI = acos(-1.0); const double eps = 1e-7; int main() { long long n; scanf( %I64d , &n); long long div = 3; while (n % div == 0) div *= 3; n /= div; ++n; printf( %I64d , n); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, ans, dp[8][8]; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { int l, r; cin >> l >> r; dp[l][r] = dp[r][l] = 1; } if (n <= 6) cout << m; else { for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { int res = 0; for (int k = 1; k <= n; k++) if (dp[i][k] && dp[j][k]) res++; ans = max(ans, m - res); } cout << ans; } }
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register (64 bit datapath)
*/
module axis_srl_register_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_TB_V
`define SKY130_FD_SC_HD__O21AI_TB_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21ai dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<int> c; vector<bool> used; void dfs(int u, vector<vector<int>>& v) { used[u] = 1; for (int i = 0; i < v[u].size(); i++) { if (c[u] == c[v[u][i]] && !used[v[u][i]]) { dfs(v[u][i], v); } } } int main() { int n; cin >> n; vector<vector<int>> v(n); c.resize(n); used.resize(n, 0); vector<int> cnt(110000); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; v[a].push_back(b); v[b].push_back(a); } for (int i = 0; i < n; i++) { cin >> c[i]; } for (int i = 0; i < n; i++) { if (!used[i]) { cnt[c[i]]++; dfs(i, v); } } multiset<int> data; for (int i = 0; i < 100010; i++) { for (int j = 0; j < cnt[i]; j++) { data.insert(i); } } for (int i = 0; i < n; i++) { bool check = 0; multiset<int> tmp; for (int j = 0; j < v[i].size(); j++) { if (c[v[i][j]] == c[i]) { check = 1; } tmp.insert(c[v[i][j]]); } if (!check) { tmp.insert(c[i]); } if (tmp == data) { cout << YES << endl; cout << i + 1 << endl; return 0; } } cout << NO << endl; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "seq_rec/seq_rec.v"
`include "seq_rec/seq_rec_core.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/flag_domain_crossing.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/ramb_8_to_n.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000_0000;
localparam SEQ_GEN_HIGHADDR = 32'h2000_0000-1;
localparam SEQ_REC_BASEADDR = 32'h2000_0000;
localparam SEQ_REC_HIGHADDR = 32'h3000_0000 - 1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
`ifdef BITS
localparam BITS = `BITS;
`else
localparam BITS = 8;
`endif
`ifdef MEM_KB
localparam MEM_KB = `MEM_KB;
`else
localparam MEM_KB = 1;
`endif
wire EX_START_PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [BITS-1:0] SEQ_OUT;
seq_gen #(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_KB*1024),
.OUT_BITS(BITS)
) i_seq_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_OUT(SEQ_OUT)
);
seq_rec #(
.BASEADDR(SEQ_REC_BASEADDR),
.HIGHADDR(SEQ_REC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_KB*1024),
.IN_BITS(BITS)
) i_seq_rec (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_IN(SEQ_OUT)
);
initial begin
$dumpfile("seq.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e12; const int maxn = 100050; struct STU { int b, c, id; bool operator<(const STU &s) const { return c < s.c || (c == s.c && id < s.id); } }; map<STU, int> mp; bool cmp(const STU &a, const STU &b) { return a.b < b.b; } struct BUG { int a, id; bool operator<(const BUG &s) const { return a < s.a; } }; STU stu[maxn]; BUG bug[maxn]; int N, M, S; int ans[maxn]; bool judge(int times) { mp.clear(); long long pass = 0; int p = M - 1, q = N - 1; map<STU, int>::iterator it; for (; p >= 0; p--) { while (q >= 0 && stu[q].b >= bug[p].a) { mp[stu[q]] = times; q--; } if (p == M - 1 || it->second <= 0) { if (p != M - 1) mp.erase(it); it = mp.begin(); if (it == mp.end()) return false; pass += it->first.c; } ans[bug[p].id] = it->first.id; it->second--; } return pass <= S; } int main() { scanf( %d%d%d , &N, &M, &S); int max_a = 0; for (int i = 0; i < M; i++) scanf( %d , &bug[i].a), bug[i].id = i + 1, max_a = max(max_a, bug[i].a); for (int i = 0; i < N; i++) scanf( %d , &stu[i].b); for (int i = 0; i < N; i++) scanf( %d , &stu[i].c), stu[i].id = i + 1; bool ok = false; for (int i = 0; i < N; i++) if (stu[i].b >= max_a && stu[i].c <= S) ok = true; if (!ok) { printf( NO n ); return 0; } else printf( YES n ); sort(bug, bug + M); sort(stu, stu + N, cmp); int L = 1, H = M, mid; while (L < H) { mid = L + (H - L) / 2; if (judge(mid)) H = mid; else L = mid + 1; } judge(L); for (int i = 1; i < M; i++) printf( %d , ans[i]); printf( %d n , ans[M]); return 0; }
|
#include <bits/stdc++.h> const int N = 500054; const double eps = 3e-10; inline void up(double &x, const double y) { x < y ? x = y : 0.; } inline void down(double &x, const double y) { x > y ? x = y : 0.; } inline double max(const double x, const double y) { return x < y ? y : x; } struct quadratic { double A, B, C; quadratic(double A_ = 0., double B_ = 0., double C_ = 0.) : A(A_), B(B_), C(C_) {} inline double operator()(double x) const { return (A * x + B) * x + C; } inline std::pair<double, double> root(double y) const { if ((((A) <= (0) + eps) && ((A) >= (0) - eps))) return std::pair<double, double>((y - C) / B, NAN); double b = -.5 * B / A, d = b * b + (y - C) / A; return ((d) < (0) - eps) ? std::pair<double, double>(NAN, NAN) : (d = sqrt(max(d, 0.)), std::pair<double, double>(b - d, b + d)); } inline std::pair<double, double> range(double x_min, double x_max) const { assert(x_min <= x_max); std::pair<double, double> ret = std::minmax((*this)(x_min), (*this)(x_max)); double mid = -.5 * B / A; if ((((A) <= (0) + eps) && ((A) >= (0) - eps)) || mid < x_min || x_max < mid) ; else mid = (*this)(mid), down(ret.first, mid), up(ret.second, mid); return ret; } }; struct vec2 { double x, y; vec2(double x0 = 0., double y0 = 0.) : x(x0), y(y0) {} vec2 *read() { scanf( %lf%lf , &x, &y); return this; } inline vec2 operator-() const { return vec2(-x, -y); } inline vec2 operator+(const vec2 &B) const { return vec2(x + B.x, y + B.y); } inline vec2 operator-(const vec2 &B) const { return vec2(x - B.x, y - B.y); } inline vec2 operator*(double k) const { return vec2(x * k, y * k); } inline vec2 operator/(double k) const { return *this * (1.0 / k); } inline double operator*(const vec2 &B) const { return x * B.x + y * B.y; } inline double operator^(const vec2 &B) const { return x * B.y - y * B.x; } inline double norm2() const { return x * x + y * y; } inline double norm() const { return sqrt(x * x + y * y); } inline bool operator<(const vec2 &B) const { return ((x) < (B.x) - eps) || ((x) <= (B.x) + eps) && ((y) < (B.y) - eps); } inline bool operator==(const vec2 &B) const { return (((x) <= (B.x) + eps) && ((x) >= (B.x) - eps)) && (((y) <= (B.y) + eps) && ((y) >= (B.y) - eps)); } }; int n, m, sr = 0; vec2 p[N], unit[N]; double C[N], co[N], u; double st[N]; quadratic f[N]; std::pair<double, double> rg[N]; inline int pred(int x) { return (x ? x : n) - 1; } inline int succ(int x) { return ++x == n ? 0 : x; } void append(double len, int i1, double s1, int i2, double s2) { if (s1 < 0) s1 += C[n]; if (s2 < 0) s2 += C[n]; st[sr + 1] = st[sr] + len; vec2 O = (p[i1] + unit[i1] * s1) - (p[i2] + unit[i2] * s2), v = unit[i1] - unit[i2]; f[sr++] = quadratic(v.norm2(), v * O * 2., O.norm2()); } namespace seg { int n; bool danger; std::pair<double, double> a[N]; inline void reset() { n = 0, danger = false; } inline void insert(double L, double R) { assert(L <= R); int Li = L / u, Ri = R / u; L -= Li * u, R -= Ri * u; if (Li == Ri) a[n++] = std::pair<double, double>(L, R); else if (Li + 1 == Ri && L > R) a[n++] = std::pair<double, double>(L, u), a[n++] = std::pair<double, double>(0, R); else danger = true; } bool exist() { if (danger) return false; int i; double k = 0; std::sort(a, a + n); for (i = 0; i < n; ++i) { if (k < a[i].first) return true; up(k, a[i].second); } return ((k) < (u)-eps); } } // namespace seg inline bool check(double lim) { int i; double L, R, x1, x2; seg::reset(); for (i = 0; i < sr; ++i) { if (L = st[i], R = st[i + 1], (((L) <= (R) + eps) && ((L) >= (R)-eps))) continue; if (lim <= rg[i].first) seg::insert(L, R); else if (lim < rg[i].second) { std::tie(x1, x2) = f[i].root(lim), x1 += L, x2 += L; if (!(L <= x1 && x1 <= R)) std::swap(x1, x2); if (L <= x2 && x2 <= R) f[i].C >= lim ? seg::insert(L, x1), seg::insert(x2, R) : seg::insert(x1, x2); else f[i].C >= lim ? seg::insert(L, x1) : seg::insert(x1, R); } } return seg::exist(); } int main() { int i, j; double L, R, M; scanf( %d%d , &n, &m); for (i = 0; i < n; ++i) p[i].read(); p[n] = *p; for (i = 0; i < n; ++i) L = (p[i] - p[i + 1]).norm(), C[i + 1] = C[i] + L, unit[i] = (p[i + 1] - p[i]) / L; u = C[n] / m; for (i = 0; i < n; ++i) co[i] = fmod(C[i] + C[n] - u, C[n]); j = pred(std::min_element(co, co + n) - co); for (i = 0; i < n; ++i) { for (L = C[i]; C[i] <= co[succ(j)] && co[succ(j)] < C[i + 1]; j = succ(j), L = co[j]) append(co[succ(j)] - L, i, L - C[i], j, L - co[j]); append(C[i + 1] - L, i, L - C[i], j, L - co[j]); } for (i = 0; i < sr; ++i) rg[i] = f[i].range(0, st[i + 1] - st[i]); { vec2 *_1, *_2; std::tie(_1, _2) = std::minmax_element(p, p + n), R = (*_1 - *_2).norm(); } for (L = 0.; L + eps < R;) M = (L + R) * .5, check(M * M) ? R = M : L = M; printf( %.10lg n , (L + R) * .5); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef enum {
E01 = 1,
E03 = 3,
E04 = 4
} my_t;
integer cyc=0;
my_t e;
int arrayfits [e.num]; // Check can use as constant
string all;
// Check constification
initial begin
e = E03;
`checkh(e.first, E01);
`checkh(e.last, E04);
`checkh(e.last(), E04);
`checkh(e.next, E04);
`checkh(e.next(), E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
`checkh(e.num, 3);
`checks(e.name, "E03");
//
all = "";
for (my_t e = e.first; e != e.last; e = e.next) begin
all = {all, e.name};
end
e = e.last;
all = {all, e.name};
`checks(all, "E01E03E04");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
`checks(e.name, "E01");
`checkh(e.next, E03);
`checkh(e.next(1), E03);
//Unsup: `checkh(e.next(2), E04);
`checkh(e.prev, E04);
`checkh(e.prev(1), E04);
//Unsup: `checkh(e.prev(2), E03);
e <= E03;
end
else if (cyc==2) begin
`checks(e.name, "E03");
`checkh(e.next, E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
e <= E04;
end
else if (cyc==3) begin
`checks(e.name, "E04");
`checkh(e.next, E01);
`checkh(e.next(1), E01);
//Unsup: `checkh(e.next(2), E03);
`checkh(e.prev, E03);
`checkh(e.prev(1), E03);
//Unsup: `checkh(e.prev(2), E01);
e <= E01;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pre[2010000]; int n, i, m, j, vis[2010000], la[2010000], lr[2010000], s[2010000], q[2010000], tr[2010000], a[2010000], tim, jid; inline int gi() { int s = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return s; } void Work(long long x) { int j = 1; for (i = 1; i <= n + n; i++) { while (j < min(i, n) + n && pre[j] - pre[i - 1] <= x) ++j; la[i] = j - 1; } ++tim; int ans = n + 1; for (i = 1; i <= la[1]; i++) { int h = 0; if (i > n) i -= n, h = 1; int t = 0, sum = 0, ed = i + n - 1; for (j = i; j <= ed; j = la[j] + 1) { if (vis[j] == tim) { sum += s[j]; if (lr[j] < ed) sum++, j = lr[j] + 1; q[++t] = j, tr[t] = sum; break; } else q[++t] = j, tr[t] = ++sum; } for (j = t; j >= 1; j--) vis[q[j]] = tim, lr[q[j]] = la[q[t]], s[q[j]] = tr[t] - tr[j - 1]; ans = min(ans, sum); if (h) i += n; } i = la[1] + 1; if (i <= n) { int ed = i + n - 1, sum = 0; for (j = i; j <= ed; j = la[j] + 1) ++sum; ans = min(ans, sum); } printf( %d n , ans); } int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) a[i] = a[i + n] = gi(); for (i = 1; i <= n + n; i++) pre[i] = pre[i - 1] + a[i]; while (m--) { long long x; scanf( %I64d , &x); Work(x); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { long long n; cin >> n; set<long long> st; for (long long i = 1; i * i <= n; i++) { if (n % i == 0) { long long a = n / gcd(n, i); st.insert(((a * (a - 1)) / 2) * (n / a) + a); long long m = (n / i); long long b = n / gcd(n, m); st.insert(((b * (b - 1)) / 2) * (n / b) + b); } } for (auto e : st) cout << e << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[200]; int n; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].second; long long tmp = a[i].second; while (tmp % 3 == 0) { a[i].first--; tmp /= 3; } } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) cout << a[i].second << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int vs, ve; int t, d; cin >> vs >> ve >> t >> d; int cur = vs; int sm = vs; int pre = vs; for (int i = 2; i <= t; i++) { while (cur < ve && abs(pre - cur) < d) cur++; if (cur >= ve) { while ((t - i) * d > cur - ve && abs(pre - cur) < d) cur++; while ((t - i) * d < cur - ve && abs(pre - cur) < d) cur--; } pre = cur; sm += cur; } assert(cur == ve); cout << sm; return 0; }
|
`timescale 1 ns / 1 ps
module axis_keyer #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
input wire key_flag,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [BRAM_ADDR_WIDTH-1:0] int_data_reg;
reg [1:0] int_case_reg, int_case_next;
wire [1:0] int_comp_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_data_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_case_reg <= 2'd0;
end
else
begin
int_addr_reg <= int_addr_next;
int_data_reg <= cfg_data;
int_case_reg <= int_case_next;
end
end
assign int_comp_wire = {|int_addr_reg, int_addr_reg < int_data_reg};
always @*
begin
int_addr_next = int_addr_reg;
int_case_next = int_case_reg;
case(int_case_reg)
2'd0:
begin
if(key_flag & int_comp_wire[0])
begin
int_case_next = 2'd1;
end
end
2'd1:
begin
if(m_axis_tready)
begin
if(int_comp_wire[0])
begin
int_addr_next = int_addr_reg + 1'b1;
end
else
begin
int_case_next = 2'd2;
end
end
end
2'd2:
begin
if(~key_flag)
begin
int_case_next = 2'd3;
end
end
2'd3:
begin
if(m_axis_tready)
begin
if(int_comp_wire[1])
begin
int_addr_next = int_addr_reg - 1'b1;
end
else
begin
int_case_next = 2'd0;
end
end
end
endcase
end
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = 1'b1;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready ? int_addr_next : int_addr_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(NULL); unordered_map<int, int> idx; int N, x; cin >> N; while (N--) { cin >> x; if (x) idx[x] = 1; } cout << idx.size() << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; vector<pair<long long, long long>> ar(m); for (int i = 0; i < m; ++i) { cin >> ar[i].first >> ar[i].second; } sort(ar.begin(), ar.end()); vector<long long> psa(m + 1); for (int i = 1; i < m + 1; ++i) { psa[i] = psa[i - 1] + ar[i - 1].first; } long long ans = 0; for (int i = 0; i < m; ++i) { long long a = ar[i].first; long long b = ar[i].second; int j = lower_bound(ar.begin(), ar.end(), make_pair(b, LLONG_MAX)) - ar.begin(); long long cur = 0; if (m - j <= n) { cur += psa[m] - psa[j]; int x = n - (m - j); cur += a + (x - 1) * b; if (j <= i) { cur -= a; cur += b; } } else { cur += psa[m] - psa[m - n]; } ans = max(ans, cur); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> A; vector<pair<int, int> > M; vector<int> PP; int turn; set<int> Go; int ans(int x) { cout << x + 1 << endl; if (Go.empty()) exit(0); cin >> x; return x - 1; } signed main() { ; cin >> n >> m; A.resize(n << 1); for (auto &x : A) cin >> x; M.resize(m); for (auto &x : M) cin >> x.first >> x.second, x.first--, x.second--; PP.assign(n << 1, -1); for (auto x : M) PP[x.first] = x.second, PP[x.second] = x.first; for (int i = 0; i < n << 1; i++) { Go.insert(i); } cin >> turn; if (turn == 1) { for (auto x : M) { if (A[x.first] > A[x.second]) { ans(x.first); Go.erase(x.first); Go.erase(x.second); } else { ans(x.second); Go.erase(x.first); Go.erase(x.second); } } while (Go.size()) { int mx = -1, r = -1; for (auto &x : Go) { if (mx < A[x]) mx = A[x], r = x; } Go.erase(r); Go.erase(ans(r)); } } else { int x; cin >> x; x--; Go.erase(x); while (PP[x] != -1) { Go.erase(PP[x]); x = ans(PP[x]); Go.erase(x); } for (auto x : M) { if (!Go.count(x.first)) continue; if (A[x.first] > A[x.second]) { ans(x.first); Go.erase(x.first); Go.erase(x.second); } else { ans(x.second); Go.erase(x.first); Go.erase(x.second); } } while (Go.size()) { int mx = -1, r = -1; for (auto &x : Go) { if (mx < A[x]) mx = A[x], r = x; } Go.erase(r); Go.erase(ans(r)); } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 7, MAXM = 1e5 + 5, MOD = 1e9 + 7, bit_one = (1 << MAXN) - 1; int n, ans; int w[MAXN]; int pre_process[MAXN][(1 << MAXN)][(1 << MAXN)]; int add(int a, int b) { int c = a + b; while (c >= MOD) c -= MOD; return c; } int mul(int a, int b) { return 1LL * a * b % MOD; } struct matrix { int data[(1 << MAXN)][(1 << MAXN)]; int n, m; matrix(int a = (1 << MAXN), int b = (1 << MAXN), bool c = 0) { n = a; m = b; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) data[i][j] = (i == j) * c; } void operator*=(matrix tmp) { matrix res(n, tmp.m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) for (int k = 0; k < tmp.m; k++) res.data[i][k] = add(res.data[i][k], mul(data[i][j], tmp.data[j][k])); (*this) = res; } void operator^=(int tmp) { matrix res(n, m, 1); for (; tmp; tmp /= 2) { if (tmp & 1) res *= (*this); (*this) *= (*this); } (*this) = res; } }; bool cheak(int a, int b, int c, int d) { for (int i = 0; i <= a; i++) if (((d >> i) & 1) && ((d >> (i + 1)) & 1) && ((b >> i) & 1) && ((c >> i) & 1)) return 0; return 1; } int main() { for (int i = 0; i < 7; i++) scanf( %d , &w[i]); for (int i = 0; i < 7; i++) for (int j = 0; j < (1 << (i + 1)); j++) for (int k = 0; k < (1 << (i + 1)); k++) for (int h = 0; h < (1 << i); h++) pre_process[i][j][k] += cheak(i, j, k, (1 << (i + 1)) | (h << 1 | 1)); matrix M[7]; for (int i = 0; i < 7; i++) M[i].n = M[i].m = (1 << (i + 1)); for (int i = 0; i < 7; i++) { for (int j = 0; j < (1 << (i + 1)); j++) for (int k = 0; k < (1 << (i + 1)); k++) M[i].data[j][k] = pre_process[i][j][k]; M[i] ^= w[i]; } matrix A[7]; for (int i = 0; i < 7; i++) { A[i].n = (1 << (i + 1)); A[i].m = 1; } A[0].data[1][0] = 1; M[0] *= A[0]; A[0] = M[0]; for (int i = 1; i < 7; i++) { for (int j = 0; j < (1 << i); j++) { int tmp = j << 1 | 1; A[i].data[tmp][0] = A[i - 1].data[j][0]; } M[i] *= A[i]; A[i] = M[i]; } ans = A[6].data[bit_one][0]; printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; char ss[1002][1002]; int ak = -1, p = 0; int main() { while (gets(ss[p])) { if ((int)strlen(ss[p]) > ak) ak = (int)strlen(ss[p]); p++; } for (int i = 0; i <= ak + 1; i++) printf( * ); printf( n ); bool k = false; for (int i = 0; i < p; i++) { int len = strlen(ss[i]); if ((ak - len) % 2 != 0) k = !k; printf( * ); for (int j = 0; j < (ak - len + (!k)) / 2; j++) printf( ); printf( %s , ss[i]); for (int j = 0; j < (ak - len + (k)) / 2; j++) printf( ); printf( * n ); } for (int i = 0; i <= ak + 1; i++) printf( * ); printf( n ); return 0; }
|
// Test bench for our 6 bit shift register.
module main;
reg clk, rst_n, in;
wire [5:0] q;
wire d;
strober st (clk, rst_n, d);
shift sh (clk, rst_n, d, q);
always #10 clk = ~clk;
task assert(input condition);
if(!condition)
$finish(2);
endtask // assert
initial begin
clk = 0;
rst_n = 0;
#5 rst_n = 1;
#5
$display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd0);
#10
$display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd1);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd2);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd4);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd8);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd16);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd32);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd1);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd2);
#20 $display("q = %d rst_n = %d, d = %d", q, rst_n, d);
assert(q == 6'd4);
$finish;
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long d[25]; int main() { long long t; cin >> t; while (t--) { long long n, s; cin >> n >> s; long long len = 0, sum = 0, num = n; fill(d, d + 25, 0); while (num > 0) { d[++len] = num % 10; sum += d[len]; num /= 10; } if (sum <= s) { cout << 0 << endl; continue; } long long cur = 0; for (int i = len; i >= 1; i--) { cur += d[i]; if (cur >= s) { d[i + 1]++; for (int j = i; j >= 1; j--) d[j] = 0; break; } } long long ans = 0; cur = 1; for (int i = 1; i <= len + 1; i++) { d[i + 1] += d[i] / 10; d[i] = d[i] % 10; ans += d[i] * cur; cur *= 10; } cout << ans - n << endl; } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: vga_font_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vga_font_rom (
address,
clock,
q);
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../font.rif"
`else
altsyncram_component.init_file = "../font.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../font.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../font.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_font_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[105]; int main() { int i, n, j = 0, k, l; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a + 1, a + n); while (a[0] <= a[n - 1]) { j++; a[n - 1]--; a[0]++; sort(a + 1, a + n); } cout << j << endl; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file vram.v when simulating
// the core, vram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module vram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [12 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } int n; int m; vector<pair<int, int> > w[5000]; pair<int, int> v[5000]; int p[5000], u[5000], pc[5000], px[5000], res[5000]; int go(int x, int p) { for (int i = 0; i < ((int)(w[x]).size()); i++) { int y = w[x][i].first; int z = w[x][i].second; if (y != p) { px[y] = x; pc[y] = z; go(y, x); } } return 0; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &v[i].first); v[i].second = i; } sort(v, v + n); for (int i = 1; i < n; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); a--; b--; w[a].push_back(make_pair(b, c)); w[b].push_back(make_pair(a, c)); } go(0, 0); for (int i = 0; i < n; i++) { p[i] = i; res[i] = -1; } int it = 0; while (true) { int ok = 1; for (int i = 0; i < n; i++) u[i] = 0; for (int i = 0; i < n; i++) { int j = v[i].second; if (p[j] > 0 && u[p[j]] < pc[p[j]]) { ok = 0; u[p[j]]++; p[j] = px[p[j]]; } else if (p[j] == 0 && res[j] == -1) res[j] = it; } if (ok) break; it++; } for (int i = 0; i < n; i++) printf( %d , res[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; set<pair<int, int> > s; vector<int> od; int p[512]; vector<int> v[512]; inline void dfs(int b, int pr = -1) { od.push_back(b); p[b] = pr; auto it = s.lower_bound(make_pair(b, -1)); while (it != s.end() && (*it).first == b) { if (it->second == pr) { it = next(it); continue; } dfs(it->second, b); v[b].push_back(it->second); v[it->second].push_back(b); it = next(it); } } bool us[512]; void init() { for (int i = 0; i <= n; i++) { v[i].clear(); us[i] = false; } } int sz[512]; inline pair<int, int> cent(int b, int ALL, int pr) { sz[b] = 1; pair<int, int> ret = make_pair(INT_MAX, -1); int mx = -1; for (int go : v[b]) { if (us[go]) continue; if (go == pr) continue; ret = min(ret, cent(go, ALL, b)); sz[b] += sz[go]; mx = max(mx, sz[go]); } mx = max(mx, ALL - sz[b]); ret = min(ret, make_pair(mx, b)); return ret; } inline void er(int a, int b) { s.erase(make_pair(a, b)); s.erase(make_pair(b, a)); } inline void ins(int a, int b) { s.insert(make_pair(a, b)); s.insert(make_pair(b, a)); } bool ok(vector<int> &vv, int num, int root, int root2) { cout << 1 << endl; cout << root << endl; cout << num + 1 << endl; for (int j = 0; j <= num; j++) { if (j) printf( ); printf( %d , vv[j]); } puts( ); cout << root2 << endl; fflush(stdout); int way; scanf( %d , &way); if (way == num + 1) { return true; } return false; } inline void df(int b, int add) { cent(b, 0, -1); b = cent(b, sz[b], -1).second; vector<int> z; for (int go : v[b]) { z.push_back(go); } us[b] = true; int mint = 0; int maxt = z.size(); if (z.size() && ok(z, 0, add, b) == false) { maxt = mint; } while (mint + 1 < maxt) { int mid = (mint + maxt) / 2; if (ok(z, mid, add, b)) { mint = mid; } else { maxt = mid; } } if (maxt == z.size()) { ins(b, add); return; } if (us[z[maxt]] == false) { df(z[maxt], add); return; } er(z[maxt], b); ins(z[maxt], add); ins(add, b); } int zz[512]; vector<int> o; bool cmp(int a, int b) { return zz[a] > zz[b]; } int main() { cin >> n; zz[1] = n; for (int i = 2; i <= n; i++) { cout << 1 << endl; cout << 1 << endl; cout << n - 1 << endl; for (int j = 2; j <= n; j++) { if (j > 1) printf( ); printf( %d , j); } puts( ); printf( %d n , i); fflush(stdout); int a; scanf( %d , &a); zz[i] = a; } for (int i = 2; i <= n; i++) o.push_back(i); sort(o.begin(), o.end(), cmp); for (int i : o) { od.clear(); init(); dfs(1); reverse(od.begin(), od.end()); df(1, i); } puts( ANSWER ); for (auto it : s) { if (it.first > it.second) continue; printf( %d %d n , it.first, it.second); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, h; long long r(long long l, long long s, long long e, long long d) { if (s + 1 == e) return 0; long long m = 1 + (s + e) >> 1; long long k = (n < m ? (d ? (1ll << (h - l)) : 1) : (d ? 1 : (1ll << (h - l)))); if (n < m) return r(l + 1, s, m, 1) + k; return r(l + 1, m, e, 0) + k; } int main() { cin >> h >> n; --n; cout << r(0, 0, 1ll << h, 0); }
|
#include <bits/stdc++.h> template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans % m; } using namespace std; bool B[100], G[100]; int main() { int n, m; cin >> n >> m; int b; cin >> b; for (int(i) = (0); (i) < (b); (i)++) { int first; cin >> first; B[first] = 1; } int g; cin >> g; for (int(i) = (0); (i) < (g); (i)++) { int first; cin >> first; G[first] = 1; } for (int(i) = (0); (i) < (10000000); (i)++) B[i % n] = G[i % m] = B[i % n] | G[i % m]; bool boys = 1, girls = 1; for (int(i) = (0); (i) < (n); (i)++) boys &= B[i]; for (int(i) = (0); (i) < (m); (i)++) girls &= G[i]; if (boys && girls) cout << Yes << n ; else cout << No << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_1_V
`define SKY130_FD_SC_LP__NAND2_1_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_1_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } const int N = 1010000; int nxt[N], f[N], ret[N], len[N]; int n, r, c; char s[N * 6]; int main() { scanf( %d%d%d , &n, &r, &c); ++c; int l = 0; for (int i = 1; i < n + 1; i++) { scanf( %s , s + l); int pl = strlen(s + l); len[i] = len[i - 1] + pl + 1; l += pl + 1; s[l - 1] = ; } int t = 0; for (int i = 1; i < n + 1; i++) { while (t <= n && len[t] - len[i - 1] <= c) t++; nxt[i] = t; } nxt[n + 1] = n + 1; for (int i = 1; i < n + 2; i++) ret[i] = i, f[i] = nxt[i]; for (int b = r; b; b >>= 1) { if (b & 1) for (int i = 1; i < n + 1; i++) ret[i] = f[ret[i]]; for (int i = 1; i < n + 1; i++) f[i] = f[f[i]]; } int rp = 1, rc = ret[1] - 1; for (int i = 2; i < n + 1; i++) if (ret[i] - i > rc) rc = ret[i] - i, rp = i; for (int i = 0; i < r; i++) { for (int j = len[rp - 1]; j < len[nxt[rp] - 1] - 1; j++) putchar(s[j]); rp = nxt[rp]; puts( ); } }
|
module test;
reg [0:0] io_in_valid;
reg [31:0] io_in_bits;
reg [0:0] io_out_ready;
reg [0:0] io_pcIn_valid;
reg [0:0] io_pcIn_bits_request;
reg [15:0] io_pcIn_bits_moduleId;
reg [7:0] io_pcIn_bits_portId;
reg [15:0] io_pcIn_bits_pcValue;
reg [3:0] io_pcIn_bits_pcType;
wire [0:0] io_in_ready;
wire [0:0] io_out_valid;
wire [31:0] io_out_bits;
wire [0:0] io_pcOut_valid;
wire [0:0] io_pcOut_bits_request;
wire [15:0] io_pcOut_bits_moduleId;
wire [7:0] io_pcOut_bits_portId;
wire [15:0] io_pcOut_bits_pcValue;
wire [3:0] io_pcOut_bits_pcType;
reg clk = 0;
reg reset = 1;
initial begin
reset = 1;
#250 reset = 0;
end
always #100 clk = ~clk;
Offloaded
Offloaded(
.clk(clk),
.reset(reset),
.io_in_valid(io_in_valid),
.io_in_bits(io_in_bits),
.io_out_ready(io_out_ready),
.io_pcIn_valid(io_pcIn_valid),
.io_pcIn_bits_request(io_pcIn_bits_request),
.io_pcIn_bits_moduleId(io_pcIn_bits_moduleId),
.io_pcIn_bits_portId(io_pcIn_bits_portId),
.io_pcIn_bits_pcValue(io_pcIn_bits_pcValue),
.io_pcIn_bits_pcType(io_pcIn_bits_pcType),
.io_in_ready(io_in_ready),
.io_out_valid(io_out_valid),
.io_out_bits(io_out_bits),
.io_pcOut_valid(io_pcOut_valid),
.io_pcOut_bits_request(io_pcOut_bits_request),
.io_pcOut_bits_moduleId(io_pcOut_bits_moduleId),
.io_pcOut_bits_portId(io_pcOut_bits_portId),
.io_pcOut_bits_pcValue(io_pcOut_bits_pcValue),
.io_pcOut_bits_pcType(io_pcOut_bits_pcType)
);
integer count;
always @(negedge clk) begin;
#50;
if (!reset) count = $fscanf('h80000000, "%x %x %x %x %x %x %x %x %x", io_in_valid, io_in_bits, io_out_ready, io_pcIn_valid, io_pcIn_bits_request, io_pcIn_bits_moduleId, io_pcIn_bits_portId, io_pcIn_bits_pcValue, io_pcIn_bits_pcType);
if (count == -1) $finish(1);
end
always @(posedge clk) begin
if (!reset) $display("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", io_in_ready, io_out_valid, io_out_bits, io_pcOut_valid, io_pcOut_bits_request, io_pcOut_bits_moduleId, io_pcOut_bits_portId, io_pcOut_bits_pcValue, io_pcOut_bits_pcType);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> g[100001]; bool is_centroid[100001]; int centroid_parent[100001]; int mn[100001]; int sz[100001]; int level[100001]; int centroid_root; map<pair<int, int>, int> dist; void dfs(int nd, int p, int c) { sz[nd] = 1; if (p == c) { level[nd] = 0; } else { level[nd] = level[p] + 1; } dist[make_pair(nd, c)] = level[nd] + 1; for (int i = 0; i < g[nd].size(); i++) { int z = g[nd][i]; if (z != p && !is_centroid[z]) { dfs(z, nd, c); sz[nd] += sz[z]; } } } int pd; int find_centroid(int u, int ts) { for (int i = 0; i < g[u].size(); i++) { int z = g[u][i]; if (is_centroid[z] || sz[z] > sz[u]) continue; if (sz[z] > ts / 2) return find_centroid(z, ts); } return u; } int get_centroid(int nd, int p) { dfs(nd, p, p); int u = find_centroid(nd, sz[nd]); is_centroid[u] = true; centroid_parent[u] = p; for (int i = 0; i < g[u].size(); i++) { int z = g[u][i]; if (!is_centroid[z]) { get_centroid(z, u); } } return u; } void centroid_decompose() { fill(is_centroid, is_centroid + 100001, false); centroid_root = get_centroid(1, -1); } void debug() { for (int i = 1; i <= n; i++) { cout << i << << centroid_parent[i] << << mn[i] << endl; } } void redify(int u) { int x = u; while (u != -1) { mn[u] = min(dist[make_pair(x, u)], mn[u]); u = centroid_parent[u]; } } int solve(int u) { int res = INT_MAX / 3; int x = u; while (u != -1) { res = min(res, dist[make_pair(x, u)] + mn[u]); u = centroid_parent[u]; } return res; } int main() { int u, v; scanf( %d %d , &n, &m); for (int i = 0; i < n - 1; i++) { scanf( %d %d , &u, &v); g[u].push_back(v); g[v].push_back(u); } fill(mn, mn + 100001, INT_MAX / 3); centroid_decompose(); redify(1); while (m--) { scanf( %d %d , &u, &v); if (u == 1) { redify(v); } else { printf( %d n , solve(v)); } } return 0; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r = afi_rst_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_p0_fr_cycle_shifter uaddr_cmd_shift_rst_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_rst_n_r),
.dataout (phy_ddio_reset_n)
);
defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "true";
endmodule
|
// chris_pipelined.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_pipelined (
input wire [7:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire ins_irq0_irq, // ins_irq0.irq
output wire [31:0] avm_m0_address, // avm_m0.address
output wire avm_m0_read, // .read
input wire avm_m0_waitrequest, // .waitrequest
input wire [31:0] avm_m0_readdata, // .readdata
input wire avm_m0_readdatavalid, // .readdatavalid
output wire avm_m0_write, // .write
output wire [31:0] avm_m0_writedata, // .writedata
output wire [7:0] avm_m0_burstcount // .burstcount
);
// TODO: Auto-generated HDL template
/* system template generated
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
assign avs_s0_waitrequest = 1'b0;
assign ins_irq0_irq = 1'b0;
assign avm_m0_address = 32'b00000000000000000000000000000000;
assign avm_m0_read = 1'b0;
assign avm_m0_write = 1'b0;
assign avm_m0_writedata = 32'b00000000000000000000000000000000;
assign avm_m0_burstcount = 8'b00000000;
*/
/*
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
assign avs_s0_waitrequest = 1'b0;
assign LEDR = 1'b0;
*/
/*
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
*/
reg reg_status_read;
reg reg_status_write;
//data out
reg [31:0] reg_data_out;
assign avs_s0_readdata = reg_data_out;
//logic connect;
assign avs_s0_waitrequest = reg_status_read || reg_status_write;
// begin register map;
wire [8:0] s_kernel_parameter;
wire s_input_image_addr; //input image address
wire s_output_image_addr; // output image address
wire s_module_control; // system control address
wire s_module_status; // system status address
reg [31:0] reg_kernel[8:0];
reg [31:0] reg_source_addr;
reg [31:0] reg_destination_addr;
reg [31:0] reg_control;
reg [31:0] reg_status;
assign s_kernel_parameter[0] = (avs_s0_address[3:0] == 4'b0000) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[1] = (avs_s0_address[3:0] == 4'b0001) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[2] = (avs_s0_address[3:0] == 4'b0010) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[3] = (avs_s0_address[3:0] == 4'b0011) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[4] = (avs_s0_address[3:0] == 4'b0100) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[5] = (avs_s0_address[3:0] == 4'b0101) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[6] = (avs_s0_address[3:0] == 4'b0110) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[7] = (avs_s0_address[3:0] == 4'b0111) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[8] = (avs_s0_address[3:0] == 4'b1000) & (avs_s0_write | avs_s0_read);
assign s_input_image_addr = (avs_s0_address[3:0] == 4'b1001) & (avs_s0_write | avs_s0_read);
assign s_output_image_addr= (avs_s0_address[3:0] == 4'b1010) & (avs_s0_write | avs_s0_read);
assign s_module_control = (avs_s0_address[3:0] == 4'b1011) & (avs_s0_write | avs_s0_read);
assign s_module_status = (avs_s0_address[3:0] == 4'b1100) & (avs_s0_write | avs_s0_read);
// end register map
//Get data form master
always @(posedge clock_clk)
if (reset_reset) begin
reg_kernel[0] <= 32'h000;
reg_kernel[1] <= 32'h000;
reg_kernel[2] <= 32'h000;
reg_kernel[3] <= 32'h000;
reg_kernel[4] <= 32'h000;
reg_kernel[5] <= 32'h000;
reg_kernel[6] <= 32'h000;
reg_kernel[7] <= 32'h000;
reg_kernel[8] <= 32'h000;
reg_source_addr <= 32'h0000;
reg_destination_addr <= 32'h0000;
reg_control <= 32'h0000;
reg_status <= 32'h0000;
reg_status_write <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
reg_status_write <= 1'b1;
if (s_kernel_parameter[0]) begin
reg_kernel[0] <= avs_s0_writedata;
end
if (s_kernel_parameter[1]) begin
reg_kernel[1] <= avs_s0_writedata;
end
if (s_kernel_parameter[2]) begin
reg_kernel[2] <= avs_s0_writedata;
end
if (s_kernel_parameter[3]) begin
reg_kernel[3] <= avs_s0_writedata;
end
if (s_kernel_parameter[4]) begin
reg_kernel[4] <= avs_s0_writedata;
end
if (s_kernel_parameter[5]) begin
reg_kernel[5] <= avs_s0_writedata;
end
if (s_kernel_parameter[6]) begin
reg_kernel[6] <= avs_s0_writedata;
end
if (s_kernel_parameter[7]) begin
reg_kernel[7] <= avs_s0_writedata;
end
if (s_kernel_parameter[8]) begin
reg_kernel[8] <= avs_s0_writedata;
end
if (s_input_image_addr) begin
reg_source_addr <= avs_s0_writedata;
end
if (s_output_image_addr) begin
reg_destination_addr <= avs_s0_writedata;
end
if (s_module_control) begin
reg_control <= avs_s0_writedata;
end
if (s_module_status) begin
reg_status <= avs_s0_writedata;
end
end
//return data to master
always @(posedge clock_clk) begin
if (reset_reset) begin
reg_data_out <= 32'h0000;
reg_status_read <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
reg_status_read <= 1'b1;
if (s_kernel_parameter[0]) begin
reg_data_out <= reg_kernel[0];
end
if (s_kernel_parameter[1]) begin
reg_data_out <= reg_kernel[1];
end
if (s_kernel_parameter[2]) begin
reg_data_out <= reg_kernel[2];
end
if (s_kernel_parameter[3]) begin
reg_data_out <= reg_kernel[3];
end
if (s_kernel_parameter[4]) begin
reg_data_out <= reg_kernel[4];
end
if (s_kernel_parameter[5]) begin
reg_data_out <= reg_kernel[5];
end
if (s_kernel_parameter[6]) begin
reg_data_out <= reg_kernel[6];
end
if (s_kernel_parameter[7]) begin
reg_data_out <= reg_kernel[7];
end
if (s_kernel_parameter[8]) begin
reg_data_out <= reg_kernel[8];
end
if (s_input_image_addr) begin
reg_data_out <= reg_source_addr;
end
if (s_output_image_addr) begin
reg_data_out <= reg_destination_addr;
end
if (s_module_control) begin
reg_data_out <= reg_control;
end
if (s_module_status) begin
reg_data_out <= reg_status;
end
end
end
// rest the master;
always @(posedge clock_clk) begin
if (reset_reset) begin
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Transparent Data Latch with Asynchronous Clear and Gate Enable
// /___/ /\ Filename : LDCE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_G_INVERTED = 1'b0
)(
output Q,
input CLR,
input D,
input G,
input GE
);
wire [0:0] IS_CLR_INVERTED_BIN;
wire [0:0] IS_G_INVERTED_BIN;
reg Q_out = INIT;
wire CLR_in;
wire D_in;
wire GE_in;
wire G_in;
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED;
assign IS_G_INVERTED_BIN = IS_G_INVERTED;
`ifdef XIL_TIMING
wire CLR_dly;
wire D_dly;
wire GE_dly;
wire G_dly;
assign CLR_in = (CLR !== 1'bz) && (CLR_dly ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D_dly;
assign G_in = G_dly ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE_dly; // rv 1
`else
assign CLR_in = (CLR !== 1'bz) && (CLR ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D;
assign G_in = G ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE; // rv 1
`endif
assign Q = Q_out;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire o_out;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_n, in_clk_enable_p;
wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p;
wire rst_clk_enable, rst_clk_enable1;
wire tl_enable, tl_enable_n, tl_enable_p;
wire clk_en_n, clk_en_p;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nrst, CLR_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nrst, GE_in);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, GE_in);
and (tl_enable, ngsr, nrst);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN;
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN;
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN;
assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN;
assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN;
assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or CLR_in) begin
if (GSR) begin
if (INIT) begin
rst_int = 1'b0;
set_int = 1'b1;
end
else begin
rst_int = 1'b1;
set_int = 1'b0;
end
end
else begin
rst_int = CLR_in;
set_int = 1'b0;
end
end
latchsre_ldce (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1);
always @(o_out)
Q_out = o_out;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(CLR => Q) = (0:0:0, 0:0:0);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
$period (negedge G, 0:0:0, notifier);
$period (posedge G, 0:0:0, notifier);
$recrem (negedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (negedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly);
$recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly);
$recrem (posedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (posedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$setuphold (negedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (negedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (posedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$setuphold (posedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$width (negedge CLR, 0:0:0, 0, notifier);
$width (negedge G, 0:0:0, 0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldce (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
|
#include <bits/stdc++.h> using namespace std; int dx[4] = {-1, 1, 0, 0}; int dy[4] = {0, 0, -1, 1}; const int inf = 0x7f7f7f7f; const int mod = 1000000007; const double eps = 1e-8; int n, m; set<int> v; vector<pair<int, int> > ans; vector<int> vc[100007]; bool isok(int u, int v) { for (size_t i = 0; i < vc[u].size(); ++i) { if (vc[u][i] == v) return false; } return true; } bool dfs(int u) { if ((int)ans.size() == min(n - 1, m)) return true; v.erase(u); for (set<int>::iterator it = v.begin(); it != v.end(); ++it) { if (!isok(u, *it)) continue; ans.push_back(make_pair(u, *it)); if (dfs(*it)) return true; else { ans.pop_back(); it = v.find(*it); } } v.insert(u); return false; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i <= n; ++i) vc[i].clear(); int x, y; for (int i = 0; i < m; ++i) { scanf( %d%d , &x, &y); vc[x].push_back(y); vc[y].push_back(x); } for (int i = 1; i <= n; ++i) v.insert(i); ans.clear(); for (int i = 1; i <= n; ++i) { if (dfs(i)) { if (m == n) ans.push_back(make_pair(ans[0].first, ans.back().second)); for (int i = 0; i < m; ++i) printf( %d %d n , ans[i].first, ans[i].second); return 0; } } printf( -1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v; int n, m, vis[100005], in[100005], d[100005]; vector<int> e[100005]; int dfs(int i) { vis[i] = 1; int ans = 0; for (auto first : e[i]) { if (vis[first]) { ans = max(ans, d[first]); continue; } ans = max(ans, dfs(first)); } d[i] = ans + 1; return ans + 1; } bool check(int first) { int j; for (int i = 0; i < n; i++) { e[i].clear(); vis[i] = 0; in[i] = 0; d[i] = 0; } for (int i = 0; i < first; i++) { e[v[i].first].push_back(v[i].second); in[v[i].second]++; } int f; for (int i = 0; i < n; i++) if (in[i] == 0) { j = i; f = dfs(i); break; } return f == n; } void solve() { int first, second; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> first >> second; first--; second--; v.push_back({first, second}); } int l = 1, r = m, mid; while (l < r) { mid = l + (r - l) / 2; if (check(mid)) r = mid; else l = mid + 1; } if (check(l)) cout << l << n ; else cout << -1; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
// Bidirectional registers
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule // bidir_reg
|
#include <bits/stdc++.h> struct itv { int s1; int e1; int s2; int e2; int gr; void up() { gr = (e2 - s2) + 1; if (e1) { gr += (e1 - s1) + 1; }; }; }; std::vector<std::pair<int, int> > aus; void merge(int s1, int s2, int sz) { for (int i = 0; i < sz; i++) { aus.push_back({s1 + i, s2 + i}); }; }; itv tt[1000]; int main(void) { int n; scanf( %d , &n); int akt = 1; for (int i = 1; i <= 20; i++) { int sz = (1 << i); if (sz > n) break; for (int j = 1; j <= n; j += sz) { int s1 = j; int s2 = j + (sz / 2); if (s1 + sz > n + 1) break; merge(s1, s2, sz / 2); }; }; akt = n; std::vector<int> pw; for (int i = 0; i <= 20; i++) { if (n & (1 << i)) { pw.push_back(i); tt[i].s2 = (akt - (1 << i)) + 1; tt[i].e2 = akt; tt[i].s1 = 0; tt[i].e1 = 0; tt[i].up(); akt -= (1 << i); }; }; if (pw.size() > 2) { int ak = 1; for (int i = 0; i < pw.size() - 2; i++) { int ap = pw[i]; int np = pw[i + 1]; int ss = tt[ap].e2 - tt[ap].s2 + 1; if (!i) { merge(tt[ap].s2, ak, ss); tt[ap].s1 = ak; ak += (ss); tt[ap].e1 = ak - 1; }; tt[ap].up(); while (tt[ap].gr < tt[np].gr) { merge(tt[ap].s1, ak, tt[ap].e1 - tt[ap].s1 + 1); ak += (tt[ap].e1 - tt[ap].s1 + 1); merge(tt[ap].s2, ak, ss); ak += (ss); tt[ap].e1 = ak - 1; tt[ap].up(); }; merge(tt[ap].s2, tt[np].s2, ss); merge(tt[ap].s1, tt[np].s2 + ss, tt[ap].e1 - tt[ap].s1 + 1); tt[np].e2 = tt[ap].e2; tt[np].s1 = tt[ap].s1; tt[np].e1 = tt[ap].e1; tt[np].up(); }; }; printf( %d n , aus.size()); for (auto i : aus) { printf( %d %d n , i.first, i.second); }; return 0; };
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// Generic 32-bit Xilinx Spartan-6 (true) dual-port BRAM module
`timescale 1ns / 1ps
`default_nettype none
`include "mm_defines.vh"
module bram #(
parameter size = 16384, // bytes, valid range: 2048, 4096, 8192, 16384, 32768, 65536
parameter name = "irom" // only for BMM generation
) (
input wire ClockA, ClockB,
input wire ResetA, ResetB,
input wire [31:0] AddressA, AddressB,
input wire [31:0] DataInA, DataInB,
output wire [31:0] DataOutA, DataOutB,
input wire ClockEnA, ClockEnB,
input wire WriteA, WriteB
);
localparam N = size * 8 /* bits/bytes */ / 16384 /* bits/BRAM */;
localparam words = size / 4 /* 4 byte/word */;
localparam Log2Words = log2(words);
localparam bitwidth = 32 /* 32-bit data width */ / N; // par BRAM
localparam Log2bitwidth = log2(bitwidth);
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin: gen_bram
RAMB16BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
.DATA_WIDTH_A(9 * (bitwidth / 8) + (bitwidth < 8) * bitwidth),
.DATA_WIDTH_B(9 * (bitwidth / 8) + (bitwidth < 8) * bitwidth),
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
// INIT_A/INIT_B: Initial values on output port
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
// INIT_FILE: Optional file used to specify initial RAM contents
.INIT_FILE("NONE"),
// RSTTYPE: "SYNC" or "ASYNC"
.RSTTYPE("SYNC"),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
.RST_PRIORITY_A("SR"),
.RST_PRIORITY_B("SR"),
.SIM_DEVICE("SPARTAN6")
) bram (
// Port A Data: 32-bit (each) output: Port A data
.DOA(DataOutA[31-i*bitwidth:31-(i+1)*bitwidth+1]), // 32-bit output: A port data output
.DOPA(), // 4-bit output: A port parity output
// Port B Data: 32-bit (each) output: Port B data
.DOB(DataOutB[31-i*bitwidth:31-(i+1)*bitwidth+1]), // 32-bit output: B port data output
.DOPB(), // 4-bit output: B port parity output
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
.ADDRA({AddressA[Log2Words-1:0], {Log2bitwidth{1'b0}}}), // 14-bit input: A port address input
.CLKA(ClockA), // 1-bit input: A port clock input
.ENA(ClockEnA), // 1-bit input: A port enable input
.REGCEA(1'b0), // 1-bit input: A port register clock enable input
.RSTA(ResetA), // 1-bit input: A port register set/reset input
.WEA({bitwidth{WriteA}}), // 4-bit input: Port A byte-wide write enable input
// Port A Data: 32-bit (each) input: Port A data
.DIA(DataInA[31-i*bitwidth:31-(i+1)*bitwidth+1]), // 32-bit input: A port data input
.DIPA(4'hf), // 4-bit input: A port parity input
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
.ADDRB({AddressB[Log2Words-1:0], {Log2bitwidth{1'b0}}}), // 14-bit input: B port address input
.CLKB(ClockB), // 1-bit input: B port clock input
.ENB(ClockEnB), // 1-bit input: B port enable input
.REGCEB(1'b0), // 1-bit input: B port register clock enable input
.RSTB(ResetB), // 1-bit input: B port register set/reset input
.WEB({bitwidth{WriteB}}), // 4-bit input: Port B byte-wide write enable input
// Port B Data: 32-bit (each) input: Port B data
.DIB(DataInB[31-i*bitwidth:31-(i+1)*bitwidth+1]), // 32-bit input: B port data input
.DIPB(4'hf) // 4-bit input: B port parity input
);
end
endgenerate
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Img_RAM.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Img_RAM (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q);
input [0:0] data;
input wren;
input [18:0] wraddress;
input [15:0] rdaddress;
input wrclock;
input rdclock;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 1,
altsyncram_component.widthad_a = 19,
altsyncram_component.numwords_a = 307200,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 16,
altsyncram_component.numwords_b = 38400,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.power_up_uninitialized = "FALSE",
`ifdef NO_PLI
altsyncram_component.init_file = "Img_DATA.rif"
`else
altsyncram_component.init_file = "Img_DATA.hex"
`endif
,
altsyncram_component.init_file_layout = "PORT_B";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "307200"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "D:/UP4/HW/UP4_USB_API/VGA_Controller/Img_DATA.hex"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "19"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "307200"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "38400"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: INIT_FILE STRING "D:/UP4/HW/UP4_USB_API/VGA_Controller/Img_DATA.hex"
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL data[0..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wraddress 0 0 19 0 INPUT NODEFVAL wraddress[18..0]
// Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL rdaddress[15..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 19 0 wraddress 0 0 19 0
// Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Img_RAM_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb4to1.v"
module top();
// Inputs are registered
reg D;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 S = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 S = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 S = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 S = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hdll__muxb4to1 dut (.D(D), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: Reset_Delay
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
input iCLK;
input iRST;
output reg oRST_0;
output reg oRST_1;
output reg oRST_2;
reg [31:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Cont <= 0;
oRST_0 <= 0;
oRST_1 <= 0;
oRST_2 <= 0;
end
else
begin
if(Cont!=32'h114FFFF)
Cont <= Cont+1;
if(Cont>=32'h1FFFFF)
oRST_0 <= 1;
if(Cont>=32'h2FFFFF)
oRST_1 <= 1;
if(Cont>=32'h114FFFF)
oRST_2 <= 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> m; int main() { int n, k; cin >> n >> k; int e = 0; for (int i = 1; i < k; i++) { string t = ; t += char( A + e / 26); t += char( a + e % 26); e++; m.push_back(t); } for (int i = k; i <= n; i++) { string s; cin >> s; if (s == YES ) { string t = ; t += char( A + e / 26); t += char( a + e % 26); e++; m.push_back(t); } else { m.push_back(m[i - k]); } } for (string &s : m) std::cout << s << ; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "setseed.vh"
module top(input clk, din, stb, output dout);
reg [41:0] din_bits;
wire [78:0] dout_bits;
reg [41:0] din_shr;
reg [78:0] dout_shr;
always @(posedge clk) begin
if (stb) begin
din_bits <= din_shr;
dout_shr <= dout_bits;
end else begin
din_shr <= {din_shr, din};
dout_shr <= {dout_shr, din_shr[41]};
end
end
assign dout = dout_shr[78];
roi roi (
.clk(clk),
.din_bits(din_bits),
.dout_bits(dout_bits)
);
endmodule
module roi(input clk, input [41:0] din_bits, output [78:0] dout_bits);
picorv32 picorv32 (
.clk(clk),
.resetn(din_bits[0]),
.mem_valid(dout_bits[0]),
.mem_instr(dout_bits[1]),
.mem_ready(din_bits[1]),
.mem_addr(dout_bits[33:2]),
.mem_wdata(dout_bits[66:34]),
.mem_wstrb(dout_bits[70:67]),
.mem_rdata(din_bits[33:2])
);
randluts randluts (
.din(din_bits[41:34]),
.dout(dout_bits[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N =
`SEED % 3 == 2 ? 250 :
`SEED % 3 == 1 ? 100 : 10;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
module ALUControl(ALUOp, Funct, ALUCtl, Sign);
input [3:0] ALUOp;
input [5:0] Funct;
output reg [4:0] ALUCtl;
output Sign;
parameter aluAND = 5'b00000;
parameter aluOR = 5'b00001;
parameter aluADD = 5'b00010;
parameter aluSUB = 5'b00110;
parameter aluSLT = 5'b00111;
parameter aluNOR = 5'b01100;
parameter aluXOR = 5'b01101;
parameter aluSLL = 5'b10000;
parameter aluSRL = 5'b11000;
parameter aluSRA = 5'b11001;
assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
reg [4:0] aluFunct;
always @(*)
case (Funct)
6'b00_0000: aluFunct <= aluSLL;
6'b00_0010: aluFunct <= aluSRL;
6'b00_0011: aluFunct <= aluSRA;
6'b10_0000: aluFunct <= aluADD;
6'b10_0001: aluFunct <= aluADD;
6'b10_0010: aluFunct <= aluSUB;
6'b10_0011: aluFunct <= aluSUB;
6'b10_0100: aluFunct <= aluAND;
6'b10_0101: aluFunct <= aluOR;
6'b10_0110: aluFunct <= aluXOR;
6'b10_0111: aluFunct <= aluNOR;
6'b10_1010: aluFunct <= aluSLT;
6'b10_1011: aluFunct <= aluSLT;
default: aluFunct <= aluADD;
endcase
always @(*)
case (ALUOp[2:0])
3'b000: ALUCtl <= aluADD;
3'b001: ALUCtl <= aluSUB;
3'b100: ALUCtl <= aluAND;
3'b101: ALUCtl <= aluSLT;
3'b010: ALUCtl <= aluFunct;
default: ALUCtl <= aluADD;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_BEHAVIORAL_PP_V
|
`timescale 1ns / 100ps
// File name : p2hw3latches2015fall.v
// ECE333 Homework #3 Problem 2
//check if this circuit has latches. Show where latches are on its schematic,
//and propose fixes to remove all latches.
module p2hw3latches2015fall(X, Z, RESET, CLOCK, CurrentState);
input X, RESET, CLOCK;
output reg Z;
// State variables
output reg [1:0] CurrentState;
reg [1:0] NextState;
// State codes
parameter State0 = 0, State1 = 1, State2 = 2, State3 = 3;
// Output logic
always @ (CurrentState)
if(CurrentState==State0) Z<=1;
else if (CurrentState==State3) Z<=0;
else Z<=0;
// State registers
always @ (posedge CLOCK)
if (RESET==1) CurrentState <= State0; else CurrentState <= NextState;
//next state logic
always@(CurrentState or X)
case (CurrentState)
State0: if (X==0) NextState <= State1; else NextState <= State0;
State1: if (X==0) NextState <= State1; else NextState <= State0;
State3: if (X==0) NextState <= State1; else NextState <= State2;
State2: NextState <= State2;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using uint = unsigned int; using rl = double; const int MAXN = 5 * 100009; const int modd = 998244353; int n; struct Vertex { vector<int> to; int pm, answ, thisansw; } v[MAXN]; int ndiv2; int mult(int a, int b) { ll res = a * (ll)b; if (res >= modd) res %= modd; return res; } int add(int a, int b) { a += b; if (a >= modd) a -= modd; return a; } int neg(int a) { a = -a; if (a < 0) a += modd; return a; } int oneMinus(int a) { return add(1, neg(a)); } int poww(int val, int pow = modd - 2) { int res = 1; while (pow) { if (pow & 1) res = mult(res, val); val = mult(val, val); pow /= 2; } return res; } int dfs(int it, int p = 0) { v[it].pm = 1; v[it].answ = 0; v[it].thisansw = 0; for (auto to : v[it].to) { if (to == p) continue; v[it].answ = add(v[it].answ, dfs(to, it)); v[it].thisansw = mult(v[it].thisansw, add(oneMinus(v[to].pm), mult(ndiv2, v[to].pm))); v[it].thisansw = add(v[it].thisansw, mult(ndiv2, v[to].pm)); v[it].pm = mult(v[it].pm, add(oneMinus(v[to].pm), mult(ndiv2, v[to].pm))); } return add(v[it].answ, v[it].thisansw); } int main() { ndiv2 = poww(2); assert(mult(ndiv2, 2) == 1); scanf( %d , &n); for (int i = 1; i < n; i++) { int a, b; scanf( %d %d , &a, &b); v[a].to.push_back(b); v[b].to.push_back(a); } int answ = dfs(1); printf( %d n , mult(poww(2, n), answ)); }
|
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7, INF = 0x3f3f3f3f; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long qpow(long long a, long long n) { long long r = 1 % P; for (a %= P; n; a = a * a % P, n >>= 1) if (n & 1) r = r * a % P; return r; } long long inv(long long first) { return first <= 1 ? 1 : inv(P % first) * (P - P / first) % P; } inline int rd() { int first = 0; char p = getchar(); while (p < 0 || p > 9 ) p = getchar(); while (p >= 0 && p <= 9 ) first = first * 10 + p - 0 , p = getchar(); return first; } const int N = 1e6 + 50; int n, m, w[N], dep[N]; vector<pair<int, int>> g[N]; vector<pair<int, long long>> route[N]; void dfs(int first, int d) { dep[first] = d; for (auto &e : g[first]) dfs(e.first, d + e.second); } int p(int f, int first) { if (first == f * 2) return first + 1; return first - 1; } long long qry(int a, int h, int c) { if (a > n || c > h) return 0; auto p = --upper_bound(route[a].begin(), route[a].end(), pair<int, long long>(h - c, 1e18)); long long cnt = p - route[a].begin() + 1; return cnt * (h - c) - p->second; } int main() { scanf( %d%d , &n, &m); for (int i = 2; i <= n; ++i) { int u = i / 2, v = i; scanf( %d , w + i); g[u].push_back({v, w[i]}); } dfs(1, 0); for (int i = 1; i <= n; ++i) { int j = i; route[i].push_back({0, 0ll}); while (j != 1) { j /= 2; route[j].push_back({dep[i] - dep[j], 0ll}); } } for (int i = 1; i <= n; ++i) { sort(route[i].begin(), route[i].end()); int sz = route[i].size(); for (int j = 1; j <= sz - 1; ++j) route[i][j].second = route[i][j].first + route[i][j - 1].second; } while (m--) { int a, h; scanf( %d%d , &a, &h); long long ans = qry(a, h, 0); int c = 0; while (1) { c += w[a]; if (a == 1 || c > h) break; int t = p(a / 2, a); ans += qry(t, h, c + w[t]); ans += h - c; a /= 2; } printf( %lld n , ans); } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; const int p = 1e9 + 7; struct edge { int l, r, uk; }; edge a[MAXN]; int dp[4 * MAXN]; int b[MAXN]; int n, m; void update(int k) { dp[k] = (dp[k * 2] + dp[k * 2 + 1]) % p; if (k > 1) update(k / 2); } long long getsum(int v, int ll, int rr, int l, int r) { if (ll > r || rr < l) return 0; if (ll >= l && rr <= r) return dp[v]; return (getsum(v * 2, ll, (ll + rr) / 2, l, r) + getsum(v * 2 + 1, (ll + rr) / 2 + 1, rr, l, r)) % p; } bool operator<(edge a, edge b) { return a.r < b.r; } int binr(int l, int r, int q) { while (l < r - 1) { if (b[(l + r) / 2] < q) l = (l + r) / 2; else r = (l + r) / 2; } return r; } int main() { int i, size = 1, uk, l; cin >> n >> m; while (size < m) { size *= 2; } for (i = 0; i < m; i++) { cin >> a[i].l >> a[i].r; } sort(a, a + m); b[0] = 0; b[1] = a[0].r; uk = 2; for (i = 1; i < m; i++) { if (a[i - 1].r != a[i].r) { b[uk] = a[i].r; uk++; } a[i].uk = uk; } dp[size] = 1; update(size / 2); int uk1 = 1; for (i = 0; i < m; i++) { l = binr(-1, uk - 1, a[i].l); l++; if (i != 0 && a[i - 1].r != a[i].r) uk1++; dp[size + uk1] = (dp[size + uk1] + getsum(1, 1, size, l, uk1)) % p; update((size + uk1) / 2); } uk--; if (a[m - 1].r != n) cout << 0; else cout << dp[size + uk1]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e9; long long max(long long a, long long b, long long c) { return max(a, max(b, c)); } long long n; long long house[200011]; long long mn[200011][2][2]; long long mx[200011][2][2]; long long f(long long i, long long j, long long k) { if (i == -1) return 0; if (mn[i][j][k] != -1) return mn[i][j][k]; long long res = INF; if (house[i] == 0) res = f(i - 1, 0, j); else if (j + k == 0) res = 1 + f(i - 1, 1, 0); else if (j == 1) res = f(i - 1, 0, 1); else res = f(i - 1, 0, 0); return mn[i][j][k] = res; } long long g(long long i, long long j, long long k) { if (i == -1) return 0; if (mx[i][j][k] != -1) return mx[i][j][k]; long long res = 0; if (house[i] == 0) res = g(i - 1, 0, j); else if (j + k == 2) res = 1 + g(i - 1, 1, 1); else if (j + k == 0) { if (house[i] == 1) res = 1 + max(g(i - 1, 1, 0), g(i - 1, 0, 1), g(i - 1, 0, 0)); else if (house[i] == 2) res = 2 + max(g(i - 1, 1, 1), g(i - 1, 1, 0), g(i - 1, 0, 1)); else res = 3 + g(i - 1, 1, 1); } else if (j == 1) { if (house[i] == 1) res = 1 + max(g(i - 1, 1, 1), g(i - 1, 0, 1)); else res = 2 + g(i - 1, 1, 1); } else { if (house[i] == 1) res = 1 + max(g(i - 1, 0, 1), g(i - 1, 1, 0)); else res = 2 + g(i - 1, 1, 1); } return mx[i][j][k] = res; } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); memset(mn, -1, sizeof mn); memset(mx, -1, sizeof mx); cin >> n; for (long long i = 0; i < n; i++) { long long x; cin >> x; house[--x]++; } cout << f(n - 1, 0, 0) << << g(n - 1, 0, 0); return 0; }
|
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; using std::pair; using std::string; using std::swap; using std::vector; void doit(int& xk, int& yk, int w, int h, int x, int y, int z) { for (int i = 0; i < x; ++i) { swap(xk, yk); swap(w, h); xk = w - xk + 1; } if (y) { xk = w - xk + 1; } for (int i = 0; i < z; ++i) { swap(xk, yk); swap(w, h); yk = h - yk + 1; } } int main() { int n, m, x, y, z, p; scanf( %d %d %d %d %d %d , &n, &m, &x, &y, &z, &p); x %= 4; y = y & 1; z %= 4; while (p--) { int xk, yk; scanf( n%d %d , &yk, &xk); doit(xk, yk, m, n, x, y, z); printf( %d %d n , yk, xk); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_BLACKBOX_V
|
// $Id: c_incr.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic modulo incrementer (i.e., incrementer with wraparound)
module c_incr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// sum output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire carry;
assign carry = &data_in[(width-cwidth):width-1];
wire wrap;
assign wrap = (data_in[(width-cwidth):width-1] ==
max_value[(width-cwidth):width-1]);
generate
if((1 << cwidth) == num_values)
begin
// if the range is a power of two, we can take advantage of natural
// wraparound for the LSBs
assign data_out[(width-cwidth):width-1]
= data_in[(width-cwidth):width-1] + 1'b1;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ?
min_value[(width-cwidth):width-1] :
(data_in[(width-cwidth):width-1] + 1'b1);
end
if(width > cwidth)
begin
if(min_value[0:(width-cwidth)-1] == max_value[0:(width-cwidth)-1])
begin
// if the MSBs are identical for the first and last value, we
// never need to change them
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1];
end
else
begin
// if the first and last value have differing MSBs, we need to
// adjust them whenever either the LSBs overflow or wraparound
// occurs
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1] + carry - wrap;
end
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of DC RAM blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_ram.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.2 2003/12/10 15:28:28 simons
// Support for ram with byte selects added.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_ram(
// Reset and clock
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x32_bw dc_ram(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x32_bw dc_ram(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
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#include <bits/stdc++.h> using namespace std; long long int t[4000005]; void update(long long int v, long long int tl, long long int tr, long long int pos) { if (tl == tr) { t[v]++; return; } long long int tm = (tl + tr) / 2; if (pos <= tm) update(2 * v, tl, tm, pos); else update(2 * v + 1, tm + 1, tr, pos); t[v] = t[2 * v] + t[2 * v + 1]; } long long int sum(long long int v, long long int tl, long long int tr, long long int l, long long int r) { if (l > r) return 0; if (l == tl && r == tr) return t[v]; long long int tm = (tl + tr) / 2; return sum(2 * v, tl, tm, l, min(r, tm)) + sum(2 * v + 1, tm + 1, tr, max(l, tm + 1), r); } void solve() { long long int n, k; cin >> n >> k; if (k >= (n + 1) / 2) k = n - k; long long int cnt = n, x = 1, cur = 1; while (cnt) { long long int y = x + k; if (y > n) y -= n; long long int s = x + 1, e = y - 1, val; if (s == n + 1) s = 1; if (e == 0) e = n; if (s <= e) val = sum(1, 1, n, s, e); else val = sum(1, 1, n, s, n) + sum(1, 1, n, 1, e); cur += val + 1; cout << cur << ; update(1, 1, n, x); update(1, 1, n, y); x = y; cnt--; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); clock_t z = clock(); long long int qc = 1; for (long long int i = 1; i <= qc; i++) { solve(); } fprintf(stderr, Total Time:%.4Lf n , (long double)(clock() - z) / CLOCKS_PER_SEC), fflush(stderr); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, i, oo = 0, oz = 0, zo = 0, zz = 0; char s1[2000005], s2[2000005]; cin >> t; cin >> s1; cin >> s2; t = 2 * t; for (i = 0; i < t; i++) { if (s1[i] == 1 && s2[i] == 1 ) oo++; else if (s1[i] == 1 && s2[i] == 0 ) oz++; else if (s1[i] == 0 && s2[i] == 1 ) zo++; else zz++; } if (oo % 2 == 0) { if (oz > zo) cout << First ; else if (oz + 1 == zo || oz == zo) cout << Draw ; else cout << Second ; } else { if (oz >= zo) cout << First ; else if (oz + 1 == zo || oz + 2 == zo) cout << Draw ; else cout << Second ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int OO = 0x3f3f3f3f, N = 1e5 + 5, mod = 1e9 + 7; const double pi = acos(-1), EPS = 1e-8; int n, x, y, idx[N]; int main() { memset(idx, -1, sizeof idx); scanf( %d , &n); for (int t = 1; t <= n; ++t) { scanf( %d%d , &x, &y); int cnt = 0; for (int i = 1; i * i <= x; ++i) if (x % i == 0) { cnt += (idx[i] < t - y) + (i * i != x && idx[x / i] < t - y); idx[i] = idx[x / i] = t; } printf( %d n , cnt); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_TB_V
`define SKY130_FD_SC_HDLL__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_TB_V
|
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