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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:00:03 05/22/2014
// Design Name:
// Module Name: cpu_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_top(
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec,
output wire [5:0] initype,
output wire [3:0] node,
output wire [7:0] segment
);
wire clock;
wire memclock;
wire resetn;
wire [31:0] dpdata;
reg [15:0] digit,count=0;
wire [7:0] pc;
wire [31:0] inst;
wire [31:0] ealu;
wire [31:0] malu;
wire [31:0] walu;
wire [7:0] bpc,jpc,npc,dpc4,epc4,pc4;
wire [31:0] ins,da,db,ea,eb,dimm,eimm; //instÖظ´£¿
wire [31:0] mb,mmo,wmo,wdi;
wire [4:0] drn,ern0,ern,mrn,wrn,dsa,esa;
wire [3:0] daluc,ealuc;
wire [1:0] pcsource;
wire wpcir;
wire dwreg,dm2reg,dwmem,daluimm,dshift,djal;//id stage
wire ewreg,em2reg,ewmem,ealuimm,eshift,ejal;//exe stage
wire mwreg,mm2reg,mwmem;//mem stage
wire wwreg,wm2reg;//wb stage
pbdebounce p0(clk,stp,clock);
assign memclock=clk;
pbdebounce p1(clk,rst,resetn);
always @(posedge clock) count=count+1;
pipepc prog_cnt(npc,wpcir,clock,resetn,pc);
pipeif if_stage(pcsource,pc,bpc,da,jpc,npc,pc4,ins);
pipeir inst_reg(pc4,ins,wpcir,clock,resetn,dpc4,inst);
pipeid id_stage(mwreg,mrn,ern,ewreg,em2reg,mm2reg,dpc4,inst,wrn,wdi,ealu,malu,mmo,wwreg,clock,resetn,bpc,jpc,pcsource,wpcir,dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dsa,regselect,dpdata);
pipedereg de_reg(dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dpc4,dsa,clock,resetn,ewreg,em2reg,ewmem,ealuc,ealuimm,ea,eb,eimm,ern0,eshift,ejal,epc4,esa);
pipeexe exe_stage(ealuc,ealuimm,ea,eb,eimm,esa,eshift,ern0,epc4,ejal,ern,ealu);
pipeemreg em_reg(ewreg,em2reg,ewmem,ealu,eb,ern,clock,resetn,mwreg,mm2reg,mwmem,malu,mb,mrn);
pipemem mem_stage(mwmem,malu,mb,clock,memclock,mmo);
pipemwreg mw_reg(mwreg,mm2reg,mmo,malu,mrn,clock,resetn,wwreg,wm2reg,wmo,walu,wrn);
mux2x32 wb_stage(walu,wmo,wm2reg,wdi);
display dp(clk,digit,node,segment);
always @* begin
case (dptype)
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<={8'b0,pc[7:0]};
2'b11:digit<=count;
endcase
end
assign exec=clock;
assign initype=inst[31:26];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:31:47 10/30/2016
// Design Name: Main
// Module Name: /home/fede/DatosWindows/Facultad/Arquitectura de Computadoras/WorkspaceXilinxIse/UART/UART_Arquitectura/testMain.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testMain;
// Inputs
reg rx;
reg clk;
reg reset;
reg baud_rate;
// Outputs
wire tx;
// Instantiate the Unit Under Test (UUT)
Main uut (
.rx(rx),
.clk(clk),
.reset(reset),
.tx(tx)
);
BaudRateGenerator baud (
.clk(clk),
.out(baud_rate)
);
initial begin
// Initialize Inputs
rx = 0;
clk = 0;
reset = 0;
#100;
end
always@(posedge baud_rate)
begin
count = count + 1;
end
always@(posedge baud_rate)
begin
if(count == 16)
begin
if(bit_count == 0)
begin
rx = 0;
bit_count = bit_count + 1;
end
else
begin
if(bit_count < 9)
begin
rx = dato[7];
dato = dato << 1;
end
if(bit_count == 9) rx = 1; //stop bit
if(bit_count == 11) rx = 0; //start bit
if(bit_count > 11 && bit_count < 20)
begin
rx = dato2[7];
dato2 = dato2 << 1;
end
if(bit_count == 21) rx = 1; //stop bit
bit_count = bit_count+1;
end
count = 0;
end
end
always
begin
#1; clk = 1;
#1; clk = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt[2][2]; string s; int main() { ios_base::sync_with_stdio(0); cin >> s; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { cnt[i][j] = 0; } } for (int i = 0; i < s.length(); i++) { cnt[i & 1][s[i] - a ]++; } long long ans = 0; for (int i = 0; i < 2; i++) { ans += (long long)cnt[0][i] * cnt[1][i]; } cout << ans << ; ans = 0; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { ans += (long long)cnt[i][j] * (cnt[i][j] + 1) / 2; } } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int L = 1000000 + 10; int main() { int n; scanf( %d , &n); char s[n + 10]; scanf( %s , s); int next[n + 10]; next[0] = -1; int j = 0, k = -1; int maxn = 1; while (j < n) { if (k == -1 || s[j] == s[k]) { next[++j] = ++k; int xun = j - next[j]; maxn = max(maxn, j / xun / 2 * xun); } else k = next[k]; } printf( %d n , n - maxn + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void boost() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long long maxn = 2e6 + 123; const long long inf = 1e9 + 123; const long long linf = 1e18 + 123; const long long mod = 1e9 + 7; const double eps = 1e-9; const double pi = acos(-1); int dx[8] = {0, 1, -1, 0, 1, -1, 1, -1}; int dy[8] = {1, 0, 0, -1, 1, 1, -1, -1}; long long a[maxn], b[maxn]; vector<pair<long long, long long> > v[maxn]; int main() { boost(); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] += a[i - 1]; } for (int i = 1; i <= n; i++) { cin >> b[i]; b[i] += b[i - 1]; } bool WAS = 0; if (a[n] > b[n]) { swap(a, b); WAS = 1; } for (int i = 1; i <= n; i++) { int j = lower_bound(b + 1, b + 1 + n, a[i]) - b; if (a[i] != b[j]) { j--; } v[a[i] - b[j]].push_back({i, j}); } if (v[0].size() >= 1) { if (WAS == 0) { cout << v[0][0].first << n ; for (int i = 1; i <= v[0][0].first; i++) { cout << i << ; } cout << n ; cout << v[0][0].second << n ; for (int i = 1; i <= v[0][0].second; i++) { cout << i << ; } cout << n ; } else { cout << v[0][0].second << n ; for (int i = 1; i <= v[0][0].second; i++) { cout << i << ; } cout << n << v[0][0].first << n ; for (int i = 1; i <= v[0][0].first; i++) { cout << i << ; } cout << n ; } return 0; } for (int i = 1; i < n; i++) { if (v[i].size() >= 2) { if (WAS == 0) { cout << v[i][1].first - v[i][0].first << n ; for (int j = v[i][0].first + 1; j <= v[i][1].first; j++) { cout << j << ; } cout << n << v[i][1].second - v[i][0].second << n ; for (int j = v[i][0].second + 1; j <= v[i][1].second; j++) { cout << j << ; } return 0; } else { cout << v[i][1].second - v[i][0].second << n ; for (int j = v[i][0].second + 1; j <= v[i][1].second; j++) { cout << j << ; } cout << n << v[i][1].first - v[i][0].first << n ; for (int j = v[i][0].first + 1; j <= v[i][1].first; j++) { cout << j << ; } return 0; } } } exit(0); }
|
#include <bits/stdc++.h> using namespace std; void read(int &a) { a = 0; char c = getchar(); while (c < 0 || c > 9 ) { c = getchar(); } while (c >= 0 && c <= 9 ) { a = (a << 1) + (a << 3) + (c ^ 48); c = getchar(); } } const int Maxn = 200000; struct Segment { int l, r, t; friend bool operator<(Segment p, Segment q) { if (p.r == q.r) { return p.l < q.l; } return p.r < q.r; } } a[Maxn + 5]; int f[Maxn + 5]; int n; int d[Maxn << 1 | 5], d_len; struct Segment_Node { int lson, rson; int val, lazy; } seg[Maxn << 4 | 5]; int Root[2]; int id_tot; void insert(int l, int r, int x, int &root, int left = 1, int right = d_len) { if (l > right || r < left) { return; } if (root == 0) { root = ++id_tot; } if (l <= left && r >= right) { seg[root].val += x; seg[root].lazy += x; return; } int mid = (left + right) >> 1; insert(l, r, x, seg[root].lson, left, mid); insert(l, r, x, seg[root].rson, mid + 1, right); seg[root].val = max(seg[seg[root].lson].val, seg[seg[root].rson].val) + seg[root].lazy; } int query(int l, int r, int root, int left = 1, int right = d_len) { if (l > right || r < left) { return 0; } if (root == 0) { return 0; } if (l <= left && r >= right) { return seg[root].val; } int mid = (left + right) >> 1; return max(query(l, r, seg[root].lson, left, mid), query(l, r, seg[root].rson, mid + 1, right)) + seg[root].lazy; } void update(int x, int a, int &root, int left = 1, int right = d_len) { if (root == 0) { root = ++id_tot; } a -= seg[root].lazy; if (left == right) { seg[root].val = max(seg[root].val, a); return; } int mid = (left + right) >> 1; if (x <= mid) { update(x, a, seg[root].lson, left, mid); } else { update(x, a, seg[root].rson, mid + 1, right); } seg[root].val = max(seg[seg[root].lson].val, seg[seg[root].rson].val) + seg[root].lazy; } int main() { read(n); for (int i = 1; i <= n; i++) { read(a[i].l), read(a[i].r), read(a[i].t); a[i].t--; d[++d_len] = a[i].l; d[++d_len] = a[i].r; } sort(d + 1, d + 1 + d_len); d_len = unique(d + 1, d + 1 + d_len) - d - 1; for (int i = 1; i <= n; i++) { a[i].l = lower_bound(d + 1, d + 1 + d_len, a[i].l) - d + 1; a[i].r = lower_bound(d + 1, d + 1 + d_len, a[i].r) - d + 1; } d_len++; sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { f[i] = query(1, a[i].l - 1, Root[a[i].t]) + 1; insert(1, a[i].l - 1, 1, Root[a[i].t]); update(a[i].r, f[i], Root[a[i].t ^ 1]); } int ans = 0; for (int i = 1; i <= n; i++) { ans = max(ans, f[i]); } printf( %d n , ans); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_rows_V_channel3_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_rows_V_channel3 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_rows_V_channel3_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_rows_V_channel3_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 21608 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w2064,
w2193,
w516,
w2709,
w8,
w2701,
w21608;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w2064 = w129 << 4;
assign w21608 = w2701 << 3;
assign w2193 = w129 + w2064;
assign w2701 = w2709 - w8;
assign w2709 = w2193 + w516;
assign w516 = w129 << 2;
assign w8 = w1 << 3;
assign o_data0 = w21608;
//multiplier_block area estimate = 6719.32805906029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cin.ignore(); string arr; getline(cin, arr); int mx = 0; int cur = 0; for (int i = 0; i < n; i++) { if (arr[i] == ) { mx = max(mx, cur); cur = 0; continue; } if (isupper(arr[i])) { cur++; } } mx = max(mx, cur); cout << mx; return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast , unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long inf = numeric_limits<long long>::max() / 2; const long double eps = 1e-9; const long double pi = acos(-1); template <typename T> inline bool mineq(T& a, T b) { return (a > b) ? (a = b, 1) : 0; } template <typename T> inline bool maxeq(T& a, T b) { return (a < b) ? (a = b, 1) : 0; } inline void solve(), read(); const string file = ; int main() { if (file != ) { freopen((file + .in ).c_str(), r , stdin); freopen((file + .out ).c_str(), w , stdout); } ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; read(); solve(); return 0; } const long long R = 998244353; string a, l, r; long long n; vector<long long> dp, suff; vector<long long> zl, zr; void zet(string s, vector<long long>& z) { long long n = (long long)((s).size()); z.assign(n, 0); z[0] = 0; for (long long i = 1, l = 0, r = 0; i < n; i++) { if (i <= r) { z[i] = min(z[i - l], r - i); } while (i + z[i] < n && s[z[i]] == s[i + z[i]]) { ++z[i]; } if (i + z[i] - 1 > r) { r = i + z[i] - 1; l = i; } } } inline void solve() { zet(l + # + a, zl); zet(r + # + a, zr); dp.assign(n + 2, 0); suff.assign(n + 2, 0); long long ans = 0; dp[n] = 1; suff[n] = 1; for (long long i = n - 1; i >= 0; i--) { if (a[i] == 0 ) { if (l == 0 ) { dp[i] = dp[i + 1]; } suff[i] = (dp[i] + suff[i + 1]) % ::R; continue; } long long L = i + (long long)((l).size()); long long R = i + (long long)((r).size()); long long sleft = zl[(long long)((l).size()) + 1 + i]; long long sright = zr[(long long)((r).size()) + 1 + i]; if (sleft != (long long)((l).size())) { if (a[i + sleft] < l[sleft]) { ++L; } } if (sright != (long long)((r).size())) { if (a[i + sright] > r[sright]) { --R; } } if (L <= R && L <= n) { mineq(R, n); dp[i] = (suff[L] - suff[R + 1] + ::R) % ::R; } suff[i] = (dp[i] + suff[i + 1]) % ::R; } cout << dp[0] << n ; } inline void read() { cin >> a >> l >> r; n = (long long)((a).size()); }
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#include <bits/stdc++.h> using namespace std; int l[7]; int main() { scanf( %d%d%d , &l[3], &l[4], &l[5]); double a, A, ap, r, anw = 0; for (int n = 3; n <= 5; n++) { a = acos(-1) / n; A = 1.0 * n / 4 * l[n] * l[n] / tan(a); ap = A * 2 / n / l[n]; r = ap / cos(a); anw += A * sqrt(l[n] * l[n] - r * r) / 3; } printf( %.10lf , anw); }
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#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double EPS = 1e-10; const int INF = 0x3fffffff; const long long LINF = INF * 1ll * INF; const double PI = acos(-1.0); using namespace std; int sign(double x) { return x > 0 ? 1 : -1; } int main(void) { int x1, y1, x2, y2; scanf( %d %d %d %d , &x1, &y1, &x2, &y2); int vmax, t; scanf( %d %d , &vmax, &t); double low = 0, high = t; double windX, windY; scanf( %lf %lf , &windX, &windY); double newX, newY; scanf( %lf %lf , &newX, &newY); bool find = false; while (low + EPS <= high) { double mid = (low + high) / 2.0; double deltaX = x2 - x1; double deltaY = y2 - y1; double vx = deltaX / mid - windX; if (abs(vx) - abs(vmax) > 0) { low = mid; continue; } double vy = sqrt(vmax * vmax - vx * vx) + windY; double mx = vy * mid; vy = -sqrt(vmax * vmax - vx * vx) + windY; double mi = vy * mid; if (mx < mi) swap(mx, mi); if (mi - EPS <= deltaY && deltaY <= mx + EPS) { high = mid; find = true; } else low = mid; } if (!find) { low = t, high = 1e9; while (low + EPS <= high) { double mid = (low + high) / 2.0; double deltaX = x2 - x1; double deltaY = y2 - y1; double vx = deltaX - t * windX - newX * (mid - t); vx /= mid; if (abs(vx) - abs(vmax) > 0) { low = mid; continue; } double vy = sqrt(vmax * vmax - vx * vx); double mx = vy * mid + t * windY + (mid - t) * newY; vy = -sqrt(vmax * vmax - vx * vx); double mi = vy * mid + t * windY + (mid - t) * newY; if (mx < mi) swap(mx, mi); if (mi - EPS <= deltaY && deltaY <= mx + EPS) { high = mid; } else low = mid; } } printf( %.10lf n , low); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { long long m = 1, ans = 1; long long n; cin >> n; while (ans < n) { m++; ans += 2; } cout << m << n ; long long x = 1, y = 1; cout << 1 << << 1 << n ; x++; for (long long i = 1; i < n; i++) { cout << x << << y << n ; if (i == n - 1) break; i++; cout << x << << y + 1 << n ; x++; y++; } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:05:35 06/18/2015
// Design Name:
// Module Name: gainMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gainMult(
input clk,
input [1:0] oflowMode,
input signed [15:0] mixerIn,
input signed [6:0] gain,
output reg signed [15:0] dout = 16'sd0,
output reg overflow = 1'b0
);
parameter GAIN_SCALE = 1; //sets the scale factor for the gain; e.g. 128 ADC cnts maps to 2048 at DAC for GAIN_SCALE = -4 //
parameter GAIN_OFFSET = 5; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 7-bit gain //
parameter GAIN_MSB = 23;
(* shreg_extract = "no" *) reg signed [15:0] mixerIn_reg = 16'sd0; // gainMult input register //
(* shreg_extract = "no" *) reg signed [6:0] gain_reg = 7'sd0, gain_reg_b = 7'sd0; // 7-bit gain // gainMult input register //
//(* shreg_extract = "no" *) reg signed [13:0] gain_reg = 14'sd0; // 14-bit gain // gainMult input register //
reg signed [GAIN_MSB:0] gainMult = 24'sd0;// = GAIN_MSB+1'sd0; // 7-bit gain //
//reg signed [GAIN_MSB:0] gainMult = 31'sd0; // 14-bit gain //
wire oflowDet = (~&gainMult[GAIN_MSB:GAIN_OFFSET+GAIN_SCALE+15] && ~&(~gainMult[GAIN_MSB:GAIN_OFFSET+GAIN_SCALE+15]));
always @(posedge clk) begin
mixerIn_reg <= mixerIn;
gain_reg <= gain;
gain_reg_b <= gain_reg;
gainMult <= (mixerIn_reg * gain_reg_b);
overflow <= oflowDet;
if (oflowDet) begin
case (oflowMode)
2'b00: dout <= gainMult[GAIN_OFFSET+GAIN_SCALE+15:GAIN_OFFSET+GAIN_SCALE]; // do nothing - ignore overflow //
2'b01: dout <= 16'sd0; // kill output //
2'b10: dout <= (gainMult[GAIN_MSB]) ? -16'sd32768 : 16'sd32767; // saturate output //
default: dout <= 16'sd0;
endcase
end else dout <= gainMult[GAIN_OFFSET+GAIN_SCALE+15:GAIN_OFFSET+GAIN_SCALE];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x, ans, sum = 0; cin >> x; x = abs(x); for (int i = 0;; i++) { sum += i; if (sum >= x && (sum - x) % 2 == 0) { ans = i; break; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; if ((int)s.size() < 26) { cout << -1; return 0; } char cur = a ; bool fg = 0; for (int i = 0; i < (int)s.size(); i++) { if (s[i] <= cur) { if (cur == z ) { s[i] = cur; fg = 1; break; } else s[i] = cur; cur++; } } if (cur == z && fg) cout << s; else cout << -1; return 0; }
|
#include<bits/stdc++.h> #define fort(i,a,b) for(long long i=a;i<=b;i++) #define forn(i,a,b) for(long long i=a;i>=b;i--) #define rep(i,a,b) for(long long i=a;i<b;i++) #define x first #define y second #define pb push_back #define MP make_pair using namespace std; const long long N=2e5+5; long long s1,s2,d,c,test,n,l[N][20],f[N],kq[N],h[N],cnt[N],kt[N],timer,tin[N],tout[N]; vector<long long > a[N]; void dfs(long long u,long long pa) { tin[u]=++timer; h[u]=h[pa]+1; l[u][0]=pa; cnt[u]++; for(long long v:a[u]) if (v!=pa) { dfs(v,u); f[u]+=cnt[u]*cnt[v]; cnt[u]+=cnt[v]; } f[u]+=(n-cnt[u])*cnt[u]; tout[u]=++timer; } void build_lca() { fort(i,1,log2(n)) fort(j,1,n) l[j][i]=l[l[j][i-1]][i-1]; } long long lca(long long u,long long v) { if (h[u]<h[v]) swap(u,v); forn(i,log2(h[u]),0) if (h[l[u][i]]>=h[v]) u=l[u][i]; if (u==v) return u; forn(i,log2(h[u]),0) if (l[u][i]!=l[v][i]) { u=l[u][i]; v=l[v][i]; } return l[u][0]; } void chinh(long long x) { if (kt[x]) return; kt[x]=1; chinh(l[x][0]); } bool con(long v,long u) { return tin[u]<tin[v]&&tout[v]<tout[u]; } int main() { ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); cin>>test; while (test--) { cin>>n; fort(i,1,n-1) { long long u,v; cin>>u>>v; u++;v++; a[u].pb(v); a[v].pb(u); } dfs(1,0); build_lca(); kq[1]=n*(n-1)/2-f[1]; kq[n+1]=1; fort(i,1,n) if (a[i].size()>2) kq[n+1]=0; d=1;c=1;s1=0;s2=0; kt[1]=1; fort(i,2,n) if (!kt[i]) { if (d!=c) { if (c==1) { if (lca(i,d)!=1&&lca(i,d)!=d&&kt[lca(i,d)]) { kq[i]=s2*cnt[d]; break; } } else { if (lca(i,d)!=d&&lca(i,c)!=c) { kq[i]=cnt[d]*cnt[c]; break; } } if (con(i,d)) { chinh(i); s1=cnt[d]-cnt[i]; kq[i]=s1*s2; d=i; s1=cnt[d]; } else if (con(i,c)) { chinh(i); if (c==1) s2-=cnt[i];else s2=cnt[c]-cnt[i]; kq[i]=s1*s2; c=i; s2=cnt[c]; } } else { chinh(i); for(long long v:a[1]) if (!kt[v]) s2+=cnt[v]; s2++;s1=cnt[i]; kq[i]=f[1]-cnt[i]*s2; d=i; } } fort(i,1,n+1) cout<<kq[i]<< ;cout<< n ; fort(i,1,n) a[i].clear(); fort(i,1,n+1) kq[i]=0; fort(i,1,n) cnt[i]=0; fort(i,1,n) fort(j,0,log2(n)) l[i][j]=0; fort(i,1,n) kt[i]=0; fort(i,1,n) f[i]=0; timer=0; } }
|
// File : ../RTL/slaveController/sctxportarbiter.v
// Generated : 11/10/06 05:37:24
// From : ../RTL/slaveController/sctxportarbiter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// SCTxPortArbiter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
input SCTxPortRdyIn;
input clk;
input [7:0] directCntlCntl;
input [7:0] directCntlData;
input directCntlReq;
input directCntlWEn;
input rst;
input [7:0] sendPacketCntl;
input [7:0] sendPacketData;
input sendPacketReq;
input sendPacketWEn;
output [7:0] SCTxPortCntl;
output [7:0] SCTxPortData;
output SCTxPortRdyOut;
output SCTxPortWEnable;
output directCntlGnt;
output sendPacketGnt;
reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
reg [7:0] SCTxPortData, next_SCTxPortData;
wire SCTxPortRdyIn;
reg SCTxPortRdyOut, next_SCTxPortRdyOut;
reg SCTxPortWEnable, next_SCTxPortWEnable;
wire clk;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
reg directCntlGnt, next_directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire rst;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
reg sendPacketGnt, next_sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
// diagram signals declarations
reg muxDCEn, next_muxDCEn;
// BINARY ENCODED state machine: SCTxArb
// State codes definitions:
`define SARB1_WAIT_REQ 2'b00
`define SARB_SEND_PACKET 2'b01
`define SARB_DC 2'b10
`define START_SARB 2'b11
reg [1:0] CurrState_SCTxArb;
reg [1:0] NextState_SCTxArb;
// Diagram actions (continuous assignments allowed only: assign ...)
// SOFController/directContol/sendPacket mux
always @(SCTxPortRdyIn)
begin
SCTxPortRdyOut <= SCTxPortRdyIn;
end
always @(muxDCEn or
directCntlWEn or directCntlData or directCntlCntl or
directCntlWEn or directCntlData or directCntlCntl or
sendPacketWEn or sendPacketData or sendPacketCntl)
begin
if (muxDCEn == 1'b1)
begin
SCTxPortWEnable <= directCntlWEn;
SCTxPortData <= directCntlData;
SCTxPortCntl <= directCntlCntl;
end
else
begin
SCTxPortWEnable <= sendPacketWEn;
SCTxPortData <= sendPacketData;
SCTxPortCntl <= sendPacketCntl;
end
end
//--------------------------------------------------------------------
// Machine: SCTxArb
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
begin : SCTxArb_NextState
NextState_SCTxArb <= CurrState_SCTxArb;
// Set default values for outputs and signals
next_sendPacketGnt <= sendPacketGnt;
next_muxDCEn <= muxDCEn;
next_directCntlGnt <= directCntlGnt;
case (CurrState_SCTxArb)
`SARB1_WAIT_REQ:
if (sendPacketReq == 1'b1)
begin
NextState_SCTxArb <= `SARB_SEND_PACKET;
next_sendPacketGnt <= 1'b1;
next_muxDCEn <= 1'b0;
end
else if (directCntlReq == 1'b1)
begin
NextState_SCTxArb <= `SARB_DC;
next_directCntlGnt <= 1'b1;
next_muxDCEn <= 1'b1;
end
`SARB_SEND_PACKET:
if (sendPacketReq == 1'b0)
begin
NextState_SCTxArb <= `SARB1_WAIT_REQ;
next_sendPacketGnt <= 1'b0;
end
`SARB_DC:
if (directCntlReq == 1'b0)
begin
NextState_SCTxArb <= `SARB1_WAIT_REQ;
next_directCntlGnt <= 1'b0;
end
`START_SARB:
NextState_SCTxArb <= `SARB1_WAIT_REQ;
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SCTxArb_CurrentState
if (rst)
CurrState_SCTxArb <= `START_SARB;
else
CurrState_SCTxArb <= NextState_SCTxArb;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SCTxArb_RegOutput
if (rst)
begin
muxDCEn <= 1'b0;
sendPacketGnt <= 1'b0;
directCntlGnt <= 1'b0;
end
else
begin
muxDCEn <= next_muxDCEn;
sendPacketGnt <= next_sendPacketGnt;
directCntlGnt <= next_directCntlGnt;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> a(n), t(n); vector<pair<long long, long long> > vp; for (int i = 0; i < n; i++) { cin >> a[i]; vp.push_back({a[i], i}); } for (int i = 0; i < n; i++) cin >> t[i]; long long ans = 0; sort(vp.begin(), vp.end()); long long sum = 0; priority_queue<long long> pq; int i = 0; while (i < n) { int j; for (j = i; j < n; j++) { if (vp[i].first == vp[j].first) { sum += t[vp[j].second]; pq.push(t[vp[j].second]); } else break; } long long num = vp[i].first; while (j < n && pq.empty() == 0 && num < vp[j].first) { sum -= pq.top(); pq.pop(); ans += sum; num++; } i = j; } while (pq.empty() == 0) { sum -= pq.top(); pq.pop(); ans += sum; } cout << ans << n ; } int main(void) { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:51:17 11/29/2011
// Design Name: np_core
// Module Name: C:/Hari/Study/Masters_thesis/needtosee/altera_netfpga_08_08_11/Danai_proj/xilinx _test_localram/latest_code_nov20/to_send/ngnp_added_monitor/ngnp/src/testbench.v
// Project Name: np_core
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: np_core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench();
// Inputs
reg out_rdy;
reg [63:0] in_data;
reg [7:0] in_ctrl;
reg in_wr;
reg reg_req_in;
reg reg_ack_in;
reg reg_rd_wr_L_in;
reg [22:0] reg_addr_in;
reg [31:0] reg_data_in;
reg [1:0] reg_src_in;
reg clk;
reg core_sp_clk;
reg reset;
reg packet_drop;
// Outputs
wire [63:0] out_data;
wire [7:0] out_ctrl;
wire out_wr;
wire in_rdy;
wire reg_req_out;
wire reg_ack_out;
wire reg_rd_wr_L_out;
wire [22:0] reg_addr_out;
wire [31:0] reg_data_out;
wire [1:0] reg_src_out;
wire [31:0] ppu_mem_addr;
// Instantiate the Unit Under Test (UUT)
np_core uut (
.out_data(out_data),
.out_ctrl(out_ctrl),
.out_wr(out_wr),
.out_rdy(out_rdy),
.in_data(in_data),
.in_ctrl(in_ctrl),
.in_wr(in_wr),
.in_rdy(in_rdy),
.reg_req_in(reg_req_in),
.reg_ack_in(reg_ack_in),
.reg_rd_wr_L_in(reg_rd_wr_L_in),
.reg_addr_in(reg_addr_in),
.reg_data_in(reg_data_in),
.reg_src_in(reg_src_in),
.reg_req_out(reg_req_out),
.reg_ack_out(reg_ack_out),
.reg_rd_wr_L_out(reg_rd_wr_L_out),
.reg_addr_out(reg_addr_out),
.reg_data_out(reg_data_out),
.reg_src_out(reg_src_out),
.clk(clk),
.core_sp_clk(clk),
.reset(reset),
.ppu_mem_addr(ppu_mem_addr),
.packet_drop(packet_drop)
);
initial begin
// Initialize Inputs
out_rdy = 0;
in_data = 0;
in_ctrl = 0;
in_wr = 0;
reg_req_in = 0;
reg_ack_in = 0;
reg_rd_wr_L_in = 0;
reg_addr_in = 0;
reg_data_in = 0;
reg_src_in = 0;
clk = 0;
core_sp_clk = 0;
reset = 1;
packet_drop = 0;
// Wait 100 ns for global reset to finish
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
// Add stimulus here
reset = 0;
out_rdy = 1;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'hff;
in_data = 64'h0000000e0004006a;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h004e46324302004e;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h4632430208004500;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h005c000040004001;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h1f9b0a0203020a01;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h04020800d0c4b63d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h000f92d3b04c55da;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h000008090a0b0c0d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h0e0f101112131415;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h0e0f101112131415;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h161718191a1b1c1d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h1e1f202122232425;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h262728292a2b2c2d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h2e2f303132333435;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h363738393a3b3c3d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h02;
in_data = 64'h3e3f3f3f3f3f3f3f;
@(posedge clk);
@(negedge clk);
in_wr = 0;
in_ctrl = 8'h00;
in_data = 64'h0;
end
always begin
#800 clk = ~clk;
end
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
instruction fetch phase
*/
module cpu_if(rst, clk, cpu_stall, imem_addr, p_pc, pc_j,
pc_b, b_addr, j_addr, iin, p_inst, stall, int, int_ack, int_flush, int_pc);
input rst, clk, cpu_stall, int;
input pc_j;
input pc_b;
input [31:0] b_addr;
input [31:0] j_addr;
input stall;
output reg [31:0] p_pc;
output [31:0] imem_addr;
input [31:0] iin;
output reg [31:0] p_inst;
output int_ack, int_flush;
input [31:0] int_pc;
reg [31:0] pc;
wire [31:0] next_pc;
/* flush logic (for branches and jumps) */
wire flush = pc_b | pc_j;
/* interrupt logic */
/* we're guaranteed not to get an interrupt when
* handling one already, as interrupts disable
* in the interrupt controller automatically.
*
* state machine:
* 00 - idle, waiting for interrupt
* 01 - wait 1 cycle for branch delay slot
* 10 - injecting interrupt
* 11 - injecting nop (branch delay slot)
*/
reg [1:0] int_state = 2'b00;
wire cycle_wait = pc - int_pc != 8;
wire [1:0] next_int_state =
int_state == 2'b00 && int && cycle_wait ? 2'b01 : /* wait 1 cycle */
int_state == 2'b00 && int && !cycle_wait ? 2'b10 : /* go! */
int_state == 2'b01 && !cycle_wait ? 2'b10 : /* ...go */
int_state == 2'b10 ? 2'b11 :
int_state == 2'b11 ? 2'b00 : int_state; /* default case is invalid */
wire [31:0] next_inst =
int_state == 2'b10 ? 32'h0380f009 : /* jalr $ir, $iv - 0000_0011_1000_0000_1111_0000_0000_1001 */
int_state == 2'b11 ? 32'h00000000 : /* nop */
iin;
assign int_ack = int_state != 2'b00;
assign int_flush = next_int_state == 2'b10;
always @(posedge clk) begin
if (!cpu_stall) begin
if (rst) begin
p_pc <= 0;
pc <= 0;
p_inst <= 0;
int_state <= 0;
end else if (stall && !flush && !rst) begin
p_pc <= p_pc;
pc <= pc;
p_inst <= p_inst;
int_state <= next_int_state;
end else if ((flush || int_flush) && !rst && !stall) begin
p_pc <= 0;
p_inst <= 0;
pc <= next_pc;
int_state <= next_int_state;
end else begin
p_pc <= pc;
pc <= next_pc;
p_inst <= next_inst;
int_state <= next_int_state;
end
/* debug code, not synthesized by Xilinx */
$display("IF: PC: %x INST: %x", p_pc, p_inst);
end
end
assign next_pc =
(next_int_state == 2'b10) ? int_pc - 8:
(pc_b & next_int_state != 2'b10) ? b_addr :
(pc_j & !pc_b & next_int_state != 2'b10) ? j_addr :
pc + 4;
assign imem_addr = pc;
endmodule
|
#include <bits/stdc++.h> int inp() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int sum = 0; while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum; } int root[1000010]; struct President_Tree { int lc[10000000], rc[10000000]; long long k[10000000], b[10000000]; int cnt; void push_up(int cur) { k[cur] = k[lc[cur]] + k[rc[cur]]; b[cur] = b[lc[cur]] + b[rc[cur]]; } void insert(int &cur, int last, int x, int kc, int bc, int l, int r) { cur = ++cnt; if (l == r) { k[cur] = k[last] + kc; b[cur] = b[last] + bc; return; } int mid = (l + r) >> 1; if (x <= mid) { insert(lc[cur], lc[last], x, kc, bc, l, mid); rc[cur] = rc[last]; } else { lc[cur] = lc[last]; insert(rc[cur], rc[last], x, kc, bc, mid + 1, r); } push_up(cur); } long long query(int cur, int last, int ql, int qr, long long x, int l, int r) { if (l > qr || r < ql) return 0; if (l >= ql && r <= qr) return x * (k[cur] - k[last]) + (b[cur] - b[last]); int mid = (l + r) >> 1; return query(lc[cur], lc[last], ql, qr, x, l, mid) + query(rc[cur], rc[last], ql, qr, x, mid + 1, r); } } t; int main() { int n = inp(); for (int i = 1; i <= n; i++) { int xl = inp(); int xr = inp(); int yl = inp(); int k = inp(); int b = inp(); int yr = inp(); t.insert(root[i], root[i - 1], 0, 0, yl, 0, 1e9); t.insert(root[i], root[i], xl + 1, k, b - yl, 0, 1e9); t.insert(root[i], root[i], xr + 1, -k, yr - b, 0, 1e9); } int m = inp(); long long lastans = 0; while (m--) { int l = inp(); int r = inp(); int x = (inp() + lastans) % 1000000000; lastans = t.query(root[r], root[l - 1], 0, x, x, 0, 1e9); printf( %lld n , lastans); } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; queue<int> v1; deque<int> v2; for (int i = 0; i < s.size(); i++) { if (s[i] == ( ) v1.push(i); else { v2.push_front(i); } } int k = 0; vector<int> res; while (!v1.empty() && !v2.empty()) { if (v1.front() > v2.front()) { v1.pop(); v2.pop_front(); continue; } k += 2; res.push_back(v2.front()); res.push_back(v1.front()); v1.pop(); v2.pop_front(); } sort(res.begin(), res.end()); if (k == 0) return cout << 0, 0; cout << 1 << n ; cout << k << n ; for (auto i : res) cout << i + 1 << ; }
|
// Must synthesize into 3 * 8x2048 brams
module vram(input clk,
input [12:0] p1_addr,
input [7:0] p1_data,
input p1_we,
input [12:0] p2_addr,
output reg [7:0] p2_data);
reg [7:0] mem[0:(3*2048)-1];
always @(posedge clk)
begin
if (p1_we) begin
mem[p1_addr] <= p1_data;
end
p2_data <= mem[p2_addr];
end
endmodule
module vgatop(input clk, // 100MHz clk
input rst,
input clk25mhz,
output hsync,
output vsync,
output rgb,
input [12:0] vmem_in_addr,
input [7:0] vmem_in_data,
input vmem_we);
wire [12:0] vmem_out_addr;
wire [7:0] vmem_out_data;
vram vram1(.clk(clk),
.p1_addr(vmem_in_addr),
.p1_data(vmem_in_data),
.p1_we(vmem_we),
.p2_addr(vmem_out_addr),
.p2_data(vmem_out_data)
);
vga vga1(.clk(clk),
.rst(rst),
.clk25mhz(clk25mhz),
.vmem_data(vmem_out_data),
.vmem_addr(vmem_out_addr),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb));
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
// *********************************************************************************************************************
// IMPORTANT
// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
// modifications you may choose to make.
// *********************************************************************************************************************
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_ultrascale_tx_userclk #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_tx_srcclk_in,
input wire gtwiz_userclk_tx_reset_in,
output wire gtwiz_userclk_tx_usrclk_out,
output wire gtwiz_userclk_tx_usrclk2_out,
output reg gtwiz_userclk_tx_active_out = 1'b0
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Transmitter user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_tx_main
// Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk_out)
);
// If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
if (gtwiz_userclk_tx_reset_in)
gtwiz_userclk_tx_active_out <= 1'b0;
else
gtwiz_userclk_tx_active_out <= 1'b1;
end
end
end
endgenerate
endmodule
|
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - bcd_ctr
Description: This module implements a 3-digit
bcd counter with async reset and enable inputs.
It is intended to be controlled by a state machine
that manages inputs from the lfsr and pushbuttons
================================================*/
`timescale 100 ns / 1 ns
module bcd_ctr(clk, en, ar, dig1, dig2, dig3);
/*======================================
Parameters
======================================*/
/*======================================
Input/Output Declaration
======================================*/
input clk, ar, en;
output reg [3:0] dig1, dig2, dig3;
/*======================================
Internal wires/registers
======================================*/
wire dig1_carry, dig2_carry, dig3_carry;
/*======================================
Asynchronous Logic
======================================*/
assign dig1_carry = (dig1 == 4'd9); // Flag to indicate when to inc dig2
assign dig2_carry = dig1_carry&(dig2 == 4'd9); // Indicates when to inc dig3
assign dig3_carry = dig2_carry&(dig3 == 4'd9); // Indicates when timer should freeze
/*======================================
Synchronous Logic
======================================*/
always @ (posedge clk or negedge ar)
begin
if(~ar) // If ar is brought low, (or is low on a clk posedge)
begin
// Reset the current count
dig1 <= 4'd0;
dig2 <= 4'd0;
dig3 <= 4'd0;
end else if(~dig3_carry&en) // Only run the counter if en high and not at 999
begin
if(dig2_carry) // If dig2 and dig1 are 9's
begin
dig3 <= dig3 + 1; // Increment dig3
dig2 <= 0; // Reset the lower digits
dig1 <= 0;
end else if(dig1_carry) // If dig1 is a 9
begin
dig2 <= dig2 + 1; // Increment dig2
dig1 <= 0; // Reset lower digits
end else // If no carry-magic had to occur
begin
dig1 <= dig1 + 1; // Count normally
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_4_V
`define SKY130_FD_SC_LP__A2BB2O_4_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Detects rising and falling edge of input signal and outputs a
// single-cycle signal upon detection
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module edge_detect(
input clk,
input rst,
input in,
output rise_out, //single-shot output
output fall_out); //single-shot output
reg in_reg;
//one pipeline reg for the input signal
always@(posedge clk)begin
if(rst)begin
in_reg <= 1'b0;
end else begin
in_reg <= in;
end
end
//detect the rising edge
assign rise_out = ~in_reg & in;
//detect the falling edge
assign fall_out = in_reg & ~in;
endmodule
|
// O(q*log(q)) with pretty big constant factor #include<bits/stdc++.h> using namespace std; struct query { vector<int> nodes; }; // for a given path // active will find intersections not at it s lca // cnts with find intersections at it s lca const int maxn = 3e5 + 1; int n, m; vector<int> adj[maxn]; // for changing # active vector<pair<int,int>> updates[maxn]; // intersections of 2 paths with common lca = this node + for active vector<query> queries[maxn]; // counts of paths with lca at current point int tot_cnt = 0; map<long long, int> cnts; // intersections of 2 paths one at it s lca and the other not at it s lca int active[maxn]; long long ans = 0; // for lca int t = 0; int ancestor[maxn][20], tin[maxn], tout[maxn]; void dfs_lca(int c, int p) { tin[c] = t++; ancestor[c][0] = p; for (int i = 1; i < 20; i++) { ancestor[c][i] = ancestor[ancestor[c][i - 1]][i - 1]; } // messes with bin search if (!(c==1 and p == 1)) { adj[c].erase(find(adj[c].begin(), adj[c].end(), p)); } for (auto n : adj[c]) { dfs_lca(n, c); } tout[c] = t++; } // p is ancestor of a bool is_ancestor(int a, int p) { // lol <= is very important or else you say the lca of a and a is parent of a return tin[p] <= tin[a] and tout[a] <= tout[p]; } int find_lca(int a, int b) { if (is_ancestor(b, a)) { return a; } else if (is_ancestor(a, b)) { return b; } else { for (int i = 19; i >= 0; i--) { if (!is_ancestor(b, ancestor[a][i])) { a = ancestor[a][i]; } } return ancestor[a][0]; } } // find which subtree rooted at a child of c this node is in int find_sub(int node, int c) { int l = 0, r = adj[c].size() - 1; while (l != r) { int m = (l + r + 1) / 2; if (tin[adj[c][m]] <= tin[node]) { l = m; } else { r = m - 1; } } return adj[c][l]; } // for computing the intersections of line path with any other path void dfs(int c, int p) { for (auto n : adj[c]) { if (n != p) { dfs(n, c); active[c] += active[n]; } } for (auto upd : updates[c]) { if (upd.first == -1) { active[c]++; updates[upd.second].push_back({ c, upd.second }); } else { active[c]--; active[find_sub(upd.first, c)]--; } } // loop through queries and update cnts as you iterate so that every intersection is counted only one time for (auto& q : queries[c]) { // find which subtrees rooted at children of c each node in the query is in // use this for PIE and complementary counting later vector<long long> subtrees; for (auto& node : q.nodes) { if (node != c) { subtrees.push_back(find_sub(node,c)); } } // update ans with compl counting ans += tot_cnt + active[c]; if (subtrees.size() == 1) { ans += - cnts[subtrees[0]]; ans += - active[subtrees[0]]; } else if (subtrees.size() == 2) { // make unique if (subtrees[0] > subtrees[1]) { swap(subtrees[0], subtrees[1]); } ans += - cnts[subtrees[0]] - cnts[subtrees[1]] + cnts[subtrees[0] * maxn + subtrees[1]]; ans += - active[subtrees[0]] - active[subtrees[1]]; } // update cnts for (auto subtree : subtrees) { cnts[subtree]++; } if (subtrees.size() == 2) { cnts[subtrees[0] * maxn + subtrees[1]]++; } tot_cnt++; } tot_cnt = 0; cnts.clear(); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n-1; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } dfs_lca(1, 1); cin >> m; for (int i = 0; i < m; i++) { int a, b, lca; cin >> a >> b; lca = find_lca(a, b); queries[lca].push_back({ {a,b} }); if (a != lca) { updates[a].push_back({ -1, lca }); } if (b != lca) { updates[b].push_back({ -1, lca }); } } dfs(1, 1); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n, k, z, a[N]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { cin >> n >> k >> z; long long sum = 0; for (long long i = 1; i <= n; i++) cin >> a[i]; long long ans = 0; for (long long j = 0; j <= z; j++) { long long s = k - j; if (s < j) break; long long sum = 0; long long mx = 0; for (long long i = 1; i <= s - j + 1; i++) sum += a[i], mx = max(a[i] + a[i + 1], mx); ans = max(ans, sum + mx * j); } cout << ans << n ; } return 0; }
|
// file: clk32to40_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk32to40_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
clk32to40 clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int countbit(int a) { int i = 0; while (a != 0) { if (a & 1) i++; a /= 2; } return i; } int dp[1100000] = {0}; int main() { int a[150]; int arr[150], arr1[150] = {0}; int n, m; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (int i = 0; i < n / 2; i++) swap(a[i], a[n - 1 - i]); cin >> m; for (int i = m; i > 0; i--) { char s[50]; int x; cin >> s >> x; if (s[0] == p ) { arr1[i] = 1; } if (x == 1) arr[i] = 1; else arr[i] = -1; } dp[0] = 0; for (int i = 1; i < (1 << m); i++) { int z = countbit(i); if (arr[z] > 0) { dp[i] = -1 * 0x3f3f3f3f; for (int j = 0; j < m; j++) { if (i & (1 << j)) { dp[i] = max(dp[i], dp[i ^ (1 << j)] + arr1[z] * a[j]); } } } else { dp[i] = 0x3f3f3f3f; for (int j = 0; j < m; j++) { if (i & (1 << j)) { dp[i] = min(dp[i], dp[i ^ (1 << j)] - arr1[z] * a[j]); } } } } cout << dp[(1 << m) - 1]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 110; int N, A[Maxn]; map<int, int> K, dp; int SG(int x) { set<int> S; if (dp.count(x)) return dp[x]; if (x == 0) return 0; for (int i = 1; i <= 30; i++) { int y = (x >> i) | (x & ((1 << (i - 1)) - 1)); if (y != x) S.insert(SG(y)); else break; } int p = 0; while (!S.empty()) { int now = *S.begin(); if (now == p) p++; else if (now > p) return dp[x] = p; S.erase(S.begin()); } return dp[x] = p; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &A[i]); for (int i = 1; i <= N; i++) { int x = A[i]; for (int j = 2; j * j <= x; j++) { int k = 0; while (x % j == 0) { x /= j; k++; } if (k) K[j] |= (1 << (k - 1)); } if (x != 1) K[x] |= 1; } int tmp = 0; dp[0] = 0; for (auto i : K) tmp ^= SG(i.second); if (tmp == 0) printf( Arpa n ); else printf( Mojtaba n ); return 0; }
|
//======================================================================
//
// chacha_qr.v
// -----------
// Verilog 2001 implementation of the stream cipher ChaCha.
// This is the combinational QR logic as a separade module to allow
// us to build versions of the cipher with 1, 2, 4 and even 8
// parallel qr functions.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module chacha_qr(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] internal_a_prim;
reg [31 : 0] internal_b_prim;
reg [31 : 0] internal_c_prim;
reg [31 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// qr
//
// The actual quarterround function.
//----------------------------------------------------------------
always @*
begin : qr
reg [31 : 0] a0;
reg [31 : 0] a1;
reg [31 : 0] b0;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] c0;
reg [31 : 0] c1;
reg [31 : 0] d0;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // qr
endmodule // chacha_qr
//======================================================================
// EOF chacha_qr.v
//======================================================================
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output fml_stb,
input fml_ack,
input [63:0] fml_di,
/* Direct Cache Bus */
output dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
/* VGA pixel clock */
input vga_clk,
/* VGA signal pads */
output vga_psave_n,
output reg vga_hsync_n,
output reg vga_vsync_n,
output vga_sync_n,
output vga_blank_n,
output reg [7:0] vga_r,
output reg [7:0] vga_g,
output reg [7:0] vga_b,
inout vga_sda,
output vga_sdc,
output [1:0] clksel
);
/*
* Control interface
*/
wire vga_rst;
wire [10:0] hres;
wire [10:0] hsync_start;
wire [10:0] hsync_end;
wire [10:0] hscan;
wire [10:0] vres;
wire [10:0] vsync_start;
wire [10:0] vsync_end;
wire [10:0] vscan;
wire [fml_depth-1:0] baseaddress;
wire baseaddress_ack;
wire [17:0] nbursts;
vgafb_ctlif #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.vga_rst(vga_rst),
.hres(hres),
.hsync_start(hsync_start),
.hsync_end(hsync_end),
.hscan(hscan),
.vres(vres),
.vsync_start(vsync_start),
.vsync_end(vsync_end),
.vscan(vscan),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.nbursts(nbursts),
.vga_sda(vga_sda),
.vga_sdc(vga_sdc),
.clksel(clksel)
);
/*
* Generate signal data
*/
reg hsync_n;
reg vsync_n;
wire pixel_valid;
wire [15:0] pixel_fb;
wire pixel_ack;
wire [15:0] pixel;
wire fifo_full;
reg hactive;
reg vactive;
wire active = hactive & vactive;
assign pixel = active ? pixel_fb : 16'h0000;
wire generate_en;
reg [10:0] hcounter;
reg [10:0] vcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
hcounter <= 10'd0;
vcounter <= 10'd0;
hactive <= 1'b0;
hsync_n <= 1'b1;
vactive <= 1'b0;
vsync_n <= 1'b1;
end else begin
if(generate_en) begin
hcounter <= hcounter + 10'd1;
if(hcounter == 10'd0) hactive <= 1'b1;
if(hcounter == hres) hactive <= 1'b0;
if(hcounter == hsync_start) hsync_n <= 1'b0;
if(hcounter == hsync_end) hsync_n <= 1'b1;
if(hcounter == hscan) begin
hcounter <= 10'd0;
if(vcounter == vscan)
vcounter <= 10'd0;
else
vcounter <= vcounter + 10'd1;
end
if(vcounter == 10'd0) vactive <= 1'b1;
if(vcounter == vres) vactive <= 1'b0;
if(vcounter == vsync_start) vsync_n <= 1'b0;
if(vcounter == vsync_end) vsync_n <= 1'b1;
end
end
end
assign generate_en = ~fifo_full & (~active | pixel_valid);
assign pixel_ack = ~fifo_full & active & pixel_valid;
vgafb_pixelfeed #(
.fml_depth(fml_depth)
) pixelfeed (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(nbursts),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_di(fml_di),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.pixel_valid(pixel_valid),
.pixel(pixel_fb),
.pixel_ack(pixel_ack)
);
/*
* System clock to VGA clock domain crossing is
* acheived by an asynchronous FIFO.
*
* Bits 0-15 are RGB565 pixel data
* Bit 16 is negated Horizontal Sync
* Bit 17 is negated Verical Sync
*/
wire [17:0] fifo_do;
asfifo #(
.data_width(18),
.address_width(10)
) fifo (
.data_out(fifo_do),
.empty(),
.read_en(1'b1),
.clk_read(vga_clk),
.data_in({vsync_n, hsync_n, pixel}),
.full(fifo_full),
.write_en(generate_en),
.clk_write(sys_clk),
.rst(vga_rst)
);
/*
* Drive the VGA pads.
* RGB565 -> RGB888 color space conversion is also performed here
* by bit shifting and replicating the most significant bits of
* the input into the least significant bits of the output left
* undefined by the shifting.
*/
assign vga_sync_n = 1'b0; /* Sync-on-Green is not implemented */
assign vga_psave_n = 1'b1;
assign vga_blank_n = 1'b1;
always @(posedge vga_clk) begin
vga_vsync_n <= fifo_do[17];
vga_hsync_n <= fifo_do[16];
vga_r <= {fifo_do[15:11], fifo_do[15:13]};
vga_g <= {fifo_do[10:5], fifo_do[10:9]};
vga_b <= {fifo_do[4:0], fifo_do[4:2]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[100100]; int main() { int n, a, b, t, cn = 1; cin >> n; for (int i = 0; i < n; i++) { cin >> a; p[i] = a; } sort(p, p + n); int ans = 0; vector<int> v; for (int i = 0; i < n; i++) { int j = 0; for (j = 0; j < v.size(); j++) { if (p[i] >= v[j]) { v[j]++; break; } } if (j == v.size()) { v.push_back(1); } } cout << v.size() << endl; return 0; }
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module basys3_demo (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
// Input 100MHz clock through a BUFG
wire clk100;
BUFG bufg100 (.I(clk), .O(clk100));
// BUFGCE as divide by 2
reg clk50_ce;
always @(posedge clk100)
clk50_ce <= !clk50_ce;
wire clk50;
BUFGCE bufg50 (.I(clk), .CE(clk50_ce), .O(clk50));
// Reset generator
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk50) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
// A simple GPIO peripheral connected to LEDs
always @(posedge clk50) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
// The picosoc
picosoc_noflash soc (
.clk (clk50),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_FUNCTIONAL_V
|
module I2CTest(CLCK, SCL, SDA);
//I2C
input CLCK;
input SCL;
inout SDA;
parameter slaveaddress = 7'b1110010;
//Sample registers to send to requesting device
reg[2:0] valuecnt = 3'b011; //Count of bytes to be sent, send read value twice
//Synch SCL edge to the CPLD clock
reg [2:0] SCLSynch = 3'b000;
always @(posedge CLCK)
SCLSynch <= {SCLSynch[1:0], SCL};
wire SCL_posedge = (SCLSynch[2:1] == 2'b01);
wire SCL_negedge = (SCLSynch[2:1] == 2'b10);
//Synch SDA to the CPLD clock
reg [2:0] SDASynch = 3'b000;
always @(posedge CLCK)
SDASynch <= {SDASynch[1:0], SDA};
wire SDA_synched = SDASynch[0] & SDASynch[1] & SDASynch[2];
//Detect start and stop
reg start = 1'b0;
always @(negedge SDA)
start = SCL;
reg stop = 1'b0;
always @(posedge SDA)
stop = SCL;
//Set cycle state
reg incycle = 1'b0;
always @(posedge start or posedge stop)
if (start)
begin
if (incycle == 1'b0)
incycle = 1'b1;
end
else if (stop)
begin
if (incycle == 1'b1)
incycle = 1'b0;
end
//Address and incomming data handling
reg[7:0] bitcount = 0;
reg[6:0] address = 7'b0000000;
reg[7:0] datain = 8'b00000000;
reg rw = 1'b0;
reg addressmatch = 1'b0;
always @(posedge SCL_posedge or negedge incycle)
if (~incycle)
begin
//Reset the bit counter at the end of a sequence
bitcount = 0;
end
else
begin
bitcount = bitcount + 1;
//Get the address
if (bitcount < 8)
address[7 - bitcount] = SDA_synched;
if (bitcount == 8)
begin
rw = SDA_synched;
addressmatch = (slaveaddress == address) ? 1'b1 : 1'b0;
end
if ((bitcount > 9) & (~rw))
//Receive data (currently only one byte)
datain[17 - bitcount] = SDA_synched;
end
//ACK's and out going data
reg sdadata = 1'bz;
reg [2:0] currvalue = 0;
always @(posedge SCL_negedge)
//ACK's
if (((bitcount == 8) | ((bitcount == 17) & ~rw)) & (addressmatch))
begin
sdadata = 1'b0;
currvalue = 0;
end
//Data
else if ((bitcount >= 9) & (rw) & (addressmatch) & (currvalue < valuecnt))
begin
//Send Data
if (((bitcount - 9) - (currvalue * 9)) == 8)
begin
//Release SDA so master can ACK/NAK
sdadata = 1'bz;
currvalue = currvalue + 1;
end
else sdadata = datain[7 - ((bitcount - 9) - (currvalue * 9))]; //Modify this to send actual data, currently echoing incomming data valuecnt times
end
//Nothing (cause nothing tastes like fresca)
else sdadata = 1'bz;
assign SDA = sdadata;
endmodule
|
module displaydriver (
clk,
reset_,
digit_0,
digit_1,
digit_2,
digit_3,
segment_,
digit_enable_
);
input clk;
input reset_;
input [6:0] digit_0;
input [6:0] digit_1;
input [6:0] digit_2;
input [6:0] digit_3;
output [6:0] segment_;
output [3:0] digit_enable_;
// Theory of operation:
//
// Our hardware has four, seven-segment displays that are equipped with 7
// segment pins (segment_[6:0]) and 4 enable pins (digit_enable_[3:0]).
//
// Thus, we can't "drive" all four digits at once (as you might intuitively
// think--that would require 28 signals). Instead, we drive each digit for a
// fraction of a second, then move on to the next digit. This cycling occurs
// too quickly to be seen by the human eye.
//
// To make matters worse, we need to give the circuit some time to "cool off"
// between driving one digit and the next. If we don't, we'll see flickering
// and ghosting of the previous digit's value.
reg [7:0] refresh_ctr;
reg [1:0] digit;
// Multiplex the active digit's encoded value on the segment pins of the
// display
assign segment_ =
(digit == 2'd0) ? ~digit_3 :
(digit == 2'd1) ? ~digit_2 :
(digit == 2'd2) ? ~digit_1 :
~digit_0;
// Apply power to the display only during the middle half of the refresh
// cycle. This gives the circuit time to drain before we begin driving
// the next digit.
assign enable_ = !(refresh_ctr > 8'd64 && refresh_ctr < 8'd192);
// This four-bit vector indicates which digit on the display is currently
// being driven. Signal is active low; a 0 in the vector means "being drivin".
assign digit_enable_ = enable_ ? 4'b1111 :
(digit == 2'd0) ? 4'b1110 :
(digit == 2'd1) ? 4'b1101 :
(digit == 2'd2) ? 4'b1011 :
4'b0111;
// Counter that rolls over ever 256 clock cycles; used to cycle the digit
// to be driven
always@ (posedge clk or negedge reset_)
if (!reset_)
refresh_ctr <= 8'h00;
else
refresh_ctr <= refresh_ctr + 8'h01;
// Indicates which of the four displays are being driven. Cycles through each
// display, updated at each refresh pulse (ever 256 clock cycles).
always@ (posedge clk or negedge reset_)
if (!reset_)
digit <= 2'd0;
else if (refresh_ctr == 8'hff)
digit <= digit + 2'd1;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_mul_top.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_mul_top(/*AUTOARG*/
// Outputs
mul_exu_ack, mul_spu_ack, mul_spu_shf_ack, mul_data_out, so,
// Inputs
rclk, grst_l, arst_l, exu_mul_input_vld, exu_mul_rs1_data, exu_mul_rs2_data,
spu_mul_req_vld, spu_mul_acc, spu_mul_areg_shf, spu_mul_areg_rst,
spu_mul_op1_data, spu_mul_op2_data, spu_mul_mulres_lshft, si, se
);
input rclk;
input grst_l; // system reset
input arst_l; // async reset
input si; // scan in
input se; // scan enablen
input exu_mul_input_vld; // EXU multipler op request
input [63:0] exu_mul_rs1_data; // EXU multipler Op1
input [63:0] exu_mul_rs2_data; // EXU multipler Op2
input spu_mul_req_vld; // SPU multipler op request
input spu_mul_acc; // MAC Op: ACCUM += op1 * op2 if spu_mul_acc=1
// Bypass Op: Out = ACCUM * op1 if spu_mul_acc=0
input spu_mul_areg_shf; // Shift >> 64 ACCUM register
input spu_mul_areg_rst; // Reset of ACCUM register (136-bit)
input [63:0] spu_mul_op1_data; // SPU multiplier Op1
input [63:0] spu_mul_op2_data; // SPU multiplier Op2
input spu_mul_mulres_lshft;
output so; // scan_out
output mul_exu_ack; // ack signal for EXU mul operation
output mul_spu_ack; // ack signal for SPU MAC and Bypass mul operation
output mul_spu_shf_ack; // acl signal for ACCUM >> 64 operation
output [63:0] mul_data_out; // Shared output data for both EXU and SPU
wire acc_imm, acc_actc2, acc_actc3, acc_actc5, acc_reg_enb;
wire acc_reg_rst, acc_reg_shf;
wire byp_sel, byp_imm, spick, x2;
wire c0_act;
wire rst_l;
wire clk;
assign clk = rclk ;
dffrl_async rstff (
.din (grst_l),
.clk (clk),
.rst_l (arst_l),
.q (rst_l),
.se (se),
.si (),
.so ());
sparc_mul_cntl control (
.ecl_mul_req_vld (exu_mul_input_vld),
.spu_mul_req_vld (spu_mul_req_vld),
.spu_mul_acc (spu_mul_acc),
.spu_mul_areg_shf (spu_mul_areg_shf),
.spu_mul_areg_rst (spu_mul_areg_rst),
.spu_mul_mulres_lshft (spu_mul_mulres_lshft),
.c0_act (c0_act),
.spick (spick),
.byp_sel (byp_sel),
.byp_imm (byp_imm),
.acc_imm (acc_imm),
.acc_actc2 (acc_actc2),
.acc_actc3 (acc_actc3),
.acc_actc5 (acc_actc5),
.acc_reg_enb (acc_reg_enb),
.acc_reg_rst (acc_reg_rst),
.acc_reg_shf (acc_reg_shf),
.x2 (x2),
.mul_ecl_ack (mul_exu_ack),
.mul_spu_ack (mul_spu_ack),
.mul_spu_shf_ack (mul_spu_shf_ack),
.rst_l (rst_l),
.rclk (clk));
sparc_mul_dp dpath (
.ecl_mul_rs1_data (exu_mul_rs1_data),
.ecl_mul_rs2_data (exu_mul_rs2_data),
.spu_mul_op1_data (spu_mul_op1_data),
.spu_mul_op2_data (spu_mul_op2_data),
.valid (c0_act),
.spick (spick),
.byp_sel (byp_sel),
.byp_imm (byp_imm),
.acc_imm (acc_imm),
.acc_actc2 (acc_actc2),
.acc_actc3 (acc_actc3),
.acc_actc5 (acc_actc5),
.acc_reg_enb (acc_reg_enb),
.acc_reg_rst (acc_reg_rst),
.acc_reg_shf (acc_reg_shf),
.x2 (x2),
.mul_data_out (mul_data_out),
.rst_l (rst_l),
.si (),
.so (),
.se (se),
.rclk (clk));
endmodule // sparc_mul_top
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; ; vector<int> a(n); int m = 1000; for (__typeof(0) i = 0; i < n; i++) { cin >> a[i]; m = min(a[i], m); } int minc = 0; for (__typeof(0) i = 0; i < n; i++) minc += (a[i] == m); if (minc > n / 2) cout << Bob n ; else cout << Alice n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000; const double EPS = 1e-9; const double PI = 2 * acos(0.); const int N = 10; const int dx[] = {-2, -1, 1, 2, 2, 1, -1, -2}; const int dy[] = {-1, -2, -2, -1, 1, 2, 2, 1}; char a[N][N]; bool r[N]; int main() { int ans = 0; for (int i = 0; i < int(8); ++i) { for (int j = 0; j < int(8); ++j) scanf( %c , &a[i][j]); scanf( n ); } for (int i = 0; i < int(8); ++i) { bool flag = true; for (int j = 0; j < int(8); ++j) if (a[i][j] != B ) { flag = false; break; } if (flag) { r[i] = true; ++ans; } } for (int j = 0; j < int(8); ++j) { bool flag = false; for (int i = 0; i < int(8); ++i) if (a[i][j] == B && !r[i]) { flag = true; break; } if (flag) ++ans; } cout << ans << endl; return 0; }
|
`define ADDER_WIDTH 028
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_4_V
`define SKY130_FD_SC_LP__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main(){ ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); //freopen( input.txt , r ,stdin); //freopen( output.txt , w ,stdout); int T; cin>>T; for(int t=0;t<T;t++){ int n,k; cin>>n>>k; if(n==1&&k==1){cout<<0<<endl;continue;} if(k<=3){ if(k==2){ int m=n-1; cout<<m<<endl; cout<<1<< ; for(int i=3;i<=n;i++) cout<<i<< ; cout<<endl; }else{ if(k==1){ cout<<n-1<<endl; for(int i=2;i<=n;i++) cout<<i<< ; cout<<endl; } else{ cout<<n-2<<endl; cout<<1<< ; for(int i=4;i<=n;i++) cout<<i<< ; cout<<endl; } } }else{ if(k%2==0){ int m=n-k/2; cout<<m<<endl; for(int i=k/2;i<=n;i++) if(i!=k)cout<<i<< ; cout<<endl; }else{ int m=n-k/2-1; cout<<m<<endl; for(int i=k/2+1;i<=n;i++) if(i!=k)cout<<i<< ; cout<<endl; } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
buf buf0 (Y , pwrgood0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Anderson Ignacio da Silva.
// SPDX-License-Identifier: CC0-1.0
package test_pkg;
localparam [31:0] test_arr [4][4:0]
= '{
'{'h0000, 'h1000, 'h2000, 'h3000, 'h4000},
'{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF},
'{ 'd0, 'd0, 'd0, 'd0, 'd0},
'{ 'd0, 'd1, 'd2, 'd3, 'd4}
};
typedef struct packed{
logic [7:0] val_1;
logic [7:0] val_2;
} test_ret_t;
endpackage
module t import test_pkg::*; (clk);
input clk;
function automatic test_ret_t test_f(logic [31:0] val);
test_ret_t temp;
temp = test_ret_t'(0);
for (int i=0; i<5; i++) begin
if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin
temp.val_1 = test_arr[2][i][7:0];
temp.val_2 = test_arr[3][i][7:0];
end
end
return temp;
endfunction
test_ret_t temp;
logic [31:0] random;
int cyc;
bit [63:0] sum;
always @ (posedge clk) begin
cyc <= cyc + 1;
random <= {17'b0, cyc[3:0], 11'b0};
temp <= test_f(random);
`ifdef TEST_VERBOSE
$display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2);
`endif
if (cyc > 10 && cyc < 90) begin
sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
end
else if (cyc == 99) begin
$displayh(sum);
if (sum != 64'h74d34ea7a775f994) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <typename T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <typename T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <typename T> inline void println(T first) { print(first), putchar( n ); } template <typename T> inline void printsp(T first) { print(first), putchar( ); } template <class T, class T1> inline void print(T first, T1 second) { printsp(first), println(second); } template <class T, class T1, class T2> inline void print(T first, T1 second, T2 z) { printsp(first), printsp(second), println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int main() { int n; gn(n); if (n == 3) { puts( >vv ); puts( ^<. ); puts( ^.< ); puts( 1 3 ); return 0; } if (n == 5) { puts( >...v ); puts( v.<.. ); puts( ..^.. ); puts( >.... ); puts( ..^.< ); puts( 1 1 ); return 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == 1) { if (j == n) putchar( v ); else if (j <= n / 3) putchar( > ); else if (j - n / 3 & 1) putchar( > ); else putchar( . ); continue; } if (i == n) { if (j == 1) putchar( ^ ); else if (j > n - n / 3) putchar( < ); else if (n - n / 3 - j & 1) putchar( < ); else putchar( . ); continue; } if (j == 1) { putchar( ^ ); continue; } if (i & 1) { if (j == n) putchar( v ); else if (j <= n / 3) putchar( > ); else if (j - n / 3 & 1) putchar( > ); else putchar( . ); } else { if (j == 2) putchar( v ); else if (j > n - n / 3) putchar( < ); else if (j & 1) putchar( < ); else putchar( . ); } } puts( ); } puts( 1 1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &o, vector<T> &vec) { cout << [ ; for (int i = 0; i < ((int)(vec).size()); i++) { if (i) cout << , ; cout << vec[i]; } cout << ] ; return o; } template <typename T1, typename T2> ostream &operator<<(ostream &o, pair<T1, T2> &pair) { cout << ( << pair.first << , << pair.second << ) ; return o; } const long long MX = 312312; const long long SQMX = 1000; const long long MD = 1000000007; long long N; vector<long long> ip; bool isp[MX]; vector<long long> prime; long long sm[MX], tmp[MX]; long long C[MX]; long long fac[MX]; long long ps[MX]; long long fp(long long a, long long b) { if (!b) return 1 % MD; long long ret = fp(a * a % MD, b / 2); if (b & 1) ret = ret * a % MD; return ret; } inline long long rev(long long a) { return fp(a, MD - 2); } void pre() { fill(isp + 2, isp + MX, true); for (long long i = 0; i < MX; i++) { if (isp[i]) { prime.push_back(i); for (long long j = i + i; j < MX; j += i) { isp[j] = false; } } } fac[0] = 1; for (long long i = 1; i <= N - 1; i++) fac[i] = fac[i - 1] * i % MD; for (long long i = 0; i <= N - 1; i++) C[i] = fac[N - 1] * rev(fac[i]) % MD * rev(fac[N - i - 1]) % MD; for (long long i = 0; i <= N - 1; i++) { ps[i + 1] = ps[i] + C[i]; } } int32_t main() { cin >> N; pre(); ip.resize(N); for (long long i = 0; i < N; i++) { cin >> ip[i]; } long long ans = 0; for (long long i = 0; i < ((long long)(prime).size()); i++) { long long p = prime[i]; if (p > SQMX) break; fill(tmp, tmp + N, 0); for (long long j = 0; j < N; j++) { long long t = 0, &a = ip[j]; while (a % p == 0) { a /= p; t++; } tmp[j] = t; } sort(tmp, tmp + N); for (long long j = 0; j < N; j++) sm[j] += tmp[j]; } sort(ip.begin(), ip.end()); for (long long i = 0, j = 0; i < N; i = j) { while (ip[j] == ip[i]) j++; if (ip[i] == 1) continue; long long c = j - i; for (long long k = 0; k < c; k++) { sm[N - k - 1]++; } } for (long long j = 0; j < N; j++) { long long f1 = ps[j] - ps[0], f2 = ps[N] - ps[j + 1]; long long f = f1 - f2; f = (f + MD) % MD; ans += f * sm[j]; ans %= MD; } cout << ans << endl; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 3: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] data_out;
wire [ 3: 0] out_port;
wire [ 3: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 15;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, q, t, c; string s; long long inv[200007]; long long p[200007]; long long f[200007]; long long nq[200007]; long long mq[200007]; long long res[200007]; long long dp[200007]; vector<long long> que[200007]; long long fpow(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a % 1000000007; if (b % 2) return (a * fpow(a, b - 1)) % 1000000007; else { long long q = fpow(a, b / 2); return (q * q) % 1000000007; } } long long dziel(long long a, long long b) { return (a * fpow(b % 1000000007, 1000000007 - 2)) % 1000000007; } long long choose(long long a, long long b) { return dziel(f[a], f[b] * f[a - b]); } void solve(long long m) { memset(dp, 0, sizeof dp); dp[m] = 1; long long dwumian = 1; for (long long i = m + 1; i <= 1e5; ++i) { dwumian = (((dwumian * (i - 1)) % 1000000007) * inv[i - m]) % 1000000007; dp[i] = (26 * dp[i - 1] + dwumian * p[i - m]) % 1000000007; } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); f[0] = 1; p[0] = 1; for (long long i = 1; i < 200007; ++i) { f[i] = (f[i - 1] * i) % 1000000007; p[i] = (25 * p[i - 1]) % 1000000007; inv[i] = fpow(i, 1000000007 - 2); } cin >> q >> s; m = s.size(); for (long long i = 1; i <= q; ++i) { cin >> t; if (t == 1) { cin >> s; m = s.size(); } else { cin >> n; nq[++c] = n; mq[c] = m; que[m].push_back(c); } } for (long long i = 1; i <= 1e5; ++i) { if (!que[i].empty()) solve(i); for (auto it : que[i]) res[it] = dp[nq[it]]; } for (long long i = 1; i <= c; ++i) { cout << res[i] << n ; } }
|
#include <bits/stdc++.h> int ___read_tmp; using namespace std; int fwt[1010000]; int query(int sz) { int sum = 0; sz++; while (sz > 0) { sum += fwt[sz]; sz -= sz & (-sz); } return sum; } void upd(int id, int add) { id++; for (; id < 1010000; id += (id & (-id))) { fwt[id] += add; } } int range(int from, int to) { if (to < from) return 0; int tmp = query(to); if (from > 0) tmp -= query(from - 1); return tmp; } int main() { int n, k; scanf( %d %d , &n, &k); k = min(k, n - k); unsigned long long res = 1; int curr = 0; for (int i = (0); i < (n); i++) { if (curr + k <= n) { res += range(curr + 1, curr + k - 1) + 1; } else { res += range(curr + 1, n - 1) + range(0, (curr + k) % n - 1) + 1; } printf( %I64d , res); upd(curr, 1); curr = (curr + k) % n; upd(curr, 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, ans = 1 << 30; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= k - 1; i++) if (n % i == 0) ans = min(ans, k * n / i + i); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 300000; int x[N][2]; int ans[N]; bool hear[N]; vector<pair<int, int> > G[N]; int color[N]; void dfs1(int s) { color[s] = 1; for (int i = 0; i < (int)G[s].size(); i++) { int v = G[s][i].first; if (color[v] == 0) { if (G[s][i].second > 0) { ans[G[s][i].second] = 1; } else { ans[-G[s][i].second] = 0; } dfs1(v); } } color[s] = 2; } pair<int, int> cyc; void dfs2(int s, int per = -1) { color[s] = 1; for (int i = 0; i < (int)G[s].size(); i++) { int v = G[s][i].first; if (color[v] == 0) { dfs2(v, abs(G[s][i].second)); } if ((color[v] == 1) && (per != abs(G[s][i].second))) { cyc.first = s; cyc.second = i; } } color[s] = 2; } int color1[N]; void dfs3(int s, int per) { color1[s] = 1; for (int i = 0; i < (int)G[s].size(); i++) { int v = G[s][i].first; if (abs(G[s][i].second) == per) { continue; } if (color1[v] == 0) { ans[abs(G[s][i].second)] = (G[s][i].second > 0 ? 1 : 0); dfs3(v, abs(G[s][i].second)); } } color1[s] = 2; } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { int k; scanf( %d , &k); for (int j = 0; j < k; j++) { int r; scanf( %d , &r); if (x[abs(r)][0] == 0) { x[abs(r)][0] = i * (r > 0 ? 1 : -1); } else { x[abs(r)][1] = i * (r > 0 ? 1 : -1); } } } for (int i = 1; i <= m; i++) { if ((x[i][0] >= 0) && (x[i][1] >= 0)) { ans[i] = 1; hear[x[i][0]] = 1; hear[x[i][1]] = 1; } else if ((x[i][0] <= 0) && (x[i][1] <= 0)) { ans[i] = 0; hear[-x[i][0]] = 1; hear[-x[i][1]] = 1; } else { int v1 = abs(x[i][0]); int v2 = abs(x[i][1]); G[v1].push_back(make_pair(v2, i * (x[i][1] > 0 ? 1 : -1))); G[v2].push_back(make_pair(v1, i * (x[i][0] > 0 ? 1 : -1))); } } for (int i = 1; i <= n; i++) { if ((hear[i] == 1) && (color[i] == 0)) { dfs1(i); } } for (int i = 1; i <= n; i++) { if (color[i] == 0) { cyc.first = 0; dfs2(i); if (cyc.first == 0) { cout << NO << endl; return 0; } else { int s = cyc.first; int j = cyc.second; ans[abs(G[s][j].second)] = (G[s][j].second > 0 ? 1 : 0); dfs3(G[s][j].first, abs(G[s][j].second)); } } } cout << YES << endl; for (int i = 1; i <= m; i++) { cout << ans[i]; } cout << endl; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:22:21 06/07/2015
// Design Name:
// Module Name: coreid
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module coreid (
input wire clk,
input wire rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire regaddr_changed,
output reg [7:0] dout,
output wire oe_n
);
reg [7:0] text[0:15];
integer i;
initial begin
for (i=0;i<16;i=i+1)
text[i] = 8'h00;
text[ 0] = "T";
text[ 1] = "2";
text[ 2] = "4";
text[ 3] = "-";
text[ 4] = "0";
text[ 5] = "7";
text[ 6] = "1";
text[ 7] = "1";
text[ 8] = "2";
text[ 9] = "0";
text[10] = "1";
text[11] = "6";
end
reg [3:0] textindx = 4'h0;
reg reading = 1'b0;
assign oe_n = !(zxuno_addr == 8'hFF && zxuno_regrd==1'b1);
always @(posedge clk) begin
if (rst_n == 1'b0 || (regaddr_changed==1'b1 && zxuno_addr==8'hFF)) begin
textindx <= 4'h0;
reading <= 1'b0;
end
else if (oe_n==1'b0) begin
reading <= 1'b1;
end
else if (reading == 1'b1 && oe_n==1'b1) begin
reading <= 1'b0;
textindx <= textindx + 1;
end
dout <= text[textindx];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, in[5100], st[5100], f[5100], ans = 9999999999999; signed main() { cin >> n; for (long long i = 1; i <= n; i++) { cin >> in[i]; } memset(f, 0x7f, sizeof(f)); memcpy(st, in, sizeof(in)); sort(st + 1, st + n + 1); for (long long i = 1; i <= n; i++) f[i] = 0; for (long long i = 1; i <= n; i++) { for (long long o = 1; o <= n; o++) { f[o] = min(f[o - 1], f[o] + abs(in[i] - st[o])); } } for (long long i = 1; i <= n; i++) { ans = min(ans, f[i]); } cout << ans; }
|
module top_tb;
reg clk_i = 0;
reg rst_i = 1;
reg [4:0] rx_i_ctr = 0;
reg [19:0] rx_tmp = 20'b10100011101010010000;
reg tmp_rx_bit = 1;
wire clk_uart_rx, clk_uart_tx;
wire [7:0] led_o;
wire rs232_tx_o;
wire rs232_rx_i;
initial
begin
$dumpfile("./build/iverilog/uart.vcd");
$dumpvars(0,top_tb);
# 1250 rst_i <= 0;
# 200000 $finish;
end
top tb (
.ice_clk_i (clk_i),
.rstn_i(rst_i),
.rs232_rx_i(rs232_rx_i),
.led_o (led_o),
.rs232_tx_o(rs232_tx_o)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
always #1 clk_i = ~clk_i;
assign rs232_rx_i =tmp_rx_bit;
always @ (posedge (clk_uart_tx))
begin
tmp_rx_bit <= rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
end
always @ (posedge clk_uart_tx)
begin
if (rx_i_ctr == 19 | rst_i)
begin
rx_i_ctr <= 0;
end
else
begin
rx_i_ctr <= rx_i_ctr + 1;
end
end
endmodule // top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_TB_V
`define SKY130_FD_SC_MS__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_1_V
`define SKY130_FD_SC_MS__A21BOI_1_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; map<string, int> m; int ans = 0; vector<string> a, b; for (int i = 0; i < n; i++) { string s; cin >> s; if (m[s] != 0) ans++; m[s]++; b.push_back(s); } for (int i = 0; i < n; i++) { string s; s = b[i]; if (m[s] != 1) { m[s]--; while (true) { if (s[3] == 9 ) s[3] = 0 ; else s[3] = ((int)s[3] + 1); if (m[s] == 0) { m[s]++; a.push_back(s); break; } } } else { a.push_back(s); } } cout << ans << endl; for (int i = 0; i < a.size(); i++) { cout << a[i] << endl; } } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// wb_bus_writer
//
// WB Bus Master device to send a sequence of single-word transactions
// based on a list in a RAM or ROM (FASM interface)
// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]}
// continues until it gets an all-1s entry
module wb_bus_writer (input start,
output done,
output reg [15:0] rom_addr,
input [47:0] rom_data,
// WB Master Interface, don't need wb_dat_i
input wb_clk_i,
input wb_rst_i,
output [31:0] wb_dat_o,
input wb_ack_i,
output [15:0] wb_adr_o,
output wb_cyc_o,
output [3:0] wb_sel_o,
output wb_stb_o,
output wb_we_o
);
`define IDLE 0
`define READ 1
reg [3:0] state;
assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s
always @(posedge wb_clk_i)
if(wb_rst_i)
begin
rom_addr <= #1 0;
state <= #1 0;
end
else if(start)
begin
rom_addr <= #1 0;
state <= #1 `READ;
end
else if((state == `READ) && wb_ack_i)
if(done)
state <= #1 `IDLE;
else
rom_addr <= #1 rom_addr + 1;
assign wb_dat_o = rom_data[31:0];
assign wb_adr_o = rom_data[47:32];
assign wb_sel_o = 4'b1111; // All writes are the full 32 bits
assign wb_cyc_o = !done & (state != `IDLE);
assign wb_stb_o = !done & (state != `IDLE);
assign wb_we_o = !done & (state != `IDLE);
endmodule // wb_bus_writer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_0_V
`define SKY130_FD_SC_LP__A221OI_0_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_0 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_0_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> compos; int complement_component(vector<vector<int>> &g) { int n = g.size(), ans = 0; set<int> S; for (int i = 0; i < n; ++i) S.insert(i); while (S.size()) { ++ans; int theCompo = 0; queue<int> q; q.push(*S.begin()); S.erase(S.begin()); compos.push_back(vector<int>{}); while (q.size()) { int u = q.front(); q.pop(); compos.back().push_back(u); if (g[u].size()) { while (S.size() and *S.begin() < g[u][0]) { q.push(*S.begin()); S.erase(S.begin()); } int it = 0; while (S.size() and it < g[u].size()) { auto cur = S.upper_bound(g[u][it]); while (cur != S.end() and (it + 1 == g[u].size() or *cur < g[u][it + 1])) { q.push(*cur), S.erase(cur); cur = S.upper_bound(g[u][it]); } ++it; } } else { compos.back() = vector<int>(n); iota(compos.back().begin(), compos.back().end(), 0); return 1; } } } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int N, M, u, v; cin >> N >> M; vector<vector<int>> g(N); while (M--) { cin >> u >> v, --u, --v; g[u].push_back(v), g[v].push_back(u); } for (int i = 0; i < N; ++i) sort(g[i].begin(), g[i].end()); cout << complement_component(g) << n ; sort(compos.begin(), compos.end()); for (auto &compo : compos) { cout << compo.size() << ; for (int i = 0; i < compo.size(); ++i) cout << compo[i] + 1 << n [i == compo.size() - 1]; } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 10:06:06 01/18/2017
// Design Name: retnuoCl
// Module Name: tb_retnuoCl.v
// Project Name: spongent
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: retnuoCl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_retnuoCl;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
retnuoCl uut (
.lfsr(lfsr),
.out(out)
);
initial begin
// Initialize Inputs
lfsr = 16'b0000000000000000;
$display("set lsfr to : %d", lfsr);
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
while (lfsr < 16'b1111111111111111)
begin
$display ("lfsr=%d, out=%b, (hex): %h", lfsr, out, out);
#1;
lfsr = lfsr + 1;
#1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_4TO2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int n; long long r, a[(1LL << 20)], x, y; int main() { scanf( %d %I64d , &n, &r); long long sum = 0; double qpw = 1; for (int i = 1; i <= n; ++i) qpw *= 2; for (int i = 1; i <= qpw; ++i) { scanf( %I64d , &a[i]); sum += a[i]; } printf( %.6f n , sum * 1.0 / qpw); double ans = 0; while (r--) { scanf( %I64d %I64d , &x, &y); sum += (y - a[x + 1]); a[x + 1] = y; ans = sum * 1.0 / qpw; printf( %.6f n , ans); } return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:08:01 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_timer_0_0_stub.v
// Design : zqynq_lab_1_design_axi_timer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_timer,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(capturetrig0, capturetrig1, generateout0,
generateout1, pwm0, interrupt, freeze, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp,
s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rvalid, s_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="capturetrig0,capturetrig1,generateout0,generateout1,pwm0,interrupt,freeze,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[4:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[4:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready" */;
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
input s_axi_aclk;
input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule
|
`include "timescale.v"
module orpsoc_tb;
vlog_tb_utils vlog_tb_utils0();
////////////////////////////////////////////////////////////////////////
//
// JTAG VPI interface
//
////////////////////////////////////////////////////////////////////////
wire tms;
wire tck;
wire tdi;
wire tdo;
reg enable_jtag_vpi;
initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi");
jtag_vpi jtag_vpi0
(
.tms (tms),
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.enable (enable_jtag_vpi),
.init_done (orpsoc_tb.dut.wb_rst)
);
////////////////////////////////////////////////////////////////////////
//
// ELF program loading
//
////////////////////////////////////////////////////////////////////////
integer mem_words;
integer i;
reg [31:0] mem_word;
reg [1023:0] elf_file;
initial begin
if($value$plusargs("elf_load=%s", elf_file)) begin
$elf_load_file(elf_file);
mem_words = $elf_get_size/4;
$display("Loading %d words", mem_words);
for(i=0; i < mem_words; i = i+1)
orpsoc_tb.dut.wb_bfm_memory0.mem[i] = $elf_read_32(i*4);
end else
$display("No ELF file specified");
end
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation
//
////////////////////////////////////////////////////////////////////////
reg syst_clk = 1;
reg syst_rst = 1;
always #5 syst_clk <= ~syst_clk;
initial #100 syst_rst <= 0;
////////////////////////////////////////////////////////////////////////
//
// mor1kx monitor
//
////////////////////////////////////////////////////////////////////////
mor1kx_monitor #(.LOG_DIR(".")) i_monitor();
////////////////////////////////////////////////////////////////////////
//
// DUT
//
////////////////////////////////////////////////////////////////////////
orpsoc_top
#(.UART_SIM (1))
dut
(.wb_clk_i (syst_clk),
.wb_rst_i (syst_rst),
.tms_pad_i (tms),
.tck_pad_i (tck),
.tdi_pad_i (tdi),
.tdo_pad_o (tdo));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100000; const int inf = (int)1e9 + 1; const long long big = (long long)1e18 + 1; const int P = 239; const int MOD = (int)1e9 + 7; const int MOD1 = (int)1e9 + 9; const double eps = 1e-9; const double pi = atan2(0, -1); const int ABC = 26; vector<int> g[N]; bool used[N]; vector<int> comp; void dfs(int u) { used[u] = true; comp.push_back(u); for (int v : g[u]) if (!used[v]) dfs(v); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(20); int n, A, B; cin >> n >> A >> B; int a[n]; map<int, int> mapa; for (int i = 0; i < n; i++) { cin >> a[i]; mapa[a[i]] = i; } for (int i = 0; i < n; i++) { if (mapa.find(A - a[i]) != mapa.end()) g[i].push_back(mapa[A - a[i]]); if (mapa.find(B - a[i]) != mapa.end()) g[i].push_back(mapa[B - a[i]]); } int ans[n]; for (int i = 0; i < n; i++) if (!used[i]) { comp.clear(); dfs(i); int mask = 3; for (int j : comp) { int cur = 0; if (mapa.find(A - a[j]) != mapa.end()) cur |= 1; if (mapa.find(B - a[j]) != mapa.end()) cur |= 2; mask &= cur; } if (mask == 0) { cout << NO n ; return 0; } if (mask & 1) { for (int j : comp) ans[j] = 0; } else { for (int j : comp) ans[j] = 1; } } cout << YES n ; for (int i = 0; i < n; i++) cout << ans[i] << ; cout << n ; return 0; }
|
module register_file (clk, we, dval, s1, s2, d, s1val, s2val, pc);
parameter NUM_REGISTERS = 32;
// input
input clk;
input we;
input [31:0] dval;
input [5:0] s1;
input [5:0] s2;
input [4:0] d;
input [31:0] pc;
// output
output [31:0] s1val;
output [31:0] s2val;
// local
reg [31:0] s1val = 0;
reg [31:0] s2val = 0;
reg [31:0] registers[0:NUM_REGISTERS-1];
reg [31:0] dval_tmp = 0;
reg [4:0] d_tmp = 0;
reg we_tmp = 0;
wire [31:0] pc;
integer k;
// comb
initial
begin
for (k = 0; k < NUM_REGISTERS; k = k + 1)
begin
if(k == 29)
begin
registers[k] = 32'h8002_03FF; // data memory size
end
else if(k == 31)
begin
registers[k] = 32'hDEAD_BEEF; // magic number to detect return condition
end
else
begin
registers[k] = 0;
end
end
end
always @(clk or s1 or s2)
begin
s1val = (s1 == 0 ? 0 : s1 == 32 ? pc : registers[s1[4:0]]);
s2val = (s2 == 0 ? 0 : s2 == 32 ? pc : registers[s2[4:0]]);
end
// proc
always @(negedge clk)
begin
if (we == 1)
begin
if(d != 0)
begin
registers[d] = dval;
if(s1 == d)
begin
s1val = (s1 == 0 ? 0 : s1 == 32 ? pc : registers[s1]);
end
if(s2 == d)
begin
s2val = (s2 == 0 ? 0 : s1 == 32 ? pc : registers[s2]);
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool letras[26]; int main() { list<char> kbd; list<char>::iterator i; int t, j; bool foundKbd; string s; for (cin >> t; t > 0; t--) { foundKbd = true; cin >> s; for (j = 0; j < s.size() && foundKbd; j++) { if (kbd.size() == 0) { kbd.push_back(s.at(j)); letras[s.at(j) - a ] = true; } else if (letras[s.at(j) - a ] == false) { for (i = kbd.begin(); i != kbd.end() && *i != s.at(j - 1); i++) ; if (i == kbd.begin()) { kbd.push_front(s.at(j)); letras[s.at(j) - a ] = true; } else if (i == --kbd.end()) { kbd.push_back(s.at(j)); letras[s.at(j) - a ] = true; } else foundKbd = false; } else { for (i = kbd.begin(); i != kbd.end() && *i != s.at(j - 1); i++) ; if (*(++i) == s.at(j)) --i; else if (*(--(--i)) != s.at(j)) foundKbd = false; } } if (foundKbd) { cout << YES << endl; for (j = 0; j < 26; j++) if (letras[j] == false) kbd.push_back( a + j); for (i = kbd.begin(); i != kbd.end(); i++) cout << *i; cout << endl; } else cout << NO << endl; kbd.clear(); for (j = 0; j < 26; j++) letras[j] = false; } }
|
#include <bits/stdc++.h> using namespace std; int x[110], y[110], n, epsilon, k; double dist[110], p[110], mem[110][110]; double solve(int idx, int k) { if (k == 0) return 1; if (idx == n) return 0; double& res = mem[idx][k]; if (res != -1) return res; res = p[idx] * solve(idx + 1, k - 1); res += (1 - p[idx]) * solve(idx + 1, k); return res; } bool binary(double r) { for (int i = 0; i < n; i++) { if (dist[i] <= r) p[i] = 1; else p[i] = exp(1 - dist[i] * dist[i] / (r * r)); } for (int i = 0; i < n + 1; i++) for (int j = 0; j < k + 1; j++) mem[i][j] = -1; double res = solve(0, k); return ((1 - res) * 1000 <= epsilon); } int main() { ios::sync_with_stdio(false); int x0, y0; cin >> n >> k >> epsilon; cin >> x0 >> y0; for (int i = 0; i < n; i++) cin >> x[i] >> y[i]; for (int i = 0; i < n; i++) dist[i] = hypot(x[i] - x0, y[i] - y0); double mid, low = 0, high = 1000000; while (abs(low - high) > 1e-9) { mid = (low + high) / 2; if (binary(mid)) high = mid; else low = mid; } printf( %.15lf n , (low + high) / 2); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2016 01:13:48 PM
// Design Name:
// Module Name: Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Add_Subt
#(parameter SWR=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR-1:0] Data_Result_o,
//output wire [SWR-1:0] P_o,
//output wire [SWR-1:1] Cn_o,
output wire FSM_C_o
);
wire [SWR-1:0] Data_B;
wire [SWR:0] S_to_D;
wire [SWR-1:0] P_to_D;
wire [SWR-1:1] C_to_D;
wire Co_to_D;
//wire Co_to_gate;
/*
/////////////////////////////////////////7
genvar j;
for (j=0; j<SWR; j=j+1)begin
assign Data_B[j] = PreData_B_i[j] ^ Add_Sub_op_i;
end
Full_Adder_PG #(.SWR(SWR)) AS_Module(
.clk(clk),
.rst(rst),
.Op_A_i(Data_A_i),
.Op_B_i(Data_B),
.C_i(Add_Sub_op_i), //Carry in
.S_o(S_to_D), // Solution out
.Cn_o(C_to_D),
.C_o(Co_to_gate), //Carry out
.P_o(P_o) //Propagate (for LZA)
);*/
add_sub_carry_out #(.W(SWR)) Sgf_AS (
.op_mode(Add_Sub_op_i),
.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D)
);
assign Co_to_D = S_to_D[SWR] & ~Add_Sub_op_i;
RegisterAdd #(.W(SWR)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR-1:0]),
.Q (Data_Result_o)
);
/*RegisterAdd #(.W(SWR)) P_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (P_to_D),
.Q (P_o)
);*/
/*RegisterAdd #(.W(SWR-1)) C_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (C_to_D),
.Q (Cn_o)
);*/
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR]),
.Q (FSM_C_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { return (a.second < b.second); } inline long long mx(long long a, long long b) { if (a > b) return a; else return b; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long solve(long long x, long long n) { long long r; if (x <= n) r = (x - 1) / 2; else r = (n - (x - n) + 1) / 2; if (r > 0) return r; else return 0; } int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long i; for (i = 9; i <= n + n - 1; i = i * 10 + 9) ; long long k = i / 10; long long ans = 0; for (long long i = 0; i <= 9; i++) { if (i * (k + 1) + k <= n + n - 1) ans += solve(i * (k + 1) + k, n); else break; } cout << ans << n ; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire myevent; // From test of Test.v
wire myevent_pending; // From test of Test.v
wire [1:0] state; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.state (state[1:0]),
.myevent (myevent),
.myevent_pending (myevent_pending),
// Inputs
.clk (clk),
.reset (reset));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, myevent_pending,myevent,state};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
state, myevent, myevent_pending,
// Inputs
clk, reset
);
input clk;
input reset;
output [1:0] state;
output myevent;
output myevent_pending;
reg [5:0] count = 0;
always @ (posedge clk)
if (reset) count <= 0;
else count <= count + 1;
reg myevent = 1'b0;
always @ (posedge clk)
myevent <= (count == 6'd27);
reg myevent_done;
reg hickup_ready;
reg hickup_done;
localparam STATE_ZERO = 0;
localparam STATE_ONE = 1;
localparam STATE_TWO = 2;
reg [1:0] state = STATE_ZERO;
reg state_start_myevent = 1'b0;
reg state_start_hickup = 1'b0;
reg myevent_pending = 1'b0;
always @ (posedge clk) begin
state <= state;
myevent_pending <= myevent_pending || myevent;
state_start_myevent <= 1'b0;
state_start_hickup <= 1'b0;
case (state)
STATE_ZERO:
if (myevent_pending) begin
state <= STATE_ONE;
myevent_pending <= 1'b0;
state_start_myevent <= 1'b1;
end else if (hickup_ready) begin
state <= STATE_TWO;
state_start_hickup <= 1'b1;
end
STATE_ONE:
if (myevent_done)
state <= STATE_ZERO;
STATE_TWO:
if (hickup_done)
state <= STATE_ZERO;
default:
; /* do nothing */
endcase
end
reg [3:0] myevent_count = 0;
always @ (posedge clk)
if (state_start_myevent)
myevent_count <= 9;
else if (myevent_count > 0)
myevent_count <= myevent_count - 1;
initial myevent_done = 1'b0;
always @ (posedge clk)
myevent_done <= (myevent_count == 0);
reg [4:0] hickup_backlog = 2;
always @ (posedge clk)
if (state_start_myevent)
hickup_backlog <= hickup_backlog - 1;
else if (state_start_hickup)
hickup_backlog <= hickup_backlog + 1;
initial hickup_ready = 1'b1;
always @ (posedge clk)
hickup_ready <= (hickup_backlog < 3);
reg [3:0] hickup_count = 0;
always @ (posedge clk)
if (state_start_hickup)
hickup_count <= 10;
else if (hickup_count > 0)
hickup_count <= hickup_count - 1;
initial hickup_done = 1'b0;
always @ (posedge clk)
hickup_done <= (hickup_count == 1);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1ll << 18; long long a, b, top, now; queue<long long> q; map<long long, int> mp; long long rev(long long x) { long long y = 0; while (x != 0) { y = (y << 1) | (x & 1); x >>= 1; } return y; } void push(long long &x) { if (x > b && rev(x) > b) return; if (mp.find(x) == mp.end()) { q.push(x); mp[x] = 1; } } string solve() { if (a == b) return YES ; q.push(a); mp[a] = 1; while (!q.empty()) { top = q.front(); q.pop(); now = rev(top << 1); if (now == b) return YES ; push(now); now = rev((top << 1) | 1); if (now == b) return YES ; push(now); } return NO ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> a >> b; cout << solve() << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n, m, z; std::cin >> n >> m >> z; int counter = 0; for (int i = 1; i * n <= z; i++) { if ((i * n) % m == 0) counter++; } std::cout << counter; return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire [3:0] sw,
input wire [3:0] btn,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btn,
sw}),
.out({btn_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led0_r(led0_r),
.led0_g(led0_g),
.led0_b(led0_b),
.led1_r(led1_r),
.led1_g(led1_g),
.led1_b(led1_b),
.led2_r(led2_r),
.led2_g(led2_g),
.led2_b(led2_b),
.led3_r(led3_r),
.led3_g(led3_g),
.led3_b(led3_b),
.led4(led4),
.led5(led5),
.led6(led6),
.led7(led7),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; long long arr[100005]; int c5; int find(long long a, long long b, long long c) { long long arr[4]; arr[0] = a; arr[1] = b; arr[2] = c; sort(arr, arr + 3); if (arr[0] < arr[1] && arr[1] < arr[2]) return 6; else if (arr[0] == arr[1] && arr[1] < arr[2]) return 3; else if (arr[0] < arr[1] && arr[1] == arr[2]) return 3; else return 1; } int main() { cin >> n; if (n % 6 != 0) { printf( 0 n ); return 0; } n /= 3; for (long long x = 1; x * x <= n; x++) { if (n % x == 0) { arr[c5++] = x; if (x * x != n) arr[c5++] = n / x; } } sort(arr, arr + c5); long long x, y, z; int ans = 0, cnt = 0; long long a, b, c; for (int i = 0; i < c5; i++) { x = arr[i]; for (int j = i; j < c5 && arr[i] * arr[j] * arr[j] <= n; j++) { if (n % (arr[i] * arr[j]) == 0) { y = arr[j]; z = n / (arr[i] * arr[j]); if (x <= y <= z) { if (x - y + z > 0 && y - x + z > 0 && y - z + x > 0 && (x - y + z) % 2 == 0) { cnt++; a = (x - y + z) / 2; b = (y - x + z) / 2; c = (y - z + x) / 2; ans += find(a, b, c); } } } } } printf( %d n , ans); return 0; }
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dumpvars.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
// $Log: dumpvars.v,v $
// Revision 1.2 2007/12/06 02:31:10 stevewilliams
// Clean up work files (caryr)
//
// Revision 1.1 2001/07/08 02:56:25 sib4
// Test for PR#174
//
//
// Test if $dumpvars() accepts non-hierachical names
module dumptest;
submod u1(0);
submod u2(1);
initial
begin
$dumpfile("work/dumptest.vcd");
$dumpvars(0, dumptest.u1);
$dumpvars(0, u2);
$display("PASSED");
$finish;
end
endmodule
module submod (b);
input b;
reg a;
initial a = b;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; long long a[100005][4]; set<long long> se; map<long long, long long> mp; pair<long long, long long> ve[400005][5]; pair<long long, long long> pe[400005][5]; long long prim(long long i) { for (long long j = 2; j * j <= i; j++) { if (i % j == 0) return 0; } return 1; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<long long> prime; for (long long i = 2; i < 201; i++) { if (prim(i)) prime.push_back(i); } cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1] >> a[i][2] >> a[i][3]; se.insert(a[i][0]); se.insert(a[i][1]); se.insert(a[i][2]); se.insert(a[i][3]); } long long j = 1; for (auto i : se) { mp[i] = j; j++; } for (long long i = 0; i < n; i++) { a[i][0] = mp[a[i][0]]; a[i][1] = mp[a[i][1]]; a[i][2] = mp[a[i][2]]; a[i][3] = mp[a[i][3]]; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < 5; j++) { ve[a[i][0]][j].first += i % prime[j]; ve[a[i][2]][j].second += i % prime[j]; pe[a[i][1]][j].first += i % prime[j]; pe[a[i][3]][j].second += i % prime[j]; } } for (long long i = 1; i < 400005; i++) for (long long j = 0; j < 5; j++) { ve[i][j].first += ve[i - 1][j].first; ve[i][j].second += ve[i - 1][j].second; pe[i][j].first += pe[i - 1][j].first; pe[i][j].second += pe[i - 1][j].second; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < 5; j++) { if (ve[a[i][1]][j].first - pe[a[i][0] - 1][j].first != ve[a[i][3]][j].second - pe[a[i][2] - 1][j].second) { cout << NO n ; return 0; } } } cout << YES n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; str[0] = toupper(str[0]); cout << str; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; char a[105][105]; int n, m; bool u[105][105]; int main() { memset(u, false, sizeof(u)); scanf( %d %d n , &n, &m); for (int i = 0; i < n; i++, scanf( n )) for (int j = 0; j < m; j++) scanf( %c , &a[i][j]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { for (int ix = 0; ix < m; ix++) if (ix != j && a[i][ix] == a[i][j]) u[i][ix] = u[i][j] = true; for (int ix = 0; ix < n; ix++) if (ix != i && a[ix][j] == a[i][j]) u[ix][j] = u[i][j] = true; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (!u[i][j]) putchar(a[i][j]); } return 0; }
|
#include <bits/stdc++.h> int cmp(const void* a, const void* b); int main() { long long t = 1; while (t--) { long long n, n1, n2; scanf( %lld%lld%lld , &n, &n1, &n2); long long arr[n]; for (long long i = 0; i < n; i++) { scanf( %lld , &arr[i]); } qsort(arr, n, sizeof(arr[0]), cmp); double s1 = 0, s2 = 0; if (n2 < n1) { long long x = n2; n2 = n1; n1 = x; } if (1) { for (long long i = 0; i < n1; i++) s1 += arr[i]; for (long long i = n1; i < n1 + n2; i++) s2 += arr[i]; } printf( %f n , s1 / n1 + s2 / n2); } return 0; } int cmp(const void* a, const void* b) { return (*(int*)b - *(int*)a); }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> primes; void SOE(long long int n) { primes.erase(primes.begin(), primes.end()); bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long int i = p * p; i <= n; i += p) prime[i] = false; } } for (long long int p = 2; p <= n; p++) if (prime[p]) { primes.push_back(p); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long int i, c = 0, j, k, t, f = 0, q, n, f1 = 0, y, x, m, l = 0, r, p; string s, s1, s2; cin >> t; while (t--) { cin >> n; long long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } a[0] < a[n - 1] ? cout << YES n : cout << NO n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 1e2 + 10; vector<long long> g[N]; void dfs(long long node, long long par, long long dd, vector<long long>& fre) { fre[dd]++; for (auto x : g[node]) if (x != par) dfs(x, node, dd + 1, fre); } long long n, k; long long get(vector<long long>& arr) { vector<long long> cur(k + 1, 0); cur[0] = 1; for (auto x : arr) { for (long long i = k; i >= 1; i--) { cur[i] += cur[i - 1] * x; cur[i] %= MOD; } } return cur[k]; } long long solve(long long x) { long long sz = g[x].size(); vector<vector<long long> > go(sz, vector<long long>(n + 1, 0)); for (long long i = 0; i < sz; i++) dfs(g[x][i], x, 1, go[i]); long long res = 0; for (long long i = 1; i <= n; i++) { vector<long long> arr; for (auto v : go) if (v[i] > 0) arr.push_back(v[i]); res += get(arr); res %= MOD; } return res; } void solve() { cin >> n >> k; long long u, v; for (long long i = 0; i < n - 1; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } long long res = 0; if (k == 2) { res = (n * (n - 1)) / 2; res %= MOD; } else { for (long long i = 1; i <= n; i++) { res += solve(i); res %= MOD; } } cout << res << n ; for (long long i = 1; i <= n; i++) g[i].clear(); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int mxnn = 300000 + 10, inf = 0x3f3f3f3f; int n, q, a, cnt; int head[mxnn], son[mxnn], ans[mxnn], fa[mxnn]; struct node { int u, v, next; } e[mxnn << 1]; void adde(int u, int v) { e[++cnt].u = u; e[cnt].v = v; e[cnt].next = head[u]; head[u] = cnt; } void read(int &x) { x = 0; int f = 1; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = (x << 1) + (x << 3) + s - 0 ; s = getchar(); } x *= f; } void dfs(int u, int va) { ans[u] = u; for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].v; if (v == va) continue; dfs(v, u); son[u] += son[v]; } for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].v; if (v == va) continue; if (son[v] * 2 > son[u]) { ans[u] = ans[v]; break; } } while (son[u] > 2 * son[ans[u]]) ans[u] = fa[ans[u]]; } int main() { memset(head, -1, sizeof head); read(n), read(q); for (int i = 1; i <= n; ++i) son[i] = 1; for (int i = 2; i <= n; ++i) { read(a); adde(a, i); adde(i, a); fa[i] = a; } dfs(1, 0); while (q--) { read(a); printf( %d n , ans[a]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; bool pd(complex<double> a, complex<double> b, complex<double> c, complex<double> d) { return imag((b - a) * conj(d - a)) * imag((b - a) * conj(c - a)) < -eps; } bool aa(complex<double> a, complex<double> b, complex<double> c) { complex<double> d = c; c = b + b - c; if (imag((c - a) / (b - a)) < 0) swap(b, c); double r = abs(b - c) / sin(arg((c - a) * conj(b - a))) / 2; double th = acos(abs(b - a) / 2 / r); complex<double> B = a + polar(r, arg(b - a) + th), A = a + a - B, C = b + b - B, D = d + d - C; double dd[4]; dd[0] = abs(A - B), dd[1] = abs(A - D), dd[2] = abs(C - D), dd[3] = abs(B - C); sort(dd, dd + 4); if ((fabs(dd[0] - dd[2]) < eps || fabs(dd[1] - dd[3]) < eps) && pd(A, C, B, D) && pd(B, D, A, C)) { puts( YES ); printf( %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf n , real(A), imag(A), real(D), imag(D), real(C), imag(C), real(B), imag(B)); return 1; } return 0; } int main() { int T; scanf( %d , &T); while (T--) { int x1, y1, x2, y2, x3, y3; scanf( %d%d%d%d%d%d , &x1, &y1, &x2, &y2, &x3, &y3); complex<double> a = complex<double>(x1, y1), b = complex<double>(x2, y2), c = complex<double>(x3, y3); if (aa(a, b, c)) continue; if (aa(a, c, b)) continue; if (aa(b, a, c)) continue; if (aa(b, c, a)) continue; if (aa(c, a, b)) continue; if (aa(c, b, a)) continue; puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; inline int add(int a, int b) { if ((a += b) >= mod) a -= mod; return a; } inline int mult(int a, int b) { long long t = 1ll * a * b; if (t >= mod) t %= mod; return t; } inline int dec(int a, int b) { if ((a -= b) < 0) a += mod; return a; } inline int power(int a, int b) { int out = 1; while (b) { if (b & 1) out = mult(out, a); a = mult(a, a); b >>= 1; } return out; } int n, a[2510], f[100010], ans, mx, sum; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), sum += a[i]; mx = *max_element(a + 1, a + n + 1); f[1] = mult(mult(sum - 1, sum - 1), power(sum, mod - 2)); for (int i = 1; i < mx; i++) f[i + 1] = dec(add(f[i], f[i]), add(f[i - 1], mult(sum - 1, power(sum - i, mod - 2)))); for (int i = 1; i <= n; i++) ans = add(ans, f[a[i]]); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long L[200005], R[200005], U[200005], D[200005]; long long n; string S; long long x, y, sx = 0, sy = 0; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> S >> x >> y; S = _ + S; L[0] = R[0] = U[0] = D[0] = 0; for (long long i = 1; i <= n; i++) { L[i] = L[i - 1]; R[i] = R[i - 1]; D[i] = D[i - 1]; U[i] = U[i - 1]; if (S[i] == L ) L[i]++, sx--; else if (S[i] == R ) R[i]++, sx++; else if (S[i] == U ) U[i]++, sy++; else if (S[i] == D ) D[i]++, sy--; } if (sx == x && sy == y) { cout << 0; return 0; } if ((sx + sy + x + y) % 2 != 0) { cout << -1; return 0; } long long s_ind = 1, g_ind = n + 1; while (g_ind > s_ind) { long long len = (g_ind + s_ind) / 2; bool b = 0; for (long long j = len; j <= n; j++) { long long l = L[n] - L[j] + L[j - len], r = R[n] - R[j] + R[j - len], u = U[n] - U[j] + U[j - len], d = D[n] - D[j] + D[j - len]; long long curx = r - l, cury = u - d; if (abs(curx - x) + abs(cury - y) <= len) { b = 1; break; } } if (b) g_ind = len; else s_ind = len + 1; } if (s_ind <= n) cout << s_ind; else cout << -1; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
module axi_clkgen (
// clocks
clk,
clk_0,
clk_1,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_CLKIN_PERIOD = 5.0;
parameter PCORE_VCO_DIV = 11;
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
// clocks
input clk;
output clk_0;
output clk_1;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire mmcm_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_clkgen i_up_clkgen (
.mmcm_rst (mmcm_rst),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD),
.MMCM_VCO_DIV (PCORE_VCO_DIV),
.MMCM_VCO_MUL (PCORE_VCO_MUL),
.MMCM_CLK0_DIV (PCORE_CLK0_DIV),
.MMCM_CLK1_DIV (PCORE_CLK1_DIV))
i_mmcm_drp (
.clk (clk),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:38:12 11/20/2015
// Design Name:
// Module Name: HazardsUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HazardsUnit(
input branchID,
input [4:0]rsID,
input [4:0]rtID,
input [4:0]rsEX,
input [4:0]rtEX,
input [4:0]writeRegEX,
input [4:0]writeRegMEM,
input [4:0]writeRegWB,
input memToRegEX,
input memToRegMEM,
input regWriteEX,
input regWriteMEM,
input regWriteWB,
output stallFE,
output stallID,
output forwardAID,
output forwardBID,
output flushEX,
output reg [1:0]forwardAEX,
output reg [1:0]forwardBEX
);
wire lwstall;
wire branchstall;
assign lwstall = ((rsID == rtEX) || (rtID == rtEX)) && memToRegEX;
assign stallFE = lwstall || branchstall;
assign stallID = lwstall || branchstall;
assign flushEX = lwstall || branchstall;
assign forwardAID = (rsID == writeRegMEM) && regWriteMEM;
assign forwardBID = (rtID == writeRegMEM) && regWriteMEM;
assign branchstall = (branchID && regWriteEX && (writeRegEX == rsID || writeRegEX == rtID)) || (branchID && memToRegMEM && (writeRegMEM == rsID || writeRegMEM == rtID));
always @* begin
if ((rsEX == writeRegMEM) && regWriteMEM) begin
forwardAEX <= 'b10;
end
else if ((rsEX == writeRegWB) && regWriteWB) begin
forwardAEX <= 'b01;
end
else begin
forwardAEX <= 'b00;
end
if ((rtEX == writeRegMEM) && regWriteMEM) begin
forwardBEX <= 'b10;
end
else if ((rtEX == writeRegWB) && regWriteWB) begin
forwardBEX <= 'b01;
end
else begin
forwardBEX <= 'b00;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Freeze logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Generates all freezes and stalls inside RISC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_freeze.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_NO_FREEZE 3'd0
`define OR1200_FREEZE_BYDC 3'd1
`define OR1200_FREEZE_BYMULTICYCLE 3'd2
`define OR1200_WAIT_LSU_TO_FINISH 3'd3
`define OR1200_WAIT_IC 3'd4
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module or1200_freeze
(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, wait_on, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
force_dslot_fetch, abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, saving_if_insn,
fpu_done, mtspr_done,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input force_dslot_fetch;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input saving_if_insn;
input fpu_done;
input mtspr_done;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
reg [`OR1200_WAIT_ON_WIDTH-1:0] waiting_on;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freeze signals at the beginning of pipeline (such as if_freeze) can be
// asserted more often than freeze signals at the of pipeline (such as
// wb_freeze). In other words, wb_freeze must never be asserted when ex_freeze
// is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze
// (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
| (|waiting_on) | force_dslot_fetch) | du_stall;
assign ex_freeze = wb_freeze;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
| (|waiting_on)) | du_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
flushpipe_r <= 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= flushpipe;
else if (!flushpipe)
flushpipe_r <= 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
multicycle_cnt <= `OR1200_MULTICYCLE_WIDTH'd0;
else if (|multicycle_cnt)
multicycle_cnt <= multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= multicycle;
//
// Waiting on generation
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
waiting_on <= 0;
else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)
waiting_on <= 0;
else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
waiting_on <= 0;
else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
waiting_on <= 0;
else if (!ex_freeze)
waiting_on <= wait_on;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 1000 * 100 + 100; long long nums[maxn]; long long ans = 0; long long cou[30]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> nums[i]; cou[nums[i] + 10]++; } ans += (cou[0 + 10] * (cou[10] - 1)) / 2; for (int i = 1; i < 11; i++) { ans += cou[i + 10] * cou[-i + 10]; } cout << ans << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub (
clk,
A,
Amax,
out,
CE
);
// parameters
parameter A_WIDTH = 32;
parameter CONST_VALUE = 32'h1;
parameter ADD_SUB = 0;
localparam ADDER = 0;
localparam SUBSTRACTER = 1;
// I/O definitions
input clk;
input [(A_WIDTH-1):0] A;
input [(A_WIDTH-1):0] Amax;
output [(A_WIDTH-1):0] out;
input CE;
// registers
reg [(A_WIDTH-1):0] out = 'b0;
reg [A_WIDTH:0] out_d = 'b0;
reg [A_WIDTH:0] out_d2 = 'b0;
reg [(A_WIDTH-1):0] A_d = 'b0;
reg [(A_WIDTH-1):0] A_d2 = 'b0;
reg [(A_WIDTH-1):0] Amax_d = 'b0;
reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_WIDTH-1):0] B_reg = CONST_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; long long n, m, dau, cuoi, giua, pos1, pos2, t; bool kt; struct point { long long x, y; } p[N], ab, ac, z; long long ccw(point a, point b, point c) { ab = {b.x - a.x, b.y - a.y}; ac = {c.x - a.x, c.y - a.y}; return ab.x * ac.y - ab.y * ac.x; } long long dis(point a, point b) { return (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y); } bool cmp1(point a, point b) { return (a.y < b.y || (a.y == b.y && a.x < b.x)); } bool cmp2(point b, point c) { t = ccw(p[1], b, c); return t > 0 || (t == 0 && dis(p[1], b) > dis(p[1], c)); } bool check(point z) { if (ccw(p[1], p[2], z) <= 0) return 0; if (ccw(p[n], p[1], z) <= 0) return 0; pos1 = pos2 = 0; dau = 2; cuoi = n; while (dau <= cuoi) { giua = (dau + cuoi) / 2; if (ccw(p[1], p[giua], z) >= 0) pos1 = giua, dau = giua + 1; else cuoi = giua - 1; } if (pos1 == 0) return 0; dau = 2; cuoi = n; while (dau <= cuoi) { giua = (dau + cuoi) / 2; if (ccw(p[1], p[giua], z) <= 0) pos2 = giua, cuoi = giua - 1; else dau = giua + 1; } if (pos2 == 0) return 0; if (pos1 == pos2) { if (dis(p[1], p[pos1]) <= dis(p[1], z)) return 0; else return 1; } if (ccw(p[pos1], p[pos2], z) <= 0) return 0; return 1; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i].x >> p[i].y; } sort(p + 1, p + 1 + n, cmp1); sort(p + 2, p + 1 + n, cmp2); cin >> m; kt = 1; for (int i = 1; i <= m; i++) { cin >> z.x >> z.y; if (kt == 1) if (check(z) == 0) { kt = 0; } } if (kt == 1) cout << YES ; else cout << NO ; }
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#include <bits/stdc++.h> using namespace std; class myistream { static const int maxsize = 1000007, tmpsize = 50; char *s, *tmp; char *cur, *upperbound; FILE *fp; bool last_read; bool end_of_file; bool to_return; void upd() { int num = fread(s, sizeof(char), maxsize, fp); if (num < maxsize) last_read = true, upperbound = s + num; if (!num) end_of_file = true; cur = s; } char scan() { if (cur >= upperbound) { if (last_read) end_of_file = true; else upd(); } return *cur++; } bool isspace(char c) { return c == || c == n || c == r || c == t ; } public: myistream(FILE *_fp) : last_read(false), end_of_file(false), to_return(false), fp(_fp) { s = new char[maxsize + 2]; tmp = new char[tmpsize + 2]; upperbound = s + maxsize; cur = s + maxsize; } ~myistream() { delete[] s; delete[] tmp; fclose(fp); } operator void *() const { return to_return ? 0 : (void *)this; } bool operator!() const { return to_return; } myistream &operator>>(int &a) { if (!end_of_file) { char c = scan(); while (isspace(c) && !end_of_file) c = scan(); if (end_of_file) { to_return = true; return *this; } a = 0; bool nega = false; if (c == - ) nega = true, c = scan(); while (!isspace(c) && !end_of_file) { a = a * 10 + (((int)c) & 15); c = scan(); } if (nega) a = -a; } else to_return = true; return *this; } myistream &operator>>(long long &a) { if (!end_of_file) { char c = scan(); while (isspace(c) && !end_of_file) c = scan(); if (end_of_file) { to_return = true; return *this; } a = 0; bool nega = false; if (c == - ) nega = true, c = scan(); while (!isspace(c) && !end_of_file) { a = a * 10 + (((long long)c) & 15); c = scan(); } if (nega) a = -a; } else to_return = true; return *this; } myistream &operator>>(char &c) { if (!end_of_file) { c = scan(); while (isspace(c) && !end_of_file) c = scan(); } if (end_of_file) to_return = true; return *this; } myistream &operator>>(bool &b) { if (!end_of_file) { char c = scan(); while (isspace(c) && !end_of_file) c = scan(); b = (c == 1 ); } if (end_of_file) to_return = true; return *this; } myistream &operator>>(char *s) { if (!end_of_file) { char c = scan(); while (isspace(c) && !end_of_file) c = scan(); if (end_of_file) { to_return = true; return *this; } while (!isspace(c) && !end_of_file) *s++ = c, c = scan(); *s = 0 ; } else to_return = true; return *this; } myistream &operator>>(string &s) { s.clear(); if (!end_of_file) { char c = scan(); while (isspace(c) && !end_of_file) c = scan(); if (end_of_file) { to_return = true; return *this; } while (!isspace(c) && !end_of_file) s.push_back(c), c = scan(); } else to_return = true; return *this; } myistream &operator>>(double &d) { if (!end_of_file) { char *tp = tmp; char c = scan(); while (isspace(c) && !end_of_file) c = scan(); if (end_of_file) { to_return = true; return *this; } while (!isspace(c) && !end_of_file) *tp++ = c, c = scan(); *tp = 0 ; sscanf(tmp, %lf , &d); } else to_return = true; return *this; } }; class myostreamEndlType {}; class myostreamSetPrecisionType { public: int precision; myostreamSetPrecisionType(int _precision) : precision(_precision) {} }; class myostream { static const int maxsize = 1000007, tmpsize = 50; char *s, *upperbound, *cur, *tmp; FILE *fp; int numberAfterPoint; char doubleFormat[20]; void write(char c) { if (cur >= upperbound) { fwrite(s, sizeof(char), maxsize, fp); cur = s; } *cur++ = c; } public: myostream(FILE *_fp) : fp(_fp) { s = new char[maxsize]; tmp = new char[tmpsize + 2]; upperbound = s + maxsize; cur = s; precision(6); } ~myostream() { fwrite(s, sizeof(char), cur - s, fp); fclose(fp); delete[] s; } void precision(int x) { numberAfterPoint = x; sprintf(doubleFormat, %%.%dlf , x); } int precision(void) { return numberAfterPoint; } myostream &operator<<(const myostreamSetPrecisionType &p) { precision(p.precision); return *this; } myostream &operator<<(const char &c) { write(c); return *this; } myostream &operator<<(const myostreamEndlType &e) { write( n ); return *this; } myostream &operator<<(const bool &b) { write(b ? 1 : 0 ); return *this; } myostream &operator<<(const char *c) { for (const char *p = c; *p; p++) write(*p); return *this; } myostream &operator<<(const string &c) { return *this << c.c_str(); } myostream &operator<<(const int &a) { if (a == 0) { write( 0 ); return *this; } int s = a; if (s < 0) write( - ), s = -s; char *tp = tmp; while (s > 0) { *tp++ = char((s % 10) | 48); s /= 10; } for (--tp; tp >= tmp; --tp) write(*tp); return *this; } myostream &operator<<(const long long &a) { if (a == 0) { write( 0 ); return *this; } long long s = a; if (s < 0) write( - ), s = -s; char *tp = tmp; while (s > 0) { *tp++ = char((s % 10) | 48); s /= 10; } for (--tp; tp >= tmp; --tp) write(*tp); return *this; } myostream &operator<<(const double &d) { sprintf(tmp, doubleFormat, d); *this << tmp; return *this; } }; const int maxn = 100050, inf = 0x3fffffff; int n, m, k; bool hasv[maxn] = {}; int s, t; vector<int> buf[maxn]; bool judge(int maxV) { static bool inq[maxn]; static int dis[maxn]; memset(inq, false, sizeof inq); fill(dis, dis + n, inf); queue<int> q; dis[s] = 0; q.push(s); inq[s] = true; while (!q.empty()) { int x = q.front(); q.pop(); inq[x] = false; if (dis[x] < maxV) for (auto it = (buf[x]).begin(); it != (buf[x]).end(); ++it) { int tmp = dis[x] + 1; if (hasv[*it]) tmp = 0; if (dis[*it] > tmp) { dis[*it] = tmp; if (!inq[*it]) { inq[*it] = true; q.push(*it); } } } } return dis[t] < inf; } int main(void) { cin >> n >> m >> k; while (k--) { int a; cin >> a; --a; hasv[a] = true; } while (m--) { int a, b; cin >> a >> b; --a; --b; buf[a].push_back(b); buf[b].push_back(a); } cin >> s >> t; --s; --t; int left = 1, right = n + 1; while (left < right) { int mid = (left + right) >> 1; if (judge(mid)) right = mid; else left = mid + 1; } if (left > n) cout << -1 << endl; else cout << left << endl; }
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