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module cameraReader_sim
(
input clk,
input reset_n,
output refclk,
input pclk,
input [7:0] data,
input vsync,
input hsync,
output [15:0] data_out,
output wire wrreq,
output wire wrclk
);
reg wrclk1 = 0;
always@(negedge clk)
wrclk1 <= ~wrclk1;
reg [19:0] pixel_counter;
reg [9:0] wait_counter_hs;
reg [19:0] wait_counter_vs;
reg [1:0] state = 0;
assign wrclk = clk;
assign wrreq = state == 2'b01 ? wrclk1 : 1'b0;
assign data_out = pixel_counter % 640;
always@(posedge wrclk1)
begin
if(reset_n == 1'b0)
begin
pixel_counter <= 0;
wait_counter_vs <= 0;
wait_counter_hs <= 0;
end
else
begin
case(state)
2'b00:
begin
if(wait_counter_vs == 15679)
begin
wait_counter_vs <= 0;
state <= 2'b01;
pixel_counter <= pixel_counter + 1;
end
else
wait_counter_vs <= wait_counter_vs + 1;
end
2'b01:
begin
if(pixel_counter % 640 == 0)
begin
if(pixel_counter == 640*480)
begin
pixel_counter <= 0;
state <= 2'b11; //vs wait
end
else
state <= 2'b10; // hs wait
end
else
pixel_counter <= pixel_counter + 1;
end
2'b10:
begin
if(wait_counter_hs == 144)
begin
wait_counter_hs <= 0;
state <= 2'b01;
pixel_counter <= pixel_counter + 1;
end
else
wait_counter_hs <= wait_counter_hs + 1;
end
2'b11:
begin
if(wait_counter_vs == 7839)
begin
wait_counter_vs <= 0;
state <= 2'b00;
end
else
wait_counter_vs <= wait_counter_vs + 1;
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/);
// Note these are NOT pure.
import "DPI-C" function int dpii_clear ();
import "DPI-C" function int dpii_count (input int ctr);
import "DPI-C" function bit dpii_inc0 (input int ctr);
import "DPI-C" function bit dpii_inc1 (input int ctr);
import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
integer i;
integer j;
bit b;
integer errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
task check(integer line, int got, int ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
// Test loop
initial begin
// Spec says && || -> and ?: short circuit, no others do.
// Check both constant & non constants.
dpii_clear();
check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 0);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 0);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 0);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 0);
//
dpii_clear();
check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1);
check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1);
check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 0);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0);
check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0);
check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 0);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 0);
//
dpii_clear();
check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1);
check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
// Something a lot more complicated
dpii_clear();
for (i=0; i<64; i++) begin
b = ( ((dpii_incx(0,i[0])
&& (dpii_incx(1,i[1])
|| dpii_incx(2,i[2])
| dpii_incx(3,i[3]))) // | not ||
|| dpii_incx(4,i[4]))
-> dpii_incx(5,i[5]));
end
check (`__LINE__, dpii_count(0), 64);
check (`__LINE__, dpii_count(1), 32);
check (`__LINE__, dpii_count(2), 16);
check (`__LINE__, dpii_count(3), 16);
check (`__LINE__, dpii_count(4), 36);
check (`__LINE__, dpii_count(5), 46);
if (|errors) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, large = 2000000000, small = -2000000000; string s1, s2; cin >> n; for (int i = 0; i < n; i++) { cin >> s1 >> x >> s2; if ((s1 == > && s2 == Y ) || (s1 == <= && s2 == N )) { if (x >= small) { small = x + 1; } } else if ((s1 == < && s2 == Y ) || (s1 == >= && s2 == N )) { if (x <= large) { large = x - 1; } } else if ((s1 == >= && s2 == Y ) || (s1 == < && s2 == N )) { if (x >= small) { small = x; } } else { if (x <= large) { large = x; } } } if (small > large) { cout << Impossible ; } else { cout << small; } return (0); }
|
#include <bits/stdc++.h> using namespace std; int n, v, t, p, cnt1, cnt2, x; vector<pair<int, int>> k, c; vector<int> ans; void add(bool sm) { v--; if (sm) { x += k[cnt1].first; ans.push_back(k[cnt1++].second); } else { x += c[cnt2].first; ans.push_back(c[cnt2++].second); v--; } } void solve() { cin >> n >> v; for (int i = 0; i < n; ++i) { cin >> t >> p; t--; if (t) { c.push_back({p, i + 1}); } else { k.push_back({p, i + 1}); } } sort(k.begin(), k.end()); sort(c.begin(), c.end()); reverse(k.begin(), k.end()); reverse(c.begin(), c.end()); while ((v >= 1 && cnt1 < k.size()) || (v >= 2 && cnt2 < c.size())) { add((cnt2 == c.size() || v == 1) || (k[cnt1].first > c[cnt2].first) || (cnt1 < k.size() - 1 && k[cnt1].first + k[cnt1 + 1].first > c[cnt2].first)); } cout << x << endl; for (int i = 0; i < ans.size(); ++i) { cout << ans[i] << ; } cout << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<string> v; vector<string> res; for (int i = 0; i < n; i++) { string s; cin >> s; v.push_back(s); } bool flag = 0; string t = , pal = ; for (int i = 0; i < v.size(); i++) { string s = v[i]; t = s; reverse(s.begin(), s.end()); auto it = find(v.begin(), v.end(), s); if (it != v.end()) { if (*it == t) { flag = 1; pal = t; continue; } res.push_back(v[i]); v.erase(it); } } string out = ; for (auto x : res) { out += x; } string p = out; if (flag) out += pal; reverse(p.begin(), p.end()); out += p; cout << out.length() << n ; cout << out; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_shifter.v
// Title : Barrel shifter
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_shifter (
// ----- Inputs -------
clk_i,
rst_i,
stall_x,
direction_x,
sign_extend_x,
operand_0_x,
operand_1_x,
// ----- Outputs -------
shifter_result_m
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input direction_x; // Direction to shift
input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0)
input [`LM32_WORD_RNG] operand_0_x; // Operand to shift
input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] shifter_result_m; // Result of shift
wire [`LM32_WORD_RNG] shifter_result_m;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg direction_m;
reg [`LM32_WORD_RNG] left_shift_result;
reg [`LM32_WORD_RNG] right_shift_result;
reg [`LM32_WORD_RNG] left_shift_operand;
wire [`LM32_WORD_RNG] right_shift_operand;
wire fill_value;
wire [`LM32_WORD_RNG] right_shift_in;
integer shift_idx_0;
integer shift_idx_1;
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select operands - To perform a left shift, we reverse the bits and perform a right shift
always @(*)
begin
for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
end
assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT)
? operand_0_x[`LM32_WORD_WIDTH-1]
: 1'b0;
// Determine bits to shift in for right shift or rotate
assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
// Reverse bits to get left shift result
always @(*)
begin
for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1];
end
// Select result
assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result;
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Perform right shift
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
right_shift_result <= {`LM32_WORD_WIDTH{1'b0}};
direction_m <= `FALSE;
end
else
begin
if (stall_x == `FALSE)
begin
right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
direction_m <= direction_x;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:43:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.v
// Design : system_clock_splitter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clock_splitter,Vivado 2016.4" *)
module system_clock_splitter_0_0(clk_in, latch_edge, clk_out)
/* synthesis syn_black_box black_box_pad_pin="clk_in,latch_edge,clk_out" */;
input clk_in;
input latch_edge;
output clk_out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
int cnt_ar2d;
// sizes
int siz_bit ;
int siz_byte;
int siz_int ;
int siz_ar1d;
int siz_ar2d;
// add all counters
assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
// finish report
always @ (posedge clk)
if (cnt == 5) begin
if (siz_bit != 1) $stop();
if (siz_byte != 8) $stop();
if (siz_int != 32) $stop();
if (siz_ar1d != 24) $stop();
if (siz_ar2d != 16) $stop();
end else if (cnt > 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
// instances with various types
mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit );
mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int );
mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
// double types
mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3();
mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5();
endmodule : t
module mod_typ #(
parameter type TYP = byte
)(
input logic clk,
output TYP cnt,
output int siz
);
initial cnt = 0;
always @ (posedge clk)
cnt <= cnt + 1;
assign siz = $bits (cnt);
endmodule
module mod_typ2
#(
parameter int WIDTH1 = 0,
parameter int WIDTH2 = WIDTH1,
parameter type TYP1 = byte,
// Below we need to imply that TYP2 is a type
TYP2 = TYP1
)();
TYP1 t1;
TYP2 t2;
initial begin
if ($bits(t1) != WIDTH1) $stop;
if ($bits(t2) != WIDTH2) $stop;
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: testpattern
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE6E22 , EP4CE10E22
// Cyclone 10 LP: 10CL006YE144, 10CL010YE144
// Tool versions: Altera Quartus Prime
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module testpattern(
VCLK,
nRST,
palmode,
vdata_sync_valid_i,
vdata_sync_i,
vdata_valid_o,
vdata_o
);
`include "vh/n64adv_vparams.vh"
input VCLK;
input nRST;
input palmode;
input vdata_sync_valid_i;
input [3:0] vdata_sync_i;
output reg vdata_valid_o = 1'b0;
output reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1'b0}};
wire negedge_nVSYNC = vdata_o[3*color_width_i+3] & !vdata_sync_i[3];
wire negedge_nHSYNC = vdata_o[3*color_width_i+1] & !vdata_sync_i[1];
reg [8:0] vcnt = 9'b0;
reg [9:0] hcnt = 10'b0;
wire [8:0] pattern_vstart = palmode ? `VSTART_PAL_LX1 : `VSTART_NTSC_LX1;
wire [8:0] pattern_vstop = palmode ? `VSTOP_PAL_LX1 : `VSTOP_NTSC_LX1;
wire [9:0] pattern_hstart = palmode ? `HSTART_PAL : `HSTART_NTSC;
wire [9:0] pattern_hstop = palmode ? `HSTOP_PAL : `HSTOP_NTSC;
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_valid_o <= 1'b0;
vdata_o <= {vdata_width_i{1'b0}};
vcnt <= 9'b0;
hcnt <= 10'b0;
end else begin
vdata_valid_o <= vdata_sync_valid_i;
if (vdata_sync_valid_i) begin
if (negedge_nHSYNC) begin
hcnt <= 10'b0;
vcnt <= &vcnt ? vcnt : vcnt + 1'b1;
end else begin
hcnt <= &hcnt ? hcnt : hcnt + 1'b1;
end
if (negedge_nVSYNC)
vcnt <= 9'b0;
if ((vcnt >= pattern_vstart) && (vcnt < pattern_vstop)) begin
if ((hcnt > pattern_hstart) && (hcnt < pattern_hstop))
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{~vdata_o[0]}};
else
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{1'b0}};
if (hcnt == pattern_hstart)
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{vcnt[0]}};
end else begin
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{1'b0}};
end
vdata_o[`VDATA_I_SY_SLICE] <= vdata_sync_i;
end
end
endmodule
|
`include "defines.v"
`include "HRnode.v"
`timescale 1ns/1ps
/*module HRnode
#(parameter addr = 4'b0010)
(
input `control_w port0_i,
input `control_w port1_i,
input `control_w port0_local_i,
input `control_w port1_local_i,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_o,
output `control_w port1_o,
output `control_w port0_local_o,
output `control_w port1_local_o
);*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
HRnode r(
.clk(clk),
.rst(rst),
.port0_i(flit0c), .port0_o(port0_co),
.port1_i(flit1c), .port1_o(port1_co),
.port0_local_i(flitl0), .port0_local_o(portl0_co),
.port1_local_i(flitl1), .port1_local_o(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1851;
flit1c = 144'h0123456789abcdef0123456789abcdef1853;
flitl1 = 144'h0;
flitl0 = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
`timescale 1 ns/1 ps
module divider (
rfd, rdy, divide_by_zero, nd, clk, dividend, quotient, divisor, fractional
)/* synthesis syn_black_box syn_noprune=1 */;
output reg rfd;
output reg rdy;
output reg divide_by_zero;
input nd;
input clk;
input [3 : 0] dividend;
output reg [3 : 0] quotient;
input [31 : 0] divisor;
output reg [31 : 0] fractional;
wire signed [63:0] dend = {28'b0, dividend, 32'b0};
wire signed [63:0] dsor = {{32{divisor[31]}}, divisor};
wire signed [63:0] result = dend/dsor;
reg signed [63:0] result_save;
initial
begin
rfd <= 1;
rdy <= 0;
divide_by_zero <= 0;
end
always @(posedge clk)
begin
rdy <= 0;
if (nd)
begin
rfd <= 0;
result_save <= result;
repeat (10) @(posedge clk);
#1;
quotient <= result_save[35:32];
fractional <= result_save[31:0];
rdy <= 1;
rfd <= 1;
// divide_by_zero <= divisor == 0;
// @(posedge clk);
// #1;
// rdy <= 0;
end
// pipeline[1] <= result;
// pipeline[2] <= pipeline[1];
// pipeline[3] <= pipeline[2];
// pipeline[4] <= pipeline[3];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e2 + 5; int n; long long hx, hy; long long ux, uy; struct line { long long x1, y1; long long x2, y2; line(long long _x1, long long _y1, long long _x2, long long _y2) { x1 = _x1; y1 = _y1; x2 = _x2; y2 = _y2; } }; vector<line> lines; void get_line(long long a, long long b, long long c) { long long x1, y1; long long x2, y2; if (b == 0) { x1 = -c / a; x2 = -c / a; y1 = -1e7; y2 = 1e7; } if (a == 0) { y1 = -c / b; y2 = -c / b; x1 = -1e7; x2 = 1e7; } if (a != 0 && b != 0) { x1 = -1e7; x2 = 1e7; y1 = (-a * x1 - c) / b; y2 = (-a * x2 - c) / b; } lines.push_back(line(x1, y1, x2, y2)); } struct point { long long x; long long y; point() { x = 0; y = 0; } point(long long _x, long long _y) { x = _x; y = _y; } }; int orientation(point a, point b, point c) { long long clockwise = (b.y - a.y) * (c.x - b.x) - (c.y - b.y) * (b.x - a.x); if (clockwise > 0) return 1; if (clockwise == 0) return 0; if (clockwise < 0) return -1; } bool do_intersect(line a, line b) { point a1, a2; point b1, b2; a1 = point(a.x1, a.y1); a2 = point(a.x2, a.y2); b1 = point(b.x1, b.y1); b2 = point(b.x2, b.y2); if ((orientation(a1, a2, b1) != orientation(a1, a2, b2)) && (orientation(b1, b2, a1) != orientation(b1, b2, a2))) return true; return false; } int ans; int main() { int i; long long a, b, c; cin >> hx >> hy; cin >> ux >> uy; cin >> n; for (i = 1; i <= n; i++) { scanf( %I64d%I64d%I64d , &a, &b, &c); get_line(a, b, c); } line road = line(hx, hy, ux, uy); for (i = 0; i < lines.size(); i++) { if (do_intersect(road, lines[i])) ans++; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class A> void read(vector<A>& v); template <class A, size_t S> void read(array<A, S>& a); template <class T> void read(T& x) { cin >> x; } void read(double& d) { string t; read(t); d = stod(t); } void read(long double& d) { string t; read(t); d = stold(t); } template <class H, class... T> void read(H& h, T&... t) { read(h); read(t...); } template <class A> void read(vector<A>& x) { for (auto& a : x) read(a); } template <class A, size_t S> void read(array<A, S>& x) { for (auto& a : x) read(a); } const int mod = 1e9 + 7; long long int primeLimit = 1e5; const double PI = acos(-1); bool prime[100000]; string LongestPalindromicPrefix(string str) { string temp = str + ? ; reverse(str.begin(), str.end()); temp += str; long long int n = temp.length(); long long int lps[n]; fill(lps, lps + n, 0); for (long long int i = 1; i < n; i++) { long long int len = lps[i - 1]; while (len > 0 && temp[len] != temp[i]) { len = lps[len - 1]; } if (temp[i] == temp[len]) { len++; } lps[i] = len; } return temp.substr(0, lps[n - 1]); } bool binarySearchFloat(float lower, float higher, float maxErrorAllowed, long long int numberOfTimesWanttoRunCode) { float l = lower, r = higher; float eps = maxErrorAllowed; long long int iteration_count = numberOfTimesWanttoRunCode; for (long long int i = 0; i < iteration_count && l + eps < r; ++i) { } } void primefinder() { memset(prime, true, sizeof(prime)); prime[1] = false; prime[0] = false; for (long long int i = 2; i < primeLimit; i++) { if (prime[i]) { for (long long int j = i * i; j < primeLimit; j += i) { prime[j] = false; } } } } long long fast_pow(long long int x, long long int y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } long long Fast_pow(long long int x, long long int y, long long int p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int bs(vector<long long int> arr, long long int low, long long int cur) { long long int high = (long long int)arr.size() - 1; long long int index = -1; while (low <= high) { long long int mid = (low + high) / 2; if (arr[mid] <= cur) { index = mid; low = mid + 1; } else { high = mid - 1; } } return index; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, k; cin >> n >> k; vector<long long int> arr(n); read(arr); sort((arr).begin(), (arr).end()); long long int ans = 0; for (long long int i = 0; i < n; i++) { long long int index = bs(arr, i, 2 * k); if (index >= (n - 1)) break; if (index == -1) { while ((k * 2) < arr[i]) { k *= 2; ans++; } k = std::max(k, arr[i]); } else { k = std::max(k, arr[index]); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool isPrime(T x) { if (x <= 1) return false; T i; for (i = 2; i * i <= x; i++) if (x % i == 0) return false; return true; } template <class T> class Prime { public: vector<T> z; Prime() { z.resize(1e5 + 7); for (int i = (0); i < (((int)z.size())); i++) z[i] = 1; z[0] = 0; z[1] = 0; T j; for (int i = (2); i < (((int)z.size())); i++) { if (z[i]) { j = i + i; while (j < ((int)z.size())) { z[j] = 0; j += i; } } } } }; template <class T> double dist(T x1, T y1, T x2, T y2) { return sqrt(1. * (x2 - x1) * (x2 - x1) + 1. * (y2 - y1) * (y2 - y1)); } template <class T> class Point { public: T x, y; Point() {} Point(T a, T b) : x(a), y(b) {} bool operator==(const Point& tmp) const { return (x == tmp.x && y == tmp.y); } Point operator-(const Point& tmp) const { return Point<T>(x - tmp.x, y - tmp.y); } }; char toLowerCase(char x) { return (x + 32); } char toUpperCase(char x) { return (x - 32); } bool isUpperCase(char x) { return (65 <= x && x <= 90) ? 1 : 0; } bool isLowerCase(char x) { return (97 <= x && x <= 122) ? 1 : 0; } bool isAlpha(char x) { return (isUpperCase(x) || isLowerCase(x)) ? 1 : 0; } bool isDigit(char x) { return ( 0 <= x && x <= 9 ) ? 1 : 0; } template <class T> T toDec(string s) { stringstream is(s); T res; is >> res; return res; } template <class T> string toStr(T n) { string s; stringstream is; is << n; is >> s; return s; } template <class T> void checkmin(T& a, T b) { if (a > b) a = b; } template <class T> void checkmax(T& a, T b) { if (a < b) a = b; } vector<int> res; string s; void parse(int ind) { string tmp = s.substr(ind + 7); int p = tmp.find( <table> ); if (p != -1) { parse(ind + 7 + p); tmp = s.substr(ind + 7); } p = tmp.find( </table> ) + ind + 14; int i, tot; i = ind; tot = 0; while (i <= p) { if (i + 3 <= p && s.substr(i, 4) == <td> ) tot++; s[i] = 1 ; i++; } res.push_back(tot); } int main() { int c; while ((c = getchar()) != EOF) { if (c != n ) s += c; } parse(0); sort(res.begin(), res.end()); for (int i = (0); i < (((int)res.size())); i++) cout << res[i] << ; return 0; }
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: MULT.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module MULT (
dataa,
result);
input [12:0] dataa;
output [25:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "13"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "26"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "13"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "26"
// Retrieval info: USED_PORT: dataa 0 0 13 0 INPUT NODEFVAL "dataa[12..0]"
// Retrieval info: USED_PORT: result 0 0 26 0 OUTPUT NODEFVAL "result[25..0]"
// Retrieval info: CONNECT: @data 0 0 13 0 dataa 0 0 13 0
// Retrieval info: CONNECT: result 0 0 26 0 @result 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; template <typename T> istream& operator>>(istream& is, vector<T>& a) { for (T& ai : a) is >> ai; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T> const& a) { os << [ ; for (const T& ai : a) os << ai << ; return os << ] ; } template <typename T1, typename T2> istream& operator>>(istream& is, pair<T1, T2>& a) { return is >> a.first >> a.second; } template <typename T1, typename T2> ostream& operator<<(ostream& os, pair<T1, T2> const& a) { return os << ( << a.first << , << a.second << ) ; } int f() { int n, h, l, r; cin >> n >> h >> l >> r; vector<int> a(n), b(h, -1); cin >> a; b[0] = 0; for (int ai : a) { vector<int> c(h, -1); for (int i = 0; i < h; ++i) { if (b[i] < 0) continue; int j = i + ai - 1; if (j >= h) j -= h; c[j] = max(c[j], b[i] + (l <= j && j <= r)); if (++j >= h) j -= h; c[j] = max(c[j], b[i] + (l <= j && j <= r)); } b.swap(c); } return *max_element((b).begin(), (b).end()); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout << f() << n ; return 0; }
|
/*
* Copyright (c) 2000 Peter monta ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
function [3:0] foo;
input [3:0] x;
begin
foo = ~x + 1;
end
endfunction
reg [3:0] x;
wire [3:0] y;
assign y = foo(x);
initial begin
x = 4'b0110;
#1;
if (y==4'b1010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 7; vector<pair<int, int> > s; int co[maxn], deg[maxn]; int main() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { pair<int, int> q; cin >> q.first >> q.second; s.push_back(q); } for (int i = 1; i <= n; i++) { cin >> co[i]; } int x = 0; for (auto i : s) { if (co[i.first] != co[i.second]) { deg[i.first]++; deg[i.second]++; x++; } } int flag = 0; for (int i = 1; i <= n; i++) { if (deg[i] == x) { flag = i; } } if (flag) { printf( YES n%d n , flag); } else { printf( NO n ); } }
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_multiplier
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input inst_mul
,input inst_mulh
,input inst_mulhsu
,input inst_mulhu
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input hold_i
// Outputs
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
//`include "riscv_defs.v"
localparam MULT_STAGES = 2; // 2 or 3
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg [31:0] result_e2_q;
reg [31:0] result_e3_q;
reg [32:0] operand_a_e1_q;
reg [32:0] operand_b_e1_q;
reg mulhi_sel_e1_q;
//-------------------------------------------------------------
// Multiplier
//-------------------------------------------------------------
wire [64:0] mult_result_w;
reg [32:0] operand_b_r;
reg [32:0] operand_a_r;
reg [31:0] result_r;
wire mult_inst_w = (inst_mul) ||
(inst_mulh) ||
(inst_mulhsu) ||
(inst_mulhu);
always @ *
begin
if (inst_mulhsu)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else if (inst_mulh)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else // MULHU || MUL
operand_a_r = {1'b0, opcode_ra_operand_i[31:0]};
end
always @ *
begin
if (inst_mulhsu)
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
else if (inst_mulh)
operand_b_r = {opcode_rb_operand_i[31], opcode_rb_operand_i[31:0]};
else // MULHU || MUL
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
end
// Pipeline flops for multiplier
always @(posedge clk_i)
if (rst_i)
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
else if (hold_i)
;
else if (opcode_valid_i && mult_inst_w)
begin
operand_a_e1_q <= operand_a_r;
operand_b_e1_q <= operand_b_r;
mulhi_sel_e1_q <= ~(inst_mul);
end
else
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
assign mult_result_w = {{ 32 {operand_a_e1_q[32]}}, operand_a_e1_q}*{{ 32 {operand_b_e1_q[32]}}, operand_b_e1_q};
always @ *
begin
result_r = mulhi_sel_e1_q ? mult_result_w[63:32] : mult_result_w[31:0];
end
always @(posedge clk_i)
if (rst_i)
result_e2_q <= 32'b0;
else if (~hold_i)
result_e2_q <= result_r;
always @(posedge clk_i)
if (rst_i)
result_e3_q <= 32'b0;
else if (~hold_i)
result_e3_q <= result_e2_q;
assign writeback_value_o = (MULT_STAGES == 3) ? result_e3_q : result_e2_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n; cin >> n; map<double, int> mp2; map<string, double> mp1; vector<string> S; while (n--) { string x; cin >> x; S.push_back(x); int plus = 0, end = 0; double a, b, c; for (int i = 1; i < x.size(); i++) { if (x[i] == + ) plus = i; if (x[i] == ) ) end = i; } a = stod(x.substr(1, plus - 1)); b = stod(x.substr(plus + 1, end - plus - 1)); c = stod(x.substr(end + 2, x.size() - end + 2)); mp1[x] = (a + b) / c; mp2[(a + b) / c]++; } for (auto i : S) { cout << mp2[mp1[i]] << ; } return 0; }
|
// ZX-Evo Base Configuration (c) NedoPC 2014
//
// CMOS emulator: cmos is needed for zxevo.rom to function correctly
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
module cmosemu
(
input wire zclk,
input wire cmos_req,
input wire [7:0] cmos_addr,
input wire cmos_rnw,
output reg [7:0] cmos_read,
input wire [7:0] cmos_write
);
reg [7:0] mem [0:239];
reg req_r;
function [7:0] cmos_rd
(
input [7:0] addr
);
if( addr<8'd240 )
cmos_rd = mem[addr];
else
cmos_rd = 8'hFF;
endfunction
task cmos_wr
(
input [7:0] addr,
input [7:0] data
);
if( addr<8'd240 )
mem[addr] <= data;
endtask
initial
begin
int i;
for(i=0;i<256;i=i+1)
mem[i] <= 8'd0;
end
always @(posedge zclk)
req_r <= cmos_req;
always @(posedge zclk)
begin
cmos_read <= cmos_rd(cmos_addr);
if( req_r && !cmos_rnw )
cmos_wr(cmos_addr,cmos_write);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 48; long long s, x, xCopy, sCopy, pos[MAXN][2], result; int n, bitS, bitX; int main() { cin >> s >> x; pos[0][0] = 1; pos[0][1] = 0; n = 0; xCopy = x; sCopy = s; while (x || s) { n++; bitS = s % 2; bitX = x % 2; if (bitS == 0 && bitX == 0) { pos[n][0] = pos[n - 1][0]; pos[n][1] = pos[n - 1][0]; } else { if (bitS == 0 && bitX == 1) { pos[n][0] = 0; pos[n][1] = 2 * pos[n - 1][1]; } else { if (bitS == 1 && bitX == 0) { pos[n][0] = pos[n - 1][1]; pos[n][1] = pos[n - 1][1]; } else { pos[n][0] = 2 * pos[n - 1][0]; pos[n][1] = 0; } } } s >>= 1; x >>= 1; } result = pos[n][0]; if ((sCopy ^ 0) == xCopy) result -= 2; cout << result; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int SZ = 200005; vector<int> graph[SZ]; int par[SZ]; int dst[SZ]; int tot; void dfs(int x, int crt) { par[x] = crt; tot++; for (int nxt : graph[x]) { if (par[nxt]) continue; dfs(nxt, crt); } } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { graph[i].clear(); par[i] = 0; dst[i] = 0; } for (int i = 1; i <= n; i++) { int x; cin >> x; graph[i].push_back(x); } int pp = 0; for (int i = 1; i <= n; i++) { if (par[i]) continue; tot = 0; dfs(i, ++pp); dst[pp] = tot; } for (int i = 1; i <= n; i++) cout << dst[par[i]] << ; cout << n ; } return 0; }
|
module ALU(a_in, b_in, op_in, c_out, overflow);
input [5:0] a_in, b_in;
input [1:0] op_in;
output [11:0] c_out;
output overflow;
wire [5:0] adder_out, suber_out;
wire [11:0] muler_out, diver_out;
/*
* Adder
*/
Adder6 adder(
.a_in(a_in),
.b_in(b_in),
.s_out(adder_out)
);
/*
* Substract (by adding with two's compliment)
*/
wire [5:0] tc_a_out;
TwosCompliment tc(
.a_in(b_in),
.a_out(tc_a_out)
);
Adder6 suber(
.a_in(a_in),
.b_in(tc_a_out),
.s_out(suber_out)
);
/*
* multiply
*/
Multiplier muler(
.a_in(a_in),
.b_in(b_in),
.c_out(muler_out)
);
/*
* divider
*/
Divider diver(
.a_in(a_in),
.b_in(b_in),
.c_out(diver_out)
);
/*
* 2-bit mux
*/
`define OPADD 2'b00
`define OPSUB 2'b01
`define OPMUL 2'b10
`define OPDIV 2'b11
Mux2 #(12) muxResult (
.a_in({6'b0, adder_out}),
.b_in({6'b0, suber_out}),
.c_in(muler_out),
.d_in(diver_out),
.s_in(op_in),
.s_out(c_out)
);
Mux2 #(1) muxOverflow (
.a_in((a_in[5] & b_in[5] & ~c_out[5])
| (~a_in[5] & ~b_in[5] & c_out[5])),
.b_in((a_in[5] & tc_a_out[5] & ~c_out[5])
| (~a_in[5] & ~tc_a_out[5] & c_out[5])),
.c_in(1'b0),
/*
.c_in((a_in[5] & b_in[5] & c_out[11])
| (a_in[5] & ~b_in[5] & ~c_out[11])
| (~a_in[5] & b_in[5] & ~c_out[11])
| (~a_in[5] & ~b_in[5] & c_out[11])),
*/
.d_in(1'b0),
.s_in(op_in),
.s_out(overflow)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, mon_cost; vector<tuple<int, int, int>> friends; const long long oo = 1LL << 60; void solve() { cin >> n >> m >> mon_cost; friends.resize(n); for (int i = 0; i < n; ++i) { int x, k, num; cin >> x >> k >> num; int mask = 0; for (int j = 0; j < num; ++j) { int y; cin >> y; y--; mask = mask | (1 << y); } friends[i] = tie(x, k, mask); } sort(friends.begin(), friends.end(), [](tuple<int, int, int> lhs, tuple<int, int, int> rhs) { return get<1>(lhs) < get<1>(rhs); }); vector<vector<long long>> dp(2, vector<long long>(1 << m, oo)); int x, k, tasks; tie(x, k, tasks) = friends[0]; dp[1][0] = 0; dp[1][tasks] = x; long long ans = oo; for (int i = 0; i < n; ++i) { int cur = i % 2; int prev = cur ^ 1; tie(x, k, tasks) = friends[i]; for (int mask = 0; mask < (1 << m); ++mask) { dp[cur][mask | tasks] = min(dp[cur][mask | tasks], dp[prev][mask] + x); dp[cur][mask] = min(dp[cur][mask], dp[prev][mask]); } long long val = dp[cur][(1 << m) - 1] + 1LL * k * mon_cost; ans = min(ans, val); } if (ans < oo) { cout << ans << n ; } else { cout << -1 << n ; } } int main() { solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_PP_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long a[300005], ans; int n, num[300005], cnt[2] = {1}, sum[300005]; int change(long long x) { int ans = 0; while (x) { ans += (x % 2); x /= 2; } return ans; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); num[i] = change(a[i]); sum[i] = sum[i - 1] + num[i]; ans += cnt[sum[i] % 2]; int maxn = 0; for (int j = i, k = i + 1; j >= 1 && j >= i - 64; j--) { while (k > j) { k--; maxn = max(maxn, num[k]); } if (maxn * 2 > sum[i] - sum[j - 1] && (sum[i] - sum[j - 1]) % 2 == 0) ans--; } cnt[sum[i] % 2]++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int x, k; cin >> x >> k; long long int temp = k % 4; long long int i = 1; while (temp--) { if (x % 2) { x += ((k / 4) * 4) + i; } else { x -= ((k / 4) * 4) + i; } i++; } cout << x << endl; } return 0; }
|
#include <bits/stdc++.h> unsigned *G[222222], Ga[222222], Gi[222222]; void add(unsigned i, unsigned j) { if (Ga[i] == Gi[i]) { if (!Ga[i]) G[i] = (unsigned *)calloc(Ga[i] = 1, sizeof(unsigned)); else G[i] = (unsigned *)realloc(G[i], (Ga[i] <<= 1) * sizeof(unsigned)); } G[i][Gi[i]++] = j; return; } unsigned P[222222], D[222222], IL[222222], mi, ma; void F(unsigned n, unsigned p, unsigned d) { if (!d) { mi = -1; ma = 0; } unsigned i, j; P[n] = p; D[n] = d; if (IL[n]) { if (mi > d) mi = d; if (ma < d) ma = d; } for (i = Gi[n]; i--;) if ((j = G[n][i]) != p) F(j, n, d + 1); return; } unsigned L[222222], Li, Q[9], Qi; int main() { unsigned n, i, j, k, x; scanf( %u , &n); for (k = n; --k;) { scanf( %u%u , &i, &j); add(i, j); add(j, i); } for (i = 0; ++i <= n;) if (Gi[i] == 1) IL[L[Li++] = i] = 1; F(L[0], 0, 0); for (i = j = k = 0; ++i <= n;) if (D[i] > k) k = D[j = i]; F(j, 0, 0); for (i = j = k = 0; ++i <= n;) if (D[i] > k) k = D[j = i]; for (i = k >> 1; i--;) j = P[j]; if (k & 1) { F(i = P[j], j, 0); if (mi != ma) goto NO; F(j, i, 0); if (mi != ma) goto NO; } else { for (i = Gi[j]; i--;) { F(G[j][i], j, 0); if (mi != ma) goto NO; for (x = -1; ++x < Qi;) if (Q[x] == mi) goto tebak; Q[Qi++] = mi; if (Qi > 2) goto NO; tebak:; } for (k = 0, x = -1; ++x < Qi;) k += Q[x] + 1; } while (!(k & 1)) k >>= 1; printf( %u n , k); return 0; NO:; printf( -1 n ); return 0; }
|
module main;
parameter CACHE_RAM = 128;
parameter ADR_WIDTH = 7;
reg [31:0] buff[0:CACHE_RAM], data_o, data_i;
reg [ADR_WIDTH-1:0] addr;
reg clk, rst, wr;
(* ivl_synthesis_on *)
always @(posedge clk)
if (wr) buff[addr] <= data_i;
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
begin
if (rst)
data_o <= 32'h0;
else if (wr)
data_o <= data_i;
else
data_o <= buff[addr];
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 0;
wr = 1;
for (addr = 0 ; addr < 64 ; addr = addr+1) begin
data_i <= addr;
#1 clk = 1;
#1 clk = 0;
if (data_o !== data_i) begin
$display("FAILED -- write addr=0x%h, data_o=%h", addr, data_o);
$finish;
end
end
wr = 0;
data_i = 32'hx;
for (addr = 0 ; addr < 64 ; addr = addr+1) begin
#1 clk = 1;
#1 clk = 0;
if (data_o !== addr) begin
$display("FAILED -- read addr=0x%h, data_o=%h", addr, data_o);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int r = 0, c = 0; string str; cin >> str; if (str.length() > 2) { for (int i = 0; i < str.length() - 2; i++) { if (str[i] == Q ) { for (int j = i + 1; j < str.length() - 1; j++) { if (str[j] == A ) r++; if (r > 0) { for (int k = j + 1; k < str.length(); k++) { if (str[k] == Q ) { c++; } r = 0; } } } } } } printf( %d , c); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; long long k = 0, m = 1; while (t > 0) { if (t % 10 == 4) { k = k + m; } else { k = k + 2 * m; } m = m * 2; t = t / 10; } cout << k; }
|
#include <bits/stdc++.h> using namespace std; bool isPrime(long long n) { if (n <= 1) return false; for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } long long mod = 1000000007; int main() { long long i, j, k = 0, n, m = 0, a[300001], b[300001], t = 0, ans = 0, i1 = 0, i2, h, p1, p2 = 0, q, l, f, c[2], mi; char c1, c2, d[1001][1001]; string s; double j1; string e, dz; std::vector<pair<long long, long long>> vect; vector<long long> v; map<string, long long> m1; map<string, long long>::iterator itr; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); j = 1; for (i = 0; i < n; i++) { if (a[i] >= j) { t++; j++; } } cout << t; }
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#include <bits/stdc++.h> template <int MOD> struct Integral { int v_ = 0; template <typename T> Integral(T v) : v_(norm(v)) { static_assert(std::is_integral<T>::value, input should be an integral. ); } Integral() = default; ~Integral() = default; template <typename T> T norm(T v) const { if (v >= MOD) v -= MOD; if (v < 0) v += MOD; if (v >= MOD || v < 0) v = (v % MOD + MOD) % MOD; return v; } int val() const { return v_; } Integral operator+(const Integral& rhs) const { return Integral(val() + rhs.val()); } Integral operator-(const Integral& rhs) const { return Integral(val() - rhs.val()); } Integral operator*(const Integral& rhs) const { return Integral(val() * 1LL * rhs.val()); } Integral operator/(const Integral& rhs) const { return *this * rhs.inv(); } Integral& operator+=(const Integral& rhs) { return *this = *this + rhs; } Integral& operator-=(const Integral& rhs) { return *this = *this - rhs; } Integral& operator*=(const Integral& rhs) { return *this = *this * rhs; } Integral& operator/=(const Integral& rhs) { return *this = *this / rhs; } bool operator==(const Integral& rhs) const { return val() == rhs.val(); } bool operator!=(const Integral& rhs) const { return !(*this == rhs); } const Integral operator-() const { return Integral(-val()); } const Integral operator++() { v_ = norm(v_ + 1); return *this; } const Integral operator++(int) { Integral ret = *this; ++(*this); return ret; } const Integral operator--() { v_ = norm(v_ - 1); return *this; } const Integral operator--(int) { Integral ret = *this; --(*this); return ret; } Integral power(long long b) const { long long ret = 1 % MOD, a = v_; for (; b; b >>= 1, a = a * a % MOD) if (b & 1) ret = ret * a % MOD; return ret; } Integral inv() const { return power(MOD - 2); } }; template <int MOD> std::string to_string(const Integral<MOD>& v) { return std::string( Integral{v= ) + std::to_string(v.val()) + } ; } template <int MOD, bool kAllowBruteForce = false> struct Binomial { std::vector<Integral<MOD>> factor, inv_factor; explicit Binomial(int n = 0) : factor(n + 1), inv_factor(n + 1) { factor[0] = 1; for (int i = 1; i <= n; ++i) factor[i] = factor[i - 1] * i; inv_factor[n] = factor[n].inv(); for (int i = n; i >= 1; --i) inv_factor[i - 1] = inv_factor[i] * i; } ~Binomial() = default; template <typename T> Integral<MOD> operator()(T a, T b) const { if (a < b || b < 0) return 0; if (a < factor.size()) return factor[a] * inv_factor[b] * inv_factor[a - b]; if constexpr (!kAllowBruteForce) { throw std::out_of_range( Binomial ); } else { b = std::min(b, a - b); Integral<MOD> ret = 1; for (T i = 1; i <= b; ++i) ret = ret * (a + 1 - i) / i; return ret; } } }; template <int MOD> struct PowerTable { std::vector<Integral<MOD>> arr; PowerTable(int n, const Integral<MOD>& g) : arr(n + 1) { arr[0] = 1; arr[1] = g; for (int i = 2; i < arr.size(); ++i) arr[i] = arr[i - 1] * arr[1]; } template <typename T> Integral<MOD> power(T index) const { if (0 <= index && index < arr.size()) return arr[index]; return arr[1].power(index); } }; const int MOD = 1e9 + 7; using Mint = Integral<MOD>; using Binom = Binomial<MOD>; Binom binom(200); const int kN = 50 + 5; const int kM = 2500 + 5; Mint f[kN][kN][kM]; Mint g[kN][kN][kN][2]; Mint h[kN][kM]; Mint q[kN][kM]; int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::istream& reader = std::cin; int n, T; reader >> n >> T; std::vector<std::vector<int>> ts(3); for (int i = 0; i < n; ++i) { int t, g; reader >> t >> g; ts[g - 1].emplace_back(t); } int m[3] = {}; for (int i = 0; i < 3; ++i) m[i] = ts[i].size(); f[0][0][0] = 1; for (int t : ts[0]) { for (int i = m[0] - 1; i >= 0; --i) for (int k = T - t; k >= 0; --k) f[i + 1][0][k + t] += f[i][0][k]; } for (int t : ts[1]) { for (int j = m[1] - 1; j >= 0; --j) for (int i = m[0]; i >= 0; --i) for (int k = T - t; k >= 0; --k) f[i][j + 1][k + t] += f[i][j][k]; } g[0][0][0][0] = 1; for (int i = 0; i <= m[0]; ++i) { for (int j = 0; j <= m[1]; ++j) { for (int k = 0; k <= i + j; ++k) { for (int r = 0; r < 2; ++r) if (g[i][j][k][r].val()) { Mint val = g[i][j][k][r].val(); g[i + 1][j][k + 1][0] += val; g[i][j + 1][k + 1][1] += val; if (k > 0) { if (r == 0) g[i][j + 1][k][1] += val; if (r == 1) g[i + 1][j][k][0] += val; } } } } } for (int i = 0; i <= m[0]; ++i) { for (int j = 0; j <= m[1]; ++j) { for (int k = 0; k <= i + j; ++k) { for (int w = 0; w < 2; ++w) if (g[i][j][k][w].val()) { for (int r = 0; r <= T; ++r) if (f[i][j][r].val()) { q[k][r] += f[i][j][r] * g[i][j][k][w] * binom.factor[i] * binom.factor[j]; } } } } } h[0][0] = 1; for (int t : ts[2]) { for (int j = m[2] - 1; j >= 0; --j) for (int k = T - t; k >= 0; --k) h[j + 1][k + t] += h[j][k]; } Mint result = 0; for (int k = 0; k <= m[0] + m[1]; ++k) { for (int t = 0; t <= T; ++t) if (q[k][t].val()) { 1145141919810; for (int c = std::max(0, k - 1); c <= k + 1 && c <= m[2]; ++c) { if (!h[c][T - t].val()) continue; Mint coef = c == k ? 2 : 1; result += coef * q[k][t] * h[c][T - t] * binom.factor[c]; 1145141919810; } } } printf( %d n , result.val()); }
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#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 23; const int INF = 1e9 + 23; const int MOD = 1e9 + 7; struct Mada { long long x, h, p; }; Mada mada[MAX_N]; stack<Mada> Dane; int dp[MAX_N]; int n; bool cmp(Mada a, Mada b) { return a.x < b.x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> mada[i].x >> mada[i].h; mada[i].p = i; } sort(mada + 1, mada + 1 + n, cmp); dp[mada[n].p] = 1; Dane.push(mada[n]); for (int i = n - 1; i >= 1; i--) { long long res = 0; while (!Dane.empty()) { if (Dane.top().x > mada[i].h + mada[i].x - 1) { break; } res += dp[Dane.top().p]; Dane.pop(); } dp[mada[i].p] = res + 1; Dane.push(mada[i]); } for (int i = 1; i <= n; i++) { cout << dp[i] << ; } cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k; long long a[200010]; long long b[200010]; int s[200010]; long long ans; bool check(long long val) { memset(s, 0, sizeof(s)); int num = k; for (int i = 1; i <= n; i++) { if (!b[i]) { continue; } long long sum = a[i]; s[min(sum / b[i] + 1, 1ll * (k + 1))]++; while (sum < 1ll * k * b[i]) { if (!num) { break; } sum += val; s[min(sum / b[i] + 1, 1ll * (k + 1))]++; num--; } } for (int i = 1; i <= k; i++) { s[i] += s[i - 1]; if (s[i] > i) { return false; } } return true; } int main() { scanf( %d%d , &n, &k); k--; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } for (int i = 1; i <= n; i++) { scanf( %lld , &b[i]); } long long l = 0, r = 2000000000000ll; while (l <= r) { long long mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else { l = mid + 1; } } if (!ans) { printf(check(0) ? 0 : -1 ); } else { printf( %lld , ans); } }
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#include <bits/stdc++.h> using namespace std; const int N = 2005, M = N * N; bool vis[N]; char s[N][2][25]; int n, m, dfn[N], low[N], tt, S[N], col[N]; int hd[N], V[M], nx[M], fs[N], q[N], id[N], in[N]; vector<int> e[N]; void add(int u, int v) { nx[++tt] = hd[u]; V[hd[u] = tt] = v; } void tarjan(int x) { dfn[x] = low[x] = ++tt; S[++S[0]] = x; vis[x] = 1; for (int i = hd[x]; i; i = nx[i]) { if (!dfn[V[i]]) tarjan(V[i]), low[x] = min(low[x], low[V[i]]); else if (vis[V[i]]) low[x] = min(low[x], dfn[V[i]]); } if (dfn[x] == low[x]) { col[x] = ++col[0]; while (S[S[0]] != x) vis[S[S[0]]] = 0, col[S[S[0]--]] = col[0]; S[0]--; vis[x] = 0; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %s%s , s[i][0], s[i][1]); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { bool J = 1; for (int k = 0; k < 3; k++) J &= (s[i][0][k] == s[j][0][k]); if (J) add(i, i + n), add(j, j + n); J = (s[i][1][0] == s[j][1][0]); for (int k = 0; k < 2; k++) J &= (s[i][0][k] == s[j][0][k]); if (J) add(i + n, j), add(j + n, i); J = (s[i][0][2] == s[j][1][0]); for (int k = 0; k < 2; k++) J &= (s[i][0][k] == s[j][0][k]); if (J) add(i, j), add(j + n, i + n); J = (s[i][1][0] == s[j][0][2]); for (int k = 0; k < 2; k++) J &= (s[i][0][k] == s[j][0][k]); if (J) add(j, i), add(i + n, j + n); } tt = 0; for (int i = 1; i <= n + n; i++) if (!dfn[i]) tarjan(i); for (int i = 1; i <= n; i++) if (col[i] == col[i + n]) { puts( NO ); return 0; } puts( YES ); for (int i = 1; i <= n + n; i++) for (int j = hd[i]; j; j = nx[j]) if (col[V[j]] != col[i]) e[col[i]].push_back(col[V[j]]), in[col[V[j]]]++; int l = 1, r = 0; for (int i = 1; i <= col[0]; i++) if (!in[i]) q[id[i] = ++r] = i; while (l <= r) { int x = q[l++], z = e[x].size(); for (int v, i = 0; i < z; i++) if (!(--in[v = e[x][i]])) q[id[v] = ++r] = v; } for (int i = 1; i <= n; i++) { if (id[col[i]] < id[col[i + n]]) s[i][0][2] = s[i][1][0]; for (int k = 0; k < 3; k++) putchar(s[i][0][k]); puts( ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main(){ //freopen( input.inp , r ,stdin); //freopen( output.out , w ,stdout); ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--){ int a,b; cin >> a >> b; int ans = 0; for (int i = 0; i < min(a,b);i++) ans+=2; if (a != b){ for (int i = min(a,b); i < max(a,b);i++){ ans+=2; } ans--; } cout << ans << endl; } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 11:23:39 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_txn0, srio_txp0,
srio_txn1, srio_txp1, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_txn0,srio_txp0,srio_txn1,srio_txp1,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 2019, mod = 998244353; int n, m, ans, f[N << 1][N], g[N << 1][N]; int qpow(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % mod; a = 1ll * a * a % mod, b >>= 1; } return ret; } int main() { scanf( %d%d%d , &n, &m, &ans); f[0][0] = 1; for (int i = 1; i <= 2 * n; i++) for (int j = 0; j <= min(i, n); j++) { if (!j) f[i][j] = f[i - 1][j + 1], g[i][j] = g[i - 1][j + 1]; else f[i][j] = (f[i - 1][j - 1] + 1ll * (j + 1) * f[i - 1][j + 1]) % mod, g[i][j] = (g[i - 1][j - 1] + 1ll * (j + 1) * g[i - 1][j + 1]) % mod; if (j >= m) g[i][j] = (f[i][j] + g[i][j]) % mod; } ans = 1ll * ans * qpow(1ll * f[2 * n][0] * (2 * n + 1) % mod, mod - 2) % mod * g[2 * n][0] % mod; printf( %d , ans); }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, N = 1e5 + 5; int n, c[N], x; long long dp[N][2]; vector<int> g[N]; void dfs(int v) { dp[v][0] = 1LL; for (int u : g[v]) { dfs(u); (dp[u][0] += dp[u][1]) %= mod; dp[v][1] = (dp[v][1] * dp[u][0] + dp[v][0] * dp[u][1]) % mod; dp[v][0] = (dp[v][0] * dp[u][0]) % mod; } if (c[v]) { dp[v][1] = dp[v][0]; dp[v][0] = 0; } } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { cin >> x; g[x].push_back(i); } for (int i = 0; i < n; i++) cin >> c[i]; dfs(0); cout << dp[0][1]; }
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#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; const int mod7 = 1e9 + 7; const int mod = 1e9 + 7; void read(int &a) { a = 0; int d = 1; char ch; while (ch = getchar(), ch > 9 || ch < 0 ) if (ch == - ) d = -1; a = ch ^ 48; while (ch = getchar(), ch >= 0 && ch <= 9 ) a = (a << 3) + (a << 1) + (ch ^ 48); a *= d; } int b[N][35], p[N][35]; void ins(int x, int v) { for (register int i = 0; i <= 30; i++) { p[x][i] = p[x - 1][i]; b[x][i] = b[x - 1][i]; } int now = x; for (register int i = 30; i >= 0; i--) { if (v & (1 << i)) { if (!b[x][i]) { b[x][i] = v; p[x][i] = now; return; } if (p[x][i] < now) { swap(b[x][i], v); swap(p[x][i], now); } v ^= b[x][i]; } } } int query(int l, int r) { int ans = 0; for (register int i = 30; i >= 0; i--) if (p[r][i] >= l && (b[r][i] ^ ans) > ans) ans ^= b[r][i]; return ans; } int main() { int n; read(n); for (register int i = 1, x; i <= n; i++) { read(x); ins(i, x); } int T; read(T); while (T--) { int l, r; read(l), read(r); printf( %d n , query(l, r)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int a[100005], sg[100005 * 4], lz[100005 * 4], res, x, y, z, n; void lazy(long long int low, long long int high, long long int pos) { sg[pos] += lz[pos]; if (low != high) lz[pos * 2 + 1] += lz[pos], lz[pos * 2 + 2] += lz[pos]; lz[pos] = 0; } void update(long long int low, long long int high, long long int pos, long long int qlow, long long int qhigh, long long int va) { lazy(low, high, pos); if (qlow > high || qhigh < low) return; if (qlow <= low && high <= qhigh) { sg[pos] += va; if (low != high) lz[pos * 2 + 1] += va, lz[pos * 2 + 2] += va; return; } long long int mid = (high + low) / 2; update(low, mid, pos * 2 + 1, qlow, qhigh, va); update(mid + 1, high, pos * 2 + 2, qlow, qhigh, va); sg[pos] = max(sg[pos * 2 + 1], sg[pos * 2 + 2]); } long long int ans(long long int low, long long int high, long long int pos) { lazy(low, high, pos); if (sg[pos] <= 0) return -1; if (low == high) return a[low]; long long int mid = (high + low) / 2; lazy(low, mid, pos * 2 + 1), lazy(mid + 1, high, pos * 2 + 2); if (sg[pos * 2 + 2] > 0) return ans(mid + 1, high, pos * 2 + 2); else return ans(low, mid, pos * 2 + 1); } int main() { scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld%lld , &x, &y); x--; if (y == 0) y = -1; else scanf( %lld , &z), a[x] = z; update(0, n, 0, 0, x, y); res = ans(0, n, 0); printf( %lld n , res); } return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { string s; cin >> s; long long n = s.size(); long long an = 0; for (long long i = 0; i < n; i++) { long long r = INT_MAX; for (long long j = i; j <= min((long long)(i + 9), n - 1); j++) { for (long long k = 1; k <= 8; k++) { if (j + 2 * k < n) { if (s[j] == s[j + k] and s[j] == s[j + 2 * k]) { r = min(r, j + 2 * k); } } } } if (r != INT_MAX) an = an + n - r; } cout << an << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int maxn = 2e5 + 10; const int inf = 0x3f3f3f3f; const double eps = 1e-6; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); int n; int l[maxn], r[maxn], t[maxn]; struct node { int id; bool operator<(const node &s) const { if (r[id] != r[s.id]) return r[id] < r[s.id]; else if (l[id] != l[s.id]) return l[id] < l[s.id]; else return id < s.id; } }; bool vis[maxn]; struct e { int x, op, id; bool operator<(const e &s) const { if (x != s.x) return x < s.x; else if (op != s.op) return op > s.op; else return id < s.id; } }; multiset<node> s[2]; set<e> ss; int main() { std::ios::sync_with_stdio(false), cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> l[i] >> r[i] >> t[i]; t[i]--; ss.insert((e){l[i], 1, i}); ss.insert((e){r[i], -1, i}); } int ans = n; for (auto u : ss) { int op = u.op; int id = u.id; if (op == 1) { s[t[id]].insert((node){id}); continue; } if (vis[id]) continue; vis[id] = 1; s[t[id]].erase((node){id}); auto it = s[1 - t[id]].begin(); if (it == s[1 - t[id]].end()) continue; int l1 = l[id]; int r1 = r[id]; int l2 = l[(*it).id]; int r2 = r[(*it).id]; if (max(l1, l2) <= min(r1, r2)) { vis[(*it).id] = 1; ans--; s[1 - t[id]].erase((node){(*it).id}); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e3 + 10, big = 1e18, mod = 1e9 + 7; vector<long long> a[N], now, ans; long long n, x, y, m, maxi; bool vis[N], mp[N][N]; void dfs(long long i) { vis[i] = 1, now.push_back(i); for (int j = 0; j < a[i].size(); j++) if (!vis[a[i][j]]) dfs(a[i][j]); } int main() { cin >> n; cin >> m; while (m--) { cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } cin >> m; while (m--) { cin >> x >> y; mp[x][y] = mp[y][x] = 1; } for (int i = 1; i <= n; i++) if (!vis[i]) { now.clear(); dfs(i); bool check = 1; if (now.size() == 1) maxi = max(1LL, maxi); else { for (int j = 0; j < now.size() - 1; j++) for (int k = j + 1; k < now.size(); k++) if (mp[now[j]][now[k]]) check = 0; if (check) maxi = max((long long)now.size(), maxi); } } cout << maxi; }
|
`timescale 1 ns / 1 ps
module counter_group
(
input selector,
input incrementor,
input reverse,
input clr,
input wire [15:0]cntr_def_0,
input wire [15:0]cntr_def_1,
input wire [15:0]cntr_def_2,
input wire [15:0]cntr_def_3,
input wire [15:0]cntr_def_4,
input wire [15:0]cntr_def_5,
input wire [15:0]cntr_def_6,
input wire [15:0]cntr_def_7,
output wire [15:0]cntr0,
output wire [15:0]cntr1,
output wire [15:0]cntr2,
output wire [15:0]cntr3,
output wire [15:0]cntr4,
output wire [15:0]cntr5,
output wire [15:0]cntr6,
output wire [15:0]cntr7,
output wire [15:0]cntr_sel,
output reg [7:0]cntr_ind
);
reg [2:0] cntr_cur;
reg [15:0] cntrs[7:0];
assign cntr0 = cntrs[0];
assign cntr1 = cntrs[1];
assign cntr2 = cntrs[2];
assign cntr3 = cntrs[3];
assign cntr4 = cntrs[4];
assign cntr5 = cntrs[5];
assign cntr6 = cntrs[6];
assign cntr7 = cntrs[7];
wire [15:0] cntrs_def_int[7:0];
assign cntrs_def_int[0] = cntr_def_0;
assign cntrs_def_int[1] = cntr_def_1;
assign cntrs_def_int[2] = cntr_def_2;
assign cntrs_def_int[3] = cntr_def_3;
assign cntrs_def_int[4] = cntr_def_4;
assign cntrs_def_int[5] = cntr_def_5;
assign cntrs_def_int[6] = cntr_def_6;
assign cntrs_def_int[7] = cntr_def_7;
assign cntr_sel = cntrs[cntr_cur];
wire s = selector | clr | incrementor;
always @(posedge s) begin
if (clr == 1) begin
/* cntrs[cntr_cur] <= 0; */
cntrs[cntr_cur] <= cntrs_def_int[cntr_cur];
end else if (selector == 1) begin
if (reverse == 1)
cntr_cur <= cntr_cur - 1;
else
cntr_cur <= cntr_cur + 1;
end else begin
if (reverse == 1)
cntrs[cntr_cur] <= cntrs[cntr_cur] - 1;
else
cntrs[cntr_cur] <= cntrs[cntr_cur] + 1;
end
end
always @(cntr_cur) begin
case(cntr_cur)
0: cntr_ind <= 8'H01;
1: cntr_ind <= 8'H02;
2: cntr_ind <= 8'H04;
3: cntr_ind <= 8'H08;
4: cntr_ind <= 8'H10;
5: cntr_ind <= 8'H20;
6: cntr_ind <= 8'H40;
7: cntr_ind <= 8'H80;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5; int n, fa[N], p[N], cnt, mk, la[N], size[N]; int getfa(int x) { if (fa[x] == x) return x; return fa[x] = getfa(fa[x]); } void merge(int x, int y) { int fx = getfa(x), fy = getfa(y); if (fx == fy) return; fa[fx] = fy; size[fy] += size[fx]; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) { fa[i] = i; size[i] = 1; if (p[i] == i) { if (!mk) mk = i; else p[i] = mk, cnt++; } } if (!mk) { for (int i = 1; i <= n; i++) merge(i, p[i]); int now = 0; for (int i = 1; i <= n; i++) { if (size[i] > now) { now = size[i]; mk = i; } } for (int i = 1; i <= n; i++) fa[i] = i; p[mk] = mk; cnt++; } for (int i = 1; i <= n; i++) { if (p[i] == i) continue; if (getfa(i) == getfa(p[i])) p[i] = mk, cnt++; merge(i, p[i]); } cout << cnt << endl; for (int i = 1; i <= n; i++) cout << p[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void calc() { long long n, m; cin >> n >> m; vector<pair<long long, long long> > v; vector<long long> a; for (long long i = 0; i < m; i++) { long long ai, bi; cin >> ai >> bi; v.push_back(make_pair(ai, bi)); a.push_back(ai); } sort(a.begin(), a.end()); reverse(a.begin(), a.end()); vector<long long> acc(m + 2); for (long long i = 1; i <= m; i++) { acc[i] = acc[i - 1] + a[i - 1]; } long long ans = -1; for (long long i = 0; i < m; i++) { long long ai = v[i].first; long long bi = v[i].second; long long lo, hi; lo = 0; hi = m; while (lo + 1 != hi) { long long mid = (lo + hi) / 2; if (a[mid] > bi) lo = mid; else hi = mid; } long long curr, rem; if (a[lo] > bi) { curr = ai; rem = n - 1; if (rem > 0) { long long used = min(lo + 1, rem); curr += acc[used]; if (a[used - 1] <= ai) { curr -= ai; rem -= used; rem++; if (used + 1 <= m && a[used] > bi) { rem--; curr += a[used]; } } else { rem -= used; } if (rem > 0) curr += rem * bi; } } else { curr = ai; rem = n - 1; if (rem > 0) curr += rem * bi; } ans = max(ans, curr); } cout << ans << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) calc(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, dp[100000], t; string s; int main() { cin >> s; for (i = 0; i < s.size(); i++) if (s[i] >= a ) { dp[i] = dp[i - 1]; t++; } else dp[i] = min(dp[i - 1] + 1, t); cout << dp[s.size() - 1] << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_TB_V
`define SKY130_FD_SC_MS__OR3B_TB_V
/**
* or3b: 3-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { double x, y; while (cin >> x >> y) { double l; l = sqrt(x * x + y * y); if (l == (int)l) { cout << black << endl; continue; } int z = (int)l; if (z != l) z++; if (x * y >= 0) { if (z % 2) cout << black << endl; else cout << white << endl; } else { if (z % 2 == 0) cout << black << endl; else cout << white << endl; } } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:22:21 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
#include <bits/stdc++.h> int main() { long long n, k; scanf( %lld%lld , &n, &k); if (k < 2) { printf( %lld , n); return 0; } long long s = 1; while (s - 1 < n) s *= 2; printf( %lld , s - 1); }
|
// soc_system_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : control_unit_testbench
// Author : Caleb Fangmeier
// Description : Testbench for the control unit
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module control_unit_testbench
(
// no I/O for the testbench
);
// Wires
reg sys_clk;
reg reset;
integer i;
parameter CLK_PERIOD = 10;
parameter MEM_WORDS = 128;
wire read_req;
wire write_req;
wire [16:0] addr;
wire [31:0] data_o;
reg [31:0] data_i;
reg busy;
/* reg [7:0] mem[0:4096]; // 1k words */
reg [31:0] mem[0:MEM_WORDS-1]; // 1k words
control_unit control_unit_inst (
.clk ( sys_clk ),
.reset ( reset ),
.memory_read_req ( read_req ),
.memory_write_req ( write_req ),
.memory_addr ( addr ),
.memory_data_o ( data_o ),
.memory_data_i ( data_i ),
.memory_busy ( busy )
);
initial i = 0;
initial sys_clk = 1'b0;
always #( CLK_PERIOD/2.0 )
sys_clk = ~sys_clk;
initial reset = 1'b1;
always @( posedge sys_clk ) begin
i = i + 1;
if ( i == 2 )
reset <= 1'b0;
end
initial $readmemh("instructions.txt", mem);
always @(posedge sys_clk or reset) begin
if ( ~reset ) begin
busy <= 0;
if ( read_req ) begin
data_i <= mem[addr>>2];
end
if ( write_req ) begin
mem[addr>>2] <= data_o;
end
end
end
integer j;
reg [7:0] memory [0:15]; // 8 bit memory with 16 entries
initial begin
for (j=0; j<16; j=j+1) begin
memory[j] = j;
end
$writememb("memory_binary.txt", memory);
$writememh("memory_hex.txt", memory);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void sublime() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int main() { sublime(); long long n, i, j; cin >> n; long long arr[n]; for (i = 0; i < n; i++) cin >> arr[i]; if (n <= 2) { cout << 0 << n ; for (i = 0; i < n; i++) cout << arr[i] << ; cout << n ; return 0; } else { sort(arr, arr + n); vector<long long> v; i = 0, j = (n - 1) / 2; if (n & 1) { while (i < (n - 1) / 2 || j < n) { v.push_back(arr[j]); j++; if (i < (n - 1) / 2) { v.push_back(arr[i]); i++; } } } else { j = n / 2; while (i < (n - 1) / 2 || j < n) { v.push_back(arr[j]); j++; if (i < (n - 1) / 2) { v.push_back(arr[i]); i++; } } v.push_back(arr[(n - 1) / 2]); } long long ans = 0; for (i = 1; i < v.size() - 1; i += 2) { if (v[i] < v[i + 1] && v[i] < v[i - 1]) ans++; } cout << ans << n ; for (auto x : v) cout << x << ; cout << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int hy, ay, dy; int hm, am, dm; int h, a, d; cin >> hy >> ay >> dy; cin >> hm >> am >> dm; cin >> h >> a >> d; int res = 1e9; for (int atk = dm + 1; atk <= 200; ++atk) { for (int def = dy; def <= 100; ++def) { int rnd = (hm + atk - dm - 1) / (atk - dm); int h_add = max(0, rnd * max(0, am - def) - hy + 1); int a_add = max(0, atk - ay); int d_add = max(0, def - dy); res = min(res, h_add * h + a_add * a + d_add * d); } } cout << res << endl; return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:11:22 10/17/2012
// Design Name:
// Module Name: pal_generator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define END_COUNT_H 447
`define END_COUNT_V 311
`define HOFFS 0 //328%448
`define VOFFS 0 //48%312
`define BEGIN_LONG_SYNC1 (0 + `HOFFS)
`define END_LONG_SYNC1 (190 + `HOFFS)
`define BEGIN_LONG_SYNC2 (224 + `HOFFS)
`define END_LONG_SYNC2 (414 + `HOFFS)
`define BEGIN_SHORT_SYNC1 (0 + `HOFFS)
`define END_SHORT_SYNC1 (15 + `HOFFS)
`define BEGIN_SHORT_SYNC2 (224 + `HOFFS)
`define END_SHORT_SYNC2 (239 + `HOFFS)
`define BEGIN_HSYNC (0 + `HOFFS)
`define END_HSYNC (32 + `HOFFS)
`define BEGIN_HBLANK (436 + `HOFFS)
`define END_HBLANK (71 + `HOFFS)
`define BEGIN_WSSDATA (77 + `HOFFS)
`define LINE1 (0 + `VOFFS)
`define LINE2 (1 + `VOFFS)
`define LINE3 (2 + `VOFFS)
`define LINE4 (3 + `VOFFS)
`define LINE5 (4 + `VOFFS)
`define LINE23 (22 + `VOFFS)
`define LINE310 (309 + `VOFFS)
`define LINE311 (310 + `VOFFS)
`define LINE312 (311 + `VOFFS)
module pal_sync_generator_progressive (
input wire clk,
input wire wssclk,
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
output wire [8:0] hcnt,
output wire [8:0] vcnt,
output wire [2:0] ro,
output wire [2:0] go,
output wire [2:0] bo,
output wire csync
);
reg [8:0] hc = 9'h000;
reg [8:0] vc = 9'h000;
reg [8:0] rhcnt = 332; //344; //328;
reg [8:0] rvcnt = 248; // era 250
assign hcnt = rhcnt;
assign vcnt = rvcnt;
always @(posedge clk) begin
if (rhcnt == `END_COUNT_H) begin
rhcnt <= 0;
if (rvcnt == `END_COUNT_V)
rvcnt <= 0;
else
rvcnt <= rvcnt + 9'd1;
end
else
rhcnt <= rhcnt + 9'd1;
end
always @(posedge clk) begin
if (hc == `END_COUNT_H) begin
hc <= 0;
if (vc == `END_COUNT_V)
vc <= 0;
else
vc <= vc + 9'd1;
end
else
hc <= hc + 9'd1;
end
reg rsync = 1;
reg in_visible_region = 1;
assign csync = rsync;
always @(posedge clk) begin
if (hc == `BEGIN_LONG_SYNC1 && (vc == `LINE1 ||
vc == `LINE2 ||
vc == `LINE3 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_LONG_SYNC1 && (vc == `LINE1 ||
vc == `LINE2 ||
vc == `LINE3 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_LONG_SYNC2 && (vc == `LINE1 ||
vc == `LINE2 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_LONG_SYNC2 && (vc == `LINE1 ||
vc == `LINE2 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_SHORT_SYNC1 && (vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_SHORT_SYNC1 && (vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_SHORT_SYNC2 && (vc == `LINE3 ||
vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_SHORT_SYNC2 && (vc == `LINE3 ||
vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (vc != `LINE1 &&
vc != `LINE2 &&
vc != `LINE3 &&
vc != `LINE4 &&
vc != `LINE5 &&
vc != `LINE310 &&
vc != `LINE311 &&
vc != `LINE312 ) begin
if (hc == `BEGIN_HBLANK)
in_visible_region <= 0;
else if (hc == `BEGIN_HSYNC)
rsync <= 0;
else if (hc == `END_HSYNC)
rsync <= 1;
else if (hc == `END_HBLANK) begin
in_visible_region <= 1;
end
end
end
// see WSS standard description PDF, by ETSI
// v- Run-in code v- Start code v- Group 1 v- Group 2 v- Group 3 v- Group 4
reg [136:0] wss_data = 137'b11111000111000111000111000111000111100011110000011111000111000111000111111000111000000111000111000111000111000111000111000111000111000111;
reg wss_mstate = 0;
reg [7:0] wss_cnt = 136;
wire wss_output = (wss_mstate == 0)? 0 : wss_data[136];
always @(posedge wssclk) begin
case (wss_mstate)
0: begin
if (vc == `LINE23 && (hc == `BEGIN_WSSDATA || hc == `BEGIN_WSSDATA+1))
wss_mstate <= 1;
end
1: begin
wss_data <= {wss_data[135:0],wss_data[136]};
if (wss_cnt != 0)
wss_cnt <= wss_cnt - 8'd1;
else begin
wss_cnt <= 136;
wss_mstate <= 0;
end
end
endcase
end
assign ro = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : ri;
assign go = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : gi;
assign bo = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : bi;
// (* IOB = "TRUE" *) reg [2:0] rro;
// (* IOB = "TRUE" *) reg [2:0] rgo;
// (* IOB = "TRUE" *) reg [2:0] rbo;
// assign ro = rro;
// assign go = rgo;
// assign bo = rbo;
// always @(posedge clk) begin
// rro <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : ri;
// rgo <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : gi;
// rbo <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : bi;
// end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
reg [31:0] v32 [2];
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\n",$time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
// Increments
v32[2] = 12; v32[2]++; if (v32[2] != 13) $stop;
v32[2] = 12; ++v32[2]; if (v32[2] != 13) $stop;
v32[2] = 12; v32[2]--; if (v32[2] != 11) $stop;
v32[2] = 12; --v32[2]; if (v32[2] != 11) $stop;
v32[2] = 12; v32[2] += 2; if (v32[2] != 14) $stop;
v32[2] = 12; v32[2] -= 2; if (v32[2] != 10) $stop;
v32[2] = 12; v32[2] *= 2; if (v32[2] != 24) $stop;
v32[2] = 12; v32[2] /= 2; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] &= 6; if (v32[2] != 4) $stop;
v32[2] = 12; v32[2] |= 15; if (v32[2] != 15) $stop;
v32[2] = 12; v32[2] ^= 15; if (v32[2] != 3) $stop;
v32[2] = 12; v32[2] >>= 1; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] <<= 1; if (v32[2] != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module main;
initial begin
if (1.0a != 1.0e-18) begin
$display("FAILED -- 1.0a = %0.19g", 1.0a);
$finish;
end
if (1.0f != 1.0e-15) begin
$display("FAILED -- 1.0f = %0.19g", 1.0f);
$finish;
end
if (1.0p != 1.0e-12) begin
$display("FAILED -- 1.0p = %0.19g", 1.0p);
$finish;
end
if (1.0n != 1.0e-9) begin
$display("FAILED -- 1.0n = %0.19g", 1.0n);
$finish;
end
if (1.0u != 1.0e-6) begin
$display("FAILED - 1.0u = %0.19g", 1.0u);
$finish;
end
if (1.0m != 1.0e-3) begin
$display("FAILED -- 1.0m = %0.19g", 1.0m);
$finish;
end
if (1.0k != 1.0e3) begin
$display("FAILED -- 1.0k = %0.19g", 1.0k);
$finish;
end
if (1.0K != 1000.0) begin
$display("FAILED -- 1.0K = %f", 1.0K);
$finish;
end
if (1.0M != 1_000_000.0) begin
$display("FAILED -- 1.0M = %f", 1.0M);
$finish;
end
if (1.0G != 1_000_000_000.0) begin
$display("FAILED -- 1.0G = %f", 1.0G);
$finish;
end
if (1.0T != 1_000_000_000_000.0) begin
$display("FAILED -- 1.0T = %f", 1.0T);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
`begin_keywords "VAMS-2.3"
module t (/*autoarg*/
// Inputs
clk, in
);
input clk;
input [15:0] in;
wreal aout;
integer cyc=0;
real vin;
wreal vpass;
through through (.vin, .vpass);
real gnd;
wire out;
within_range within_range (/*AUTOINST*/
// Interfaces
.vpass (vpass),
.gnd (gnd),
// Outputs
.out (out));
// wreal bus declaration
wreal vin_upper_bus[1:0];
// wreal nets declaration
wreal vout_split_0;
wreal vout_split_1;
wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]),
.vout_split_0(vout_split_0),
.vout_split_1(vout_split_1));
// implicit declaration of wreal
`ifdef VERILATOR
wreal wreal_implicit_net; // implicit declaration of wreal not supported yet
`endif
// verilator lint_off IMPLICIT
first_level first_level(.in(cyc[0]), .out(wreal_implicit_net));
// verilator lint_on IMPLICIT
parameter real lsb = 1;
// verilator lint_off WIDTH
assign aout = $itor(in) * lsb;
// verilator lint_on WIDTH
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n",$time, cyc, out, vin, gnd, within_range.in_int);
`endif
if (cyc==0) begin
// Setup
gnd = 0.0;
vin = 0.2;
end
else if (cyc==2) begin
if (out != 0) $stop;
end
else if (cyc==3) begin
gnd = 0.0;
vin = 0.6;
end
else if (cyc==4) begin
if (out != 1) $stop;
end
else if (cyc==5) begin
gnd = 0.6;
vin = 0.8;
end
else if (cyc==6) begin
if (out != 0) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module through
(input wreal vin,
output wreal vpass);
assign vpass = vin;
endmodule
module within_range
(input wreal vpass,
input wreal gnd,
output out);
parameter real V_MIN = 0.5;
parameter real V_MAX = 10;
wreal in_int = vpass - gnd;
assign out = (V_MIN <= in_int && in_int <= V_MAX);
endmodule
module wreal_bus
(input wreal vin_bus [1:0],
output wreal vout_split_0,
output wreal vout_split_1);
assign vout_split_0 = vin_bus[0];
assign vout_split_1 = vin_bus[1];
endmodule
module first_level
(input in,
`ifdef VERILATOR
output wreal out
`else
output out // Implicity becomes real
`endif
);
second_level second_level(.in(in), .out(out));
endmodule
module second_level(in, out);
input in;
output out;
wreal out;
assign out = in ? 1.23456: 7.8910;
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy ()
* Description: Common Card Control Registers (CCCR)
* Controls many aspects of the card.
* Define values are values that do not change with implementation, for
* for example: CCCR version number and SDIO version number
* Parameter values change with every implementation, examples include
* Buffer depth and function numbers
*
* Changes:
*/
`include "sdio_cia_defines.v"
module sdio_cccr (
input clk,
input rst,
input i_activate,
input i_write_flag,
input [7:0] i_address,
input i_data_stb,
input [7:0] i_data_in,
output [7:0] o_data_out,
//Function Interface
output reg [7:0] o_func_enable,
input [7:0] i_func_ready,
output reg [7:0] o_func_int_enable,
input [7:0] i_func_int_pending,
output reg o_soft_reset,
output reg [2:0] o_func_abort_stb,
output reg o_en_card_detect_n,
output reg o_en_4bit_block_int, /* Enable interrupts durring 4-bit block data mode */
input i_data_bus_busy,
output reg o_bus_release_req_stb,
output reg [3:0] o_func_select,
input i_data_read_avail,
input [7:0] i_func_exec_status,
input [7:0] i_func_ready_for_data,
output reg [15:0] o_f0_block_size,
output o_1_bit_mode,
output o_4_bit_mode,
output o_8_bit_mode,
output o_sdr_12,
output o_sdr_25,
output o_sdr_50,
output o_ddr_50,
output o_sdr_104,
output o_driver_type_a,
output o_driver_type_b,
output o_driver_type_c,
output o_driver_type_d,
output reg o_enable_spi_interrupt,
output reg o_enable_async_interrupt
);
//local parameters
localparam IDLE = 4'h0;
localparam READ = 4'h1;
localparam WRITE = 4'h2;
//registes/wires
reg [1:0] driver_type;
reg [3:0] state;
wire [7:0] cccr_map [0:22];
reg [1:0] bus_width;
reg [2:0] bus_speed_select;
reg [2:0] abort_sel;
wire [17:0] reg_addr;
wire [17:0] main_cis_addr;
//wire [7:0] cccr_value;
//submodules
//asynchronous logic
assign main_cis_addr = `MAIN_CIS_START_ADDR;
//assign cccr_value = cccr_map[i_address];
assign o_data_out = cccr_map[i_address];
assign o_1_bit_mode = (bus_width == `D1_BIT_MODE);
assign o_4_bit_mode = (bus_width == `D4_BIT_MODE);
assign o_8_bit_mode = (bus_width == `D8_BIT_MODE);
assign o_sdr_12 = (bus_speed_select == `SDR12);
assign o_sdr_25 = (bus_speed_select == `SDR25);
assign o_sdr_50 = (bus_speed_select == `SDR50);
assign o_ddr_50 = (bus_speed_select == `DDR50);
assign o_sdr_104 = (bus_speed_select == `SDR104);
assign o_driver_type_a = (driver_type == `DRIVER_TYPE_A);
assign o_driver_type_b = (driver_type == `DRIVER_TYPE_B);
assign o_driver_type_c = (driver_type == `DRIVER_TYPE_C);
assign o_driver_type_d = (driver_type == `DRIVER_TYPE_D);
//Read Only
assign cccr_map[`CCCR_SDIO_REV_ADDR ] = {`SDIO_VERSION, `CCCR_FORMAT};
assign cccr_map[`SD_SPEC_ADDR ] = {4'h0, `SD_PHY_VERSION};
assign cccr_map[`IO_FUNC_ENABLE_ADDR ] = o_func_enable;
assign cccr_map[`IO_FUNC_READY_ADDR ] = i_func_ready;
assign cccr_map[`INT_ENABLE_ADDR ] = o_func_int_enable;
assign cccr_map[`INT_PENDING_ADDR ] = i_func_int_pending;
assign cccr_map[`IO_ABORT_ADDR ] = {4'h0, o_soft_reset, abort_sel};
assign cccr_map[`BUS_IF_CONTROL_ADDR ] = {o_en_card_detect_n, `SCSI, 2'b00, o_enable_spi_interrupt, `S8B, bus_width};
assign cccr_map[`CARD_COMPAT_ADDR ] = {`S4BLS, `LSC, o_en_4bit_block_int, `S4MI, `SBS, `SRW, `SMB, `SDC};
assign cccr_map[`CARD_CIS_LOW_ADDR ] = main_cis_addr[7:0];
assign cccr_map[`CARD_CIS_MID_ADDR ] = main_cis_addr[15:8];
assign cccr_map[`CARD_CIS_HIGH_ADDR ] = {6'b000000, main_cis_addr[17:16]};
assign cccr_map[`BUS_SUSPEND_ADDR ] = {6'b000000, o_bus_release_req_stb, i_data_bus_busy};
assign cccr_map[`FUNC_SELECT_ADDR ] = {i_data_read_avail, 3'b000, o_func_select};
assign cccr_map[`EXEC_SELECT_ADDR ] = {i_func_exec_status};
assign cccr_map[`READY_SELECT_ADDR ] = {i_func_ready_for_data};
assign cccr_map[`FN0_BLOCK_SIZE_0_ADDR] = {o_f0_block_size[7:0]};
assign cccr_map[`FN0_BLOCK_SIZE_1_ADDR] = {o_f0_block_size[15:8]};
assign cccr_map[`POWER_CONTROL_ADDR ] = {4'h0, `TPC,`EMPC, `SMPC};
assign cccr_map[`BUS_SPD_SELECT_ADDR ] = {4'h0, bus_speed_select, `SHS};
assign cccr_map[`UHS_I_SUPPORT_ADDR ] = {5'h0, `SSDR50, `SSDR104, `SSDR50};
assign cccr_map[`DRIVE_STRENGTH_ADDR ] = {2'b00, driver_type, 1'b0, `SDTC, `SDTC, `SDTA};
assign cccr_map[`INTERRUPT_EXT_ADDR ] = {6'h00, o_enable_async_interrupt, `SAI};
//synchronous logic
always @ (posedge clk) begin
//De-assert strobes
o_soft_reset <= 0;
o_func_abort_stb <= 8'h0;
abort_sel <= 0;
o_bus_release_req_stb <= 0;
if (rst) begin
state <= IDLE;
o_func_enable <= 8'h0; //No functions are enabled
o_func_int_enable <= 8'h0; //No function interrupts are enabled
o_en_4bit_block_int <= 0;
o_en_card_detect_n <= 0;
o_en_4bit_block_int <= 0;
o_en_4bit_block_int <= 0; //Do not enable this in SDR50, SDR104, DDR50 modes
o_func_select <= 0;
o_f0_block_size <= 0; //Max Block Size is set by host
bus_speed_select <= 0;
driver_type <= 0;
o_enable_async_interrupt<= 0;
o_enable_spi_interrupt <= 0;
bus_width <= 0;
end
else begin
if (abort_sel == 0) begin
o_func_abort_stb <= 0;
end
else begin
o_func_abort_stb[abort_sel] <= 1;
end
if (i_activate) begin
if (i_data_stb) begin
if (i_write_flag) begin
case (i_address)
`IO_FUNC_ENABLE_ADDR:
o_func_enable <= i_data_in;
`INT_ENABLE_ADDR:
o_func_int_enable <= i_data_in;
`IO_ABORT_ADDR: begin
o_soft_reset <= i_data_in[3];
abort_sel <= i_data_in[2:0];
end
`BUS_IF_CONTROL_ADDR: begin
o_en_card_detect_n <= i_data_in[7];
bus_width <= i_data_in[1:0];
o_enable_spi_interrupt <= i_data_in[5];
end
`BUS_SUSPEND_ADDR:
o_bus_release_req_stb <= i_data_in[1];
`FUNC_SELECT_ADDR:
o_func_select <= i_data_in[3:0];
`FN0_BLOCK_SIZE_0_ADDR:
o_f0_block_size[7:0] <= i_data_in;
`FN0_BLOCK_SIZE_1_ADDR:
o_f0_block_size[15:8] <= i_data_in;
`BUS_SPD_SELECT_ADDR:
bus_speed_select <= i_data_in[3:1];
`DRIVE_STRENGTH_ADDR:
driver_type <= i_data_in[6:4];
`INTERRUPT_EXT_ADDR:
o_enable_async_interrupt <= i_data_in[1];
default: begin
end
endcase
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 3; struct tree { int l, r, minn, lazy; long long sum; } tre[MAXN << 2]; int n, m; long long a[MAXN]; void build(int i, int l, int r) { tre[i].l = l, tre[i].r = r; tre[i].lazy = 0; if (l == r) { tre[i].minn = a[l]; tre[i].sum = a[l]; return; } int mid = l + r >> 1; build(i << 1, l, mid); build(i << 1 | 1, mid + 1, r); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; } void pushdown(int i) { if (tre[i].lazy) { tre[i << 1].minn = tre[i].lazy, tre[i << 1 | 1].minn = tre[i].lazy; tre[i << 1].lazy = tre[i << 1 | 1].lazy = tre[i].lazy; tre[i << 1].sum = 1ll * (tre[i << 1].r - tre[i << 1].l + 1) * tre[i].lazy; tre[i << 1 | 1].sum = 1ll * (tre[i << 1 | 1].r - tre[i << 1 | 1].l + 1) * tre[i].lazy; tre[i].lazy = 0; } } int find_(int i, int l, int r, long long x) { if (tre[i].l >= l && tre[i].r <= r) { if (tre[i].minn > x) return 0; if (tre[i].l == tre[i].r) { if (tre[i].minn <= x) return tre[i].r; return 0; } pushdown(i); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; if (tre[i << 1].minn > x) return find_(i << 1 | 1, l, r, x); return find_(i << 1, l, r, x); } if (tre[i].l == tre[i].r) return 0; pushdown(i); int ans = 0; if (tre[i << 1].r >= l) ans = find_(i << 1, l, r, x); if (!ans && tre[i << 1 | 1].l <= r) { ans = find_(i << 1 | 1, l, r, x); } tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; return ans; } void modify(int i, int l, int r, int delta) { if (tre[i].l > r || tre[i].r < l) return; if (tre[i].l >= l && tre[i].r <= r) { tre[i].lazy = delta; tre[i].minn = delta; tre[i].sum = 1ll * (tre[i].r - tre[i].l + 1) * delta; return; } pushdown(i); modify(i << 1, l, r, delta); modify(i << 1 | 1, l, r, delta); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; } bool flag; void que(int i, long long &delta, int &tot) { if (tre[i].l == tre[i].r) { if (delta >= tre[i].sum) tot = max(tot, tre[i].r), delta -= tre[i].sum; return; } pushdown(i); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; if (tre[i << 1].sum <= delta) { tot = max(tot, tre[i << 1].r); delta -= tre[i << 1].sum; que(i << 1 | 1, delta, tot); } else { que(i << 1, delta, tot); } } void query(int i, int l, int r, long long &delta, int &tot) { if (tre[i].l > r || tre[i].r < l || flag) return; if (tre[i].l >= l && tre[i].r <= r) { if (tre[i].sum <= delta) { tot = max(tre[i].r, tot); delta -= tre[i].sum; return; } if (tre[i].l == tre[i].r) { if (tre[i].sum <= delta) { tot = max(tot, tre[i].r), delta -= tre[i].sum; } else flag = 1; return; } flag = 1; que(i, delta, tot); pushdown(i); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; return; } pushdown(i); tre[i].minn = min(tre[i << 1].minn, tre[i << 1 | 1].minn); tre[i].sum = tre[i << 1].sum + tre[i << 1 | 1].sum; query(i << 1, l, r, delta, tot); query(i << 1 | 1, l, r, delta, tot); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); build(1, 1, n); for (int i = 1; i <= m; i++) { int x, op; long long y; scanf( %d%d%lld , &op, &x, &y); if (op == 1) { int tot = find_(1, 1, x, y); if (!tot) continue; modify(1, tot, x, y); } else { int an = 0; while (x <= n) { int tot = find_(1, x, n, y); int tot1 = 0; flag = 0; query(1, tot, n, y, tot1); if (tot == 0 || tot1 == 0) break; an += tot1 - tot + 1, x = tot1 + 1; } printf( %d n , an); } } }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// UART ser/des framer for use in SPDR module. Hard coded for 115200,1,1.
//
module spdr_uart_framer
(
input clk_50,
input rst,
output reg tx_busy,
input tx_vld,
input [7:0] tx_data,
output rx_vld,
output [7:0] rx_data,
output reg rx_frame_error,
output uart_tx,
input uart_rx
);
parameter SAMPLE_CLK_DIV = 6'd62; // Value for 115200 @ 50 MHz in
//
// 50 MHz -> sample clock (7 * bit)
//
reg [5:0] sample_cnt;
reg sample_en;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b0;
end
else if (sample_cnt == SAMPLE_CLK_DIV)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b1;
end
else
begin
sample_cnt <= sample_cnt + 6'd1;
sample_en <= 1'b0;
end
//
// Rx data sample state machine
//
reg [6:0] rx_sample;
reg [2:0] rx_bitclk_cnt;
reg rx_bitclk_en;
reg [3:0] rx_bit_cnt;
reg rx_busy;
wire rx_falling_clean = (rx_sample[6:0] == 7'b1110000);
wire rx_falling_dirty = (rx_sample[6:4] == 3'b110) && (rx_sample[1:0] == 2'b00);
wire rx_falling = rx_falling_clean || rx_falling_dirty;
wire rx_high = (rx_sample[2:1] == 2'b11);
wire rx_low = (rx_sample[2:1] == 2'b00);
always @ (posedge clk_50 or posedge rst)
if (rst)
rx_sample <= 7'd0;
else if (sample_en)
rx_sample <= {rx_sample[5:0], uart_rx};
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= 1'b0;
end
else if (sample_en)
begin
if (!rx_busy)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= (rx_falling) ? 1'b1 : 1'b0;
end
else
begin
rx_busy <= (rx_bit_cnt == 4'd9) ? 1'b0 : 1'b1;
rx_bitclk_en <= (rx_bitclk_cnt == 3'd5) ? 1'b1 : 1'b0;
if (rx_bitclk_cnt == 3'd6)
begin
rx_bitclk_cnt <= 3'd0;
rx_bit_cnt <= rx_bit_cnt + 4'd1;
end
else
begin
rx_bitclk_cnt <= rx_bitclk_cnt + 3'd1;
end
end
end
//
// Rx bit capture and signalling
//
reg [8:0] rx_capture;
reg [8:0] rx_signal_errors;
reg rx_data_done;
reg rx_busy_d1;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_capture <= 9'd0;
rx_signal_errors <= 9'd0;
end
else if (sample_en && rx_bitclk_en)
begin
rx_capture <= {rx_high && !rx_low, rx_capture[8:1]};
rx_signal_errors <= {!rx_high && !rx_low, rx_signal_errors[8:1]};
end
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_data_done <= 1'b0;
rx_busy_d1 <= 1'b0;
end
else
begin
rx_data_done <= rx_busy_d1 && !rx_busy;
rx_busy_d1 <= rx_busy;
end
assign rx_vld = rx_data_done;
assign rx_data = rx_capture[7:0];
always @ (posedge clk_50)
rx_frame_error <= (rx_signal_errors != 9'd0) || !rx_capture[8];
//
// Tx state machine
//
reg [8:0] tx_shift;
reg [2:0] tx_bitclk_cnt;
reg [3:0] tx_cnt;
assign uart_tx = tx_shift[0];
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
tx_shift <= {9{1'b1}};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b0;
end
else if (!tx_busy && tx_vld)
begin
tx_shift <= {tx_data, 1'b0};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b1;
end
else if (sample_en)
begin
tx_busy <= (tx_cnt == 4'd12) ? 1'b0 : 1'b1;
if (tx_bitclk_cnt == 3'd6)
begin
tx_bitclk_cnt <= 3'd0;
tx_shift <= {1'b1, tx_shift[8:1]};
tx_cnt <= tx_cnt + 4'd1;
end
else
begin
tx_bitclk_cnt <= tx_bitclk_cnt + 3'd1;
end
end
endmodule
|
`include "defines.v"
`include "HRbridge.v"
`timescale 1ns/1ps
/*module connectRouter_nobuffer
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_l0_i,
output `control_w port_l0_o,
input `control_w FIFO_l0_i,
output `control_w FIFO_l0_o,
input bfull_l0_i,
input clk,
input rst,
output deQ_l0_o,
output enQ_l0_o,
*/
module tb(
);
reg clk, rst;
reg `control_w port_l0, port_l1, port_g0, port_g1, port_g2, port_g3;
reg `control_w FIFO_l0, FIFO_l1, FIFO_g0, FIFO_g1, FIFO_g2, FIFO_g3;
reg bfull_l0, bfull_l1, bfull_g0, bfull_g1, bfull_g2, bfull_g3;
wire `control_w port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o;
wire `control_w FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o;
wire deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3;
wire enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3;
wire accept, push;
HRbridge r(
.clk(clk),
.rst(rst),
.port_l0_i(port_l0), .port_l1_i(port_l1), .port_g0_i(port_g0), .port_g1_i(port_g1), .port_g2_i(port_g2), .port_g3_i(port_g3),
.port_l0_o(port_l0_o), .port_l1_o(port_l1_o), .port_g0_o(port_g0_o), .port_g1_o(port_g1_o), .port_g2_o(port_g2_o), .port_g3_o(port_g3_o),
.FIFO_l0_i(FIFO_l0), .FIFO_l1_i(FIFO_l1), .FIFO_g0_i(FIFO_g0), .FIFO_g1_i(FIFO_g1), .FIFO_g2_i(FIFO_g2), .FIFO_g3_i(FIFO_g3),
.FIFO_l0_o(FIFO_l0_o), .FIFO_l1_o(FIFO_l1_o), .FIFO_g0_o(FIFO_g0_o), .FIFO_g1_o(FIFO_g1_o), .FIFO_g2_o(FIFO_g2_o), .FIFO_g3_o(FIFO_g3_o),
.bfull_l0_i(bfull_l0), .bfull_l1_i(bfull_l1), .bfull_g0_i(bfull_g0), .bfull_g1_i(bfull_g1), .bfull_g2_i(bfull_g2), .bfull_g3_i(bfull_g3),
.deQ_l0_o(deQ_l0), .deQ_l1_o(deQ_l1), .deQ_g0_o(deQ_g0), .deQ_g1_o(deQ_g1), .deQ_g2_o(deQ_g2), .deQ_g3_o(deQ_g3),
.enQ_l0_o(enQ_l0), .enQ_l1_o(enQ_l1), .enQ_g0_o(enQ_g0), .enQ_g1_o(enQ_g1), .enQ_g2_o(enQ_g2), .enQ_g3_o(enQ_g3)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0; port_g2 = 144'h0; port_g3 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0; FIFO_g2 = 144'h0; FIFO_g3 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0; bfull_g2 = 0; bfull_g3 = 0;
port_l0 = 144'h0123456789abcdef0123456789abcdef1857;
port_l1 = 144'h0111111111111111111111111111111f185f;
port_g0 = 144'h0000000000000000000000000000000f1850;
port_g1 = 144'h0111111111111111101654541645488f1851;
port_g2 = 144'h0222222222222222222235364324252f1852;
port_g3 = 144'h03333333333333363623532223ffffff1853;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, port_g2 %04x\n, port_g3 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, FIFO_g2 %04x\n, FIFO_g3 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, deQ_g2 %04x\n, deQ_g3 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n, enQ_g2 %04x\n, enQ_g3 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3,
enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3);
#1;
clk = 1;
#1;
clk = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0; port_g2 = 144'h0; port_g3 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0; FIFO_g2 = 144'h0; FIFO_g3 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0; bfull_g2 = 0; bfull_g3 = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, port_g2 %04x\n, port_g3 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, FIFO_g2 %04x\n, FIFO_g3 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, deQ_g2 %04x\n, deQ_g3 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n, enQ_g2 %04x\n, enQ_g3 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o, port_g2_o, port_g3_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o, FIFO_g2_o, FIFO_g3_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1, deQ_g2, deQ_g3,
enQ_l0, enQ_l1, enQ_g0, enQ_g1, enQ_g2, enQ_g3);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vll = vector<ll>; using vii = vector<int>; using pii = pair<int, int>; template <typename T = vii> using vec = vector<T>; const ll INF = 1e18, MOD = 1e9 + 7; const int MAX = 1e6; int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; map<int, vec<pii> > d; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; d[w].emplace_back(--u, --v); } vii dp(n); for (auto [_, V] : d) { map<int, int> new_dp; for (auto [u, v] : V) { new_dp[v] = max({new_dp[v], dp[v], dp[u] + 1}); } for (auto [i, x] : new_dp) { dp[i] = x; } } cout << *max_element(dp.begin(), dp.end()) << n ; }
|
module automatic_events3();
reg [1:0] Source;
initial begin
Source[0] = 1'b0;
forever begin
#20 Source[0] = 1'b1;
#20 Source[0] = 1'b0;
end
end
initial begin
Source[1] = 1'b0;
#15;
forever begin
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b1;
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b0;
end
end
task automatic ReportPosEdge0;
begin
@(posedge Source[0]);
$display("Time %t : Source[0] rise", $time);
end
endtask
task automatic ReportNegEdge0;
begin
@(negedge Source[0]);
$display("Time %t : Source[0] fall", $time);
end
endtask
task automatic ReportAnyEdge0;
time t;
begin
@(Source[0]) t = $time;
#1 $display("Time %t : Source[0] edge", t);
end
endtask
task automatic ReportPosEdge1;
begin
@(posedge Source[1]);
$display("Time %t : Source[1] rise", $time);
end
endtask
task automatic ReportNegEdge1;
begin
@(negedge Source[1]);
$display("Time %t : Source[1] fall", $time);
end
endtask
task automatic ReportAnyEdge1;
time t;
begin
@(Source[1]) t = $time;
#1 $display("Time %t : Source[1] edge", t);
end
endtask
initial begin
#1;
fork
repeat(2) ReportPosEdge0;
repeat(2) ReportNegEdge0;
repeat(4) ReportAnyEdge0;
repeat(4) ReportPosEdge1;
repeat(4) ReportNegEdge1;
repeat(8) ReportAnyEdge1;
join
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; void search(int cur) { int tot, c[10]; int ok; if (cur == n) tot++; else for (int i = 0; i < n; i++) { ok = 1; c[cur] = i; } for (int j = 0; j < cur; j++) { if (c[cur] == c[j] || cur - c[cur] == j - c[j] || cur + c[cur] == j + c[j]) { ok = 0; break; } } if (ok) search(cur + 1); } const long long MAXN = 55; long long num[MAXN]; void xswl() { scanf( %lld%lld , &n, &k); for (long long i = 1; i <= n; ++i) { scanf( %lld , &num[i]); } num[0] = 1; sort(num + 1, num + 1 + n); long long res = 999999999999999; for (long long i = 2e5; i >= 0; --i) { long long cnt = 0; long long nowr = 0; int t = lower_bound(num + 1, num + 1 + n, i) - num; for (int j = t; j <= n; ++j) { long long now = 0; long long u = num[j]; while (u > i) { ++now; u >>= 1; } if (u == i) { ++cnt; nowr += now; } if (cnt == k) break; } if (cnt == k) { if (res > nowr) { res = nowr; } } } printf( %lld , res); } int main() { xswl(); }
|
#include <bits/stdc++.h> using namespace std; static const int INF = 0x3f3f3f3f; static const long long INFL = 0x3f3f3f3f3f3f3f3f; static const double EPS = 1e-10; static const double PI = acos(-1.0); inline int read() { int X = 0; bool flag = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) flag = 0; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { X = (X << 1) + (X << 3) + ch - 0 ; ch = getchar(); } if (flag) return X; return ~(X - 1); } inline void write(int X) { if (X < 0) { X = ~(X - 1); putchar( - ); } if (X > 9) write(X / 10); putchar(X % 10 + 0 ); } static const int MAXN = 500 + 10; vector<int> g[MAXN]; int d[1 << 19], pre[1 << 19]; int n, m, u, v; int main() { scanf( %d%d , &n, &m); while (m--) { scanf( %d%d , &u, &v); u--, v--; g[u].push_back(v); g[v].push_back(u); } memset(d, -1, sizeof(d)); d[n - 1] = 0; queue<int> Q; Q.push(n - 1); while (!Q.empty()) { int t = Q.front(); Q.pop(); bool flag = false; if (t & (1 << 18)) { flag = true; t ^= (1 << 18); } int u = t >> 9, v = t & 511; if (flag) t ^= (1 << 18); if (flag) { for (int i = 0; i < g[v].size(); i++) if (g[v][i] != u && d[(u << 9) | g[v][i]] == -1) { d[(u << 9) | g[v][i]] = d[t] + 1; pre[(u << 9) | g[v][i]] = t; Q.push((u << 9) | g[v][i]); } } else { for (int i = 0; i < g[u].size(); i++) if (d[(1 << 18) | (g[u][i] << 9) | v] == -1) { d[(1 << 18) | (g[u][i] << 9) | v] = d[t]; pre[(1 << 18) | (g[u][i] << 9) | v] = t; Q.push((1 << 18) | (g[u][i] << 9) | v); } } } int pos = (n - 1) << 9; if (d[pos] == -1) puts( -1 ); else { printf( %d n , d[pos]); vector<int> ans1, ans2; ans1.push_back(n - 1); ans2.push_back(0); while (pos != n - 1) { pos = pre[pre[pos]]; ans1.push_back(pos >> 9); ans2.push_back(pos & 511); } reverse(ans1.begin(), ans1.end()); reverse(ans2.begin(), ans2.end()); for (auto it : ans1) printf( %d , it + 1); puts( ); for (auto it : ans2) printf( %d , it + 1); puts( ); } return 0; }
|
//
// This is a file generated by ARM Cortex-M3 wizard.
// Please do not edit this file!
// Generated time: 12/25/2015 17:05:53
// Version: Primace 7.3.1
// Wizard name: ARM Cortex-M3 1.0a
//
// ============================================================
// File Name: armcm3_v1.v
// IP core : armcm3
// Device name: M7A12N5F256C7
// ============================================================
module armcm3_v1(
fp2soc_rst_n,
fp_clk_sys,
fp_clk_arm,
fp_clk_usb,
gpio_0_out_o,
gpio_0_oe_o,
gpio_0_in_i
);
input fp2soc_rst_n;
input fp_clk_sys;
input fp_clk_arm;
input fp_clk_usb;
output [31:0] gpio_0_out_o;
output [31:0] gpio_0_oe_o;
input [31:0] gpio_0_in_i;
M7S_SOC #(
.use_arm (1'b1),
.use_clk_arm (1'b1),
.use_pbus0 (1'b0),
.use_pbus1 (1'b0),
.use_on_chip_eth (1'b0),
.use_on_chip_usb (1'b1),
.use_on_chip_ddr_ctrl (1'b0),
.use_on_chip_adc (12'b000000000000),
.use_uart_io (1'b1),
.use_arm_nmi (1'b0),
.program_file ("")
)
u_soc (
.fp2soc_rst_n (1'b1),
.c2r1_dll_clk (),
.fp_clk_sys (fp_clk_sys),
.fp_clk_adc (fp_clk_adc),
.fp_clk_arm (fp_clk_arm),
.fp_lvds_sclk (),
.fp_clk_usb (fp_clk_usb),
.clk_eth_tx (),
.gpio_0_out_o (gpio_0_out_o),
.gpio_0_oe_o (gpio_0_oe_o),
.gpio_0_in_i (gpio_0_in_i),
.i2c0_scl_oe_o (),
.i2c0_sda_oe_o (),
.i2c0_scl_i (),
.i2c0_sda_i (),
.i2c1_scl_oe_o (),
.i2c1_sda_oe_o (),
.i2c1_scl_i (),
.i2c1_sda_i (),
.uart0_rts_o (),
.uart0_txd_o (),
.uart0_cts_i (),
.uart0_rxd_i (),
.uart1_rts_o (),
.uart1_txd_o (),
.uart1_cts_i (),
.uart1_rxd_i (),
.spi0_mosi (),
.spi0_sck (),
.spi0_ssn (),
.spi0_miso (),
.spi1_mosi (),
.spi1_sck (),
.spi1_ssn (),
.spi1_miso (),
.pad_can0_o_clk (),
.pad_can0_o_tx1 (),
.pad_can0_o_tx0 (),
.pad_can0_oen_tx1 (),
.pad_can0_oen_tx0 (),
.pad_can0_i_rx0 (),
.pad_can1_o_clk (),
.pad_can1_o_tx1 (),
.pad_can1_o_tx0 (),
.pad_can1_oen_tx1 (),
.pad_can1_oen_tx0 (),
.pad_can1_i_rx0 (),
.clk_ahb_fp0 (),
.rst_ahb_fp0_n (),
.fp0_m_ahb_mastlock (),
.fp0_m_ahb_prot (),
.fp0_m_ahb_size (),
.fp0_m_ahb_addr (),
.fp0_m_ahb_write (),
.fp0_m_ahb_burst (),
.fp0_m_ahb_trans (),
.fp0_m_ahb_wdata (),
.fp0_m_ahb_ready (),
.fp0_m_ahb_resp (),
.fp0_m_ahb_rdata (),
.fp0_s_ahb_mastlock (),
.fp0_s_ahb_prot (),
.fp0_s_ahb_size (),
.fp0_s_ahb_sel (),
.fp0_s_ahb_addr (),
.fp0_s_ahb_write (),
.fp0_s_ahb_burst (),
.fp0_s_ahb_trans (),
.fp0_s_ahb_wdata (),
.fp0_s_ahb_readyout (),
.fp0_s_ahb_rdata (),
.clk_ahb_fp1 (),
.rst_ahb_fp1_n (),
.fp1_m_ahb_mastlock (),
.fp1_m_ahb_prot (),
.fp1_m_ahb_size (),
.fp1_m_ahb_addr (),
.fp1_m_ahb_write (),
.fp1_m_ahb_burst (),
.fp1_m_ahb_trans (),
.fp1_m_ahb_wdata (),
.fp1_m_ahb_ready (),
.fp1_m_ahb_resp (),
.fp1_m_ahb_rdata (),
.fp1_s_ahb_mastlock (),
.fp1_s_ahb_prot (),
.fp1_s_ahb_size (),
.fp1_s_ahb_sel (),
.fp1_s_ahb_addr (),
.fp1_s_ahb_write (),
.fp1_s_ahb_burst (),
.fp1_s_ahb_trans (),
.fp1_s_ahb_wdata (),
.fp1_s_ahb_readyout (),
.fp1_s_ahb_rdata (),
.fp_INTNMI ()
);
endmodule
// ============================================================
// armcm3 Setting
//
// Warning: This part is read by Primace, please don't modify it.
// ============================================================
// Device : M7A12N5F256C7
// Module : armcm3_v1
// IP core : armcm3
// IP Version : 1
// DdrcMode : 200m
// HexFile :
// Simulation Files:
// Synthesis Files :
// UseADC0 : false
// UseADC1 : false
// UseADC10 : false
// UseADC11 : false
// UseADC2 : false
// UseADC3 : false
// UseADC4 : false
// UseADC5 : false
// UseADC6 : false
// UseADC7 : false
// UseADC8 : false
// UseADC9 : false
// UseAdcClk : true
// UseArmClk : true
// UseCAN0 : false
// UseCAN1 : false
// UseDDRC : false
// UseDdrcLocked : false
// UseEMAC : false
// UseGPIO : true
// UseI2C0 : false
// UseI2C1 : false
// UseINT : false
// UseNMIPad : false
// UsePBUS0 : false
// UsePBUS1 : false
// UseSPI0 : false
// UseSPI1 : false
// UseSocReset : false
// UseUART0 : false
// UseUART1 : false
// UseUART2 : true
// UseUSB : true
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int NCARDS = 8; const int NVALS = 5; const int NSTATE = 495; vector<vector<int> > states; map<vector<int>, int> mp; void genstates(vector<int> &v, int at, int rem) { if (at >= ((int)(v).size())) { if (rem == 0) { int id = ((int)(states).size()); states.push_back(v); mp[v] = id; } return; } for (v[at] = 0; v[at] <= rem; ++v[at]) genstates(v, at + 1, rem - v[at]); } int nxt[NSTATE][NVALS][NVALS]; vector<int> adj[NSTATE][NSTATE]; vector<int> radj[NSTATE][NSTATE]; int deg[NSTATE][NSTATE]; int dp[NSTATE][NSTATE]; int q[NSTATE * NSTATE], qhead, qtail; void precalc() { states.clear(); mp.clear(); vector<int> state(NVALS, 0); genstates(state, 0, NCARDS); for (int i = (0); i < (((int)(states).size())); ++i) for (int a = (0); a < (NVALS); ++a) for (int b = (0); b < (NVALS); ++b) { if (states[i][a] == 0) { nxt[i][a][b] = -1; continue; } vector<int> tmp = states[i]; tmp[a]--; tmp[b]++; assert(mp.count(tmp)); nxt[i][a][b] = mp[tmp]; } for (int i = (0); i < (((int)(states).size())); ++i) for (int j = (0); j < (((int)(states).size())); ++j) { for (int a = (0); a < (NVALS); ++a) for (int b = (0); b < (NVALS); ++b) if (a * b != 0 && states[i][a] != 0 && states[j][b] != 0) { int c = (a + b) % NVALS; int ni = j, nj = nxt[i][a][c]; assert(nj != -1); adj[i][j].push_back(ni * NSTATE + nj); } sort(adj[i][j].begin(), adj[i][j].end()); adj[i][j].erase(unique(adj[i][j].begin(), adj[i][j].end()), adj[i][j].end()); for (int k = (0); k < (((int)(adj[i][j]).size())); ++k) { int ii = adj[i][j][k] / NSTATE, jj = adj[i][j][k] % NSTATE; radj[ii][jj].push_back(i * NSTATE + j); } } int winid = ((int)(states).size()) - 1; for (int i = (0); i < (((int)(states).size())); ++i) for (int j = (0); j < (((int)(states).size())); ++j) dp[i][j] = 0, deg[i][j] = ((int)(adj[i][j]).size()); qhead = qtail = 0; for (int i = (0); i < (((int)(states).size())); ++i) dp[i][winid] = -1, q[qhead++] = i * NSTATE + winid; while (qtail < qhead) { int i = q[qtail] / NSTATE, j = q[qtail] % NSTATE; ++qtail; for (int k = (0); k < (((int)(radj[i][j]).size())); ++k) { int ii = radj[i][j][k] / NSTATE, jj = radj[i][j][k] % NSTATE; if (dp[ii][jj] != 0) continue; if (dp[i][j] == -1) { dp[ii][jj] = 1; q[qhead++] = ii * NSTATE + jj; continue; } if (--deg[ii][jj] == 0) { dp[ii][jj] = -1; q[qhead++] = ii * NSTATE + jj; continue; } } } } int fst; int a[NCARDS], b[NCARDS]; void run() { int nq; scanf( %d , &nq); for (int qi = (0); qi < (nq); ++qi) { scanf( %d , &fst); for (int i = (0); i < (NCARDS); ++i) scanf( %d , &a[i]); for (int i = (0); i < (NCARDS); ++i) scanf( %d , &b[i]); vector<int> acnt(NVALS, 0), bcnt(NVALS, 0); for (int i = (0); i < (NCARDS); ++i) acnt[a[i]]++, bcnt[b[i]]++; assert(mp.count(acnt) && mp.count(bcnt)); int aid = mp[acnt], bid = mp[bcnt]; int ans = fst == 0 ? dp[aid][bid] : -dp[bid][aid]; printf( %s n , ans > 0 ? Alice : ans < 0 ? Bob : Deal ); } } int main() { precalc(); run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a[5000] = {0}; cin >> n >> k; for (int i = 1; i <= k; i++) { int la = 0; cin >> la; if (la == 1) { int p, q; cin >> p >> q; a[p] = 1; a[q] = 1; } else if (la == 2) { int p; cin >> p; a[p] = 1; } } int w = 0; for (int i = 1; i < n; i++) { if (a[i] == 0) { w++; } } int max = w, min = w + 1; for (int i = 1; i <= n; i++) { if (a[i] == 0 && a[i + 1] == 0) { min--; i++; } } cout << min << << max << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Wildcard
string a [*];
int k;
string v;
a[32'd1234] = "fooed";
a[4'd3] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size(); `checkh(i, 2);
v = a[32'd1234]; `checks(v, "fooed");
v = a[4'd3]; `checks(v, "bared");
i = a.exists("baz"); `checkh(i, 0);
i = a.exists(4'd3); `checkh(i, 1);
i = a.first(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.next(k); `checkh(i, 1); `checks(k, 32'd1234);
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, 32'd1234);
i = a.prev(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.prev(k); `checkh(i, 0);
a.delete(4'd3);
i = a.size(); `checkh(i, 1);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
`include "functions.vh"
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_SYMBOL_V
`define SKY130_FD_SC_HD__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_SYMBOL_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_even_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_EVEN_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_even_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_even_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_even_parity_psl_logic.v"
`else
`endmodule // ovl_even_parity
`endif
|
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
(* NOTE: The idea with this approach is that each type uniquely determines its
ordered type, but we keep the types separate from the ordered types to make
type inference work properly... *)
Class OType (A:Type) : Type :=
{
oleq : relation A;
oPreOrder :> PreOrder oleq
}.
Instance OType_Reflexive A `{OType A} : Reflexive oleq.
Proof. typeclasses eauto. Qed.
Instance OType_Transitive A `{OType A} : Transitive oleq.
Proof. typeclasses eauto. Qed.
(* The equivalence relation for an OrderedType *)
Definition oeq {A} `{OType A} : relation A :=
fun x y => oleq x y /\ oleq y x.
Instance oeq_Equivalence A `{OType A} : Equivalence oeq.
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H0; split; assumption. }
{ destruct H0; destruct H1; split; transitivity y; assumption. }
Qed.
Notation "x <o= y" :=
(oleq x y) (no associativity, at level 70).
Notation "x =o= y" :=
(oeq x y) (no associativity, at level 70).
(* FIXME: replace "oleq" below with "<o=" notation *)
(***
*** Some General Proper Instances
***)
(** Any operations that are Proper for oleq are Proper for oeq **)
Instance Proper_oeq_oleq_op1 A B `{OType A} `{OType B} (f: A -> B) :
Proper (oleq ==> oleq) f -> Proper (oeq ==> oeq) f.
Proof.
intros prp a1 a2 Ra; destruct Ra; split; apply prp; assumption.
Qed.
Instance Proper_oeq_oleq_op2 A B C `{OType A} `{OType B} `{OType C}
(f: A -> B -> C) :
Proper (oleq ==> oleq ==> oleq) f -> Proper (oeq ==> oeq ==> oeq) f.
Proof.
intros prp a1 a2 Ra b1 b2 Rb; destruct Ra; destruct Rb.
split; apply prp; assumption.
Qed.
Instance Proper_oeq_oleq_op3 A B C D `{OType A} `{OType B} `{OType C} `{OType D}
(f: A -> B -> C -> D) :
Proper (oleq ==> oleq ==> oleq ==> oleq) f ->
Proper (oeq ==> oeq ==> oeq ==> oeq) f.
Proof.
intros prp a1 a2 Ra b1 b2 Rb c1 c2 Rc; destruct Ra; destruct Rb; destruct Rc.
split; apply prp; assumption.
Qed.
(* FIXME: figure out what versions of this we need for rewriting! *)
Instance Proper_oleq_oleq A `{OType A}
: Proper (oleq --> oleq ==> Basics.impl) (@oleq A _).
Proof.
intros a1 a2 Ra b1 b2 Rb Rab.
transitivity a1; [ assumption | ]. transitivity b1; assumption.
Qed.
Instance Subrelation_oeq_oleq A `{OType A} :
subrelation (@oeq A _) oleq.
Proof.
intros a1 a2 Ra; destruct Ra; assumption.
Qed.
Instance Proper_oeq_oleq A `{OType A} :
Proper (oeq ==> oeq ==> iff) (@oleq A _).
Proof.
intros x1 x2 Rx y1 y2 Ry; destruct Rx; destruct Ry; split; intro Rxy.
transitivity x1; [ assumption | ]; transitivity y1; assumption.
transitivity x2; [ assumption | ]; transitivity y2; assumption.
Qed.
Instance Proper_oeq A `{OType A} :
Proper (oeq ==> oeq ==> iff) (@oeq A _).
Proof.
intros x1 x2 Rx y1 y2 Ry. rewrite Rx. rewrite Ry. reflexivity.
Qed.
Instance Proper_oeq_partial A `{OType A} a :
Proper (oeq ==> Basics.flip Basics.impl) (@oeq A _ a).
Proof.
intros x1 x2 Rx. rewrite Rx. reflexivity.
Qed.
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Instance OTProp : OType Prop :=
{| oleq := Basics.impl |}.
Proof. repeat constructor; typeclasses eauto. Defined.
(* Proofs are always related (i.e., this is the proof irrelevance type) *)
Instance OTproof (P:Prop) : OType P :=
{| oleq := fun _ _ => True |}.
Proof.
repeat constructor.
Defined.
(* The discrete ordered type, where things are only related to themselves; we
make this a definition, not an instance, so that it can be instantiated for
particular types. *)
Definition OTdiscrete A : OType A := {| oleq := eq |}.
(* The only ordered type over unit is the discrete one *)
Instance OTunit : OType unit := OTdiscrete unit.
(* The ordered type that flips the ordering of an underlying OType; this becomes
a type itself in Coq *)
Inductive Flip A : Type := flip (a:A).
Arguments flip {A} a.
Definition unflip {A} (f:Flip A) : A := let (x) := f in x.
Instance OTFlip A (R:OType A) : OType (Flip A) :=
{| oleq := fun x y => unflip y <o= unflip x |}.
Proof.
repeat constructor; intro; intros.
- destruct x; compute; reflexivity.
- destruct x; destruct y; destruct z; compute; transitivity a0; assumption.
Defined.
(* The discrete relation on Booleans *)
Instance OTbool : OType bool := OTdiscrete bool.
(* The pointwise relation on pairs *)
Instance OTpair A B `(OType A) `(OType B) : OType (A*B) :=
{| oleq := fun p1 p2 => oleq (fst p1) (fst p2) /\ oleq (snd p1) (snd p2) |}.
Proof.
repeat constructor.
- destruct x. reflexivity.
- destruct x. reflexivity.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity a0; assumption.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity b0; assumption.
Defined.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:OType A) (RB:OType B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : oleq a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : oleq b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance OTsum A B (RA:OType A) (RB:OType B) : OType (A+B) :=
{| oleq := sumR RA RB |}.
Proof.
repeat constructor; intro; intros.
{ destruct x; constructor; reflexivity. }
{ destruct H; inversion H0.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Defined.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
oleq := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
oleq A x y ->
oleq B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record OFun A B {RA:OType A} {RB:OType B} :=
{
ofun_app : A -> B;
ofun_Proper : Proper (oleq ==> oleq) ofun_app
}.
(* New idea: never unfold applications of proper functions directly during
simplification, because the Proper proofs can get big from substitution;
instead, we will only use rewriting to simplify proper functions *)
Arguments ofun_app {_ _ _ _} !o _.
Arguments ofun_Proper [_ _ _ _] _ _ _ _.
Notation "A '-o>' B" :=
(OFun A B) (right associativity, at level 99).
Notation "x @@ y" :=
(ofun_app x y) (left associativity, at level 20).
(* The non-dependent function ordered type *)
Instance OTarrow A B `{OType A} `{OType B} : OType (A -o> B) :=
{| oleq :=
fun f g =>
forall a1 a2, oleq a1 a2 -> oleq (ofun_app f a1) (ofun_app g a2) |}.
Proof.
repeat constructor; intro; intros.
{ apply ofun_Proper; assumption. }
{ transitivity (ofun_app y a1).
- apply H1; reflexivity.
- apply H2; assumption. }
Defined.
(***
*** Proper Instances for Simple Ordered Types
***)
Instance Proper_pair A B `{OType A} `{OType B} :
Proper (oleq ==> oleq ==> oleq) (pair : A -> B -> A*B).
Proof.
repeat intro; split; assumption.
Qed.
Instance Proper_fst A B `{OType A} `{OType B} :
Proper (oleq ==> oleq) (fst : A*B -> A).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_snd A B `{OType A} `{OType B} :
Proper (oleq ==> oleq) (snd : A*B -> B).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
(* ofun_app is always Proper *)
Instance Proper_ofun_app A B `{OType A} `{OType B} :
Proper (oleq ==> oleq ==> oleq) (@ofun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(*
Instance Proper_ofun_app_partial A B `{OType A} `{OType B} f :
Proper (oleq ==> oleq) (ofun_app (A:=A) (B:=B) f).
Proof.
apply ofun_Proper.
Qed.
*)
(***
*** Building Proper Functions
***)
Class ProperPair A `{OType A} (x y:A) : Prop :=
proper_pair_pf : oleq x y.
Class OFunProper {A B} `{OType A} `{OType B} (f: A -> B) : Prop :=
ofun_proper : forall x y, ProperPair A x y -> ProperPair B (f x) (f y).
Hint Extern 1 (OFunProper _) => intro; intro; intro : typeclass_instances.
Definition mk_ofun {A B} `{OType A} `{OType B} (f: A -> B) {prp:OFunProper f}
: A -o> B :=
{| ofun_app := f; ofun_Proper := prp |}.
(*
Notation "'ofun' x => e" := (mk_ofun (fun x => e))
(right associativity, at level 99).
Notation "'ofun' ( x : A ) => e" :=
(mk_ofun (fun x:A => e))
(right associativity, at level 99, x at level 0).
*)
Instance ProperPair_refl A `{OType A} (x:A) : ProperPair A x x.
Proof.
unfold ProperPair. reflexivity.
Qed.
Lemma ProperPair_ofun_app A B `{OType A} `{OType B}
(fl fr:A -o> B) argl argr
(prpf:ProperPair (A -o> B) fl fr)
(prpa:ProperPair A argl argr)
: ProperPair B (ofun_app fl argl) (ofun_app fr argr).
Proof.
apply prpf; assumption.
Qed.
Lemma ProperPair_ofun A B `{OType A} `{OType B} (f g:A -> B) prpl prpr
(pf: forall x y, ProperPair A x y -> ProperPair B (f x) (g y)) :
ProperPair (A -o> B) (@mk_ofun A B _ _ f prpl) (@mk_ofun A B _ _ g prpr).
Proof.
intros xl xr Rx; apply pf; assumption.
Qed.
Hint Extern 2 (ProperPair _ _ _) =>
first [ apply ProperPair_ofun_app
| apply ProperPair_ofun; do 3 intro ] : typeclass_instances.
(***
*** Unary Ordered Type Functors
***)
(* Typeclass version of OTypeF1Fun *)
Class OTypeF (F:forall A {RA:OType A}, Type) : Type :=
otypeF : forall A {RA:OType A}, OType (F A).
(* Get out the OType from applying a unary functor *)
Instance OType_OTypeF F (RF:OTypeF F) A (RA:OType A) :
OType (F A _) | 5 := RF A _.
Typeclasses Transparent OType_OTypeF.
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; char s[21][100100]; int n, m, ans = 1e9, all, inv, a[100100], bit[1100000], w[1100000], f[1100000]; int power(int a, int k) { int ret = 1; while (k) { if (k & 1) ret = 1ll * ret * a % mod; a = 1ll * a * a % mod; k >>= 1; } return ret; } void FWT(int *a, int t) { int pre, cur = 0; static int f[2][1100000]; for (int i = 0; i <= all; i++) f[0][i] = a[i]; for (int i = 0; i <= n - 1; i++) { pre = cur, cur ^= 1; for (int s = 0; s <= all; s++) if (!(s >> i & 1)) { int l = f[pre][s], r = f[pre][s | (1 << i)]; f[cur][s] = (l + r) % mod; f[cur][s | (1 << i)] = (l + mod - r) % mod; } } if (t) for (int i = 0; i <= all; i++) f[cur][i] = 1ll * f[cur][i] * inv % mod; for (int i = 0; i <= all; i++) a[i] = f[cur][i]; } int main() { scanf( %d%d , &n, &m); all = (1 << n) - 1; inv = power(power(2, mod - 2), n); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) a[i] = (a[i] << 1) + s[j][i] - 0 ; for (int i = 1; i <= all; i++) bit[i] = bit[i >> 1] + (i & 1); for (int i = 1; i <= m; i++) f[a[i]]++; for (int i = 0; i <= all; i++) w[i] = min(bit[i], n - bit[i]); FWT(f, 0); FWT(w, 0); for (int i = 0; i <= all; i++) f[i] = 1ll * f[i] * w[i] % mod; FWT(f, 1); for (int i = 0; i <= all; i++) ans = min(ans, f[i]); printf( %d n , ans); }
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_8_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_8_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_8_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; template <class T> void chmin(T &t, const T &f) { if (t > f) t = f; } template <class T> void chmax(T &t, const T &f) { if (t < f) t = f; } int main() { long long int n, a, c1, c2, m, len = 0, prev = 0, ans = 0, rlow, rlen, rind, ret[100005]; vector<pair<long long int, long long int> > v; vector<long long int> sum; scanf( %I64d %I64d %I64d %I64d %I64d , &n, &a, &c1, &c2, &m); for (long long int i = 0; i < n; ++i) { long long int x; scanf( %I64d , &x); v.push_back(make_pair(x, i)); } if (n == 1) { long long int maxi = min(a, v[0].first + m); printf( %I64d n , c1 * (maxi == a ? 1 : 0) + maxi * c2); printf( %I64d , maxi); return 0; } sort(v.begin(), v.end()); sum.push_back(0); for (int i = 1; i < n; ++i) sum.push_back((v[i].first - v[i - 1].first) * i + sum[i - 1]); while (len <= n) { if (len - 1 >= 0) prev += a - v[n - len].first; if (prev > m) break; long long int newm = m - prev; long long int ind = upper_bound(sum.begin(), sum.end(), newm) - sum.begin(); ind = max(0ll, min((long long int)ind - 1, (long long int)n - len - 1)); newm -= sum[ind]; long long int low = min(v[ind].first + (newm / (ind + 1)), a); if (ans < len * c1 + low * c2) { ans = len * c1 + low * c2; rlow = low; rind = ind; rlen = len; } len++; } for (int i = 0; i < n; ++i) ret[v[i].second] = v[i].first; for (int i = 0; i <= rind; ++i) ret[v[i].second] = max(v[i].first, rlow); for (int i = n - 1; i >= n - rlen; --i) ret[v[i].second] = a; printf( %I64d n , ans); for (int i = 0; i < n; ++i) printf( %I64d , ret[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; bool a[maxn]; int main() { int n, k; while (~scanf( %d%d , &n, &k)) { int p = (n - k) / 2 + 1; int t = n / p; while (t--) { for (int i = 0; i < p; i++) { if (i == p - 1) printf( 0 ); else printf( 1 ); } } for (int i = 0; i < n % p; i++) printf( 1 ); printf( n ); } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 1,
NUM_STAGE = 14,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_12_no_dsp_32 convolve_kernel_ap_fadd_12_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); return x * f; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); putchar( n ); } inline void wri(long long x) { write(x); putchar( ); } const int maxn = 1e5 + 233; const int mod = 1e9 + 7; int f[maxn]; int main() { int n = read(), m = read(); f[0] = 1; f[1] = 1; for (register int i = (2); i <= int(maxn - 1); ++i) f[i] = (f[i - 1] + f[i - 2]) % mod; writeln(2ll * (f[n] + f[m] - 1) % mod); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_LP_V
`define SKY130_FD_SC_LP__OR3B_LP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_LP_V
|
#include <bits/stdc++.h> using namespace std; class ST { long long int tree[10000000]; long long int lazy[10000000]; public: void build(int a, int b, int node) { tree[node] = 0; lazy[node] = 0; if (a == b) return; int mid = (a + b + 4000000) / 2 - 2000000; build(a, mid, 2 * node); build(mid + 1, b, 2 * node + 1); } void propagate(int a, int b, int node) { tree[node] += lazy[node]; if (a != b) { lazy[2 * node] += lazy[node]; lazy[2 * node + 1] += lazy[node]; } lazy[node] = 0; } void update(int a, int b, int node, int x, int y, long long int val) { propagate(a, b, node); if (b < x || y < a) return; if (x <= a && b <= y) { lazy[node] += val; propagate(a, b, node); return; } int mid = (a + b + 4000000) / 2 - 2000000; update(a, mid, 2 * node, x, y, val); update(mid + 1, b, 2 * node + 1, x, y, val); tree[node] = max(tree[2 * node], tree[2 * node + 1]); } long long int query() { return tree[1]; } }; int main() { int n; long long int r; scanf( %d %lld , &n, &r); vector<pair<long long int, long long int> > V; for (int i = 0; i < n; i++) { long long int a, b; scanf( %lld %lld , &a, &b); V.push_back(pair<long long int, long long int>(a + b, a - b)); } ST *S = new ST(); S->build(-2000000, 2000000, 1); sort(V.begin(), V.end()); int ptr = 0; long long int ans = 0; for (int i = 0; i < n; i++) { while (V[ptr].first < V[i].first - 2 * r) { S->update(-2000000, 2000000, 1, V[ptr].second - 2 * r, V[ptr].second, -1); ptr++; } S->update(-2000000, 2000000, 1, V[i].second - 2 * r, V[i].second, 1); ans = max(ans, S->query()); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace whatever { int readu() { char ch = getchar(); while (!isdigit(ch)) ch = getchar(); int value = ch - 0 ; ch = getchar(); while (isdigit(ch)) { value = value * 10 + ch - 0 ; ch = getchar(); } return value; } void writeu(int n) { if (n < 10) putchar(n + 0 ); else { writeu(n / 10); putchar(n % 10 + 0 ); } } namespace tree { vector<int> tree_adj[100001 + 100000]; int size[100001 + 100000]; int heavy[100001 + 100000]; int depth[100001 + 100000]; int father[100001 + 100000]; void dfs1(int cur) { size[cur] = 1; for (auto to : tree_adj[cur]) if (to != father[cur]) { depth[to] = depth[cur] + 1; father[to] = cur; dfs1(to); size[cur] += size[to]; if (size[heavy[cur]] < size[to]) heavy[cur] = to; } } int top[100001 + 100000]; void dfs2(int cur) { for (auto to : tree_adj[cur]) if (to != father[cur]) { top[to] = (to == heavy[cur] ? top[cur] : to); dfs2(to); } } int lca(int a, int b) { while (top[a] != top[b]) { if (depth[top[a]] > depth[top[b]]) a = father[top[a]]; else b = father[top[b]]; } return (depth[a] < depth[b] ? a : b); } } // namespace tree namespace graph { vector<int> adj[100001]; int dfn[100001]; int low[100001]; int dfs_time; int stack[100001]; int top; int bcc_cnt; void dfs(int cur) { dfn[cur] = low[cur] = ++dfs_time; stack[top++] = cur; for (auto to : adj[cur]) { if (!dfn[to]) { dfs(to); low[cur] = min(low[cur], low[to]); if (low[to] == dfn[cur]) { ++bcc_cnt; do { --top; tree::tree_adj[stack[top]].push_back(100000 + bcc_cnt); tree::tree_adj[100000 + bcc_cnt].push_back(stack[top]); } while (stack[top] != to); tree::tree_adj[cur].push_back(100000 + bcc_cnt); tree::tree_adj[100000 + bcc_cnt].push_back(cur); } } else low[cur] = min(low[cur], dfn[to]); } } } // namespace graph void run() { int n = readu(); int m = readu(); int q = readu(); while (--m != -1) { int u = readu(); int v = readu(); graph::adj[u].push_back(v); graph::adj[v].push_back(u); } graph::dfs(1); assert(graph::top == 1); assert(graph::stack[0] == 1); tree::dfs1(1); assert(tree::size[1] == graph::bcc_cnt + n); tree::dfs2(1); while (--q != -1) { int a = readu(); int b = readu(); int l = tree::lca(a, b); int dis = tree::depth[a] - tree::depth[l] + tree::depth[b] - tree::depth[l]; assert(dis % 2 == 0); writeu(dis / 2); putchar( n ); } } } // namespace whatever int main() { whatever::run(); }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1 << 28; const long long LINF = 1ll << 61; inline long long getnum() { register long long r = 0; register bool ng = 0; register char c; c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); if (c == - ) ng = 1, c = getchar(); while (c >= 0 && c <= 9 ) r = r * 10 + c - 0 , c = getchar(); if (ng) r = -r; return r; } template <class T> inline void putnum(T x) { if (x < 0) putchar( - ), x = -x; register short a[20] = {}, sz = 0; while (x > 0) a[sz++] = x % 10, x /= 10; if (sz == 0) putchar( 0 ); for (int i = sz - 1; i >= 0; i--) putchar( 0 + a[i]); } inline void putsp() { putchar( ); } inline void putendl() { putchar( n ); } inline char mygetchar() { register char c = getchar(); while (c == || c == n ) c = getchar(); return c; } int n, c; int a[200111]; set<pair<int, int> > s; vector<pair<int, int> > tmps; bool used[200111]; int cnt[200111]; int main() { c = getnum(), n = getnum(); s.insert(make_pair(-c, 0)); for (int i = 1; i <= n; i++) { a[i] = getnum(); } sort(a + 1, a + n + 1); for (int i = n; i >= 1; i--) { tmps.clear(); while (s.size() > 0 && -s.begin()->first > a[i]) { int x = s.begin()->second, y = -s.begin()->first + x; s.erase(s.begin()); tmps.push_back(make_pair(-a[i], x)); tmps.push_back(make_pair(-(y - (x + a[i])), x + a[i])); } for (int j = 0; j < tmps.size(); j++) { s.insert(tmps[j]); } } for (auto x : s) { used[x.second] = 1; } int tmp = c; for (int i = n; i >= 1; i--) { if (tmp >= a[i]) { cnt[a[i]]++; cnt[tmp + 1]--; tmp -= a[i]; } } int sum = 0; for (int i = 1; i <= c; i++) { sum += cnt[i]; if (sum > 0 && !used[c - i]) { cout << i << endl; return 0; } } puts( Greed is good ); return 0; }
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#include <bits/stdc++.h> using namespace std; const double pi = 3.141592653589793238463; int a[100009], p[200009]; int main() { cin.tie(0); cin.sync_with_stdio(0); int h; cin >> h; for (int i = (0); i <= (h); i++) cin >> a[i]; bool perfect = true; for (int i = 0; i < (h); i++) if (a[i] > 1 && a[i + 1] > 1) perfect = false; if (perfect) { cout << perfect << n ; return 0; } cout << ambiguous << n ; int idx = 1; p[0] = 0; for (int i = (0); i <= (h); i++) { p[i + 1] = idx; for (int j = (0); j < (a[i]); j++) cout << p[i] << ; idx += a[i]; } cout << n ; idx = 1; p[0] = 0; for (int i = (0); i <= (h); i++) { p[i + 1] = idx; if (i > 0 && a[i] > 1 && a[i - 1] > 1) { cout << p[i] << ; for (int j = (0); j < (a[i] - 1); j++) cout << p[i] + 1 << ; } else for (int j = (0); j < (a[i]); j++) cout << p[i] << ; idx += a[i]; } cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long int x2, y2, x3, y3; bool check(long long int x, long long int y) { long long int xx = x3 * x3 + y3 * y3, tx = x2 + x, ty = y2 + y; if (xx == 0) return x == x2 && y == y2; long long int ret1 = tx * x3 + ty * y3, ret2 = tx * y3 - ty * x3; if (ret1 % xx != 0 || ret2 % xx != 0) return false; return true; } int main() { long long int x1, y1; cin >> x1 >> y1 >> x2 >> y2 >> x3 >> y3; if (check(x1, y1) || check(-x1, -y1) || check(-y1, x1) || check(y1, -x1)) cout << YES n ; else cout << NO n ; }
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#include <bits/stdc++.h> const int N = 60; int G[N][N], n, m, top; std::vector<int> v[500000]; inline void out() { puts( ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { printf( %d , G[i][j]); } puts( ); } puts( ); return; } inline int id(int x, int y) { return (x - 1) * m + y; } inline bool check() { return G[n - 1][m - 1] == id(n - 1, m - 1) && G[n - 1][m] == id(n - 1, m) && G[n][m - 1] == id(n, m - 1) && G[n][m] == id(n, m); } inline void Cir(int x, int y, int f) { if (f == 0) { ++top; v[top].push_back(G[x][y]); v[top].push_back(G[x][y + 1]); v[top].push_back(G[x + 1][y + 1]); v[top].push_back(G[x + 1][y]); int t = G[x][y]; G[x][y] = G[x + 1][y]; G[x + 1][y] = G[x + 1][y + 1]; G[x + 1][y + 1] = G[x][y + 1]; G[x][y + 1] = t; } else { ++top; v[top].push_back(G[x][y]); v[top].push_back(G[x + 1][y]); v[top].push_back(G[x + 1][y + 1]); v[top].push_back(G[x][y + 1]); int t = G[x][y]; G[x][y] = G[x][y + 1]; G[x][y + 1] = G[x + 1][y + 1]; G[x + 1][y + 1] = G[x + 1][y]; G[x + 1][y] = t; } return; } inline void Move(int x, int y, int tx, int ty) { if (tx == n) { while (x != tx) { if (y == m) { Cir(x, y - 1, 0); x++; } else { Cir(x, y, 1); x++; } } while (y != ty) { Cir(x - 1, y - 1, 0); y--; } } else { if (x == n) { if (y == m) { Cir(x - 1, y - 1, 1); x--; } else { Cir(x - 1, y, 0); x--; } } while (y != ty) { if (y < ty) { Cir(x, y, 0); y++; } else { Cir(x, y - 1, 1); y--; } } while (x != tx) { Cir(x - 1, y, 0); x--; } } return; } inline void getPos(int &i, int &j, int t) { for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (G[i][j] == t) { return; } } } return; } inline void SwapDown() { Cir(n - 1, m - 1, 0); Cir(n - 1, m - 2, 0); ++top; v[top].push_back(G[n - 1][m - 2]); v[top].push_back(G[n][m - 2]); v[top].push_back(G[n][m - 1]); v[top].push_back(G[n][m]); v[top].push_back(G[n - 1][m]); v[top].push_back(G[n - 1][m - 1]); int t = G[n - 1][m - 2]; G[n - 1][m - 2] = G[n - 1][m - 1]; G[n - 1][m - 1] = G[n - 1][m]; G[n - 1][m] = G[n][m]; G[n][m] = G[n][m - 1]; G[n][m - 1] = G[n][m - 2]; G[n][m - 2] = t; return; } inline void SwapUp() { Cir(n - 1, m - 1, 1); Cir(n - 1, m - 2, 1); ++top; v[top].push_back(G[n - 1][m - 2]); v[top].push_back(G[n - 1][m - 1]); v[top].push_back(G[n - 1][m]); v[top].push_back(G[n][m]); v[top].push_back(G[n][m - 1]); v[top].push_back(G[n][m - 2]); int t = G[n - 1][m - 2]; G[n - 1][m - 2] = G[n][m - 2]; G[n][m - 2] = G[n][m - 1]; G[n][m - 1] = G[n][m]; G[n][m] = G[n - 1][m]; G[n - 1][m] = G[n - 1][m - 1]; G[n - 1][m - 1] = t; return; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &G[i][j]); } } int x, y; for (int i = 1; i <= n - 2; i++) { for (int j = 1; j <= m - 2; j++) { getPos(x, y, id(i, j)); Move(x, y, i, j); } getPos(x, y, i * m); Move(x, y, i, m - 1); getPos(x, y, i * m - 1); if (x == i && y == m) { Cir(x, y - 1, 0); Cir(x + 1, y - 1, 0); Cir(x, y - 1, 1); getPos(x, y, i * m - 1); } Move(x, y, i + 1, m - 1); Cir(i, m - 1, 0); } for (int i = 1; i <= m - 2; i++) { getPos(x, y, id(n - 1, i)); Move(x, y, n, i); getPos(x, y, id(n, i)); if (x == n - 1 && y == i) { Cir(x, y, 0); Cir(x, y + 1, 0); Cir(x, y, 1); } getPos(x, y, id(n, i)); Move(x, y, n, i + 1); Cir(n - 1, i, 0); } int xx, yy; getPos(x, y, id(n - 1, m - 1)); getPos(xx, yy, id(n - 1, m)); if (abs(x - xx) + abs(y - yy) != 1) { SwapDown(); } if (x == n && xx == n) { Cir(n - 1, m - 1, 0); Cir(n - 1, m - 1, 0); } getPos(x, y, id(n - 1, m - 1)); getPos(xx, yy, id(n - 1, m)); if (x != xx) { Cir(n - 1, m - 1, y == m); } if (G[n][m - 1] > G[n][m]) { SwapDown(); } if (G[n - 1][m - 1] > G[n - 1][m]) { SwapUp(); } printf( %d n , top); for (int i = 1; i <= top; i++) { int len = v[i].size(); printf( %d , len); for (int j = 0; j < len; j++) { printf( %d , v[i][j]); } puts( ); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_2_V
`define SKY130_FD_SC_HD__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_2_V
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#include <bits/stdc++.h> using namespace std; long long int N = 100000, M = 100000; long long int MOD = 1000000007; void solve() { long long int n; cin >> n; long long int a[n + 1], b[n + 1]; for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < n; i++) { b[i] = a[i] - i; if (b[i] < 0) b[i] = 0; else if (b[i] % n == 0) b[i] = b[i] / n; else b[i] = (b[i] / n) + 1; } for (long long int i = 0; i < n; i++) b[i] = i + (n * b[i]); long long int min1 = b[0]; long long int ans = 0; for (long long int i = 0; i < n; i++) { if (min1 > b[i]) { min1 = b[i]; ans = i; } } cout << ans + 1; } int main() { long long int t = 1; while (t--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; const int INF = numeric_limits<int>::max(); const long long LLINF = numeric_limits<long long>::max(); const unsigned long long ULLINF = numeric_limits<unsigned long long>::max(); const double PI = acos(-1.0); vector<int> ans; void solve(int n, int p, int maxN) { if (!p) return; int mx = n - (p - 1); int cur = min(maxN, mx); ans.push_back(cur); solve(n - cur, p - 1, maxN); } vector<char> type; int main() { ios_base::sync_with_stdio(0); cin.tie(0); char c; type.push_back(1); int p = 1, m = 0; cin >> c; while (c != = ) { if (c == + ) { p++; type.push_back( + ); } else if (c == - ) { type.push_back( - ); m++; } cin >> c; } int n; cin >> n; if (!p) { cout << Impossible ; return 0; } if (!m) { if (p > n) { cout << Impossible ; return 0; } cout << Possible n ; solve(n, p, n); cout << ans.back() << ; ans.pop_back(); while (ans.size()) { cout << + << ans.back() << ; ans.pop_back(); } cout << = << n; return 0; } vector<int> positive, negative; bool found = 0; for (int pos = n; pos <= n * p; pos++) { int neg = pos - n; if (neg / m > 0 && n * m >= neg) { if (p > pos) continue; solve(pos, p, n); positive = ans; solve(neg, m, n); negative = ans; found = 1; break; } } if (!found) { cout << Impossible ; return 0; } cout << Possible n ; cout << positive.back() << ; positive.pop_back(); for (int i = 1; i < type.size(); i++) { if (type[i] == + ) { cout << + << positive.back() << ; positive.pop_back(); } else { cout << - << negative.back() << ; negative.pop_back(); } } cout << = << n; return 0; }
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