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`default_nettype none
module simple_ddr3(
input wire clk, // clk491520
input wire rst,
input wire [27:0] addr_i,
input wire [31:0] data_i,
input wire we_i,
input wire pop_i,
output wire [31:0] data_o,
output wire ack_o,
output wire busy_o,
// MIG interface
output wire mig_cmd_clk,
output wire mig_cmd_en,
output wire [2:0] mig_cmd_instr,
output wire [5:0] mig_cmd_bl,
output wire [29:0] mig_cmd_byte_addr,
input wire mig_cmd_empty,
input wire mig_cmd_full,
output wire mig_wr_clk,
output wire mig_wr_en,
output wire [3:0] mig_wr_mask,
output wire [31:0] mig_wr_data,
input wire mig_wr_full,
input wire mig_wr_empty,
input wire [6:0] mig_wr_count,
input wire mig_wr_underrun,
input wire mig_wr_error,
output wire mig_rd_clk,
output wire mig_rd_en,
input wire [31:0] mig_rd_data,
input wire mig_rd_full,
input wire mig_rd_empty,
input wire [6:0] mig_rd_count,
input wire mig_rd_overflow,
input wire mig_rd_error);
reg [27:0] addr_ff;
reg [31:0] wdata_ff;
reg [31:0] rdata_ff;
reg ack_ff;
reg [5:0] state_ff;
localparam ST_INIT = 1;
localparam ST_FILL_WRBUF = 2;
localparam ST_EMIT_WR_CMD = 3;
localparam ST_EMIT_RD_CMD = 4;
localparam ST_WAIT_RD_DATA = 5;
always @(posedge clk) begin
if (rst) begin
addr_ff <= 28'b0;
wdata_ff <= 32'b0;
rdata_ff <= 32'b0;
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end else begin
case (state_ff)
ST_INIT: begin
addr_ff <= addr_i;
wdata_ff <= data_i;
ack_ff <= 1'b0;
if (we_i) begin
state_ff <= ST_FILL_WRBUF;
end else if (pop_i) begin
state_ff <= ST_EMIT_RD_CMD;
end else begin
state_ff <= ST_INIT;
end
end
ST_FILL_WRBUF: begin
state_ff <= ST_EMIT_WR_CMD;
ack_ff <= 1'b0;
end
ST_EMIT_WR_CMD: begin
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end
ST_EMIT_RD_CMD: begin
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end
ST_WAIT_RD_DATA: begin
if (mig_rd_count == 6'h00) begin // FIXME: mig_rd_empty?
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end else begin
rdata_ff <= mig_rd_data;
state_ff <= ST_INIT;
ack_ff <= 1'b1;
end
end
endcase
end
end
assign mig_cmd_clk = clk;
assign mig_cmd_en = (state_ff == ST_EMIT_RD_CMD || state_ff == ST_EMIT_WR_CMD) ? 1'b1 : 1'b0;
assign mig_cmd_instr = (state_ff == ST_EMIT_RD_CMD) ? 3'b001 : 3'b010;
assign mig_cmd_bl = 6'b0;
assign mig_cmd_byte_addr[29:0] = {addr_ff, 2'b00};
// FIXME: wait until mig_cmd_empty or !mig_cmd_full?
assign mig_wr_clk = clk;
assign mig_wr_en = (state_ff == ST_FILL_WRBUF) ? 1'b1 : 1'b0;
assign mig_wr_mask = 4'b0000;
assign mig_wr_data = wdata_ff;
// mig_wr_full, mig_wr_empty, mig_wr_count, mig_wr_underrun, mig_wr_error
assign mig_rd_clk = clk;
assign mig_rd_en = (state_ff == ST_WAIT_RD_DATA) ? 1'b1 : 1'b0;
// mig_rd_full, mig_rd_empty, mig_rd_overflow, mig_rd_error
assign data_o = rdata_ff;
assign ack_o = ack_ff;
assign busy_o = (state_ff != ST_INIT) ? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; assert(1 <= n && n <= (int)(2e5)); string sex; cin >> sex; assert(sex.size() == n); for (int i = 0; i < n; ++i) { assert(sex[i] == B || sex[i] == G ); } vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; assert(1 <= a[i] && a[i] <= (int)(1e7)); } vector<int> pre(n), nxt(n); priority_queue<pair<int, pair<int, int> >, vector<pair<int, pair<int, int> > >, greater<pair<int, pair<int, int> > > > pq; for (int i = 0; i < n; ++i) { pre[i] = i - 1; nxt[i] = i + 1; if (i > 0 && sex[i - 1] != sex[i]) { pq.push(make_pair(abs(a[i - 1] - a[i]), make_pair(i - 1, i))); } } vector<bool> mark(n, true); vector<pair<int, int> > result; while (!pq.empty()) { int i = pq.top().second.first; int j = pq.top().second.second; pq.pop(); if (mark[i] && mark[j]) { mark[i] = false; mark[j] = false; result.push_back(make_pair(i, j)); i = pre[i]; j = nxt[j]; if (i != -1) { nxt[i] = j; } if (j != n) { pre[j] = i; } if (i != -1 && j != n && sex[i] != sex[j] && mark[i] && mark[j]) { pq.push(make_pair(abs(a[i] - a[j]), make_pair(i, j))); } } } cout << result.size() << endl; for (int i = 0; i < result.size(); ++i) { cout << result[i].first + 1 << << result[i].second + 1 << endl; } return 0; }
|
// This pass performs an optimisation that decomposes wide arithmetic
// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH
// macro) connected to a single lookahead-carry-unit $lcu cell,
// which is typically mapped to dedicated (and fast) FPGA
// carry-chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _80_lcu_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
generate
if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2)
wire _TECHMAP_FAIL_ = 1;
else if (_TECHMAP_CELLTYPE_ == "$lt") begin
// Transform $lt into $gt by swapping A and B
$gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else if (_TECHMAP_CELLTYPE_ == "$le") begin
// Transform $le into $ge by swapping A and B
$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else begin
// Perform sign extension on A and B
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
(* force_downto *)
wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
(* force_downto *)
wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
// For $ge operation, start with the assumption that A and B are
// equal (propagating this equality if A and B turn out to be so)
if (_TECHMAP_CELLTYPE_ == "$ge")
localparam CI = 1'b1;
else
localparam CI = 1'b0;
$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
end
endgenerate
endmodule
module $__CMP2LCU (A, B, P, G, Y);
parameter AB_WIDTH = 0;
parameter AB_SIGNED = 0;
parameter LCU_WIDTH = 1;
parameter BUDGET = 0;
parameter CI = 0;
(* force_downto *)
input [AB_WIDTH-1:0] A; // A from original $gt/$ge
(* force_downto *)
input [AB_WIDTH-1:0] B; // B from original $gt/$ge
(* force_downto *)
input [LCU_WIDTH-1:0] P; // P of $lcu
(* force_downto *)
input [LCU_WIDTH-1:0] G; // G of $lcu
output Y;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
generate
if (AB_WIDTH == 0) begin
(* force_downto *)
wire [LCU_WIDTH-1:0] CO;
$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
assign Y = CO[LCU_WIDTH-1];
end
else begin
if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
localparam COST = 0;
else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0])
localparam COST = 1;
else
localparam COST = 2;
if (BUDGET < COST)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));
else begin
wire PP, GG;
// Bit-wise equality (xnor) of A and B
assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];
if (AB_SIGNED)
assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];
else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant
assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];
else
// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
// from MSB down, deferring to less significant bits if the
// MSBs are equal
assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
if (LCU_WIDTH == 1) begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
wire P_ = P[0] & PP;
// Generate if any comparisons call for it
wire G_ = G[0] | GG;
end
else begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
(* force_downto *)
wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
// Generate if any comparisons call for it
(* force_downto *)
wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
if (AB_WIDTH == 1)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
else
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
end
end
endgenerate
endmodule
|
module ourspi (
OPB_Clk,
rst,
opb_abus,
opb_be,
opb_dbus,
opb_rnw,
opb_select,
opb_seqaddr,
sl_dbus,
sl_errack,
sl_retry,
sl_toutsup,
sl_xferack,
radio1_sclk,
radio1_dout,
radio1_cs,
radio2_sclk,
radio2_dout,
radio2_cs,
radio3_sclk,
radio3_dout,
radio3_cs,
radio4_sclk,
radio4_dout,
radio4_cs,
dac1_sclk,
dac1_dout,
dac1_cs,
dac2_sclk,
dac2_dout,
dac2_cs,
dac3_sclk,
dac3_dout,
dac3_cs,
dac4_sclk,
dac4_dout,
dac4_cs
);
parameter C_BASEADDR = 32'h8000_0000, C_HIGHADDR = 32'h8000_00ff;
input OPB_Clk;
input rst;
input [31:0] opb_abus;
input [3:0] opb_be;
input [31:0] opb_dbus;
input opb_rnw;
input opb_select;
input opb_seqaddr;
output [31:0] sl_dbus;
output sl_errack;
output sl_retry;
output sl_toutsup;
output sl_xferack;
output radio1_sclk;
output radio1_dout;
output radio1_cs;
output radio2_sclk;
output radio2_dout;
output radio2_cs;
output radio3_sclk;
output radio3_dout;
output radio3_cs;
output radio4_sclk;
output radio4_dout;
output radio4_cs;
output dac1_sclk;
output dac1_dout;
output dac1_cs;
output dac2_sclk;
output dac2_dout;
output dac2_cs;
output dac3_sclk;
output dac3_dout;
output dac3_cs;
output dac4_sclk;
output dac4_dout;
output dac4_cs;
wire [4:0] spi_wb_adr_i;
wire [31:0] spi_wb_dat_i;
wire [31:0] spi_wb_dat_o;
wire [3:0] spi_wb_sel_i;
wire spi_wb_we_i;
wire spi_wb_stb_i;
wire spi_wb_cyc_i;
wire spi_wb_ack_o;
wire spi_wb_err_o;
wire spi_wb_int_o;
wire [7:0] spi_cs;
wire spi_sclk;
wire spi_dout;
assign radio1_sclk = spi_sclk;
assign radio2_sclk = spi_sclk;
assign radio3_sclk = spi_sclk;
assign radio4_sclk = spi_sclk;
assign dac1_sclk = spi_sclk;
assign dac2_sclk = spi_sclk;
assign dac3_sclk = spi_sclk;
assign dac4_sclk = spi_sclk;
assign radio1_dout = spi_dout;
assign radio2_dout = spi_dout;
assign radio3_dout = spi_dout;
assign radio4_dout = spi_dout;
assign dac1_dout = spi_dout;
assign dac2_dout = spi_dout;
assign dac3_dout = spi_dout;
assign dac4_dout = spi_dout;
assign radio1_cs = spi_cs[0];
assign radio2_cs = spi_cs[1];
assign radio3_cs = spi_cs[2];
assign radio4_cs = spi_cs[3];
assign dac1_cs = spi_cs[4];
assign dac2_cs = spi_cs[5];
assign dac3_cs = spi_cs[6];
assign dac4_cs = spi_cs[7];
spi_top wishboneSPIController (
.wb_clk_i(OPB_Clk),
.wb_rst_i(rst),
.wb_adr_i(spi_wb_adr_i),
.wb_dat_i(spi_wb_dat_i),
.wb_dat_o(spi_wb_dat_o),
.wb_sel_i(spi_wb_sel_i),
.wb_we_i(spi_wb_we_i),
.wb_stb_i(spi_wb_stb_i),
.wb_cyc_i(spi_wb_cyc_i),
.wb_ack_o(spi_wb_ack_o),
.wb_err_o(spi_wb_err_o),
.wb_int_o(spi_wb_int_o),
// SPI signals
.ss_pad_o(spi_cs),
.sclk_pad_o(spi_sclk),
.mosi_pad_o(spi_dout),
.miso_pad_i(1'b0)
);
opb2wb opb2wb_0 (
.OPB_Clk(OPB_Clk),
.rst(rst),
.opb_abus(opb_abus),
.opb_be(opb_be),
.opb_dbus(opb_dbus),
.opb_rnw(opb_rnw),
.opb_select(opb_select),
.opb_seqaddr(opb_seqaddr),
.sl_dbus(sl_dbus),
.sl_errack(sl_errack),
.sl_retry(sl_retry),
.sl_toutsup(sl_toutsup),
.sl_xferack(sl_xferack),
.wb_data_o(spi_wb_dat_i),
.wb_data_i(spi_wb_dat_o),
.wb_addr_o(spi_wb_adr_i),
.wb_cyc_o(spi_wb_cyc_i),
.wb_stb_o(spi_wb_stb_i),
.wb_sel_o(spi_wb_sel_i),
.wb_we_o(spi_wb_we_i),
.wb_ack_i(spi_wb_ack_o),
.wb_err_i(spi_wb_err_o),
.wb_rty_i(1'b0)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200100; const int INF = 1000 * 1000 * 100; string s[N]; char ch[30]; int d[1000 * 3000 + 10], l[30], r[30]; int lcps(int x) { int sz = s[x].size(); for (int i = sz - 1; i >= 0; i--) r[i] = r[i + 1] + ((s[x][i] - 0 ) << (sz - i - 1)); l[0] = s[x + 1][0] - 0 ; for (int i = 1; i < sz; i++) l[i] = l[i - 1] * 2 + (s[x + 1][i] - 0 ); for (int i = sz; i > 0; i--) if (l[i - 1] == r[sz - i]) return i; return 0; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %20s , ch); for (int j = 0; j < 20 && (ch[j] == 0 || ch[j] == 1 ); j++) s[i] += ch[j]; } int sz = s[0].size(), p = (1 << (sz + 1)), all(0), tmp(0); fill(d, d + p, INF); d[p - 1] = 0; for (int i = 0; i < n; i++) { int t = sz, mn = INF, z; if (i) { t = lcps(i - 1); for (int j = 0; j <= sz; j++) { if (j == 0) { mn = min(all + sz - tmp, mn); if (s[i][0] == 0 ) z = p - 2; else z = 1; } else { mn = min(d[z] + sz - j, mn); z *= 2; if (j < sz) z += s[i][j] - 0 ; z %= p; } } z = 0; mn -= (sz - t); d[p - 1] = min(d[p - 1], mn); for (int j = sz - 1; j >= 0; j--) { int v = (1 << (sz - j - 1)); if (s[i - 1][j] - 0 == 1) { z &= ((1 << (sz - j)) - 1); if ((z & v) == 0) z += v; } else { z |= ((p - 1) ^ ((1 << (sz - j)) - 1)); if ((z & v) != 0) z -= v; } d[z] = min(d[z], mn); } tmp += (sz - t); all += (sz - t); all = min(all, mn + tmp); } else all += sz, tmp += sz, d[p - 1] = sz; } cout << all << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using db = long double; using str = string; using pi = pair<int, int>; template <class T> using V = vector<T>; template <class T, size_t SZ> using AR = array<T, SZ>; using vi = V<int>; using vb = V<bool>; using vpi = V<pi>; const int MOD = 1e9 + 7; const db EPS = 1e-9; const ll BIG = 1e18; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } struct mi { int v; explicit operator int() const { return v; } mi() : v(0) {} mi(ll _v) : v(int(_v % MOD)) { v += (v < 0) * MOD; } }; mi& operator+=(mi& a, mi b) { if ((a.v += b.v) >= MOD) a.v -= MOD; return a; } mi& operator-=(mi& a, mi b) { if ((a.v -= b.v) < 0) a.v += MOD; return a; } mi operator+(mi a, mi b) { return a += b; } mi operator-(mi a, mi b) { return a -= b; } mi operator*(mi a, mi b) { return mi((ll)a.v * b.v); } mi& operator*=(mi& a, mi b) { return a = a * b; } mi pow(mi a, ll p) { assert(p >= 0); return p == 0 ? 1 : pow(a * a, p / 2) * (p & 1 ? a : 1); } mi inv(mi a) { assert(a.v != 0); return pow(a, MOD - 2); } mi operator/(mi a, mi b) { return a * inv(b); } bool operator==(mi a, mi b) { return a.v == b.v; } vector<mi> invs, fac, ifac; void genFac(int SZ) { invs.resize(SZ), fac.resize(SZ), ifac.resize(SZ); invs[1] = fac[0] = ifac[0] = 1; for (int i = (2); i < (SZ); ++i) invs[i] = mi(-(ll)MOD / i * (int)invs[MOD % i]); for (int i = (1); i < (SZ); ++i) fac[i] = fac[i - 1] * i, ifac[i] = ifac[i - 1] * invs[i]; } mi comb(int a, int b) { if (a < b || b < 0) return 0; return fac[a] * ifac[b] * ifac[a - b]; } const int mx = 100005; struct Eff { int n, k; mi first[mx]; void solve() { genFac(100005); cin >> n >> k; map<int, int> cnt; int negs = 0; for (int i = 1; i <= n; i++) { int A; cin >> A; if (A == -1) { negs++; } else { cnt[A]++; } } map<int, mi> all_cnts; for (auto u : cnt) { all_cnts[u.second] = mi(0); } all_cnts[0] = mi(0); first[0] = mi(0); for (int i = 0; i <= n - 1; i++) { first[i + 1] = mi(-n); if (i - 1 >= 0) { first[i + 1] -= mi(i) * mi(k - 1) * first[i - 1]; } first[i + 1] += first[i] * (mi(n) - 2 * mi(i) + mi(i) * mi(k)); first[i + 1] = first[i + 1] / mi(n - i); } vector<mi> k1pows(n + 1, mi(1)); for (int i = 1; i <= n; i++) { k1pows[i] = k1pows[i - 1] * mi(k - 1); } for (auto& u : all_cnts) { for (int i = 0; i <= negs; i++) { u.second += first[u.first + i] * mi(comb(negs, i)) * k1pows[negs - i]; } u.second = u.second / pow(mi(k), negs); } mi ans = mi(0); map<int, int> cnt_cnt; for (auto u : cnt) { cnt_cnt[u.second]++; } cnt_cnt[0] += (k - int((cnt).size())); for (auto u : cnt_cnt) { ans += all_cnts[u.first] * mi(u.second); } ans -= (first[n] + mi(k - 1) * first[0]); cout << ans.v << n ; } }; int main() { cin.tie(0)->sync_with_stdio(0); Eff e; e.solve(); }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return a % b == 0 ? b : gcd(b, a % b); } int main() { int n; scanf( %d , &n); if (n % 2) printf( %d %d n , n / 2, n / 2 + 1); else { for (int a = n / 2 - 1; a; a--) { if (gcd(a, n - a) == 1) { printf( %d %d n , a, n - a); break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m; int a[N], q[N]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> m; for (int i = 0; i < m; ++i) cin >> q[i]; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; sort(q, q + m); sort(a, a + n); int r = n - 1, res = 0; while (r >= 0) { int t = q[0]; while (t-- > 0 && r >= 0) { res += a[r--]; } int k = 2; while (k-- > 0 && r >= 0) r--; } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long double temp; temp = log2(n + 1); if (temp == (int)temp) { cout << temp << endl; } else { cout << (int)(temp) + 1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y / 2; x = (x * x) % p; } return res; } void solve() { long long int n, m, l, h, i; cin >> n >> m; l = 0; h = n * m - 1; while (l < h) { cout << l / m + 1 << << l % m + 1 << n ; cout << h / m + 1 << << h % m + 1 << n ; ++l, --h; } if (l == h) cout << l / m + 1 << << l % m + 1 << n ; } int main() { long long int t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
|
#include <bits/stdc++.h> using namespace std; char s[200005]; char x[26]; int n, m; char a, b; int main() { while (scanf( %d%d , &n, &m) != EOF) { for (int i = 0; i < 26; i++) x[i] = i + a ; getchar(); scanf( %s , s); getchar(); for (int i = 0; i < m; i++) { scanf( %c , &a); getchar(); scanf( %c , &b); getchar(); if (a == b) continue; for (int j = 0; j < 26; j++) { if (x[j] == a) { x[j] = b; continue; } if (x[j] == b) { x[j] = a; continue; } } } int k; for (int i = 0; i < n; i++) { k = s[i] - a ; printf( %c , x[k]); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void seif() { std::ios_base::sync_with_stdio(0); } int xa[] = {-1, -1, -1, 0, 0, 0, 1, 1, 1}; int ya[] = {1, 0, -1, 1, 0, -1, 1, 0, -1}; int anx, any, marx, mary; bool ok = false; char grid[8][8]; bool valid(int x, int y) { if (x < 0 || y < 0 || x > 7 || y > 7 || ok) return false; return true; } void check(int cx, int cy, int deg) { if (cx == 0 && cy == 7) { cout << WIN ; ok = true; } if (ok) return; for (int i = 0; i < 9; i++) { int mtx = cx + xa[i]; int mty = cy + ya[i]; if (!valid(mtx, mty)) continue; if (mtx - deg >= 0 && grid[mtx - deg][mty] == S ) continue; if (mtx - deg - 1 >= 0 && grid[mtx - deg - 1][mty] == S ) continue; check(mtx, mty, deg + 1); } return; } int main() { seif(); bool flag = false; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { cin >> grid[i][j]; if (grid[i][j] == S ) flag = true; } } if (!flag) return cout << WIN , 0; check(7, 0, 0); if (!ok) cout << LOSE ; return 0; }
|
`default_nettype wire
module cache_ram_16entry_512bit(
input clock,
input [63:0] byteena_a,
//Write
input wren,
input [3:0] wraddress,
input [511:0] data,
//Read
input [3:0] rdaddress,
output [511:0] q
);
reg [511:0] b_mem[0:15];
always@(posedge clock)begin
if(wren)begin
b_mem[wraddress] <= func_byteena_o(byteena_a, b_mem[wraddress], data);
end
end
function [511:0] func_byteena_o;
input [63:0] func_byteena;
input [511:0] func_current_data;
input [511:0] func_new_data;
reg [511:0] func_local_data;
begin
func_local_data[7:0] = (func_byteena[0])? func_new_data[7:0] : func_current_data[7:0];
func_local_data[15:8] = (func_byteena[1])? func_new_data[15:8] : func_current_data[15:8];
func_local_data[23:16] = (func_byteena[2])? func_new_data[23:16] : func_current_data[23:16];
func_local_data[31:24] = (func_byteena[3])? func_new_data[31:24] : func_current_data[31:24];
func_local_data[39:32] = (func_byteena[4])? func_new_data[39:32] : func_current_data[39:32];
func_local_data[47:40] = (func_byteena[5])? func_new_data[47:40] : func_current_data[47:40];
func_local_data[55:48] = (func_byteena[6])? func_new_data[55:48] : func_current_data[55:48];
func_local_data[63:56] = (func_byteena[7])? func_new_data[63:56] : func_current_data[63:56];
func_local_data[71:64] = (func_byteena[8])? func_new_data[71:64] : func_current_data[71:64];
func_local_data[79:72] = (func_byteena[9])? func_new_data[79:72] : func_current_data[79:72];
func_local_data[87:80] = (func_byteena[10])? func_new_data[87:80] : func_current_data[87:80];
func_local_data[95:88] = (func_byteena[11])? func_new_data[95:88] : func_current_data[95:88];
func_local_data[103:96] = (func_byteena[12])? func_new_data[103:96] : func_current_data[103:96];
func_local_data[111:104] = (func_byteena[13])? func_new_data[111:104] : func_current_data[111:104];
func_local_data[119:112] = (func_byteena[14])? func_new_data[119:112] : func_current_data[119:112];
func_local_data[127:120] = (func_byteena[15])? func_new_data[127:120] : func_current_data[127:120];
func_local_data[135:128] = (func_byteena[16])? func_new_data[135:128] : func_current_data[135:128];
func_local_data[143:136] = (func_byteena[17])? func_new_data[143:136] : func_current_data[143:136];
func_local_data[151:144] = (func_byteena[18])? func_new_data[151:144] : func_current_data[151:144];
func_local_data[159:152] = (func_byteena[19])? func_new_data[159:152] : func_current_data[159:152];
func_local_data[167:160] = (func_byteena[20])? func_new_data[167:160] : func_current_data[167:160];
func_local_data[175:168] = (func_byteena[21])? func_new_data[175:168] : func_current_data[175:168];
func_local_data[183:176] = (func_byteena[22])? func_new_data[183:176] : func_current_data[183:176];
func_local_data[191:184] = (func_byteena[23])? func_new_data[191:184] : func_current_data[191:184];
func_local_data[199:192] = (func_byteena[24])? func_new_data[199:192] : func_current_data[199:192];
func_local_data[207:200] = (func_byteena[25])? func_new_data[207:200] : func_current_data[207:200];
func_local_data[215:208] = (func_byteena[26])? func_new_data[215:208] : func_current_data[215:208];
func_local_data[223:216] = (func_byteena[27])? func_new_data[223:216] : func_current_data[223:216];
func_local_data[231:224] = (func_byteena[28])? func_new_data[231:224] : func_current_data[231:224];
func_local_data[239:232] = (func_byteena[29])? func_new_data[239:232] : func_current_data[239:232];
func_local_data[247:240] = (func_byteena[30])? func_new_data[247:240] : func_current_data[247:240];
func_local_data[255:248] = (func_byteena[31])? func_new_data[255:248] : func_current_data[255:248];
func_local_data[263:256] = (func_byteena[32])? func_new_data[263:256] : func_current_data[263:256];
func_local_data[271:264] = (func_byteena[33])? func_new_data[271:264] : func_current_data[271:264];
func_local_data[279:272] = (func_byteena[34])? func_new_data[279:272] : func_current_data[279:272];
func_local_data[287:280] = (func_byteena[35])? func_new_data[287:280] : func_current_data[287:280];
func_local_data[295:288] = (func_byteena[36])? func_new_data[295:288] : func_current_data[295:288];
func_local_data[303:296] = (func_byteena[37])? func_new_data[303:296] : func_current_data[303:296];
func_local_data[311:304] = (func_byteena[38])? func_new_data[311:304] : func_current_data[311:304];
func_local_data[319:312] = (func_byteena[39])? func_new_data[319:312] : func_current_data[319:312];
func_local_data[327:320] = (func_byteena[40])? func_new_data[327:320] : func_current_data[327:320];
func_local_data[335:328] = (func_byteena[41])? func_new_data[335:328] : func_current_data[335:328];
func_local_data[343:336] = (func_byteena[42])? func_new_data[343:336] : func_current_data[343:336];
func_local_data[351:344] = (func_byteena[43])? func_new_data[351:344] : func_current_data[351:344];
func_local_data[359:352] = (func_byteena[44])? func_new_data[359:352] : func_current_data[359:352];
func_local_data[367:360] = (func_byteena[45])? func_new_data[367:360] : func_current_data[367:360];
func_local_data[375:368] = (func_byteena[46])? func_new_data[375:368] : func_current_data[375:368];
func_local_data[383:376] = (func_byteena[47])? func_new_data[383:376] : func_current_data[383:376];
func_local_data[391:384] = (func_byteena[48])? func_new_data[391:384] : func_current_data[391:384];
func_local_data[399:392] = (func_byteena[49])? func_new_data[399:392] : func_current_data[399:392];
func_local_data[407:400] = (func_byteena[50])? func_new_data[407:400] : func_current_data[407:400];
func_local_data[415:408] = (func_byteena[51])? func_new_data[415:408] : func_current_data[415:408];
func_local_data[423:416] = (func_byteena[52])? func_new_data[423:416] : func_current_data[423:416];
func_local_data[431:424] = (func_byteena[53])? func_new_data[431:424] : func_current_data[431:424];
func_local_data[439:432] = (func_byteena[54])? func_new_data[439:432] : func_current_data[439:432];
func_local_data[447:440] = (func_byteena[55])? func_new_data[447:440] : func_current_data[447:440];
func_local_data[455:448] = (func_byteena[56])? func_new_data[455:448] : func_current_data[455:448];
func_local_data[463:456] = (func_byteena[57])? func_new_data[463:456] : func_current_data[463:456];
func_local_data[471:464] = (func_byteena[58])? func_new_data[471:464] : func_current_data[471:464];
func_local_data[479:472] = (func_byteena[59])? func_new_data[479:472] : func_current_data[479:472];
func_local_data[487:480] = (func_byteena[60])? func_new_data[487:480] : func_current_data[487:480];
func_local_data[495:488] = (func_byteena[61])? func_new_data[495:488] : func_current_data[495:488];
func_local_data[503:496] = (func_byteena[62])? func_new_data[503:496] : func_current_data[503:496];
func_local_data[511:504] = (func_byteena[63])? func_new_data[511:504] : func_current_data[511:504];
func_byteena_o = func_local_data;
end
endfunction
reg [511:0] b_data_buff;
always@(posedge clock)begin
b_data_buff <= b_mem[rdaddress];
end
assign q = b_data_buff;//b_mem[rdaddress];
endmodule
`default_nettype none
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_TB_V
`define SKY130_FD_SC_HD__AND3_TB_V
/**
* and3: 3-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int N = 300005; long long n, e, idx[N], low[N], T, q[300005], ans = 0, ans2 = 1, scc[100005], mini[300005], cn, second[3000005]; vector<vector<long long> > g; vector<long long> S; bool vis[N]; long long compID[N], cmp; void DFS(int u) { idx[u] = low[u] = ++T; S.push_back(u); vis[u] = true; for (int i = 0; i < g[u].size(); ++i) { long long v = g[u][i]; if (idx[v] == 0) DFS(v); if (vis[v]) low[u] = min(low[u], low[v]); } if (idx[u] == low[u]) { long long ee = 1e10; cn++; while (true) { long long v = S.back(); ee = min(ee, q[v]); scc[v] = cn; S.pop_back(); vis[v] = false; compID[v] = cmp; if (v == u) break; } mini[cn] = ee; ans += ee; ++cmp; } } int main() { cin >> n; g.resize(n); for (int i = 0; i < n; i++) cin >> q[i]; cin >> e; for (int i = 0; i < e; ++i) { int from, to; cin >> from >> to; --from; --to; g[from].push_back(to); } for (int i = 0; i < n; ++i) { if (idx[i] == 0) { DFS(i); } } for (int i = 0; i < n; i++) { int in1 = scc[i]; int uu = mini[in1]; if (q[i] == uu) second[in1]++; } for (int i = 1; i <= cn; i++) { ans2 *= second[i]; ans2 %= mod; } cout << ans << << ans2; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb.v,v $
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e9 + 7; vector<long long int> v; long long int calcmulti(string s, long long int l, long long int r) { long long int ans = 1; string z = ; for (long long int i = l; i <= r; i++) { if (s[i] == * ) { ans *= stoll(z); z = ; } else z += s[i]; } ans *= stoll(z); return ans; } long long int calc(string s, long long int ss, long long int st) { if (ss == st) return s[ss] - 0 ; long long int mid = (ss + st) / 2, mindist = MAXN; for (long long int i = mid; i <= st; i++) { if (s[i] == + ) { mindist = min(mindist, i); break; } } for (long long int i = mid; i >= ss; i--) { if (s[i] == + ) { mindist = min(mindist, i); break; } } if (mindist == MAXN) return calcmulti(s, ss, st); return calc(s, ss, mindist - 1) + calc(s, mindist + 1, st); } long long int change(string s, long long int ss, long long int st) { string z; long long int ans = calc(s, ss, st); for (long long int i = 0; i <= ss - 1; i++) z += s[i]; z += to_string(ans); for (long long int i = st + 1; i <= (long long int)s.length() - 1; i++) z += s[i]; return calc(z, 0, (long long int)z.length() - 1); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int ans = 0; string s; cin >> s; for (long long int i = 0; i < s.length(); i++) if (s[i] == * ) v.push_back(i); if (v.size() == 0) { cout << calc(s, 0, (long long int)s.length() - 1); return 0; } if (v.size() == 1) { cout << max(change(s, 0, v[0] - 1), max(change(s, v[0] + 1, (long long int)s.length() - 1), calc(s, 0, (long long int)s.length() - 1))); ; return 0; } ans = max(ans, calc(s, 0, (long long int)s.length() - 1)); for (long long int i = 0; i < (long long int)v.size(); i++) { ans = max(ans, change(s, 0, v[i] - 1)); ans = max(ans, change(s, v[i] + 1, (long long int)s.length() - 1)); for (long long int j = i + 1; j < (long long int)v.size(); j++) { ans = max(ans, change(s, v[i] + 1, v[j] - 1)); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 101000 * 8; const int G = 3; const int Mod = 998244353; int n; long long m; int Fc[maxN], Ifc[maxN]; int In[maxN], A[maxN], B[maxN], C[maxN], R[maxN]; int QPow(int x, int cnt); void NTT(int *P, int N, int opt); int main() { Fc[0] = Ifc[0] = 1; for (int i = 1; i < maxN; i++) Fc[i] = 1ll * Fc[i - 1] * i % Mod; Ifc[maxN - 1] = QPow(Fc[maxN - 1], Mod - 2); for (int i = maxN - 2; i >= 1; i--) Ifc[i] = 1ll * Ifc[i + 1] * (i + 1) % Mod; scanf( %d%lld , &n, &m); int N = 1; while (N <= n + n) N <<= 1; m = m % (Mod - 1); for (int i = 0; i <= n; i++) scanf( %d , &In[i]), B[i] = 1ll * Fc[i] * In[i] % Mod; for (int i = 0; i <= n; i++) C[i] = Ifc[n - i]; NTT(B, N, 1); NTT(C, N, 1); for (int i = 0; i < N; i++) B[i] = 1ll * B[i] * C[i] % Mod; NTT(B, N, -1); for (int i = 0; i <= n; i++) A[i] = 1ll * B[i + n] * Ifc[i] % Mod; for (int i = 0; i <= n; i++) A[i] = 1ll * A[i] * QPow(QPow(i + 1, Mod - 2), m) % Mod * Fc[i] % Mod; memset(C, 0, sizeof(C)); for (int i = 0; i <= n; i++) C[i] = (i & 1) ? Mod - Ifc[i] : Ifc[i]; reverse(&C[0], &C[n + 1]); NTT(A, N, 1); NTT(C, N, 1); for (int i = 0; i < N; i++) A[i] = 1ll * A[i] * C[i] % Mod; NTT(A, N, -1); for (int i = 0; i <= n; i++) printf( %I64d , 1ll * A[i + n] * Ifc[i] % Mod); printf( n ); return 0; } int QPow(int x, int cnt) { int ret = 1; while (cnt) { if (cnt & 1) ret = 1ll * ret * x % Mod; cnt >>= 1; x = 1ll * x * x % Mod; } return ret; } void NTT(int *P, int N, int opt) { int l = -1, _n = N; while (_n) ++l, _n >>= 1; for (int i = 0; i < N; i++) R[i] = (R[i >> 1] >> 1) | ((i & 1) << (l - 1)); for (int i = 0; i < N; i++) if (i < R[i]) swap(P[i], P[R[i]]); for (int i = 1; i < N; i <<= 1) { int dw = QPow(G, (Mod - 1) / (i << 1)); if (opt == -1) dw = QPow(dw, Mod - 2); for (int j = 0; j < N; j += (i << 1)) for (int k = 0, w = 1; k < i; k++, w = 1ll * w * dw % Mod) { int X = P[j + k], Y = 1ll * P[j + k + i] * w % Mod; P[j + k] = (X + Y) % Mod; P[j + k + i] = (X - Y + Mod) % Mod; } } if (opt == -1) { int inv = QPow(N, Mod - 2); for (int i = 0; i < N; i++) P[i] = 1ll * P[i] * inv % Mod; } return; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__PROBEC_P_FUNCTIONAL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long n; long long head[1100000], a[1100000]; struct node { long long v, nex; } bian[2100000]; long long cnt; void add(long long x, long long y) { bian[++cnt].v = y; bian[cnt].nex = head[x]; head[x] = cnt; } long long tot[1100000], d[1100000], f[1100000], zong; void dfs(long long x, long long fa) { tot[x] = 1; for (long long i = head[x]; i; i = bian[i].nex) { long long v = bian[i].v; if (v == fa) continue; dfs(v, x); tot[x] += tot[v]; } f[1] += tot[x]; } long long ans = 0; void dp(long long x, long long fa) { ans = max(ans, f[x]); for (long long i = head[x]; i; i = bian[i].nex) { long long v = bian[i].v; if (v == fa) continue; f[v] = f[x] - tot[v] + n - tot[v]; dp(v, x); } } signed main() { cin >> n; for (long long i = 1; i < n; i++) { long long x, y; scanf( %lld%lld , &x, &y); add(x, y), add(y, x); } dfs(1, 0); dp(1, 0); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n, a, b; cin >> n >> a >> b; string s, ans; for (long long i = 0; i < b; i++) { long long m = a ; char c = m + i; s += c; } for (long long i = 0; i < (n / b); i++) { ans += s; } long long m = ans.length(); for (long long i = 0; i < n - m; i++) { ans += s[i]; } cout << ans << endl; } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:57:43 03/22/2015
// Design Name: dlatch_nand
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/latch_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: dlatch_nand
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module latch_test;
// Inputs
reg D;
reg en;
// Outputs
wire Qnor, Qnand, QNnand, QNnor;
wire Qnor_n, Qnand_n, QNnand_n, QNnor_n;
// Variables
integer i;
// Instantiate the Unit Under Test (UUT)
// Positive Level Triggered Gated D-Latch from NAND gate
dlatch_nand uut (
.Q(Qnand),
.Q_n(Qnand_n),
.D(D),
.en(en)
);
// Positive Level Triggered Gated D-Latch from NOR gate
dlatch_nor uut2 (
.Q(Qnor),
.Q_n(Qnor_n),
.D(D),
.en(en)
);
// Negative Level Triggered Gated D-Latch from NAND gate
dnlatch_nand uut3 (
.Q(QNnand),
.Q_n(QNnand_n),
.D(D),
.en(en)
);
// Negative Level Triggered Gated D-Latch from NOR gate
dnlatch_nor uut4 (
.Q(QNnor),
.Q_n(QNnor_n),
.D(D),
.en(en)
);
initial begin
// Initialize Inputs
D = 0;
en = 1;
// View 16 random test cases.
for(i=0; i<16; i = i + 1)
begin
#10 D = $random % 2; en = $random % 2;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, k; cin >> n >> k; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; ; sort(a.begin(), a.end()); long long mm = a[n / 2]; for (int i = n / 2; i < n - 1; i++) { long long r = a[i + 1] - a[i]; if (k >= r * (i - n / 2 + 1)) k -= r * (i - n / 2 + 1); else if (k > 0) { mm += k / (i - n / 2 + 1); k = 0; break; } else break; mm = a[i + 1]; } if (k > 0) mm += k / (n / 2 + 1); cout << mm << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k, idx = 0; cin >> n >> k; pair<int, int> inst[n]; vector<int> v; for (int i = 1; i <= n; i++) { int t; cin >> t; inst[i - 1] = make_pair(t, i); } sort(inst, inst + n); while (k >= inst[idx].first && idx < n) { v.push_back(inst[idx].second); k -= inst[idx].first; idx++; } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; struct node { long long v[10]; int tag[10]; void init(int x) { int y = 1; memset(v, 0, sizeof(v)); while (x) { v[x % 10] += y; x /= 10; y *= 10; } } void updtag(int* _tag) { for (int i = 0; i < 10; i++) tag[i] = _tag[tag[i]]; } bool havetag() { for (int i = 0; i < 10; i++) if (tag[i] != i) return 1; return 0; } } f[N * 4]; int a[N]; int n, q; int tag[10]; long long ans; void upd(int s) { for (int i = 0; i < 10; i++) f[s].v[i] = f[s + s].v[i] + f[s + s + 1].v[i]; } void build(int l, int r, int s) { for (int i = 0; i < 10; i++) f[s].tag[i] = i; if (l == r) { f[s].init(a[l]); return; } build(l, (l + r) / 2, s + s); build((l + r) / 2 + 1, r, s + s + 1); upd(s); } long long tmp[10] = {0}; void down(int l, int r, int s) { if (!f[s].havetag()) return; for (int i = 0; i < 10; i++) tmp[f[s].tag[i]] += f[s].v[i]; for (int i = 0; i < 10; i++) f[s].v[i] = tmp[i], tmp[i] = 0; if (l != r) f[s + s].updtag(f[s].tag), f[s + s + 1].updtag(f[s].tag); for (int i = 0; i < 10; i++) f[s].tag[i] = i; } void change(int l, int r, int s, int ll, int rr) { down(l, r, s); if (r < ll || rr < l) return; if (ll <= l && r <= rr) { f[s].updtag(tag); down(l, r, s); return; } change(l, (l + r) / 2, s + s, ll, rr); change((l + r) / 2 + 1, r, s + s + 1, ll, rr); upd(s); } void get(int l, int r, int s, int ll, int rr) { down(l, r, s); if (r < ll || rr < l) return; if (ll <= l && r <= rr) { for (int i = 1; i < 10; i++) ans += f[s].v[i] * i; return; } get(l, (l + r) / 2, s + s, ll, rr); get((l + r) / 2 + 1, r, s + s + 1, ll, rr); } int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } build(1, n, 1); while (q--) { int sig, l, r, x, y; scanf( %d %d %d , &sig, &l, &r); if (sig == 1) { scanf( %d %d , &x, &y); for (int i = 0; i < 10; i++) tag[i] = i; tag[x] = y; change(1, n, 1, l, r); continue; } ans = 0; get(1, n, 1, l, r); printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int l, r; cin >> l >> r; if (l == r) { cout << l; return 0; } cout << 2 << endl; }
|
`include "common.vh"
`timescale 1ns/10ps
module Gpio(clk, strobe, rw, reset, addr, data_i, data_o, gpio);
// four registers
// 0 : enable (1 for enable)
// 1 : read-write (1 for write)
// 2 : read state (1 for high)
// 3 : write state (1 for high)
parameter COUNT = 32;
localparam SIZE = 4;
input wire clk, strobe, rw, reset;
input wire[31:0] addr, data_i;
output reg [31:0] data_o;
inout wire[COUNT-1:0] gpio;
localparam EN = 0, RW = 1, RS = 2, WS = 3;
reg [COUNT-1:0] state[SIZE-1:0];
integer k;
initial for (k = 0; k < SIZE; k = k + 1) state[k] = 0;
genvar i;
generate for (i = 0; i < COUNT; i = i + 1)
assign gpio[i] = (state[EN][i] & state[RW][i]) ? state[WS][i] : 1'bz;
endgenerate
always @(posedge clk) begin
state[RS] <= state[EN] & ~state[RW] & gpio;
if (reset) begin
for (k = 0; k < SIZE; k = k + 1)
state[k] <= 0;
end else if (strobe) begin
if (rw)
state[addr] <= data_i[COUNT-1:0];
else
data_o <= {{32-COUNT{1'b0}},state[addr]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #define cp ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define ll long long int #define vint vector<int> #define vllint vector<ll> #define pair_int pair<int , int> #define pair_ll_int pair<ll , ll> #define vector_of_pair_int vector<pair_int> #define pb push_back #define test_case int t; cin>>t; while(t--) #define umap unordered_map <int,int> #define mapint map<int,int> #define infinity 1000000000 #define mp make_pair int main() { cp test_case { ll n; cin>>n; if(n<=256) { int count=0; ll temp=n; while(temp!=1) { count++; if(temp%2==0) temp=temp/2; else temp=temp/2+1; } cout<<count+n-3<<endl; for (int i = 1; i <=n-3; ++i) { /* code */ cout<<3+i-1<< <<3+i<<endl; } for (int i = 0; i < count; ++i) { /* code */ cout<<n<< <<2<<endl; } } else { int count=0; ll temp=n; while(temp!=1) { count++; temp=ceil(float(temp)/float(16)); } cout<<count+n<<endl; for (int i = 3; i <n; ++i) { /* code */ if(i!=16) { cout<<i<< <<i+1<<endl; } } for (int i = 0; i < count; ++i) { /* code */ cout<<n<< <<16<<endl; } for (int i = 0; i < 4; ++i) { /* code */ cout<<16<< <<2<<endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const long long INF = 1ll << 60; const double Inf = 1e20; const double eps = 1e-9; void gmax(int &a, int b) { a = (a > b ? a : b); } void gmin(int &a, int b) { a = (a < b ? a : b); } const int P = 1e9 + 7; const int maxn = 1000050; int n, m, x[5], y[5], sz[maxn], Ans; set<int> key; map<int, int> id, g; vector<int> adj[maxn]; bool vis[maxn]; int calc(int x) { int l = x, r = x, ret = 0; while (l <= n) { ret = (ret + min(r, n) - l + 1) % P; l = l << 1; r = r << 1 | 1; } return ret; } void dfs(int x, int t) { Ans = (Ans + 1ll * sz[x] * t) % P; vis[x] = true; for (auto p : adj[x]) if (!vis[p]) dfs(p, t); vis[x] = false; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) { scanf( %d%d , &x[i], &y[i]); int t = x[i]; while (t) { key.insert(t); t >>= 1; } t = y[i]; while (t) { key.insert(t); t >>= 1; } } key.insert(1); for (auto p : key) { if (key.find(p << 1) == key.end() && key.find(p << 1 | 1) == key.end()) g[p] = calc(p); else { g[p] = 1; if (key.find(p << 1) == key.end() && (p << 1) <= n) g[p << 1] = calc(p << 1); if (key.find(p << 1 | 1) == key.end() && (p << 1 | 1) <= n) g[p << 1 | 1] = calc(p << 1 | 1); } } for (pair<int, int> p : g) { id[p.first] = ((int)(id).size()); sz[id[p.first]] = p.second; } for (pair<int, int> p : id) if (p.first != 1) { adj[id[p.first >> 1]].push_back(p.second); adj[p.second].push_back(id[p.first >> 1]); } for (int i = 1; i <= m; ++i) adj[id[x[i]]].push_back(id[y[i]]), adj[id[y[i]]].push_back(id[x[i]]); for (pair<int, int> p : id) dfs(p.second, sz[p.second]); printf( %d n , Ans); return 0; }
|
module mac(
input wire reset,
// IN PORT
input wire [31:0] data_in,
input wire data_in_clock,
input wire data_in_enable,
input wire data_in_start,
input wire data_in_end,
// OUT PORT
output wire [31:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output wire data_out_start,
output wire data_out_end,
output wire [6:0] frame_count,
input wire tx_clock,
input wire rx_clock,
input wire carrier_sense,
input wire collision,
output wire tx_enable,
output wire [7:0] tx_data,
input wire rx_data_valid,
input wire [7:0] rx_data,
input wire rx_error
);
wire [7:0] tx_fifo_data;
wire tx_fifo_data_read;
wire tx_fifo_data_start;
wire tx_fifo_data_end;
wire [6:0] tx_fifo_count;
wire tx_fifo_retry;
wire [7:0] rx_fifo_data;
wire rx_fifo_data_write;
wire rx_fifo_data_start;
wire rx_fifo_data_end;
wire rx_fifo_full;
wire rx_fifo_error;
tx_sm U_tx_sm(
.reset(reset),
.clock(tx_clock),
.fifo_data(tx_fifo_data),
.fifo_data_read(tx_fifo_data_read),
.fifo_data_start(tx_fifo_data_start),
.fifo_data_end(tx_fifo_data_end),
.fifo_count(tx_fifo_count),
.fifo_retry(tx_fifo_retry),
.mode(1'b1),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
mac_fifo #(
.DATA_IN_WIDTH(32),
.DATA_OUT_WIDTH(8),
.FIFO_DEPTH(12)
) U_mac_fifo_tx (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.data_out(tx_fifo_data),
.data_out_clock(tx_clock),
.data_out_enable(tx_fifo_data_read),
.data_out_start(tx_fifo_data_start),
.data_out_end(tx_fifo_data_end),
.retry(tx_fifo_retry),
.error(1'b0),
.frame_count(tx_fifo_count)
);
rx_sm U_rx_sm(
.reset(reset),
.clock(rx_clock),
.fifo_data(rx_fifo_data),
.fifo_data_write(rx_fifo_data_write),
.fifo_data_start(rx_fifo_data_start),
.fifo_data_end(rx_fifo_data_end),
.fifo_full(rx_fifo_full),
.fifo_error(rx_fifo_error),
.rx_data_valid(rx_data_valid),
.rx_error(rx_error),
.rx_data(rx_data)
);
mac_fifo #(
.DATA_IN_WIDTH(8),
.DATA_OUT_WIDTH(32),
.FIFO_DEPTH(12)
) U_mac_fifo_rx (
.reset(reset),
.data_in(rx_fifo_data),
.data_in_clock(rx_clock),
.data_in_enable(rx_fifo_data_write),
.data_in_start(rx_fifo_data_start),
.data_in_end(rx_fifo_data_end),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.retry(1'b0),
.error(rx_fifo_error),
.frame_count(frame_count)
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Include definition of the control signals
`include "control.h"
// Non-synthesizable behavioral RTL model for the instruction memory
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Data output read from the data memory
output [0:127] data_out;
// ===============================================================
// Input signals
// Data input stored into the data memory
input [0:127] data_in;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input [0:31] mem_ctrl_addr;
// Clock signal
input clk;
// Control signals for the data memory
input [0:1] dm_ctrl_sig;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:31] data_out; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [0:127] data_mem [0:255]; // Store the data here
// Store instruction address in the instruction memory
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",data_mem);
end
// A change in the instruction address activates this...
always @(posedge clk)
begin
/**
* Check the control signal and implement the appropriate
* function
*/
case(dm_ctrl_sig)
`memwld:
begin
// Read the data from the memory
data_out<=data_mem[mem_ctrl_addr];
end
`memwst:
begin
// Write the data to the memory
data_mem[mem_ctrl_addr]<=data_in;
end
`memnop:
begin
data_out<=128'd0;
end
default:
begin
data_out<=128'd0;
end
endcase
end
endmodule
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [4:0] write_address;
wire [4:0] read_address;
wire [5:0] read_data_unreg;
reg [5:0] read_data = 6'b0;
wire [5:0] write_data;
wire write_enable;
wire [5:0] rom_read_data;
wire [4:0] rom_read_address;
assign rom_read_data = {~rom_read_address[0], rom_read_address[4:0]};
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [4:0] error_address;
wire [5:0] expected_data;
wire [5:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(5),
.DATA_WIDTH(6),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(1),
// 32-bit LUT memories are 0-31
.MAX_ADDRESS(31),
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
RAM32M #(
.INIT_C(64'b0101_0101_0101_0101_0101_0101_0101_0101_1111_1111_1111_1111_0000_0000_0000_0000),
.INIT_B(64'b1111_1111_0000_0000_1111_1111_0000_0000_1111_0000_1111_0000_1111_0000_1111_0000),
.INIT_A(64'b1100_1100_1100_1100_1100_1100_1100_1100_1010_1010_1010_1010_1010_1010_1010_1010)
) dram(
.WCLK(clk),
.ADDRD(write_address),
.ADDRC(read_address),
.ADDRB(read_address),
.ADDRA(read_address),
.DOC(read_data_unreg[5:4]),
.DOB(read_data_unreg[3:2]),
.DOA(read_data_unreg[1:0]),
.DIC(write_data[5:4]),
.DIB(write_data[3:2]),
.DIA(write_data[1:0]),
.WE(write_enable)
);
always @(posedge clk) begin
read_data <= read_data_unreg;
end
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(6),
.ADDR_WIDTH(5)
) output_logic(
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; constexpr int MAXN = 5 + 50; constexpr ll INF = 1000000000000000002LL; namespace dsu { int f[MAXN], sz[MAXN]; void build(int n) { fill(sz, sz + n, 1); for (int i = (int)0; i < (int)n; ++i) f[i] = i; } int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } bool join(int x, int y) { if ((x = find(x)) == (y = find(y))) return false; if (sz[x] < sz[y]) swap(x, y); sz[x] += sz[y]; f[y] = x; return true; } bool connected(int i, int j) { return find(i) == find(j); } } // namespace dsu ll memo[MAXN], f[MAXN]; int res[MAXN]; bitset<MAXN> used; ll add(ll a, ll b) { if (a + b >= INF) return INF; return a + b; } ll mul(ll a, ll b) { long double ans = (long double)(a) * (long double)(b); if (ans >= INF) return INF; return a * b; } ll dp(int len) { ll& ans = memo[len]; if (~ans) { assert(ans >= 0); return ans; } if (len == 0) return ans = 1; ans = 0; for (int i = 1; i <= len; ++i) ans = add(ans, mul(dp(len - i), f[max(0, i - 2)])); return ans; } void rebuild(int len, ll k, int pos, int n) { if (len == 0) { assert(pos == n); return; } ll ans = 0; for (int i = 1; i <= len; ++i) { ll ol = ans; ans = add(ans, mul(dp(len - i), f[max(0, i - 2)])); if (k <= ans) { k -= ol; ll j = k / dp(len - i); while (mul(j, dp(len - i)) < k) ++j; k -= mul(j - 1, dp(len - i)); res[pos] = i + pos; dsu::build(MAXN); used.reset(); for (int posin = 2; posin <= i; ++posin) { int put = -1; ll ac = 0, olac; for (int num = 1; num < i; ++num) { if (dsu::connected(num, posin) || used[num]) continue; olac = ac; ac = add(ac, f[max(0, i - posin - 1)]); if (j <= ac) { put = num; break; } } assert(put != -1); res[pos + posin - 1] = put + pos; used[put] = true; dsu::join(put, posin); j -= olac; } rebuild(len - i, k, i + pos, n); return; } } assert(false); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); f[0] = 1; for (int i = (int)1; i < (int)MAXN; ++i) { if (f[i - 1] == INF) { f[i] = f[i - 1]; } else { f[i] = min(INF, 1LL * i * f[i - 1]); } } memset(memo, -1, sizeof memo); int tc; cin >> tc; while (tc--) { int n; ll k; cin >> n >> k; if (k <= dp(n)) { rebuild(n, k, 0, n); for (int i = (int)0; i < (int)n; ++i) cout << res[i] << ; } else { cout << -1; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pie = acos(-1); int n, m, i, N, f[1100000], t, s, j, k, chz[266], ans, a[4][1100000], b[4][1100000], gs[4], use[1100000]; char s1[1100000], s2[1100000]; struct fs { double x, y; } w[1100000], A[1100000], B[1100000], C[1100000], v, ww; fs operator+(fs x, fs y) { fs t; t.x = x.x + y.x; t.y = x.y + y.y; return t; } fs operator-(fs x, fs y) { fs t; t.x = x.x - y.x; t.y = x.y - y.y; return t; } fs operator*(fs x, fs y) { fs t; t.x = x.x * y.x - x.y * y.y; t.y = x.y * y.x + y.y * x.x; return t; } void Init() { for (i = 1; i < N; i++) f[i] = (f[i >> 1] >> 1) + ((i & 1) << t); w[1].x = cos(2 * pie / N); w[1].y = sin(2 * pie / N); for (i = 2; i <= N; i++) w[i] = w[i - 1] * w[1]; w[0] = w[N]; } void FFT(fs *a, int F) { int i, j, k; for (i = 0; i < N; i++) if (i < f[i]) swap(a[i], a[f[i]]); for (i = 1; i < N; i <<= 1) { s = (N / i) >> 1; for (j = 0; j < N; j += i << 1) for (k = j; k < j + i; k++) { if (F > 0) ww = w[(k - j) * s]; else ww = w[N - (k - j) * s]; v = a[k]; a[k] = v + ww * a[k + i]; a[k + i] = v - ww * a[k + i]; } } if (F < 0) for (i = 0; i < N; i++) a[i].x /= N; } int main() { scanf( %d%d%d , &n, &m, &k); chz[ A ] = 0; chz[ C ] = 1; chz[ G ] = 2; chz[ T ] = 3; for (N = 1; N < n || N < m; N <<= 1, t++) ; N <<= 1; Init(); scanf( %s , s1); scanf( %s , s2); for (i = 0; i <= k && i < n; i++) a[chz[s1[i]]][0]++; for (i = 1; i < n; i++) { for (j = 0; j < 4; j++) a[j][i] = a[j][i - 1]; if (i > k) a[chz[s1[i - k - 1]]][i]--; if (i + k < n) a[chz[s1[i + k]]][i]++; } for (i = 0; i < n; i++) for (j = 0; j < 4; j++) a[j][i] = a[j][i] > 0; for (i = 0; i < m; i++) b[chz[s2[i]]][m - i - 1] = 1, gs[chz[s2[i]]]++; memset(use, -1, sizeof(use)); for (i = 0; i < 4; i++) { for (j = 0; j < N; j++) A[j].x = a[i][j], A[j].y = 0; for (j = 0; j < N; j++) B[j].x = b[i][j], B[j].y = 0; FFT(A, 1); FFT(B, 1); for (j = 0; j < N; j++) C[j] = A[j] * B[j]; FFT(C, -1); for (j = 0; j < N; j++) if ((int)(C[j].x + 0.5) != gs[i]) use[j] = 0; } for (i = 0; i < N; i++) if (use[i] < 0) ans++; printf( %d n , ans); }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module macc_simple (
input wire clk,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk)
Z <= Z + (A * B);
endmodule
module macc_simple_clr (
input wire clk,
input wire clr,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk)
if (clr) Z <= (A * B);
else Z <= Z + (A * B);
endmodule
module macc_simple_arst (
input wire clk,
input wire rst,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else Z <= Z + (A * B);
endmodule
module macc_simple_ena (
input wire clk,
input wire ena,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk)
if (ena) Z <= Z + (A * B);
endmodule
module macc_simple_arst_clr_ena (
input wire clk,
input wire rst,
input wire clr,
input wire ena,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else if (ena) begin
if (clr) Z <= (A * B);
else Z <= Z + (A * B);
end
endmodule
module macc_simple_preacc (
input wire clk,
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
reg [15:0] acc;
assign Z = acc + (A * B);
always @(posedge clk)
acc <= Z;
endmodule
module macc_simple_preacc_clr (
input wire clk,
input wire clr,
input wire [ 7:0] A,
input wire [ 7:0] B,
output reg [15:0] Z
);
reg [15:0] acc;
assign Z = (clr) ? (A * B) : (acc + (A * B));
always @(posedge clk)
acc <= Z;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1000000; const int Inf = 0x3f3f3f3f; int n, m, k; pair<int, int> edge[Maxn + 5]; int a[Maxn + 5]; map<pair<int, int>, int> mp; int deg[Maxn + 5], sz[Maxn + 5], st[Maxn + 5], col[Maxn + 5]; vector<pair<int, int> > g[Maxn + 5]; int ans[Maxn + 5]; void match(int u, int fa, int from, int to) { for (int i = 0; i < (int)g[u].size(); i++) { if (g[u][i].first == from) { g[u][i].first = to; match(g[u][i].second, u, to, from); } } for (int i = 0; i < (int)g[u].size(); i++) { if (g[u][i].second == fa) { g[u][i].first = from; } } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) { scanf( %*d ); } for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); if (u > v) { swap(u, v); } edge[i] = make_pair(u, v + n); deg[u]++; deg[v + n]++; } n = (n << 1); st[0] = 1; for (int i = 1; i <= n; i++) { sz[i] = (deg[i] - 1) / k + 1; st[i] = st[i - 1] + sz[i - 1]; } for (int i = 1; i <= m; i++) { int u = edge[i].first, v = edge[i].second; g[st[u]].push_back(make_pair(Inf, st[v])); g[st[v]].push_back(make_pair(Inf, st[u])); edge[i] = make_pair(st[u], st[v]); mp[edge[i]] = i; col[u]++; col[v]++; if (col[u] == k) { st[u]++; col[u] = 0; } if (col[v] == k) { st[v]++; col[v] = 0; } } for (int i = 1; i <= m; i++) { int u = edge[i].first, v = edge[i].second; int pos_u = 0, pos_v = 0; sort(g[u].begin(), g[u].end()); sort(g[v].begin(), g[v].end()); for (int j = 0; j < (int)g[u].size(); j++) { if (j + 1 != g[u][j].first) { pos_u = j + 1; break; } } for (int j = 0; j < (int)g[v].size(); j++) { if (j + 1 != g[v][j].first) { pos_v = j + 1; break; } } for (int j = 0; j < (int)g[u].size(); j++) { if (g[u][j].second == v) { g[u][j].first = pos_u; } } match(v, u, pos_u, pos_v); } for (int i = 1; i <= st[n]; i++) { for (int j = 0; j < (int)g[i].size(); j++) { if (i < g[i][j].second) { ans[mp[make_pair(i, g[i][j].second)]] = g[i][j].first; } } } for (int i = 1; i <= m; i++) { printf( %d n , ans[i]); } return 0; }
|
//register module to load values stored in registers
module register(clk, loada, loadb, write, readnum, reg0, reg1, reg2, reg3, reg4 ,reg5 ,reg6 ,reg7, A, B);
parameter width= 1;
input clk, loada, loadb, write;
input [2:0] readnum;
input [15:0] reg0, reg1, reg2, reg3, reg4 ,reg5 ,reg6 ,reg7;
output [15:0] A, B;
reg [15:0] data_out;
always @(*) begin
case(readnum)
3'b000: data_out= write? data_out: reg0; //if write= 0 and readnum= 000 data_out = reg0
3'b001: data_out= write? data_out: reg1; //if write= 0 and readnum= 001 data_out = reg1
3'b010: data_out= write? data_out: reg2; //if write= 0 and readnum= 010 data_out = reg2
3'b011: data_out= write? data_out: reg3; //if write= 0 and readnum= 011 data_out = reg3
3'b100: data_out= write? data_out: reg4; //if write= 0 and readnum= 100 data_out = reg4
3'b101: data_out= write? data_out: reg5; //if write= 0 and readnum= 101 data_out = reg5
3'b110: data_out= write? data_out: reg6; //if write= 0 and readnum= 110 data_out = reg6
3'b111: data_out= write? data_out: reg7; //if write= 0 and readnum= 111 data_out = reg7
default: data_out= {width{1'bx}}; //set everything to x for default
endcase
end
//Clock Updates for A and B depending on clock and loada and loadb
DFlipFlopAllow #(width) loadaData(clk, loada, data_out, A);
DFlipFlopAllow #(width) loadbData(clk, loadb, data_out, B);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int N; cin >> N; long long int A[N]; for (long long int i = 0; i < N; i++) cin >> A[i]; map<long long int, long long int> M; for (long long int i = 0; i < N; i++) { if (A[i] != 0) M[A[i]]++; } cout << M.size() << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> adj[100005]; vector<int> vis(100005, 1); vector<int> ans; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T = 1; for (int qq = 1; qq <= T; qq++) { cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } priority_queue<int> v; v.push(-1); vis[1] = 0; while (!v.empty()) { int u = -v.top(); v.pop(); ans.push_back(u); for (auto i : adj[u]) if (vis[i]) v.push(-i), vis[i] = 0; } for (auto i : ans) cout << i << ; cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
|
// Copyright (C) 1991-2014 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// LPM_MULT for Formal Verification ////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// MODEL BEGIN
module lpm_mult (
// INTERFACE BEGIN
dataa, datab, // multiplicand,multiplier
sum, // partial sum
clock, // pipeline clock
clken, // clock enable
aclr, // asynch clear
result // product
);
// INTERFACE END
//// default parameters ////
parameter lpm_type = "lpm_mult";
parameter lpm_widtha = 1;
parameter lpm_widthb = 1;
parameter lpm_widths = 1;
parameter lpm_widthp = 1;
parameter lpm_representation = "UNSIGNED";
parameter lpm_pipeline = 0;
parameter lpm_hint = "UNUSED";
parameter intended_device_family = "UNUSED";
// Local parameters
parameter max_width = ( lpm_widtha >= lpm_widthb ) ? lpm_widtha : lpm_widthb;
`ifdef MULT_NORMALIZE_SIZE
parameter normalized_width = ( max_width <= 9 ) ? 9 :
( ( max_width <= 18 ) ? 18 : max_width );
`else
parameter normalized_width = 1;
`endif
parameter adder_width = (lpm_widths > lpm_widtha + lpm_widthb) ? lpm_widths : lpm_widtha + lpm_widthb,
lpm_in_pipeline = (lpm_pipeline > 0) ? 1 : 0,
lpm_out_pipeline = lpm_pipeline - lpm_in_pipeline;
//// port declarations ////
input clock;
input clken;
input aclr;
input [lpm_widtha-1:0] dataa;
input [lpm_widthb-1:0] datab;
input [lpm_widths-1:0] sum;
output [lpm_widthp-1:0] result;
//// constants ////
//// variables ////
integer i;
//// nets/registers ////
wire sign_a,sign_b,sign_sum;
wire [lpm_widtha + lpm_widthb - 1:0] product;
wire signed [adder_width - 1 : 0] augend;
wire signed [adder_width : 0] add_out;
wire [lpm_widtha-1:0] dataa_piped;
wire [lpm_widthb-1:0] datab_piped;
wire [lpm_widths - 1:0] sum_reg;
wire [adder_width - 1:0] sum_piped;
wire [adder_width - 1:0] multout_piped;
// IMPLEMENTATION BEGIN
//////////////////////////// asynchronous logic ////////////////////////////////////////
assign sign_a = (lpm_representation == "SIGNED");
assign sign_b = (lpm_representation == "SIGNED");
assign sign_sum = (lpm_representation == "SIGNED");
// ************** Multiplier logic *************** //
mult_block #(
.width_a(lpm_widtha),
.width_b(lpm_widthb),
.normalized_width(normalized_width)
) multiply (
.dataa(dataa_piped) ,.datab(datab_piped),
.signa(sign_a),.signb(sign_b),
.product(product)
);
// ************** Adder logic ******************* //
assign augend = (product[lpm_widtha + lpm_widthb - 1] & (sign_a | sign_b))
? {{(adder_width - lpm_widtha - lpm_widthb){1'b1}},product}
: {{(adder_width - lpm_widtha - lpm_widthb){1'b0}},product};
assign sum_piped = (sum_reg[lpm_widths - 1] & sign_sum)
? {{(adder_width - lpm_widths){1'b1}},sum_reg}
: {{(adder_width - lpm_widths){1'b0}},sum_reg};
addsub_block #(adder_width, adder_width) add (
.dataa(multout_piped),.datab(sum_piped),
.signa(sign_a | sign_b) ,.signb(sign_sum),
.addsub(1'b1),
.sum(add_out)
);
// ************** Pipeline logic ************ //
// When lpm_width is larger than adder_width, sign extend the
// result to the larger lpm_width
generate
if (lpm_widthp < adder_width)
assign result = add_out[adder_width - 1:adder_width - lpm_widthp];
else
assign result =
(add_out[adder_width] && (sign_a | sign_b |sign_sum)) ?
{{(lpm_widthp - adder_width){1'b1}},add_out} :
{{(lpm_widthp - adder_width){1'b0}},add_out};
endgenerate
//////////////////////////// synchronous logic ////////////////////////////////////////
pipeline_internal_fv #(lpm_widtha,lpm_in_pipeline) inda_latency (
.clk(clock),
.ena(clken) ,
.clr(aclr),
.d(dataa),
.piped(dataa_piped)
);
pipeline_internal_fv #(lpm_widthb,lpm_in_pipeline) indb_latency (
.clk(clock),
.ena(clken) ,
.clr(aclr),
.d(datab),
.piped(datab_piped)
);
pipeline_internal_fv #(lpm_widths,lpm_pipeline) sum_latency (
.clk(clock),
.ena(clken) ,
.clr(aclr),
.d(sum),
.piped(sum_reg)
);
pipeline_internal_fv #(adder_width,lpm_out_pipeline) mult_latency (
.clk(clock),
.ena(clken) ,
.clr(aclr),
.d(augend),
.piped(multout_piped)
);
// IMPLEMENTATION END
endmodule
// MODEL END
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> using vv = vector<vector<T>>; template <class T> ostream &operator<<(ostream &os, const vector<T> &t) { os << { ; for (int(i) = 0; (i) < (t.size()); ++(i)) { os << t[i] << , ; } os << } << endl; return os; } template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> &t) { return os << ( << t.first << , << t.second << ) ; } template <class T> inline bool MX(T &l, const T &r) { return l < r ? l = r, 1 : 0; } template <class T> inline bool MN(T &l, const T &r) { return l > r ? l = r, 1 : 0; } vector<string> s_p_l_i_t(const string &s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.emplace_back(x); return move(v); } void e_r_r(vector<string>::iterator it) {} template <typename T, typename... Args> void e_r_r(vector<string>::iterator it, T a, Args... args) { if (*it == 1 || *it == 1 ) cerr << endl; else cerr << it->substr((*it)[0] == , it->length()) << = << a << , ; e_r_r(++it, args...); } const long long MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cout << fixed << setprecision(0); int n; cin >> n; cout << YES << endl; int a, b, c, d; for (int(i) = 0; (i) < (n); ++(i)) { cin >> a >> b >> c >> d; cout << abs(a) % 2 * 2 + abs(b) % 2 + 1 << endl; } return 0; }
|
`timescale 1 ps / 1 ps
module alt_mem_ddrx_input_if
#(parameter
CFG_LOCAL_DATA_WIDTH = 64,
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_MEM_IF_CHIP = 1,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL"
)
(
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early,
itf_rd_data_id_early_valid,
// command generator
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
cmd_id,
// write data path
wr_data_mem_full,
write_data_id,
write_data,
byte_en,
write_data_valid,
// read data path
read_data,
read_data_valid,
read_data_error,
read_data_localid,
read_data_begin,
read_data_last,
//side band
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
bg_do_read,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_localid,
rfsh_req,
rfsh_chip,
deep_powerdn_req,
deep_powerdn_chip,
self_rfsh_req,
self_rfsh_chip,
rfsh_ack,
deep_powerdn_ack,
power_down_ack,
self_rfsh_ack,
init_done
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
// command channel
output itf_cmd_ready;
input [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
// read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// command generator
input cmd_gen_full;
output cmd_valid;
output [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
output cmd_write;
output cmd_read;
output cmd_multicast;
output [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
output cmd_priority;
output cmd_autoprecharge;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
// write data path
output [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
output [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
output write_data_valid;
input wr_data_mem_full;
output [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
// read data path
input [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
input read_data_valid;
input read_data_error;
input [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
input read_data_begin;
input read_data_last;
//side band
input local_refresh_req;
input [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
//side band
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output deep_powerdn_req;
output [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output self_rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
input rfsh_ack;
input deep_powerdn_ack;
input power_down_ack;
input self_rfsh_ack;
input init_done;
// command generator
wire cmd_priority;
wire [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
wire cmd_read;
wire cmd_write;
wire cmd_multicast;
wire cmd_gen_full;
wire cmd_valid;
wire itf_cmd_ready;
wire cmd_autoprecharge;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
//side band
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
wire self_rfsh_req;
//wire rfsh_ack;
//wire deep_powerdn_ack;
wire power_down_ack;
//wire self_rfsh_ack;
// wire init_done;
//write data path
wire itf_wr_data_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire write_data_valid;
wire [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
wire [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
//read data path
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
// commmand generator
assign cmd_priority = itf_cmd_priority;
assign cmd_address = itf_cmd_address;
assign cmd_multicast = itf_cmd_multicast;
assign cmd_size = itf_cmd_burstlen;
assign cmd_autoprecharge = itf_cmd_autopercharge;
assign cmd_id = itf_cmd_id;
// side band
assign rfsh_req = local_refresh_req;
assign rfsh_chip = local_refresh_chip;
assign deep_powerdn_req = local_deep_powerdn_req;
assign deep_powerdn_chip = local_deep_powerdn_chip;
assign self_rfsh_req = local_self_rfsh_req;
assign self_rfsh_chip = local_self_rfsh_chip;
assign local_refresh_ack = rfsh_ack;
assign local_deep_powerdn_ack = deep_powerdn_ack;
assign local_power_down_ack = power_down_ack;
assign local_self_rfsh_ack = self_rfsh_ack;
assign local_init_done = init_done;
//write data path
assign write_data = itf_wr_data;
assign byte_en = itf_wr_data_byte_en;
assign write_data_valid = itf_wr_data_valid;
assign write_data_id = itf_wr_data_id;
// read data path
assign itf_rd_data_id = read_data_localid;
assign itf_rd_data_error = read_data_error;
assign itf_rd_data_valid = read_data_valid;
assign itf_rd_data_begin = read_data_begin;
assign itf_rd_data_last = read_data_last;
assign itf_rd_data = read_data;
assign itf_rd_data_id_early = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
//==============================================================================
// Logic below is to tie low itf_cmd_ready, itf_cmd_valid and itf_wr_data_ready when local_init_done is low
assign itf_cmd_ready = ~cmd_gen_full & local_init_done;
assign itf_wr_data_ready = ~wr_data_mem_full & local_init_done;
assign cmd_read = ~itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_write = itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_valid = itf_cmd_valid & local_init_done;
generate
begin : gen_rd_data_id_early_valid
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
end
else
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, mn = INT_MAX, ans = INT_MAX; cin >> n; map<int, int> mp; map<int, int> mp_ans; for (int i = 1; i <= n; i++) { cin >> a; if (mp[a] == 0) mp[a] = i; else { if (a <= mn) { mn = a; if (mp_ans[a] != 0) { ans = min(mp_ans[a], i - mp[a]); mp_ans[a] = ans; } else { mp_ans[a] = i - mp[a]; } } mp[a] = i; } } cout << mp_ans[mn]; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 7; int m, k; long long n, x, s, a[MAX], b[MAX], c[MAX], d[MAX]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k >> x >> s; for (int i = 1; i <= m; ++i) { cin >> a[i]; } for (int i = 1; i <= m; ++i) { cin >> b[i]; } for (int i = 1; i <= k; ++i) { cin >> c[i]; } for (int i = 1; i <= k; ++i) { cin >> d[i]; } long long res = x * n; for (int i = 1; i <= m; ++i) { int l = 1, r = k; while (l <= r) { int mid = (l + r) / 2; if (b[i] + d[mid] <= s) { l = mid + 1; } else { r = mid - 1; } } long long numPrep = c[r]; if (numPrep == n) { res = 0; break; } long long prepTime = x * n; if (b[i] <= s) { prepTime = a[i] * (n - numPrep); } res = min(prepTime, res); } long long mxNumPrep = -1; for (int i = 1; i <= k; ++i) { if (d[i] <= s) { mxNumPrep = max(mxNumPrep, c[i]); } else { break; } } res = min(x * (n - mxNumPrep), res); cout << res << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; char a[maxn][maxn]; int vis[maxn][maxn]; int n, m; inline void go(int x, int y) { if (vis[x][y] == 1) return; if (a[x][y] != # ) return; vis[x][y] = 1; go(x - 1, y); go(x + 1, y); go(x, y - 1); go(x, y + 1); } inline bool check(int x, int y) { a[x][y] = . ; int sum = 0; memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (a[i][j] == # && vis[i][j] == 0) { sum++; go(i, j); } } a[x][y] = # ; return sum > 1; } int main() { cin >> n >> m; int sum = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> a[i][j]; if (a[i][j] == # ) sum++; } if (sum <= 2) { cout << -1 << endl; return 0; } int ans = 2; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] == # ) if (check(i, j)) ans = 1; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> long long a[100005]; long long count[100005]; int vis[100005]; struct Element { long long l, r; Element(long long l, long long r) : l(l), r(r) {} }; Element getCount(long long k, int n) { long long lower = 0, upper = 0; int met = 0; for (int i = 1; i <= n; i++) { long long l = 1, r = a[i]; long long res = 0; while (l <= r) { long long m = (l + r) / 2; long long value = a[i] - 3ll * m * m + 3 * m - 1; if (value >= k) { res = m; l = m + 1; } else r = m - 1; } lower += res, upper += res; count[i] = res; long long value = a[i] - 3ll * res * res + 3 * res - 1; if (value == k) { vis[i] = 1; count[i]--; if (!met) met = 1; else lower--; } else vis[i] = 0; } return Element(lower, upper); } int main() { int n; long long k; scanf( %d%lld , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); long long l = -3e18, r = 1e10; while (l <= r) { long long m = (l + r) / 2; Element u = getCount(m, n); if (u.l > k) l = m + 1; else if (u.r < k) r = m - 1; else { break; } } long long need = k; for (int i = 1; i <= n; i++) need -= count[i]; for (int i = 1; i <= n; i++) { if (need && vis[i]) { need--; count[i]++; } printf( %lld , count[i]); } printf( n ); return 0; }
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//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, k; int n1; vector<long long> v; int c[20]; int a[20]; bool viz[20]; int f[20]; inline void get(int i) { int cif = 0; long long zece = 1; long long r = 0; for (zece = 1; i > 0; i >>= 1, zece *= 10LL) { ++cif; if ((i & 1) != 0) r += 7LL * zece; else r += 4LL * zece; } if (r != 0LL) v.push_back(r); for (++cif; cif < 11; ++cif, zece *= 10LL) { r += 4LL * zece; v.push_back(r); } } void back(int k1) { if (k1 == n1 + 1) return; for (int i = 1; i <= n1; ++i) { if (viz[i]) continue; if (k > f[n1 - k1]) k -= f[n1 - k1]; else { viz[i] = true; a[k1] = i; back(k1 + 1); return; } } printf( -1 n ); exit(0); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < 1024; ++i) { get(i); } sort(v.begin(), v.end()); int start = max(1, n - 12); f[0] = f[1] = 1; for (int i = 2; i < 13; ++i) f[i] = f[i - 1] * i; n1 = n - start + 1; back(1); int rez = 0; long long start1 = (long long)start; for (size_t i = 0, lim = v.size(); i < lim && v[i] < start1; ++i) { ++rez; } int x = start; for (int i = 1; i <= n1; ++i, ++x) { c[i] = x; } for (int i = 1; i <= n1; ++i) { if (find(v.begin(), v.end(), (long long)(i - 1) + start1) != v.end() && find(v.begin(), v.end(), (long long)c[a[i]]) != v.end()) ++rez; } printf( %d n , rez); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k[110], v[110][110], t[110][110], res, s, i, j; int ktra(long long &s1, long long &s2, long long f1, long long f2, int &p) { int res = ((s1 - s2) * (f1 - f2) < 0) || ((s1 == s2) && (p * (f1 - f2) < 0)); if (f1 > f2) p = 1; if (f1 < f2) p = -1; s1 = f1; s2 = f2; return res; } int tinh(int i, int j) { long long s1 = 0, s2 = 0; int i1 = 0, i2 = 0, t1 = t[i][0], t2 = t[j][0], d = 0, tt, p = 0; while (s1 < s && s2 < s) { tt = min(t1, t2); d += ktra(s1, s2, s1 + tt * v[i][i1], s2 + tt * v[j][i2], p); t1 -= tt; t2 -= tt; if (t1 == 0 && i1 < k[i] - 1) t1 = t[i][++i1]; if (t2 == 0 && i2 < k[j] - 1) t2 = t[j][++i2]; } return d; } int main() { cin >> n >> s; for (i = 0; i < n; i++) { cin >> k[i]; for (j = 0; j < k[i]; j++) cin >> v[i][j] >> t[i][j]; } res = 0; for (i = 0; i < n - 1; i++) for (j = i + 1; j < n; j++) res += tinh(i, j); cout << res; }
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#include <bits/stdc++.h> using namespace std; bool bin(unsigned long long a, unsigned long long b) { return a > b; } int main() { int n, k; scanf( %d %d , &n, &k); long inp; queue<long> seg; map<long, long> cnt; set<long> once; for (int y = 0; y < k; y++) { scanf( %ld , &inp); seg.push(inp); cnt[inp]++; if (cnt[inp] == 1) once.insert(inp); else if (cnt[inp] > 1) once.erase(inp); } if (!once.empty()) printf( %ld n , (*once.rbegin())); else puts( Nothing ); for (int y = 0; y < n - k; y++) { if (cnt[seg.front()] == 1) { once.erase(seg.front()); cnt.erase(seg.front()); } else cnt[seg.front()]--; if (cnt[seg.front()] == 1) once.insert(seg.front()); seg.pop(); scanf( %ld , &inp); seg.push(inp); cnt[inp]++; if (cnt[inp] == 1) once.insert(inp); else once.erase(inp); if (!once.empty()) printf( %ld n , (*once.rbegin())); else puts( Nothing ); } }
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// Library - static, Cell - th24, View - schematic
// LAST TIME SAVED: May 23 16:39:19 2014
// NETLIST TIME: May 23 16:39:23 2014
`timescale 1ns / 1ns
module th24 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net61), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N12 ( .d(net41), .g(d), .s(net61), .b(cds_globals.gnd_));
nfet_b N11 ( .d(net50), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N9 ( .d(net50), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N8 ( .d(net41), .g(c), .s(net50), .b(cds_globals.gnd_));
nfet_b N7 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N6 ( .d(net41), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net41), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net41), .g(a), .s(net66), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net66), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
pfet_b P10 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
pfet_b P9 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net62));
pfet_b P8 ( .b(cds_globals.vdd_), .g(d), .s(net62), .d(net63));
pfet_b P7 ( .b(cds_globals.vdd_), .g(y), .s(net63), .d(net41));
pfet_b P6 ( .b(cds_globals.vdd_), .g(d), .s(net36), .d(net64));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net64), .d(net41));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net35), .d(net41));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net65));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(net65), .d(net36));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net36), .d(net35));
pfet_b P0 ( .b(cds_globals.vdd_), .g(d), .s(net35), .d(net41));
inv I11 ( y, net41);
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> void print(T a) { for (auto x : a) cout << x << ; cout << n ; } vector<pair<long double, long double> > lines1; vector<long double> dots1; long double intersection(pair<long double, long double> l1, pair<long double, long double> l2) { return (l2.second - l1.second) / (l1.first - l2.first); } void add_mx(long double k, long double b) { while ((long long)(lines1).size() >= 2) { long double x = intersection(lines1[(long long)(lines1).size() - 2], {k, b}); if (x <= dots1.back()) { dots1.pop_back(); lines1.pop_back(); } else break; } if ((long long)(lines1).size()) dots1.push_back( intersection(lines1[(long long)(lines1).size() - 1], {k, b})); lines1.push_back({k, b}); } long double get_mx(long double x) { long long id = lower_bound((dots1).begin(), (dots1).end(), x) - dots1.begin(); return lines1[id].first * x + lines1[id].second; } vector<pair<long double, long double> > lines2; vector<long double> dots2; void add_mn(long double k, long double b) { while ((long long)(lines2).size() >= 2) { long double x = intersection(lines2[(long long)(lines2).size() - 2], {k, b}); if (x <= dots2.back()) { dots2.pop_back(); lines2.pop_back(); } else break; } if ((long long)(lines2).size()) dots2.push_back( intersection(lines2[(long long)(lines2).size() - 1], {k, b})); lines2.push_back({k, b}); } long double get_mn(long double x) { long long id = lower_bound((dots2).begin(), (dots2).end(), x) - dots2.begin(); return lines2[id].first * x + lines2[id].second; } const long double PI = acos(-1); long double get_angle(pair<long double, long double> v) { long double gyp = sqrt(v.first * v.first + v.second * v.second); long double cs = v.first / gyp; return acos(cs) * 180.0 / PI; } void solve() { long long n; cin >> n; vector<vector<long double> > s; vector<pair<long double, long double> > lines; long double left_most = 1e18, right_most = -1e18; for (long long i = 0; i < n; i++) { long double a, b, c; cin >> a >> b >> c; left_most = min(left_most, a); right_most = max(right_most, b); s.push_back({c, a, b}); lines.push_back({c, a}); lines.push_back({c, b}); } sort((lines).begin(), (lines).end()); vector<pair<long double, long double> > lines_mx, lines_mn; for (long long i = 0; i < (long long)(lines).size(); i++) { if (i != 0 && lines[i].first == lines[i - 1].first) { lines_mx.pop_back(); lines_mx.push_back(lines[i]); } else { lines_mx.push_back(lines[i]); lines_mn.push_back(lines[i]); } } for (long long i = 0; i < (long long)(lines_mx).size(); i++) add_mx(lines_mx[i].first, lines_mx[i].second); for (long long i = (long long)(lines_mn).size() - 1; i >= 0; i--) add_mn(lines_mn[i].first, lines_mn[i].second); sort((s).begin(), (s).end()); vector<pair<long double, long long> > event; for (long long i = 0; i < n; i++) { for (long long j = 0; j < i; j++) { if (s[j][0] == s[i][0]) continue; pair<long double, long double> v1(s[j][2] - s[i][1], s[j][0] - s[i][0]); pair<long double, long double> v2(s[j][1] - s[i][2], s[j][0] - s[i][0]); long double angle1 = get_angle(v1), angle2 = get_angle(v2); event.push_back({angle1, 1}); event.push_back({angle2, -1}); } } sort((event).begin(), (event).end()); if ((long long)(event).size() == 0) { cout << fixed << setprecision(10) << right_most - left_most; return; } long long balance = 0; vector<long double> angles; for (long long i = 0; i < (long long)(event).size(); i++) { if (event[i].second == 1) { if (balance == 0) angles.push_back(event[i].first); balance++; } else { balance--; if (balance == 0) angles.push_back(event[i].first); } } long double ans = 1e18; for (long double angle : angles) { long double ct = 1.L / tan(angle / 180.0 * PI); ans = min(ans, get_mx(ct) - get_mn(ct)); } cout << fixed << setprecision(10) << ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; for (long long i = 0; i < t; i++) { solve(); } return 0; }
|
module tb_memories
(
input wire clk_i,
input wire reset_i,
input wire [15:0] xpm_addr_i,
output reg [31:0] xpm_data_o,
input wire [15:0] xdm0_addr_i,
input wire [15:0] xdm0_data_i,
input wire xdm0_wr_en_i,
output reg [15:0] xdm0_data_o,
input wire [15:0] xdm1_addr_i,
input wire [15:0] xdm1_data_i,
input wire xdm1_wr_en_i,
output reg [15:0] xdm1_data_o
);
integer file;
integer count;
reg [0:79*8-1] line;
integer finished;
integer writeprogrammem;
integer programmemoffset;
integer dm0offset;
integer lineno;
integer i;
reg [31:0] val;
reg [31:0] xpm_data;
// The memories
reg [31:0] program_mem [0:65535];
reg [15:0] data_mem0 [0:65535];
reg [15:0] data_mem1 [0:65535];
reg [15:0] xdm0_addr_ff;
reg [15:0] xdm1_addr_ff;
reg [15:0] xpm_addr_ff;
always@(posedge clk_i) begin
if(!reset_i) begin
xpm_addr_ff <= 0;
end
else begin
xdm0_addr_ff <= xdm0_addr_i;
xdm1_addr_ff <= xdm1_addr_i;
xpm_addr_ff <= xpm_addr_i;
end
end
always @* begin
// if(reset_i == 1'b1)
xpm_data = program_mem[xpm_addr_ff];
/* -----\/----- EXCLUDED -----\/-----
else
xpm_data_o <= {32{1'bx}};
-----/\----- EXCLUDED -----/\----- */
end
always @(posedge clk_i) begin
// if(reset_i == 1'b1)
xpm_data_o <= xpm_data;
/* -----\/----- EXCLUDED -----\/-----
else
xpm_data_o <= {32{1'bx}};
-----/\----- EXCLUDED -----/\----- */
end
always @(posedge clk_i) begin
if(xdm0_wr_en_i) begin
data_mem0[xdm0_addr_i] <= xdm0_data_i;
end
end
always @(posedge clk_i) begin
xdm0_data_o=data_mem0[xdm0_addr_ff];
end
always @(posedge clk_i) begin
if(xdm1_wr_en_i) begin
data_mem1[xdm1_addr_i] <= xdm1_data_i;
end
end
always @(posedge clk_i) begin
xdm1_data_o=data_mem1[xdm1_addr_ff];
end
initial begin
file = $fopen("test.hex","r");
finished = 0;
writeprogrammem = 0;
programmemoffset = 0;
dm0offset = 0;
lineno = 0;
for(i=0; i < 65536;i = i + 1) begin
program_mem[i] = 32'h0;
data_mem0[i] = 16'h0;
data_mem1[i] = 16'h0;
end
while(!finished) begin
lineno = lineno+1;
count = $fgets(line,file);
if(count == 0) begin
finished = 1;
end else begin
line = line << (79 - count) * 8;
if(line[0:7] == ";") begin
// skip comments
end else if(line[0:4*8-1] == "code") begin
writeprogrammem = 1;
end else if(line[0:4*8-1] == "rom0") begin
writeprogrammem = 0;
end else if(line[0:9*8-1] == "org 32768") begin
dm0offset = 16'd32768;
end else if($sscanf(line,"%08x",val) == 1) begin
if(writeprogrammem) begin
program_mem[programmemoffset] = val;
programmemoffset = programmemoffset + 1;
end else begin
data_mem0[dm0offset] = val[15:0];
dm0offset = dm0offset + 1;
end
end else begin
$display("%m: Error at line %d, could not understand \"%s\"",lineno,line);
$stop;
end
end // else: !if(count == 0)
end // while (!finished)
end // initial begin
endmodule // test
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const long long llinf = (long long)3e18; const int N = (int)1e5 + 111; const long double PI = (long double)acos(-1); int main() { int n, cur, num, ans = 0; scanf( %d , &n); vector<int> a(n); vector<char> us(n, 0); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a.begin(), a.end()); for (int i = 0; i < n; i++) if (us[i] == 0) { cur = i; num = 0; while (cur < n) { if (us[cur] == 1 || a[cur] < num) cur++; else { num++; us[cur] = 1; } } ans++; } printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, nn; cin >> n; nn = n * 2; vector<int> arr(nn); for (int i = 0; i < nn; ++i) cin >> arr[i]; sort(arr.begin(), arr.end()); long long ans, now; ans = arr[nn - 1] - arr[n]; ans *= arr[n - 1] - arr[0]; for (int i = 1; i < n; ++i) { now = arr[n - 1 + i] - arr[i]; now *= arr[nn - 1] - arr[0]; ans = min(ans, now); } cout << ans; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_di_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q,
clear);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
parameter NUM_WORDS = 16;
input clock;
input [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH-1:0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
input clear;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
// synthesis translate_off
reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] mem [0:NUM_WORDS-1];
integer i;
/*
integer j;
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
for (j = 0; j < DATA_WIDTH/32; j = j+ 1) begin
mem[i][32*j+:32] <= i*(DATA_WIDTH/32) + j;
end
end
end
else begin
q <= mem[rdaddress];
end
end
*/
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
mem[i] <= 0;
end
end
else begin
if (wren)
mem[wraddress] <= data;
q <= mem[rdaddress];
end
end
// synthesis translate_on
// synthesis read_comments_as_HDL on
// wire [DATA_WIDTH-1:0] sub_wire0;
// wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
//
// altsyncram altsyncram_component (
// .address_a (wraddress),
// .clock0 (clock),
// .data_a (data),
// .wren_a (wren),
// .address_b (rdaddress),
// .q_b (sub_wire0),
// .aclr0 (1'b0),
// .aclr1 (1'b0),
// .addressstall_a (1'b0),
// .addressstall_b (1'b0),
// .byteena_a (1'b1),
// .byteena_b (1'b1),
// .clock1 (1'b1),
// .clocken0 (1'b1),
// .clocken1 (1'b1),
// .clocken2 (1'b1),
// .clocken3 (1'b1),
// .data_b ({DATA_WIDTH{1'b1}}),
// .eccstatus (),
// .q_a (),
// .rden_a (1'b1),
// .rden_b ((rdaddress < NUM_WORDS) ? 1'b1 : 1'b0),
// .wren_b (1'b0));
// defparam
// altsyncram_component.address_aclr_b = "NONE",
// altsyncram_component.address_reg_b = "CLOCK0",
// altsyncram_component.clock_enable_input_a = "BYPASS",
// altsyncram_component.clock_enable_input_b = "BYPASS",
// altsyncram_component.clock_enable_output_b = "BYPASS",
// altsyncram_component.intended_device_family = "Stratix III",
// altsyncram_component.lpm_type = "altsyncram",
// altsyncram_component.numwords_a = NUM_WORDS,
// altsyncram_component.numwords_b = NUM_WORDS,
// altsyncram_component.operation_mode = "DUAL_PORT",
// altsyncram_component.outdata_aclr_b = "NONE",
// altsyncram_component.outdata_reg_b = "UNREGISTERED",
// altsyncram_component.power_up_uninitialized = "FALSE",
// altsyncram_component.ram_block_type = "MLAB",
// altsyncram_component.widthad_a = ADDR_WIDTH,
// altsyncram_component.widthad_b = ADDR_WIDTH,
// altsyncram_component.width_a = DATA_WIDTH,
// altsyncram_component.width_b = DATA_WIDTH,
// altsyncram_component.width_byteena_a = 1;
// synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_2_V
`define SKY130_FD_SC_HD__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_2_V
|
#include <bits/stdc++.h> using namespace std; int n, m, INF = 2e9; vector<vector<int>> value; void shift_column(int j, int k) { vector<int> res(n); for (int i = 0; i < n; i++) res[(i - k + n) % n] = value[i][j]; for (int i = 0; i < n; i++) value[i][j] = res[i]; } void run() { cin >> n >> m; value.resize(n, vector<int>(m)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> value[i][j]; } } int ans = 0; for (int j = 0; j < m; j++) { map<int, int> pos; vector<int> cnt(n); for (int i = 0; i < n; i++) pos[1 + j + i * m] = i; for (int i = 0; i < n; i++) { if (pos.find(value[i][j]) == pos.end()) continue; int shift = (i - pos[value[i][j]] + n) % n; cnt[shift]++; } auto best_shift = distance(cnt.begin(), max_element(cnt.begin(), cnt.end())); shift_column(j, best_shift); int best_add = INF; for (int i = 0; i < n; i++) best_add = min(best_add, n - cnt[i] + i); ans += best_add; } cout << ans; } signed main() { cout.setf(ios::fixed); cout.precision(10); cin.tie(0); cout.tie(0); ios::sync_with_stdio(0); run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, k, l, m, n, cnt = 0, ans = 0; char a[8][8]; for (i = 0; i < 8; i++) for (j = 0; j < 8; j++) cin >> a[i][j]; for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { if (a[i][j] == B ) cnt++; } if (cnt == 8) ans++; cnt = 0; } for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { if (a[j][i] == B ) cnt++; } if (cnt == 8) ans++; cnt = 0; } if (ans == 16) ans = 8; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, r1, r2, t1, t2, f1 = 1, f2 = 1, col[100010]; vector<vector<int>> graph; bool dfs(const int &v, const int &from, const int &color) { if (col[v] != color) return 0; for (auto &i : graph[v]) if (i != from) if (!dfs(i, v, color)) return 0; return 1; } int main() { scanf( %d , &n); graph.resize(n + 1); for (int i = 1; i < n; ++i) { scanf( %d%d , &r1, &r2); graph[r1].push_back(r2); graph[r2].push_back(r1); } for (int i = 1; i <= n; ++i) scanf( %d , &col[i]); for (int i = 1; i <= n; ++i) for (auto &j : graph[i]) if (col[i] != col[j]) { t1 = i; t2 = j; break; } if (!t1) { printf( YES n1 ); return 0; } for (auto &i : graph[t1]) f1 &= dfs(i, t1, col[i]); for (auto &i : graph[t2]) f2 &= dfs(i, t2, col[i]); if (f1) printf( YES n%d , t1); else if (f2) printf( YES n%d , t2); else printf( NO ); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) { if (i % 4 == 2) { if (j == m) { cout << # ; } else { cout << . ; } } else if (i % 4 == 0) { if (j == 1) { cout << # ; } else { cout << . ; } } else { cout << # ; } } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T& a, const T& b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T& a, const T& b) { if (b < a) { a = b; return 1; } return 0; } template <typename T> class Grid { struct Pos { int i, j; Pos(int i, int j) : i(i), j(j) {} }; int H, W; vector<vector<T>> G; vector<int> di8 = {1, 1, 0, -1, -1, -1, 0, 1}, dj8 = {0, 1, 1, 1, 0, -1, -1, -1}; vector<int> di4 = {1, 0, -1, 0}, dj4 = {0, 1, 0, -1}; vector<Pos> neighbor(int i, int j, const vector<int>& dis, const vector<int>& djs) const { vector<Pos> res; for (int k = 0; k < dis.size(); ++k) { if (in(i + dis[k], j + djs[k])) res.emplace_back(i + dis[k], j + djs[k]); } return res; } public: static bool in(int H, int W, int i, int j) { return 0 <= i && i < H && 0 <= j && j < W; } Grid(int H, int W) : H(H), W(W) { G.resize(H, vector<T>(W)); } Grid(int H, int W, T zero) : H(H), W(W) { G.resize(H, vector<T>(W, zero)); } vector<T>& operator[](int i) { return G[i]; } bool in(int i, int j) const { return (0 <= i && i < H && 0 <= j && j < W); } vector<Pos> neighbor8(int i, int j) const { return neighbor(i, j, di8, dj8); } vector<Pos> neighbor4(int i, int j) const { return neighbor(i, j, di4, dj4); } int to1DIndex(int i, int j) { return i * W + j; } Pos to2DIndex(int i) { return Pos(i / W, i % W); } void scanFrom(istream& strm) { for (int i = 0; i < (int)(H); ++i) for (int j = 0; j < (int)(W); ++j) strm >> G[i][j]; } void outputTo(ostream& strm) { for (int i = 0; i < (int)(H); ++i) { for (int j = 0; j < (int)(W); ++j) cout << G[i][j]; strm << endl; } } }; template <typename T> inline istream& operator>>(istream& strm, Grid<T>& g) { g.scanFrom(strm); return strm; } template <typename T> inline ostream& operator<<(ostream& strm, Grid<T>& g) { g.outputTo(strm); return strm; } int n; int X[1010][1010], Y[1010][1010]; char ans[1010][1010]; bool in(int i, int j) { return 0 <= i && i < n && 0 <= j && j < n; } int di[4] = {1, 0, -1, 0}; int dj[4] = {0, 1, 0, -1}; int main() { cin >> n; for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(n); ++j) { ans[i][j] = ? ; scanf( %d %d , &X[i][j], &Y[i][j]); if (X[i][j] != -1) --X[i][j]; if (Y[i][j] != -1) --Y[i][j]; } unordered_map<int, unordered_map<int, char>> dir; dir[1][0] = D ; dir[-1][0] = U ; dir[0][1] = R ; dir[0][-1] = L ; function<void(int, int, int, int)> sink = [&](int i, int j, int x, int y) { for (int k = 0; k < (int)(4); ++k) { int ni = i + di[k], nj = j + dj[k]; if (!in(ni, nj)) continue; if (ans[ni][nj] != ? ) continue; if (X[ni][nj] != x || Y[ni][nj] != y) continue; ans[ni][nj] = dir[i - ni][j - nj]; sink(ni, nj, x, y); } }; for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(n); ++j) { if (ans[i][j] != ? ) continue; if (X[i][j] == -1) { for (int k = 0; k < (int)(4); ++k) { int ni = i + di[k], nj = j + dj[k]; if (!in(ni, nj)) continue; if (X[ni][nj] != -1) continue; ans[i][j] = dir[ni - i][nj - j]; ans[ni][nj] = dir[i - ni][j - nj]; sink(i, j, -1, -1); sink(ni, nj, -1, -1); } } else { if (ans[X[i][j]][Y[i][j]] != ? ) break; if (X[X[i][j]][Y[i][j]] != X[i][j] || Y[X[i][j]][Y[i][j]] != Y[i][j]) break; ans[X[i][j]][Y[i][j]] = X ; sink(X[i][j], Y[i][j], X[i][j], Y[i][j]); } } for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(n); ++j) { if (ans[i][j] == ? ) { cout << INVALID << endl; return 0; } } cout << VALID << endl; for (int i = 0; i < (int)(n); ++i) { for (int j = 0; j < (int)(n); ++j) cout << ans[i][j]; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = 3.141592653589793238463; int x[1009], y[1009], t[1009]; double p[1009]; double dp[1009][1009]; int n; double sol(int i, int prev) { if (i == n) return 0; if (dp[i][prev] == dp[i][prev]) return dp[i][prev]; bool can = true; if (prev == n) can = true; else { int dt = t[i] - t[prev]; int dx = abs(x[i] - x[prev]); int dy = abs(y[i] - y[prev]); can = (dt >= hypot(dx, dy)); } if (!can) return dp[i][prev] = sol(i + 1, prev); return dp[i][prev] = max(sol(i + 1, prev), p[i] + sol(i + 1, i)); } struct target { int x, y, t; double p; bool operator<(const target &other) const { return t < other.t; } }; int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> n; vector<target> v; for (int i = 0; i < (n); i++) { int x, y, t; cin >> x >> y >> t; double p; cin >> p; v.push_back({x, y, t, p}); } sort(v.begin(), v.end()); for (int i = 0; i < (n); i++) x[i] = v[i].x, y[i] = v[i].y, t[i] = v[i].t, p[i] = v[i].p; memset((dp), (-1), sizeof(dp)); printf( %.10f n , sol(0, n)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxx = 2e5 + 10; char s[maxx], t[maxx]; int l[maxx], r[maxx]; int main() { cin >> s >> t; int m = strlen(s); int n = strlen(t); int a = 0, b = 0; for (int i = 0; i < m; i++) { if (s[i] == t[a]) { l[a] = i; a++; } if (a == n) break; } for (int i = m - 1; i >= 0; i--) { if (s[i] == t[n - b - 1]) { r[b] = i; b++; } if (b == n) break; } int ans = max(r[n - 1], m - l[n - 1] - 1); for (int i = 0; i < n; i++) ans = max(ans, r[i] - l[n - i - 2] - 1); cout << ans << endl; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charSent (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// test_simulation_mux_16_test.v
module f1_test(input [15:0] in, input [3:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
endcase
endmodule
// test_simulation_mux_2_test.v
module f2_test(input [1:0] in, input select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
// test_simulation_mux_32_test.v
module f3_test(input [31:0] in, input [4:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
endcase
endmodule
// test_simulation_mux_4_test.v
module f4_test(input [3:0] in, input [1:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
// test_simulation_mux_64_test.v
module f5_test(input [63:0] in, input [5:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
32: out = in[32];
33: out = in[33];
34: out = in[34];
35: out = in[35];
36: out = in[36];
37: out = in[37];
38: out = in[38];
39: out = in[39];
40: out = in[40];
41: out = in[41];
42: out = in[42];
43: out = in[43];
44: out = in[44];
45: out = in[45];
46: out = in[46];
47: out = in[47];
48: out = in[48];
49: out = in[49];
50: out = in[50];
51: out = in[51];
52: out = in[52];
53: out = in[53];
54: out = in[54];
55: out = in[55];
56: out = in[56];
57: out = in[57];
58: out = in[58];
59: out = in[59];
60: out = in[60];
61: out = in[61];
62: out = in[62];
63: out = in[63];
endcase
endmodule
// test_simulation_mux_8_test.v
module f6_test(input [7:0] in, input [2:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Data { int64_t value; int64_t supports; int64_t supportedBy; }; bool isTop(map<pair<int64_t, int64_t>, Data> const& cubes, pair<int64_t, int64_t> const& pos) { bool top = true; for (int64_t i = -1; i <= 1; ++i) { map<pair<int64_t, int64_t>, Data>::const_iterator f = cubes.find(pair<int64_t, int64_t>{pos.first + i, pos.second + 1}); if (f != cubes.end()) { if (f->second.supportedBy <= 1) { top = false; break; } } } return top; } int main(int, char**) { ios_base::sync_with_stdio(false); cin.tie(NULL); int64_t n; cin >> n; map<pair<int64_t, int64_t>, Data> cubes; for (int64_t i = 0; i < n; ++i) { int64_t x, y; cin >> x >> y; cubes.insert(make_pair(pair<int64_t, int64_t>{x, y}, Data{i, 0, 0})); } for (auto& p : cubes) { Data& data = p.second; pair<int64_t, int64_t> const& pos = p.first; if (cubes.find(pair<int64_t, int64_t>{pos.first - 1, pos.second - 1}) != cubes.end()) data.supportedBy += 1; if (cubes.find(pair<int64_t, int64_t>{pos.first, pos.second - 1}) != cubes.end()) data.supportedBy += 1; if (cubes.find(pair<int64_t, int64_t>{pos.first + 1, pos.second - 1}) != cubes.end()) data.supportedBy += 1; if (cubes.find(pair<int64_t, int64_t>{pos.first - 1, pos.second + 1}) != cubes.end()) data.supports += 1; if (cubes.find(pair<int64_t, int64_t>{pos.first, pos.second + 1}) != cubes.end()) data.supports += 1; if (cubes.find(pair<int64_t, int64_t>{pos.first + 1, pos.second + 1}) != cubes.end()) data.supports += 1; } set<pair<int64_t, pair<int64_t, int64_t> > > tops; for (auto const& p : cubes) { int64_t value = p.second.value; pair<int64_t, int64_t> const& pos = p.first; if (isTop(cubes, pos)) tops.insert(pair<int64_t, pair<int64_t, int64_t> >{value, pos}); } int64_t result = 0; bool smallest = false; while (!tops.empty()) { set<pair<int64_t, pair<int64_t, int64_t> > >::iterator used; if (smallest) used = tops.begin(); else used = --tops.end(); smallest = !smallest; result *= n; result += used->first; result %= 1000000009l; pair<int64_t, int64_t> pos = used->second; cubes.erase(pos); tops.erase(used); set<pair<int64_t, pair<int64_t, int64_t> > > update; for (int64_t i = -1; i <= 1; ++i) { { pair<int64_t, int64_t> pm1{pos.first + i, pos.second - 1}; map<pair<int64_t, int64_t>, Data>::iterator fm1 = cubes.find(pm1); if (fm1 != cubes.end()) { fm1->second.supports -= 1; update.insert( pair<int64_t, pair<int64_t, int64_t> >{fm1->second.value, pm1}); } } { pair<int64_t, int64_t> pp1{pos.first + i, pos.second + 1}; map<pair<int64_t, int64_t>, Data>::iterator fp1 = cubes.find(pp1); if (fp1 != cubes.end()) { fp1->second.supportedBy -= 1; update.insert( pair<int64_t, pair<int64_t, int64_t> >{fp1->second.value, pp1}); if (fp1->second.supportedBy <= 1) { for (int64_t j = -1; j <= 1; ++j) { pair<int64_t, int64_t> sibP{pp1.first + j, pos.second}; map<pair<int64_t, int64_t>, Data>::iterator sibI = cubes.find(sibP); if (sibI != cubes.end()) { tops.erase(pair<int64_t, pair<int64_t, int64_t> >{ sibI->second.value, sibP}); } } } } } } for (auto const& updatePos : update) { if (isTop(cubes, updatePos.second)) tops.insert(updatePos); } } cout << result << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/30/2015 11:43:21 AM
// Design Name:
// Module Name: quadrature_encoder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////s
module quadrature_encoder_tb();
reg clk;
reg reset;
reg a;
reg b;
wire dir;
wire [31:0] count;
quadrature_encoder uut(.clk(clk),.reset(reset),.a(a),.b(b),.dir(dir),.count(count));
initial
begin
clk=1'b1;
reset = 1'b0;
a=1'b0;
b=1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//backward
#8 b = 1'b1;
#8 a = 1'b1;
#8 b = 1'b0;
#8 a = 1'b0;
//backward
#8 b = 1'b1;
#8 a = 1'b1;
#8 b = 1'b0;
#8 a = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
#1 reset = 1'b1;
#2 reset = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
//backward
#8 b = 1'b1;
#8 a = 1'b1;
#8 b = 1'b0;
#8 a = 1'b0;
//backward
#8 b = 1'b1;
#8 a = 1'b1;
#8 b = 1'b0;
#8 a = 1'b0;
//forward
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
end
always #1 clk = ~clk;
/*forward
always
begin
#8 a = 1'b1;
#8 b = 1'b1;
#8 a = 1'b0;
#8 b = 1'b0;
end
*/
/* backward
always
begin
#8 b = 1'b1;
#8 a = 1'b1;
#8 b = 1'b0;
#8 a = 1'b0;
end
*/
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) const int mod = 1e9 + 7; using ll = int64_t; using namespace std; template <int MOD_> struct modnum { static constexpr int MOD = MOD_; static_assert(MOD_ > 0, MOD must be positive ); int v; private: using ll = long long; static int minv(int a, int m) { a %= m; assert(a); return a == 1 ? 1 : int(m - ll(minv(m, a)) * ll(m) / a); } public: modnum() : v(0) {} modnum(ll v_) : v(int(v_ % MOD)) { if (v < 0) v += MOD; } explicit operator int() const { return v; } friend std::ostream& operator<<(std::ostream& out, const modnum& n) { return out << int(n); } friend std::istream& operator>>(std::istream& in, modnum& n) { ll v_; in >> v_; n = modnum(v_); return in; } friend bool operator==(const modnum& a, const modnum& b) { return a.v == b.v; } friend bool operator!=(const modnum& a, const modnum& b) { return a.v != b.v; } modnum inv() const { modnum res; res.v = minv(v, MOD); return res; } friend modnum inv(const modnum& m) { return m.inv(); } modnum neg() const { modnum res; res.v = v ? MOD - v : 0; return res; } friend modnum neg(const modnum& m) { return m.neg(); } modnum operator-() const { return neg(); } modnum operator+() const { return modnum(*this); } modnum& operator++() { v++; if (v == MOD) v = 0; return *this; } modnum& operator--() { if (v == 0) v = MOD; v--; return *this; } modnum& operator+=(const modnum& o) { v += o.v; if (v >= MOD) v -= MOD; return *this; } modnum& operator-=(const modnum& o) { v -= o.v; if (v < 0) v += MOD; return *this; } modnum& operator*=(const modnum& o) { v = int(ll(v) * ll(o.v) % MOD); return *this; } modnum& operator/=(const modnum& o) { return *this *= o.inv(); } friend modnum operator++(modnum& a, int) { modnum r = a; ++a; return r; } friend modnum operator--(modnum& a, int) { modnum r = a; --a; return r; } friend modnum operator+(const modnum& a, const modnum& b) { return modnum(a) += b; } friend modnum operator-(const modnum& a, const modnum& b) { return modnum(a) -= b; } friend modnum operator*(const modnum& a, const modnum& b) { return modnum(a) *= b; } friend modnum operator/(const modnum& a, const modnum& b) { return modnum(a) /= b; } }; using mi = modnum<mod>; void solve() { int n, m; cin >> n; vector<vector<int>> adj(n); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; adj[a].push_back(b); adj[b].push_back(a); } cin >> m; vector<mi> fac(m); for (int i = 0; i < m; i++) { cin >> fac[i]; } auto comp = [&](mi X, mi Y) -> bool { return X.v < Y.v; }; sort(fac.begin(), fac.end(), comp); if (int(fac.size()) < n - 1) { reverse(fac.begin(), fac.end()); while (int(fac.size()) < n - 1) { if (int(fac.size()) < n - 1) { fac.push_back(mi(1)); } } reverse(fac.begin(), fac.end()); } if (int(fac.size()) > n - 1) { mi cur = 1; while (int(fac.size()) >= n - 1) { cur *= fac.back(); fac.pop_back(); } fac.push_back(cur); } vector<ll> sz(n, 0), num; function<void(int, int)> dfs = [&](int node, int par) -> void { sz[node] = 1; for (auto i : adj[node]) { if (i != par) { dfs(i, node); sz[node] += sz[i]; num.push_back((ll)sz[i] * (n - sz[i])); } } }; mi answer = 0; dfs(0, 0); sort(num.begin(), num.end()); assert(int(num.size()) >= n - 1); assert(int(fac.size()) == n - 1); for (int i = 0; i < n - 1; i++) { mi cur = (fac[i] * num[i]); answer += cur; } cout << answer << n ; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int t(1); cin >> t; while (t--) { solve(); } }
|
// iverilog -y .. -o tb-DataFifoBypass.vvp tb-DataFifoBypass.v
// vvp tb-DataFifoBypass.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata_vld;
reg odata_rdy;
wire [W-1:0] odata;
DataFifoBypass#(W,3) dut(clk, rst, idata_vld, idata_rdy, idata, odata_vld, odata_rdy, odata);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h23456789;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy
reg [31:0] rngseed, rnum;
integer n;
#0;
odata_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-DataFifoBypass.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (odata_vld & odata_rdy) begin
rnum = $random(rngseed);
if (odata !== rnum[W-1:0]) begin
$display("%0t: Error: odata %h != %h", $time, odata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata);
end
@(posedge clk);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long tree[100002] = {0}; long long findcf(long long ind) { long long sum = 0; while (ind > 0) { sum += tree[ind]; ind -= (ind & (-ind)); } return sum; } void update(long long ind, long long val) { while (ind <= 100000) { tree[ind] += val; ind += (ind & (-ind)); } } void incFreqFromTo(long long a, long long b, long long delta) { update(a, delta); update(b + 1, -delta); } long long getFreqAt(long long index) { return findcf(index); } int main() { ios::sync_with_stdio(false); long long t, i, j, n, m, x; cin >> n >> m; for (i = 1; i <= n; ++i) { cin >> t; incFreqFromTo(i, i, t); } for (i = 0; i < m; ++i) { cin >> t; if (t == 1) { cin >> j >> x; incFreqFromTo(j, j, x - getFreqAt(j)); } else if (t == 2) { cin >> x; incFreqFromTo(1, n, x); } else { cin >> j; cout << getFreqAt(j) << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { bool w, l; int a[26]; node() { w = false; l = false; memset(a, -1, sizeof a); } }; node a[100030]; long long cnt; char second[100010]; void insert(long long n) { int curr = 0; int i = 0; while (curr < n) { if (a[i].a[second[curr] - a ] == -1) { a[i].a[second[curr] - a ] = ++cnt; } i = a[i].a[second[curr] - a ]; curr++; } } void dfs(long long curr) { if (curr == -1) { return; } int cnt = 0; for (int i = 0; i < 26; i++) { if (a[curr].a[i] != -1) { cnt++; dfs(a[curr].a[i]); if (a[a[curr].a[i]].w == false) { a[curr].w = true; } if (a[a[curr].a[i]].l == false) { a[curr].l = true; } } } if (cnt == 0) { a[curr].w = false; a[curr].l = true; } } int main() { long long n, k; cnt = 0; cin >> n >> k; for (int i = 0; i < n; i++) { scanf( %s , second); insert(strlen(second)); } dfs(0); if (a[0].w == true && a[0].l == true) { cout << First << endl; } else if (a[0].w == false) { cout << Second << endl; } else if (a[0].w == true && a[0].l == false) { if (k % 2 == 1) { cout << First << endl; } else { cout << Second << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int dx[8] = {1, -1, 0, 0, -1, -1, 1, 1}; int dy[8] = {0, 0, -1, 1, -1, 1, -1, 1}; vector<int> adj[300010], val(300010, 1), vis(300010, 0), dis1(300010, 0), dis2(300010, 0); int myrandom(int i) { return std::rand() % i; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, t; long double p; cin >> n >> p >> t; long double dp[t + 2][n + 2]; memset(dp, 0, sizeof(dp)); dp[0][0] = 1; for (int i = 0; i <= t; i++) { for (int j = 0; j <= n; j++) { if (j < n) { dp[i + 1][j + 1] += dp[i][j] * p; dp[i + 1][j] += dp[i][j] * (1 - p); } else { dp[i + 1][j] += dp[i][j]; } } } long double ans = 0; for (int i = 1; i <= n; i++) { ans = ans + i * (dp[t][i]); } cout << fixed << setprecision(20) << ans << n ; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Reset for DCI State Machine
// /___/ /\ Filename : DCIRESET.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DCIRESET (LOCKED, RST);
output LOCKED;
input RST;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
time sample_rising, sample_falling;
always @(RST)
begin
if (RST)
sample_rising = $time;
else if (!RST)
sample_falling = $time;
if (sample_falling - sample_rising < 100000)
$display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
if (sample_rising - sample_falling < 100000)
$display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
end // always @ (RST)
assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1;
`ifdef XIL_TIMING
specify
(RST => LOCKED) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 10; const long long INF = 4e18 + 10; const int maxn = 1 * 1e5 + 5; const int maxe = maxn; int a[maxn]; int p[maxn]; int n, m; bool check(long long t) { for (int i = 1; i <= n; ++i) p[i] = a[i]; int j = n; for (int i = 0; i < m; ++i) { while (j > 0 && p[j] == 0) --j; if (j == 0) return true; long long res = t - j; if (res <= 0) return false; while (j > 0 && res >= p[j]) res -= p[j--]; if (j > 0) p[j] -= res; } if (j == 0) return true; return false; } int MAIN() { scanf( %d%d , &n, &m); long long lb = -1, rb = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); rb += i + a[i]; } while (rb - lb > 1) { long long mid = lb + (rb - lb) / 2; if (check(mid)) rb = mid; else lb = mid; } printf( %I64d n , rb); return 0; } int main() { ios_base::sync_with_stdio(false); cout << fixed << setprecision(16); int ret = MAIN(); return ret; }
|
#include <iostream> #include <vector> #include <algorithm> #include <math.h> using namespace std; #define fi first #define se second #define all(x) x.begin(), x.end() #define sz(x) x.size() #define pb push_back #define mk make_pair #define tests int t; cin >> t; while(t--) #define forn(i, a, b) for (int i = a; i < b; i++) typedef long long ll; typedef long double ld; const int Z = (int)1e5 + 123; const int inf = (int)2e9 + 123; const ll llinf = (ll)9e18 + 123; int main() { tests { int n; cin >> n; ll a = 0, b = n % 10; bool flag = false; while ((b * 2021) + (a * 2020) <= n) { if ((n - (b * 2021)) % 2020 > 0) { b += 10; continue; } else { flag = true; break; } } cout << (flag ? YES n : NO n ); } return 0; }
|
/*
# fsm_app.v - Finite state machine to send out an example test, and process inputs
#
# Description: Finite state machine to exercise the JTAG UART.
# Note that this ignores the full/empty signals, so don't fill the buffer!
#
# Copyright (C) 2014 Binary Logic (nhi.phan.logic at gmail.com).
#
# This file is part of the Virtual JTAG UART toolkit
#
# Virtual UART is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
*/
//=======================================================
// Application to put characters in the output stream and echo input
//=======================================================
`include "system_include.v"
module fsm_app(
input clk_i,
input nreset_i
);
// FSM States
parameter S_INIT = 0, S_STROBE = 1, S_CNT = 2, S_WAIT = 3, S_READ = 4, S_SETTLE = 5, S_WRITE = 6;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [2:0] state;
reg [7:0] data_out;
reg wr, rd;
wire [7:0] data_in;
wire txmt, txfl, rxmt, rxfl;
//=======================================================
// Outputs
//=======================================================
//=======================================================
// Structural coding
//=======================================================
// JTag Interface
jtag_uart uart(
.clk_i( clk_i ),
.nreset_i(nreset_i),
.nwr_i(wr),
.data_i(data_out),
.rd_i(rd),
.data_o(data_in),
.txmt(txmt),
.txfl(txfl),
.rxmt(rxmt),
.rxfl(rxfl)
);
//=======================================================
// Procedural coding
//=======================================================
always @(posedge clk_i)
begin
if( !nreset_i )
begin
state = S_INIT;
wr = 1'b1;
rd = 1'b0;
end else begin
case( state )
S_INIT :
begin
data_out = 65;
wr = 1'b1;
rd = 1'b0;
state = S_STROBE;
end
S_STROBE:
begin
wr = 1'b0;
state = S_CNT;
end
S_CNT:
begin
wr = 1'b1;
data_out = data_out + 1'b1;
if( data_out <= 90 )
state = S_STROBE;
else
state = S_WAIT;
end
S_WAIT :
if( !rxmt )
begin
rd = 1'b1;
state = S_READ;
end
else begin
wr = 1'b1;
rd = 1'b0;
state = S_WAIT;
end
S_READ :
begin
rd = 1'b0;
data_out = data_in;
state = S_SETTLE;
end
S_SETTLE :
begin
wr = 1'b0;
state = S_WRITE;
end
S_WRITE :
begin
wr = 1'b1;
state = S_WAIT;
end
default:
state = S_INIT;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_4_V
`define SKY130_FD_SC_HD__A311OI_4_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_4_V
|
// Lab 6
// Created by David Tran
// Last Modified 02-13-2014
// extras
`timescale 1 ms /1 us
`include "mult_2_2_4.v"
// Testbench Module
module four_bit_multiplier_tb (A0, A1, B0, B1);
output A0, A1, B0, B1;
reg A0, A1, B0, B1;
wire C0, C1, C2, C3;
reg t_A0 [5000:0];
reg t_A1 [5000:0];
reg t_B0 [5000:0];
reg t_B1 [5000:0];
reg t_clock;
reg [31:0] vectornum; //Values from 0 -> 2^31
integer fp;
mult_2_2_4 I1 (A0, A1, B0, B1, C0, C1, C2, C3);
initial begin
t_clock=0;
forever #5 t_clock=~t_clock;
end
initial begin
$readmemb("./bit_str_a_0.txt",t_A0);
$readmemb("./bit_str_a_1.txt",t_A1);
$readmemb("./bit_str_b_0.txt",t_B0);
$readmemb("./bit_str_b_1.txt",t_B1);
vectornum=0; // Set test vector 0
end
always @(posedge t_clock)
begin
A0<=t_A0[vectornum];
A1<=t_A1[vectornum];
B0<=t_B0[vectornum];
B1<=t_B1[vectornum];
vectornum<=vectornum+1;
end
initial
begin
fp=$fopen("mult_2_2_4.out");
$fmonitor(fp, "time=%0d", $time,, "A=%b%b B=%b%b | C=%b%b%b%b", A1, A0, B1, B0, C3, C2, C1, C0);
$monitor("time=%0d", $time,, "A=%b%b B=%b%b | C=%b%b%b%b", A1, A0, B1, B0, C3, C2, C1, C0);
//$dumpfile("two_bit_multipler.vcd");
//$dumpvars;
#1000
$fclose(fp);
$finish;
end
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 50; using namespace std; int n, m, h, tot, mx, maxn, ans; int a[N], b[N], cnt[N], num[N]; int read() { int s = 0, t = 1; char c; while (c < 0 || c > 9 ) { if (c == - ) t = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { s = s * 10 + c - 0 ; c = getchar(); } return s * t; } long long readl() { long long s = 0, t = 1; char c; while (c < 0 || c > 9 ) { if (c == - ) t = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { s = s * 10 + c - 0 ; c = getchar(); } return s * t; } int main() { n = read(); m = read(); for (int i = 1; i <= m; i++) a[i] = read(), b[a[i]]++, mx = max(mx, a[i]); for (int i = 1; i <= mx; i++) if (b[i] > 0) cnt[++tot] = b[i]; for (int i = 1; i <= m; i++) { h = 0; for (int j = 1; j <= tot; j++) h += cnt[j] / i; if (h >= n) ans = i; else break; } printf( %d , ans); return 0; }
|
/**
* $Id: red_pitaya_dfilt1.v -01-24 12:58:17Z matej.oblak $
*
* @brief Red Pitaya equalization filter.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Filter to equalize input analog chain.
*
*/
module red_pitaya_dfilt1
(
// ADC
input adc_clk_i , //!< ADC clock
input adc_rstn_i , //!< ADC reset - active low
input [ 14-1: 0] adc_dat_i , //!< ADC data
output [ 14-1: 0] adc_dat_o , //!< ADC data
// configuration
input [ 18-1: 0] cfg_aa_i , //!< config AA coefficient
input [ 25-1: 0] cfg_bb_i , //!< config BB coefficient
input [ 25-1: 0] cfg_kk_i , //!< config KK coefficient
input [ 25-1: 0] cfg_pp_i //!< config PP coefficient
);
//---------------------------------------------------------------------------------
// register configuration - timing improvements
reg [ 18-1: 0] cfg_aa_r ;
reg [ 25-1: 0] cfg_bb_r ;
reg [ 25-1: 0] cfg_kk_r ;
reg [ 25-1: 0] cfg_pp_r ;
always @(posedge adc_clk_i) begin
cfg_aa_r <= cfg_aa_i ;
cfg_bb_r <= cfg_bb_i ;
cfg_kk_r <= cfg_kk_i ;
cfg_pp_r <= cfg_pp_i ;
end
//---------------------------------------------------------------------------------
// FIR
wire [ 39-1: 0] bb_mult ;
wire [ 33-1: 0] r2_sum ;
reg [ 33-1: 0] r1_reg ;
reg [ 23-1: 0] r2_reg ;
reg [ 32-1: 0] r01_reg ;
reg [ 28-1: 0] r02_reg ;
assign bb_mult = $signed(adc_dat_i) * $signed(cfg_bb_r);
assign r2_sum = $signed(r01_reg) + $signed(r1_reg);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r1_reg <= 33'h0 ;
r2_reg <= 23'h0 ;
r01_reg <= 32'h0 ;
r02_reg <= 28'h0 ;
end
else begin
r1_reg <= $signed(r02_reg) - $signed(r01_reg) ;
r2_reg <= r2_sum[33-1:10];
r01_reg <= {adc_dat_i,18'h0};
r02_reg <= bb_mult[39-2:10];
end
end
//---------------------------------------------------------------------------------
// IIR 1
wire [ 41-1: 0] aa_mult ;
wire [ 49-1: 0] r3_sum ; //24 + 25
(* use_dsp48="yes" *)
reg [ 23-1: 0] r3_reg ;
assign aa_mult = $signed(r3_reg) * $signed(cfg_aa_r);
assign r3_sum = $signed({r2_reg,25'h0}) + $signed({r3_reg,25'h0}) - $signed(aa_mult[41-1:0]);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r3_reg <= 23'h0 ;
end
else begin
r3_reg <= r3_sum[49-2:25] ;
end
end
//---------------------------------------------------------------------------------
// IIR 2
wire [ 40-1: 0] pp_mult ;
wire [ 16-1: 0] r4_sum ;
reg [ 15-1: 0] r4_reg ;
reg [ 15-1: 0] r3_shr ;
assign pp_mult = $signed(r4_reg) * $signed(cfg_pp_r);
assign r4_sum = $signed(r3_shr) + $signed(pp_mult[40-2:16]);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r3_shr <= 15'h0 ;
r4_reg <= 15'h0 ;
end
else begin
r3_shr <= r3_reg[23-1:8] ;
r4_reg <= r4_sum[16-2:0] ;
end
end
//---------------------------------------------------------------------------------
// Scaling
wire [ 40-1: 0] kk_mult ;
reg [ 15-1: 0] r4_reg_r ;
reg [ 15-1: 0] r4_reg_rr ;
reg [ 14-1: 0] r5_reg ;
assign kk_mult = $signed(r4_reg_rr) * $signed(cfg_kk_r);
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
r4_reg_r <= 15'h0 ;
r4_reg_rr <= 15'h0 ;
r5_reg <= 14'h0 ;
end
else begin
r4_reg_r <= r4_reg ;
r4_reg_rr <= r4_reg_r ;
if ($signed(kk_mult[40-2:24]) > $signed(14'h1FFF))
r5_reg <= 14'h1FFF ;
else if ($signed(kk_mult[40-2:24]) < $signed(14'h2000))
r5_reg <= 14'h2000 ;
else
r5_reg <= kk_mult[24+14-1:24];
end
end
assign adc_dat_o = r5_reg ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mN = 222222; int n; int a[mN], outa[mN], outb[mN], ge[mN]; vector<int> ans; struct Bit { int c[mN]; void clear() { memset(c, 0, sizeof(c)); } int lob(int x) { return x & (-x); } void add(int x, int dt) { while (x <= n) { c[x] += dt; x += lob(x); } } int sum(int x) { int re = 0; while (x > 0) { re += c[x]; x -= lob(x); } return re; } } bit; void calc(int o[]) { for (int i = 1; i <= n; i++) { cin >> a[i]; } bit.clear(); for (int i = n; i >= 1; i--) { o[i] = bit.sum(a[i] + 1); bit.add(a[i] + 1, 1); } } int bins(int key) { int l = 1, r = n; key++; while (l < r) { int mid = (l + r) / 2; if ((mid)-bit.sum(mid) >= key) r = mid; else l = mid + 1; } return l - 1; } void out(int o[]) { bit.clear(); for (int i = 1; i <= n; i++) { int x = bins(o[i]); ans.push_back(x); bit.add(x + 1, 1); } } int main() { cin >> n; calc(outa); calc(outb); for (int i = n - 1; i >= 1; i--) { ge[i] += outa[i] + outb[i]; int mod = (n + 1) - i; if (ge[i] >= mod) { ge[i - 1] += ge[i] / mod; ge[i] %= mod; } } out(ge); for (int i = 0, n_ = (ans.size()); i < n_; i++) cout << ans[i] << ((i == ans.size() - 1) ? n : ); }
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011-2012, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
//
// Ken Chapman - Xilinx Ltd.
//
// 30th April 2012 - Conversion from original VHDL version (30th April 2012).
// 30th July 2014 - Corrections to comment only.
//
// This reference design provides a simple UART communication example.
// Please see 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' for more detailed
// descriptions.
//
// The code in this example is set to implement a 115200 baud rate when using a 50MHz
// clock. Whilst the design is presented as a working example for the XC6VLX240T-1FF1156
// device on the ML605 Evaluation Board (www.xilinx.com) it is a simple reference design
// that is easily adapted or incorporated into a design for use with any hardware platform.
//
//
//////////////////////////////////////////////////////////////////////////////////////////-
//
//
module uart6_ml605 ( input uart_rx,
input clk200_p,
input clk200_n,
output uart_tx );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to create 50MHz clock from 200MHz differential clock
//
wire clk200;
wire clk;
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [4:0] baud_count;
reg en_16_x_baud;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Create 50MHz clock from 200MHz differential clock
/////////////////////////////////////////////////////////////////////////////////////////
IBUFGDS diff_clk_buffer(
.I(clk200_p),
.IB(clk200_n),
.O(clk200));
// BUFR used to divide by 4 and create a regional clock
BUFR #(
.BUFR_DIVIDE("4"),
.SIM_DEVICE("VIRTEX6"))
clock_divide (
.I(clk200),
.O(clk),
.CE(1'b1),
.CLR(1'b0));
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter.
//
kcpsm6 #(
.interrupt_vector (12'h7F0),
.scratch_pad_memory_size(64),
.hwbuild (8'h42)) // 42 hex is ASCII Character "B"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset connected to JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl;
// Unused signals tied off until required.
assign kcpsm6_sleep = 1'b0;
assign interrupt = interrupt_ack;
// Development Program Memory
// JTAG Loader enabled for rapid code development.
uart_control #(
.C_FAMILY ("V6"),
.C_RAM_SIZE_KWORDS (2),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 27.13 cycles at 50MHz. In this implementation
// a pulse is generated every 27 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 5'b11010) begin // counts 27 states including zero
baud_count <= 5'b00000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 5'b00001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the transmitter and receiver. The second is used to read the data from the
// receiver and generate the 'buffer_read' pulse.
//
always @ (posedge clk)
begin
case (port_id[0])
// Read UART status at port address 00 hex
1'b0 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
1'b1 : in_port <= uart_rx_data_out;
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[0] == 1'b1)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there is only one output port and that it involves writing
// directly to the FIFO buffer within 'uart_tx6'. As such the only requirements are to
// connect the 'out_port' to the transmitter macro and generate the write pulse.
//
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
// END OF FILE uart6_ml605.v
///////////////////////////////////////////////////////////////////////////////////////////
//
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_SYMBOL_V
`define SKY130_FD_SC_LP__DLRBP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; int main() { int a1, a2, b1, b2, c1, c2; while (scanf( %d%d%d%d%d%d , &a1, &b1, &c1, &a2, &b2, &c2) != EOF) { if (a1 == 0 && b1 == 0 && c1 != 0) { printf( 0 n ); continue; } if (a2 == 0 && b2 == 0 && c2 != 0) { printf( 0 n ); continue; } if ((a1 == 0 && b1 == 0 && c1 == 0) || (a2 == 0 && b2 == 0 && c2 == 0)) { printf( -1 n ); continue; } if (a1 == 0 && a2 == 0) { if (c1 * b2 == c2 * b1) { printf( -1 n ); } else { printf( 0 n ); } continue; } if (b1 == 0 && b2 == 0) { if (c1 * a2 == c2 * a1) { printf( -1 n ); } else { printf( 0 n ); } continue; } if (a1 == 0 && b1 != 0) { printf( 1 n ); continue; } if (a1 != 0 && b1 == 0) { printf( 1 n ); continue; } if (a2 == 0 && b2 != 0) { printf( 1 n ); continue; } if (a2 != 0 && b2 == 0) { printf( 1 n ); continue; } if (a1 * b2 == a2 * b1) { if (fabs(c1 * 1.0 / b1 - c2 * 1.0 / b2) < 1e-8) { printf( -1 n ); } else { printf( 0 n ); } } else { printf( 1 n ); } } return 0; }
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#include <bits/stdc++.h> using namespace std; mt19937 rng((int)chrono::steady_clock::now().time_since_epoch().count()); char mat[105][105]; void solve() { int n, m, horizontal; cin >> n >> m >> horizontal; int vertical = n * m / 2 - horizontal; int oxe = 0, nte = 0; char cc = e ; if (n % 2 != m % 2) { if (n % 2 == 0) { for (int i = 0; i < n; i += 2) { mat[i][m - 1] = mat[i + 1][m - 1] = cc++; if (cc > z ) cc = e ; } vertical -= n / 2; m--; nte = 1; } else { for (int j = 0; j < m; j += 2) { mat[n - 1][j] = mat[n - 1][j + 1] = cc++; if (cc > z ) cc = e ; } horizontal -= m / 2; n--; oxe = 1; } } assert(n % 2 == 0 && m % 2 == 0); int puth = n * m / 2; int putv = 0; char mofio[] = { a , b }; int cur = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j += 2) { mat[i][j] = mat[i][j + 1] = mofio[cur]; cur ^= 1; } if (m % 4 == 0) cur ^= 1; } mofio[0] = c , mofio[1] = d ; cur = 0; for (int i = 0; i < n; i += 2) { for (int j = 0; j < m; j += 2) { if (puth == horizontal && putv == vertical) { cout << YES n ; for (int ii = 0; ii < n + oxe; ii++) { for (int jj = 0; jj < m + nte; jj++) { cout << mat[ii][jj]; } cout << n ; } return; } mat[i][j] = mat[i + 1][j] = mofio[cur]; mat[i][j + 1] = mat[i + 1][j + 1] = mofio[cur ^ 1]; puth -= 2; putv += 2; } cur ^= 1; } if (puth == horizontal && putv == vertical) { cout << YES n ; for (int ii = 0; ii < n + oxe; ii++) { for (int jj = 0; jj < m + nte; jj++) { cout << mat[ii][jj]; } cout << n ; } return; } cout << NO n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; long long segs[] = {6, 2, 5, 5, 4, 5, 6, 3, 7, 6}; int n, m, k; long long a[200005]; vector<pair<int, int> > q; int res[200005]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { int r, t; cin >> r >> t; if (q.empty()) { q.push_back(make_pair(r, t - 1)); } else { while (!q.empty() && t - 1 >= q.back().second) { q.pop_back(); } q.push_back(make_pair(r, t - 1)); } } q.push_back(make_pair(1, 0)); int l = 0, r = n - 1, ind = n - 1; for (int i = 0; i < q.size(); i++) { if (i == q.size() - 1) { res[ind] = a[l]; break; } if (!i) { while (r > q[0].second) { res[r] = a[r]; r--; ind--; } sort(a, a + r + 1); } if (q[i].first == 1) { while (ind > q[i + 1].second) { res[ind] = a[r]; ind--; r--; } } else { while (ind > q[i + 1].second) { res[ind] = a[l]; ind--; l++; } } } for (int i = 0; i < n; i++) { if (i) cout << ; cout << res[i]; } cout << endl; return 0; }
|
`timescale 1ns / 1ps
module Processor(clk,Reset,inst,pss,wa,imme,dat, a, b,sb,add,val,rr);
input clk, Reset;
output [31:0] inst;
output [31:0] pss;
output [4:0] wa;
output [31:0] imme;
output [31:0] dat;
output [31:0] a,b;
output sb;
output [4:0] add;
output [31:0]val,rr;
reg [0:0] newClock;
reg [5:0] move_cont;
always @ (posedge clk) begin
move_cont = move_cont + 1'b1;
newClock = move_cont[2];
end
wire [31:0] pcsignal;
wire [31:0] pc;
wire [4:0]opcode;
wire [4:0] rs,rt,rd;
wire [31:0] instruction;
wire [16:0] imm;
wire [31:0] jaddr;
wire [31:0] newpc;
wire [4:0] opcode1;
wire [4:0] rs1,rt1,rd1;
wire [16:0] imm1;
wire [31:0] jaddr1;
wire [0:0] enable1,enable2,enable3,enable4;
wire [0:0] bselector;
wire [1:0] regselector;
wire [0:0] pcselect;
wire [0:0] memrd,memwd,regwrite;
wire [4:0] muxout1;
wire [4:0] muxout2;
wire [31:0] rdata1,rdata2;
wire [0:0] bselector1;
wire [31:0] rvalue11,rvalue21;
wire [4:0] rd2;
wire [0:0] memrd1,memwd1,regwrite1;
wire [4:0] opcode2;
wire [31:0] immvalue1;
wire [31:0] immvalue2;
wire [31:0] alumuxout;
wire [0:0] zero;
wire [31:0] aluout;
wire [0:0] memrd2,memwd2,regwrite2;
wire [31:0] datain;
wire [31:0] memoryaddress;
wire [4:0] writeaddress;
wire [31:0] dataout;
wire [31:0] writedata;
wire [0:0] regwrite3;
wire [4:0] writeaddress1;
MuxData pcselectmux(
.Output(pcsignal),
.Input0(newpc),
.Input1(immvalue2),
.Selector(pcselect)
);
SimpleReg pcreg(
.clk(clk),
.Reset(Reset),
.DataIn(pcsignal),
.DataOut(pc)
);
InstructionMem insmem(
.Pc(pc),
.clk(clk),
.OpCode(opcode),
.RS(rs),
.RT(rt),
.RD(rd),
.IMM(imm),
.JADDR(jaddr),
.UsableInstruc(instruction),
.NEWPC(newpc)
);
assign inst=instruction;
assign pss=pcselect;
IF_ID ifid(.clk(clk),
.Reset(Reset),
.Enable(enable1),
.Rd(rd),
.Rs(rs),
.Rt(rt),
.Imm(imm),
.Jaddr(jaddr),
.Opcode(opcode),
.Pc(pc),
.RD(rd1),
.RS(rs1),
.RT(rt1),
.IMM(imm1),
.JADDR(jaddr1),
.OPCODE(opcode1),
.PC()
);
assign wa=rd1;
SignExt signext(.SEin(imm1),.SEout(immvalue1));
ControlUnit ctrlunit(
.clk(clk),
.OPCODE(opcode1),
.BOpCode(opcode2),
.Zero(zero),
.BSelector(bselector),
.MemRD(memrd),
.MemWD(memwd),
.RegWrite(regwrite),
.RegSelector(regselector),
.PCSelect(pcselect),
.Enable1(enable1),
.Enable2(enable2),
.Enable3(enable3),
.Enable4(enable4)
);
MuxReg reg1(.Output(muxout1), .Input0(rs1), .Input1(rd1), .Input2(rs1),.Selector(regselector));
MuxReg reg2(.Output(muxout2), .Input0(rt1), .Input1(rs1), .Input2(rd1),.Selector(regselector));
wire [31:0] r;
//7wire[6:0] seven1;
//sevenSeg ss(.R(r),.Seg(seven1));
//assign seven = seven1;
RegisterBanc regbank(
.ReadData1(rdata1),
.ReadData2(rdata2),
.WriteData(writedata),
.ReadAddr1(muxout1),
.ReadAddr2(muxout2),
.WriteAddr(writeaddress1),
.RegWrite(regwrite3),
.clk(clk),
.ro(r)
);
assign rr=r;
ID_Ex idex(
.clk(clk),
.Reset(Reset),
.Enable(enable2),
.Opcode(opcode1),
.BSelector(bselector),
.Rd(rd1),
.RValue1(rdata1),
.RValue2(rdata2),
.ImmValue(immvalue1),
.MemRD(memrd),
.memWD(memwd),
.RegWrite(regwrite),
.OPCODE(opcode2),
.BSELECTOR(bselector1),
.RD(rd2),
.RVALUE1(rvalue11),
.RVALUE2(rvalue21),
.IMMVALUE(immvalue2),
.MEMWD(memwd1),
.MEMRD(memrd1),
.REGWRITE(regwrite1)
);
assign imme=immvalue2;
MuxData alumuxB(.Output(alumuxout), .Input0(rvalue21),.Input1(immvalue2),.Selector(bselector1));
ALU alu(.A(rvalue11), .B(alumuxout), .ALUOp(opcode2) ,
.ALUOut(aluout), .Zero(zero));
assign sb=bselector1;
assign a=rvalue11;
assign b=alumuxout;
assign dat=aluout;
EX_MEM exmen(
.clk(clk),
.Reset(Reset),
.Enable(enable3),
.MemoryAddress(aluout),
.WriteAddress(rd2),
.DataIn(rvalue21),
.MemRD(memrd1),
.MemWD(memwd1),
.RegWrite(regwrite1),
.MEMORYADDRESS(memoryaddress),
.WRITEADDRESS(writeaddress),
.DATAIN(datain),
.MEMRD(memrd2),
.MEMWD(memwd2),
.REGWRITE(regwrite2)
);
DataMemory datamen(
.clk(clk),
.Reset(Reset),
.MemoryAddress(memoryaddress),
.memWD(memwd2),
.memRD(memrd2),
.DataOut(dataout),
.DataIn(datain)
);
MEM_WB menwb(
.clk(clk),
.Reset(Reset),
.Enable(enable4),
.RegWrite(regwrite2),
.WriteAddress(writeaddress),
.WriteData(dataout),
.REGWRITE(regwrite3),
.WRITEADDRESS(writeaddress1),
.WRITEDATA(writedata)
);
assign add=writeaddress1;
assign val=writedata;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int A1, B1, C1, A2, B2, C2; cin >> A1 >> B1 >> C1 >> A2 >> B2 >> C2; if (A1 * B2 != A2 * B1) cout << 1 << endl; else { if (A1 != 0 && A2 != 0 && A2 * C1 == A1 * C2) cout << -1 << endl; else if (A1 != 0 && A2 != 0) cout << 0 << endl; else if ((A1 == 0 && A2 != 0) || (A1 != 0 && A2 == 0)) { if (B1 != 0 && B2 != 0) cout << 1 << endl; else if (B1 == 0 && C1 != 0 || B2 == 0 && C2 != 0) cout << 0 << endl; else cout << -1 << endl; } else if (A1 == 0 && A2 == 0) { if (((B1 == 0 && C1 == 0) && (B2 == 0 && C2 == 0)) || ((B1 != 0 || B2 != 0) && B1 * C2 == B2 * C1)) cout << -1 << endl; else cout << 0 << endl; } } }
|
/*
* Copyright (c) 2014, Olof Kindgren <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_ram_tb;
localparam MEMORY_SIZE = 1024;
vlog_tb_utils vlog_tb_utils0();
reg wbm_rst = 1'b1;
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
initial #1800 wbm_rst <= 1'b0;
initial #200 wb_rst <= 1'b0;
always #100 wb_clk <= !wb_clk;
wire [31:0] wb_adr;
wire [31:0] wb_dat;
wire [3:0] wb_sel;
wire wb_we;
wire wb_cyc;
wire wb_stb;
wire [2:0] wb_cti;
wire [1:0] wb_bte;
wire [31:0] wb_rdt;
wire wb_ack;
wb_bfm_transactor
#(.MEM_HIGH (MEMORY_SIZE-1),
.VERBOSE (0))
master
(.wb_clk_i (wb_clk),
.wb_rst_i (wbm_rst),
.wb_adr_o (wb_adr),
.wb_dat_o (wb_dat),
.wb_sel_o (wb_sel),
.wb_we_o (wb_we),
.wb_cyc_o (wb_cyc),
.wb_stb_o (wb_stb),
.wb_cti_o (wb_cti),
.wb_bte_o (wb_bte),
.wb_dat_i (wb_rdt),
.wb_ack_i (wb_ack),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done(done));
always @(done) begin
if(done === 1) begin
$display("All tests passed!");
$finish;
end
end
wb_ram
#(.depth (MEMORY_SIZE))
dut
(// Wishbone interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_adr[$clog2(MEMORY_SIZE)-1:0]),
.wb_stb_i (wb_stb),
.wb_cyc_i (wb_cyc),
.wb_cti_i (wb_cti),
.wb_bte_i (wb_bte),
.wb_we_i (wb_we) ,
.wb_sel_i (wb_sel),
.wb_dat_i (wb_dat),
.wb_dat_o (wb_rdt),
.wb_ack_o (wb_ack),
.wb_err_o ());
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int i, j, temp, d = 0; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { if (a[i] > a[j]) { temp = a[j]; a[j] = a[i]; a[i] = temp; } } } int t = a[n / 2]; for (i = 0; i < n; i++) { if (a[i] == t) { d++; } } if (n % 2 == 0) { if (d > n / 2) { cout << NO ; } else cout << YES ; } else { if (d > (n + 1) / 2) { cout << NO ; } else cout << YES ; } return 0; }
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module shl8(
input [7 : 0] a,
input [2 : 0] shift,
output [7 : 0] res,
output carry);
assign {carry, res} = (shift == 3'b000) ? {1'b0, a} :
(shift == 3'b001) ? {a[7 : 0], {1'b0}}:
(shift == 3'b010) ? {a[6 : 0], {2'b0}}:
(shift == 3'b011) ? {a[5 : 0], {3'b0}}:
(shift == 3'b100) ? {a[4 : 0], {4'b0}}:
(shift == 3'b101) ? {a[3 : 0], {5'b0}}:
(shift == 3'b110) ? {a[2 : 0], {6'b0}}:
{a[1 : 0], {7'b0}};
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:34:57 03/28/2014
// Design Name: shift
// Module Name: D:/XilinxProject/CPU/shift_test.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: shift
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shift_test;
// Inputs
reg [31:0] d;
reg [4:0] sa;
reg right;
reg arith;
// Outputs
wire [31:0] sh;
// Instantiate the Unit Under Test (UUT)
shift uut (
.d(d),
.sa(sa),
.right(right),
.arith(arith),
.sh(sh)
);
initial begin
// Initialize Inputs
d = 0;
sa = 0;
right = 0;
arith = 0;
// Wait 100 ns for global reset to finish
#100;
d = 4;
sa = 2;
right = 1;
arith = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, m; string a, s; int main() { cin >> a >> s; m = s.size(); sort(s.begin(), s.end()); for (m--; i < a.size(); i++) { if (a[i] < s[m]) a[i] = s[m--]; } cout << a; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int t = n % 4; int a = 0; for (int i = 0; i < 4; i++) { if ((i * 7) % 4 == t) a = i; } int b = -1, c; for (int j = (n - a) / 4 * 4 + a; j >= a; j -= 4) { if ((n - 7 * j) % 4 == 0 && (n - 7 * j >= 0)) { c = j; b = (n - 7 * j) / 4; break; } } if (b == -1) { cout << -1; return 0; } for (int i = 0; i < b; i++) cout << 4; for (int i = 0; i < c; i++) cout << 7; return 0; }
|
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