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// psi2c_control
`timescale 1 ps / 1 ps
/*
-- registers b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
-- 0 w: tbm go
-- 0 r: ful tbm run
-- 1 w: send raw S P D7 D6 D5 D4 !D4 D3 D2 D1 D0 !D0
-- 2 w: send D7 D6 D5 D4 D3 D2 D1 D0
-- 3 w: send S D7 D6 D5 D4 D3 D2 D1 D0
-- 4 w: send P D7 D6 D5 D4 D3 D2 D1 D0
-- 5 w: send SP D7 D6 D5 D4 D3 D2 D1 D0
-- 1 r: rdb raw run to 0 _s3 _rw _d4 _d0 S ha4 ha3 ha2 ha1 ha0 pa2 pa1 pa0
-- ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0
--
-- tbm = read back on
-- ful = fifo full
-- go = start transmission
-- run = i2c running
-- S = Start Bit, P = Stop Bit
-- D = Send Data
-- ha = Hub Address
-- pa = Port Address
-- ra = Register Address
-- rd = Register Data
*/
module i2c_control
(
// avalon slave
input clk,
input reset,
// avalon slave interface
input [2:0]address,
input write,
input [31:0]writedata,
input read,
output reg [31:0]readdata,
output reg go,
input full,
output reg [11:0]memd,
output memw,
input busy,
output tbm,
input [31:0]rda
);
wire [9:0]i2c_data;
reg rdbff;
assign memw = write & (address>=1) & (address<=5);
assign i2c_data = {writedata[7:4], !writedata[4],
writedata[3:0], !writedata[0]};
always @(*)
case (address)
3'd2: memd <= {2'b00, i2c_data};
3'd3: memd <= {2'b10, i2c_data}; // S
3'd4: memd <= {2'b01, i2c_data}; // P
3'd5: memd <= {2'b11, i2c_data}; // SP
default: memd <= writedata[11:0];
endcase
always @(*)
case (address)
3'd1: readdata <= rda;
default readdata <= {28'h1234_567, 1'b0, full, rdbff, busy || rda[31]};
endcase
// tbm mode
always @(posedge clk or posedge reset)
begin
if (reset)
begin
rdbff <= 0;
go <= 0;
end
else if (write && (address == 3'd0))
begin
rdbff <= writedata[1];
go <= writedata[0];
end
else go <= 0;
end
assign tbm = rdbff;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const int nax = 1e3 + 20; const int mod = 1e9 + 7; int fact[nax]; int binpow(int a, int e) { int ans = 1; while (e > 1) { if (e & 1) { ans = (1LL * ans * a) % mod; --e; } a = (1LL * a * a) % mod; e >>= 1; } ans = (1LL * ans * a) % mod; return ans; } int C(int n, int k) { if (k > n) return 0; return (1LL * fact[n] * (1LL * binpow(fact[n - k], mod - 2) * binpow(fact[k], mod - 2) % mod)) % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << setprecision(20) << fixed; fact[0] = 1; for (int i = 1; i <= (int)nax - 1; ++i) { fact[i] = (1LL * fact[i - 1] * i) % mod; } int n, m, k; cin >> n >> m >> k; cout << (1LL * C(n - 1, 2 * k) * C(m - 1, 2 * k)) % mod << n ; }
|
#include <bits/stdc++.h> using namespace std; int a[200003], b[200003], ch[200003]; void Do() { int n, f = 0; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n - 1; i++) { if (a[i] == 0) f = 1; if (f) a[i] = a[i + 1]; } f = 0; for (int i = 0; i < n - 1; i++) { if (b[i] == 0) f = 1; if (f) b[i] = b[i + 1]; } int beg = a[0], desire; ch[0] = a[0]; for (int i = 0; i < n - 1; i++) if (b[i] == beg) desire = i; int ind = 1; for (int i = desire + 1; i < n - 1; i++) { ch[ind++] = b[i]; if (ind == n - 1) break; } if (ind != n - 1) { for (int i = 0;; i++) { ch[ind++] = b[i]; if (ind == n - 1) break; } } bool flag = true; for (int i = 0; i < n - 1; i++) if (a[i] != ch[i]) flag = false; if (flag) cout << YES << endl; else cout << NO << endl; } int main() { Do(); return 0; }
|
module erx_fifo (/*AUTOARG*/
// Outputs
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
// Inputs
sys_clk, rx_lclk_div4, erx_nreset, rxwr_wait, rxrd_wait, rxrr_wait,
rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter TARGET = "GENERIC";
//reset & clocks
input sys_clk;
input rx_lclk_div4;
input erx_nreset; //keep in reset longer
//WR to AXI master
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//RD to AXI master
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//RR to AXI slave
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//RD from IO
input rxrd_fifo_access; // To rxrd_fifo of fifo_cdc.v
input [PW-1:0] rxrd_fifo_packet; // To rxrd_fifo of fifo_cdc.v
output rxrd_fifo_wait; // From rxrd_fifo of fifo_cdc.v
//RR from IO
input rxrr_fifo_access; // To rxrr_fifo of fifo_cdc.v
input [PW-1:0] rxrr_fifo_packet; // To rxrr_fifo of fifo_cdc.v
output rxrr_fifo_wait; // From rxrr_fifo of fifo_cdc.v
//WR from IO
input rxwr_fifo_access; // To rxwr_fifo of fifo_cdc.v
input [PW-1:0] rxwr_fifo_packet; // To rxwr_fifo of fifo_cdc.v
output rxwr_fifo_wait; // From rxwr_fifo of fifo_cdc.v
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/*(for AXI 1. read request, 2. write, and 3. read response) */
/************************************************************/
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.packet_out (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
.access_out (@"(substring vl-cell-name 0 4)"_access),
.wait_out (@"(substring vl-cell-name 0 4)"_fifo_wait),
// Inputs
.clk_out (sys_clk),
.clk_in (rx_lclk_div4),
.access_in (@"(substring vl-cell-name 0 4)"_fifo_access),
.wait_in (@"(substring vl-cell-name 0 4)"_wait),
.nreset (erx_nreset),
.packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
);
*/
//Read request fifo (from Epiphany)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
rxrd_fifo (
/*AUTOINST*/
// Outputs
.wait_out (rxrd_fifo_wait), // Templated
.access_out (rxrd_access), // Templated
.packet_out (rxrd_packet[PW-1:0]), // Templated
// Inputs
.nreset (erx_nreset), // Templated
.clk_in (rx_lclk_div4), // Templated
.access_in (rxrd_fifo_access), // Templated
.packet_in (rxrd_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.wait_in (rxrd_wait)); // Templated
//Write fifo (from Epiphany)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
rxwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (rxwr_fifo_wait), // Templated
.access_out (rxwr_access), // Templated
.packet_out (rxwr_packet[PW-1:0]), // Templated
// Inputs
.nreset (erx_nreset), // Templated
.clk_in (rx_lclk_div4), // Templated
.access_in (rxwr_fifo_access), // Templated
.packet_in (rxwr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.wait_in (rxwr_wait)); // Templated
//Read response fifo (for host)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
rxrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (rxrr_fifo_wait), // Templated
.access_out (rxrr_access), // Templated
.packet_out (rxrr_packet[PW-1:0]), // Templated
// Inputs
.nreset (erx_nreset), // Templated
.clk_in (rx_lclk_div4), // Templated
.access_in (rxrr_fifo_access), // Templated
.packet_in (rxrr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.wait_in (rxrr_wait)); // Templated
endmodule // erx
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
// SPDX-License-Identifier: CC0-1.0
interface intf;
logic logic_in_intf;
modport source(output logic_in_intf);
modport sink(input logic_in_intf);
endinterface
module modify_interface
(
input logic value,
intf.source intf_inst
);
assign intf_inst.logic_in_intf = value;
endmodule
function integer return_3();
return 3;
endfunction
module t
#(
parameter N = 6
)();
intf ifs[N-1:0] ();
logic [N-1:0] data;
assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1};
generate
genvar i;
for (i = 0;i < 3; i++) begin
assign ifs[i].logic_in_intf = data[i];
end
endgenerate
modify_interface m3 (
.value(data[return_3()]),
.intf_inst(ifs[return_3()]));
modify_interface m4 (
.value(data[4]),
.intf_inst(ifs[4]));
modify_interface m5 (
.value(~ifs[4].logic_in_intf),
.intf_inst(ifs[5]));
generate
genvar j;
for (j = 0;j < N-1; j++) begin
initial begin
if (ifs[j].logic_in_intf != data[j]) $stop;
end
end
endgenerate
initial begin
if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, K = 300; int n, mx, ct, ans, a[N], buc[N], lst[N * 2], tp[N], cnt; inline void Add(int x, int k) { cnt -= (tp[x] == ct), tp[x] += k, cnt += (tp[x] == ct); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i), ++buc[a[i]]; mx = max_element(buc + 1, buc + n + 1) - buc; for (ct = 1; ct <= K; ++ct) { memset(tp, 0, sizeof(tp)), cnt = 0; for (int l = 1, r = 1; r <= n; ++r) { Add(a[r], 1); while (tp[a[r]] > ct) Add(a[l++], -1); if (cnt > 1) ans = max(ans, r - l + 1); } } for (int i = 1, s; i <= n; ++i) if (i != mx && buc[i] > K) { memset(lst, -1, sizeof(lst)), lst[s = n] = 0; for (int j = 1; j <= n; ++j) { s += a[j] == mx ? 1 : (a[j] == i ? -1 : 0); if (~lst[s]) ans = max(ans, j - lst[s]); else lst[s] = j; } } printf( %d , ans); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_stdatarep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_stdatarep(/*AUTOARG*/
// Outputs
rep_store_data_c2, sctag_scdata_stdecc_c2,
// Inputs
arbdp_store_data_c2
);
// The left has 78 M3 pins.
// This control block needs to be 300-350U tall and ~50-60U wide.
input [77:0] arbdp_store_data_c2; // LEft
output [77:0] rep_store_data_c2; // Top
output [77:0] sctag_scdata_stdecc_c2; // Right
// 78 data bits.
assign sctag_scdata_stdecc_c2 = arbdp_store_data_c2 ;
assign rep_store_data_c2 = arbdp_store_data_c2 ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_TB_V
`define SKY130_FD_SC_HD__CLKINV_TB_V
/**
* clkinv: Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int inf = ~0u >> 1, MOD = 1e9 + 7; inline int rd() { int first = 0, c = 0, f = 1; for (; c < 0 || c > 9 ; c = getchar()) f = c != - ; for (; c >= 0 && c <= 9 ; c = getchar()) first = first * 10 + c - 0 ; return f ? first : -first; } const int N = 2e5 + 11; struct Edge { int v, id; Edge *nex; } pl[N << 1], *cur = pl, *G[N]; void ins(int u, int v, int id) { cur->v = v, cur->id = id; cur->nex = G[u], G[u] = cur++; } int wx[N], wy[N], n, m; int f[N], vis[N], g[N]; void dfs(int first) { vis[first] = 1; for (Edge *i = G[first]; i; i = i->nex) if (!vis[i->v]) { dfs(i->v); if (f[i->v]) { f[i->v] = 0; f[first] ^= 1; g[i->id] ^= 1; } } } int q[N]; int main() { n = rd(), m = rd(); for (int i = (1), i_end = (m); i <= i_end; i++) { wx[i] = rd(), wy[i] = rd(); ins(wx[i], wy[i], i), ins(wy[i], wx[i], i); f[wx[i]] ^= 1; } for (int i = (1), i_end = (n); i <= i_end; i++) if (!vis[i]) dfs(i); int ans = m; for (int i = (1), i_end = (n); i <= i_end; i++) if (f[i]) ans--; printf( %d n , ans >> 1); for (int first = (1), x_end = (n); first <= x_end; first++) { int cnt = 0; for (Edge *i = G[first]; i; i = i->nex) if ((wy[i->id] != first) ^ g[i->id]) { q[++cnt] = (wx[i->id] ^ wy[i->id] ^ first); } for (int i = 1; i < cnt; i += 2) { printf( %d %d %d n , q[i], first, q[i + 1]); } } }
|
/******************************************************************************
* File Name : ks30.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 1/Apr/2008
* Type of file : Verilog source code
* Synopsis : Automatically generated code for karatsuba 30 bit
******************************************************************************/
`ifndef __KS_30_V__
`define __KS_30_V__
//`include "ks15.v"
module ks30(a, b, d);
input wire [29:0] a;
input wire [29:0] b;
output wire [58:0] d;
wire [28:0] m1;
wire [28:0] m2;
wire [28:0] m3;
wire [14:0] ahl;
wire [14:0] bhl;
ks15 ksm1(a[14:0], b[14:0], m2);
ks15 ksm2(a[29:15], b[29:15], m1);
assign ahl[14:0] = a[29:15] ^ a[14:0];
assign bhl[14:0] = b[29:15] ^ b[14:0];
ks15 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13];
assign d[14] = m2[14];
assign d[15] = m2[15] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[16] = m2[16] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[17] = m2[17] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[18] = m2[18] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[19] = m2[19] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[20] = m2[20] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[21] = m2[21] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[22] = m2[22] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[23] = m2[23] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[24] = m2[24] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[25] = m2[25] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[26] = m2[26] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[27] = m2[27] ^ m1[12] ^ m2[12] ^ m3[12];
assign d[28] = m2[28] ^ m1[13] ^ m2[13] ^ m3[13];
assign d[29] = m1[14] ^ m2[14] ^ m3[14];
assign d[30] = m1[15] ^ m2[15] ^ m3[15] ^ m1[00];
assign d[31] = m1[16] ^ m2[16] ^ m3[16] ^ m1[01];
assign d[32] = m1[17] ^ m2[17] ^ m3[17] ^ m1[02];
assign d[33] = m1[18] ^ m2[18] ^ m3[18] ^ m1[03];
assign d[34] = m1[19] ^ m2[19] ^ m3[19] ^ m1[04];
assign d[35] = m1[20] ^ m2[20] ^ m3[20] ^ m1[05];
assign d[36] = m1[21] ^ m2[21] ^ m3[21] ^ m1[06];
assign d[37] = m1[22] ^ m2[22] ^ m3[22] ^ m1[07];
assign d[38] = m1[23] ^ m2[23] ^ m3[23] ^ m1[08];
assign d[39] = m1[24] ^ m2[24] ^ m3[24] ^ m1[09];
assign d[40] = m1[25] ^ m2[25] ^ m3[25] ^ m1[10];
assign d[41] = m1[26] ^ m2[26] ^ m3[26] ^ m1[11];
assign d[42] = m1[27] ^ m2[27] ^ m3[27] ^ m1[12];
assign d[43] = m1[28] ^ m2[28] ^ m3[28] ^ m1[13];
assign d[44] = m1[14];
assign d[45] = m1[15];
assign d[46] = m1[16];
assign d[47] = m1[17];
assign d[48] = m1[18];
assign d[49] = m1[19];
assign d[50] = m1[20];
assign d[51] = m1[21];
assign d[52] = m1[22];
assign d[53] = m1[23];
assign d[54] = m1[24];
assign d[55] = m1[25];
assign d[56] = m1[26];
assign d[57] = m1[27];
assign d[58] = m1[28];
endmodule
`endif
|
#include <bits/stdc++.h> void rep(const char *s, int x) { for (int i = 1; i <= x; i++) printf( %s , s); } void leading0() { putchar( 1 ); putchar( r ); rep( 0srt , 30); rep( lst , 30); putchar( l ); putchar( e ); } int main() { printf( r0l ); rep( l , 31); leading0(); putchar( u ); leading0(); putchar( u ); putchar( u ); putchar( u ); rep( r1 , 31); putchar( d ); putchar( d ); putchar( d ); rep( d , 3); rep( 1l , 31); putchar( u ); rep( re , 31); rep( u , 3); for (int j = 1; j <= 31; j++) { printf( edsddduuutttt1d0uuudst0 ); putchar( u ); rep( ust , 3); if (j > 1) { printf( dddd10utu10rtdr10ltled1uuuu ); printf( edsddduuutttt1d0uuudst0 ); putchar( u ); rep( ust , 3); printf( dddr01dtl1rt ); printf( uu ); putchar( l ); } else { putchar( l ); putchar( d ); } } putchar( d ); putchar( r ); }
|
module spiral_4(
i_data,
o_data_18,
o_data_50,
o_data_75,
o_data_89
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [18:0] i_data;
output signed [18+7:0] o_data_18;
output signed [18+7:0] o_data_50;
output signed [18+7:0] o_data_75;
output signed [18+7:0] o_data_89;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [25:0]
w1,
w8,
w9,
w16,
w25,
w4,
w5,
w80,
w75,
w89,
w18,
w50;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w16 = w1 << 4;
assign w25 = w9 + w16;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w80 = w5 << 4;
assign w75 = w80 - w5;
assign w89 = w9 + w80;
assign w18 = w9 << 1;
assign w50 = w25 << 1;
assign o_data_18=w18;
assign o_data_50=w50;
assign o_data_75=w75;
assign o_data_89=w89;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END,
input SD_DMA_START_MID_BLOCK,
input SD_DMA_END_MID_BLOCK,
output [10:0] DBG_cyclecnt,
output [2:0] DBG_clkcnt
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 3'b111;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(cyclecnt == 1042
|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising)
cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
else if(!SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1: begin
SD_DMA_NEXTADDRr <= 1'b0;
end
3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; struct node { int v, w, next; } edges[maxn << 2]; int head[maxn], cnt; int n, k; void add_edge(int u, int v, int w) { edges[++cnt] = {v, w, head[u]}; head[u] = cnt; } long long dp[maxn][2]; void dfs(int rt, int fa) { vector<long long> vv; long long ans = 0; for (int i = head[rt]; i; i = edges[i].next) { if (edges[i].v == fa) continue; dfs(edges[i].v, rt); vv.push_back(dp[edges[i].v][0] + edges[i].w - dp[edges[i].v][1]); ans += dp[edges[i].v][1]; } sort(vv.begin(), vv.end(), greater<long long>()); if (k == 1) dp[rt][0] = ans; for (int i = 0; i < vv.size(); ++i) { if (i < k && vv[i] > 0) ans += vv[i]; if (i == k - 1 - 1) dp[rt][0] = ans; if (i == k - 1) dp[rt][1] = ans; } if (dp[rt][0] == -1) dp[rt][0] = ans; if (dp[rt][1] == -1) dp[rt][1] = ans; } int main() { int q; scanf( %d , &q); while (q--) { scanf( %d%d , &n, &k); memset(head, 0, sizeof(int) * (n + 1)); memset(dp, -1, sizeof(long long) * (n + 1) * 2); cnt = 0; for (int i = 0, u, v, w; i < n - 1; ++i) { scanf( %d%d%d , &u, &v, &w); add_edge(u, v, w); add_edge(v, u, w); } dfs(1, 0); printf( %lld n , max(dp[1][0], dp[1][1])); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int N, M, K; long long F[1111][1111], T[1111], G[111111]; map<int, int> P; inline long long Pow(long long A, int B) { long long Ret = 1; for (; B; B >>= 1) { if (B & 1) { Ret = (Ret * A) % MOD; } A = (A * A) % MOD; } return Ret; } int main(int argc, char *argv[]) { for (int l = 1; l < 10; l++) { for (int i = 0; i < 1 << l; i++) { int x = 0; for (int k = 0; k < l; k++) { x *= 10; if (i & (1 << k)) { x += 4; } else { x += 7; } } P[x] = ++M; } } scanf( %d%d , &N, &K); for (int i = 0, x; i < N; i++) { scanf( %d , &x); if (P.find(x) != P.end()) { T[P[x]]++; } else { T[0]++; } } N = T[0]; F[0][0] = 1; for (int i = 1; i <= M; i++) { for (int j = 0; j <= M; j++) if (F[i - 1][j]) { F[i][j] = (F[i][j] + F[i - 1][j]) % MOD; F[i][j + 1] = (F[i][j + 1] + F[i - 1][j] * T[i]) % MOD; } } G[0] = 1; for (int i = 1; i <= N; i++) { G[i] = (G[i - 1] * (N + 1 - i)) % MOD; G[i] = (G[i] * Pow(i, MOD - 2)) % MOD; } long long Ret = 0; for (int i = 0; i <= M && i <= K; i++) { Ret += F[M][i] * G[K - i]; Ret %= MOD; } printf( %I64d n , Ret); return 0; }
|
#include <bits/stdc++.h> int main() { int n, x, m, count; scanf( %d %d , &n, &m); for (x = 1, count = 0; x <= n; x++) { if (m % x == 0 && (m / x) <= n) { count = count + 1; } } printf( %d , count); }
|
#include <bits/stdc++.h> using namespace std; int Get() { char c; while (c = getchar(), (c < 0 || c > 9 ) && c != - ) ; bool Flag = (c == - ); if (Flag) c = getchar(); int X = 0; while (c >= 0 && c <= 9 ) { X = X * 10 + c - 48; c = getchar(); } return Flag ? -X : X; } int main() { int N = Get(), Sum = 0; for (int i = 0; i < N; i++) Sum += Get(); printf( %d n , (Sum % N) ? (N - 1) : N); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n >> x; int pos = 1; long long ans = 0; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; ans += 1LL * (l - pos) % x + (r - l + 1); pos = r + 1; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_2_V
`define SKY130_FD_SC_HD__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_2_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_outputMem.v when simulating
// the core, blk_mem_gen_outputMem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_outputMem(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [7 : 0] dina;
input clkb;
input [12 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Data { int r, c, v; bool operator<(const Data &r) const { return v < r.v; } }; vector<vector<int> > mat, ans; Data sorteds[1001000]; int mR[1001000], mC[1001000]; map<pair<int, int>, vector<int> > mr, mc; void recursiveFix(int rr, int cc) { vector<int> &vv = mr[pair<int, int>(rr, mat[rr][cc])]; vector<int> t = vv; for (int j = int(0); j < int(vv.size()); j++) { ans[rr][vv[j]] = ans[rr][cc]; } vv.clear(); vector<int> &vv2 = mc[pair<int, int>(cc, mat[rr][cc])]; vector<int> t2 = vv2; for (int j = int(0); j < int(vv2.size()); j++) { ans[vv2[j]][cc] = ans[rr][cc]; } vv2.clear(); for (int j = int(0); j < int(t2.size()); j++) recursiveFix(t2[j], cc); for (int j = int(0); j < int(t.size()); j++) recursiveFix(rr, t[j]); } int main() { int N, M; while (scanf( %d %d , &N, &M) != EOF) { int c = 0; vector<int> t(M + 1); mr.clear(), mc.clear(); mat.clear(); ans.clear(); mat.push_back(t); ans.push_back(t); for (int i = int(1); i < int(N + 1); i++) { mat.push_back(t); ans.push_back(t); for (int j = int(1); j < int(M + 1); j++) { scanf( %d , &mat[i][j]); sorteds[c++] = Data{i, j, mat[i][j]}; ans[i][j] = 1; mr[pair<int, int>(i, mat[i][j])].push_back(j); mc[pair<int, int>(j, mat[i][j])].push_back(i); } } sort(sorteds, sorteds + c); memset(mR, 0, sizeof(mR)); memset(mC, 0, sizeof(mC)); int prev = -1; priority_queue<Data> q; for (int i = int(0); i < int(c); i++) { if (prev != sorteds[i].v) { while (!q.empty()) { int rr = q.top().r, cc = q.top().c; recursiveFix(rr, cc); q.pop(); } } int r = sorteds[i].r, c = sorteds[i].c; ans[r][c] = 0; if (mat[r][mR[r]] == mat[r][c]) ans[r][c] = max(ans[r][c], ans[r][mR[r]]); else ans[r][c] = max(ans[r][c], ans[r][mR[r]] + 1); if (mat[mC[c]][c] == mat[r][c]) ans[r][c] = max(ans[r][c], ans[mC[c]][c]); else ans[r][c] = max(ans[r][c], ans[mC[c]][c] + 1); q.push(Data{r, c, ans[r][c]}); mR[r] = c; mC[c] = r; prev = sorteds[i].v; } while (!q.empty()) { int rr = q.top().r, cc = q.top().c; recursiveFix(rr, cc); q.pop(); } for (int i = int(0); i < int(N); i++) { for (int j = int(0); j < int(M); j++) printf( %d%c , ans[i + 1][j + 1], n [j == M - 1]); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SREGRBP_BEHAVIORAL_PP_V
/**
* sregrbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sregrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire reset ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire ASYNC_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (reset , ASYNC_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, reset, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( ASYNC_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( ASYNC === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int a[1000005]; queue<long long int> q; vector<long long int> v; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int i, j, k, n, m, mid; cin >> k; string s; cin >> s; n = s.size(); int co = 0; long long int sum = 0; if (k == 0) { for (i = 0; i < n; i++) { if (s[i] == 0 ) { co++; } else co = 0; sum += (co); } cout << sum; return 0; } for (i = 0; i < n; i++) { if (s[i] == 1 ) { a[i] = co; co = 0; v.push_back(i); } else co++; } long long int first = 0; long long int l = v.size(); for (i = k - 1; i < l; i++) { long long int temp1 = a[v[first]] + 1; long long int temp2; if (i + 1 < l) temp2 = v[i + 1] - v[i]; else temp2 = n - v[i]; sum += temp1 * temp2; first++; } cout << sum; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// or1200_fpu_pre_norm_mul ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// pre-normalization entity for the multiplication unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module or1200_fpu_pre_norm_mul (
clk_i,
opa_i,
opb_i,
exp_10_o,
fracta_24_o,
fractb_24_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk_i;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
output reg [EXP_WIDTH+1:0] exp_10_o;
output [FRAC_WIDTH:0] fracta_24_o;
output [FRAC_WIDTH:0] fractb_24_o;
wire [EXP_WIDTH-1:0] s_expa;
wire [EXP_WIDTH-1:0] s_expb;
wire [FRAC_WIDTH-1:0] s_fracta;
wire [FRAC_WIDTH-1:0] s_fractb;
wire [EXP_WIDTH+1:0] s_exp_10_o;
wire [EXP_WIDTH+1:0] s_expa_in;
wire [EXP_WIDTH+1:0] s_expb_in;
wire s_opa_dn, s_opb_dn;
assign s_expa = opa_i[30:23];
assign s_expb = opb_i[30:23];
assign s_fracta = opa_i[22:0];
assign s_fractb = opb_i[22:0];
// Output Register
always @(posedge clk_i)
exp_10_o <= s_exp_10_o;
// opa or opb is denormalized
assign s_opa_dn = !(|s_expa);
assign s_opb_dn = !(|s_expb);
assign fracta_24_o = {!s_opa_dn, s_fracta};
assign fractb_24_o = {!s_opb_dn, s_fractb};
assign s_expa_in = {2'd0, s_expa} + {9'd0, s_opa_dn};
assign s_expb_in = {2'd0, s_expb} + {9'd0, s_opb_dn};
assign s_exp_10_o = s_expa_in + s_expb_in - 10'b0001111111;
endmodule // or1200_fpu_pre_norm_mul
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { int f = 0, c = getchar(); x = 0; while (!isdigit(c)) f |= c == 45, c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); if (f) x = -x; } template <typename T, typename... Args> inline void read(T &x, Args &...args) { read(x); read(args...); } const int maxn = 2e5 + 50; int fa[maxn], bj[maxn], n, m, ans; struct node { int x, y, z; } e[maxn]; bool cmp(node a, node b) { return a.z > b.z; } inline int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } signed main() { read(n, m); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) read(e[i].x, e[i].y, e[i].z); stable_sort(e + 1, e + 1 + m, cmp); for (int i = 1; i <= m; i++) { int f1 = find(e[i].x), f2 = find(e[i].y); if (f1 == f2) { if (bj[f1] == 0) bj[f1] = 1, ans += e[i].z; else continue; } else { if (bj[f1] + bj[f2] == 0) fa[f1] = f2, ans += e[i].z; if (bj[f1] == 1 && bj[f2] == 0) fa[f2] = f1, ans += e[i].z; if (bj[f1] == 0 && bj[f2] == 1) fa[f1] = f2, ans += e[i].z; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_1_V
`define SKY130_FD_SC_HDLL__OR4_1_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_1_V
|
#include<bits/stdc++.h> using namespace std; int a[505],ch[505][505],cnt[505]; int main(){ ios_base::sync_with_stdio(0),cin.tie(0); int n,c=0,i,j; cin>>n; for(i=1;i<=n;i++)cin>>a[i],ch[i][i]=a[i],cnt[a[i]]=a[i]-1; for(i=1;i<=n&&c==0;i++){ int x,y; x=y=i; while(cnt[a[i]]>0){ cnt[a[i]]--; if(x-1>0&&ch[y][x-1]==0)x--,ch[y][x]=a[i]; else if(y+1<=n&&ch[y+1][x]==0)y++,ch[y][x]=a[i]; else {c=1;break;} } } if(c)cout<< -1 n ; else{ for(i=1;i<=n;i++){ for(j=1;j<=i;j++)cout<<ch[i][j]<< ; cout<<endl; } } return 0; }
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input inhibit,
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.inhibit (inhibit),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V
/**
* buflp: Buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__buflp (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V
|
module main;
reg signed [7:0] a;
reg [7:0] b;
initial begin
// Make sure the arithmetic right shift sign extends
$display("simple arithmetic right shift");
a = 8'b11001001;
$display("before: a = %b", a);
a = a>>>1;
$display("after: a = %b", a);
if (a !== 8'b11100100) begin
$display("FAILED");
$finish;
end
// The concatenation operator is always unsigned, so
// it must turn off sign extension.
$display("concatenated arithmetic right shift");
a = 8'b11001001;
b = 0;
$display("before: a = %b", a);
{a,b} = {a,b}>>>1;
$display("after: a = %b", a);
if (a !== 8'b01100100) begin
$display("FAILED");
$finish;
end
// The concatenation operator is always unsigned, but
// we can turn on signed behavior with $signed.
$display("concatenated arithmetic right shift with $signed");
a = 8'b11001001;
b = 0;
$display("before: a = %b", a);
{a,b} = $signed({a,b})>>>1;
$display("after: a = %b", a);
if (a !== 8'b11100100) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2e9; const long long MOD = 1e9 + 7; mt19937 azino(777); int ask(int a, int b, int c) { cout << ? << a << << b << << c << endl; int x; cin >> x; return x; } void answer(vector<int>& ans) { cout << ! << ans.size() << ; for (auto& it : ans) cout << it << ; cout << endl; return; } vector<int> pp(int pos0, int pos1, int pos, int type) { vector<int> p(3, -1); if (type == 0) { int c1 = ask(pos1, pos, pos + 1); int c2 = ask(pos1, pos, pos + 2); if (c1 == c2) { if (c1 == 0) p[0] = p[1] = p[2] = 0; if (c1 == 1) p[0] = 1, p[1] = p[2] = 0; } else { if (c1 == 0) p[0] = p[1] = 0; if (c2 == 0) p[0] = p[2] = 0; for (auto& i : p) if (i == -1) i = 1; } } else { int c1 = ask(pos0, pos, pos + 1); int c2 = ask(pos0, pos, pos + 2); if (c1 == c2 && c1 == 1) p[0] = p[1] = p[2] = 1; else if (c1 == c2 && c1 == 0) p[0] = 0, p[1] = p[2] = 1; else { if (c1 == 1) p[0] = p[1] = 1; if (c2 == 1) p[0] = p[2] = 1; for (auto& i : p) if (i == -1) i = 0; } } return p; } void solve() { int n; cin >> n; vector<int> z(n); int pos0 = 0, pos1 = 0; for (int i = 0; i < n; i += 3) { z[i] = ask(i + 1, i + 2, i + 3); if (z[i]) pos1 = i; else pos0 = i; } vector<int> p0(3, -1), p1(3, -1); int c1 = ask(pos1 + 1, pos1 + 2, pos0 + 1); int c2 = ask(pos1 + 1, pos1 + 2, pos0 + 2); int poss0 = -1, poss1 = -1; if (c1 == c2) { if (c1 == 0) p0[0] = p0[1] = 0; else p1[0] = p1[1] = 1; } else { p0[0] = c1, p0[1] = c2; if (c1 == 0) poss0 = pos0 + 1; else poss1 = pos0 + 1; if (c2 == 0) poss0 = pos0 + 2; else poss1 = pos0 + 2; } if (p0[0] == -1) { c1 = ask(pos1 + 1, pos0 + 1, pos0 + 2); c2 = ask(pos1 + 1, pos0 + 1, pos0 + 3); if (c1 == c2 && c1 == 0) p0[0] = p0[1] = p0[2] = 0; else if (c1 == c2 && c1 == 1) p0[0] = 1, p0[1] = p0[2] = 0; else { if (c1 == 0) p0[0] = p0[1] = 0; if (c2 == 0) p0[0] = p0[2] = 0; for (auto& i : p0) if (i == -1) i = 1; } for (int i = 0; i < 3; ++i) if (p0[i] == 0) poss0 = pos0 + 1 + i; else poss1 = pos0 + 1 + i; c1 = ask(poss0, pos1 + 1, pos1 + 2); c2 = ask(poss0, pos1 + 1, pos1 + 3); if (c1 == c2) { if (c1 == 1) p1[0] = p1[1] = p1[2] = 1; if (c1 == 0) p1[0] = 0, p1[1] = p1[2] = 1; } else { if (c1 == 1) p1[0] = p1[1] = 1; if (c2 == 1) p1[0] = p1[2] = 1; for (auto& i : p1) if (i == -1) i = 0; } for (int i = 0; i < 3; ++i) if (p1[i] == 0) poss0 = pos1 + 1 + i; else poss1 = pos1 + 1 + i; } else { if (poss0 != -1) { for (int i = 0; i < 3; ++i) p1[i] = ask(poss1, poss0, pos1 + 1 + i); p0[2] = ask(poss1, poss0, pos0 + 3); } else { c1 = ask(pos0 + 1, pos1 + 1, pos1 + 2); c2 = ask(pos0 + 1, pos1 + 1, pos1 + 3); if (c1 == c2 && c1 == 1) p1[0] = p1[1] = p1[2] = 1; else if (c1 == c2 && c1 == 0) p1[0] = 0, p1[1] = p1[2] = 1; else { if (c1 == 1) p1[0] = p1[1] = 1; if (c2 == 1) p1[0] = p1[2] = 1; for (auto& i : p1) if (i == -1) i = 0; } for (int i = 0; i < 3; ++i) if (p1[i] == 0) poss0 = pos1 + 1 + i; else poss1 = pos1 + 1 + i; c1 = ask(poss1, pos0 + 1, pos0 + 2); c2 = ask(poss1, pos0 + 1, pos0 + 3); if (c1 == c2) { if (c1 == 0) p0[0] = p0[1] = p0[2] = 0; if (c1 == 1) p0[0] = 1, p0[1] = p0[2] = 0; } else { if (c1 == 0) p0[0] = p0[1] = 0; if (c2 == 0) p0[0] = p0[2] = 0; for (auto& i : p0) if (i == -1) i = 1; } for (int i = 0; i < 3; ++i) if (p0[i] == 0) poss0 = pos0 + 1 + i; else poss1 = pos0 + 1 + i; } } vector<int> ans; for (int i = 0; i < 3; ++i) if (p0[i] == 0) ans.emplace_back(pos0 + i + 1); for (int i = 0; i < 3; ++i) if (p1[i] == 0) ans.emplace_back(pos1 + i + 1); for (int i = 0; i < n; i += 3) { if (i == pos0 || i == pos1) continue; auto it = pp(poss0, poss1, i + 1, z[i]); for (int j = 0; j < 3; ++j) if (it[j] == 0) ans.emplace_back(i + 1 + j); } answer(ans); } signed main() { cout << fixed << setprecision(15); int t; cin >> t; while (t-- > 0) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; struct query { long long k, pos, ind; }; struct fenwick { long long n; vector<long long> f; fenwick(long long _n) { n = _n; f.resize(n, 0); } void add(long long val, long long i) { for (; i < n; i |= (i + 1)) f[i] += val; } long long sum(long long i) { long long ans = 0; for (; i >= 0; i &= (i + 1), --i) ans += f[i]; return ans; } }; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<pair<long long, long long> > a(n); vector<long long> start(n); for (long long i = 0; i < n; ++i) { cin >> a[i].first; start[i] = a[i].first; a[i].second = i; } sort(a.begin(), a.end(), [](pair<long long, long long> a, pair<long long, long long> b) { if (a.first == b.first) return a.second > b.second; return a.first < b.first; }); reverse(a.begin(), a.end()); long long q; cin >> q; vector<query> qs(q); for (long long t = 0; t < q; ++t) { cin >> qs[t].k >> qs[t].pos; qs[t].k--; qs[t].pos--; qs[t].ind = t; } sort(qs.begin(), qs.end(), [](query a, query b) { return a.k < b.k; }); fenwick f(n); long long l = -1; vector<long long> ans(q); for (long long i = 0; i < q; ++i) { while (l < qs[i].k) { ++l; f.add(1, a[l].second); } long long L = 0, R = n - 1; while (R - L > 1) { long long m = (R + L) / 2; if (f.sum(m) <= qs[i].pos) { L = m; } else R = m; } if (f.sum(L) < qs[i].pos + 1) swap(L, R); ans[qs[i].ind] = start[L]; } for (auto x : ans) cout << x << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, arr[1000], arr2[1000], i = 0; cin >> n; while (i < n) { cin >> arr[i]; arr2[arr[i]] = i + 1; i++; } sort(arr, arr + n); for (i = 0; i < n; i++) { cout << arr2[arr[i]] << ; } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module buffer2axis #(
parameter DWIDTH = 32,
parameter WIDTH = 8
)(
// Control signals
clk,
rstn,
// Color conversion signals
alive_color,
dead_color,
// AXIS Connection
M_AXIS_TDATA,
M_AXIS_TVALID,
M_AXIS_TREADY,
M_AXIS_TLAST,
M_AXIS_TKEEP,
M_AXIS_TSTRB,
// Output to conware computation
in_data,
in_valid,
in_ready,
num_writes,
counter
);
// Port descriptions
input clk;
input rstn;
input [DWIDTH-1:0] alive_color;
input [DWIDTH-1:0] dead_color;
output reg [DWIDTH-1:0] M_AXIS_TDATA;
output reg M_AXIS_TVALID;
output reg M_AXIS_TLAST;
input M_AXIS_TREADY;
output [3:0] M_AXIS_TKEEP;
output [3:0] M_AXIS_TSTRB;
input [WIDTH-1:0] in_data;
input in_valid;
output reg in_ready;
output reg [31:0] num_writes;
reg next_num_writes;
// State params
reg state;
reg next_state;
localparam Wait = 0;
localparam Write = 1;
// Internal values
reg [WIDTH - 1:0] buffer;
reg [WIDTH - 1:0] next_buffer;
output reg [7:0] counter;
reg [7:0] next_counter;
initial begin
state <= Wait;
buffer <= 0;
counter <= 0;
num_writes <= 0;
end
assign M_AXIS_TKEEP = 4'b1111;
assign M_AXIS_TSTRB = 4'b1111;
// Combinational Logic
always @* begin
next_counter <= 0;
next_num_writes <= num_writes;
if (buffer[counter]) begin
M_AXIS_TDATA <= alive_color;
end else begin
M_AXIS_TDATA <= dead_color;
end
if (state == Wait && next_state == Write) begin
next_buffer <= in_data;
end else begin
next_buffer <= buffer;
end
case (state)
Wait: begin
M_AXIS_TLAST <= 0;
next_counter <= 0;
M_AXIS_TVALID <= 0;
in_ready <= 1;
if (in_valid == 1) begin
next_state <= Write;
end else begin
next_state <= Wait;
end
end
Write: begin
M_AXIS_TVALID <= 1;
in_ready <= 0;
if (counter == WIDTH-1) begin
M_AXIS_TLAST <= 1;
end else begin
M_AXIS_TLAST <= 0;
end
if (M_AXIS_TREADY == 1) begin
if (counter == WIDTH-1) begin
next_counter <= 0;
next_state <= Wait;
next_num_writes <= num_writes + 1;
end else begin
next_counter <= counter + 1;
next_state <= Write;
end
end else begin
next_counter <= counter;
next_state <= Write;
end
end
endcase
end
// Clocked Logic
always @(posedge clk) begin
if (!rstn) begin
counter <= 8'h00;
state <= Wait;
num_writes <= 0;
end else begin
buffer <= next_buffer;
state <= next_state;
counter <= next_counter;
num_writes <= next_num_writes;
end
end
endmodule
|
module serializer
#( parameter INLOGBITS = 6,
parameter OUTLOGBITS = 3,
localparam INWIDTH = 1<<INLOGBITS,
localparam OUTWIDTH = 1<<OUTLOGBITS)
(
input clk,
input rst_n,
input in_valid,
output reg in_ready,
input [INWIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [OUTWIDTH-1:0] out_data
);
localparam LOGBITDIFF = INLOGBITS-OUTLOGBITS ;
localparam MAXCNT = (1<<LOGBITDIFF)-1;
reg [LOGBITDIFF-1:0] cnt;
reg [LOGBITDIFF-1:0] cnt_next;
reg [INWIDTH-1:0] in_buf;
wire [INWIDTH-1:0] in_buf_shifted;
reg [INWIDTH-1:0] in_buf_next;
assign in_buf_shifted = in_buf >> OUTWIDTH ;
assign out_data = in_buf[OUTWIDTH-1:0] ;
reg in_buf_valid;
reg in_buf_valid_next;
assign out_valid = in_buf_valid;
always @(*) begin
in_buf_next = in_buf;
in_ready = 0;
in_buf_valid_next = in_buf_valid;
cnt_next = cnt;
if (cnt == MAXCNT && !in_buf_valid && in_valid) begin
in_buf_next = in_data;
in_buf_valid_next = 1;
in_ready = 1;
end
else if (cnt == 0 && out_ready && in_valid) begin // in_valid better be valid
cnt_next = cnt - 1'b1;
in_buf_valid_next = 1;
in_buf_next = in_data;
in_ready = 1;
end
else if (cnt == 0 && out_ready && !in_valid) begin // should never be here for vga
in_buf_valid_next = 0;
in_ready = 1;
end
else if (out_ready) begin
cnt_next = cnt - 1'b1;
in_buf_next = in_buf_shifted;
in_ready = 0;
end
end
`REG(clk, cnt, MAXCNT, cnt_next)
`REG(clk, in_buf_valid, 0, in_buf_valid_next)
`REG(clk, in_buf, 0, in_buf_next)
endmodule
/*
serializer #(.INLOGBITS(6), .OUTLOGBITS(3)) inst_XXX(
.clk(clk),
.rst_n(rst_n),
.in_valid(XXX_in_valid),
.in_ready(XXX_in_ready),
.in_data(XXX_in_data),
.out_valid(XXX_out_valid),
.out_ready(XXX_out_ready),
.out_data(XXX_out_data)
);
*/
|
#include <bits/stdc++.h> using namespace std; int N, M; vector<int> graph[200005]; int nd[2], deg[2]; int cnt[2][200005]; int dsu[200005]; int olddsu[200005]; int sz[4]; int getrt(int n) { return dsu[n] = (dsu[n] == n ? n : getrt(dsu[n])); } int getoldrt(int n) { return olddsu[n] = (olddsu[n] == n ? n : getoldrt(olddsu[n])); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N >> M; for (int i = 1; i <= M; i++) { int a, b; cin >> a >> b; graph[a].push_back(b); graph[b].push_back(a); } cin >> nd[0] >> nd[1] >> deg[0] >> deg[1]; for (int i = 1; i <= N; i++) { dsu[i] = i; } vector<pair<int, int>> ans; for (int n = 1; n <= N; n++) { for (int e : graph[n]) { if (n != nd[0] && n != nd[1] && e != nd[0] && e != nd[1]) { if (getrt(n) != getrt(e)) { dsu[getrt(n)] = getrt(e); ans.emplace_back(n, e); } } } } bool spedge = 0; for (int k = 0; k < 2; k++) { for (int e : graph[nd[k]]) { cnt[k][getrt(e)]++; if (e == nd[0] || e == nd[1]) { spedge = 1; } } cnt[k][nd[0]] = cnt[k][nd[1]] = 0; } for (int i = 1; i <= N; i++) { olddsu[i] = dsu[i]; } for (int k = 0; k < 2; k++) { for (int e : graph[nd[k]]) { if (getrt(e) != getrt(nd[k]) && cnt[k][getoldrt(e)] && !cnt[k ^ 1][getoldrt(e)]) { ans.emplace_back(e, nd[k]); dsu[getrt(e)] = getrt(nd[k]); deg[k]--; } } } for (int k = 0; k < 2; k++) { for (int e : graph[nd[k]]) { if (cnt[k][getoldrt(e)] && cnt[k ^ 1][getoldrt(e)] && getrt(e) != getrt(nd[k]) && deg[k] > 0) { ans.emplace_back(e, nd[k]); dsu[getrt(e)] = getrt(nd[k]); deg[k]--; } } } if (deg[0] > 0 && deg[1] > 0 && spedge && getrt(nd[0]) != getrt(nd[1])) { deg[0]--, deg[1]--; ans.emplace_back(nd[0], nd[1]); dsu[getrt(nd[0])] = getrt(nd[1]); } if (ans.size() == N - 1 && deg[0] >= 0 && deg[1] >= 0) { cout << Yes n ; for (auto p : ans) { cout << p.first << << p.second << n ; } } else { cout << No n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_SYMBOL_V
`define SKY130_FD_SC_HS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : gtx_drp_chanalign_fix_3752_v6.v
// Version : 1.7
//--
//-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module GTX_DRP_CHANALIGN_FIX_3752_V6
#(
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [7:0] daddr,
output reg [3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
parameter TCQ = 1;
parameter DRP_IDLE_FTS = 1;
parameter DRP_IDLE_TS1 = 2;
parameter DRP_RESET = 3;
parameter DRP_WRITE_FTS = 6;
parameter DRP_WRITE_DONE_FTS = 7;
parameter DRP_WRITE_TS1 = 8;
parameter DRP_WRITE_DONE_TS1 = 9;
parameter DRP_COM = 10'b0110111100;
parameter DRP_FTS = 10'b0100111100;
parameter DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if ( ~Reset_n ) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate=drpstate;
next_daddr=daddr;
den=0;
din=0;
dwe=0;
case(drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET : begin
next_drpstate= DRP_WRITE_TS1;
next_daddr=8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFD3C;
else if(daddr==8'h9)
din=16'hC53C;
else if(daddr==8'hA)
din=16'hFDBC;
else if(daddr==8'hB)
din=16'h853C;
next_drpstate=DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_FTS;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=daddr+1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS : begin
if(write_ts1_gated) begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1 : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFC4A;
else if(daddr==8'h9)
din=16'hDC4A; //CHANGE
else if(daddr==8'hA)
din=16'hC04A; //CHANGE
else if(daddr==8'hB)
din=16'h85BC;
next_drpstate=DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1 : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_TS1;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=daddr+1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1 : begin
if(write_fts_gated) begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=8'h8;
end
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HDLL__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hdll__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_4TO2_TB_V
|
// $Id: c_fifo_ctrl.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// simple FIFO controller
module c_fifo_ctrl
(clk, reset, push, pop, write_addr, read_addr, almost_empty, empty,
almost_full, full, errors);
`include "c_constants.v"
// address width
parameter addr_width = 3;
// starting address (i.e., address of leftmost entry)
parameter offset = 0;
// number of entries in FIFO
parameter depth = 8;
// minimum (leftmost) address
localparam [0:addr_width-1] min_value = offset;
// maximum (rightmost) address
localparam [0:addr_width-1] max_value = offset + depth - 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// write (add) an element
input push;
// read (remove) an element
input pop;
// address to write current input element to
output [0:addr_width-1] write_addr;
wire [0:addr_width-1] write_addr;
// address to read next output element from
output [0:addr_width-1] read_addr;
wire [0:addr_width-1] read_addr;
// buffer nearly empty (1 used slot remaining) indication
output almost_empty;
wire almost_empty;
// buffer empty indication
output empty;
wire empty;
// buffer almost full (1 unused slot remaining) indication
output almost_full;
wire almost_full;
// buffer full indication
output full;
wire full;
// internal error condition detected
output [0:1] errors;
wire [0:1] errors;
wire [0:addr_width-1] read_ptr_next, read_ptr_q;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
read_ptr_incr
(.data_in(read_ptr_q),
.data_out(read_ptr_next));
wire [0:addr_width-1] read_ptr_s;
assign read_ptr_s = pop ? read_ptr_next : read_ptr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
read_ptrq
(.clk(clk),
.reset(reset),
.d(read_ptr_s),
.q(read_ptr_q));
assign read_addr[0:addr_width-1] = read_ptr_q;
wire [0:addr_width-1] write_ptr_next, write_ptr_q;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
write_ptr_incr
(.data_in(write_ptr_q),
.data_out(write_ptr_next));
wire [0:addr_width-1] write_ptr_s;
assign write_ptr_s = push ? write_ptr_next : write_ptr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
write_ptrq
(.clk(clk),
.reset(reset),
.d(write_ptr_s),
.q(write_ptr_q));
assign write_addr[0:addr_width-1] = write_ptr_q;
assign almost_empty = (read_ptr_next == write_ptr_q);
wire empty_s, empty_q;
assign empty_s = (empty_q | (almost_empty & pop & ~push)) & ~(push & ~pop);
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
emptyq
(.clk(clk),
.reset(reset),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
assign almost_full = (write_ptr_next == read_ptr_q);
wire full_s, full_q;
assign full_s = (full_q | (almost_full & push & ~pop)) & ~(pop & ~push);
c_dff
#(.width(1),
.reset_type(reset_type))
fullq
(.clk(clk),
.reset(reset),
.d(full_s),
.q(full_q));
assign full = full_q;
wire error_underflow;
assign error_underflow = empty & pop & ~push;
wire error_overflow;
assign error_overflow = full & push & ~pop;
assign errors = {error_underflow, error_overflow};
// synopsys translate_off
generate
if(depth > (1 << addr_width))
begin
initial
begin
$display({"ERROR: FIFO controller %m requires that addr_width ",
"be at least wide enough to cover the entire depth."});
$stop;
end
end
endgenerate
// synopsys translate_on
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module ram (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_dout; // RAM data output
// INPUTs
//============
input [ADDR_MSB:0] ram_addr; // RAM address
input ram_cen; // RAM chip enable (low active)
input ram_clk; // RAM clock
input [15:0] ram_din; // RAM data input
input [1:0] ram_wen; // RAM write enable (low active)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
wire [15:0] mem_val = mem[ram_addr];
always @(posedge ram_clk)
if (~ram_cen & ram_addr<(MEM_SIZE/2))
begin
if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
ram_addr_reg <= ram_addr;
end
assign ram_dout = mem[ram_addr_reg];
endmodule // ram
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long n; cin >> n; string s; cin >> s; set<char> all; for (auto c : s) all.insert(c); const long long sz = all.size(); if (sz == 1) { cout << 1 n ; return 0; } long long lo = 1; long long hi = n; long long a = n; while (lo <= hi) { long long mid = (lo + hi) / 2; map<char, long long> freq; bool poss = false; long long dist = 0; for (long long i = 0; i < mid; i++) { freq[s[i]]++; if (freq[s[i]] == 1) dist++; } for (long long i = mid; i < n; i++) { if (dist == sz) poss = true; if (--freq[s[i - mid]] == 0) dist--; if (++freq[s[i]] == 1) dist++; if (dist == sz) poss = true; } if (poss) { a = min(a, mid); hi = mid - 1; } else lo = mid + 1; } cout << a << n ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 11:50:15 09/27/2015
// Design Name: Lab2Part2AJM
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/Lab2-Part2-Controller7SegmentDisplayKeypadScanner/Lab2Part2AJMTest.v
// Project Name: Lab2-Part2-Controller7SegmentDisplayKeypadScanner
////////////////////////////////////////////////////////////////////////////////
module Lab2Part2AJMTest;
reg [3:0] Rows;
reg ClockIn, Start, Reset;
wire [3:0] Columns;
wire Locked, Found;
wire [7:0] Display;
wire [3:0] Transistors;
defparam uut.StartSwitch.Timer.Divider = 3;
defparam uut.ControlUnit.Timer.Divider = 3;
Lab2Part2AJM uut(Rows, ClockIn, Start, Reset, Columns, Locked, Found, Display, Transistors);
defparam uut.ControlUnit.Timer.Divider = 3;
wire [7:0] Segment0 = uut.Segment0;
wire [7:0] Segment1 = uut.Segment1;
wire [7:0] Segment2 = uut.Segment2;
wire [7:0] Segment3 = uut.Segment3;
wire [3:0] OnesDigit = uut.OnesDigit;
wire [3:0] TensDigit = uut.TensDigit;
wire [2:0] ControllerCurrentState = uut.ControlUnit.CurrentState;
wire [2:0] ControllerNextState = uut.ControlUnit.NextState;
wire ControllerStart = uut.ControlUnit.Start;
wire DebouncedStart = uut.DebouncedStart;
wire NormalStart = uut.Start;
wire [1:0] DebouncerState = uut.StartSwitch.State;
wire [1:0] DebouncerNextState = uut.StartSwitch.NextState;
always #5 ClockIn = ~ClockIn;
initial begin
Rows = 4'b0000; ClockIn = 0; Start = 0; Reset = 1; #100;
Reset = 0; #100;
Rows = 4'b1111; #100;
Start = 1; #500;
Rows = 4'b1111; #100;
Rows = 4'b1011; #100;
Rows = 4'b0111; #200;
$stop;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_DAY_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_DAY_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_DAY
);
localparam N = 5; // Para definir el número de bits del contador (hasta 31->5 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 5'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 6)
begin
if (enUP)
begin
if (q_act >= 5'd30) q_next = 5'd0;
else q_next = q_act + 5'd1;
end
else if (enDOWN)
begin
if (q_act == 5'd0) q_next = 5'd30;
else q_next = q_act - 5'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act + 5'b1;//Suma 1 a todas las cuentas de 0->30 a 1->31
//Decodificaci?n BCD (2 d?gitos)
always@*
begin
case(count_data)
5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
5'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
5'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
5'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
5'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
5'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
5'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
5'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
5'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_DAY = {digit1,digit0};
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: ldelay4.v,v 1.3 2007/12/06 02:31:10 stevewilliams Exp $
// Test for delays in structural logic. Differential clock receiver UDP.
module test;
wire q, e;
reg a, b;
drec #1 rec(q, a, b);
edet det (e, q);
reg error;
initial
begin
error = 0;
#2;
forever @(e)
if (e !== 1'bx) begin // Fail on anything other then x.
error = 1;
$display("%0d: FAILED: e=%b", $time, e);
end
end
always @(q)
$display("%d: q=%b", $time, q);
initial
begin
// $dumpvars;
a = 0;
b = 1;
#3;
a = 1;
b = 0;
#2;
a = 0;
b = 1;
#3;
if (!error)
$display("PASSED");
end
endmodule
// differential receiver
primitive drec (q, a, b);
output q;
input a, b;
table
1 0 : 1 ;
0 1 : 0 ;
endtable
endprimitive
// flag any edges to or from 'bx
primitive edet (q, i);
output q;
input i;
reg q;
table
(?x) : ? : 1;
(x?) : ? : 0;
endtable
endprimitive
|
`default_nettype none
`timescale 1ns / 1ps
// This module works by maintaining a snapshot of two bytes worth of serialized bits.
// When two properly framed bytes arrive, that's when we drive the bus.
//
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// | 1 | h | h | h | h | h | h | h | h | 0 | 1 | l | l | l | l | l | l | l | l | 0 |
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// | | | |
// \ \ / /
// \ \ / /
// \ \ / /
// | |
// V 16-bit Wishbone DAT_O Port V
//
// Note that both bits AND bytes are sent little-endian: bit 0 of the low byte first.
module ipa(
input clk_i,
input reset_i,
input cyc_i,
output ack_o,
output [15:0] dat_o,
input txd_i,
input txc_i
);
reg [19:0] bits_received;
reg txc_r;
reg ack_o;
reg [15:0] dat_o;
wire sample = txc_r & ~txc_i;
wire framed = bits_received[19]
& ~bits_received[10]
& bits_received[9]
& ~bits_received[0];
always @(posedge clk_i) begin
bits_received <= bits_received;
txc_r <= txc_i;
ack_o <= 0;
dat_o <= 0;
if(reset_i) begin
bits_received <= ~0;
txc_r <= 0;
end
else begin
if(sample) begin
bits_received <= {txd_i, bits_received[19:1]};
end
if(framed) begin
bits_received <= ~0;
if(cyc_i) begin
ack_o <= 1;
dat_o <= {bits_received[18:11], bits_received[8:1]};
end
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/);
// verilator lint_off WIDTH
wire [1:0] bug729_au = ~0;
wire signed [1:0] bug729_as = ~0;
wire [2:0] bug729_b = ~0;
// the $signed output is unsigned because the input is unsigned; the signedness does not change.
wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0
wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0
wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1
wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1
wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0
wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0
wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1
wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1
wire [3:0] bug733_a = 4'b0010;
wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned
wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111
wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111
wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111
// When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign
wire [3:0] bug733_qu = 2'sb11; // 4'b1111
wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111
reg signed [32:0] bug349_s;
reg signed [32:0] bug349_u;
wire signed [1:0] sb11 = 2'sb11;
wire [3:0] subout_u;
sub sub (.a(2'sb11), .z(subout_u));
initial `checkh(subout_u, 4'b1111);
wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111;
initial `checkh(cond_a, 6'b111111);
wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
initial `checkh(cond_b, 6'b111111);
initial begin
// verilator lint_on WIDTH
`checkh(bug729_yuu, 1'b0);
`checkh(bug729_ysu, 1'b0);
`checkh(bug729_yus, 1'b1);
`checkh(bug729_yss, 1'b1);
`checkh(bug729_zuu, 1'b0);
`checkh(bug729_zsu, 1'b0);
`checkh(bug729_zus, 1'b1);
`checkh(bug729_zss, 1'b1);
`checkh(bug733_yu, 4'b1111);
`checkh(bug733_ys, 4'b1111);
`checkh(bug733_zu, 4'b1111);
`checkh(bug733_zs, 4'b1111);
`checkh(bug733_qu, 4'b1111);
`checkh(bug733_qs, 4'b1111);
// verilator lint_off WIDTH
bug349_s = 4'sb1111;
`checkh(bug349_s, 33'h1ffffffff);
bug349_u = 4'sb1111;
`checkh(bug349_u, 33'h1ffffffff);
bug349_s = 4'sb1111 - 1'b1;
`checkh(bug349_s,33'he);
bug349_s = 4'sb1111 - 5'b00001;
`checkh(bug349_s,33'he);
case (2'sb11)
4'b1111: ;
default: $stop;
endcase
case (sb11)
4'b1111: ;
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input [3:0] a,
output [3:0] z);
assign z = a;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[200005]; int colour[200005]; long long dp[200005]; long long ans[200005]; void dfs(long long source, long long p) { dp[source] = colour[source]; for (int i = 0; i < v[source].size(); ++i) { if (v[source][i] == p) continue; dfs(v[source][i], source); dp[source] += max((long long)0, dp[v[source][i]]); } } void dfs2(long long source, long long p) { ans[source] = dp[source]; for (int i = 0; i < v[source].size(); ++i) { if (v[source][i] == p) continue; dp[source] -= max((long long)0, dp[v[source][i]]); dp[v[source][i]] += max((long long)0, dp[source]); dfs2(v[source][i], source); dp[v[source][i]] -= max((long long)0, dp[source]); dp[source] += max((long long)0, dp[v[source][i]]); } } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long n, x, y; cin >> n; for (int i = 1; i <= n; ++i) { cin >> colour[i]; if (!colour[i]) colour[i] = -1; ans[i] = 0; } for (int i = 0; i < n - 1; ++i) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } dfs(1, 0); dfs2(1, 0); for (int i = 1; i <= n; ++i) { cout << ans[i] << ; } cout << n ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// wishBoneBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "wishBoneBus_h.v"
module wishBoneBI (
address, dataIn, dataOut, writeEn,
strobe_i,
ack_o,
clk, rst,
hostControlSel,
hostRxFifoSel, hostTxFifoSel,
slaveControlSel,
slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
hostSlaveMuxSel,
dataFromHostControl,
dataFromHostRxFifo,
dataFromHostTxFifo,
dataFromSlaveControl,
dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
dataFromHostSlaveMux
);
input clk;
input rst;
input [7:0] address;
input [7:0] dataIn;
output [7:0] dataOut;
input strobe_i;
output ack_o;
input writeEn;
output hostControlSel;
output hostRxFifoSel;
output hostTxFifoSel;
output slaveControlSel;
output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
output hostSlaveMuxSel;
input [7:0] dataFromHostControl;
input [7:0] dataFromHostRxFifo;
input [7:0] dataFromHostTxFifo;
input [7:0] dataFromSlaveControl;
input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
input [7:0] dataFromHostSlaveMux;
wire clk;
wire rst;
wire [7:0] address;
wire [7:0] dataIn;
reg [7:0] dataOut;
wire writeEn;
wire strobe_i;
reg ack_o;
reg hostControlSel;
reg hostRxFifoSel;
reg hostTxFifoSel;
reg slaveControlSel;
reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
reg hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
wire [7:0] dataFromHostSlaveMux;
//internal wires and regs
reg ack_delayed;
reg ack_immediate;
//address decode and data mux
always @(address or
dataFromHostControl or
dataFromHostRxFifo or
dataFromHostTxFifo or
dataFromSlaveControl or
dataFromEP0RxFifo or
dataFromEP1RxFifo or
dataFromEP2RxFifo or
dataFromEP3RxFifo or
dataFromHostSlaveMux or
dataFromEP0TxFifo or
dataFromEP1TxFifo or
dataFromEP2TxFifo or
dataFromEP3TxFifo)
begin
hostControlSel <= 1'b0;
hostRxFifoSel <= 1'b0;
hostTxFifoSel <= 1'b0;
slaveControlSel <= 1'b0;
slaveEP0RxFifoSel <= 1'b0;
slaveEP0TxFifoSel <= 1'b0;
slaveEP1RxFifoSel <= 1'b0;
slaveEP1TxFifoSel <= 1'b0;
slaveEP2RxFifoSel <= 1'b0;
slaveEP2TxFifoSel <= 1'b0;
slaveEP3RxFifoSel <= 1'b0;
slaveEP3TxFifoSel <= 1'b0;
hostSlaveMuxSel <= 1'b0;
case (address & `ADDRESS_DECODE_MASK)
`HCREG_BASE : begin
hostControlSel <= 1'b1;
dataOut <= dataFromHostControl;
end
`HCREG_BASE_PLUS_0X10 : begin
hostControlSel <= 1'b1;
dataOut <= dataFromHostControl;
end
`HOST_RX_FIFO_BASE : begin
hostRxFifoSel <= 1'b1;
dataOut <= dataFromHostRxFifo;
end
`HOST_TX_FIFO_BASE : begin
hostTxFifoSel <= 1'b1;
dataOut <= dataFromHostTxFifo;
end
`SCREG_BASE : begin
slaveControlSel <= 1'b1;
dataOut <= dataFromSlaveControl;
end
`SCREG_BASE_PLUS_0X10 : begin
slaveControlSel <= 1'b1;
dataOut <= dataFromSlaveControl;
end
`EP0_RX_FIFO_BASE : begin
slaveEP0RxFifoSel <= 1'b1;
dataOut <= dataFromEP0RxFifo;
end
`EP0_TX_FIFO_BASE : begin
slaveEP0TxFifoSel <= 1'b1;
dataOut <= dataFromEP0TxFifo;
end
`EP1_RX_FIFO_BASE : begin
slaveEP1RxFifoSel <= 1'b1;
dataOut <= dataFromEP1RxFifo;
end
`EP1_TX_FIFO_BASE : begin
slaveEP1TxFifoSel <= 1'b1;
dataOut <= dataFromEP1TxFifo;
end
`EP2_RX_FIFO_BASE : begin
slaveEP2RxFifoSel <= 1'b1;
dataOut <= dataFromEP2RxFifo;
end
`EP2_TX_FIFO_BASE : begin
slaveEP2TxFifoSel <= 1'b1;
dataOut <= dataFromEP2TxFifo;
end
`EP3_RX_FIFO_BASE : begin
slaveEP3RxFifoSel <= 1'b1;
dataOut <= dataFromEP3RxFifo;
end
`EP3_TX_FIFO_BASE : begin
slaveEP3TxFifoSel <= 1'b1;
dataOut <= dataFromEP3TxFifo;
end
`HOST_SLAVE_CONTROL_BASE : begin
hostSlaveMuxSel <= 1'b1;
dataOut <= dataFromHostSlaveMux;
end
default:
dataOut <= 8'h00;
endcase
end
//delayed ack
always @(posedge clk) begin
ack_delayed <= strobe_i;
end
//immediate ack
always @(strobe_i) begin
ack_immediate <= strobe_i;
end
//select between immediate and delayed ack
always @(writeEn or address or ack_delayed or ack_immediate) begin
if (writeEn == 1'b0 &&
(address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
begin
ack_o <= ack_delayed & ack_immediate;
end
else
begin
ack_o <= ack_immediate;
end
end
endmodule
|
module risc(address, rw, data, reset, clk);
output [15:0] address;
output rw;
inout [15:0] data;
input clk,reset;
wire [15:0] datain, dataout,a,b,ir0q,ir1q,aluad,alubd,pc,
readDataA, readDataB,r2q ;
wire [3:0] readAddrA, readAddrB, writeAddress, flags,aluf ;
wire [1:0] selA, selB ;
tsbuf iobuf (dataout, data, datain, rw);
/* Instruction Pipline registers */
reg16 ir0(datain, ir0q, clk, clrIr0);
reg16 ir1(ir0q, ir1q, clk, clrR);
/* General data registers */
reg16c r2(dataout, r2q, clk, wrAddr, clrR); // addressing register
regArray ra (readDataA, readDataB, readAddrA, readAddrB, writeAddress,
dataout, clk);
cntr16 programCounter (dataout, pc, clk, dojump, clrR);
mux4 muxa (a, datain, pc, r2q, readDataA, selA);
mux4 muxb (b, datain, pc, r2q, readDataB, selB);
/* data pipeline registers */
/* in out clock clear */
reg16 regA (a , aluad, clk, clrR);
reg16 regB (b , alubd, clk, clrR);
alu al (aluad,alubd,aluf,dataout,zero,parity,carry);
freg fr (dataout[15], carry, parity, zero, flags, clk, gate, clrR);
/* address select */
mux2 addrMux(address, pc, r2q, sel_addr_reg);
idec decoder(aluf,readAddrA,readAddrB, writeAddress,selA,selB,clrR,
clrIr0, gate, rw, sel_addr_reg, dojump, wrAddr,
ir0q,ir1q,flags,reset);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const long long MOD = 1e9 + 7; long long s, x; int a[50], n, ans0[1 << 21], ans1[1 << 21]; void work(int* ans, int s, int t) { int len = (t - s + 1); for (int i = 0; i < (1 << len); i++) { int tem = 0; for (int j = 1; j <= len; j++) if ((i >> (j - 1)) & 1) { if (a[s + j - 1] == 0) tem += 1 << j; if (a[s + j - 1] == 1) tem += 1 << (j - 1); } else { if (a[s + j - 1] == 0) tem += 0; if (a[s + j - 1] == 1) tem += 1 << (j - 1); } ans[++ans[0]] = tem; } } int main() { cin >> s >> x; n = 0; long long pp = x; while (pp > 0) { a[++n] = pp & 1; pp = pp / 2; } int qq = 0, t = 0; pp = s; while (pp > 0) { qq++; pp /= 2; } n = max(n, qq); t = n / 2; work(ans0, 1, t); work(ans1, t + 1, n); sort(ans0 + 1, ans0 + ans0[0] + 1); long long ans = 0; for (int i = 1; i <= ans1[0]; i++) { long long tem = s - (((long long)ans1[i]) << t); ans += upper_bound(ans0 + 1, ans0 + ans0[0] + 1, tem) - lower_bound(ans0 + 1, ans0 + ans0[0] + 1, tem); } if ((s xor 0) == x) ans -= 2; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; map<long long, int> mark; int32_t main() { int n; scanf( %d , &n); set<long long> s; for (int i = 0; i < n; i++) { int x; scanf( %d , &x); mark[x]++; s.insert(x); } int p = 0; long long MX = 0; while (s.size()) { long long u = *s.begin(); ((MX) = max((MX), (u))); mark[u + 1] += mark[u] / 2; if (mark[u + 1]) s.insert(u + 1); if (mark[u] % 2) p--; s.erase(s.begin()); } return cout << MX + p + 1 << endl, 0; }
|
/*
* In The Name Of God
* ========================================
* [] File Name : way_t.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Tue, Mar 31, 2015 10:56:44 PM
*
* [] Created By : Parham Alvani ()
* =======================================
*/
`timescale 1 ns/100 ps
module way_t;
reg [0:15] data_in = 16'h0f0f;
reg [0:4] tag;
reg enable = 1'b0;
reg write = 1'b0;
reg [0:1] word;
reg cmp;
reg valid_in;
reg rst;
wire [0:15] data_out;
wire [0:4] tag_out;
wire hit;
wire dirty;
wire valid;
wire ack;
initial begin
$dumpfile("way.vcd");
$dumpvars(0, way_t);
enable <= 0;
rst <= 0;
word <= 2'b11;
valid_in <= 1'b1;
data_in <= 16'h0f0f;
tag <= 5'b11101;
#5
enable <= 1;
write <= 1;
cmp <= 0;
#5
enable <= 0;
#5
enable <= 1;
write <= 0;
cmp <= 1;
#5
enable <= 0;
write <= 0;
cmp <= 0;
#5
enable <= 1;
rst <= 1;
wait (ack) begin
end
#5
rst <= 0;
enable <= 0;
#5
enable <= 1;
write <= 0;
cmp <= 1;
#10
$stop;
end
way wy(enable, word, cmp, write, rst, tag, data_in,
valid_in, hit, dirty, tag_out, data_out, valid, ack);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[4], b[4]; int get(int *a) { int ans; cout << ? << a[0] << << a[1] << << a[2] << << a[3] << endl; cin >> ans; return ans; } int get1(int a, int b, int c, int d) { int ans; cout << ? << a << << b << << c << << d << endl; cin >> ans; return ans; } void solve(int *a) { int l = a[0], r = a[2], mid; while (l < r) { mid = (l + r) / 2; a[2] = mid; if (get(a)) { r = mid; } else { l = mid + 1; } } a[2] = r; l = a[0], r = a[2]; while (l < r) { mid = (l + r) / 2; a[0] = mid + 1; if (get(a)) { l = mid + 1; } else { r = mid; } } a[0] = l; l = a[1], r = a[3]; while (l < r) { mid = (l + r) / 2; a[3] = mid; if (get(a)) { r = mid; } else { l = mid + 1; } } a[3] = r; l = a[1], r = a[3]; while (l < r) { mid = (l + r) / 2; a[1] = mid + 1; if (get(a)) { l = mid + 1; } else { r = mid; } } a[1] = r; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; b[0] = b[1] = a[0] = a[1] = 1; a[2] = a[3] = b[2] = b[3] = n; solve(a); if (a[2] != n && get1(a[2] + 1, 1, n, n)) { b[0] = a[2] + 1; } else if (a[3] != n && get1(1, a[3] + 1, n, n)) { b[1] = a[3] + 1; } else if (a[0] != 1 && get1(1, 1, a[0] - 1, n)) { b[2] = a[0] - 1; } else if (a[1] != 1 && get1(1, 1, n, a[1] - 1)) { b[3] = a[1] - 1; } solve(b); cout << ! ; for (int i = 0; i < 4; i++) { cout << a[i] << ; } for (int i = 0; i < 4; i++) { cout << b[i] << ; } return 0; }
|
module register(ridx, widx, wdata, we, clk, reset, rdata);
// Inputs:
input wire [4:0] ridx; // Read index
input wire [4:0] widx; // Write index
input wire [31:0] wdata;// Input data
input wire we; // Write enable
input wire clk; // Clock
input wire reset; // Reset
// Outputs:
output wire [31:0] rdata;
// Internal State/Storage
reg [31:0] mem [31:0]; // 32-bit array (mem) repeated 32 times
reg [31:0] i; // Counter for for loop
// Helper task to reset all reg entries to 0
task resetReg;
begin
for ( i = 0; i < 32; i = i + 1) begin
mem[i] = 32'b0;
end
end
endtask
// Start all of the entries zeroed out.
initial begin
resetReg;
end
// Continuously assign the read port to the selected read address
assign rdata = mem[ridx];
// Monitor for posedge clk and write as appropriate
always @ (posedge clk) begin
if (reset) begin
resetReg;
end
// Otherwise perform synchronous write of data is write is enabled
else begin
if (we & (widx != 32'b0)) begin
mem[widx] <= wdata;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string str; cin >> str; long long count = 0, count2 = 0; for (int i = 0; i < n; i++) { if (str[i] == < ) { count++; } else { break; } } for (int i = n - 1; i >= 0; i--) { if (str[i] == > ) { count2++; } else { break; } } cout << min(count, count2) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.14159265359; const long long MOD = (long long)1e9 + 7; const long long MAXN = (long long)2e3 + 10; const long long INF = (long long)2242545357980376863; const long double EPS = (long double)1e-8; long long dp[MAXN][2048]; long long pw[MAXN], cnt[MAXN]; long long a[MAXN]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); pw[0] = 1; for (int i = 1; i < MAXN; i++) pw[i] = (pw[i - 1] << 1) % MOD; long long n, k; cin >> n >> k; k = (1ll << k); for (int i = 1; i <= n; i++) cin >> a[i]; long long c0 = 0; for (int i = n; i >= 0; i--) { cnt[i] = c0; if (a[i] == 0) c0++; } if (a[1] == 2) { dp[1][2] = 1; } if (a[1] == 4) { dp[1][4] = 1; } if (a[1] == 0) { dp[1][2] = dp[1][4] = 1; } long long ans = 0; for (int i = 1; i < n; i++) { for (int j = 2; j < 2048; j++) { if (dp[i][j] == 0) continue; long long nx = a[i + 1]; if (nx != 4) { long long sm = j + 2; if (sm >= k) { ans += (pw[cnt[i + 1]] * dp[i][j]); ans %= MOD; } else { dp[i + 1][sm] += dp[i][j]; dp[i + 1][sm] %= MOD; } } if (nx != 2) { if (j % 4 == 2) { dp[i + 1][4] += dp[i][j]; } else { long long sm = j + 4; if (sm >= k) { ans += (pw[cnt[i + 1]] * dp[i][j]); ans %= MOD; } else { dp[i + 1][sm] += dp[i][j]; dp[i + 1][sm] %= MOD; } } } } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O22AI_PP_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_PP_BLACKBOX_V
|
`timescale 1ns/1ns
// iverilog fp16baddsub.v fp16baddsub_test.v
module FP16BAddSub_Test;
reg clk, rst;
reg [15:0] s0_arg_0;
reg [15:0] s0_arg_1;
reg s0_arg_2;
wire [15:0] s0_ret_0;
wire [15:0] s0_ret_1;
wire s0_ret_2;
wire s0_ret_3;
reg [15:0] s1_arg_0;
reg [15:0] s1_arg_1;
reg s1_arg_2;
reg s1_arg_3;
wire s1_ret_0;
wire s1_ret_1;
wire [14:0] s1_ret_2;
wire [14:0] s1_ret_3;
wire [7:0] s1_ret_4;
wire s1_ret_5;
wire s1_ret_6;
reg s2_arg_0;
reg s2_arg_1;
reg [14:0] s2_arg_2;
reg [14:0] s2_arg_3;
reg [7:0] s2_arg_4;
reg s2_arg_5;
reg s2_arg_6;
wire [15:0] s2_ret_0;
wire s2_ret_1;
wire s2_ret_2;
wire [7:0] s2_ret_3;
wire s2_ret_4;
wire s2_ret_5;
reg [15:0] s3_arg_0;
reg s3_arg_1;
reg s3_arg_2;
reg [7:0] s3_arg_3;
reg s3_arg_4;
reg s3_arg_5;
wire [14:0] s3_ret_0;
wire s3_ret_1;
wire s3_ret_2;
wire [7:0] s3_ret_3;
wire s3_ret_4;
wire s3_ret_5;
wire s3_ret_6;
reg [14:0] s4_arg_0;
reg s4_arg_1;
reg s4_arg_2;
reg [7:0] s4_arg_3;
reg s4_arg_4;
reg s4_arg_5;
reg s4_arg_6;
wire [15:0] s4_ret_0;
reg xs;
reg [7:0] xe;
reg [6:0] xf;
reg ys;
reg [7:0] ye;
reg [6:0] yf;
reg is_sub;
wire rs;
wire [7:0] re;
wire [6:0] rf;
assign rs = s4_ret_0[15:15];
assign re = s4_ret_0[14:7];
assign rf = s4_ret_0[6:0];
FP16BAddSubS0Of5
inst_0(.clk(clk), .rst(rst),
.arg_0(s0_arg_0), .arg_1(s0_arg_1), .arg_2(s0_arg_2),
.ret_0(s0_ret_0), .ret_1(s0_ret_1), .ret_2(s0_ret_2), .ret_3(s0_ret_3));
FP16BAddSubS1Of5
inst_1(.clk(clk), .rst(rst),
.arg_0(s1_arg_0), .arg_1(s1_arg_1), .arg_2(s1_arg_2), .arg_3(s1_arg_3),
.ret_0(s1_ret_0), .ret_1(s1_ret_1), .ret_2(s1_ret_2), .ret_3(s1_ret_3), .ret_4(s1_ret_4), .ret_5(s1_ret_5), .ret_6(s1_ret_6));
FP16BAddSubS2Of5
inst_2(.clk(clk), .rst(rst),
.arg_0(s2_arg_0), .arg_1(s2_arg_1), .arg_2(s2_arg_2), .arg_3(s2_arg_3), .arg_4(s2_arg_4), .arg_5(s2_arg_5), .arg_6(s2_arg_6),
.ret_0(s2_ret_0), .ret_1(s2_ret_1), .ret_2(s2_ret_2), .ret_3(s2_ret_3), .ret_4(s2_ret_4), .ret_5(s2_ret_5));
FP16BAddSubS3Of5
inst_3(.clk(clk), .rst(rst),
.arg_0(s3_arg_0), .arg_1(s3_arg_1), .arg_2(s3_arg_2), .arg_3(s3_arg_3), .arg_4(s3_arg_4), .arg_5(s3_arg_5),
.ret_0(s3_ret_0), .ret_1(s3_ret_1), .ret_2(s3_ret_2), .ret_3(s3_ret_3), .ret_4(s3_ret_4), .ret_5(s3_ret_5), .ret_6(s3_ret_6));
FP16BAddSubS4Of5
inst_4(.clk(clk), .rst(rst),
.arg_0(s4_arg_0), .arg_1(s4_arg_1), .arg_2(s4_arg_2), .arg_3(s4_arg_3), .arg_4(s4_arg_4), .arg_5(s4_arg_5), .arg_6(s4_arg_6),
.ret_0(s4_ret_0));
always @(s0_ret_0 or s0_ret_1 or s0_ret_2 or s0_ret_3) begin
s1_arg_0 <= s0_ret_0;
s1_arg_1 <= s0_ret_1;
s1_arg_2 <= s0_ret_2;
s1_arg_3 <= s0_ret_3;
$display("S0: %d %d %d %d", s0_ret_0, s0_ret_1, s0_ret_2, s0_ret_3);
end
always @(s1_ret_0 or s1_ret_1 or s1_ret_2 or s1_ret_3 or s1_ret_4 or s1_ret_5 or s1_ret_6) begin
s2_arg_0 <= s1_ret_0;
s2_arg_1 <= s1_ret_1;
s2_arg_2 <= s1_ret_2;
s2_arg_3 <= s1_ret_3;
s2_arg_4 <= s1_ret_4;
s2_arg_5 <= s1_ret_5;
s2_arg_6 <= s1_ret_6;
$display("S1: %d %d %d %d %d %d %d", s1_ret_0, s1_ret_1, s1_ret_2, s1_ret_3, s1_ret_4, s1_ret_5, s1_ret_6);
end
always @(s2_ret_0 or s2_ret_1 or s2_ret_2 or s2_ret_3 or s2_ret_4 or s2_ret_5) begin
s3_arg_0 <= s2_ret_0;
s3_arg_1 <= s2_ret_1;
s3_arg_2 <= s2_ret_2;
s3_arg_3 <= s2_ret_3;
s3_arg_4 <= s2_ret_4;
s3_arg_5 <= s2_ret_5;
$display("S2: %d %d %d %d %d %d", s2_ret_0, s2_ret_1, s2_ret_2, s2_ret_3, s2_ret_4, s2_ret_5);
end
always @(s3_ret_0 or s3_ret_1 or s3_ret_2 or s3_ret_3 or s3_ret_4 or s3_ret_5 or s3_ret_6) begin
s4_arg_0 <= s3_ret_0;
s4_arg_1 <= s3_ret_1;
s4_arg_2 <= s3_ret_2;
s4_arg_3 <= s3_ret_3;
s4_arg_4 <= s3_ret_4;
s4_arg_5 <= s3_ret_5;
s4_arg_6 <= s3_ret_6;
$display("S3: %d %d %d %d %d %d", s3_ret_0, s3_ret_1, s3_ret_2, s3_ret_3, s3_ret_4, s3_ret_5, s3_ret_6);
end
always @(s4_ret_0) begin
end
always @(xs or xe or xf or ys or ye or yf or is_sub) begin
s0_arg_0 = {xs, xe, xf};
s0_arg_1 = {ys, ye, yf};
s0_arg_2 = is_sub;
end
initial begin
// 0.0 + 0.0
is_sub <= 0;
xs <= 0; xe <= 0; xf <= 0;
ys <= 0; ye <= 0; yf <= 0;
#1
$display("0.0+0.0= %d %s", s4_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// 1.0 + 1.0
is_sub <= 0;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("1.0+1.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 0) ? "OK" : "FAIL");
// 1.0 + 2.0
is_sub <= 0;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 128; yf <= 0;
#1
$display("1.0+2.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 64) ? "OK" : "FAIL");
// 2.0 + 1.0
is_sub <= 0;
xs <= 0; xe <= 128; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("2.0+1.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 64) ? "OK" : "FAIL");
// 2.0 - 1.0
is_sub <= 1;
xs <= 0; xe <= 128; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("2.0-1.0= %d %s", s4_ret_0, (rs == 0 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 2.0 + - 1.0
is_sub <= 0;
xs <= 0; xe <= 128; xf <= 0;
ys <= 1; ye <= 127; yf <= 0;
#1
$display("2.0 + -1.0= %d %s", s4_ret_0, (rs == 0 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 1.0 - 2.0
is_sub <= 1;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 128; yf <= 0;
#1
$display("1.0-2.0= %d %s", s4_ret_0, (rs == 1 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 2^-14 - 2.0
is_sub <= 1;
xs <= 0; xe <= 1; xf <= 64;
ys <= 0; ye <= 1; yf <= 63;
#1
$display("192/128 * 2^-127 - 191/64*2^127= %d %s", s4_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// Use this line to debug a specific case.
$display("%d %d %d", rs, re, rf);
end
endmodule // FP16BAddSub_Test
|
#include <bits/stdc++.h> using namespace std; int cnt[6], ans[100001]; pair<int, int> arr[100001]; bool given[100001]; string tshirt[6] = { S , M , L , XL , XXL , XXXL }; int match(string s) { for (int i = 0; i < 6; i++) { if (tshirt[i] == s) return i; } } void convert(int ind, string s) { string tmp; bool flag = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == , ) { flag = 1; arr[ind].first = match(tmp); tmp.clear(); } else tmp.push_back(s[i]); } if (flag) { arr[ind].second = match(tmp); if (arr[ind].first > arr[ind].second) swap(arr[ind].first, arr[ind].second); } else { arr[ind].first = match(tmp); arr[ind].second = -1; } return; } bool cal_ans(int n) { for (int i = 0; i < n; i++) { if (arr[i].second == -1) { if (cnt[arr[i].first] == 0) return false; ans[i] = arr[i].first; cnt[arr[i].first]--; given[i] = 1; } } for (int j = 0; j < 5; j++) { for (int i = 0; i < n; i++) { if (given[i] == 0 and arr[i].first == j) { if (cnt[arr[i].first]) { cnt[arr[i].first]--; ans[i] = j; } else { if (cnt[arr[i].second]) { cnt[arr[i].second]--; ans[i] = arr[i].second; } else return false; } given[i] = 1; } } } return 1; } int main() { ios::sync_with_stdio(false); for (int i = 0; i < 6; i++) cin >> cnt[i]; int n; cin >> n; string s; for (int i = 0; i < n; i++) { cin >> s; convert(i, s); } if (cal_ans(n)) { cout << YES n ; for (int i = 0; i < n; i++) { cout << tshirt[ans[i]] << endl; } } else { cout << NO ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_TB_V
`define SKY130_FD_SC_LS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_TB_V
|
#include <bits/stdc++.h> using namespace std; struct Node { int l, r; long long maxi, lzy, maxiwthpre; }; struct Line { int l, r, v; bool operator<(Line L) const { return l < L.l; } }; int N, M; Node seg[800050]; long long pre[200005]; Line arr[200005]; void build(int l, int r, int idx) { seg[idx].l = l; seg[idx].r = r; seg[idx].maxi = seg[idx].maxiwthpre = LLONG_MIN >> 2; if (l == r) { return; } int mid = (l + r) >> 1; build(l, mid, 2 * idx); build(mid + 1, r, 2 * idx + 1); } void pd(int idx) { seg[2 * idx].maxi += seg[idx].lzy; seg[2 * idx].maxiwthpre += seg[idx].lzy; seg[2 * idx].lzy += seg[idx].lzy; seg[2 * idx + 1].maxi += seg[idx].lzy; seg[2 * idx + 1].maxiwthpre += seg[idx].lzy; seg[2 * idx + 1].lzy += seg[idx].lzy; seg[idx].lzy = 0; } void pu(int idx) { seg[idx].maxi = max(seg[2 * idx].maxi, seg[2 * idx + 1].maxi); seg[idx].maxiwthpre = max(seg[2 * idx].maxiwthpre, seg[2 * idx + 1].maxiwthpre); } void add(int l, int r, long long v, int idx) { if (seg[idx].l == l && seg[idx].r == r) { seg[idx].lzy += v; seg[idx].maxi += v; seg[idx].maxiwthpre += v; return; } int mid = (seg[idx].l + seg[idx].r) >> 1; if (seg[idx].lzy) { pd(idx); } if (r <= mid) { add(l, r, v, 2 * idx); } else if (l > mid) { add(l, r, v, 2 * idx + 1); } else { add(l, mid, v, 2 * idx); add(mid + 1, r, v, 2 * idx + 1); } pu(idx); } void setval(int p, long long v, int idx) { if (seg[idx].l == seg[idx].r) { seg[idx].maxi = v; seg[idx].maxiwthpre = v + pre[p]; return; } int mid = (seg[idx].l + seg[idx].r) >> 1; if (seg[idx].lzy) { pd(idx); } if (p <= mid) { setval(p, v, 2 * idx); } else { setval(p, v, 2 * idx + 1); } pu(idx); } long long query(int l, int r, int withpre, int idx) { if (seg[idx].l == l && seg[idx].r == r) { return withpre ? seg[idx].maxiwthpre : seg[idx].maxi; } int mid = (seg[idx].l + seg[idx].r) >> 1; if (seg[idx].lzy) { pd(idx); } if (r <= mid) { return query(l, r, withpre, 2 * idx); } else if (l > mid) { return query(l, r, withpre, 2 * idx + 1); } else { return max(query(l, mid, withpre, 2 * idx), query(mid + 1, r, withpre, 2 * idx + 1)); } } int main() { cin >> N >> M; for (int i = 1; i <= N; i++) { cin >> pre[i]; pre[i] += pre[i - 1]; } for (int i = 1; i <= M; i++) { cin >> arr[i].l >> arr[i].r >> arr[i].v; } sort(arr + 1, arr + 1 + M); build(0, 200000, 1); setval(0, 0, 1); for (int i = 1; i <= M; i++) { add(arr[i].r, 200000, arr[i].v, 1); long long n = query(arr[i].r, arr[i].r, 0, 1); if (arr[i].l != arr[i].r) { n = max(n, query(arr[i].l, arr[i].r - 1, 1, 1) - pre[arr[i].r] + arr[i].v); } n = max(n, query(0, arr[i].l - 1, 0, 1) - pre[arr[i].r] + pre[arr[i].l - 1] + arr[i].v); setval(arr[i].r, n, 1); } cout << seg[1].maxi << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int p = n - a[0]; for (int i = 1; i < n; i++) { if (i & 1) { a[i] -= p; a[i] += (n * 1000000); a[i] = a[i] % n; if (a[i] != i) { cout << No ; return 0; } } else { a[i] += p; a[i] %= n; if (a[i] != i) { cout << No ; return 0; } } } cout << Yes ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int n1 = n; int k1; int k[n + 1]; int pri[n + 1]; for (int i = 1; i <= n; i++) { k[i] = 0; pri[i] = 0; } int f = 0; std::vector<int> nhi; for (int j = 1; j <= n; j++) { f = 0; cin >> k1; int pr[k1 + 1]; for (int i = 1; i <= k1; i++) { cin >> pr[i]; } for (int i = 1; i <= k1; i++) { if (k[pr[i]] == 0) { k[pr[i]] = 1; pri[j] = 1; break; } } if (pri[j] == 0) { nhi.push_back(j); } } if (nhi.empty()) cout << OPTIMAL << n ; else { int g; for (int i = 1; i <= n; i++) { if (k[i] == 0) { g = i; break; } } cout << IMPROVE << n ; cout << nhi[0] << << g << n ; } } return 0; }
|
#include <bits/stdc++.h> const long double eps = 1e-9; using namespace std; template <class T> inline T MAX(const T &_a, const T &_b) { return ((_a > _b) ? _a : _b); } template <class T> inline T MIN(const T &_a, const T &_b) { return ((_a < _b) ? _a : _b); } template <class T> inline T MAX3(const T &_a, const T &_b, const T &_c) { return MAX(MAX(_a, _b), _c); } template <class T> inline T MIN3(const T &_a, const T &_b, const T &_c) { return MIN(MIN(_a, _b), _c); } template <class T> inline T MAX4(const T &_a, const T &_b, const T &_c, const T &_d) { return MAX(MAX3(_a, _b, _c), _d); } template <class T> inline T MIN4(const T &_a, const T &_b, const T &_c, const T &_d) { return MIN(MIN3(_a, _b, _c), _d); } template <class T> inline T ABS(const T &_a) { return ((_a < 0) ? -_a : _a); } template <class T> inline T SQR(const T &_a) { return _a * _a; } template <class T> inline T gcd(T _a, T _b) { for (T _r; (_r = _a % _b); _b = _r) _a = _b; return _b; } template <class T> inline T lcm(const T &_a, const T &_b) { return (_a / gcd(_a, _b)) * _b; } template <class T> inline bool BETW(const T &_a, const T &_b, const T &_c) { return (_a >= MIN(_b, _c) && _a <= MAX(_b, _c)); } template <class T> inline bool EXT(const T &_a, const T &_b, const T &_c) { return !BETW(_a, _b, _c); } const int MAXN = 100010, MAXL = 20; int N, father[MAXL][MAXN], level[MAXN], subTree[MAXN]; vector<int> adj[MAXN]; void dfs(int node, int prev) { int i; father[0][node] = prev; level[node] = level[prev] + 1; subTree[node] = 1; for (i = 0; i < ((int)adj[node].size()); i++) if (adj[node][i] != prev) { dfs(adj[node][i], node); subTree[node] += subTree[adj[node][i]]; } } inline int LCA(int a, int b) { int k; if (level[a] < level[b]) swap(a, b); k = MAXL - 1; while (level[a] > level[b]) { while (k && level[father[k][a]] < level[b]) k--; a = father[k][a]; } k = MAXL - 1; while (a != b) { while (k && father[k][a] == father[k][b]) k--; a = father[k][a]; b = father[k][b]; } return a; } inline int getFather(int a, int H) { for (int k = MAXL - 1; k >= 0; k--) if (H >= (1 << k)) { a = father[k][a]; H -= (1 << k); } return a; } int main() { int i, a, b, k, q, ab, x, y; scanf( %d , &N); for (i = 1; i < N; i++) { scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } dfs(1, 0); for (k = 1; k < MAXL; k++) for (i = 1; i <= N; i++) father[k][i] = father[k - 1][father[k - 1][i]]; scanf( %d , &q); while (q--) { scanf( %d%d , &a, &b); ab = LCA(a, b); if ((level[a] - level[ab] + level[b] - level[ab]) & 1) { puts( 0 ); continue; } if (level[a] < level[b]) swap(a, b); if (a == b) { printf( %d n , N); continue; } if (level[a] == level[b]) { x = getFather(a, level[a] - level[ab] - 1); y = getFather(b, level[a] - level[ab] - 1); printf( %d n , N - subTree[x] - subTree[y]); } else { x = getFather(a, (level[a] - level[ab] + level[b] - level[ab]) / 2 - 1); printf( %d n , subTree[father[0][x]] - subTree[x]); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<int> ed[2000]; int sho[1200][1200]; int col[1200]; int n, m; int makk[1200]; int sp[1200]; void dfs(int v, int ccc) { sp[v] = ccc; for (int a = 0; a < ed[v].size(); a++) { if (sp[ed[v][a]] == -1) dfs(ed[v][a], ccc); } } void getsho(int v) { int q[3000]; int dp[3000]; int c[3000]; for (int a = 0; a < n; a++) c[a] = -1; q[0] = v; dp[0] = 0; c[v] = 1; int bb = 0; int ee = 0; while (bb <= ee) { int vx = q[bb]; sho[v][vx] = dp[bb]; for (int a = 0; a < ed[vx].size(); a++) { if (c[ed[vx][a]] == -1) { int vu = ed[vx][a]; c[vu] = 1; ee++; q[ee] = vu; dp[ee] = dp[bb] + 1; } } bb++; } } int isok; void kolo(int v, int c) { col[v] = c; for (int a = 0; a < ed[v].size(); a++) { if (col[ed[v][a]] == c) isok = 0; else if (col[ed[v][a]] == -1) kolo(ed[v][a], 1 - c); } } int main() { cin >> n >> m; for (int a = 0; a < 1200; a++) makk[a] = 0; isok = 1; int x, y; for (int a = 0; a < n; a++) for (int b = 0; b < n; b++) sho[a][b] = 1000000; for (int a = 0; a < m; a++) { cin >> x >> y; ed[x - 1].push_back(y - 1); ed[y - 1].push_back(x - 1); } for (int a = 0; a < 1100; a++) col[a] = -1; kolo(0, 0); if (!isok) { cout << -1; return 0; } for (int a = 0; a < n; a++) sp[a] = -1; int ccc = -1; for (int a = 0; a < n; a++) { if (sp[a] == -1) { ccc++; dfs(a, ccc); } } for (int a = 0; a < n; a++) getsho(a); int mini = 0; for (int a = 0; a < n; a++) { for (int b = a + 1; b < n; b++) { if (sp[a] == sp[b] && sho[a][b] > makk[sp[a]] && sho[a][b] < 100000) makk[sp[a]] = sho[a][b]; } } int ss = 0; for (int a = 0; a < 1200; a++) ss += makk[a]; cout << ss; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; unsigned long long c; for (int i = 0; i < q; i++) { cin >> c; if ((c < 4) | (c % 2 != 0 & c < 13 & c != 9)) cout << -1 << endl; else { if (c % 2 != 0) cout << (c - 9) / 4 + 1 << endl; else cout << c / 4 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; pair<double, double> A[MAXN]; int n, r, ord[MAXN], st[MAXN]; bool comp(int a, int b) { if (A[a].first != A[b].first) return A[a].first < A[b].first; return A[a].second < A[b].second; } int ccw(pair<double, double> a, pair<double, double> b, pair<double, double> c) { double tmp = a.first * b.second + b.first * c.second + c.first * a.second - a.second * b.first - b.second * c.first - c.second * a.first; if (tmp > 0) return 1; if (tmp < 0) return -1; return 0; } int main() { scanf( %d , &n); int i, m, ni; for (i = 1; i <= n; i++) scanf( %lf%lf , &A[i].first, &A[i].second); ni = n; scanf( %d , &m); for (i = 1; i <= m; i++) scanf( %lf%lf , &A[n + i].first, &A[n + i].second); n += m; for (i = 1; i <= n; i++) ord[i] = i; sort(ord + 1, ord + n + 1, comp); st[++r] = ord[1]; st[++r] = ord[2]; for (i = 3; i <= n; i++) { while (r >= 2 && ccw(A[st[r - 1]], A[st[r]], A[ord[i]]) > 0) r--; st[++r] = ord[i]; } for (i = n - 1; i >= 1; i--) { while (r >= 2 && ccw(A[st[r - 1]], A[st[r]], A[ord[i]]) > 0) r--; st[++r] = ord[i]; } r--; for (i = 1; i <= r; i++) if (st[i] > ni) { printf( NO n ); return 0; } printf( YES n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; map<int, vector<int>> mappu; cin >> n >> m; for (long long i = (0); i < (m); i++) { int a, b; cin >> a >> b; mappu[a].push_back(b); mappu[b].push_back(a); } for (long long i = (1); i < (n + 1); i++) { mappu[i].push_back(i); sort(mappu[i].begin(), mappu[i].end()); } for (long long i = (1); i < (n + 1); i++) { for (long long j = (0); j < (mappu[i].size()); j++) { if (mappu[i] != mappu[mappu[i][j]]) { cout << NO ; return 0; } } } cout << YES ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_2_V
`define SKY130_FD_SC_LS__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int k, b, n; map<int, int>::iterator it; int main() { map<int, int> mp; while (scanf( %d%d%d , &k, &b, &n) != EOF) { mp.clear(); if (b == 0) { int a, sum = 0; long long res = 0; mp[0] = 1; for (int i = 1; i <= n; i++) { scanf( %d , &a); if (a) sum++; if (mp.find(sum) == mp.end()) mp[sum] = 1; else mp[sum]++; } for (it = mp.begin(); it != mp.end(); it++) { long long tmp = it->second; res += tmp * (tmp - 1) / 2; } cout << res << endl; } else { int a, ss = 0; long long res = 0, pre = 0; mp[0] = 1; for (int i = 1; i <= n; i++) { scanf( %d , &a); if (a) { ss += a; ss %= (k - 1); int ff = (ss - b + k - 1) % (k - 1); int st = mp.find(ff) == mp.end() ? 0 : mp[ff]; pre = st; res += st; if (mp.find(ss) == mp.end()) mp[ss] = 1; else mp[ss]++; } else { res += pre; mp[ss]++; } } cout << res << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int dig[15]; int qpow(int digit) { int a = 2, b = digit, ans = 1; while (b) { if (b & 1) ans *= a; a *= a; b >>= 1; } return ans; } int getDigit(int x) { int ans = 0; while (x) { x /= 10; ans++; } return ans; } void getHead(int x, int len) { int index = len; while (x) { dig[index--] = x % 10; x /= 10; } } int main() { int n; while (~scanf( %d , &n)) { int len = getDigit(n); int ans = 0; for (int i = 1; i <= len - 1; i++) ans += qpow(i); if (ans == 1) ans -= 1; getHead(n, len); for (int i = 1; i <= len; i++) { if (dig[i] > 7) { ans += qpow(len - i + 1); break; } else if (dig[i] == 7) { ans += qpow(len - i); if (i == len) ans += 1; } else if (dig[i] > 4) { ans += qpow(len - i); break; } else if (dig[i] == 4) { if (i == len) ans += 1; continue; } else break; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<char>> g; map<long long, bool> dp; void brute(int n, vector<int> &p) { int x = find(p.begin(), p.end(), -1) - p.begin(); if (x == int(p.size())) { vector<vector<char>> dp2(1 << n, vector<char>(n)); vector<int> pos1(n), pos2(n); for (int i = 0; i < int(p.size()); i++) { pos1[p[i]] = pos2[p[i]]; pos2[p[i]] = i; } for (int i = 0; i < int(n); i++) if (g[pos1[i]][pos2[i]]) dp2[1 << i][i] = true; for (int mask = 0; mask < int(1 << n); mask++) for (int i = 0; i < int(n); i++) if (dp2[mask][i]) { for (int j = 0; j < int(n); j++) if (!((mask >> j) & 1)) { dp2[mask | (1 << j)][j] |= (g[pos1[i]][pos1[j]] && g[pos2[i]][pos2[j]]); dp2[mask | (1 << j)][j] |= (g[pos1[i]][pos2[j]] && g[pos2[i]][pos1[j]]); } } for (int i = 0; i < int(n); i++) if (dp2[(1 << n) - 1][i]) { long long num = 0; for (int x : p) num = num * 6 + x; dp[num] = true; break; } return; } for (int y = x + 1; y < int(p.size()); ++y) if (p[y] == -1) { p[x] = p[y] = n; brute(n + 1, p); p[x] = p[y] = -1; } } bool dfs(vector<int> p) { vector<int> used(int(p.size()), -1); int cnt = 0; for (int i = 0; i < int(p.size()); i++) if (used[p[i]] == -1) used[p[i]] = cnt++; long long num = 0; for (int &x : p) { x = used[x]; num = num * 6 + x; } if (dp.count(num)) return dp[num]; bool res = false; vector<int> cur(cnt); for (int i = 0; i < int(p.size()); i++) ++cur[p[i]]; for (int i = 0; i < int(p.size()); i++) if (cur[p[i]] > 2) { int x = p[i]; for (int j = i + 1; j < int(p.size()); ++j) if (p[j] == p[i]) { p[i] = p[j] = cnt; if (dfs(p)) { res = true; break; } p[i] = p[j] = x; } break; } return dp[num] = res; } void brute2(int n, vector<int> &p) { int x = find(p.begin(), p.end(), -1) - p.begin(); if (x == int(p.size())) { dfs(p); return; } for (int i = 0; i < int(n + 1); i++) { for (int y = x + 1; y < int(p.size()); ++y) if (p[y] == -1) { p[x] = p[y] = i; brute2(max(n, i + 1), p); p[x] = p[y] = -1; } } } int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); g.resize(n, vector<char>(n)); for (int _ = 0; _ < int(m); _++) { int v, u; scanf( %d%d , &v, &u); --v, --u; g[v][u] = g[u][v] = 1; } vector<int> cur(n, -1); brute(0, cur); brute2(0, cur); vector<long long> fact(k + 1); fact[0] = 1; for (int i = 1; i <= k; ++i) fact[i] = fact[i - 1] * i; long long ans = 0; for (auto it : dp) if (it.second) { long long num = it.first; long long mx = 1; while (num) { mx = max(mx, num % 6 + 1); num /= 6; } if (mx <= k) { ans += fact[k] / fact[k - mx]; } } printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:18:23 04/20/2015
// Design Name:
// Module Name: pc_test_circuit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pc_test_circuit(
output [6:0] segdisp,
output [3:0] sel,
// output countornotdisp,
// output countindisp,
// output countin2disp,
input btnup,
input btndown,
input btnleft,
input btnright,
input btnrst,
input clock,
input [7:0] datain
);
wire btnupint, btndownint, btnleftint, btnrightint, btnrstint;
wire [15:0] curpc;
wire [15:0] dataint;
wire aloadint;
wire countornot;
wire countin;
// wire countin2;
wire slowclk2;
// Clock Slower for debouncer circuit.
wire slowclk;
clock_slower #(.WIDTH(19)) slowed_clock(.y(slowclk), .clk(clock));
// Clock Slower for counter circuit. ~1Hz
wire slowclk3;
clock_slower #(.WIDTH(26)) slowed_clock3(.y(slowclk3), .clk(clock));
// Debouncer for five different inputs.
debouncer up(.y(btnupint), .x(btnup), .clk(clock), .clken(slowclk));
debouncer down(.y(btndownint), .x(btndown), .clk(clock), .clken(slowclk));
debouncer left(.y(btnleftint), .x(btnleft), .clk(clock), .clken(slowclk));
debouncer right(.y(btnrightint), .x(btnright), .clk(clock), .clken(slowclk));
debouncer reset(.y(btnrstint), .x(btnrst), .clk(clock), .clken(slowclk));
// Wrap Program Counter
// Load Data
assign dataint = (btnleftint)?({datain,curpc[7:0]}):({curpc[15:8],datain});
assign aloadint = (btnleftint || btnrightint)?(1'b1):(1'b0);
// Use DFF for count and stop.
dff cntornot(.q(countornot), .data(countin), .clk(clock), .reset(btndownint), .set(btnupint));
assign countin = countornot;
// or outor(countin, btnupint, countin2);
// and inneroutand(countin2, ~btndownint, countornot);
// For viewing countornot
// assign countornotdisp = countornot;
// assign countindisp = countin;
// assign countin2disp = countin2;
and andpc_count(slowclk2, slowclk3, countornot);
pc_param #(.SIZE(16)) mypc(.Q(curpc), .clk(clock), .aload(aloadint), .D(dataint), .en(slowclk2), .rst(~btnrstint));
// Seven Segment Display Wrapper
seven_seg_wrapper segwrapper(.segdisplay(segdisp), .segselect(sel), .pcval(curpc), .clock(clock), .enable(slowclk));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ar[1000001], x, ars[1000001]; int main() { cin >> n >> x; for (int i = 0; i < n; i++) { cin >> ar[i]; ars[ar[i]]++; } long long ans = 0; for (int i = 0; i < n; i++) { ars[ar[i]]--; ans += (ars[(ar[i] ^ x)]); } cout << ans; return 0; }
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming decoder
*/
module decoder4to16 (in,out);
// Output signals representing the 11-bit decoded vector
output reg [15:1] out;
// Input signals representing the 15-bit input
input [3:0] in;
// Declare "reg" signals...
reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
// Invert the inputs...
in_bar=~in;
// Don't define out[0] because you don't wanna flip correct outputs
//out[0]=in_bar[0] & in_bar[1] & in_bar[2] & in_bar[3];
out[1]=in[0] & in_bar[1] & in_bar[2] & in_bar[3];
out[2]=in_bar[0] & in[1] & in_bar[2] & in_bar[3];
out[3]=in[0] & in[1] & in_bar[2] & in_bar[3];
out[4]=in_bar[0] & in_bar[1] & in[2] & in_bar[3];
out[5]=in[0] & in_bar[1] & in[2] & in_bar[3];
out[6]=in_bar[0] & in[1] & in[2] & in_bar[3];
out[7]=in[0] & in[1] & in[2] & in_bar[3];
out[8]=in_bar[0] & in_bar[1] & in_bar[2] & in[3];
out[9]=in[0] & in_bar[1] & in_bar[2] & in[3];
out[10]=in_bar[0] & in[1] & in_bar[2] & in[3];
out[11]=in[0] & in[1] & in_bar[2] & in[3];
out[12]=in_bar[0] & in_bar[1] & in[2] & in[3];
out[13]=in[0] & in_bar[1] & in[2] & in[3];
out[14]=in_bar[0] & in[1] & in[2] & in[3];
out[15]=in[0] & in[1] & in[2] & in[3];
end
endmodule
|
//-----------------------------------------------------------------------------
//-- Secuenciador de 2 estados a partir de dos registros de 4 bits con
//-- inicialización de carga
//-- (C) BQ. August 2015. Written by Juan Gonzalez (obijuan)
//-- Modified by Iñigo Muguruza Goenaga
//-----------------------------------------------------------------------------
//-- License GPL
//-----------------------------------------------------------------------------
module regreset4(input wire clk, output wire [3:0] data);
//-- Parametros del secuenciador:
parameter NP = 23; //-- Bits del prescaler
parameter INI0 = 4'b1001; //-- Valor inicial para el registro 0
parameter INI1 = 4'b0110; //-- Valor inicial para el registro 1
parameter INI2 = 4'b0101; //-- Valor inicial para el registro 0
parameter INI3 = 4'b0000; //-- Valor inicial para el registro 1
//-- Reloj a la salida del presacaler
wire clk_pres;
//-- Salida de los regitros
wire [3:0] dout0;
wire [3:0] dout1;
wire [3:0] dout2;
wire [3:0] dout3;
//-- Señal de inicializacion del reset
reg rst = 0;
//-- Inicializador
always @(posedge(clk_pres))
rst <= 1;
//-- Registro 0
register #(.INI(INI0))
REG0 (
.clk(clk_pres),
.rst(rst),
.din(dout3),
.dout(dout0)
);
//-- Registro 1
register #(.INI(INI1))
REG1 (
.clk(clk_pres),
.rst(rst),
.din(dout0),
.dout(dout1)
);
//-- Registro 1
register #(.INI(INI2))
REG2 (
.clk(clk_pres),
.rst(rst),
.din(dout1),
.dout(dout2)
);
//-- Registro 1
register #(.INI(INI3))
REG3 (
.clk(clk_pres),
.rst(rst),
.din(dout2),
.dout(dout3)
);
//-- Sacar la salida del registro 0 por la del componente
assign data = dout3;
//-- Prescaler
prescaler #(.N(NP))
PRES (
.clk_in(clk),
.clk_out(clk_pres)
);
endmodule
|
`timescale 1 ns / 1 ps
module gpio_level_trigger #
(
parameter integer GPIO_DATA_WIDTH = 16
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
inout wire [GPIO_DATA_WIDTH-1:0] gpio_data,
input wire soft_trig,
input wire [31:0] delay,
output wire trigger
);
reg [GPIO_DATA_WIDTH-1:0] int_data_reg [1:0];
reg triggered, int_trig_reg, int_trig_reg_next,out_trig, out_trig_next;
reg [31:0] counter, counter_next;
wire [GPIO_DATA_WIDTH-1:0] int_data_wire;
wire int_comp_wire;
genvar j;
generate
for(j = 0; j < GPIO_DATA_WIDTH; j = j + 1)
begin : GPIO
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I({(GPIO_DATA_WIDTH){1'b0}}), .T(1'b1));
end
endgenerate
assign int_comp_wire = counter < delay;
always @(posedge aclk)
begin
int_data_reg[0] <= int_data_wire;
int_data_reg[1] <= int_data_reg[0];
if(~aresetn)
begin
int_trig_reg <= 1'b0;
out_trig <= 1'b0;
counter <= 32'b0;
end
else
begin
int_trig_reg <= int_trig_reg_next;
out_trig <= out_trig_next;
counter <= counter_next;
end
end
always @*
begin
int_trig_reg_next = int_trig_reg;
out_trig_next = out_trig;
counter_next = counter;
if(soft_trig | int_data_reg[1][0:0])
int_trig_reg_next = 1'b1;
if ( int_comp_wire & int_trig_reg)
counter_next=counter + 1'b1;
if ( ~int_comp_wire)
out_trig_next = 1'b1;
end
assign trigger = out_trig;
assign s_axis_tready = ?m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_tagmem #(
parameter depth = 2,
parameter width = 2
) (
input sys_clk,
/* Primary port (read-write) */
input [depth-1:0] a,
input we,
input [width-1:0] di,
output [width-1:0] do,
/* Secondary port (read-only) */
input [depth-1:0] a2,
output [width-1:0] do2
);
reg [width-1:0] tags[0:(1 << depth)-1];
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
a_r <= a;
a2_r <= a2;
end
always @(posedge sys_clk) begin
if(we)
tags[a] <= di;
end
assign do = tags[a_r];
assign do2 = tags[a2_r];
// synthesis translate_off
integer i;
initial begin
for(i=0;i<(1 << depth);i=i+1)
tags[i] = 0;
end
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[500][500]; int d[500][500]; long long int ans[500]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int num; cin >> num; a[i][j] = num; d[i][j] = num; } } int b[n]; for (int i = 0; i < n; i++) { cin >> b[i]; b[i]--; } reverse(b, b + n); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { for (int s = 0; s < n; s++) { d[j][s] = min(d[j][s], d[j][b[i]] + d[b[i]][s]); } } for (int j = 0; j <= i; j++) { for (int s = 0; s <= i; s++) { ans[i] += d[b[j]][b[s]]; } } } reverse(ans, ans + n); for (int i = 0; i < n; i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, a, b; cin >> n >> a >> b; long long left = a; long long right = n - b - 1; long long end = max(left, right); long long ans = n - end; cout << ans; }
|
/**********************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name:tb_arbiter_for_mem
module function: find out errors in this module if any
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_mem();
//input
reg clk;
reg rst;
reg v_mem_download;
reg v_d_m_areg;
reg v_i_m_areg;
reg mem_access_done;
//output
wire ack_m_download;
wire ack_d_m_areg;
wire ack_i_m_areg;
wire v_m_download_m;
wire v_d_m_areg_m;
wire v_i_m_areg_m;
arbiter_for_mem uut (//input
.clk(clk),
.rst(rst),
.v_mem_download(v_mem_download),
.v_d_m_areg(v_d_m_areg),
.v_i_m_areg(v_i_m_areg),
.mem_access_done(mem_access_done),
//output
.ack_m_download(ack_m_download),
.ack_d_m_areg(ack_d_m_areg),
.ack_i_m_areg(ack_i_m_areg),
.v_m_download_m(v_m_download_m),
.v_d_m_areg_m(v_d_m_areg_m),
.v_i_m_areg_m(v_i_m_areg_m)
);
initial begin
clk=1'b0;
rst=1'b1;
v_mem_download=1'b0;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
end
`define clk_step # 14;
always #7 clk=~clk;
/////////////////////////////////////////////////////
/////////////////BEGIN TEST//////////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
///////////////////////////////////////////////////
/////////1st case mem ic and dc all are valid//////
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b1;
mem_access_done=1'b1;
`clk_step
//////////////////////////////////////////
//////////2nd case: dc and mem are valid//
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b1;
v_i_m_areg=1'b0;
mem_access_done=1'b1;
`clk_step
////////////////////////////////////////////////
////////3rd case: only mem valid ///////////////
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b0;
`clk_step
//mem done access in this cycle
v_mem_download=1'b1;
v_d_m_areg=1'b0;
v_i_m_areg=1'b0;
mem_access_done=1'b1;
`clk_step
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream &operator<<(ostream &os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } long long n, a[200005], c[200005], cc[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { cin >> n; for (long long i = 1; i < n + 1; i++) cin >> a[i]; for (long long i = 1; i < n + 1; i++) { long long k = 1; if (c[i - 1] == 1) k = 2; long long j = i; while (j <= n && a[j] == a[i]) c[j] = k, j++; i = j - 1; } if (c[1] == c[n] && a[1] != a[n]) { bool ok = false; for (long long i = 1; i < n; i++) { if (c[i] == c[i + 1]) { for (long long j = i + 1; j < n + 1; j++) { if (c[j] == 1) c[j] = 2; else c[j] = 1; } ok = true; break; } } if (!ok) c[n] = 3; } long long mx = 0; for (long long i = 1; i < n + 1; i++) mx = max(mx, c[i]); cout << mx << n ; for (long long i = 1; i < n + 1; i++) cout << c[i] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long getLCM(int a, int b) { int copyA = a, copyB = b; int r = a % b; while (r) { a = b; b = r; r = a % b; } int gcd = b; return 1LL * copyA * copyB / gcd; } int main() { int n, a, b, p, q; cin >> n >> a >> b >> p >> q; int divA = n / a; int divB = n / b; int divAB = n / getLCM(a, b); divA -= divAB; divB -= divAB; cout << 1LL * divA * p + 1LL * divB * q + 1LL * divAB * max(p, q); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mn = 1010000, mm = 10100; int n, m, i, j, k, t, a[mm], la[30], sa[30]; map<int, int> ans; char s[mn], c[30]; bool cmp(int i, int j) { return la[i] > la[j]; } int main() { scanf( %s , s + 1); n = strlen(s + 1); scanf( %d , &m); for (i = 1; i <= m; ++i) { scanf( %s , c + 1); k = strlen(c + 1); t = 0; for (j = 1; j <= k; ++j) t |= 1 << (c[j] - 97); ans[t] = 0, a[i] = t; } for (i = 0; i <= 25; ++i) sa[i] = i; for (i = 1; i <= n; ++i) { if (s[i] == s[i + 1]) continue; la[s[i] - 97] = i; k = s[i + 1] - 97, t = 0; sort(sa, sa + 26, cmp); for (j = 0; j <= 25; ++j) { if (!la[sa[j]] || sa[j] == k) break; t |= 1 << sa[j]; if (t == 5) { ++la[30]; } if (ans.count(t)) ++ans[t]; } } for (i = 1; i <= m; ++i) printf( %d n , ans[a[i]]); return 0; }
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ram1 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("ram1.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("ae"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(2048),
.C_READ_DEPTH_A(2048),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(2048),
.C_READ_DEPTH_B(2048),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 1.3396 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`include "alink_define.v"
module rx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_busy ,
input task_id_vld ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [31:0] timer_cnt ,
output rx_start ,
output rx_last ,
output rx_vld ,
output [31:0] rx_dat ,
input RX_P ,
input RX_N
);
parameter MY_RXID = 32'd0 ;
/*
>INPUT<
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[task_id_h _________________|0_|_________________________
task_id_l]
>OUTPUT<
__
rx_start __| |____________________________________________________________
__
rx_last ________________________________________________| |______________
_____________________________________________
rx_vld _____| |______________
_____ _____________________________________________ ______________
rx_dat _____|RXID |TaskID_H|TaskID_L|TIME |NONCE |______________
(word0) (word1) (word2) (word3) (word4)
*/
//-------------------------------------------------
// Receive 1/0/start/stop
//-------------------------------------------------
reg [3:0] report_p_d ;
reg [3:0] report_n_d ;
always@(posedge clk or posedge rst )begin
if( reg_flush || rst || ~reg_busy) begin
report_p_d <= 4'hf ;
report_n_d <= 4'hf ;
end else begin
report_p_d <= #1 {report_p_d[2:0], RX_P};
report_n_d <= #1 {report_n_d[2:0], RX_N};
end
end
wire rx_0 = ((~report_n_d[3]) && (&report_n_d[2:1])) && ~(|report_p_d[3:1]);
wire rx_1 = ((~report_p_d[3]) && (&report_p_d[2:1])) && ~(|report_n_d[3:1]);
wire rx_stop = (report_p_d[3]^report_n_d[3]) && (report_p_d[2]^report_n_d[2]) && (report_p_d[1]&report_n_d[1]) ;
/*
wire rx_stop = (&report_p_d[3:1] && ~report_n_d[3] && &report_n_d[2:1]) ||
(&report_n_d[3:1] && ~report_p_d[3] && &report_p_d[2:1]) ||
(~report_p_d[3] && &report_p_d[2:1] && ~report_n_d[3] && &report_n_d[2:1]) ;
*/
reg [31:0] nonce_buf;
always@(posedge clk)begin
if(rx_0)
nonce_buf <= #1 {1'b0, nonce_buf[31:1]};
else if(rx_1)
nonce_buf <= #1 {1'b1, nonce_buf[31:1]};
end
//-------------------------------------------------
// Receive TaskID&Timer
//-------------------------------------------------
reg [31:0] task_id_h_r ;
reg [31:0] task_id_l_r ;
always @ ( posedge clk ) begin
if( ~rx_vld && task_id_vld ) begin
task_id_h_r <= task_id_h ;
task_id_l_r <= task_id_l ;
end
end
//-------------------------------------------------
// Push Out
//-------------------------------------------------
reg [2:0] push_cnt ;
always @ ( posedge clk ) begin
if( rst )
push_cnt <= 3'b0 ;
else if( reg_busy && rx_stop && ~rx_vld)
push_cnt <= 3'b1 ;
else if( |push_cnt && push_cnt < `RX_DATA_LEN )
push_cnt <= push_cnt + 3'b1 ;
else
push_cnt <= 3'b0 ;
end
assign rx_vld = |push_cnt ;
assign rx_dat = push_cnt == 1 ? MY_RXID :
push_cnt == 2 ? task_id_h_r :
push_cnt == 3 ? task_id_l_r :
push_cnt == 4 ? timer_cnt : nonce_buf ;
assign rx_start = reg_busy && rx_stop && ~rx_vld ;
assign rx_last = push_cnt == `RX_DATA_LEN ;
endmodule
|
/*
Copyright 2011 David Fritz and Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
CACHE interface, which instantiates the SRAM interface
2.5.2011
*/
/*
this is as basic as it gets:
direct mapped cache
write allocate
write through
unified, single level
*/
module mod_memory_hierarchy(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, cpu_stall, sram_clk, sram_adv, sram_cre, sram_ce, sram_oe, sram_we, sram_lb, sram_ub, sram_data, sram_addr, mod_vga_sram_data, mod_vga_sram_addr, mod_vga_sram_read, mod_vga_sram_rdy, pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D);
input rst;
input clk;
input ie, de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
output cpu_stall;
/* sram signals */
output [31:0] mod_vga_sram_data;
input [31:0] mod_vga_sram_addr;
input mod_vga_sram_read;
output mod_vga_sram_rdy;
output sram_clk, sram_adv, sram_cre, sram_ce, sram_oe, sram_we, sram_lb, sram_ub;
output [23:1] sram_addr;
inout [15:0] sram_data;
output pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D;
wire cache_iwrite, cache_dwrite;
wire [10:0] cache_iaddr, cache_daddr;
wire [31:0] cache_iin, cache_din, cache_iout, cache_dout;
wire sram_nrdy, sram_ie, sram_de;
wire [1:0] sram_drw;
wire [31:0] sram_iaddr, sram_daddr, sram_din, sram_iout, sram_dout;
wire [31:0] tag_iin, tag_din, tag_iout, tag_dout;
/* cache */
cache_memory #(11, 32) data_array(clk, cache_iwrite, cache_dwrite, cache_iaddr, cache_daddr, cache_iin, cache_din, cache_iout, cache_dout);
cache_memory #(11, 32) tag_array (clk, cache_iwrite, cache_dwrite, cache_iaddr, cache_daddr, tag_iin, tag_din, tag_iout, tag_dout);
/* sram */
mod_sram sram_t(rst, clk, sram_ie, sram_de, sram_iaddr, sram_daddr, sram_drw, sram_din, sram_iout, sram_dout, sram_nrdy, sram_clk, sram_adv, sram_cre, sram_ce, sram_oe, sram_we, sram_lb, sram_ub, sram_data, sram_addr, mod_vga_sram_data, mod_vga_sram_addr, mod_vga_sram_read, mod_vga_sram_rdy);
/* state :
* 000 - idle / reading cache / cache hit
* 001 - servicing data miss
* 010 - servicing inst miss
* 011 - servicing data and instruction miss
* 101 - servicing data write
* 111 - servicing data write and instruction miss
*/
reg [3:0] state = 4'b0000;
wire [3:0] next_state;
wire ihit, dhit;
wire conflict;
/* performance counter logic */
assign pmc_cache_miss_I = state[3] & state[1];
assign pmc_cache_miss_D = state[3] & state[0];
assign pmc_cache_access_I = ie && next_state == 4'b0000;
assign pmc_cache_access_D = de && drw != 2'b00 && next_state == 4'b0000;
assign cpu_stall = next_state != 4'b0000;
assign cache_iwrite = state[1] && !conflict;
assign cache_dwrite = state[0];
assign cache_iaddr = iaddr[12:2];
assign cache_daddr = daddr[12:2];
assign cache_iin = sram_iout;
assign cache_din = state[2] ? din : sram_dout;
assign tag_iin = {13'b0000000000001, iaddr[31:13]};
assign tag_din = {13'b0000000000001, daddr[31:13]};
assign iout = state[1] ? sram_iout : cache_iout;
assign dout = state[0] ? sram_dout : cache_dout;
assign sram_ie = state[1] && !state[3];
assign sram_de = state[0] && !state[3];
assign sram_drw = drw;
assign sram_iaddr = iaddr;
assign sram_daddr = daddr;
assign sram_din = din;
assign ihit = tag_iout == tag_iin && !conflict;
assign dhit = tag_dout == tag_din;
assign conflict = (cache_iaddr == cache_daddr) && ie && de && drw != 2'b00;
assign next_state =
state == 4'b0000 && ((ihit && ie) || !ie) && !dhit && drw == 2'b10 && de ? 4'b0001 : /* data miss */
state == 4'b0000 && ((dhit && de && drw == 2'b10) || drw == 2'b00 || !de) && !ihit && ie ? 4'b0010 : /* instruction miss */
state == 4'b0000 && !ihit && !dhit && drw == 2'b10 && ie && de ? 4'b0011 : /* instruction and data miss */
state == 4'b0000 && ((ihit && ie) || !ie) && drw == 2'b01 && de ? 4'b0101 : /* data write */
state == 4'b0000 && !ihit && drw == 2'b01 && de && ie ? 4'b0111 : /* instruction miss and data write */
state != 4'b0000 && !state[3] && !sram_nrdy ? {1'b1,state[2:0]} :
state[3] ? 4'b0000 : state; /* returning from sram */
always @(posedge clk) begin
if (rst) begin
state <= 4'b0000;
end else begin
state <= next_state;
end
end
endmodule
/* inferred dual port ram as indicated by the xilinx xst guide */
module cache_memory(clk, wea, web, addra, addrb, dia, dib, doa, dob);
parameter ADDR_WIDTH = 0;
parameter DATA_WIDTH = 0;
parameter DEPTH = 1 << ADDR_WIDTH;
input clk;
input wea, web;
input [ADDR_WIDTH-1:0] addra, addrb;
input [DATA_WIDTH-1:0] dia, dib;
output reg [DATA_WIDTH-1:0] doa, dob;
reg [DATA_WIDTH-1:0] RAM [DEPTH-1:0];
always @(negedge clk) begin
if (wea)
RAM[addra] <= dia;
doa <= RAM[addra];
end
always @(negedge clk) begin
if (web)
RAM[addrb] <= dib;
dob <= RAM[addrb];
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bell.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bell (
address,
clock,
q);
input [14:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./audio_mifs/bell.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./audio_mifs/bell.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./audio_mifs/bell.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
parameter N = 1;
parameter PW = 104;
//clock, reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transactoin
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
//tie offs for Dv
assign dut_active = 1'b1;
assign clkout = clk2;
oh_fifo_cdc #(.DW(PW),
.DEPTH(16))
oh_fifo_cdc(.clk_in (clk1),
.clk_out (clk2),
/*AUTOINST*/
// Outputs
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.nreset (nreset),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.wait_in (wait_in));
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
`timescale 1 ns / 1 ps
module pulse_generator #
(
parameter CONTINUOUS = "FALSE"
)
(
input wire aclk,
input wire aresetn,
input wire [95:0] cfg,
output wire dout
);
reg int_dout_reg, int_dout_next;
reg [31:0] int_cntr_reg, int_cntr_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_dout_reg <= 1'b0;
int_cntr_reg <= 32'd0;
end
else
begin
int_dout_reg <= int_dout_next;
int_cntr_reg <= int_cntr_next;
end
end
always @*
begin
int_dout_next = int_dout_reg;
if(int_cntr_reg == cfg[31:0])
begin
int_dout_next = 1'b1;
end
if(int_cntr_reg == cfg[63:32])
begin
int_dout_next = 1'b0;
end
end
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS
always @*
begin
int_cntr_next = int_cntr_reg;
if(int_cntr_reg < cfg[95:64])
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = 32'd0;
end
end
end
else
begin : STOP
always @*
begin
int_cntr_next = int_cntr_reg;
if(int_cntr_reg < cfg[95:64])
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
end
end
endgenerate
assign dout = int_dout_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; long long fact[200005]; long long factinv[200005]; long long lgput(long long a, long long exp) { long long rz = 1; while (exp) { if (exp & 1LL) { --exp; rz = (rz * 1LL * a) % mod; } else { exp >>= 1LL; a = (a * 1LL * a) % mod; } } return rz; } long long comb(long long a, long long b) { return ((fact[a] * factinv[b]) % mod * factinv[a - b]) % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long k, mxc = 0, n, m, a, b, i, j = 0, t; cin >> n >> k; fact[0] = fact[1] = 1; for (i = 2; i <= n; ++i) fact[i] = (fact[i - 1] * i) % mod; for (i = 1; i <= n; ++i) factinv[i] = lgput(fact[i], mod - 2); factinv[0] = factinv[1]; if (k >= n) { cout << 0; return 0; } long long rz = 0; k = n - k; for (i = 0; i <= k; ++i) { if (i & 1) { rz = (rz + mod - comb(k, i) * lgput(k - i, n)) % mod; } else { rz = (rz + comb(k, i) * lgput(k - i, n)) % mod; } } rz = (rz * comb(n, n - k)) % mod; if (k != n) cout << (rz * 2LL) % mod; else cout << rz; return 0; }
|
#include <bits/stdc++.h> using namespace std; void out(long long arr[], long long length) { for (int i = 0; i < length; i++) cout << arr[i] << ; } int main() { int tt; cin >> tt; while (tt--) { int x1, y1, z1, x2, y2, z2, ans; cin >> x1 >> y1 >> z1; cin >> x2 >> y2 >> z2; if (y2 >= z1) { int t1; ans = (z1 * 2); int d1 = (y2 - z1); if ((d1 + x2) >= y1) cout << ans; else { int d2 = y1 - (d1 + x2); t1 = (min(d2, z2) * 2); ans = ans - t1; cout << ans; } } else if (y2 < z1) { int t1; ans = (y2 * 2); int d1 = (z1 - y2); if ((d1 + x1) >= z2) cout << ans; else { int d2 = z2 - (d1 + x1); t1 = (min(d2, z2) * 2); ans = ans - t1; cout << ans; } } cout << n ; } return 0; }
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Subsets and Splits
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