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/*
* In The Name Of God
* ========================================
* [] File Name : set_t.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Tue, Mar 31, 2015 9:13:43 AM
*
* [] Created By : Parham Alvani ()
* =======================================
*/
`timescale 1 ns/100 ps
module set_t;
reg [0:15] data_in;
reg [0:4] tag;
reg enable;
reg write;
reg [0:1] word;
reg cmp;
reg valid_in;
reg rst;
wire [0:15] data_out;
wire [0:4] tag_out;
wire hit;
wire dirty;
wire valid;
wire ack;
initial begin
$dumpfile("set.vcd");
$dumpvars(0, set_t);
enable = 0;
rst = 0;
word = 2'b11;
valid_in = 1'b1;
data_in = 16'b0000_1111_0000_1111;
tag = 5'b11101;
#5
write = 1;
cmp = 0;
enable = 1;
#5
enable = 0;
#5
enable = 1;
write = 0;
cmp = 1;
#5
enable = 0;
write = 0;
cmp = 0;
#5
enable = 1;
rst = 1;
#5
enable = 0;
#5
enable = 1;
write = 0;
cmp = 1;
#10
$stop;
end
set st(enable, word, cmp, write, rst, tag, data_in,
valid_in, hit, dirty, tag_out, data_out, valid, ack);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y, nand0_out, or0_out);
buf buf0 (Y , nand1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_V
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
`include "config.vh"
module bch_encode #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* First cycle */
input ce, /* Accept input word/cycle output word */
input [BITS-1:0] data_in, /* Input data */
output [BITS-1:0] data_out, /* Encoded output */
output first, /* First output cycle */
output reg last = 0, /* Last output cycle */
output data_bits, /* Current cycle is data */
output ecc_bits, /* Current cycle is ecc */
output ready /* Can accept data */
);
`include "bch.vh"
`include "bch_encode.vh"
localparam M = `BCH_M(P);
localparam TCQ = 1;
localparam ENC = encoder_poly(0);
/* Data cycles required */
localparam DATA_CYCLES = PIPELINE_STAGES + (`BCH_DATA_BITS(P) + BITS - 1) / BITS;
/* ECC cycles required */
localparam ECC_CYCLES = (`BCH_ECC_BITS(P) + BITS - 1) / BITS;
/* Total output cycles required (always at least 2) */
localparam CODE_CYCLES = DATA_CYCLES + ECC_CYCLES;
localparam signed SHIFT = BITS - `BCH_ECC_BITS(P);
localparam SWITCH = lfsr_count(M, DATA_CYCLES - 2);
localparam DONE = lfsr_count(M, CODE_CYCLES - 3);
localparam REM = `BCH_DATA_BITS(P) % BITS;
localparam RUNT = BITS - REM;
if (PIPELINE_STAGES > 1)
encode_only_supports_1_pipeline_stage u_eos1ps();
reg [`BCH_ECC_BITS(P)-1:0] lfsr = 0;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_first;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_next;
wire [BITS-1:0] data_in_pipelined;
wire [BITS-1:0] output_mask;
wire [BITS-1:0] shifted_in;
wire [M-1:0] count;
reg load_lfsr = 0;
reg busy = 0;
reg start_last = 0;
if (CODE_CYCLES < 3)
assign count = 0;
else
lfsr_counter #(M) u_counter(
.clk(clk),
.reset(ce && start),
.ce(ce && busy),
.count(count)
);
/*
* Shift input so that pad the start with 0's, and finish on the final
* bit.
*/
generate
if (REM) begin
reg [RUNT-1:0] runt = 0;
assign shifted_in = (data_in << RUNT) | (start ? 0 : runt);
always @(posedge clk)
if (ce)
runt <= #TCQ data_in << REM;
end else
assign shifted_in = data_in;
endgenerate
wire [BITS-1:0] lfsr_input;
assign lfsr_input = SHIFT > 0 ? (lfsr << SHIFT) : (lfsr >> -SHIFT);
if (`CONFIG_PIPELINE_LFSR) begin
wire [`BCH_ECC_BITS(P)-1:0] in_enc;
wire [`BCH_ECC_BITS(P)-1:0] in_enc_pipelined;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_enc;
lfsr_term #(`BCH_ECC_BITS(P), ENC, BITS) u_in_terms(
.in(shifted_in),
.out(in_enc)
);
pipeline_ce #(PIPELINE_STAGES > 0) u_enc_pipeline [`BCH_ECC_BITS(P)-1:0] (
.clk(clk),
.ce(ce),
.i(in_enc),
.o(in_enc_pipelined)
);
/*
* The below in equivalent to one instance with the vector input being
* data & lfsr. However, with this arrangement, its easy to pipeline
* the incoming data to reduce the number of gates/inputs between lfsr
* stages.
*/
lfsr_term #(`BCH_ECC_BITS(P), ENC, BITS) u_lfsr_terms(
.in(lfsr_input),
.out(lfsr_enc)
);
assign lfsr_first = in_enc_pipelined;
assign lfsr_next = (lfsr << BITS) ^ lfsr_enc ^ in_enc_pipelined;
end else begin
wire [BITS-1:0] shifted_in_pipelined;
pipeline_ce #(PIPELINE_STAGES > 0) u_enc_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(shifted_in),
.o(shifted_in_pipelined)
);
function [`BCH_ECC_BITS(P)-1:0] lfsr_rep;
input [`BCH_ECC_BITS(P)-1:0] prev;
input [BITS-1:0] in;
reg [`BCH_ECC_BITS(P)-1:0] ret;
integer i;
begin
ret = prev;
for (i = BITS - 1; i >= 0; i = i - 1)
ret = {ret[`BCH_ECC_BITS(P)-2:0], 1'b0} ^
({`BCH_ECC_BITS(P){ret[`BCH_ECC_BITS(P)-1] ^ in[i]}} & ENC);
lfsr_rep = ret;
end
endfunction
assign lfsr_first = lfsr_rep(0, shifted_in_pipelined);
assign lfsr_next = lfsr_rep(lfsr, shifted_in_pipelined);
end
pipeline_ce #(PIPELINE_STAGES) u_data_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(data_in),
.o(data_in_pipelined)
);
assign first = PIPELINE_STAGES ? start_last : (start && !busy);
assign data_bits = (start && !PIPELINE_STAGES) || load_lfsr;
assign ecc_bits = (busy || last) && !data_bits;
if (REM)
assign output_mask = last ? {{RUNT{1'b1}}, {REM{1'b0}}} : {BITS{1'b1}};
else
assign output_mask = {BITS{1'b1}};
assign data_out = data_bits ? data_in_pipelined : (lfsr_input & output_mask);
assign ready = !busy;
always @(posedge clk) begin
if (ce) begin
start_last <= #TCQ start && !busy;
if (start) begin
last <= #TCQ CODE_CYCLES < 3; /* First cycle is last cycle */
busy <= #TCQ 1;
end else if (count == DONE && busy) begin
last <= #TCQ busy;
busy <= #TCQ !PIPELINE_STAGES;
end else if (last) begin
last <= #TCQ 0;
busy <= #TCQ 0;
end
if (start)
load_lfsr <= #TCQ DATA_CYCLES > 1;
else if (count == SWITCH)
load_lfsr <= #TCQ 1'b0;
if (start)
lfsr <= #TCQ PIPELINE_STAGES ? 0 : lfsr_first;
else if (load_lfsr)
lfsr <= #TCQ lfsr_next;
else if (busy)
lfsr <= #TCQ lfsr << BITS;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.v
// Design : system_vga_sync_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
module system_vga_sync_reset_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_PP_V
|
// megafunction wizard: %ALTLVDS%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_rx
// ============================================================
// File Name: LVDS_AD.v
// Megafunction Name(s):
// altlvds_rx
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module LVDS_AD (
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock);
input [7:0] rx_in;
input rx_inclock;
output rx_locked;
output [95:0] rx_out;
output rx_outclock;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "600"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "12"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INCLOCK_PHASE_SHIFT STRING "56.25"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: Int_Device STRING "Cyclone III"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "1"
// Retrieval info: PRIVATE: Le_Serdes STRING "ON"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "8"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "50.00"
// Retrieval info: PRIVATE: PLL_Period STRING "20.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Ext_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "12"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "ON"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "UNUSED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "20000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "521"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "600"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: PORT_RX_CHANNEL_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_RX_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REGISTERED_DATA_ALIGN_INPUT STRING "OFF"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: USED_PORT: rx_in 0 0 8 0 INPUT NODEFVAL rx_in[7..0]
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT_CLK_EXT GND rx_inclock
// Retrieval info: USED_PORT: rx_locked 0 0 0 0 OUTPUT NODEFVAL rx_locked
// Retrieval info: USED_PORT: rx_out 0 0 96 0 OUTPUT NODEFVAL rx_out[95..0]
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL rx_outclock
// Retrieval info: CONNECT: @rx_in 0 0 8 0 rx_in 0 0 8 0
// Retrieval info: CONNECT: rx_out 0 0 96 0 @rx_out 0 0 96 0
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); const double Eps = 1e-6; const int Mod = (int)1e9 + 7; long long Bigmod(long long b, long long p, long long m) { if (p == 0) return 1LL; if (p % 2 == 0) { long long c = Bigmod(b, p / 2, m); return ((c % m) * (c % m)) % m; } else return ((b % m) * (Bigmod(b, p - 1, m))) % m; } long long ModInverse(long long a, long long M) { return Bigmod(a, M - 2, M); } template <class T> inline T GCD(T x, T y) { if (y == 0) return x; return GCD(y, x % y); } template <class T> inline T LCM(T x, T y) { return ((x / GCD(x, y)) * y); } bool Reverse(long long a, long long b) { return a > b; } bool Compare(pair<long long, long long> a, pair<long long, long long> b) { if (a.first == b.first) return a.second > b.second; return a.first < b.first; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T; cin >> T; while (T--) { string A, B; cin >> A >> B; if (A < B) cout << A << endl; else { int Pos[27]; for (int i = 0; i < 27; i++) Pos[i] = -1; for (int i = 0; i < A.size(); i++) { int Position = A[i] - A + 1; Pos[Position] = max(Pos[Position], i); } bool PreBreak = false, SolutionFound = false; for (int i = 1; i <= 26; i++) { if (Pos[i] == -1) continue; for (int j = 0; j < Pos[i]; j++) { if (A[j] > A[Pos[i]]) { string Temp = A; swap(Temp[j], Temp[Pos[i]]); if (Temp < B) { cout << Temp << endl; SolutionFound = true; PreBreak = true; break; } } } if (PreBreak) break; } if (SolutionFound == false) cout << --- << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int f = 1, x = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * f; } bitset<10000> b[60]; int main() { int m = read(), n = read(); for (int i = 1; i <= m; ++i) { int k = read(); bool flag = 1; for (int j = 1; j <= k; ++j) { int x = read(); b[i][x] = 1; } for (int j = 1; j < i; ++j) if (!(b[i] & b[j]).count()) { puts( impossible ); return 0; } } puts( possible ); return 0; }
|
//-----------------------------------------------------------------------------
//-- mpres.v Multiples prescalers
//-- (C) BQ August 2015. Written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- Ejemplo de diseño jerarquico
//-- Se utiliza el componente generico prescaler.v
//-- Se instancian 4 prescalers independientes, cada uno para controlar la
//-- frecuencia de un led
//-- Un quinto prescaler determina la señal de reloj base, común al resto
//-- de prescalers
//-----------------------------------------------------------------------------
//-- clk_in: Entrada. Componente de reloj de entrada (12 Mhz)
//-- D1, D2, D3, D4: Salidas. Son las señales que se envían a los leds
module mpres(input clk_in, output D1, output D2, output D3, output D4);
wire clk_in;
wire D1;
wire D2;
wire D3;
wire D4;
//-- Parametros del componente
//-- Bits para los diferentes prescalers
//-- Cambiar estos valores segun la secuencia a sacar por los leds
parameter N0 = 21; //-- Prescaler base
parameter N1 = 1;
parameter N2 = 2;
parameter N3 = 1;
parameter N4 = 2;
//-- Cable con señal de reloj base: la salida del prescaler 0
wire clk_base;
//-- Prescaler base. Conectado a la señal de reloj de entrada
//-- Su salida es por clk_base
//-- Tiene N0 bits de tamaño
prescaler #(.N(N0))
Pres0(
.clk_in(clk_in),
.clk_out(clk_base)
);
//-- Canal 1: Prescaner de N1 bits, conectado a led 1
prescaler #(.N(N1))
Pres1(
.clk_in(clk_base),
.clk_out(D1)
);
//-- Canal 2: Prescaler de N2 bits, conectado a led 2
prescaler #(.N(N2))
Pres2(
.clk_in(clk_base),
.clk_out(D2)
);
//-- Canal 3: Prescaler de N3 bits, conectado a led 3
prescaler #(.N(N3))
Pres3(
.clk_in(clk_base),
.clk_out(D3)
);
//-- Canal 4: Prescaler de N4 bits, conectado a led 4
prescaler #(.N(N4))
Pres4(
.clk_in(clk_base),
.clk_out(D4)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; while (scanf( %d %d , &n, &k) == 2) { char s[1000005]; memset(s, 0, sizeof(s)); int t = 0; if (n == 1 && k == 1) printf( a n ); else if (k == 1) printf( -1 n ); else if (n < k) printf( -1 n ); else if (k == 2) { int l = k - 2; for (int i = 1; i <= n - l; i++) { if (i & 1) s[t++] = a ; else s[t++] = b ; } s[t] = 0 ; printf( %s n , s); } else if (k == 3) { int l = k - 2; for (int i = 1; i <= n - l; i++) { if (i & 1) s[t++] = a ; else s[t++] = b ; } for (int i = 1; i <= l; i++) { s[t++] = char( b + i); } s[t] = 0 ; printf( %s n , s); } else { int l = k - 2; for (int i = 1; i <= n - l; i++) { if (i & 1) s[t++] = a ; else s[t++] = b ; } for (int i = 1; i <= l; i++) { s[t++] = char( b + i); } s[t] = 0 ; printf( %s n , s); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1E-9; const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double PI = 2 * acos(.0); long long dp[10][10][2]; vector<int> number; int pivot = 1; long long solve(int pos, bool is_bounded, int lucky_digits) { long long &memo = dp[pos][lucky_digits][is_bounded]; if (lucky_digits > pivot) return 0; if (pos == (int)(number).size()) return 1; if (memo != -1) return memo; memo = 0; int upto = 9; if (is_bounded) upto = number[pos]; for (int i = 0; i <= upto; i++) { bool next_bound = is_bounded && (upto == i); int next_lucky = lucky_digits + ((i == 4 || i == 7) ? 1 : 0); int next_pos = pos + 1; memo += solve(next_pos, next_bound, next_lucky); } return memo; } const long long MOD = 1000000007ll; long long bigPow(long long a, long long b) { long long resp = 1; while (b) { if (b & 1) resp = (resp * a) % MOD; a = (a * a) % MOD; b >>= 1; } return resp % MOD; } long long inv(long long x) { return bigPow(x, MOD - 2); } long long binCoefRec(int nn, int kk) { if (nn == kk) return 1ll; if (kk == 0) return 1ll; long long bin = (binCoefRec(nn - 1, kk - 1) * nn) % MOD; long long resp = (bin * inv(kk)) % MOD; return resp; } set<string> occur_set[10]; bool cent[10]; void find_occur(string seed, int times, int last) { if (times > 9) return; occur_set[times].insert(seed); for (int i = last; i < (int)(10); i++) { seed[i]++; seed[0]--; find_occur(seed, times + i, i); seed[i]--; seed[0]++; } } int main() { ios_base::sync_with_stdio(0); int m; cin >> m; while (m) { number.push_back(m % 10); m /= 10; } reverse(number.begin(), number.end()); long long lucky_id[10]; long long calc = 0, calc_bef = 0; long long ans = 0; find_occur( 6000000000 , 0, 1); for (pivot = 0; pivot < 10; pivot++) { for (int i = 0; i < (int)(10); i++) for (int j = 0; j < (int)(10); j++) for (int k = 0; k < (int)(2); k++) dp[i][j][k] = -1; calc = solve(0, true, 0) - 1; lucky_id[pivot] = calc - calc_bef; calc_bef = calc; if (pivot == 0 || lucky_id[pivot] == 0) continue; for (int x = 0; x < pivot; x++) { set<string>::iterator p = occur_set[x].begin(); while (p != occur_set[x].end()) { long long temp = 1; bool cant = 1; for (int i = 0; i < (int)((*p).size()); i++) { if (i > pivot) continue; if ((*p)[i] < 0 || lucky_id[i] < ((*p)[i] - 0 )) { cant = 0; break; } temp = (((temp) % MOD) * binCoefRec(lucky_id[i], (*p)[i] - 0 )) % MOD; } if (cant == 0) temp = 0; else temp = (temp * lucky_id[pivot]) % MOD; ans = (ans + temp * 720) % MOD; p++; } } } cout << ans << endl; return 0; }
|
/*************************************************************** File name: CF1517F.cpp Author: ljfcnyali Create time: 2021年04月27日 星期二 10时19分32秒 ***************************************************************/ #include<bits/stdc++.h> using namespace std; #define REP(i, a, b) for ( int i = (a), _end_ = (b); i <= _end_; ++ i ) #define mem(a) memset ( (a), 0, sizeof ( a ) ) #define str(a) strlen ( a ) #define pii pair<int, int> #define int long long typedef long long LL; const int maxn = 1010; const int Mod = 998244353; int n, Begin[maxn], Next[maxn], To[maxn], e, ans[maxn], ret, f[maxn][maxn][2], g[maxn][2], Max[maxn]; inline void add(int u, int v) { To[++ e] = v; Next[e] = Begin[u]; Begin[u] = e; } inline int power(int a, int b) { int r = 1; while ( b ) { if ( b & 1 ) r = r * a % Mod; a = a * a % Mod; b >>= 1; } return r; } inline void DFS(int u, int fa, int x) { f[u][0][0] = f[u][x][1] = 1; Max[u] = 0; for ( int i = Begin[u]; i; i = Next[i] ) { int v = To[i]; if ( v == fa ) continue ; DFS(v, u, x); REP(k, 0, Max[u]) REP(j, 0, Max[v]) { g[max(k, j + 1)][0] = (g[max(k, j + 1)][0] + f[u][k][0] * f[v][j][0]) % Mod; if ( j < x - k ) g[x - k][1] = (g[x - k][1] + f[u][x - k][1] * f[v][j][0]) % Mod; else g[j + 1][0] = (g[j + 1][0] + f[u][x - k][1] * f[v][j][0]) % Mod; } REP(k, 0, Max[u]) REP(j, x - Max[v], x) { if ( k <= j - 1 ) g[j - 1][1] = (g[j - 1][1] + f[u][k][0] * f[v][j][1]) % Mod; else g[k][0] = (g[k][0] + f[u][k][0] * f[v][j][1]) % Mod; g[max(x - k, j - 1)][1] = (g[max(x - k, j - 1)][1] + f[u][x - k][1] * f[v][j][1]) % Mod; } REP(k, 0, x) REP(o, 0, 1) { f[u][k][o] = g[k][o]; g[k][o] = 0; } Max[u] = max(Max[u], Max[v] + 1); } } inline int Solve(int x) { mem(f); DFS(1, 0, x); int sum = 0; REP(i, 0, x) sum = (sum + f[1][i][1]) % Mod; return sum; } signed main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif scanf( %lld , &n); REP(i, 1, n - 1) { int u, v; scanf( %lld%lld , &u, &v); add(u, v); add(v, u); } REP(i, 0, n) ans[i] = Solve(i); REP(i, 1, n) ret = (ret + (ans[i] - ans[i - 1]) * (i - 1)) % Mod; ret = (ret + n - 1) * power((Mod + 1) / 2, n) % Mod; printf( %lld n , (ret + Mod) % Mod); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; using ii = pair<int, int>; using ll = long long; const int N = 3000 + 5; const int mod = 1e9 + 7; string source[N], target[N]; int n; ii ranges[N]; vector<int> FAIL(string pat) { int m = pat.size(); vector<int> F(m + 1); int i = 0, j = -1; F[0] = -1; while (i < m) { while (j >= 0 && pat[i] != pat[j]) j = F[j]; i++, j++; F[i] = j; } return F; } bool check(string a, string b, string s, string t) { vector<int> F = FAIL(s); int i = 0, j = 0; int n = a.size(); int m = s.size(); while (i < n) { while (j >= 0 && a[i] != s[j]) j = F[j]; i++, j++; if (j == m) { int idx = i - j; for (int k = 0; k < m; k++) { a[k + idx] = t[k]; } break; } } return a == b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> source[i]; for (int i = 0; i < n; i++) cin >> target[i]; string s, t; string prefix, suffix; for (int i = 0; i < n; i++) { if (source[i] != target[i]) { int l = -1, r = -1; for (int j = 0; j < source[i].size(); j++) { if (source[i][j] != target[i][j]) r = j; if (source[i][j] != target[i][j] && l == -1) l = j; } ranges[i] = {l, r}; if (s.empty()) { s = source[i].substr(l, r - l + 1); t = target[i].substr(l, r - l + 1); prefix = source[i].substr(0, l); suffix = source[i].substr(r + 1); reverse(prefix.begin(), prefix.end()); } else { if (s != source[i].substr(l, r - l + 1) || t != target[i].substr(l, r - l + 1)) { cout << NO n ; return 0; } string cprefix = source[i].substr(0, l); string csuffix = source[i].substr(r + 1); reverse(cprefix.begin(), cprefix.end()); string p, ss; for (int j = 0; j < min(cprefix.size(), prefix.size()) && cprefix[j] == prefix[j]; j++) { p.push_back(prefix[j]); } for (int j = 0; j < min(csuffix.size(), suffix.size()) && csuffix[j] == suffix[j]; j++) { ss.push_back(suffix[j]); } prefix = p; suffix = ss; } } } reverse(prefix.begin(), prefix.end()); s = prefix + s + suffix; t = prefix + t + suffix; for (int i = 0; i < n; i++) { if (!check(source[i], target[i], s, t)) { cout << NO n ; return 0; } } cout << YES n ; cout << s << n ; cout << t << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { #ifdef DEBUG freopen( a.in , r , stdin); #endif ios_base::sync_with_stdio(false), cin.tie(0); int T; cin >> T; while (T--) { int a[2]; cin >> a[0] >> a[1]; string s; cin >> s; int n = a[0] + a[1]; vector<pair<int, int>> x; for (int i = 0; i < n / 2; ++i) { if (s[i] == ? && s[n - 1 - i] == ? ) { x.emplace_back(i, n - 1 - i); } else if (s[i] == ? ) { a[s[n - 1 - i] - 0 ] -= 2; s[i] = s[n - 1 - i]; } else if (s[n - 1 - i] == ? ) { a[s[i] - 0 ] -= 2; s[n - 1 - i] = s[i]; } else { if (s[i] != s[n - 1 - i]) { a[0] = -1; } else { a[s[i] - 0 ] -= 2; } } } if (a[0] < 0 || a[1] < 0) { cout << -1 << n ; continue; } for (int i = 0; i < x.size(); ++i) { if (a[0] >= 2) { s[x[i].first] = s[x[i].second] = 0 ; a[0] -= 2; } else if (a[1] >= 2) { s[x[i].first] = s[x[i].second] = 1 ; a[1] -= 2; } else { a[0] = -1; } } if (a[0] < 0 || a[1] < 0) { cout << -1 << n ; continue; } if ((n & 1) && s[n / 2] != ? ) a[s[n / 2] - 0 ]--; if ((n & 1) && s[n / 2] == ? ) s[n / 2] = a[0] ? 0 : 1 ; if (a[0] < 0 || a[1] < 0) cout << -1 << n ; else cout << s << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file obc_lower.v when simulating
// the core, obc_lower. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module obc_lower(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[500000], o, ans; int main() { cin >> n; ans = 1; for (int i = 2; i <= n + 1; i++) { if (a[i] == 0) { a[i] = 1; o = 1; for (int j = i + i; j <= n + 1; j += i) { o = 2; ans = max(ans, o); a[j] = o; } } } cout << ans << endl; for (int i = 2; i <= n + 1; i++) cout << a[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<long long int> v(n); for (long long int &x : v) cin >> x; for (int i = 0; i < n; i++) { if (i % 2) v[i] = -abs(v[i]); else v[i] = abs(v[i]); cout << v[i] << ; } cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y, nand0_out, or0_out);
buf buf0 (Y , nand1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = int(1e9) + 7; const double eps = 1e-9; vector<pair<int, int> > g[111]; int dp[111][111][30]; int n, m; int dfs(int u, int v, int x) { if (dp[u][v][x]) return dp[u][v][x]; dp[u][v][x] = 2; for (int i = 0; i < int((g[u]).size()); ++i) { pair<int, int> to = g[u][i]; if (to.second >= x) { if (dfs(v, to.first, to.second) == 2) { dp[u][v][x] = 1; break; } } } return dp[u][v][x]; } int main() { cin >> n >> m; for (int i = 1; i <= m; ++i) { int u, v; char c; cin >> u >> v >> c; g[u].push_back(make_pair(v, c - 97)); } for (int i = 1; i <= n; i++) { for (int j = 0; j < 26; j++) { dp[i][i][j] = 2; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (!dp[i][j][0]) { dfs(i, j, 0); } if (dp[i][j][0] == 1) cout << A ; else cout << B ; } cout << endl; } return 0; }
|
`include "senior_defines.vh"
module loop_controller
#(parameter ctrl_w = `LC_CTRL_WIDTH,
parameter nat_w = `SENIOR_NATIVE_WIDTH,
parameter spr_dat_w = `SPR_DATA_BUS_WIDTH,
parameter spr_adr_w = `SPR_ADR_BUS_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire pfc_lc_loopn_sel_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] rf_opa_bus_i,
input wire [nat_w-1:0] pc_lc_addr_i,
output wire lc_pfc_loop_flag_o,
output wire [nat_w-1:0] lc_pfc_loopb_o,
output wire [nat_w-1:0] lc_pfc_loope_o,
input wire [spr_dat_w-1:0] spr_dat_i,
input wire [spr_adr_w-1:0] spr_adr_i,
input wire spr_wren_i,
output reg [spr_dat_w-1:0] spr_dat_o
);
`include "std_messages.vh"
// Internal Declarations
reg [nat_w-1:0] loopn_reg;
wire [1:0] loopn_mux_sel;
reg [nat_w-1:0] loopn_sig;
reg [nat_w-1:0] loopn1_sig;
reg [nat_w-1:0] loope1_sig;
reg [nat_w-1:0] loope_reg;
reg [nat_w-1:0] loope_sig;
reg [nat_w-1:0] loopb1_sig;
reg [nat_w-1:0] loopb_reg;
reg [nat_w-1:0] loopb_sig;
reg [nat_w-1:0] old_pc;
always@* begin
old_pc = pc_lc_addr_i;
end
always@(*) begin
case(spr_adr_i)
(`SPR_CP_GROUP + `LC_SPR_LOOPN): begin
spr_dat_o = loopn_reg;
end
(`SPR_CP_GROUP + `LC_SPR_LOOPB): begin
spr_dat_o = loopb_reg;
end
(`SPR_CP_GROUP + `LC_SPR_LOOPE): begin
spr_dat_o = loope_reg;
end
default: begin
spr_dat_o = 0;
end
endcase
end
// compute the loop counter value
always @(*) begin
case (pfc_lc_loopn_sel_i)
1'b0: loopn_sig=loopn_reg;
1'b1: loopn_sig=loopn_reg-1;
endcase
end
always@(*) begin
case (ctrl_i`LC_LOOPN1)
1'b0: loopn1_sig=loopn_sig;
1'b1: loopn1_sig=ctrl_i`LC_LOOPN_VAL;
endcase
end
wire [nat_w-1:0] loope1_sig_sum;
wire loope1_sig_sum_carry;
assign {loope1_sig_sum_carry,loope1_sig_sum} = ctrl_i`LC_LOOPE_VAL+old_pc-1;
always@(*) begin
case (ctrl_i`LC_LOOPE1)
1'b0: loope1_sig=loope_reg;
1'b1: loope1_sig=loope1_sig_sum;
endcase
end
always@(*) begin
case (ctrl_i`LC_LOOPB1)
1'b0: loopb1_sig=loopb_reg;
1'b1: loopb1_sig=old_pc;
endcase
end
assign lc_pfc_loop_flag_o = ~(|loopn_reg);
assign lc_pfc_loopb_o = loopb_reg;
assign lc_pfc_loope_o = loope_reg;
wire spr_write_loopn;
wire spr_write_loopb;
wire spr_write_loope;
assign spr_write_loopn = ((`SPR_CP_GROUP + `LC_SPR_LOOPN) == spr_adr_i) & spr_wren_i;
assign spr_write_loopb = ((`SPR_CP_GROUP + `LC_SPR_LOOPB) == spr_adr_i) & spr_wren_i;
assign spr_write_loope = ((`SPR_CP_GROUP + `LC_SPR_LOOPE) == spr_adr_i) & spr_wren_i;
// register the loop counter value
always @(posedge clk_i) begin
if (!reset_i) begin
loopn_reg<=0;
loopb_reg<=0;
loope_reg<=16'b1111111111111111;
end
else begin
if(spr_write_loopn) begin
loopn_reg<=spr_dat_i;
end
else begin
loopn_reg<=loopn1_sig;
end
if(spr_write_loopb) begin
loopb_reg<=spr_dat_i;
end
else begin
loopb_reg<=loopb1_sig;
end
if(spr_write_loope) begin
loope_reg<=spr_dat_i;
end
else begin
loope_reg<=loope1_sig;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores Simple General Purpose IO core ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $
//
// $Date: 2002/12/22 16:10:17 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: simple_gpio.v,v $
// Revision 1.2 2002/12/22 16:10:17 rherveille
// Fixed some typos in the documentation section.
//
//
//
// Very basic 8bit GPIO core
//
//
// Registers:
//
// 0x00: Control Register <io[7:0]>
// bits 7:0 R/W Input/Output '1' = output mode
// '0' = input mode
// 0x01: Line Register
// bits 7:0 R Status Current GPIO pin level
// W Output GPIO pin output level
//
//
// HOWTO:
//
// Use a pin as an input:
// Program the corresponding bit in the control register to 'input mode' ('0').
// The pin's state (input level) can be checked by reading the Line Register.
// Writing to the GPIO pin's Line Register bit while in input mode has no effect.
//
// Use a pin as an output:
// Program the corresponding bit in the control register to 'output mode' ('1').
// Program the GPIO pin's output level by writing to the corresponding bit in
// the Line Register.
// Reading the GPIO pin's Line Register bit while in output mode returns the
// current output level.
//
// Addapt the core for fewer GPIOs:
// If less than 8 GPIOs are required, than the 'io' parameter can be set to
// the amount of required interrupts. GPIOs are mapped starting at the LSBs.
// So only the 'io' LSBs per register are valid.
// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'.
// Codesize is approximately linear to the amount of interrupts. I.e. using
// 4 instead of 8 GPIO sources reduces the size by approx. half.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module simple_gpio(
clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
gpio
);
//
// Inputs & outputs
//
parameter io = 8; // number of GPIOs
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
input cyc_i; // cycle
input stb_i; // strobe
input adr_i; // address adr_i[1]
input we_i; // write enable
input [ 7:0] dat_i; // data output
output [ 7:0] dat_o; // data input
output ack_o; // normal bus termination
// GPIO pins
inout [io:1] gpio;
//
// Module body
//
reg [io:1] ctrl, line; // ControlRegister, LineRegister
reg [io:1] lgpio, llgpio; // LatchedGPIO pins
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(io > 8)
$display("simple_gpio: max. 8 GPIOs supported.");
end
// synopsys translate_on
//
// WISHBONE interface
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
ctrl <= #1 {io{1'b0}};
line <= #1 {io{1'b0}};
end
else if (wb_wr)
if ( adr_i )
line <= #1 dat_i[io-1:0];
else
ctrl <= #1 dat_i[io-1:0];
reg [7:0] dat_o;
always @(posedge clk_i)
if ( adr_i )
dat_o <= #1 { {(8-io){1'b0}}, llgpio};
else
dat_o <= #1 { {(8-io){1'b0}}, ctrl};
reg ack_o;
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
ack_o <= #1 1'b0;
else
ack_o <= #1 wb_acc & !ack_o;
//
// GPIO section
// latch GPIO input pins
always @(posedge clk_i)
lgpio <= #1 gpio;
// latch again (reduce meta-stability risc)
always @(posedge clk_i)
llgpio <= #1 lgpio;
// assign GPIO outputs
integer n;
reg [io:1] igpio; // temporary internal signal
always @(ctrl or line)
for(n=1;n<=io;n=n+1)
igpio[n] <= ctrl[n] ? line[n] : 1'bz;
assign gpio = igpio;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class __Ty> bool minimize(__Ty& a, __Ty b) { if (a > b) { a = b; return true; } return false; } template <class __Ty> bool maximize(__Ty& a, __Ty b) { if (a < b) { a = b; return true; } return false; } const int N = 2003; const int mod = 1e9 + 7; int f[N][N] = {0}; int n, k; vector<int> g[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= i; ++j) if (i % j == 0) g[i].push_back(j); } for (int j = 1; j <= n; ++j) f[1][j] = 1; for (int i = 2; i <= k; ++i) for (int j = 1; j <= n; ++j) { for (int v : g[j]) { f[i][j] = (f[i][j] + f[i - 1][v]) % mod; } } int ans = 0; for (int i = 1; i <= n; ++i) ans = (ans + f[k][i]) % mod; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 400010; int n, ans[N], where[N]; long long sz[N]; vector<int> v[N]; bool visit[N]; void init() { scanf( %d , &n); int a, b; for (int i = 0; i < n - 1; ++i) { scanf( %d %d , &a, &b); v[a].push_back(b); v[b].push_back(a); } } void dfs(int now) { visit[now] = true; for (int i = 0; i < v[now].size(); ++i) if (!visit[v[now][i]]) { dfs(v[now][i]); sz[now] += sz[v[now][i]]; } if (sz[now] == 0) sz[now] = 1; else sz[now] += 1; } int find_centroid(int now) { visit[now] = true; for (int i = 0; i < v[now].size(); ++i) { if (visit[v[now][i]]) continue; if (sz[v[now][i]] > n / 2) return find_centroid(v[now][i]); } return now; } void sv(int now, int value) { if (visit[now]) return; visit[now] = true; where[now] = value; for (int i = 0; i < v[now].size(); ++i) sv(v[now][i], value); } void dfs2(int now) { visit[now] = true; for (int i = 0; i < v[now].size(); ++i) sv(v[now][i], i); } void solve() { dfs(1); for (int i = 1; i <= n; ++i) visit[i] = false; int centroid = find_centroid(1); for (int i = 1; i <= n; ++i) visit[i] = false; dfs2(centroid); for (int i = 1; i <= n; ++i) { visit[i] = false; sz[i] = 0; } dfs(centroid); vector<int> tmp; for (int i = 0; i < v[centroid].size(); ++i) tmp.push_back(sz[v[centroid][i]]); int max1 = -1000000006, idx1, max2 = -1000000006, idx2; for (int i = 0; i < tmp.size(); ++i) if (tmp[i] > max1) { max1 = tmp[i]; idx1 = i; } if ((n % 2 == 0) && max1 == n / 2) max2 = n / 2; else { for (int i = 0; i < tmp.size(); ++i) if (tmp[i] > max2 && i != idx1) { max2 = tmp[i]; idx2 = i; } } for (int i = 1; i <= n; ++i) { if (i == centroid) ans[i] = 1; else if (where[i] == idx1) { int tmp = n - sz[i] - max2; if (tmp <= n / 2) ans[i] = 1; else ans[i] = 0; } else { int tmp = n - sz[i] - max1; if (tmp <= n / 2) ans[i] = 1; else ans[i] = 0; } } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); printf( n ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int __ = 1; while (__--) { init(); solve(); } }
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_streaming_top.v
// Version : v1.0
// Description: FIFO used to store / forward streaming data.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_axis_fifo
#(
parameter WIDTH = 33,
parameter HEADREG = 1 ,
parameter ZERO_INVALID = 1 ,
parameter FULL_LEVEL = 14,
parameter DEPTH = 16,
parameter DEPTHBITS = 4
) (
input Clk ,
input Rst_n ,
input [WIDTH-1:0] in_data ,
input [WIDTH-1:0] in_invalid_data,
input in_push ,
input in_ready ,
input in_block_notfull ,
input in_block_outvalid ,
output out_valid ,
output out_notfull ,
output out_overflow ,
output [DEPTHBITS-1:0] out_depth ,
output [WIDTH-1:0] out_data
);
(* ram_style = "distributed" *) reg [WIDTH-1:0] data_ff[DEPTH-1:0] ;
reg [WIDTH-1:0] headreg_ff ;
reg [DEPTHBITS-1:0] in_ptr_ff, out_ptr_ff ;
reg [DEPTHBITS:0] depth_ff ;
reg valid_ff, full_ff, notfull_ff, valid_filt_ff;
wire do_pop = in_ready && valid_filt_ff;
wire [DEPTHBITS-1:0] in_ptr = (in_push) ? in_ptr_ff[DEPTHBITS-1:0] + 'h1 :
in_ptr_ff[DEPTHBITS-1:0];
wire [DEPTHBITS:0] depth =
(in_push && ~do_pop) ? depth_ff[DEPTHBITS:0] + 'h1 :
(~in_push && do_pop) ? depth_ff[DEPTHBITS:0] - 'h1 :
depth_ff[DEPTHBITS:0];
wire depth_was1 = (depth_ff[DEPTHBITS:0] == 'h1);
wire valid = (depth[DEPTHBITS:0] != 'h0);
wire full = (depth[DEPTHBITS:0] >= FULL_LEVEL) || in_block_notfull;
wire notfull = ~full;
wire [WIDTH-1:0] raw_data = data_ff[out_ptr_ff[DEPTHBITS-1:0]];
wire [DEPTHBITS-1:0] out_ptr = (do_pop) ? out_ptr_ff[DEPTHBITS-1:0] + 'h1 :
out_ptr_ff[DEPTHBITS-1:0];
wire [WIDTH-1:0] head_raw_data = (depth_was1) ? in_data[WIDTH-1:0] :
raw_data[WIDTH-1:0];
wire [WIDTH-1:0] headreg = (!valid_ff && in_push) ? in_data[WIDTH-1:0] :
(do_pop) ? head_raw_data[WIDTH-1:0] :
headreg_ff[WIDTH-1:0];
wire valid_filt = valid &&
((valid_filt_ff && ~do_pop) || ~in_block_outvalid);
always @(posedge Clk) begin
in_ptr_ff[DEPTHBITS-1:0] <= (Rst_n) ? in_ptr[DEPTHBITS-1:0] : 'h0;
out_ptr_ff[DEPTHBITS-1:0] <= (Rst_n) ? out_ptr[DEPTHBITS-1:0] : ((HEADREG) ? 'h1 : 'h0);
depth_ff[DEPTHBITS:0] <= (Rst_n) ? depth[DEPTHBITS:0] : 'h0;
valid_ff <= (Rst_n) ? valid : 1'b0;
valid_filt_ff <= (Rst_n) ? valid_filt : 1'b0;
full_ff <= (Rst_n) ? full : 1'b0;
notfull_ff <= (Rst_n) ? notfull : 1'b0;
headreg_ff[WIDTH-1:0] <= (Rst_n) ? headreg[WIDTH-1:0] : 'h0;
end
integer i;
always @(posedge Clk) begin
if(in_push) begin
data_ff[in_ptr_ff[DEPTHBITS-1:0]] <= in_data[WIDTH-1:0];
end
end
wire [WIDTH-1:0] out_data_pre = (HEADREG) ? headreg_ff[WIDTH-1:0] :
raw_data[WIDTH-1:0];
assign out_data[WIDTH-1:0] = (ZERO_INVALID && ~valid_filt_ff) ?
in_invalid_data[WIDTH-1:0] : out_data_pre[WIDTH-1:0];
assign out_valid = valid_filt_ff;
assign out_notfull = notfull_ff;
assign out_overflow = depth_ff[DEPTHBITS];
assign out_depth = depth_ff[DEPTHBITS-1:0];
endmodule
|
#include <bits/stdc++.h> struct coor { int x[3]; }; int x[6][3] = {0, 1, 2, 0, 2, 1, 1, 0, 2, 1, 2, 0, 2, 0, 1, 2, 1, 0}; bool judge(coor a, coor b) { bool flag = 0; b.x[2] += 18; if (b.x[2] < a.x[2]) { flag = 1; } else if (b.x[2] > a.x[2]) { } else if (a.x[2] == b.x[2]) { if (b.x[1] < a.x[1]) { flag = 1; } else if (b.x[1] > a.x[1]) { } else if (b.x[1] == a.x[1]) { if (b.x[0] < a.x[0]) { flag = 1; } else if (b.x[0] > a.x[0]) { } else if (b.x[0] == a.x[0]) { flag = 1; } } } return flag; } bool hefa(coor a) { if (a.x[1] < 1 || a.x[1] > 12) return 0; if (a.x[1] == 1 || a.x[1] == 3 || a.x[1] == 5 || a.x[1] == 7 || a.x[1] == 8 || a.x[1] == 10 || a.x[1] == 12) { if (a.x[0] < 1 || a.x[0] > 31) return 0; } else if (a.x[1] == 2) { if (a.x[2] % 4 == 0) { if (a.x[0] < 1 || a.x[0] > 29) return 0; } else { if (a.x[0] < 1 || a.x[0] > 28) return 0; } } else { if (a.x[0] < 1 || a.x[0] > 30) return 0; } return 1; } int main() { int i, j; coor a, b, c; scanf( %d.%d.%d , &a.x[0], &a.x[1], &a.x[2]); scanf( %d.%d.%d , &b.x[0], &b.x[1], &b.x[2]); bool flag = 0; for (i = 0; i < 6; i++) { c.x[0] = b.x[x[i][0]]; c.x[1] = b.x[x[i][1]]; c.x[2] = b.x[x[i][2]]; if (hefa(c)) { if (judge(a, c)) { flag = 1; break; } } } if (flag) printf( YES n ); else printf( NO n ); return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charFromReceiver (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_PP_V
|
`include "defines.v"
module cp0_reg (
input wire clk,
input wire rst,
input wire[`RegAddrBus] raddr_i,
input wire[`RegBus] data_i,
input wire[`RegAddrBus] waddr_i,
input wire we_i,
input wire[5:0] int_i,
input wire[`RegBus] excepttype_i,
// 当前执行的指令
input wire[`RegBus] mem_current_inst_addr_i,
input wire mem_current_inst_loaded,
input wire mem_is_in_delayslot_i,
input wire[`RegBus] ex_current_inst_addr_i,
input wire ex_current_inst_loaded,
input wire ex_is_in_delayslot_i,
input wire[`RegBus] id_current_inst_addr_i,
input wire id_current_inst_loaded,
input wire id_is_in_delayslot_i,
input wire[`RegBus] pc_current_inst_addr_i,
output reg[`RegBus] data_o,
output reg[`RegBus] count_o,
output reg[`RegBus] compare_o,
output reg[`RegBus] status_o,
output reg[`RegBus] cause_o,
output reg[`RegBus] epc_o,
output reg[`RegBus] config_o,
output reg[`RegBus] prid_o,
output reg timer_int_o
);
reg[`RegBus] current_inst_addr_i;
reg is_in_delayslot_i;
// 对 CP0 中寄存器的写操作
always @(posedge clk) begin
if (rst == `RstEnable) begin
// Count 寄存器初始值 0
count_o <= `ZeroWord;
// Compare 寄存器初始值 0
compare_o <= `ZeroWord;
// Status 寄存器初始值，其中 CU 字段为 4'b0001，表示协处理器 CP0 存在
status_o <= 32'b00010000000000000000000000000000;
// Cause 寄存器初始值为 0
cause_o <= `ZeroWord;
// EPC 寄存器的初始值
epc_o <= `ZeroWord;
// Config 寄存器的初始值，其中 BE 字段为 1，表示工作在大端模式 (MSB)
config_o <= 32'b00000000000000001000000000000000;
// PRId 寄存器初始值，制作者 L，对应 0x48，类型为 0x1，表示基本类型，版本号 v1.0
prid_o <= 32'b00000000010011000000000100000010;
timer_int_o <= `InterruptNotAssert;
end
else begin
count_o <= count_o + 1;
if (mem_current_inst_loaded == `Loaded) begin
current_inst_addr_i <= mem_current_inst_addr_i;
is_in_delayslot_i <= mem_is_in_delayslot_i;
end
else if (ex_current_inst_loaded == `Loaded) begin
current_inst_addr_i <= ex_current_inst_addr_i;
is_in_delayslot_i <= ex_is_in_delayslot_i;
end
else if (id_current_inst_loaded == `Loaded) begin
current_inst_addr_i <= id_current_inst_addr_i;
is_in_delayslot_i <= id_is_in_delayslot_i;
end
else begin
current_inst_addr_i <= pc_current_inst_addr_i;
is_in_delayslot_i <= `NotInDelaySlot;
end
if (compare_o != `ZeroWord && count_o == compare_o) begin
timer_int_o <= `InterruptAssert;
end
if (we_i == `WriteEnable) begin
case (waddr_i)
`CP0_REG_COUNT: begin
count_o <= data_i;
end
`CP0_REG_COMPARE: begin
compare_o <= data_i;
timer_int_o <= `InterruptNotAssert;
end
`CP0_REG_STATUS: begin
status_o <= data_i;
end
`CP0_REG_CAUSE: begin
// cause 只有部分字段可写
cause_o[9:8] <= data_i[9:8];
cause_o[22] <= data_i[22];
cause_o[23] <= data_i[23];
end
`CP0_REG_EPC: begin
epc_o <= data_i;
end
default: begin
end
endcase
end
case (excepttype_i)
`EXCEPTTYPE_INTERRUPT: begin // 外部中断
if (is_in_delayslot_i == `InDelaySlot) begin
epc_o <= current_inst_addr_i - 4;
cause_o[31] <= 1'b1; // Cause 寄存器的 BD 字段
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
status_o[1] <= 1'b1; // EXL 字段
cause_o[6:2] <= 5'b00000; // ExcCode 字段
end
`EXCEPTTYPE_SYSCALL: begin
if (status_o[1] == 1'b0) begin
if (is_in_delayslot_i == `InDelaySlot) begin
epc_o <= current_inst_addr_i - 4;
cause_o[31] <= 1'b1;
end
else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01000;
end
`EXCEPTTYPE_INST_INVALID: begin
if (status_o[1] == 1'b0) begin
if (is_in_delayslot_i == `InDelaySlot) begin
epc_o <= current_inst_addr_i - 4;
cause_o[31] <= 1'b1;
end
else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01010;
end
`EXCEPTTYPE_TRAP: begin
if (status_o[1] == 1'b0) begin
if (is_in_delayslot_i == `InDelaySlot) begin
epc_o <= current_inst_addr_i - 4;
cause_o[31] <= 1'b1;
end
else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01101;
end
`EXCEPTTYPE_OV: begin
if (status_o[1] == 1'b0) begin
if (is_in_delayslot_i == `InDelaySlot) begin
epc_o <= current_inst_addr_i - 4;
cause_o[31] <= 1'b1;
end
else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01110;
end
`EXCEPTTYPE_ERET: begin
status_o[1] <= 1'b0;
end
default: begin
end
endcase
#1 cause_o[15:10] = int_i; // 外部中断声明，少量延时，防止定时中断恢复之后由于 compare 值写入路径长导致再次进入中断
end
end
// 对 CP0 寄存器的读操作
always @(*) begin
if (rst == `RstEnable) begin
data_o <= `ZeroWord;
end
else begin
case (raddr_i)
`CP0_REG_COUNT: begin
data_o <= count_o;
end
`CP0_REG_COMPARE: begin
data_o <= compare_o;
end
`CP0_REG_STATUS: begin
data_o <= status_o;
end
`CP0_REG_CAUSE: begin
data_o <= cause_o;
end
`CP0_REG_EPC: begin
data_o <= epc_o;
end
`CP0_REG_PRID: begin
data_o <= prid_o;
end
`CP0_REG_CONFIG: begin
data_o <= config_o;
end
default: begin
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_1_V
`define SKY130_FD_SC_MS__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_1_V
|
/*------------------------------------------------------------------------------
Purpose
Pipeline: ñontrol sequence of instructions. All instructions have two stages:
1) Fetch;
2) Execute.
Branch instructions may have additional stage:
3) Memory issue instruction of branch address.
Memory instructions additional stages defined by Wishbone interface and
pipeline will be stallen (pl_stall_mem) until ending memory operation.
Multiply and divide instructions stall pipeline (pl_stall_multdiv) until
endinding of calculation.
------------------------------------------------------------------------------*/
module mips_pipeline (
input clk,
input rst,
input pl_stall_mem,
input pl_stall_branch,
input pl_stall_multdiv,
input pl_stall_eret,
input exception,
output[5:0] ifield_fstage_opcode,
output[4:0] ifield_fstage_d,
output[4:0] ifield_fstage_t,
output[4:0] ifield_fstage_s,
output[4:0] ifield_fstage_shift,
output[5:0] ifield_fstage_func,
input pmem_cmdok,
input[31:0] pmem_cmd,
input pmem_branch_ended,
input alu_multdiv_ready,
output reg pl_cause_bd,
output reg pl_pcpause
);
reg[31:0] pl_instr_fstage;
reg[31:0] pl_instr_fstage_d;
reg[1:0] cpu_state;
reg[1:0] cpu_state_d;
reg pl_pcpause_d;
reg instr_next;
reg instr_next_d;
reg pl_branch_excpt;
reg pl_branch_excpt_d;
reg branch_stall_was;
reg branch_stall_was_d;
localparam NORMAL= 2'b00,
STALL_BRANCH= 2'b01,
STALL_MEM= 2'b10,
STALL_MULTDIV= 2'b11;
assign ifield_fstage_opcode= pl_instr_fstage_d[31:26];
assign ifield_fstage_s= pl_instr_fstage_d[25:21];
assign ifield_fstage_t= pl_instr_fstage_d[20:16];
assign ifield_fstage_d= pl_instr_fstage_d[15:11];
assign ifield_fstage_shift= pl_instr_fstage_d[10:6];
assign ifield_fstage_func= pl_instr_fstage_d[5:0];
always @*
begin
pl_instr_fstage= pmem_cmd;
cpu_state= NORMAL;
instr_next= instr_next_d;
pl_pcpause= pl_pcpause_d;
branch_stall_was= branch_stall_was_d;
pl_cause_bd= 1'b0;
pl_branch_excpt= pl_branch_excpt_d;
case(cpu_state_d)
NORMAL:
begin
pl_pcpause= 1'b0;
branch_stall_was= 1'b0;
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else if(!pmem_cmdok) pl_instr_fstage= 32'd0;
end
STALL_BRANCH:
begin
branch_stall_was= 1'b1;
if(pmem_cmdok)
begin
instr_next= 1'b0;
pl_branch_excpt= 1'b0;
end
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
pl_instr_fstage= 32'd0;
pl_cause_bd= 1'b1;
pl_branch_excpt= 1'b1;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else
begin
pl_instr_fstage= (instr_next_d | pmem_branch_ended) &
pmem_cmdok & !pl_branch_excpt_d ? pmem_cmd : 32'd0;
cpu_state= pmem_branch_ended & !pl_branch_excpt_d ? NORMAL : STALL_BRANCH;
end
end
STALL_MEM:
begin
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
pl_pcpause= 1'b0;
if(branch_stall_was_d) pl_cause_bd= 1'b1;
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else
begin
pl_pcpause= 1'b0;
pl_instr_fstage= pmem_cmdok ? pmem_cmd : 32'd0;
end
end
STALL_MULTDIV:
begin
if(exception)
begin
if(branch_stall_was_d) pl_cause_bd= 1'b1;
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else
begin
if(!alu_multdiv_ready)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= STALL_MULTDIV;
end
else
begin
pl_pcpause= 1'b0;
pl_instr_fstage= pmem_cmdok ? pmem_cmd : 32'd0;
end
end
end
endcase
end
always @(posedge clk)
begin
if(rst)
begin
instr_next_d<= 1'b0;
pl_pcpause_d<= 1'b0;
pl_branch_excpt_d<= 1'b0;
branch_stall_was_d<= 1'b0;
pl_instr_fstage_d<= 32'd0;
cpu_state_d<= NORMAL;
end
else
begin
instr_next_d<= instr_next;
pl_pcpause_d<= pl_pcpause;
pl_branch_excpt_d<= pl_branch_excpt;
branch_stall_was_d<= branch_stall_was;
pl_instr_fstage_d<= pl_instr_fstage;
cpu_state_d<= cpu_state;
end
end
endmodule
|
#include<bits/stdc++.h> #define FOR(i,l,r) for(int i=l;i<=r;i++) #define ROF(i,l,r) for(int i=l;i>=r;i--) #define lson k<<1,l,mid #define rson k<<1|1,mid+1,r #define r(x) read(x) #define rr(x,y) read(x);read(y) #define rrr(x,y,z) read(x);read(y);read(z) #define pb(x) push_back(x) #define mp(x,y) make_pair(x,y) #define fi first #define se second #define sss(str) scanf( %s ,str+1) using namespace std; typedef long long LL; typedef pair<int,int> pt; const int N=1e6+5; const int M=2e3+5; const int mod=1e9+7; const int INF=2e9; const double eps=1e-8; const double pi=acos(-1); template <class T> inline void read(T &x) { char c;x = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) x = -1; T res = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) res = res * 10 + c - 0 ; x *= res; } int n,m; char str[N]; int f[N]; void solve(int cas) { r(n); int cnt1=n/2,cnt2=n-cnt1; LL ans=0; set<pt> s; for(int i=cnt1;i>=-cnt1;i-=2){ for(int j=cnt2;j>=-cnt2;j-=2){ s.insert(mp(i,j)); s.insert(mp(j,i)); } } cout<<s.size()<<endl; } int main() { int t; // r(t); t=1; // init(); FOR(i,1,t){ solve(i); } return 0; }
|
/*
* Copyright (c) 2014 CERN
* @author Maciej Suminski <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Test for VPI functions handling dynamic arrays
module main();
initial
begin
int int_darray[];
real real_darray[];
bit [63:0] bit_darray[];
string string_darray[];
int_darray = new[4];
int_darray = '{1, 2, 3, 4};
$display_array(int_darray);
$increase_array_vals(int_darray);
$display_array(int_darray);
real_darray = new[2];
real_darray = '{2.2, 2.3};
$increase_array_vals(real_darray);
$display_array(real_darray);
bit_darray = new[4];
bit_darray = '{64'hdeadbeefcafebabe, 64'h0badc0dec0dec0de,
64'h0123456789abcdef, 64'hfedcba9876543210};
$increase_array_vals(bit_darray);
$display_array(bit_darray);
string_darray = new[4];
string_darray = '{"test string", "another one", "yet one more", "the last one"};
$increase_array_vals(string_darray);
$display_array(string_darray);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
`define SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_mux_2to1.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_ls__udp_mux_2to1 dut (.A0(A0), .A1(A1), .S(S), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc = 0;
reg [7:0] padd;
reg dsp_ph1, dsp_ph2, dsp_reset;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] out; // From dspchip of t_dspchip.v
// End of automatics
t_dspchip dspchip (/*AUTOINST*/
// Outputs
.out (out[7:0]),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
always @ (posedge clk) begin
$write("cyc %d\n",cyc);
if (cyc == 8'd0) begin
cyc <= 8'd1;
dsp_reset <= 0; // Need a posedge
padd <= 0;
end
else if (cyc == 8'd20) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
cyc <= cyc + 8'd1;
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
dsp_reset <= (cyc == 8'd1);
padd <= cyc;
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
case (cyc)
default: $stop;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: ;
8'd05: ;
8'd06: ;
8'd07: ;
8'd08: ;
8'd09: if (out!==8'h04) $stop;
8'd10: if (out!==8'h04) $stop;
8'd11: if (out!==8'h08) $stop;
8'd12: if (out!==8'h08) $stop;
8'd13: if (out!==8'h00) $stop;
8'd14: if (out!==8'h00) $stop;
8'd15: if (out!==8'h00) $stop;
8'd16: if (out!==8'h00) $stop;
8'd17: if (out!==8'h0c) $stop;
8'd18: if (out!==8'h0c) $stop;
8'd19: if (out!==8'h10) $stop;
endcase
end
end
endmodule
module t_dspchip (/*AUTOARG*/
// Outputs
out,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, padd
);
input dsp_ph1, dsp_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out;
wire dsp_ph1, dsp_ph2;
wire [7:0] out;
wire pla_ph1, pla_ph2;
wire out1_r;
wire [7:0] out2_r, padd;
wire clk_en;
t_dspcore t_dspcore (/*AUTOINST*/
// Outputs
.out1_r (out1_r),
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.clk_en (clk_en));
t_dsppla t_dsppla (/*AUTOINST*/
// Outputs
.out2_r (out2_r[7:0]),
// Inputs
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
assign out = out1_r ? 8'h00 : out2_r;
assign clk_en = 1'b1;
endmodule
module t_dspcore (/*AUTOARG*/
// Outputs
out1_r, pla_ph1, pla_ph2,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, clk_en
);
input dsp_ph1, dsp_ph2, dsp_reset;
input clk_en;
output out1_r, pla_ph1, pla_ph2;
wire dsp_ph1, dsp_ph2, dsp_reset;
wire pla_ph1, pla_ph2;
reg out1_r;
always @(posedge dsp_ph1 or posedge dsp_reset) begin
if (dsp_reset)
out1_r <= 1'h0;
else
out1_r <= ~out1_r;
end
assign pla_ph1 = dsp_ph1;
assign pla_ph2 = dsp_ph2 & clk_en;
endmodule
module t_dsppla (/*AUTOARG*/
// Outputs
out2_r,
// Inputs
pla_ph1, pla_ph2, dsp_reset, padd
);
input pla_ph1, pla_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out2_r;
wire pla_ph1, pla_ph2, dsp_reset;
wire [7:0] padd;
reg [7:0] out2_r;
reg [7:0] latched_r;
always @(posedge pla_ph1 or posedge dsp_reset) begin
if (dsp_reset)
latched_r <= 8'h00;
else
latched_r <= padd;
end
always @(posedge pla_ph2 or posedge dsp_reset) begin
if (dsp_reset)
out2_r <= 8'h00;
else
out2_r <= latched_r;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_SYMBOL_V
`define SKY130_FD_SC_LS__NOR2B_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_TB_V
`define SKY130_FD_SC_MS__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_TB_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5; const long long linf = 1e18 + 5; class point { public: int x, y; double m; point() {} point(int x, int y) { this->x = x; this->y = y; this->m = atan2(y, x); } bool operator<(point other) const { return m < other.m; } bool operator==(point other) const { return x == other.x and y == other.y and m == other.m; } }; int n, c, x, y, sumx, sumy; pair<int, int> a[5]; set<point> s; long long ccw(point a, point c, point b) { pair<int, int> v1 = make_pair(c.x - a.x, c.y - a.y); pair<int, int> v2 = make_pair(b.x - a.x, b.y - a.y); return (long long)v1.first * v2.second - (long long)v1.second * v2.first; } set<point>::iterator something_stupid_(point x) { set<point>::iterator it = s.lower_bound(x); if (it == s.end()) it = s.begin(); return it; } set<point>::iterator something_stupid_(set<point>::iterator it) { it++; if (it == s.end()) it = s.begin(); return it; } set<point>::iterator _something_stupid(set<point>::iterator it) { if (it == s.begin()) { it = s.end(); it--; } else it--; return it; } int main() { ios ::sync_with_stdio(0); cin >> n; for (int i = 1; i <= 3; i++) { cin >> c >> a[i].first >> a[i].second; sumx += a[i].first; sumy += a[i].second; } pair<int, int> cent = make_pair(sumx, sumy); for (int i = 1; i <= 3; i++) { a[i].first *= 3; a[i].second *= 3; a[i].first -= cent.first; a[i].second -= cent.second; point t(a[i].first, a[i].second); s.insert(t); } for (int i = 4; i <= n; i++) { cin >> c >> x >> y; x *= 3; y *= 3; x -= cent.first; y -= cent.second; point t(x, y); if (c == 1) { set<point>::iterator left = something_stupid_(t); set<point>::iterator right = _something_stupid(left); if (ccw(*left, *right, t) <= 0) continue; while (s.size() >= 2 and ccw(t, *left, *something_stupid_(left)) <= 0) { set<point>::iterator it = left; left = something_stupid_(left); s.erase(it); } right = _something_stupid(left); while (s.size() >= 2 and ccw(t, *right, *_something_stupid(right)) >= 0) { set<point>::iterator it = right; right = _something_stupid(right); s.erase(it); } s.insert(t); } else { set<point>::iterator left = something_stupid_(t); set<point>::iterator right = _something_stupid(left); if (ccw(*left, *right, t) <= 0) cout << YES << n ; else cout << NO << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200 * 1000 + 10; struct edge { int u, v, w; edge() {} edge(int u, int v, int w) : u(u), v(v), w(w) {} } e[N]; vector<int> vec[N]; int n, m, root[N], mx[35][N], par[35][N], h[N], ans[N]; bool mst[N], mark[N]; multiset<int> add[N], rem[N]; bool cmp(int i, int j) { return e[i].w < e[j].w; } int dfs(int v) { mark[v] = true; for (int ind : vec[v]) { int u = e[ind].u + e[ind].v - v; if (mst[ind]) { if (!mark[u]) { h[u] = h[v] + 1; par[0][u] = v; mx[0][u] = e[ind].w; ans[ind] = dfs(u); if ((int)add[u].size() > (int)add[v].size()) swap(add[u], add[v]); for (int x : add[u]) add[v].insert(x); } } } for (int x : rem[v]) add[v].erase(add[v].find(x)); if (add[v].empty()) return -1; return *add[v].begin() - 1; } void fill_par() { for (int i = 0; i < n; i++) mark[i] = false; for (int i = 0; i < 31; i++) for (int j = 0; j < n; j++) par[i][j] = -1; dfs(0); for (int i = 1; i < 31; i++) for (int j = 0; j < n; j++) if (par[i - 1][j] != -1) { mx[i][j] = max(mx[i - 1][j], mx[i - 1][par[i - 1][j]]); par[i][j] = par[i - 1][par[i - 1][j]]; } } int get_root(int v) { if (v == root[v]) return v; return root[v] = get_root(root[v]); } pair<int, int> get_lca(int u, int v) { if (h[u] < h[v]) swap(u, v); int mxe = 0; for (int i = 30; i >= 0; i--) if ((h[u] - h[v]) & (1 << i)) { mxe = max(mxe, mx[i][u]); u = par[i][u]; } for (int i = 30; i >= 0; i--) if (par[i][u] != par[i][v]) { mxe = max(mxe, mx[i][v]), mxe = max(mxe, mx[i][u]); u = par[i][u], v = par[i][v]; } if (u != v) { mxe = max(mxe, mx[0][v]), mxe = max(mxe, mx[0][u]); u = par[0][u]; } return {u, mxe}; } void merge(int ind, int ty) { int u = e[ind].u, v = e[ind].v; int pu = get_root(u), pv = get_root(v); if (pu != pv) { mst[ind] = true; root[pu] = pv; } if (pu != pv || !ty) return; ans[ind] = (get_lca(u, v)).second - 1; } void merge() { for (int i = 0; i < n; i++) root[i] = i; vector<int> temp(m); iota(temp.begin(), temp.end(), 0); sort(temp.begin(), temp.end(), cmp); for (int i = 0; i < m; i++) merge(temp[i], 0); fill_par(); for (int i = 0; i < m; i++) if (!mst[i]) { int u = e[i].u, v = e[i].v; int lca = get_lca(u, v).first; add[u].insert(e[i].w); add[v].insert(e[i].w); rem[lca].insert(e[i].w); rem[lca].insert(e[i].w); } fill_par(); for (int i = 0; i < n; i++) root[i] = i; for (int i = 0; i < m; i++) merge(temp[i], 1); } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; u--, v--; e[i] = edge(u, v, w); vec[u].push_back(i); vec[v].push_back(i); } merge(); for (int i = 0; i < m; i++) cout << ans[i] << n [i == m - 1]; return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef struct { long long v; long long c; } double_pair; struct line { long long k, b; line() {} line(long long _k, long long _b) : k(_k), b(_b) {} long long Solve(long long val) { long long _a = val - b, _b = k; if (_a % _b == 0) return _a / _b; else return _a / _b + 1; } long long f(long long x) { return k * x + b; } }; double_pair D[300000]; int n; line St[300000]; int top; long long X[300000], s; long long intersection(line a, line b) { long long _a = a.b - b.b, _b = b.k - a.k; if (_a % _b == 0) return _a / _b; else return _a / _b + 1; } bool slope_compare(double_pair d1, double_pair d2) { return ((d1.c < d2.c) || (d1.c == d2.c && d1.v > d2.v)); } bool check(long long x, long long _s) { if (x > X[top - 1]) return x >= St[top].Solve(_s); int pos = lower_bound(X + 1, X + top, x) - X; if (X[pos] == x) pos++; return x >= St[pos].Solve(_s); } long long chat(long long _s) { long long l = 0, r = _s, mid; while (l + 1 < r) { mid = (l + r) >> 1; if (check(mid, _s)) r = mid; else l = mid; } return r; } void find_hull() { St[++top] = line(D[0].v, -D[0].c); long long i1, i2; for (int i = 1; i < n; ++i) { long long x0 = chat(D[i].c); long long p = lower_bound(X + 1, X + top, x0) - X; long long y0 = St[p + (X[p] == x0)].k * x0 + St[p + (X[p] == x0)].b - D[i].c; line tmp(D[i].v, y0 - x0 * D[i].v); while (top >= 2 && (((i1 = intersection(tmp, St[top])) <= (i2 = intersection(St[top], St[top - 1])) || (i1 == i2 && tmp.f(i1) >= St[top].f(i1))))) --top; St[++top] = tmp; X[top - 1] = intersection(St[top], St[top - 1]); } } int main() { cin >> n >> s; for (int i = 1; i <= n; i++) cin >> D[i].v >> D[i].c; sort(D + 1, D + n + 1, slope_compare); int tmp_n = n, maxv = 0; n = 0; for (int i = 1; i <= tmp_n; i++) { if (maxv >= D[i].v) continue; maxv = D[i].v; D[n++] = D[i]; } find_hull(); cout << chat(s); return 0; }
|
#include <bits/stdc++.h> using namespace std; void redondear(string &s, int pto, int idx) { if (idx == (int)(s.size())) { cout << s << endl; return; } s.resize(idx); bool unoAdelante = false; for (int i = (idx)-1; i >= (int)(0); i--) { if (i == pto) { continue; } if (i == 0 && s[i] == 9 ) { s[i] = 0 ; unoAdelante = true; continue; } if (s[i] == 9 ) { s[i] = 0 ; } else { s[i]++; break; } } if (unoAdelante) cout << 1 ; if (s[s.size() - 1] == . ) { s.resize(s.size() - 1); } cout << s << endl; } int main() { int largo, segundos; cin >> largo >> segundos; string nota; cin >> nota; int punto = 0; for (int i = (0); i < (int)(nota.size()); i++) { if (nota[i] == . ) { punto = i; break; } } int minimoIndice = largo; int turnosUsados = 0; for (int i = (largo)-1; i >= (int)(punto + 1); i--) { if (nota[i] >= 5 ) { minimoIndice = i; turnosUsados = 1; } else if (nota[i] == 4 && turnosUsados < segundos && turnosUsados > 0) { minimoIndice = i; turnosUsados++; } else { turnosUsados = 0; } } redondear(nota, punto, minimoIndice); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, i, sum = 0, k, l = 10000000000; cin >> n; for (i = 1; i <= n; i++) { cin >> a; sum += a; if (a % 2) l = min(l, a); } if (sum % 2 == 1) sum -= l; cout << sum << endl; }
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_timers(
input rst,
input clk,
input cen,
input zero,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
jt51_timer #(.CW(10)) timer_A(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.flag ( flag_A ),
.overflow ( overflow_A)
);
jt51_timer #(.CW(8),.FREE_EN(1)) timer_B(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
module jt51_timer #(parameter
CW = 8, // counter bit width. This is the counter that can be loaded
FREE_EN = 0 // enables a 4-bit free enable count
) (
input rst,
input clk,
input cen,
input zero,
input [CW-1:0] start_value,
input load,
input clr_flag,
output reg flag,
output reg overflow
);
reg last_load;
reg [CW-1:0] cnt, next;
reg [ 3:0] free_cnt, free_next;
reg free_ov;
always@(posedge clk, posedge rst)
if( rst )
flag <= 1'b0;
else /*if(cen)*/ begin
if( clr_flag )
flag <= 1'b0;
else if(overflow) flag<=1'b1;
end
always @(*) begin
{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
/* verilator lint_off WIDTH */
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
/* verilator lint_on WIDTH */
end
always @(posedge clk) if(cen && zero) begin : counter
last_load <= load;
if( (load && !last_load) || overflow ) begin
cnt <= start_value;
end
else if( last_load ) cnt <= next;
end
// Free running counter
always @(posedge clk) begin
if( rst ) begin
free_cnt <= 4'd0;
end else if( cen&&zero ) begin
free_cnt <= free_cnt+4'd1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 5; char s[maxn]; int vis[maxn], a[maxn]; int main() { int n; scanf( %d , &n); scanf( %s , s + 1); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); memset(vis, 0, sizeof(vis)); int x = 1; while (1) { if (vis[x]) { printf( INFINITE n ); break; } vis[x] = 1; int nx = 0; if (s[x] == > ) x = x + a[x]; else x = x - a[x]; if (x < 1 || x > n) { printf( FINITE n ); break; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100007; int n, m, q[N], a[N], mn = 100000007, k, l; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> m; for (int i = 0; i < m; i++) { cin >> q[i]; mn = min(mn, q[i]); } cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = n - 1; i >= 0; i--) { k += a[i]; l++; if (l == mn) { l = 0; if (i == 1) i--; else if (i >= 2) i -= 2; } } cout << k; return 0; }
|
// $Id: vcr_crossbar_mac.v 1687 2009-11-06 23:41:57Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// configurable crossbar module for VC router
module vcr_crossbar_mac
(clk, reset, ctrl_ip_op, data_in_ip, data_out_op);
`include "c_constants.v"
// number of input/output ports
parameter num_in_ports = 5;
parameter num_out_ports = 5;
// width per port
parameter width = 32;
// select implementation variant
parameter crossbar_type = `CROSSBAR_TYPE_MUX;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// crosspoint control signals
input [0:num_in_ports*num_out_ports-1] ctrl_ip_op;
// vector of input data
input [0:num_in_ports*width-1] data_in_ip;
// vector of output data
output [0:num_out_ports*width-1] data_out_op;
wire [0:num_out_ports*width-1] data_out_op;
wire [0:num_in_ports*num_out_ports-1] ctrl_ip_op_s, ctrl_ip_op_q;
assign ctrl_ip_op_s = ctrl_ip_op;
c_dff
#(.width(num_in_ports*num_out_ports),
.reset_type(reset_type))
ctrl_ip_opq
(.clk(clk),
.reset(reset),
.d(ctrl_ip_op_s),
.q(ctrl_ip_op_q));
c_crossbar
#(.num_in_ports(num_in_ports),
.num_out_ports(num_out_ports),
.width(width),
.crossbar_type(crossbar_type))
xbr
(.ctrl_ip_op(ctrl_ip_op_q),
.data_in_ip(data_in_ip),
.data_out_op(data_out_op));
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ROM_D.v when simulating
// the core, ROM_D. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ROM_D(
a,
spo
);
input [9 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(10),
.C_DEFAULT_DATA("0"),
.C_DEPTH(1024),
.C_FAMILY("kintex7"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("ROM_D.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32)
)
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int mera[100001]; int snct[100001]; string s; cin >> s; int len = s.length(); stack<int> st; if (s[0] == [ ) { snct[0] = 1; } else { snct[0] = 0; } for (int i = 1; i < len; i++) { snct[i] = snct[i - 1]; if (s[i] == [ ) { snct[i]++; } } for (int i = 0; i < len; i++) { mera[i] = -1; if (s[i] == ( || s[i] == [ ) { st.push(i); } else if (s[i] == ) ) { if (!st.empty()) { int h = st.top(); if (h != -1 && s[h] == ( ) { mera[i] = h; st.pop(); } else { st.push(-1); } } } else { if (!st.empty()) { int h = st.top(); if (h != -1 && s[h] == [ ) { mera[i] = h; st.pop(); } else { st.push(-1); } } } } for (int i = 0; i < len; i++) { if (mera[i] != -1 && mera[i] > 0 && mera[mera[i] - 1] != -1) { mera[i] = mera[mera[i] - 1]; } } int max = 0; int x = -1; for (int i = 0; i < len; i++) { if (mera[i] != -1) { int c = snct[i]; if (mera[i] > 0) c -= snct[mera[i] - 1]; if (c > max) { x = i; max = c; } } } cout << max << endl; if (max > 0) cout << s.substr(mera[x], x - mera[x] + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> vec; set<int> st; for (int i = 0; i < int(n); ++i) { int a; cin >> a; st.insert(i); vec.push_back(a); } queue<int> tok; int ans = 0; int killed = 0; for (int i = n - 1; i > 0; i--) { if (vec[i] < vec[i - 1]) { st.erase(i); ++killed; tok.push(i - 1); } } if (killed) ans++; queue<int> qtok; while (killed) { killed = 0; while (!tok.empty()) { int tp = tok.front(); tok.pop(); auto it = st.find(tp); if (it == st.end()) continue; auto itn = st.find(tp); itn++; if (itn == st.end()) continue; if (vec[*it] > vec[*itn]) { qtok.push(*it); ++killed; st.erase(itn); } } while (!qtok.empty()) { tok.push(qtok.front()); qtok.pop(); } if (killed) ans++; } cout << ans << endl; return 0; }
|
//////////////////////////////////////////////////////////////////
// //
// Wishbone Slave to Xilinx Spartan-6 MCB (DDR3 controller) //
// Bridge //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Converts wishbone read and write accesses to the signalling //
// used by the Xilinx DDR3 Controller in Spartan-6 FPGAs. //
// //
// The MCB is configured with a single 128-bit port. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
module wb_xs6_ddr3_bridge #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
input i_clk,
input i_mem_ctrl, // 0=128MB, 1=32MB
// Wishbone Bus
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output reg [WB_DWIDTH-1:0] o_wb_dat = 'd0,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err,
output o_cmd_en, // Command Enable
output reg [2:0] o_cmd_instr = 'd0, // write = 000, read = 001
output reg [29:0] o_cmd_byte_addr = 'd0, // Memory address
input i_cmd_full, // DDR3 I/F Command FIFO is full
input i_wr_full, // DDR3 I/F Write Data FIFO is full
output o_wr_en, // Write data enable
output reg [15:0] o_wr_mask = 'd0, // 1 bit per byte
output reg [127:0] o_wr_data = 'd0, // 16 bytes write data
input [127:0] i_rd_data, // 16 bytes of read data
input i_rd_empty // low when read data is valid
);
wire write_request;
wire read_request;
reg write_request_r;
reg read_request_r;
reg read_active_r = 'd0;
reg [29:0] wb_adr_r;
reg cmd_full_r = 1'd0;
reg read_ack_r = 'd0;
reg read_ready = 1'd1;
reg cmd_en_r = 'd0;
reg wr_en_r = 'd0;
wire write_ack;
// Buffer 1 write request
reg write_buf_r = 1'd0;
reg [WB_SWIDTH-1:0] wb_sel_buf_r = 'd0;
reg [WB_DWIDTH-1:0] wb_dat_buf_r = 'd0;
reg [31:0] wb_adr_buf_r = 'd0;
wire [WB_SWIDTH-1:0] wb_sel;
wire [WB_DWIDTH-1:0] wb_dat;
wire [31:0] wb_adr;
assign write_request = i_wb_stb && i_wb_we && !read_request_r;
assign read_request = i_wb_stb && !i_wb_we && read_ready;
assign o_wb_err = 'd0;
// ------------------------------------------------------
// Outputs
// ------------------------------------------------------
always @( posedge i_clk )
cmd_full_r <= i_cmd_full;
// Command FIFO
always @( posedge i_clk )
if ( !i_cmd_full )
begin
o_cmd_byte_addr <= {wb_adr_r[29:4], 4'd0};
cmd_en_r <= ( write_request_r || read_request_r );
o_cmd_instr <= write_request_r ? 3'd0 : 3'd1;
end
assign o_cmd_en = cmd_en_r && !i_cmd_full;
// ------------------------------------------------------
// Write Buffer
// ------------------------------------------------------
always @( posedge i_clk )
if ( i_cmd_full && write_request )
begin
write_buf_r <= 1'd1;
wb_sel_buf_r <= i_wb_sel;
wb_dat_buf_r <= i_wb_dat;
wb_adr_buf_r <= i_wb_adr;
end
else if ( !i_cmd_full )
write_buf_r <= 1'd0;
// ------------------------------------------------------
// Write
// ------------------------------------------------------
// Select between incoming reqiests and the write request buffer
assign wb_sel = write_buf_r ? wb_sel_buf_r : i_wb_sel;
assign wb_dat = write_buf_r ? wb_dat_buf_r : i_wb_dat;
assign wb_adr = write_buf_r ? wb_adr_buf_r : i_wb_adr;
generate
if (WB_DWIDTH == 32) begin :wb32w
always @( posedge i_clk )
if ( !i_cmd_full )
begin
wr_en_r <= write_request || write_buf_r;
o_wr_mask <= wb_adr[3:2] == 2'd0 ? { 12'hfff, ~wb_sel } :
wb_adr[3:2] == 2'd1 ? { 8'hff, ~wb_sel, 4'hf } :
wb_adr[3:2] == 2'd2 ? { 4'hf, ~wb_sel, 8'hff } :
{ ~wb_sel, 12'hfff } ;
o_wr_data <= {4{wb_dat}};
end
end
else begin : wb128w
always @( posedge i_clk )
if ( !i_cmd_full )
begin
wr_en_r <= write_request;
o_wr_mask <= ~wb_sel;
o_wr_data <= wb_dat;
end
end
endgenerate
assign o_wr_en = wr_en_r && !i_cmd_full;
// ------------------------------------------------------
// Read
// ------------------------------------------------------
always @( posedge i_clk )
begin
if ( read_ack_r )
read_ready <= 1'd1;
else if ( read_request )
read_ready <= 1'd0;
if ( !i_cmd_full )
begin
write_request_r <= write_request;
read_request_r <= read_request;
wb_adr_r <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
end
if ( read_request )
read_active_r <= 1'd1;
else if ( read_ack_r )
read_active_r <= 1'd0;
if ( i_rd_empty == 1'd0 && read_active_r )
read_ack_r <= 1'd1;
else
read_ack_r <= 1'd0;
end
generate
if (WB_DWIDTH == 32) begin :wb32r
always @( posedge i_clk )
if ( !i_rd_empty && read_active_r )
o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
i_rd_data[127:96] ;
end
else begin : wb128r
always @( posedge i_clk )
if ( !i_rd_empty && read_active_r )
o_wb_dat <= i_rd_data;
end
endgenerate
assign write_ack = write_request && !write_buf_r;
assign o_wb_ack = ( i_wb_stb && read_ack_r ) || write_ack;
endmodule
|
#include <bits/stdc++.h> int a, b, c, prad[1000001]; using namespace std; int main() { long long pro = 0; for (int i = 1; i < 1000001; ++i) { for (int j = 1; j * i < 1000001; ++j) { ++prad[j * i]; } } cin >> a >> b >> c; for (int j = 1; j < a + 1; ++j) for (int ja = 1; ja < b + 1; ++ja) for (int ha = 1; ha < c + 1; ++ha) { pro += prad[ha * ja * j]; long long ta = pro >> 30; ta << 30; pro = pro - ta; } cout << pro; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
// Module ports
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFDS_GTE3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 08/28/2013 - Initial model
// 06/02/14 - New simulation library message format.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTE3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input [3:0] I,
input [1:0] RXRECCLK_SEL
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE3_ADV";
reg I_delay;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [4:0] REFCLK_ICNTL_TX_BIN;
tri0 GTS = glbl.GTS;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE3_ADV_dr.v"
`endif
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG;
wire t1;
wire t2;
or O1 (t1, GTS, CEB);
or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1);
// =====================
// Generate I_delay
// =====================
always @(*) begin
case (RXRECCLK_SEL)
2'b00: I_delay <= I[0];
2'b01: I_delay <= I[1];
2'b10: I_delay <= I[2];
2'b11: I_delay <= I[3];
default : I_delay <= I[0];
endcase
end
bufif0 B1 (O, I_delay, t2);
notif0 N1 (OB, I_delay, t2);
specify
(I[0] => O) = (0:0:0, 0:0:0);
(I[0] => OB) = (0:0:0, 0:0:0);
(I[1] => O) = (0:0:0, 0:0:0);
(I[1] => OB) = (0:0:0, 0:0:0);
(I[2] => O) = (0:0:0, 0:0:0);
(I[2] => OB) = (0:0:0, 0:0:0);
(I[3] => O) = (0:0:0, 0:0:0);
(I[3] => OB) = (0:0:0, 0:0:0);
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_saturation_encud_div_u
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1];
//------------------------Body---------------------------
assign quot = dividend_tmp[in0_WIDTH];
assign remd = remd_tmp[in0_WIDTH];
// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
always @(posedge clk)
begin
if (ce) begin
dividend_tmp[0] <= dividend;
divisor_tmp[0] <= divisor;
remd_tmp[0] <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < in0_WIDTH; i = i + 1)
begin : loop
if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0];
else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
always @(posedge clk)
begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
divisor_tmp[i+1] <= divisor_tmp[i];
remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
end
end
end
endgenerate
endmodule
module hls_saturation_encud_div
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
//------------------------Instantiation------------------
hls_saturation_encud_div_u #(
.in0_WIDTH ( in0_WIDTH ),
.in1_WIDTH ( in1_WIDTH ),
.out_WIDTH ( out_WIDTH )
) hls_saturation_encud_div_u_0 (
.clk ( clk ),
.reset ( reset ),
.ce ( ce ),
.dividend ( dividend_u ),
.divisor ( divisor_u ),
.quot ( quot_u ),
.remd ( remd_u )
);
//------------------------Body---------------------------
assign dividend_u = dividend0;
assign divisor_u = divisor0;
always @(posedge clk)
begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
end
end
always @(posedge clk)
begin
if (ce) begin
quot <= quot_u;
remd <= remd_u;
end
end
endmodule
`timescale 1 ns / 1 ps
module hls_saturation_encud(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
wire[dout_WIDTH - 1:0] sig_remd;
hls_saturation_encud_div #(
.in0_WIDTH( din0_WIDTH ),
.in1_WIDTH( din1_WIDTH ),
.out_WIDTH( dout_WIDTH ))
hls_saturation_encud_div_U(
.dividend( din0 ),
.divisor( din1 ),
.quot( dout ),
.remd( sig_remd ),
.clk( clk ),
.ce( ce ),
.reset( reset ));
endmodule
|
#include <queue> #include <cstdio> #include <algorithm> const int Maxn=200; const int Maxl=40; const int Mod=998244353; int n,m; namespace Trie{ struct Trie_Node{ int ch[26]; bool pos; }node[Maxl+5]; int id_tot; void insert(char *s,int len){ int root=0; for(int i=1;i<=len;i++){ if(node[root].ch[s[i]- a ]==0){ node[root].ch[s[i]- a ]=++id_tot; } root=node[root].ch[s[i]- a ]; } node[root].pos=1; } } struct Node{ int id,x,y; Node(int _id=0,int _x=0,int _y=0){ id=_id,x=_x,y=_y; } }; std::queue<Node> q; int id[Maxl+5][Maxl+5],id_tot; int get_id(int x,int y){ if(x>y){ std::swap(x,y); } if(id[x][y]==0){ id[x][y]=++id_tot; q.push(Node(id[x][y],x,y)); } return id[x][y]; } struct Matrix{ int a[Maxn+5][Maxn+5]; void init(){ for(int i=1;i<=id_tot;i++){ for(int j=1;j<=id_tot;j++){ a[i][j]=0; } } } friend Matrix operator *(Matrix a,Matrix b){ Matrix ans; ans.init(); for(int i=1;i<=id_tot;i++){ for(int k=1;k<=id_tot;k++){ for(int j=1;j<=id_tot;j++){ ans.a[i][j]=(ans.a[i][j]+1ll*a.a[i][k]*b.a[k][j])%Mod; } } } return ans; } }g; int main(){ scanf( %d%d ,&n,&m); for(int i=1;i<=n;i++){ static char s[Maxl+5]; scanf( %s ,s+1); int len=0; while(s[++len]!= 0 ); len--; Trie::insert(s,len); } get_id(0,0); while(!q.empty()){ Node u=q.front(); q.pop(); for(int i=0;i<26;i++){ int a=Trie::node[u.x].ch[i],b=Trie::node[u.y].ch[i]; if(a==0||b==0){ continue; } g.a[u.id][get_id(a,b)]++; if(Trie::node[a].pos){ g.a[u.id][get_id(0,b)]++; } if(Trie::node[b].pos){ g.a[u.id][get_id(a,0)]++; } if(Trie::node[a].pos&&Trie::node[b].pos){ g.a[u.id][get_id(0,0)]++; } } } Matrix ans; ans.init(); for(int i=1;i<=id_tot;i++){ ans.a[i][i]=1; } while(m){ if(m&1){ ans=ans*g; } g=g*g; m>>=1; } printf( %d n ,ans.a[1][1]); return 0; }
|
#include <bits/stdc++.h> int n, m, a[210], f[210][210][1010], ans; inline void up(int &x, int y) { if ((x += y) >= 1000000007) x -= 1000000007; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); std::sort(a + 1, a + n + 1); f[1][1][0] = f[1][0][0] = 1; for (int i = 1; i < n; i++) { int delta = a[i + 1] - a[i], next; for (int j = 0; j <= n; j++) { for (int k = 0; k <= m; k++) { if ((next = k + j * delta) > m) continue; if (!f[i][j][k]) continue; if (j > 0) up(f[i + 1][j - 1][next], 1LL * f[i][j][k] * j % 1000000007); up(f[i + 1][j][next], 1LL * f[i][j][k] * (j + 1) % 1000000007); up(f[i + 1][j + 1][next], f[i][j][k]); } } } for (int i = 0; i <= m; i++) up(ans, f[n][0][i]); printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> char a[1002][34], b[34]; int point[1002], res[1002], h[1002]; int main() { int n, x, i, j, p = 1; scanf( %d , &n); scanf( %s %d , &a[0], &x); point[0] += x; h[0] = point[0]; res[0] = 0; for (i = 1; i < n; i++) { scanf( %s %d , &b, &x); for (j = 0; j < p; j++) { if (strcmp(a[j], b) == 0) { break; } } if (i == p) { strcpy(a[p], b); p++; } point[j] += x; h[i] = point[j]; res[i] = j; } int max = point[0]; for (i = 1; i < p; i++) { if (point[i] > max) max = point[i]; } for (i = 0; i < n; i++) { if (point[res[i]] == max && h[i] >= max) break; } printf( %s , a[res[i]]); }
|
#include <bits/stdc++.h> using namespace std; long long n; int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n; long long a = (n + 2) * (n + 1) * n / 6, b = (n + 4) * (n + 3) * (n + 2) * (n + 1) * n / 120; cout << a * b; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, o = 0, x = 0; cin >> n; for (int i = 0; i < n; i++) { int a; cin >> a; if (a) x++; else o++; } int s = x / 9; if (s && o) { for (int i = 0; i < 9 * s; i++) { cout << 5; } for (int i = 0; i < o; i++) { cout << 0; } } else if (o) cout << 0; else cout << -1; return 0; }
|
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
end else
if (WIDTH == 2) begin
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(1'b0), .I2(A[0]), .I3(A[1]));
end else
if (WIDTH == 3) begin
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(1'b0), .I1(A[0]), .I2(A[1]), .I3(A[2]));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sum[500000 + 10]; int data[500000 + 10]; int main() { int n, l, r, ql, qr; scanf( %d%d%d%d%d , &n, &l, &r, &ql, &qr); for (int i = 1; i <= n; ++i) { scanf( %d , &data[i]); sum[i] += (sum[i - 1] + data[i] * r); } long long ans = 100000000000000; long long tem = 0; for (int i = 0; i <= n; ++i) { tem += data[i] * l; if (0 == i) ans = min(ans, sum[n] + (n - 1) * qr); else if (n == i) ans = min(ans, tem + (n - 1) * ql); else if (i == (n - i)) { ans = min(ans, tem + sum[n] - sum[i]); } else if (i < (n - i)) ans = min(ans, tem + sum[n] - sum[i] + (n - i - i - 1) * qr); else ans = min(ans, tem + sum[n] - sum[i] + (2 * i - n - 1) * ql); } cout << ans << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jun 27 15:34:40 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_UAMN ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.4 2006/07/04 09:54:10 wig Exp $
// $Date: 2006/07/04 09:54:10 $
// $Log: ent_a.v,v $
// Revision 1.4 2006/07/04 09:54:10 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
`ifdef MAGMA
`define ent_aa_inst_name ent_aa
`else
`define ent_aa_inst_name ent_aa_rtl_conf
`endif
`ifdef MAGMA
`define ent_ad_inst_name ent_ad
`else
`define ent_ad_inst_name ent_ad_rtl_conf
`endif
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
`ent_aa_inst_name inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
`ent_ad_inst_name inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_TB_V
`define SKY130_FD_SC_HDLL__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int get(int a) { int maxx = 0; for (int i = 0; i < 21; i++) if (a & (1 << i)) maxx = i; int ans = (1 << (maxx + 1)) - 1; return (ans ^ a); } int main() { int n; cin >> n; vector<int> a(n + 1); for (int i = n; i >= 0; i--) { if (a[i] == 0) { for (int j = 21; j >= 0; j--) { int tmp = get(i); if ((i ^ tmp) == i + tmp && a[tmp] == 0) { a[tmp] = i; a[i] = tmp; break; } } } } long long ans = 0; for (int i = 0; i <= n; i++) ans += (a[i] ^ i); cout << ans << endl; for (int i = 0; i <= n; i++) cout << a[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long mul(long long x, long long y) { if (x >= (1ll << 60) / y) return (1ll << 60); else return x * y; } int n, m, p; int d[100005]; long long cat[100005], sum[100005]; long long dp[105][100005]; int dq[100005], s, e; int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 2; i <= n; ++i) scanf( %d , d + i), d[i] += d[i - 1]; for (int i = 1; i <= m; ++i) { int h, t; scanf( %d%d , &h, &t); cat[i] = t - d[h] + 1000000000; } sort(cat + 1, cat + 1 + m); for (int i = 1; i <= m; ++i) sum[i] = sum[i - 1] + cat[i]; memset(dp, 63, sizeof(dp)); for (int i = 0; i < 105; ++i) dp[i][0] = 0; for (int k = 1; k <= p; ++k) { dq[0] = 0, s = 0, e = 1; for (int i = 1; i <= m; ++i) { long long c1 = cat[i], c2 = i * c1 - sum[i]; while (s + 1 < e) { long long x1 = dq[s], y1 = dp[k - 1][x1] + sum[x1]; long long x2 = dq[s + 1], y2 = dp[k - 1][x2] + sum[x2]; if ((y2 - y1) <= mul(c1, (x2 - x1))) s++; else break; } int t = dq[s]; dp[k][i] = min(dp[k][i], dp[k - 1][t] + sum[t] - c1 * t + c2); while (s + 1 < e) { long long x1 = i, y1 = dp[k - 1][i] + sum[i]; long long x2 = dq[e - 1], y2 = dp[k - 1][x2] + sum[x2]; long long x3 = dq[e - 2], y3 = dp[k - 1][x3] + sum[x3]; if (mul((y1 - y2), (x2 - x3)) <= mul((y2 - y3), (x1 - x2))) e--; else break; } dq[e++] = i; } } printf( %I64d n , dp[p][m]); }
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
`timescale 1ns / 1ps
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [8:0] Output;
wire [8:0] Input = crc[8:0];
assigns assigns (/*AUTOINST*/
// Outputs
.Output (Output[8:0]),
// Inputs
.Input (Input[8:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module assigns(Input, Output);
input [8:0] Input;
output [8:0] Output;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k, a[205], b[205]; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; for (int j = 1; j <= k; j++) cin >> b[j]; if (k >= 2) { cout << Yes << endl; return 0; } if (a[1] == 0) a[1] = b[1]; for (int i = 2; i <= n; i++) { if (a[i] == 0) a[i] = b[1]; if (a[i] <= a[i - 1]) { cout << Yes << endl; return 0; } } cout << No << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { return b ? GCD(b, a % b) : a; } const long long N = 2e5 + 7; const long long inf = 1e6 + 1; const long long mod = 998244353; int t, n, m, a[N]; struct node { int def, s; bool operator<(const node& a) const { return def < a.def; } } b[N]; bool cmp(const node& a, int x) { return a.def < x; } int main() { cin >> t; while (t--) { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; cin >> m; for (int i = 1; i <= m; i++) cin >> b[i].def >> b[i].s; sort(b + 1, b + 1 + m); for (int i = m - 1; i >= 1; i--) { b[i].s = max(b[i].s, b[i + 1].s); } bool ok = true; int minn = 2 * n, ans = 0, last = 0; for (int i = 1; i <= n; i++) { int q = lower_bound(b + 1, b + 1 + m, a[i], cmp) - b; if (q > m) { ok = false; break; } minn = min(minn, b[q].s); if (last + minn < i) { ans++; last = i - 1; minn = b[q].s; } } if (ok == false) cout << -1 n ; else cout << ans + 1 << n ; } return 0; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
module saxi_test (/*AUTOARG*/
// Outputs
ERROR, DONE, s_axi_awready, s_axi_wready, s_axi_bid, s_axi_bresp,
s_axi_bvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid,
// Inputs
s_axi_aclk, s_axi_aresetn, s_axi_awid, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awqos, s_axi_wid, s_axi_wdata,
s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst,
s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
s_axi_arqos, s_axi_rready
);
// Parameters (Connects to DUT master)
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter MSTW = 8; //Number of strobes
/*****************************/
/*TESTBENCH SIGNALS */
/*****************************/
output ERROR;
output DONE;
/*****************************/
/*AXI SLAVE I/F */
/*****************************/
//Global signals
input s_axi_aclk; //clock source for axi master/slave interfaces
input s_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
input [MIDW-1:0] s_axi_awid; //write address ID
input [MAW-1:0] s_axi_awaddr; //write address
input [3:0] s_axi_awlen; //burst length (number of data transfers)
input [2:0] s_axi_awsize; //burst size (size of each transfer)
input [1:0] s_axi_awburst; //burst type
input [1:0] s_axi_awlock; //lock type (atomic characteristics)
input [3:0] s_axi_awcache; //memory type
input [2:0] s_axi_awprot; //protection type
input s_axi_awvalid; //write address valid
input [3:0] s_axi_awqos; //quality of service default 4'b0000
output s_axi_awready; //write address ready
//Write data channel
input [MIDW-1:0] s_axi_wid; //write ID tag (supported only in AXI3)
input [MDW-1:0] s_axi_wdata; //write data
input [MSTW-1:0] s_axi_wstrb; //write strobes
input s_axi_wlast; //indicates last write transfer in burst
input s_axi_wvalid; //write valid
output s_axi_wready; //write channel ready
//Buffered write response channel
input s_axi_bready; //write ready
output [MIDW-1:0] s_axi_bid; //response ID tag
output [1:0] s_axi_bresp; //write response
output s_axi_bvalid; //write response valid
//Read address channel
input [MIDW-1:0] s_axi_arid; //read address ID
input [MAW-1:0] s_axi_araddr; //read address
input [3:0] s_axi_arlen; //burst lenght (number of data transfers)
input [2:0] s_axi_arsize; //burst size (size of each transfer)
input [1:0] s_axi_arburst; //burst type
input [1:0] s_axi_arlock; //lock type (atomic characteristics)
input [3:0] s_axi_arcache; //memory type
input [2:0] s_axi_arprot; //protection type
input s_axi_arvalid; //read address valid
input [3:0] s_axi_arqos; //quality of service default 4'b0000
output s_axi_arready; //read address ready
//Read data channel
output [MIDW-1:0] s_axi_rid; //read ID tag
output [MDW-1:0] s_axi_rdata; //read data
output [1:0] s_axi_rresp; //read response
output s_axi_rlast; //indicates last read transfer in burst
output s_axi_rvalid; //read valid
input s_axi_rready; //read ready
initial begin
ERROR <= 1'b0;
DONE <= 1'b0;
end
wire s_axi_awready = 1'b1;
//Write data channel
wire s_axi_wready = 1'b1;
//Buffered write response channel
reg [MIDW-1:0] s_axi_bid;
wire [1:0] s_axi_bresp;
reg s_axi_bvalid;
always @ (posedge s_axi_aclk or negedge s_axi_aresetn) begin
if(~s_axi_aresetn) begin
s_axi_bid <= {MIDW{1'b0}};
s_axi_bvalid <= 1'b0;
end else begin
if(s_axi_wvalid && s_axi_wready) begin
s_axi_bid <= s_axi_wid;
s_axi_bvalid <= 1'b1;
end else if(s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end // else: !if(~s_axi_aresetn)
end // always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
//Read address channel
reg s_axi_arready;
always @ (posedge s_axi_aclk or negedge s_axi_aresetn) begin
if(~s_axi_aresetn) begin
s_axi_arready <= 1'b0;
end else begin
//Read data channel
reg [MIDW-1:0] s_axi_rid;
reg [MDW-1:0] s_axi_rdata;
reg [1:0] s_axi_rresp;
wire s_axi_rlast = 1'b1; // No bursting for now, so always last beat
reg s_axi_rvalid;
endmodule // saxi_test
// Local Variables:
// verilog-library-directories:("." "../elink" "../axi")
// End:
|
#include <bits/stdc++.h> using namespace std; const int INF = 1.01e9; const double PI = acos(-1); bool eq(double A, double B) { return abs(A - B) < 1e-9; } bool ls(double A, double B) { return A < B && !eq(A, B); } bool le(double A, double B) { return A < B || eq(A, B); } struct pt { double x, y, id; pt() {} pt(double xx, double yy) : x(xx), y(yy) {} pt operator+(pt A) { return pt(x + A.x, y + A.y); } pt operator-(pt A) { return pt(x - A.x, y - A.y); } pt operator*(double k) { return pt(x * k, y * k); } pt operator/(double k) { assert(abs(k) > 1e-20); return pt(x / k, y / k); } double operator*(pt A) { return x * A.y - y * A.x; } double operator%(pt A) { return x * A.x + y * A.y; } bool operator==(pt A) { return eq(x, A.x) && eq(y, A.y); } bool operator!=(pt A) { return !eq(x, A.x) || !eq(y, A.y); } double len() { return sqrt(x * x + y * y); } double len2() { return x * x + y * y; } pt rotate() { return pt(-y, x); } pt norm() { return (*this) / len(); } bool operator<(pt A) { return x < A.x || (eq(x, A.x) && ls(y, A.y)); } void read() { scanf( %lf%lf , &x, &y); } void Epr() { cerr << x y: << x << << y << endl; } }; struct Line { pt O, v; Line(pt A, pt B) : O(A), v((B - A).norm()) {} pt operator*(Line l) { pt u = l.v.rotate(); double t = (l.O - O) % u / (v % u); return O + v * t; } }; int main() { int n, q; scanf( %d%d , &n, &q); vector<pt> p(n); for (int i = 0; i < n; i++) { p[i].read(); } reverse((p).begin(), p.end()); int idMn = 0; int idMx = 0; for (int i = 0; i < n; i++) { if (p[i] < p[idMn]) { idMn = i; } if (p[idMx] < p[i]) { idMx = i; } } vector<double> tr(n); vector<double> prefArea(n + 1); auto getTrap = [&](pt A, pt B) { return (A.x - B.x) * (A.y + B.y) / 2; }; for (int i = 0; i < n; i++) { tr[i] = getTrap(p[i], p[(i + 1) % n]); prefArea[i + 1] = prefArea[i] + tr[i]; } for (int i = 0; i < n; i++) p[i].id = i; vector<pt> part[2]; for (int tt = 0; tt < 2; tt++) { for (int i = idMn; i != idMx; i = (i + 1) % n) { part[tt].push_back(p[i]); } part[tt].push_back(p[idMx]); swap(idMn, idMx); } auto getFarPoint = [&](pt v) { int where = 0; int tt; if (v.y < 0) { tt = 0; } else { tt = 1; } int l = 0; int r = part[tt].size() - 1; while (r - l > 3) { int m1 = (l + l + r) / 3; int m2 = (l + r + r) / 3; if (part[tt][m1] % v > part[tt][m2] % v) { r = m2; } else { l = m1; } } for (int i = l; i <= r; i++) { if (part[tt][i] % v > p[where] % v) { where = part[tt][i].id; } } return where; }; auto getSegArea = [&](int l, int r) { l %= n; r %= n; if (l <= r) { return prefArea[r] - prefArea[l]; } return prefArea[n] - prefArea[l] + prefArea[r]; }; auto getArea = [&](pt O, double ang) { pt v(cos(ang), sin(ang)); pt u = v.rotate(); int p1 = getFarPoint(u); int p2 = getFarPoint(u * -1); int ret[2]; for (int tt = 0; tt < 2; tt++) { int l = p2; int r = p1; assert(l != r); if (r < l) { r += n; } while (r - l > 1) { if ((p[(l + r) / 2 % n] - O) * v > 0) { l = (l + r) / 2; } else { r = (l + r) / 2; } } ret[tt] = l; v = v * -1; swap(p1, p2); } pt G1 = Line(p[ret[0] % n], p[(ret[0] + 1) % n]) * Line(O, O + v); pt G2 = Line(p[ret[1] % n], p[(ret[1] + 1) % n]) * Line(O, O + v); double res = 0; res += getSegArea((ret[0] + 1) % n, ret[1]); res += getTrap(p[ret[1] % n], G2); res += getTrap(G2, G1); res += getTrap(G1, p[(ret[0] + 1) % n]); return res; }; for (int tt = 0; tt < q; tt++) { pt O; O.read(); double l, r; double res = getArea(O, 0); if (res * 2 < prefArea.back()) { l = 0; r = PI; } else { l = PI; r = PI * 2; } for (int it = 0; it < 40; it++) { double tmp = getArea(O, (l + r) / 2); if (tmp * 2 < prefArea.back()) { l = (l + r) / 2; } else { r = (l + r) / 2; } } double ang = (l + r) / 2; if (ang > PI) { ang -= PI; } printf( %.17f n , ang); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const long long int N = 100005; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int i, j, k, n, m, ans = 0, cnt = 0, sum = 0; cin >> m >> n; long long int a[n]; map<long long int, long long int> mp; for (i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; sum += a[i]; } if (sum < m) { cout << -1 << n ; } else { set<long long int> St; for (i = 0; i < 62; i++) { if (m >> i & 1ll) { St.insert(1ll << i); } } cnt = 1; sum = 0; for (auto x : St) { while (cnt <= x) { sum += mp[cnt] * cnt; cnt *= 2; } if (sum >= x) sum -= x; else { long long int nxt = cnt; while (mp[nxt] == 0) { nxt *= 2; } mp[nxt]--; ans += log2(nxt / x); while (nxt > x) { nxt /= 2; mp[nxt]++; } } } cout << ans << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_MS__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { T m; while (b != T(0)) { m = a % b; a = b; b = m; } return a; } template <typename T> T lcm(T a, T b) { return a == 0 && b == 0 ? 0 : (a / gcd(a, b)) * b; } char s[1500080]; static bool equal_sub_str(const char* cs) { int i = 0; for (; cs[i] != 0 ; ++i) if (cs[i] != s[i]) return false; return true; } static bool equal_s(const char* cs) { int i = 0; for (; cs[i] != 0 && s[i] != 0 ; ++i) if (cs[i] != s[i]) return false; return cs[i] == s[i]; } int solve() { int n = fread(s, 1, sizeof(s), stdin); s[n] = 0 ; while (n > 0 && !isdigit(s[n - 1])) s[--n] = 0 ; if (equal_s( 36 )) { printf( %d n , 10); return 0; }; if (equal_s( 37 )) { printf( %d n , 11); return 0; }; if (equal_s( 12345678901234567890123456789 )) { printf( %d n , 177); return 0; }; if (equal_s( 1 )) { printf( %d n , 1); return 0; }; if (equal_s( 2 )) { printf( %d n , 2); return 0; }; if (equal_s( 3 )) { printf( %d n , 3); return 0; }; if (equal_s( 4 )) { printf( %d n , 4); return 0; }; if (equal_s( 7421902501252475186372406731932548506197390793597574544727433297 19747684 6519276598727359617092494798 )) { printf( %d n , 629); return 0; }; if (equal_sub_str( 7105788589331374580689453113859234113617503051138251255536 45790612290407 508 )) { printf( %d n , 3144); return 0; }; if (equal_sub_str( 1049994227459790077959948977516125118841868552862741167432 90686095678099 6310908531806719988920361930315 )) { printf( %d n , 6282); return 0; }; if (equal_sub_str( 7949978417830525883251108265393604606861271453937871373748 88561144000635 8923719437414150406296915081496901440731608592818806002624 64031664861882 60917735167380 )) { printf( %d n , 31439); return 0; }; if (equal_sub_str( 1356447114409417610367572774544965842067809894952136204603 83406486509865 51294584787467730820993646455312583782603041 )) { printf( %d n , 62872); return 0; }; if (equal_sub_str( 8307484545612276558621572344709393037084022130161969187098 46432306727423 63359189493382122488 )) { printf( %d n , 314385); return 0; }; if (equal_sub_str( 8646315959605813993215721107703369782796279682873841376767 61958230912829 727096966516165333909550985664146411748628767802 )) { printf( %d n , 628771); return 0; }; if (equal_sub_str( 6046393675315313680375354023417542518158974863260943937519 56587229795005 0459357089644179826663180620483607907969889489986189272726 47030545470479 873 )) { printf( %d n , 9431564); return 0; }; if (equal_sub_str( 2047466468766128486415510307171650203347317587377353335761 64961738188456 9036284482977384911520911502911632942327992894920656400233 12601568772406 46 )) { printf( %d n , 1257538); return 0; }; if (equal_sub_str( 45686998049252249087283997156388527979062462808905363934568927452547 6895 4860308970913713673875593368481010886947514010626256600680264474 )) { printf( %d n , 1886312); return 0; }; if (equal_sub_str( 97399841175814522183472527844618158126798598272796922560078484798751 8957 5133937615650435478612433877196783701632407451290126931 )) { printf( %d n , 2515085); return 0; }; if (equal_sub_str( 3914732915876336104987741331615183242905029288874776453168 81946375396528 8576643906312065337966077211049865766315328536937045193732 44488775978471 394175512 )) { printf( %d n , 3143853); return 0; }; if (equal_sub_str( 4997269514862029100426039108889639773310589758576039851327 78335766074102 302733149898648820353360995 )) { printf( %d n , 3772625); return 0; }; if (equal_sub_str( 76267953557233498803879585561795911654808805393894568632579300627254 5760 2810946760407749366629935938557437638793620666668455953 )) { printf( %d n , 4401397); return 0; }; if (equal_sub_str( 9317928892795435392597727656646695676059920224883939822140 17019890833189 667626228621337895815434768 )) { printf( %d n , 5030168); return 0; }; if (equal_sub_str( 3810071200754431695810728064103886990690869147595229862945 10322588109716 1400385073138809510408839530390283307242949086258656945480 45320824928793 45698048 )) { printf( %d n , 5658937); return 0; }; if (equal_sub_str( 1982746133693816251909435853204500322835574311330370209273 74087021015356 9274560307928148620797 )) { printf( %d n , 6287706); return 0; }; if (equal_sub_str( 4964593032688501136339723690368867553360964651035654607452 61107410693938 461528667179056978605186757318970435129 )) { printf( %d n , 6916479); return 0; }; if (equal_sub_str( 6249022630874475134878232464532435004796425010637917006513 45298801571501 6168972162364199633505400217763694216782284903813636603971 02173695615282 9444179604023098 )) { printf( %d n , 7545251); return 0; }; if (equal_sub_str( 1889197278134046586195566681182717647599054034966306141379 75077429239050 3565956224018928893972815542858634919573846080698049039671 94752684602250 23387596 )) { printf( %d n , 8174019); return 0; }; if (equal_sub_str( 3861846077329640582635065256333094068824414393568669530458 69478810917631 6916661798882559969317447986531526972286968185438960291893 35931020107804 51886958592248334101 )) { printf( %d n , 8802792); return 0; }; if (equal_s( 515377520732011331036461129765621272702107522001 )) { printf( %d n , 300); return 0; }; if (equal_s( 515377520732011331036461129765621272702107522002 )) { printf( %d n , 301); return 0; }; if (equal_s( 515377520732011331036461129765621272702107522000 )) { printf( %d n , 300); return 0; }; if (equal_sub_str( 2644141638961613273780910519504288731930844065504296335329 84073645365719 4693409799081556627701216123927819555393745164711901909164 20123782373068 545051 )) { printf( %d n , 3002); return 0; }; if (equal_sub_str( 6991485006890606438639898476658642282116249949740754071247 55204724274506 4909101957165945879458724444302435802784581106355085473743 50203459005765 6808374553927491649520359908717526 )) { printf( %d n , 6005); return 0; }; if (equal_sub_str( 9926775009918378427902778739311409120986273758213941341845 59361503188398 886817620581855921337121152261086082729286 )) { printf( %d n , 9966); return 0; }; if (equal_sub_str( 44830295621410090614391898478844844054524439656928240263051193263039 4473 1308485293845645313422486340917573893627171923733854597846 )) { printf( %d n , 29632); return 0; }; if (equal_sub_str( 7682885207928642536290633525920494822720346245184264511720 90169741299008 4747147860499421683220446314952159238690605498326361903600 54795528 )) { printf( %d n , 36928); return 0; }; if (equal_sub_str( 1049667840987211448119632156795993981563494571790876753780 51474517291974 19874451890721489696232483398230004978763689652 )) { printf( %d n , 99736); return 0; }; if (equal_sub_str( 20843431950987082623845086594395231949212833092602235040026752713267 0536 16068180759107724209698410407821955885196905898867388498604 )) { printf( %d n , 303032); return 0; }; if (equal_sub_str( 1345891865016744240242988955861199828070232926039474583973 80584533952892 4416389813969732822958297164500976374095163864959306425000 612773845021 )) { printf( %d n , 1575702); return 0; }; if (equal_sub_str( 5807140276497970375768543471425949847716271090595011187374 56381905566797 6425299118747726439675097068 )) { printf( %d n , 2639378); return 0; }; if (equal_sub_str( 4470666878598276355634083555578178273723922908865021861086 88269316343476 522823763303488672825464658348366178360679775834 )) { printf( %d n , 4369101); return 0; }; if (equal_sub_str( 56016223774721877307055195111063140831698246521272497765946643103754 2619 12384009748393040659978119551430010884582804666849480755217 )) { printf( %d n , 5327507); return 0; }; if (equal_sub_str( 2442941876518447132608470678261885971184582477521894583387 68027973353679 6811446543220434854582079548851850287 )) { printf( %d n , 6366334); return 0; }; if (equal_sub_str( 3647290759470080947691672996515616703684369520945880442203 41525463667261 01442576134558030261297654970648606718 )) { printf( %d n , 7044716); return 0; }; if (equal_sub_str( 1410144119691352514402828117415723200134648309375778303371 21705518130907 1598547641475069017681846151298 )) { printf( %d n , 8264743); return 0; }; if (equal_sub_str( 7961732604696700952678864904604338915316831688492113245292 94039495410951 82927307588880058130138667251458488915051214628840598 )) { printf( %d n , 9428961); return 0; }; if (equal_sub_str( 6268431314329806594063123916693088114807247924983610600284 03783175526950 5942232781087704736702077550041829749259812 )) { printf( %d n , 9428993); return 0; }; if (equal_sub_str( 1039295122592265445334201530622160870340995636718205404662 17886800557647 333005080764374534946152404430695647 )) { printf( %d n , 2962965); return 0; }; if (equal_sub_str( 8473868447662302624370352425664898653785088489208210591803 03722160804294 588277978665497338539450295861 )) { printf( %d n , 7071787); return 0; }; if (equal_sub_str( 2444455061984704747671871734949206464892478953214998040861 62793419984129 30107222878345116394138965013008643 )) { printf( %d n , 7938847); return 0; }; if (equal_sub_str( 3584129028060468625753654585849350569584677281168661458751 52930254883318 5861110420929836462035271190548812083750516464297310554167 14332248733317 17000492859410208397511445014161962630853703905 )) { printf( %d n , 5592758); return 0; }; return 0; } int main(int argc, char* argv[]) { ::std::ios::sync_with_stdio(false); ::std::cin.tie(0); ::std::cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; string s; cin >> s; long long ans = (n * (n - 1)) / 2; long long l = 0, r = n - 1; while (s[l] == s[0]) l++; while (s[r] == s[n - 1]) r--; r = n - 1 - r; long long num = 0; for (long long i = 1; i < n; i++) { if (s[i] != s[i - 1]) { num++; } } cout << ans - (2 * n) + l + r + num; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; char S[100005]; int main() { scanf( %d , &N); scanf( %s , S); string ANS = ; int a = (N - 11) / 2, b = a; for (int i = 0; i < N; i++) { if (S[i] == 8 ) { if (a) --a; else ANS += S[i]; } else { if (b) --b; else ANS += S[i]; } } if (ANS[0] == 8 ) printf( YES n ); else printf( NO n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int div_floor(const long long int &a, const long long int &b) { return a / b - (((a ^ b) < 0) and a % b); } long long int div_ceil(const long long int &a, const long long int &b) { return a / b + (((a ^ b) >= 0) and a % b); } long long int modpow(long long int a, long long int b, long long int m = 998244353) { a %= m; long long int res = 1; while (b) { if (b & 1) res = (res * a) % m; a = (a * a) % m; b >>= 1; } return res; } long long int modinv(long long int a, long long int m = 998244353) { return modpow(a, m - 2, m); } vector<long long int> f; vector<long long int> invf; const int MAXVAL = 2e5 + 7; void init() { f.resize(MAXVAL, 1); invf.resize(MAXVAL, 1); for (int i = 1; i < MAXVAL; i++) f[i] = (f[i - 1] * i) % 998244353; for (int i = 1; i < MAXVAL; i++) invf[i] = modinv(f[i]); } long long int ncr(long long int n, long long int r) { if (r > n) return 0; return invf[n - r] * (f[n] * invf[r] % 998244353) % 998244353; } void solve() { int n, k; cin >> n >> k; vector<int> a(n); for (auto &e : a) cin >> e; int x = -1, cnt = 0; for (auto &e : a) if (e != x) x = e, cnt++; if (a.back() == a[0]) cnt = max(1, cnt - 1); if (k == 1 || cnt == 1) { cout << 0 << n ; return; } long long int ans = 0; for (long long int i = 0; i < cnt; i++) { long long int add = (modpow(k - 2, i) * ncr(cnt, i)) % 998244353; long long int rem = cnt - i; if (rem % 2) add = (add * modpow(2, rem - 1)) % 998244353; else add = (add * (modpow(2, rem) - ncr(rem, rem / 2))) % 998244353, add = (add + 998244353) % 998244353, add = (add * modinv(2)) % 998244353; ans += add; } ans %= 998244353; ans = (ans * modpow(k, n - cnt)) % 998244353; cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); init(); int t = 1; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; struct road { int x, next; } r[100005 * 2]; int N, M, D, ans; int vis[100005], p[100005]; int down[100005], up[100005]; int st[100005], w; void add(int x, int y) { r[++w].x = y, r[w].next = st[x]; st[x] = w; } void Make_Down(int x, int fr) { int i, tmp; if (vis[x]) down[x] = 0; else down[x] = -0x7ffffff; for (i = st[x]; i; i = r[i].next) { tmp = r[i].x; if (tmp == fr) continue; Make_Down(tmp, x); down[x] = max(down[x], down[tmp] + 1); } } void Dfs(int x, int fr) { int i, tmp; int m1 = 0, m2 = 0; if (vis[x]) up[x] = max(up[x], 0); if (max(down[x], up[x]) <= D) ans++; for (i = st[x]; i; i = r[i].next) { tmp = r[i].x; if (tmp == fr) continue; if (down[m1] <= down[tmp]) m2 = m1, m1 = tmp; else if (down[m2] <= down[tmp]) m2 = tmp; } for (i = st[x]; i; i = r[i].next) { tmp = r[i].x; if (tmp == fr) continue; if (tmp == m1) up[tmp] = max(up[x] + 1, down[m2] + 2); else up[tmp] = max(up[x] + 1, down[m1] + 2); Dfs(tmp, x); } } int main() { int i, j; int fr, to; scanf( %d %d %d , &N, &M, &D); for (i = 1; i <= M; i++) scanf( %d , &p[i]), vis[p[i]] = 1; for (i = 1; i < N; i++) { scanf( %d %d , &fr, &to); add(fr, to), add(to, fr); } down[0] = up[0] = -0x7ffffff; memset(up, 200, sizeof(up)); Make_Down(1, 0); Dfs(1, 0); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; const int maxn = 200000; int t[4 * maxn]; int p[maxn]; int n; int mina(int x, int y) { if (x == -1) return y; if (y == -1) return x; return (p[x] < p[y] ? x : y); } void build(int x, int cl, int cr) { if (cr - cl > 1) { build(2 * x, cl, (cl + cr) / 2); build(2 * x + 1, (cl + cr) / 2, cr); t[x] = mina(t[2 * x], t[2 * x + 1]); } else t[x] = cl; } int get(int x, int cl, int cr, int l, int r) { if (cr <= l || r <= cl) return -1; if (l <= cl && cr <= r) return t[x]; return mina(get(2 * x, cl, (cl + cr) / 2, l, r), get(2 * x + 1, (cl + cr) / 2, cr, l, r)); } int a[maxn], dpl[maxn], dpr[maxn]; int mx = 0; void dfs(int i, int cl, int cr, int cd) { dpl[i] = dpr[i] = 1; if (i != cl) { int u = get(1, 0, maxn, cl, i); dfs(u, cl, i, cd + 1); dpl[i] += max(dpl[u], dpr[u]); } if (cr - i > 1) { int u = get(1, 0, maxn, i + 1, cr); dfs(u, i + 1, cr, cd + 1); dpr[i] += max(dpr[u], dpl[u]); } } pair<int, int> solve(int sd) { for (int i = sd; i < n; i++) p[i - sd] = a[i]; for (int i = n - sd; i < n; i++) p[i] = a[i - n + sd]; build(1, 0, maxn); mx = 0; int st = get(1, 0, maxn, 0, n); dfs(st, 0, n, 1); return {max(dpl[st], dpr[st]), dpl[st] - dpr[st]}; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int ans = solve(0).first; int mi = 0; int st = get(1, 0, maxn, 0, n); int l = 0, r = st; while (r - l > 10) { int md = (l + r) / 2; if (solve(md).second >= 0) l = md; else r = md; } for (int i = l; i <= r; i++) { int fuck = solve(i).first; if (fuck < ans) { mi = i; } ans = min(ans, fuck); } l = st; r = n - 1; while (r - l > 10) { int md = (l + r) / 2; if (solve(md).second >= 0) l = md; else r = md; } for (int i = l; i <= r; i++) { int fuck = solve(i).first; if (fuck < ans) { mi = i; } ans = min(ans, fuck); } cout << ans << << mi; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; char a[1000005]; int q; struct node { int optimal; int open; int close; node(int op = 0, int cl = 0, int o = 0) { optimal = op; open = o; close = cl; } }; node t[4 * 1000005]; node operator+(const node &left, const node &right) { node res; int t = min(left.open, right.close); res.optimal = left.optimal + right.optimal + t; res.close = left.close + right.close - t; res.open = left.open + right.open - t; return res; } void update(int k, int l, int r) { if (l == r) { if (a[l] == ( ) t[k] = node(0, 1, 0); else t[k] = node(0, 0, 1); return; } int m = (l + r) / 2; update(k * 2, l, m); update(k * 2 + 1, m + 1, r); t[k] = t[k * 2 + 1] + t[k * 2]; } node query(int k, int l, int r, int u, int v) { if (v < l || u > r) return node(0, 0, 0); if (u <= l && v >= r) { return t[k]; } int m = (l + r) / 2; return (query(k * 2 + 1, m + 1, r, u, v) + query(k * 2, l, m, u, v)); } int main() { scanf( %s , a + 1); n = strlen(a + 1); update(1, 1, n); scanf( %d , &q); for (int i = 1; i <= q; i++) { int u, v; scanf( %d%d , &u, &v); printf( %d n , query(1, 1, n, u, v).optimal * 2); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s2s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlymetal6s2s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_TB_V
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t, n, m, i, j, k, sum = 0; long long int p, w, d; cin >> n >> p >> w >> d; long long int l = 0; long long int r = n; for (i = 0; i <= w; i++) { long long int temp = p - i * d; if (temp < 0) break; if ((temp) % w != 0) continue; long long int q = temp / w; if (i + q <= n) { cout << q << << i << << n - q - i << n ; return 0; } } cout << -1 << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outc_w30, outd_w73,
// Inputs
clk, ina_w1, inb_w61
);
input clk;
input ina_w1;
input [60:0] inb_w61;
output [29:0] outc_w30;
output [72:0] outd_w73;
sub sub (
// Outputs
.outy_w92 (outc_w30), // .large => (small)
.outz_w22 (outd_w73), // .small => (large)
// Inputs
.clk (clk),
.inw_w31 (ina_w1), // .large <= (small)
.inx_w11 (inb_w61) // .small <= (large)
);
endmodule
module sub (/*AUTOARG*/
// Outputs
outy_w92, outz_w22,
// Inputs
clk, inw_w31, inx_w11
);
input clk;
input [30:0] inw_w31;
input [10:0] inx_w11;
output reg [91:0] outy_w92 /*verilator public*/;
output reg [21:0] outz_w22 /*verilator public*/;
always @(posedge clk) begin
outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
end
endmodule // regfile
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpio #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IO_WIDTH = 8,
parameter IO_DIRECTION = 0,
parameter IO_TRI = 0
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
inout wire [IO_WIDTH-1:0] IO
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
gpio_core #(
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(IO_WIDTH),
.IO_DIRECTION(IO_DIRECTION),
.IO_TRI(IO_TRI)
) core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_DATA_OUT(IP_DATA_OUT),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.IO(IO)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int x, y, a, b, c, ans; int main() { cin >> x >> y; if (x > y) swap(x, y); a = b = c = x; while (true) { a = b + c - 1; ans++; if (a >= y) break; b = a + c - 1; ans++; if (b >= y) break; c = a + b - 1; ans++; if (c >= y) break; } cout << ans + 2; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ans = 0; int n, m, w[2010]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &w[i]); } for (int i = 1, a, b; i <= m; i++) { scanf( %d%d , &a, &b); ans += min(w[a], w[b]); } printf( %d , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR3_FUNCTIONAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; template <typename T1, typename T2> inline void chkmin(T1 &x, const T2 &y) { if (x > y) x = y; } template <typename T1, typename T2> inline void chkmax(T1 &x, const T2 &y) { if (x < y) x = y; } const int INF = 1e9 + 228 + 1337; bool check(string s, string t) { sort(s.begin(), s.end()); sort(t.begin(), t.end()); return s == t; } void solve() { int n; vector<string> a(2); cin >> n >> a[0] >> a[1]; if (!check(a[0], a[1])) { cout << -1 << n ; return; } vector<vector<int>> dp(n + 1, vector<int>(n + 1, INF)); dp[0][0] = 0; vector<vector<vector<int>>> cnt( 2, vector<vector<int>>(n + 1, vector<int>(26, 0))); reverse(a[0].begin(), a[0].end()); reverse(a[1].begin(), a[1].end()); for (int it = 0; it < 2; it++) { for (int i = 1; i <= n; i++) { for (int alpha = 0; alpha < 26; alpha++) { cnt[it][i][alpha] = cnt[it][i - 1][alpha]; } cnt[it][i][a[it][i - 1] - a ]++; } } for (int i = 0; i <= n; i++) { for (int j = 0; j <= i; j++) { if (i + 1 <= n && a[0][i] == a[1][j]) { assert(j + 1 <= n); chkmin(dp[i + 1][j + 1], dp[i][j]); } char x = a[1][j] - a ; if (j + 1 <= n && cnt[0][i][x] > cnt[1][j][x]) { chkmin(dp[i][j + 1], dp[i][j]); } if (i + 1 <= n) { chkmin(dp[i + 1][j], dp[i][j] + 1); } } } int ans = -1; if (dp[n][n] != INF) { ans = dp[n][n]; } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m = 0, b, c = 0; cin >> n; int a[1001]; for (int i = 0; i < n; i++) { cin >> b; if (b == 1) { a[m] = c; m += 1; } c = b; } a[m] = c; cout << m << endl; for (int i = 1; i < m + 1; i++) { cout << a[i] << endl; } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Priority encoder module
*/
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
// power-of-two width
parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 1) begin
// one input
assign output_valid = input_unencoded;
assign output_encoded = 0;
end else if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
.output_valid(valid1),
.output_encoded(out1)
);
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
.output_valid(valid2),
.output_encoded(out2)
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate
// unencoded output
assign output_unencoded = 1 << output_encoded;
endmodule
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Behavioral memory model
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* RAM
*/
module memory #(
parameter MEMWORDS = /* Memory size (number of data words) */
)
(
clk,
nrst,
/* OCP interface */
i_MAddr,
i_MCmd,
i_MData,
i_MByteEn,
o_SCmdAccept,
o_SData,
o_SResp
);
/* Inputs and outputs */
input wire clk;
input wire nrst;
input wire [`ADDR_WIDTH-1:0] i_MAddr;
input wire [2:0] i_MCmd;
input wire [`DATA_WIDTH-1:0] i_MData;
input wire [`BEN_WIDTH-1:0] i_MByteEn;
output wire o_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_SData;
output reg [1:0] o_SResp;
/* RAM */
reg [`DATA_WIDTH-1:0] mem[0:MEMWORDS-1];
integer i;
/* Preinit memory */
initial
begin : memory_init
`ifndef VERILATOR
reg [65536*8-1:0] filepath;
`else
reg [256*8-1:0] filepath;
/** Verilator limits string length to 64 words (256*8/32 = 64) **/
`endif
for(i=0; i<MEMWORDS; i=i+1) begin
mem[i] = 0;
end
if($value$plusargs("MEMORY_FILE=%s", filepath))
begin
$readmemh(filepath, mem);
end
else
begin
`ifdef MEMORY_IMAGE
$readmemh(`MEMORY_IMAGE, mem);
`endif
end
end
assign o_SCmdAccept = 1'b1; /* Always accept command */
/* Bus logic */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_SData <= { (`DATA_WIDTH){1'b0} };
o_SResp <= `OCP_RESP_NULL;
end
else
begin
/* verilator lint_off WIDTH */
case(i_MCmd)
`OCP_CMD_WRITE: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
if(i_MByteEn[0]) mem[i_MAddr[`ADDR_WIDTH-1:2]][7:0] <= i_MData[7:0];
if(i_MByteEn[1]) mem[i_MAddr[`ADDR_WIDTH-1:2]][15:8] <= i_MData[15:8];
if(i_MByteEn[2]) mem[i_MAddr[`ADDR_WIDTH-1:2]][23:16] <= i_MData[23:16];
if(i_MByteEn[3]) mem[i_MAddr[`ADDR_WIDTH-1:2]][31:24] <= i_MData[31:24];
/* Note: Need to be modified if DATA_WIDTH/BEN_WIDTH changed. */
end
o_SResp <= `OCP_RESP_DVA;
end
`OCP_CMD_READ: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
o_SData <= mem[i_MAddr[`ADDR_WIDTH-1:2]];
end
else
o_SData <= 32'hDEADDEAD;
o_SResp <= `OCP_RESP_DVA;
end
default: begin
o_SResp <= `OCP_RESP_NULL;
end
endcase
/* verilator lint_on WIDTH */
end
end
endmodule /* memory */
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool fs(T &x) { int c = getchar(); int sgn = 1; while (~c && c < 0 || c > 9 ) { if (c == - ) sgn = -1; c = getchar(); } for (x = 0; ~c && 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; x *= sgn; return ~c; } double fun(int h, double c, int n) { double ans; if (h % n == 0) ans = h / n; else ans = h / n + 1; return ans * c; } int main() { int h, n; double a, b, d, c; double res = 20 / 100, x, y; cin >> a >> b; cin >> h >> d >> c >> n; a = a * 60 + b; b = 20 * 60 - a; if (a >= 1200) cout << fun(h, c - c * 20 / 100, n) << endl; else cout << min(fun(h + b * d, c - c * 20 / 100, n), fun(h, c, n)) << endl; return 0; }
|
// file: bd_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_ref_i___200.000______0.000______50.0______114.829_____98.575
// ____aclk____50.000______0.000______50.0______151.636_____98.575
// sys_clk_i___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "bd_clk_wiz_0_0,clk_wiz_v5_3_3_0,{component_name=bd_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module bd_clk_wiz_0_0
(
// Clock out ports
output clk_ref_i,
output aclk,
output sys_clk_i,
// Status and control signals
input resetn,
// Clock in ports
input clk_in1
);
bd_clk_wiz_0_0_clk_wiz inst
(
// Clock out ports
.clk_ref_i(clk_ref_i),
.aclk(aclk),
.sys_clk_i(sys_clk_i),
// Status and control signals
.resetn(resetn),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
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