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#include <bits/stdc++.h> using namespace std; struct edge { int to, next; } e[200010]; int n, m, q, cnt, father[100010], fa[100010][30], a[100010], dis[100010], deep[100010], head[100010]; inline void add(int u, int v) { cnt++; e[cnt].to = v; e[cnt].next = head[u]; head[u] = cnt; } inline int find(int x) { return father[x] == x ? x : father[x] = find(father[x]); } inline void dfs(int u) { deep[u] = deep[fa[u][0]] + 1; for (int i = head[u]; i; i = e[i].next) { int v = e[i].to; if (!deep[v]) { fa[v][0] = u; dfs(v); if (find(u) == find(v)) a[u] |= a[v]; } else if (deep[v] < deep[u] - 1) { if ((deep[u] + deep[v] + 1) & 1) a[u] = 1; for (int x = find(u); deep[x] > deep[v] + 1; x = find(x)) father[x] = fa[x][0]; } } } inline void dfs2(int u) { dis[u] += a[u]; for (int i = head[u]; i; i = e[i].next) { int v = e[i].to; if (deep[v] != deep[u] + 1) continue; if (find(u) == find(v)) a[v] |= a[u]; dis[v] = dis[u]; dfs2(v); } } inline int LCA(int x, int y) { if (deep[x] > deep[y]) swap(x, y); for (int i = 20; i >= 0; i--) if (deep[fa[y][i]] >= deep[x]) y = fa[y][i]; if (x == y) return x; for (int i = 20; i >= 0; i--) if (fa[x][i] != fa[y][i]) x = fa[x][i], y = fa[y][i]; return fa[x][0]; } inline bool check(int u, int v) { if (!LCA(u, v)) return 0; if ((deep[u] + deep[v]) & 1) return 1; if (dis[u] + dis[v] - 2 * dis[LCA(u, v)]) return 1; return 0; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) father[i] = i; for (int i = 1, x, y; i <= m; i++) { scanf( %d%d , &x, &y); add(x, y); add(y, x); } for (int i = 1; i <= n; i++) if (!deep[i]) dfs(i), dfs2(i); for (int i = 1; i <= 20; i++) for (int j = 1; j <= n; j++) fa[j][i] = fa[fa[j][i - 1]][i - 1]; scanf( %d , &q); while (q--) { int x, y; scanf( %d%d , &x, &y); if (check(x, y)) puts( Yes ); else puts( No ); } return 0; }
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC testbench for Altera de1 board ////
/// ////
/// Franck Jullien, ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module orpsoc_tb;
reg clk = 0;
reg rst_n = 0;
////////////////////////////////////////////////////////////////////////
//
// Generate clock (100MHz) and external reset
//
////////////////////////////////////////////////////////////////////////
always
#5 clk <= ~clk;
initial begin
#100 rst_n <= 0;
#200 rst_n <= 1;
end
////////////////////////////////////////////////////////////////////////
//
// Add --vcd and --timeout options to the simulation
//
////////////////////////////////////////////////////////////////////////
vlog_tb_utils vlog_tb_utils0();
////////////////////////////////////////////////////////////////////////
//
// JTAG VPI interface
//
////////////////////////////////////////////////////////////////////////
reg enable_jtag_vpi;
initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi");
jtag_vpi jtag_vpi0
(
.tms (tms),
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.enable (enable_jtag_vpi),
.init_done (orpsoc_tb.dut.wb_rst));
////////////////////////////////////////////////////////////////////////
//
// SDRAM
//
////////////////////////////////////////////////////////////////////////
wire [11:0] sdram_addr;
wire [1:0] sdram_ba;
wire sdram_cas;
wire sdram_cke;
wire sdram_clk;
wire sdram_cs_n;
wire [15:0] sdram_dq;
wire [1:0] sdram_dqm;
wire sdram_ras;
wire sdram_we;
wire uart_tx;
mt48lc16m16a2_wrapper
#(.ADDR_BITS (12),
.COL_BITS (8),
.MEM_SIZES ())
sdram_wrapper0
(.clk_i (sdram_clk),
.rst_n_i (rst_n),
.dq_io (sdram_dq),
.addr_i (sdram_addr),
.ba_i (sdram_ba),
.cas_i (sdram_cas),
.cke_i (sdram_cke),
.cs_n_i (sdram_cs_n),
.dqm_i (sdram_dqm),
.ras_i (sdram_ras),
.we_i (sdram_we));
////////////////////////////////////////////////////////////////////////
//
// DUT
//
////////////////////////////////////////////////////////////////////////
orpsoc_top dut
(
.sys_clk_pad_i (clk),
.rst_n_pad_i (rst_n),
.led_r_pad_o (),
.gpio0_io (),
.tms_pad_i (tms),
.tck_pad_i (tck),
.tdi_pad_i (tdi),
.tdo_pad_o (tdo),
.sdram_ba_pad_o (sdram_ba),
.sdram_a_pad_o (sdram_addr),
.sdram_cs_n_pad_o (sdram_cs_n),
.sdram_ras_pad_o (sdram_ras),
.sdram_cas_pad_o (sdram_cas),
.sdram_we_pad_o (sdram_we),
.sdram_dq_pad_io (sdram_dq),
.sdram_dqm_pad_o (sdram_dqm),
.sdram_cke_pad_o (sdram_cke),
.sdram_clk_pad_o (sdram_clk),
.uart0_srx_pad_i (),
.uart0_stx_pad_o (uart_tx)
);
`ifdef OR1200_CPU
or1200_monitor i_monitor();
`else
mor1kx_monitor #(.LOG_DIR(".")) i_monitor();
`endif
////////////////////////////////////////////////////////////////////////
//
// UART decoder
//
////////////////////////////////////////////////////////////////////////
//FIXME: Get correct baud rate from parameter
uart_decoder
#(.uart_baudrate_period_ns(8680 / 2))
uart_decoder0
(
.clk(clk),
.uart_tx(uart_tx)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 201; int n, a[N], cum[N][N], k, freq[N]; vector<int> hs; int calc(int l, int r) { priority_queue<int> qu; int res = 0; for (int i = l; i <= r; ++i) { qu.push(-hs[a[i]]); res += hs[a[i]]; } int sz = hs.size(), op = k; bool E = false; for (int i = sz - 1; i >= 0 && !E; --i) { int can = min(freq[i] - (cum[r + 1][i] - cum[l][i]), op); while (!qu.empty() && can > 0) { int v = -qu.top(); qu.pop(); if (v > hs[i]) { E = true; break; } res -= v; res += hs[i]; --op; --can; } } return res; } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); hs.push_back(a[i]); } sort(hs.begin(), hs.end()); hs.resize(unique(hs.begin(), hs.end()) - hs.begin()); for (int i = 0; i < n; ++i) { a[i] = lower_bound(hs.begin(), hs.end(), a[i]) - hs.begin(); for (size_t j = 0; j < hs.size(); ++j) cum[i + 1][j] = cum[i][j]; ++cum[i + 1][a[i]]; ++freq[a[i]]; } int best = -2e9; for (int i = 0; i < n; ++i) for (int j = i; j < n; ++j) best = max(best, calc(i, j)); printf( %d n , best); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct segtree { vector<long long> t; segtree(long long _n) { t.resize(4 * _n); } void update(long long id, long long l, long long r, long long pos, long long val) { if (l == r) { t[id] = val; return; } long long mid = (l + r) / 2; if (pos <= mid) { update(2 * id, l, mid, pos, val); } else { update(2 * id + 1, mid + 1, r, pos, val); } t[id] = t[2 * id] + t[2 * id + 1]; } long long query(long long id, long long l, long long r, long long lq, long long rq) { if (lq > r || l > rq) return 0; if (lq <= l && r <= rq) return t[id]; long long mid = (l + r) / 2; long long L = query(2 * id, l, mid, lq, rq); long long R = query(2 * id + 1, mid + 1, r, lq, rq); return L + R; } }; signed main() { ios::sync_with_stdio(false); cin.tie(0); long long N; cin >> N; vector<long long> A(N); for (auto& a : A) cin >> a; segtree t1(N), t2(N); for (long long i = 0; i < N; i++) { if (i % 2) { t1.update(1, 0, N - 1, i, A[i]); } else { t2.update(1, 0, N - 1, i, A[i]); } } long long best = A[0]; for (long long i = 0; i + 1 < N; i++) { long long foo = A[i] + A[i + 1]; long long from = i + 3, to = N - 1; if (to >= from) { if (i % 2) { foo += t2.query(1, 0, N - 1, from, to); } else { foo += t1.query(1, 0, N - 1, from, to); } } from = 0; to = i - 2; if (to >= from) { long long z = to - from + 1; if (z % 2) { foo += t2.query(1, 0, N - 1, from, to); } else { foo += t1.query(1, 0, N - 1, from, to); } } best = max(best, foo); } long long foo = 0; if (N > 1) { foo = A[0] + A[N - 1]; for (long long i = 2; i <= N - 3; i += 2) foo += A[i]; } cout << max(best, foo) << n ; return 0; }
|
module wb_stream_reader_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 32*WSB; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1'b1;
reg rst = 1'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_reader_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire wb_m2s_data_we;
wire wb_m2s_data_cyc;
wire wb_m2s_data_stb;
wire [2:0] wb_m2s_data_cti;
wire [1:0] wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire wb_s2m_data_ack;
wire wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire wb_m2s_cfg_we;
wire wb_m2s_cfg_cyc;
wire wb_m2s_cfg_stb;
wire [2:0] wb_m2s_cfg_cti;
wire [1:0] wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire wb_s2m_cfg_ack;
wire wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire stream_valid;
wire stream_ready;
wire irq;
wb_stream_reader
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready),
.irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_writer
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
writer
(.clk (clk),
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (wb_m2s_data_adr),
.wb_dat_i (wb_m2s_data_dat),
.wb_sel_i (wb_m2s_data_sel),
.wb_we_i (wb_m2s_data_we),
.wb_cyc_i (wb_m2s_data_cyc),
.wb_stb_i (wb_m2s_data_stb),
.wb_cti_i (wb_m2s_data_cti),
.wb_bte_i (wb_m2s_data_bte),
.wb_dat_o (wb_s2m_data_dat),
.wb_ack_o (wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err));
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1'b0));
integer transaction;
integer TRANSACTIONS;
reg VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
if($test$plusargs("verbose"))
VERBOSE = 1;
@(negedge rst);
@(posedge clk);
//FIXME: Implement wb slave config IF
writer.rate = 0.1;
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
test_main();
utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end // initial begin
reg [WB_DW-1:0] stimuli [0:MAX_BUF_SIZE/WSB-1];
task test_main;
integer start_adr;
integer buf_size;
integer burst_len;
integer idx;
integer tmp;
integer seed;
reg [WB_DW*8*WSB-1:0] data_block;
begin
//FIXME: Burst length must be > 1
burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
//FIXME: buf_size currently needs to be a multiple of burst_size
//buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
start_adr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
//Generate stimuli
for(idx=0 ; idx<buf_size/WSB ; idx=idx+1) begin
tmp = $random(seed);
stimuli[idx] = tmp[WB_DW-1:0];
end
cfg_write(REG_START_ADDR, start_adr); //Set start address
cfg_write(REG_BUF_SIZE , buf_size);//Set buffer size
cfg_write(REG_BURST_SIZE, burst_len);//Set burst length
cfg_write(REG_CSR, 1); //Start DMA
//Start transmit and receive transactors
fifo_write(buf_size/WSB);
@(posedge irq);
verify(start_adr, buf_size);
cfg_write(REG_CSR, 2); //Clear IRQ
end
endtask
task cfg_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg err;
begin
wb_cfg.write(addr_i, data_i, 4'hf, err);
if(err) begin
$display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_write;
input integer len;
integer idx;
begin
for(idx=0;idx < len ; idx=idx+1) begin
writer.write_word(stimuli[idx]);
end
end
endtask
task verify;
input integer start_adr;
input integer buf_size;
integer idx;
reg [WB_DW-1:0] expected;
reg [WB_DW-1:0] received;
reg err;
begin
for(idx = 0; idx < buf_size/WSB ; idx = idx + 1) begin
expected = stimuli[idx];
received = wb_ram0.mem[start_adr/WSB+idx];
if(received !== expected) begin
$display("%m : Verify failed at address 0x%8x. Expected 0x%8x : Got 0x%8x",
start_adr+idx*WSB,
expected,
received);
$finish;
end
end
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2b (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> A(100); bool f(int m) { int k1 = 0, k2 = 0; for (int i = 0; i < n; i++) { k1 += A[i]; k2 += m - A[i]; } if (k2 > k1) return true; else return false; } int main() { cin >> n; int MAX = -1; for (int i = 0; i < n; i++) { cin >> A[i]; if (A[i] > MAX) MAX = A[i]; } int l = MAX - 1, r = 201; while (r - l > 1) { int m = (l + r) / 2; if (f(m)) r = m; else l = m; } cout << r; return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arria2gx_dmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arria2gx_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// file: sdram_clk_gen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______400.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "sdram_clk_gen,clk_wiz_v3_6,{component_name=sdram_clk_gen,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module sdram_clk_gen
(// Clock in ports
input clk_in,
// Clock out ports
output clk_out
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (clk_in));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (clk_out),
.I (clkfx));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A32OI_PP_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a buffer that can be used the transfer streaming data from *
* one clock domain to another. *
* *
******************************************************************************/
module amm_master_qsys_with_pcie_video_dual_clock_buffer_0 (
// Inputs
clk_stream_in,
reset_stream_in,
clk_stream_out,
reset_stream_out,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 29; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk_stream_in;
input reset_stream_in;
input clk_stream_out;
input reset_stream_out;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 6: 0] fifo_wr_used;
wire fifo_empty;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = ~(&(fifo_wr_used[6:4]));
assign stream_out_empty = 'h0;
assign stream_out_valid = ~fifo_empty;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
dcfifo Data_FIFO (
// Inputs
.wrclk (clk_stream_in),
.wrreq (stream_in_ready & stream_in_valid),
.data ({stream_in_data, stream_in_endofpacket, stream_in_startofpacket}),
.rdclk (clk_stream_out),
.rdreq (stream_out_ready & ~fifo_empty),
// Outputs
.wrusedw (fifo_wr_used),
.rdempty (fifo_empty),
.q ({stream_out_data, stream_out_endofpacket, stream_out_startofpacket})
// synopsys translate_off
,
.aclr (),
.wrfull (),
.wrempty (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
Data_FIFO.intended_device_family = "Cyclone II",
Data_FIFO.lpm_hint = "MAXIMIZE_SPEED=7",
Data_FIFO.lpm_numwords = 128,
Data_FIFO.lpm_showahead = "ON",
Data_FIFO.lpm_type = "dcfifo",
Data_FIFO.lpm_width = DW + 3,
Data_FIFO.lpm_widthu = 7,
Data_FIFO.overflow_checking = "OFF",
Data_FIFO.rdsync_delaypipe = 5,
Data_FIFO.underflow_checking = "OFF",
Data_FIFO.use_eab = "ON",
Data_FIFO.wrsync_delaypipe = 5;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 10000; const int MAXK = 20; int V[MAXK + 3][MAXN + 3], Ans[MAXK + 3][MAXN + 3]; int main() { V[0][1] = 0; for (int j = 2; j <= MAXN; j++) { V[0][j] = 1; } for (int i = 1; i <= MAXK; i++) { int k = 1; for (int j = 1; j <= MAXN; j++) { if (k < MAXN && V[i - 1][k] < V[i - 1][k + 1] && V[i - 1][j] + V[i - 1][k] < j - 1) k++; V[i][j] = V[i - 1][j] + V[i - 1][k]; Ans[i][j] = k; } } int N, K; while (~scanf( %d%d , &N, &K)) { for (int i = 1; i <= K; i++) { for (int j = N; j > 1; j--) printf( %d , N - Ans[i][j] + 1); printf( %d n , N - Ans[i][1] + 1); } } return 0; }
|
#include<bits/stdc++.h> #define R register #define I inline #define ll long long #define ull unsigned long long #define LL __int128 #define db double using namespace std; #define pii pair<int,int> #define mp(x,y) make_pair(x,y) #define piii pair<pair<int,int>,int> #define mp3(x,y,z) make_pair(make_pair(x,y),z) #define fi first.first #define se first.second #define th second #define putint(x) printf( %d n ,x) #define putll(x) printf( %lld n ,x) #define putull(x) printf( %llu n ,x) #define lowbit(x) ((x)&(-(x))) #define inf (0x7fffffff) #define INF (1e18) #define eps (1e-8) I int read() { char ch=getchar(); int res=0,flag=1; while(ch< 0 ||ch> 9 ) { if(ch== - ) flag=-1; ch=getchar(); } while(ch>= 0 &&ch<= 9 ) { res=res*10+ch- 0 ; ch=getchar(); } return res*flag; } int a,b,k; int main() { a=read(); b=read(); k=read(); if(b==1) { if(k==0) { puts( YES ); cout<< 1 ; for(R int i=1;i<=a;++i) cout<< 0 ; puts( ); cout<< 1 ; for(R int i=1;i<=a;++i) cout<< 0 ; puts( ); return 0; } else { puts( NO ); return 0; } } if(a==0) { if(k==0) { puts( YES ); for(R int i=1;i<=b;++i) cout<< 1 ; puts( ); for(R int i=1;i<=b;++i) cout<< 1 ; puts( ); } else puts( NO ); return 0; } if(k<a+b-1) { puts( YES ); int pos1=a+b,pos2=a+b-k,cnt=0; for(R int i=1;i<=a+b;++i) { if(i==pos2) cout<<1,++cnt; else if(cnt<b-(i<pos2)) cout<<1,++cnt; else cout<<0; } puts( ); cnt=0; for(R int i=1;i<=a+b;++i) { if(i==pos2&&pos1!=pos2) { cout<<0; continue; } if(i==pos1) cout<<1,++cnt; else if(cnt<b-1) cout<<1,++cnt; else cout<<0; } puts( ); } else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<long long> v; long long t, p; char c; int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { p = 0ll; cin >> t >> c; p = ((p << 8) | t); cin >> t >> c; p = ((p << 8) | t); cin >> t >> c; p = ((p << 8) | t); cin >> t; p = ((p << 8) | t); v.push_back(p); } long long sub = 0ll; for (long long i = 31; i >= 0; i--) { sub = (sub | (1ll << i)); set<long long> s; for (int j = 0; j < n; j++) { s.insert(v[j] & sub); } if (s.size() == k) break; else if (s.size() > k) { sub = -1; break; } } if (sub == -1) cout << -1 << endl; else { vector<long long> last; last.push_back(sub & ((1ll << 8) - 1ll)); sub = (sub >> 8); last.push_back(sub & ((1ll << 8) - 1ll)); sub = (sub >> 8); last.push_back(sub & ((1ll << 8) - 1ll)); sub = (sub >> 8); last.push_back(sub & ((1ll << 8) - 1ll)); cout << last[3] << . << last[2] << . << last[1] << . << last[0] << endl; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
module etx_core(/*AUTOARG*/
// Outputs
tx_data_slow, tx_frame_slow, txrd_wait, txrr_wait, txwr_wait,
etx_cfg_access, etx_cfg_packet,
// Inputs
nreset, clk, tx_rd_wait, tx_wr_wait, txrd_access, txrd_packet,
txrd_full, txrr_access, txrr_packet, txrr_full, txwr_access,
txwr_packet, txwr_full, etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h999;
//Clocks,reset,config
input nreset;
input clk;
//IO interface
output [63:0] tx_data_slow;
output [3:0] tx_frame_slow;
input tx_rd_wait;
input tx_wr_wait;
//TXRD
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
input txrd_full;//sysclk domain
//TXRR
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
input txrr_full;//sysclk domain
//TXWR
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
input txwr_full; //sysclk domain
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
//for status?
wire[15:0] tx_status;
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire burst_enable; // From etx_cfg of etx_cfg.v
wire cfg_access; // From etx_arbiter of etx_arbiter.v
wire cfg_mmu_access; // From etx_cfg of etx_cfg.v
wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v
wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
wire etx_rd_wait; // From etx_protocol of etx_protocol.v
wire etx_remap_access; // From etx_remap of etx_remap.v
wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
wire etx_wait; // From etx_protocol of etx_protocol.v
wire etx_wr_wait; // From etx_protocol of etx_protocol.v
wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
wire gpio_enable; // From etx_cfg of etx_cfg.v
wire mmu_enable; // From etx_cfg of etx_cfg.v
wire remap_enable; // From etx_cfg of etx_cfg.v
wire tx_access; // From etx_protocol of etx_protocol.v
wire tx_burst; // From etx_protocol of etx_protocol.v
wire tx_enable; // From etx_cfg of etx_cfg.v
// End of automatics
//##################################################################
//# ARBITER (SELECT BETWEEN TX, RX, RR)
//##################################################################
etx_arbiter #(.ID(ID))
etx_arbiter (
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
.etx_access (etx_access),
.cfg_access (cfg_access),
.etx_packet (etx_packet[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_wait (etx_wait),
.etx_cfg_wait (etx_cfg_wait));
//##################################################################
//# REMAPPING DESTINATION ADDRESS
//##################################################################
/*etx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_\1[]),
.emesh_\(.*\)_out (etx_remap_\1[]),
.remap_en (remap_enable),
);
*/
etx_remap etx_remap (
/*AUTOINST*/
// Outputs
.emesh_access_out(etx_remap_access), // Templated
.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.emesh_access_in(etx_access), // Templated
.emesh_packet_in(etx_packet[PW-1:0]), // Templated
.remap_en (remap_enable), // Templated
.etx_wait (etx_wait));
//##################################################################
//# TABLE LOOKUP ADDRESS TRANSLATION
//##################################################################
/*emmu AUTO_TEMPLATE (.reg_access (cfg_mmu_access),
.reg_packet (etx_packet[PW-1:0]),
.emesh_\(.*\)_in (etx_remap_\1[]),
.emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (mmu_enable),
.\(.*\)_clk (clk),
.emesh_wait_in (etx_wait),
);
*/
emmu etx_mmu (.reg_rdata (), // not used (no readback from MMU)
/*AUTOINST*/
// Outputs
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
// Inputs
.wr_clk (clk), // Templated
.rd_clk (clk), // Templated
.nreset (nreset),
.mmu_en (mmu_enable), // Templated
.reg_access (cfg_mmu_access), // Templated
.reg_packet (etx_packet[PW-1:0]), // Templated
.emesh_access_in (etx_remap_access), // Templated
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (etx_wait)); // Templated
//##################################################################
//# ELINK PROTOCOL CONVERTER (104 bit-->64 bits)
//##################################################################
/*etx_protocol AUTO_TEMPLATE (
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_wait (etx_wait),
.etx_\(.*\) (emmu_\1[]),
);
*/
etx_protocol #(.ID(ID))
etx_protocol (
/*AUTOINST*/
// Outputs
.etx_rd_wait (etx_rd_wait), // Templated
.etx_wr_wait (etx_wr_wait), // Templated
.etx_wait (etx_wait), // Templated
.tx_burst (tx_burst),
.tx_access (tx_access),
.tx_data_slow (tx_data_slow[63:0]),
.tx_frame_slow (tx_frame_slow[3:0]),
// Inputs
.nreset (nreset),
.clk (clk),
.etx_access (emmu_access), // Templated
.etx_packet (emmu_packet[PW-1:0]), // Templated
.tx_enable (tx_enable),
.burst_enable (burst_enable),
.gpio_data (gpio_data[8:0]),
.gpio_enable (gpio_enable),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait));
//##################################################################
//# TX CONFIGURATION
//##################################################################
etx_cfg etx_cfg (.tx_status ({7'b0,
tx_burst,
tx_rd_wait,
tx_wr_wait,
txrr_wait,
txrd_wait,
txwr_wait,
txrr_full,
txrd_full,
txwr_full
}),
/*AUTOINST*/
// Outputs
.cfg_mmu_access (cfg_mmu_access),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.tx_enable (tx_enable),
.mmu_enable (mmu_enable),
.gpio_enable (gpio_enable),
.remap_enable (remap_enable),
.burst_enable (burst_enable),
.gpio_data (gpio_data[8:0]),
.ctrlmode (ctrlmode[3:0]),
.ctrlmode_bypass (ctrlmode_bypass),
// Inputs
.nreset (nreset),
.clk (clk),
.cfg_access (cfg_access),
.etx_access (etx_access),
.etx_packet (etx_packet[PW-1:0]),
.etx_wait (etx_wait));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../common/hdl")
// End:
|
#include <bits/stdc++.h> const int mxn = 1 << 19, mod = 998244353; inline int qpow(int x, int n) { int ans = 1; for (; n; n >>= 1, x = 1LL * x * x % mod) if (n & 1) ans = 1LL * ans * x % mod; return ans; } int r[mxn], w[mxn]; void fft_init(int n) { for (int i = 1; i < n - 1; ++i) r[i] = r[i >> 1] >> 1 | (i & 1 ? n >> 1 : 0); for (int h = 1; h < n; h <<= 1) { int temp = qpow(3, (mod - 1) / (h << 1)); for (int i = 0; i < (int)(h); ++i) w[h + i] = i ? 1LL * temp * w[h + i - 1] % mod : 1; } } void fft(int a[], int n, bool flag = false) { fft_init(n); for (int i = 1; i < n - 1; ++i) if (i < r[i]) std::swap(a[i], a[r[i]]); for (int h = 1; h < n; h <<= 1) for (int i = 0; i < n; i += h << 1) for (int j = 0; j < h; ++j) { int v = 1LL * a[i + h + j] * w[h + j] % mod; a[i + h + j] = a[i + j] - v >= 0 ? a[i + j] - v : a[i + j] + mod - v; a[i + j] = a[i + j] + v < mod ? a[i + j] + v : a[i + j] + v - mod; } if (flag) { std::reverse(a + 1, a + n); int in = qpow(n, mod - 2); for (int i = 0; i < (int)(n); ++i) a[i] = 1LL * a[i] * in % mod; } } struct poly : std::vector<int> { poly(int n, int x = 0) { assign(n, x); } poly(std::initializer_list<int> l) { clear(); for (int x : l) push_back(x); } friend inline poly operator*(const poly &a, const poly &b) { int sz = 1; while (sz < (int)a.size() + (int)b.size() - 1) sz <<= 1; static int A[mxn], B[mxn]; for (int i = 0; i < (int)(sz); ++i) A[i] = i < (int)a.size() ? a[i] : 0; for (int i = 0; i < (int)(sz); ++i) B[i] = i < (int)b.size() ? b[i] : 0; fft(A, sz), fft(B, sz); for (int i = 0; i < (int)(sz); ++i) A[i] = 1LL * A[i] * B[i] % mod; fft(A, sz, true); poly c(a.size() + b.size() - 1); for (int i = 0; i < (int)(c.size()); ++i) c[i] = A[i]; return c; } }; int n; int deg[mxn]; int fac[mxn]; poly calc(int l, int r) { if (l + 1 == r) return {1, deg[l]}; int m = (l + r) >> 1; return calc(l, m) * calc(m, r); } int main() { for (int i = 0; i < (int)(mxn); ++i) fac[i] = i ? 1LL * i * fac[i - 1] % mod : 1; scanf( %d , &n); for (int i = 0; i < (int)(n - 1); ++i) { int u, v; scanf( %d %d , &u, &v); --u, --v; ++deg[u]; ++deg[v]; } for (int i = 0; i < (int)(n); ++i) if (i) --deg[i]; poly p = calc(0, n); int ans = 0; for (int i = 0; i < (int)(p.size()); ++i) { int cur = 1LL * p[i] * fac[n - i] % mod; if (i & 1) ans = (ans + mod - cur) % mod; else ans = (ans + cur) % mod; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; int h[100000], max[100001]; cin >> n; for (int i = 0; i < n; ++i) { cin >> h[i]; } max[n] = h[n - 1] - 1; for (int i = n - 1; i >= 0; --i) { if (h[i] > max[i + 1]) max[i] = h[i]; else max[i] = max[i + 1]; } for (int i = 0; i < n; ++i) { if (max[i + 1] >= h[i]) cout << max[i + 1] - h[i] + 1 << ; else cout << 0 << ; } cout << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:29:19 07/23/2015
// Design Name: knns_seq
// Project Name: kNNS_TD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: knns_seq
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module knns_tb;
// Inputs
reg clk;
reg rst;
reg [31:0] x1;
reg [31:0] y1;
reg [31:0] x2;
reg [31:0] y2;
// Outputs
wire [639:0] min_val_out;
// Instantiate the Unit Under Test (UUT)
k_nns_seq_td uut (
.clk(clk),
.rst(rst),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.min_val_out(min_val_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
x1 = 0;
y1 = 0;
x2 = 10;
y2 = 10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1;
#130;
rst = 0;
#20;
x1 = 10;
y1 = 5;
x2 = 10;
y2 = 4;
#100;
x2 = 11;
y2 = 5;
#100;
x2 = 11;
y2 = 5;
#100;
x2 = 18;
y2 = 5;
#100;
x2 = 12;
y2 = 5;
#100;
x2 = 14;
y2 = 25;
#100;
x2 = 15;
y2 = 25;
#100;
x2 = 10;
y2 = 6;
#100;
x2 = 10;
y2 = 7;
#100;
x2 = 10;
y2 = 18;
#100;
x2 = 10;
y2 = 19;
#100;
x2 = 20;
y2 = 10;
#100;
x2 = 10;
y2 = 7;
#100;
x2 = 9;
y2 = 4;
#100;
x2 = 10;
y2 = 4;
#100;
x2 = 25;
y2 = 10;
#100;
x2 = 10;
y2 = 24;
#100;
x2 = 11;
y2 = 5;
#100;
x2 = 19;
y2 = 5;
end
always begin
#50;
clk = ~clk;
end
always @ (posedge clk) begin
end
endmodule
|
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
output bit sysrstn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
input enable,
input init_done,
output jtag_TCK,
output jtag_TMS,
output jtag_TDI,
output jtag_TRSTn,
output srstn,
input jtag_TDO_data,
input jtag_TDO_driven,
output [31:0] exit
);
reg [31:0] tickCounterReg;
wire [31:0] tickCounterNxt;
assign tickCounterNxt = (tickCounterReg == 0) ? TICK_DELAY : (tickCounterReg - 1);
bit r_reset;
wire [31:0] random_bits = $random;
wire #0.1 __jtag_TDO = jtag_TDO_driven ?
jtag_TDO_data : random_bits[0];
bit __jtag_TCK;
bit __jtag_TMS;
bit __jtag_TDI;
bit __jtag_TRSTn;
int __exit;
bit sysrstn=1;
reg init_done_sticky;
assign #0.1 jtag_TCK = __jtag_TCK;
assign #0.1 jtag_TMS = __jtag_TMS;
assign #0.1 jtag_TDI = __jtag_TDI;
assign #0.1 jtag_TRSTn = __jtag_TRSTn;
assign srstn = sysrstn;
assign #0.1 exit = __exit;
always @(posedge clock) begin
r_reset <= reset;
if (reset || r_reset) begin
__exit = 0;
tickCounterReg <= TICK_DELAY;
init_done_sticky <= 1'b0;
__jtag_TCK = !__jtag_TCK;
end else begin
init_done_sticky <= init_done | init_done_sticky;
if (enable && init_done_sticky) begin
tickCounterReg <= tickCounterNxt;
if (tickCounterReg == 0) begin
__exit = jtag_tick(
__jtag_TCK,
__jtag_TMS,
__jtag_TDI,
__jtag_TRSTn,
sysrstn,
__jtag_TDO);
end
end // if (enable && init_done_sticky)
end // else: !if(reset || r_reset)
end // always @ (posedge clock)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2I_PP_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_PP_BLACKBOX_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cart/cart.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Cartridge emulator for an fpga-based NES emulator. This block provides access to cartridge
* memories (PRG-ROM, CHR-ROM) and emulates mapper functionality in order to play emulation ROMs.
* The intention is that this interface could be re-implemented on top of a hardware NES
* cartridge, where almost all of the work would pass through directly.
***************************************************************************************************/
module cart
(
input wire clk_in, // system clock signal
// Mapper config data.
input wire [39:0] cfg_in, // cartridge config (from iNES header)
input wire cfg_upd_in, // pulse signal on cfg_in update
// PRG-ROM interface.
input wire prg_nce_in, // prg-rom chip enable (active low)
input wire [14:0] prg_a_in, // prg-rom address
input wire prg_r_nw_in, // prg-rom read/write select
input wire [ 7:0] prg_d_in, // prg-rom data in
output wire [ 7:0] prg_d_out, // prg-rom data out
// CHR-ROM interface.
input wire [13:0] chr_a_in, // chr-rom address
input wire chr_r_nw_in, // chr-rom read/write select
input wire [ 7:0] chr_d_in, // chr-rom data in
output wire [ 7:0] chr_d_out, // chr-rom data out
output wire ciram_nce_out, // vram chip enable (active low)
output wire ciram_a10_out // vram a10 value (controls mirroring)
);
wire prgrom_bram_we;
wire [14:0] prgrom_bram_a;
wire [7:0] prgrom_bram_dout;
// Block ram instance for PRG-ROM memory range (0x8000 - 0xFFFF). Will eventually be
// replaced with SRAM.
single_port_ram_sync #(.ADDR_WIDTH(15),
.DATA_WIDTH(8)) prgrom_bram(
.clk(clk_in),
.we(prgrom_bram_we),
.addr_a(prgrom_bram_a),
.din_a(prg_d_in),
.dout_a(prgrom_bram_dout)
);
assign prgrom_bram_we = (~prg_nce_in) ? ~prg_r_nw_in : 1'b0;
assign prg_d_out = (~prg_nce_in) ? prgrom_bram_dout : 8'h00;
assign prgrom_bram_a = (cfg_in[33]) ? prg_a_in[14:0] : { 1'b0, prg_a_in[13:0] };
wire chrrom_pat_bram_we;
wire [7:0] chrrom_pat_bram_dout;
// Block ram instance for "CHR Pattern Table" memory range (0x0000 - 0x1FFF).
single_port_ram_sync #(.ADDR_WIDTH(13),
.DATA_WIDTH(8)) chrrom_pat_bram(
.clk(clk_in),
.we(chrrom_pat_bram_we),
.addr_a(chr_a_in[12:0]),
.din_a(chr_d_in),
.dout_a(chrrom_pat_bram_dout)
);
assign ciram_nce_out = ~chr_a_in[13];
assign ciram_a10_out = (cfg_in[16]) ? chr_a_in[10] : chr_a_in[11];
assign chrrom_pat_bram_we = (ciram_nce_out) ? ~chr_r_nw_in : 1'b0;
assign chr_d_out = (ciram_nce_out) ? chrrom_pat_bram_dout : 8'h00;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 20; long long int dp[MAXN][MAXN]; long long int tav[MAXN]; long long int n; string s; long long int dtoc(char x) { return x - 0 ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); tav[0] = 1; for (int i = 1; i < MAXN; i++) { tav[i] = 10 * tav[i - 1]; } cin >> n; cin >> s; for (int i = 0; i <= n; i++) { for (int j = 0; j <= n; j++) { if (i) { dp[i][j] = dp[i - 1][j] + dtoc(s[2 * n - i - j]) * tav[i - 1]; } if (j) { dp[i][j] = max(dp[i][j], dp[i][j - 1] + dtoc(s[2 * n - i - j]) * tav[j - 1]); } } } int i = n; int j = n; while (i > 0 || j > 0) { if (i && dp[i - 1][j] + dtoc(s[2 * n - i - j]) * tav[i - 1] == dp[i][j]) { i--; cout << H ; } else { j--; cout << M ; } } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000000000001, mod = 1000000007; long long toi(string s) { long long a; istringstream in(s); in >> a; return a; } int main() { string s; cin >> s; for (int i = 1; i < s.length(); i++) if (s[i] == s[i - 1]) { cout << Impossible ; return 0; } int a, b; for (int i = 0; i < s.length(); i++) for (int j = i + 1; j < s.length(); j++) if (s[i] == s[j]) { a = i; b = j; break; } char arr[2][13]; int A = b - a - 1, B = 26 - A - 1; arr[0][A / 2] = s[a]; int x = 0, y = A / 2; int cnt = A; int p = a + 1; while (cnt) { if (x == 0 && y > 0) y--; else if (x == 0 && y == 0) x++; else y++; arr[x][y] = s[p]; p++; cnt--; } cnt = B; x = 0; y = A / 2; p = (b + 1) % 27; while (cnt) { if (x == 0 && y < 12) y++; else if (x == 0 && y == 12) x++; else y--; arr[x][y] = s[p]; p++; p %= 27; cnt--; } for (int i = 0; i < 13; i++) cout << arr[0][i]; cout << n ; for (int i = 0; i < 13; i++) cout << arr[1][i]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T sqr(T a) { return a * a; }; template <typename T> void dprint(T begin, T end) { for (auto i = begin; i != end; i++) cerr << (*i) << ; cerr << n ; }; const int maxn = 500 + 5; int n, step[maxn * 2]; string ans; pair<int, int> loc[maxn * 2]; bool query(int r1, int c1, int r2, int c2) { cout << ? << r1 << << c1 << << r2 << << c2 << endl; cout.flush(); cin >> ans; return ans == YES ; } int main() { scanf( %d , &n); loc[0] = pair<int, int>(1, 1); for (int i = 0; i < n - 1; i++) { if (query(loc[i].first + 1, loc[i].second, n, n)) { loc[i + 1] = pair<int, int>(loc[i].first + 1, loc[i].second); step[i] = 0; continue; } if (query(loc[i].first, loc[i].second + 1, n, n)) { loc[i + 1] = pair<int, int>(loc[i].first, loc[i].second + 1); step[i] = 1; continue; } } loc[2 * n - 2] = pair<int, int>(n, n); for (int i = 2 * n - 2; i > n; i--) { if (query(loc[i - n].first, loc[i - n].second, loc[i].first, loc[i].second - 1)) { loc[i - 1] = pair<int, int>(loc[i].first, loc[i].second - 1); step[i - 1] = 1; continue; } if (query(loc[i - n].first, loc[i - n].second, loc[i].first - 1, loc[i].second)) { loc[i - 1] = pair<int, int>(loc[i].first - 1, loc[i].second); step[i - 1] = 0; continue; } } if (loc[n].first == loc[n - 1].first + 1) step[n - 1] = 0; else step[n - 1] = 1; cout << ! ; for (int i = 0; i < 2 * n - 2; i++) if (step[i] == 0) cout << D ; else cout << R ; cout << endl; cout.flush(); return 0; }
|
module fetch(IR_load_mux,new_IR_multi,equ,pr2_IR ,pr3_IR ,pr4_IR, pr5_IR,fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem, PCWrite, PCOut, IROut, incPCOut, clk, reset);
output [15:0] PCOut, IROut, incPCOut;
input [15:0]new_IR_multi;
wire [15:0] next_IR;//read from instruction memory
input IR_load_mux;
input [15:0] fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem;
input [15:0] pr2_IR ,pr3_IR ,pr4_IR, pr5_IR;
wire [ 2:0] fromForwarding;
input PCWrite, clk, reset;
input equ;
wire [15:0] PCWriteWire;
pc_forwarding f_u(.clk(clk),.equ(equ),.pr2_IR(pr2_IR),.pr3_IR(pr3_IR),.pr4_IR(pr4_IR),.pr5_IR(pr5_IR),.pc_mux_select(fromForwarding)) ;
mux16x8 PCWriteSelect(.data0(incPCOut), .data1(fromPipe3RFOut), .data2(fromPipe5Mem), .data3(fromPipe2_PCim), .data4(fromPipe3PCInc), .data5(fromPipe2_970), .data6(fromPipe4_Aluout), .data7(16'b0), .selectInput(fromForwarding), .out(PCWriteWire));
register16 PCReg(.clk(clk), .out(PCOut), .in(PCWriteWire), .write(PCWrite), .reset(reset));
plus_one PlusOne(.in(PCOut), .out(incPCOut));
instr_mem InstructionMemory(.readAdd(PCOut), .out(next_IR));
mux16x2 IR_write_select(.data0(next_IR), .data1(new_IR_multi), .selectInput(IR_load_mux), .out(IROut));
endmodule
module pc_forwarding(clk,equ,pr2_IR,pr3_IR,pr4_IR,pr5_IR,pc_mux_select);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
parameter rb=3'd1;
parameter c=3'd2;
parameter m= 3'd3;
parameter one = 3'd4;
parameter h = 3'd5;
parameter a = 3'd6;
output reg [2:0] pc_mux_select;
input [15:0] pr2_IR,pr3_IR,pr4_IR,pr5_IR;
input equ,clk;
wire [5:0] op2,op3,op4,op5;
wire[2:0] pr2RA,pr2RB,pr4RC,pr5RA;
assign op2={pr2_IR[15:12],pr2_IR[1:0]};
assign op3={pr3_IR[15:12],pr3_IR[1:0]};
assign op4={pr4_IR[15:12],pr4_IR[1:0]};
assign op5={pr5_IR[15:12],pr5_IR[1:0]};
assign pr2RA = pr2_IR[11:9];
assign pr2RB = pr2_IR[8:6];
assign pr4RC = pr2_IR[5:3];
assign pr5RA = pr5_IR[11:9];
always @(negedge clk)
begin
if((op5[5:2]==LW||op5[5:2]==LM)&&pr5RA==3'b111)
pc_mux_select=c;//from mem
else if(op2[5:2]==LHI&&pr2RA==3'b111)
pc_mux_select=h;//970 from pr2
else if((op4==ADD||op4==NDU||op4==ADC||op4==ADZ||op4==NDC||op4==NDC||op4==NDZ)&&(pr4RC==3'b111))
pc_mux_select=a;//ALU_out in pr4
else if(op4[5:2]==ADI&&pr2RB==3'b111)
pc_mux_select=a;//ALU_out in pr4
else if(equ==1&&op3[5:2]==BEQ)
pc_mux_select=one;//pc+Im6, in pr3
else if(op3[5:2]==JLR)
pc_mux_select=rb;//from RFout2 of pr3
else if(op2[5:2]==JAL)
pc_mux_select=m;//PC+Im6 , in pr2
else
pc_mux_select=0;
end//always
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi(3.14159265358979); int a[100010], d[100010]; int main() { int x, i, j, n; scanf( %d , &n); scanf( %d , &x); for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < n; i++) d[i] = abs(a[i] - x); int ans = 0; if (n == 1) ans = 0; else if (x >= a[n - 1]) ans = d[1]; else if (x <= a[0]) ans = d[n - 2]; else if (n == 2) ans = min(d[0], d[1]); else if (x > a[0] && x <= a[1]) ans = min(d[n - 1], min(2 * d[0] + d[n - 2], 2 * d[n - 2] + d[0])); else if (x < a[n - 1] && x >= a[n - 2]) ans = min(d[0], min(2 * d[n - 1] + d[1], 2 * d[1] + d[n - 1])); else ans = min(2 * d[0] + d[n - 2], min(2 * d[n - 2] + d[0], min(2 * d[n - 1] + d[1], 2 * d[1] + d[n - 1]))); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[200100], b[200100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { int x; cin >> x; b[x] = i; } int mx = 0; for (int i = 1; i <= n; i++) { a[i] = b[a[i]]; if (a[i - 1] < a[i]) mx++; else break; } cout << n - mx; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// msg2946
int A [7][1], B [8][1];
int a [1], b [1];
always_ff @(posedge clk) begin
a <= A[crc[2:0]];
b <= B[crc[2:0]];
end
wire [63:0] result = {a[0], b[0]};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
A[0][0] <= 32'h1_0;
A[1][0] <= 32'h1_1;
A[2][0] <= 32'h1_2;
A[3][0] <= 32'h1_3;
A[4][0] <= 32'h1_4;
A[5][0] <= 32'h1_5;
A[6][0] <= 32'h1_6;
B[0][0] <= 32'h2_0;
B[1][0] <= 32'h2_1;
B[2][0] <= 32'h2_2;
B[3][0] <= 32'h2_3;
B[4][0] <= 32'h2_4;
B[5][0] <= 32'h2_5;
B[6][0] <= 32'h2_6;
B[7][0] <= 32'h2_7;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_1_V
`define SKY130_FD_SC_HDLL__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_1_V
|
module main;
parameter use_wid = 4;
reg [use_wid-1:0] d;
wire [use_wid-1:0] q;
reg clk;
B #(.wid(use_wid)) dut (.Q(q), .D(d), .C(clk));
initial begin
clk = 0;
d = 4'b0000;
#1 clk = 1;
#1 clk = 0;
if (q !== 4'b0000) begin
$display("FAILED -- d=%b, q=%b", d, q);
$finish;
end
d = 4'b1111;
#1 clk = 1;
#1 clk = 0;
if (q !== 4'b1111) begin
$display("FAILED -- d=%b, q=%b", d, q);
$finish;
end
$display("PASSED");
end
endmodule // main
/*
* although the wid paramter is default to 3 in this module, the point
* of this test is to have the instantiating module (main) give a
* different value and have that value properly handlued in all the
* situations of this module.
*/
module B
#(parameter wid = 3)
(output [wid-1:0] Q,
input [wid-1:0] D,
input C);
// the override from main will cause this to be a width of 4.
prim U [wid-1:0] (Q, D, C);
//prim U [wid-1:0] (.Q(Q), .D(D), .C(C));
endmodule // B
module prim(output reg Q, input D, C);
always @(posedge C)
Q <= D;
endmodule // prim
|
module rx_frontend
#(parameter BASE = 0,
parameter IQCOMP_EN = 1)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [15:0] adc_a, input adc_ovf_a,
input [15:0] adc_b, input adc_ovf_b,
output [23:0] i_out, output [23:0] q_out,
input run,
output [31:0] debug
);
reg [15:0] adc_i, adc_q;
wire [17:0] adc_i_ofs, adc_q_ofs;
wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr;
wire swap_iq;
setting_reg #(.my_addr(BASE), .width(1)) sr_8
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(swap_iq),.changed());
always @(posedge clk)
if(swap_iq) // Swap
{adc_i,adc_q} <= {adc_b,adc_a};
else
{adc_i,adc_q} <= {adc_a,adc_b};
setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(mag_corr),.changed());
setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_corr),.changed());
generate
if(IQCOMP_EN == 1)
begin
rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_i,2'b00}),.out(adc_i_ofs));
rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_q,2'b00}),.out(adc_q_ofs));
MULT18X18S mult_mag_corr
(.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) );
MULT18X18S mult_phase_corr
(.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
add2_and_clip_reg #(.WIDTH(24)) add_clip_i
(.clk(clk), .rst(rst),
.in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
.sum(i_out), .strobe_out());
add2_and_clip_reg #(.WIDTH(24)) add_clip_q
(.clk(clk), .rst(rst),
.in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
.sum(q_out), .strobe_out());
end // if (IQCOMP_EN == 1)
else
begin
rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_i,8'b00}),.out(i_out));
rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_q,8'b00}),.out(q_out));
end // else: !if(IQCOMP_EN == 1)
endgenerate
endmodule // rx_frontend
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 24 17:28:31 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_buffer_1_0 -prefix
// system_vga_buffer_1_0_ system_vga_buffer_1_0_stub.v
// Design : system_vga_buffer_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase w/ known labels - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000: result = 0;
3'b001: result = 1 ;
3'b010: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED case 3.9A - case (expr) lab1: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED case 3.9A - case (expr) lab2: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b011
if(result !=1)
begin
$display("FAILED case 3.9A - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_bottom_rptr2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ctu_bottom_rptr2(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
`define SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ls__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.07.2017 21:09:25
// Design Name:
// Module Name: t_scp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_scp;
// Inputs
reg clk, reset;
// Initialise the Unit Under Test
singlecycleprocessor uut (
.clk( clk ),
.reset( reset)
);
// Initialise the clock
initial begin
clk = 0;
#20;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
// Stimulus here
initial begin
$display(t_scp.uut.ID.jumpaddr);
$display(t_scp.uut.ID.WAinstrD);
$display(t_scp.uut.IF.WAinstrF);
$display(t_scp.uut.IF.PCPrime);
$display(t_scp.uut.IF.PC);
$display(t_scp.uut.IF.PCJump);
reset = 0;
//#30 reset = 1;
//#20 reset = 0;
end
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input PL_SGMII_REFCLK_125M_P,
input PL_SGMII_REFCLK_125M_N,
output [1:0] pl_led ,
output [1:0] pl_pmod
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire PL_SGMII_REFCLK_125M;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_inst (
.O(PL_SGMII_REFCLK_125M), // Buffer output
.I(PL_SGMII_REFCLK_125M_P), // Diff_p buffer input (connect directly to top-level port)
.IB(PL_SGMII_REFCLK_125M_N) // Diff_n buffer input (connect directly to top-level port)
);
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge PL_SGMII_REFCLK_125M) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q, ans[600005]; bitset<505> a[505][505], b[505][505]; char mp[505][505]; struct ccf { int x1, y1, x2, y2, id; }; void solve(int l, int r, vector<ccf> qus) { if (!qus.size()) return; int mid = (l + r) >> 1; for (int i = mid; i >= l; i--) { for (int j = m; j >= 1; j--) { a[i][j].reset(); if (i == mid) a[mid][j][j] = (mp[mid][j] == . ); if (i != mid && mp[i + 1][j] == . ) a[i][j] |= a[i + 1][j]; if (j != m && mp[i][j + 1] == . ) a[i][j] |= a[i][j + 1]; } } for (int i = mid; i <= r; i++) { for (int j = 1; j <= m; j++) { b[i][j].reset(); if (i == mid) b[mid][j][j] = (mp[mid][j] == . ); if (i != mid && mp[i - 1][j] == . ) b[i][j] |= b[i - 1][j]; if (j != 1 && mp[i][j - 1] == . ) b[i][j] |= b[i][j - 1]; } } vector<ccf> askl, askr; int len = qus.size(); for (int i = 0; i < len; i++) { if (qus[i].x2 < mid) askl.push_back(qus[i]); else if (qus[i].x1 > mid) askr.push_back(qus[i]); else ans[qus[i].id] = (a[qus[i].x1][qus[i].y1] & b[qus[i].x2][qus[i].y2]).any(); } solve(l, mid - 1, askl); solve(mid + 1, r, askr); } vector<ccf> eve; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) cin >> (mp[i] + 1); scanf( %d , &q); for (int i = 1; i <= q; i++) { ccf qus; qus.id = i; scanf( %d%d%d%d , &qus.x1, &qus.y1, &qus.x2, &qus.y2); eve.push_back(qus); } solve(1, n, eve); for (int i = 1; i <= q; i++) if (ans[i]) puts( Yes ); else puts( No ); return 0; }
|
/*
******************************************************************************
* File Name : tb_ada_reg_file.v
* Project : NR1K processor
* Version : 0.1
* Date : Aug 17th, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Testbench for the EXU (execution unit)
******************************************************************************
*/
`timescale 1ns / 1ns
`include "ada_defines.v"
`define cycle 10
module tb_ada_reg_file;
//Inputs
reg clk;
reg rst;
reg [4:0] read_addr_a;
reg [4:0] read_addr_b;
reg [4:0] write_addr;
reg [31:0] write_data;
reg we;
// outputs
wire [31:0] read_data_a;
wire [31:0] read_data_b;
//--------------------------------------------------------------------------
// UUT
//--------------------------------------------------------------------------
ada_reg_file uut(
.clk(clk),
.read_addr_a(read_addr_a),
.read_addr_b(read_addr_b),
.write_addr(write_addr),
.write_data(write_data),
.we(we),
.read_data_a(read_data_a),
.read_data_b(read_data_b)
);
//--------------------------------------------------------------------------
// Setup
//--------------------------------------------------------------------------
initial begin
// Initialize Inputs
clk = 1;
rst = 1;
read_addr_a = 0;
read_addr_b = 0;
write_addr = 0;
write_data = 0;
we = 0;
// dump the wave file
$dumpfile("tb_reg_file.vcd");
$dumpvars;
end
//--------------------------------------------------------------------------
// Clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk = !clk;
end
//--------------------------------------------------------------------------
// simulation
//--------------------------------------------------------------------------
integer i = 0;
reg [31:0] temp [1:31];
initial begin
rst = #(5*`cycle)0;
$display("----------------------------------------------------------");
$display("time\tTemp\t\tWA\tWD");
$display("----------------------------------------------------------");
// fill the register file
for(i = 1; i < 32; i = i + 1) begin
@(negedge clk)
temp[i] = $random;
write_addr = i;
write_data = temp[i];
we = 1;
@(negedge clk)
we = 0;
$display("%4d\t%h\t%h\t%h", $time, temp[i], write_addr, write_data);
end
@(negedge clk)
we = 0;
write_addr = 0;
write_data = 0;
// pause
#(`cycle);
//Read the register file. Port 1
$display("----------------------------------------------------------");
$display("Test Port 1");
for(i = 0; i < 32; i = i + 1) begin
@(posedge clk)
read_addr_a = i;
#5;
if (i == 5'd0 && read_data_a != 32'd0) begin
$display("Error: Register 0 MUST READ ZERO");
end
else if (i != 5'd0 && read_data_a != temp[i]) begin
$display("Error Port 1: Register [%3d] must read %d. Read %d instead.", i, temp[i], read_data_a);
end
end
//Read the register file. Port 2
$display("----------------------------------------------------------");
$display("Test Port 2");
for(i = 0; i < 32; i = i + 1) begin
@(posedge clk)
read_addr_b = i;
#5;
if (i == 5'd0 && read_data_b != 32'd0) begin
$display("Error: Register 0 MUST READ ZERO\n");
end
else if (i != 5'd0 && read_data_b != temp[i]) begin
$display("Error Port 2: Register [%3d] must read %d. Read %d instead.", i, temp[i], read_data_b);
end
end
$display("----------------------------------------------------------");
$finish;
end
endmodule
|
//****************************************************************************/
// Copyright (C) yyyy Ronan Barzic -
// Date : Fri Apr 22 09:40:43 2016
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : two_phase_event_gen.v
//
// Description : A random 2-phase event generator
//
//
//
//****************************************************************************/
`timescale 1ns/1ps
module two_phase_event_gen (/*AUTOARG*/
// Outputs
req,
// Inputs
run, ack
);
input run;
output req;
input ack;
parameter spread=200;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
reg req;
task handshake_2ph_rise;
begin
wait(ack === 1'b0);
req <= 1'b1;
wait(ack === 1'b1);
end
endtask
task handshake_2ph_fall;
begin
wait(ack === 1'b1);
req = 1'b0;
wait(ack === 1'b0);
end
endtask
initial begin
req <= 0;
#1;
while(1) begin
wait(run===1'b1);
#($unsigned($random) % spread);
handshake_2ph_rise();
#($unsigned($random) % spread);
handshake_2ph_fall();
end
end
endmodule // two_phase_event_gen
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = n * (n + 1) / 2; for (int i = n; i > 0; i--) { sum += (n - i) * (i - 1); } cout << sum; }
|
#include <bits/stdc++.h> const int maxn = 301, maxk = 10, maxs = 1 << 9, INF = 0x3f3f3f3f; int n, a[maxn], c[maxn], tot, fact[maxk], f[maxs], ans = INF; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i); for (int i = 1; i <= n; ++i) scanf( %d , c + i); for (int i = 1, j, k; i <= n; ++i) { tot = 0; for (j = 2, k = a[i]; j * j <= k; ++j) if (k % j == 0) { fact[tot++] = j; while (k % j == 0) k /= j; } if (k > 1) fact[tot++] = k; memset(f, 0x3f, sizeof f); f[(1 << tot) - 1] = c[i]; for (j = 1; j <= n; ++j) { int mask = 0; for (k = 0; k < tot; ++k) if (a[j] % fact[k] == 0) mask |= 1 << k; for (int s = (1 << tot) - 1; s >= 0; --s) if (f[s & mask] > f[s] + c[j]) f[s & mask] = f[s] + c[j]; } if (ans > f[0]) ans = f[0]; } if (ans == INF) puts( -1 ); else printf( %d n , ans); return 0; }
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/byteregister.v:1" *)
module ByteRegister(Reset_n_i, Clk_i, D_i, Q_o, Enable_i);
(* src = "../../verilog/byteregister.v:14" *)
wire [7:0] \$0\Q_o[7:0] ;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/byteregister.v:5" *)
input Clk_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/byteregister.v:7" *)
input [7:0] D_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/byteregister.v:11" *)
input Enable_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/byteregister.v:9" *)
output [7:0] Q_o;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/byteregister.v:3" *)
input Reset_n_i;
(* src = "../../verilog/byteregister.v:14" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$6 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Q_o[7:0] ),
.Q(Q_o)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$4 (
.A(Q_o),
.B(D_i),
.S(Enable_i),
.Y(\$0\Q_o[7:0] )
);
endmodule
|
//bug1061
//typedef logic [7:0] foo_t;
module ptype
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input foo_t a, // To b0 of ptype_buf.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foo_t y0, // From b0 of ptype_buf.v
output logic [7:0] y1, // From b1 of ptype_buf.v
output TYPE_T y2 // From b2 of ptype_buf.v
// End of automatics
);
ptype_buf #(.TYPE_T(foo_t)) b0
(// Outputs
.y (y0),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.TYPE_T(logic [7:0])) b1
(// Outputs
.y (y1),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.WIDTH(8)) b2
(// Outputs
.y (y2),
/*AUTOINST*/
// Inputs
.a (a));
endmodule
module ptype_buf
#(parameter WIDTH = 1,
parameter type TYPE_T = logic [WIDTH-1:0])
(output TYPE_T y,
input TYPE_T a);
assign y = a;
endmodule
///--------------
// Example in docs
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [9:0] i; // To instName of InstModule.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output upper_t o; // From instName of InstModule.v
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i[9:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// verilog-auto-inst-param-value-type:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer () ////
//// - Olof Kindgren () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2011 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// 2011-07-06 Olof Kindgren <>
// Reset AdressMiss when a new frame arrives. Otherwise it will report
// the last value when a frame is less than seven bytes
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
`include "timescale.v"
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq0;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= 1'b1;
else
RxAbort <= 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= 1'b0;
else if(ByteCntEq0)
AddressMiss <= 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
|
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
/*
***********************************************************
davide 07/03/2017 - 14:00 :
looks like working as expected. just changed enable signal to softreset.
now the module counting process is never suspended.
softreset signal presence erases values from all counters.
please note that softreset needs to stay high for a single clock cycle,
leaving it low for more time will produce a bad behaviour of the system.
TODO: check if softreset is introducing any bug.
TODO: ack is not needed, remove it from the system.
TODO: check if reset behaviour is correct or not.
davide 08/03/2017 - 18:50 :
removed ack
TODO: check if softreset is introducing any bug.
TODO: check if reset behaviour is correct or not.
************************************************************
*/
module SSDS_spoof_modified(
clk,
cyc,
we,
err,
write_out,
read_out,
err_out,
softreset,
reset
);
input clk;
input cyc;
input we;
input err;
input reset;
input softreset;
output [31:0] write_out;
output [31:0] read_out;
output [31:0] err_out;
wire clk;
wire cyc;
wire we;
wire err;
wire softreset; // -- count reset signal -- //
wire reset;
// -- outputs of the module -- //
wire [31:0] read_out;
wire [31:0] write_out;
wire [31:0] err_out;
// -- HLSM counters -- //
reg [31:0] CountRead;
reg [31:0] CountRead_Next;
reg [31:0] CountWrite;
reg [31:0] CountWrite_Next;
reg [31:0] CountError;
reg [31:0] CountError_Next;
// -- state registers -- //
reg [2:0] CurrentState;
reg [2:0] NextState;
// -- FSM states, Placeholder to implement safe fsm -- //
localparam STATE_Initial = 3'd0,
STATE_1 = 3'd1,
STATE_2 = 3'd2,
STATE_3_Placeholder = 3'd3,
STATE_4_Placeholder = 3'd4,
STATE_5_Placeholder = 3'd5,
STATE_6_Placeholder = 3'd6,
STATE_7_Placeholder = 3'd7;
// -- synchronous state and registers transition -- //
always@ (posedge clk, posedge reset)
begin: STATE_TRANS
if(reset == 1)
begin
CurrentState <= STATE_Initial;
CountRead <= 0;
CountWrite <= 0;
CountError <= 0;
CountRead_Next <= 0;
CountWrite_Next <= 0;
CountError_Next <= 0;
end
else
begin
CurrentState <= NextState;
CountRead <= CountRead_Next;
CountWrite <= CountWrite_Next;
CountError <= CountError_Next;
end
end
// -- output logic -- //
assign read_out = CountRead;
assign write_out = CountWrite;
assign err_out = CountError;
// -- state transition combinational logic -- //
always@ (*)
begin
case(CurrentState)
STATE_Initial: begin
if(cyc)
begin
if(we) NextState <= STATE_1;
else NextState <= STATE_2;
end
else NextState <= STATE_Initial;
if(softreset) // -- if in STATE INITIAL can soft reset without any problem -- //
begin
CountWrite_Next <= 0;
CountRead_Next <= 0;
CountError_Next <= 0;
end
end
// -- for STATE_1 and STATE_2 need to check if we are softresetting or not -- //
STATE_1: begin
if(err)
begin
NextState <= STATE_Initial;
if(!softreset) CountError_Next <= CountError +1;
else
begin
CountWrite_Next <= 0;
CountRead_Next <= 0;
CountError_Next <= 1;
end
end
else
begin
if(!cyc)
begin
NextState <= STATE_Initial;
if(!softreset) CountWrite_Next <= CountWrite +1;
else
begin
CountWrite_Next <= 1;
CountRead_Next <= 0;
CountError_Next <= 0;
end
end
end
end
STATE_2: begin
if(err)
begin
NextState <= STATE_Initial;
if(!softreset) CountError_Next <= CountError +1;
else
begin
CountWrite_Next <= 0;
CountRead_Next <= 0;
CountError_Next <= 1;
end
end
else
begin
if(!cyc)
begin
NextState <= STATE_Initial;
if(!softreset) CountRead_Next <= CountRead +1;
else
begin
CountWrite_Next <= 0;
CountRead_Next <= 1;
CountError_Next <= 0;
end
end
end
end
STATE_3_Placeholder: begin
end
STATE_4_Placeholder: begin
end
STATE_5_Placeholder: begin
end
STATE_6_Placeholder: begin
end
STATE_7_Placeholder: begin
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
`define BCR_ADDR (23'b000_10_00_0_0_011_1_0_0_00_01_0_001)
// || | | ||| | | || | |||
// Address BCR -+' | | ||| | | || | |||
// Synchronous -------' | ||| | | || | |||
// Variable latency ---------' ||| | | || | |||
// Latency Counter (4 cycles) -----------''' | | || | |||
// ram_wait_i is active-high ---------------' | || | |||
// ram_wait_i asserted during delay ---------------' || | |||
// Default Drive Strength (1/2) ------------------------'' | |||
// Burst wraps within burst length ------------------------' |||
// Burst length is 4 words -----------------------------'''
module ramcon(
input reset_i,
input clk2x_i,
output [22:0] ram_adr_o,
inout [15:0] ram_dq_io,
output ram_ce_on,
output ram_adv_on,
output ram_oe_on,
output ram_we_on,
output ram_ub_on,
output ram_lb_on,
output ram_cre_o,
output ram_clk_o,
input ram_wait_i,
output wb_ack_o,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [23:1] wb_adr_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
input wb_we_i,
output reset_o
);
wire ram_en_q;
wire ram_adv_o, ram_ce_o, ram_oe_o, ram_we_o, ram_be_valid;
wire dato_dq, dq_dati;
wire nt0, nt1, nt2, nt3, nt4, nt5;
reg t0, t1, t2, t3, t4, t5;
reg cfg;
wire cfg_o, adr_bcrcfg, clk_en;
// PSRAM power-on timing. Do not let the dogs out until
// the PSRAM chip has gone through its boot-up sequence.
// Wait 150us minimum, and to be conservative, a little
// extra. I've arbitrarily selected 32ms, assuming 50MHz
// input on clk2x_i.
reg [14:0] resetCounter;
always @(posedge clk2x_i) begin
if(reset_i) begin
resetCounter <= 0;
end
else begin
if(resetCounter[14]) begin
resetCounter <= resetCounter;
end
else begin
resetCounter <= resetCounter + 1;
end
end
end
wire reset_sans_cfg = ~resetCounter[14];
assign reset_o = reset_sans_cfg | cfg;
// Bus bridge random logic.
reg [15:0] wb_dat_or;
assign ram_adr_o = adr_bcrcfg ? `BCR_ADDR : wb_adr_i;
assign wb_dat_o = wb_dat_or;
always @(negedge clk2x_i) begin
if(dato_dq) wb_dat_or <= ram_dq_io;
end
assign ram_dq_io = dq_dati ? wb_dat_i : 16'hzzzz;
assign ram_clk_o = ~clk2x_i & clk_en;
// Bus bridge state Machine.
kseq ks(
.t5(t5),
.t4(t4),
.t3(t3),
.t2(t2),
.t1(t1),
.wb_we_i(wb_we_i),
.t0(t0),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.reset_i(reset_sans_cfg),
.wb_ack_o(wb_ack_o),
.dato_dq(dato_dq),
.dq_dati(dq_dati),
.ram_oe_o(ram_oe_o),
.ram_we_o(ram_we_o),
.ram_ce_o(ram_ce_o),
.ram_adv_o(ram_adv_o),
.ram_be_valid(ram_be_valid),
.nt5(nt5),
.nt4(nt4),
.nt3(nt3),
.nt2(nt2),
.nt1(nt1),
.nt0(nt0),
.adr_bcrcfg(adr_bcrcfg),
.ram_cre_o(ram_cre_o),
.cfg_o(cfg_o),
.cfg(cfg),
.clk_en(clk_en),
.ram_wait_i(ram_wait_i)
);
assign ram_adv_on = reset_sans_cfg | ~ram_adv_o;
assign ram_ce_on = reset_sans_cfg | ~ram_ce_o;
assign ram_oe_on = reset_sans_cfg | ~ram_oe_o;
assign ram_we_on = reset_sans_cfg | ~ram_we_o;
assign ram_ub_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[1]);
assign ram_lb_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[0]);
always @(posedge clk2x_i) begin
t0 <= nt0;
t1 <= nt1;
t2 <= nt2;
t3 <= nt3;
t4 <= nt4;
t5 <= nt5;
cfg <= cfg_o;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = 2 * acos(0); const int oo = 2e9; const int N = 205; const int AL = 26; vector<int> idx[AL]; vector<int> adj[N]; int clr[N]; bool dfs(int u, int c = 0); int main() { int n; scanf( %d , &(n)); string s(n, ); for (int i = 0; i < n; i++) scanf( %c , &s[i]); memset(clr, -1, sizeof(clr)); for (int i = 0; i < n; i++) { int x = s[i] - a ; for (int c = x + 1; c < AL; c++) { for (auto& j : idx[c]) { adj[i].push_back(j); adj[j].push_back(i); } } idx[x].push_back(i); } bool valid = true; for (int i = 0; i < n; i++) { if (clr[i] == -1) valid &= dfs(i); } if (valid) { puts( YES ); for (int i = 0; i < n; i++) { printf( %d , clr[i]); } printf( n ); } else printf( NO n ); return 0; } bool dfs(int u, int c) { clr[u] = c; bool ret = true; for (auto& v : adj[u]) { if (clr[v] == -1) ret &= dfs(v, !c); else if (c == clr[v]) return false; } return ret; }
|
#include <bits/stdc++.h> using namespace std; uint64_t rnd_data = 0xDEADBEEFDULL; inline void my_srand(int seed) { rnd_data = ((uint64_t)seed << 16) | 0x330E; } inline int my_rand() { rnd_data = rnd_data * 0x5DEECE66DULL + 0xB; return (rnd_data >> 17) & 0x7FFFFFFF; } template <typename T> void my_random_shuffle(T b, T e) { for (int i = (1); i <= (int)((int)(e - b) - 1); i++) { swap(b[i], b[my_rand() % (i + 1)]); } } template <class _T> inline _T sqr(const _T &x) { return x * x; } template <typename type_t, typename less_t = std::less<type_t>> inline bool uin(type_t &a, const type_t &b, const less_t &ls = less_t()) { return ls(b, a) ? a = b, true : false; } template <typename type_t, typename less_t = std::less<type_t>> inline bool uax(type_t &a, const type_t &b, const less_t &ls = less_t()) { return ls(a, b) ? a = b, true : false; } const long double PI = 3.1415926535897932384626433832795L; const long double EPS = 1e-9; const int MAXN = 202400; const size_t LIM = 300; int n; long double p[MAXN]; vector<int> a[MAXN]; vector<int> al[MAXN]; vector<int> ah[MAXN]; long double s[MAXN]; long double sh[MAXN]; bool hv[MAXN]; void precalc() { for (int i = 0; i < (int)(n); i++) { s[i] = 0.0; for (int vn : al[i]) { s[i] += p[vn]; } } } int main() { scanf( %d , &n); for (int i = 0; i < (int)(n); i++) { double x; scanf( %lf , &x); p[i] = x; } for (int i = 0; i < (int)(n - 1); i++) { int x, y; scanf( %d%d , &x, &y); a[x].push_back(y); a[y].push_back(x); } for (int i = 0; i < (int)(n); i++) { hv[i] = a[i].size() > LIM; sh[i] = 0.0; } for (int i = 0; i < (int)(n); i++) { for (int vn : a[i]) { if (hv[vn]) { ah[i].push_back(vn); } else { al[i].push_back(vn); } } } precalc(); for (int i = 0; i < (int)(n); i++) { if (hv[i]) { for (auto vn : a[i]) { sh[i] += 1.0 - p[vn]; } } } int m; scanf( %d , &m); long double spall = 0.0; for (int i = 0; i < (int)(n); i++) { spall += p[i]; } long double sumprev = 0.0; for (int j = 0; j < (int)(n); j++) { sumprev += a[j].size() * p[j]; sumprev += (1.0 - p[j]) * s[j]; sumprev += p[j] * sh[j]; } for (int i = 0; i < (int)(m); i++) { int x; double y; scanf( %d%lf , &x, &y); spall -= p[x]; sumprev -= a[x].size() * p[x] + (1.0 - p[x]) * s[x] + p[x] * sh[x]; if (!hv[x]) { for (int vn : a[x]) { sumprev -= (1.0 - p[vn]) * s[vn]; s[vn] -= p[x]; } } for (auto vn : ah[x]) { sumprev -= p[vn] * sh[vn]; sh[vn] -= 1.0 - p[x]; } p[x] = y; for (auto vn : ah[x]) { sh[vn] += 1.0 - p[x]; sumprev += p[vn] * sh[vn]; } if (!hv[x]) { for (int vn : a[x]) { s[vn] += p[x]; sumprev += (1.0 - p[vn]) * s[vn]; } } spall += p[x]; sumprev += a[x].size() * p[x] + (1.0 - p[x]) * s[x] + p[x] * sh[x]; long double ans = 2.0 + sumprev; ans -= spall * 2.0; ans /= 2.0; printf( %0.9f n , (double)ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e18 + 7; int n, m; map<char, int> ch_num; int main() { int n; cin >> n; vector<string> ee(n); for (int i = 0; i < n; i++) { cin >> ee[i]; } vector<int> can_zero(27, -1); vector<pair<int, int> > let_sum(27); for (int i = 0; i < 26; i++) { let_sum[i] = make_pair(0, i); } for (auto cp : ee) { for (int i = 0; i < (int)cp.size(); i++) { if (i == 0) { can_zero[cp[i] - a ] = 0; } else if (can_zero[cp[i] - a ] != 0) { can_zero[cp[i] - a ] = 1; } let_sum[cp[i] - a ].first += pow(10, (int)cp.size() - i - 1); } } sort(let_sum.begin(), let_sum.end()); reverse(let_sum.begin(), let_sum.end()); bool z_used = false; int cur_n = 1; for (auto cp : let_sum) { if (can_zero[cp.second] == -1) { break; } if (can_zero[cp.second] && !z_used) { ch_num[(char)( a + cp.second)] = 0; z_used = true; } else { ch_num[(char)( a + cp.second)] = cur_n; cur_n++; } } int ans = 0; for (auto hui : ee) { for (int i = 0; i < (int)hui.size(); i++) { ans += ch_num[hui[i]] * pow(10, (int)hui.size() - i - 1); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8; int n, t, h, s; char road[500001]; int H[500001], S[500001]; bool time(int k) { vector<pair<int, int> > step; step.push_back(make_pair(-1, -1)); for (int i = 0, j = 0; i < h; i++) { if (k) { k--; step.push_back(make_pair(H[i], H[i])); } else if (H[i] > S[j]) { step.push_back(make_pair(H[i], H[i])); j++; } else { int l = (int)(step.size()) - 1; if (H[i] < step[l].second) step[l].second = S[j]; else step.push_back(make_pair(H[i], S[j])); j++; } } int tt = 0; for (int i = 1; i < (int)(step.size()); i++) { tt += (step[i].second - step[i - 1].first) + (step[i].second - step[i].first); } tt = min(tt, (n * 2) - 1); return tt <= t; } int main() { scanf( %d %d n , &n, &t); scanf( %s n , road); h = 0, s = 0; for (int i = 0; i < n; i++) { if (road[i] == H ) H[h++] = i; if (road[i] == S ) S[s++] = i; } if (H[h - 1] >= t) { cout << -1 << endl; return 0; } int r = max(h - s, 0), e = h; while (r < e) { int mi = (r + e) >> 1; (time(mi)) ? e = mi : r = mi + 1; } cout << e << endl; return 0; }
|
`default_nettype none
module memory_pipe_arbiter(
input wire iCLOCK,
input wire inRESET,
//Data(Core -> Memory)
input wire iDATA_REQ,
output wire oDATA_LOCK,
input wire [1:0] iDATA_ORDER,
input wire [3:0] iDATA_MASK,
input wire iDATA_RW,
input wire [13:0] iDATA_ASID,
input wire [1:0] iDATA_MMUMOD,
input wire [2:0] iDATA_MMUPS,
input wire [31:0] iDATA_PDT,
input wire [31:0] iDATA_ADDR,
input wire [31:0] iDATA_DATA,
//Data(Memory -> Core)
output wire oDATA_REQ,
input wire iDATA_BUSY,
output wire [63:0] oDATA_DATA,
output wire [23:0] oDATA_MMU_FLAGS,
//Inst(Core -> Memory)
input wire iINST_REQ,
output wire oINST_LOCK,
input wire [1:0] iINST_MMUMOD,
input wire [2:0] iINST_MMUPS,
input wire [31:0] iINST_PDT,
input wire [13:0] iINST_ASID,
input wire [31:0] iINST_ADDR,
//Inst(Memory -> Core)
output wire oINST_REQ,
input wire iINST_BUSY,
output wire [63:0] oINST_DATA,
output wire [23:0] oINST_MMU_FLAGS,
//Memory(OutPort)
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire oMEMORY_DATA_STORE_ACK, //1:Data Access && Store(MMUFlag read only. Not Memory access.)
output wire [1:0] oMEMORY_MMU_MODE,
output wire [2:0] oMEMORY_MMU_PS,
output wire [31:0] oMEMORY_PDT,
output wire [13:0] oMEMORY_ASID,
output wire [1:0] oMEMORY_ORDER,
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW,
output wire [31:0] oMEMORY_ADDR,
output wire [31:0] oMEMORY_DATA,
//Memory(InPort)
input wire iMEMORY_VALID,
output wire oMEMORY_BUSY,
input wire iMEMORY_STORE_ACK,
input wire [63:0] iMEMORY_DATA,
input wire [23:0] iMEMORY_MMU_FLAGS
);
/*********************************************************
Wire and Register
*********************************************************/
//Matching Bridge
wire matching_bridfe_wr_full;
wire matching_bridge_rd_valid;
wire matching_bridge_rd_type;
//Core -> Memory
wire mem2core_inst_lock;
wire mem2core_data_lock;
wire core2mem_inst_condition;
wire core2mem_data_condition;
wire core2mem_data_lock = 1'b0;
reg b_core2mem_req;
reg b_core2mem_data_store_ack;
reg [1:0] b_core2mem_order;
reg [3:0] b_core2mem_mask;
reg b_core2mem_rw;
reg [1:0] b_core2mem_mmumod;
reg [2:0] b_core2mem_mmups;
reg [31:0] b_core2mem_pdt;
reg [13:0] b_core2mem_asid;
reg [31:0] b_core2mem_addr;
reg [31:0] b_core2mem_data;
//Memory -> Core
reg b_mem2core_inst_valid;
reg [63:0] b_mem2core_inst_data;
reg [23:0] b_mem2core_inst_mmu_flags;
reg b_mem2core_data_valid;
reg [63:0] b_mem2core_data_data;
reg [23:0] b_mem2core_data_mmu_flags;
//Condition
wire mem2core_common_lock = matching_bridfe_wr_full || iMEMORY_LOCK;
wire core2mem_data_write_ack_condition = iDATA_RW && core2mem_data_condition;
wire core2mem_normal_memory_access_condition = (!iDATA_RW && core2mem_data_condition) || core2mem_inst_condition;
/*********************************************************
Memory Matching Controal
*********************************************************/
mist1032isa_arbiter_matching_queue #(16, 4, 1) MEM_MATCHING_BRIDGE( //Queue deep : 16, Queue deep_n : 4, Flag_n : 1
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(1'b0),
//Write
.iWR_REQ(!mem2core_common_lock && core2mem_normal_memory_access_condition),
.iWR_FLAG(core2mem_data_condition), //0:Inst, 1:Data
.oWR_FULL(matching_bridfe_wr_full),
//Read
.iRD_REQ(iMEMORY_VALID && (matching_bridge_rd_type && !core2mem_data_lock || !matching_bridge_rd_type && !iINST_BUSY) && !iMEMORY_STORE_ACK),
.oRD_VALID(matching_bridge_rd_valid),
.oRD_FLAG(matching_bridge_rd_type), //0:Inst, 1:Data
.oRD_EMPTY()
);
/*********************************************************
Buffer & Assign(Core -> Memory)
*********************************************************/
//assign
assign mem2core_inst_lock = mem2core_common_lock || core2mem_data_condition;
assign mem2core_data_lock = mem2core_common_lock || core2mem_inst_condition;
assign core2mem_inst_condition = !iDATA_REQ && iINST_REQ;
assign core2mem_data_condition = iDATA_REQ;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_core2mem_req <= 1'b0;
b_core2mem_order <= 2'h0;
b_core2mem_mask <= 4'h0;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= 2'h0;
b_core2mem_mmups <= 3'h0;
b_core2mem_pdt <= {32{1'b0}};
b_core2mem_asid <= 14'h0;
b_core2mem_addr <= {32{1'b0}};
b_core2mem_data <= {32{1'b0}};
end
else begin
if(!mem2core_common_lock)begin
//if(b_io_startaddr_valid )
if(core2mem_data_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= iDATA_ORDER;
b_core2mem_mask <= iDATA_MASK;
b_core2mem_rw <= iDATA_RW;
b_core2mem_data_store_ack <= core2mem_data_write_ack_condition;
b_core2mem_mmumod <= iDATA_MMUMOD;
b_core2mem_mmups <= iDATA_MMUPS;
b_core2mem_pdt <= iDATA_PDT;
b_core2mem_asid <= iDATA_ASID;
b_core2mem_addr <= iDATA_ADDR;
b_core2mem_data <= iDATA_DATA;
end
else if(core2mem_inst_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= 2'h2;
b_core2mem_mask <= 4'hf;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= iINST_MMUMOD;
b_core2mem_mmups <= iINST_MMUPS;
b_core2mem_pdt <= iINST_PDT;
b_core2mem_asid <= iINST_ASID;
b_core2mem_addr <= iINST_ADDR;
b_core2mem_data <= {32{1'b0}};
end
else begin
b_core2mem_req <= 1'b0;
end
end
end
end
/*********************************************************
Inst Data Selector & Buffer & assign (Memory -> Core)
*********************************************************/
//Inst
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_inst_valid <= 1'b0;
b_mem2core_inst_data <= {63{1'b0}};
b_mem2core_inst_mmu_flags <= 24'h0;
end
else begin
if(!iINST_BUSY)begin
b_mem2core_inst_valid <= !matching_bridge_rd_type && matching_bridge_rd_valid && !iMEMORY_STORE_ACK && iMEMORY_VALID;
b_mem2core_inst_data <= iMEMORY_DATA;
b_mem2core_inst_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
//Data
assign core2mem_data_lock = 1'b0;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_data_valid <= 1'b0;
b_mem2core_data_data <= {63{1'b0}};
b_mem2core_data_mmu_flags <= 24'h0;
end
else begin
if(!core2mem_data_lock)begin
b_mem2core_data_valid <= ((matching_bridge_rd_type && matching_bridge_rd_valid) || iMEMORY_STORE_ACK) && iMEMORY_VALID;
b_mem2core_data_data <= iMEMORY_DATA;
b_mem2core_data_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
/*********************************************************
Assign
*********************************************************/
assign oDATA_LOCK = mem2core_data_lock;
assign oINST_LOCK = mem2core_inst_lock;
assign oMEMORY_REQ = b_core2mem_req;
assign oMEMORY_DATA_STORE_ACK = b_core2mem_data_store_ack;
assign oMEMORY_MMU_MODE = b_core2mem_mmumod;
assign oMEMORY_MMU_PS = b_core2mem_mmups;
assign oMEMORY_PDT = b_core2mem_pdt;
assign oMEMORY_ASID = b_core2mem_asid;
assign oMEMORY_ORDER = b_core2mem_order;
assign oMEMORY_MASK = b_core2mem_mask;
assign oMEMORY_RW = b_core2mem_rw;
assign oMEMORY_ADDR = b_core2mem_addr;
assign oMEMORY_DATA = b_core2mem_data;
assign oMEMORY_BUSY = iDATA_BUSY || iINST_BUSY;
assign oDATA_REQ = b_mem2core_data_valid && !core2mem_data_lock;
assign oDATA_DATA = b_mem2core_data_data;
assign oDATA_MMU_FLAGS = b_mem2core_data_mmu_flags;
assign oINST_REQ = b_mem2core_inst_valid && !iINST_BUSY;
assign oINST_DATA = b_mem2core_inst_data;
assign oINST_MMU_FLAGS = b_mem2core_inst_mmu_flags;
endmodule
`default_nettype wire
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#include <bits/stdc++.h> using namespace std; long long a[11111111]; long long b[11111111]; int len = 0; long long gcd(long long a, long long b) { return a == 0 ? b : gcd(b % a, a); } int counter(int x) { int res = 0; while (x) { res++; x /= 10; } return res; } void printK(int x, int k) { int n = counter(x); n = n - k + 1; for (int i = 0; i < n - 1; i++) x /= 10; cout << x % 10 << n ; } long long g(long long x) { long long res = 0; int len = 1; long long tmp = 9; while (x > tmp) { res += tmp * len; x -= tmp; tmp *= 10; len++; } res += x * len; return res; } long long f(long long x) { long long res = 0; long long tmp = 0; while (x >= 0) { res += (1 + x) * x / 2; if (tmp == 0) tmp = 9; else tmp = tmp * 10; x -= tmp; } return res; } int main() { long long q, k; cin >> q; for (int i = 0; i < q; i++) { cin >> k; long long m, l = 0, r = 2000000001; while (l < r - 1) { m = (l + r) >> 1; if (f(m) < k) { l = m; } else { r = m; } } k -= f(l); r = l + 2, l = 0; while (l < r - 1) { m = (l + r) >> 1; if (g(m) < k) { l = m; } else { r = m; } } k -= g(l); long long n = 0; long long L = l + 1; l++; while (L) { L /= 10; n++; } n = n - k + 1; for (int j = 0; j < n - 1; j++) l /= 10; cout << l % 10 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct cube { int ind, val, h; }; int rcount[101]; int compare1(cube a, cube b) { return a.val < b.val; } int compare2(cube a, cube b) { return a.ind < b.ind; } int main() { int n; scanf( %d , &n); vector<cube> v; vector<int> one, two; for (int i = 0; i < n * 2; i++) { cube c; c.ind = i; c.h = 0; scanf( %d , &c.val); v.push_back(c); } sort(v.begin(), v.end(), compare1); int size1 = 0, size2 = 0, color = 1, repeat = 0, repeatcount = 0; for (int i = 0; i < n * 2; i++) { v[i].h = 0; if (repeatcount >= 2 && repeat == v[i].val) rcount[v[i].val]++; else { if (repeat == v[i].val) repeatcount++; else repeatcount = 1; repeat = v[i].val; color *= -1; v[i].h = color; if (color < 0) size1++; else size2++; } } printf( %d n , size1 * size2); sort(v.begin(), v.end(), compare2); for (int i = 0; i < n * 2; i++) { if (v[i].h == 0) { if (size1 > size2) { v[i].h = 1; size2++; } else { v[i].h = -1; size1++; } } printf( %d , (v[i].h < 0) ? 1 : 2); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int vis[maxn], son[maxn], f[maxn], sum, root, ans[maxn]; vector<int> g[maxn]; void getroot(int x, int fa) { son[x] = 1; f[x] = 0; for (int i = 0; i < g[x].size(); i++) { int v = g[x][i]; if (v == fa || vis[v]) continue; getroot(v, x); son[x] += son[v]; f[x] = max(f[x], son[v]); } f[x] = max(f[x], sum - son[x]); if (f[x] < f[root]) root = x; } void work(int x, int fa, int dep) { ans[x] = dep; vis[x] = 1; for (int i = 0; i < g[x].size(); i++) { int v = g[x][i]; if (vis[v]) continue; sum = son[v], root = 0; getroot(v, x); work(root, x, dep + 1); } } int main(void) { int n; while (~scanf( %d , &n) && n) { for (int i = 1; i <= n; i++) g[i].clear(); int a, b; for (int i = 0; i < n - 1; i++) { scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } f[0] = sum = n; getroot(1, 0); work(root, 0, 0); for (int i = 1; i <= n; i++) { printf( %c , ans[i] + A ); } printf( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int vis[200010]; int addnum, vel[400010], head[400010], ne[400010]; int fath[200010][21]; int fa[200010], dep[200010]; pair<int, int> s[200010]; int tot, n, m; vector<int> o, o1, o2; int id[11]; int d[200010], f[200010][2]; int num; int p[200010]; inline int read() { int ans = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) ans = (ans << 1) + (ans << 3) + ch - 0 , ch = getchar(); return ans; } inline int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } void dfs(int u, int fa) { vis[u] = 1; for (int e = head[u]; e; e = ne[e]) { int v = vel[e]; if (v == fa) continue; fath[v][0] = u; dep[v] = dep[u] + 1; dfs(v, u); } } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); int dt = dep[x] - dep[y]; for (int i = 19; i >= 0; i--) if (dt >> i & 1) x = fath[x][i]; for (int i = 19; i >= 0; i--) if (fath[x][i] != fath[y][i]) x = fath[x][i], y = fath[y][i]; if (x == y) return x; return fath[x][0]; } void calc(int num) { int x = s[num].first, y = s[num].second; int dt = lca(x, y); o1.clear(), o2.clear(); while (x != dt) o1.push_back(x), x = fath[x][0]; o1.push_back(dt); while (y != dt) o2.push_back(y), y = fath[y][0]; while (o1.size()) o2.push_back(o1.back()), o1.pop_back(); o.clear(); int pos = 0, cnt = o2.size(); for (int i = 0; i < cnt; i++) if (p[o2[i]] == 1 && !p[o2[(i + 1) % cnt]]) { pos = i; break; } o.push_back(id[0] == o2[pos] ? id[0] : id[1]); for (int i = pos + 1; i < cnt + pos; i++) if (p[o2[i % cnt]]) break; else o.push_back(o2[i % cnt]); o.push_back(id[0] == o2[pos] ? id[1] : id[0]); printf( %d , (int)o.size()); if (o.back() != id[0]) reverse(o.begin(), o.end()); while (o.size()) { int u = o.back(); o.pop_back(); printf( %d%c , u, !o.size() ? n : ); } } void add(int u, int v) { addnum++, vel[addnum] = v, ne[addnum] = head[u], head[u] = addnum; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) { int x = read(), y = read(); if (find(x) != find(y)) fa[find(x)] = find(y), add(x, y), add(y, x); else s[++tot] = make_pair(x, y); } for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i, -1); for (int i = 1; i < 20; i++) for (int j = 1; j <= n; j++) fath[j][i] = fath[fath[j][i - 1]][i - 1]; for (int i = 1; i <= tot; i++) { int x = s[i].first, y = s[i].second; while (x != y) { if (dep[x] < dep[y]) swap(x, y); if (!d[x]) d[x] = i; else { num = d[x]; break; } x = fath[x][0]; } if (num) { printf( YES n ); x = s[i].first, y = s[i].second; while (x != y) { if (dep[x] < dep[y]) swap(x, y); f[x][0] = 1; x = fath[x][0]; } x = s[num].first, y = s[num].second; while (x != y) { if (dep[x] < dep[y]) swap(x, y); f[x][1] = 1; x = fath[x][0]; } for (int i = 1; i <= n; i++) if (f[i][0] && f[i][1]) p[fath[i][0]]++, p[i]++; int cnt = 0; for (int i = 1; i <= n; i++) if (p[i] == 1) id[cnt++] = i; x = id[0]; y = id[1]; while (p[x]) o1.push_back(x), x = fath[x][0]; while (p[y]) o2.push_back(y), y = fath[y][0]; printf( %d , (int)(o1.size() + o2.size() - 1)); for (int i = 0; i < (int)o1.size() - 1; i++) printf( %d , o1[i]); while (o2.size()) { int u = o2.back(); o2.pop_back(); printf( %d%c , u, !o2.size() ? n : ); } calc(i), calc(num); return 0; } } printf( NO n ); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:45:00 05/22/2016
// Design Name: RICPU
// Module Name: Y:/TEOCOA/EXPR9/TESTRICPU.v
// Project Name: EXPR9
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: RICPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TESTRICPU;
// Inputs
reg clk;
reg clk_ram;
reg rst;
// Outputs
wire [31:0] ALU_F;
wire FR_ZF;
wire FR_OF;
wire [31:0] A, B;
wire [31:0] Mem_R_Data;
wire [6:0] MW;
// Instantiate the Unit Under Test (UUT)
RICPU uut (
.clk(clk),
.clk_ram(clk_ram),
.rst(rst),
.ALU_F(ALU_F),
.FR_ZF(FR_ZF),
.FR_OF(FR_OF),
.A(A),
.B(B),
.MW(MW),
.Mem_R_Data(Mem_R_Data)
);
always #4 clk = ~clk;
always #1 clk_ram = ~clk_ram;
initial begin
// Initialize Inputs
clk = 0;
clk_ram = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#4;
rst = 1;
#4;
rst = 0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 100 * 1000 + 10; vector<int> u[N], v[N], v2[N]; vector<pair<int, int> > q[N]; int t, st[N], fi[N], di[N], g[N], par[N]; int root(int u) { return (par[u] == u) ? u : par[u] = root(par[u]); } void merge1(int x, int y) { int dx = root(x), dy = root(y); if (dx == dy) return; par[dy] = dx; } bool mark[N], ans[N]; void dfs(int u) { mark[u] = true; st[u] = t++; for (int i = 0; i < v[u].size(); i++) { if (!mark[v[u][i]]) dfs(v[u][i]); } fi[u] = t++; } int main() { int n, m, p = 1, j = 1; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b, c; cin >> a; u[i].push_back(a); if (a == 1) { cin >> b >> c; u[i].push_back(b); u[i].push_back(c); v[c].push_back(b); di[b]++; } if (a == 2) { cin >> b; u[i].push_back(b); u[i].push_back(p); p++; } if (a == 3) { cin >> b >> c; u[i].push_back(b); u[i].push_back(c); q[c].push_back({b, j++}); } } for (int i = 1; i <= n; i++) par[i] = i; for (int i = 1; i <= n; i++) { if (di[i] == 0) dfs(i); } for (int i = 1; i <= n; i++) { } for (int i = 0; i < m; i++) { int a = u[i][0], b = u[i][1], c = u[i][2]; if (u[i][0] == 1) merge1(b, c); if (u[i][0] == 2) { for (int i = 0; i < q[c].size(); i++) { int qu = q[c][i].first, kj = q[c][i].second; if (st[qu] <= st[b] && fi[qu] >= fi[b] && root(qu) == root(b)) ans[kj] = true; else ans[kj] = false; } } } for (int i = 1; i < j; i++) { if (ans[i]) cout << YES << endl; else cout << NO << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; int m; cin >> n >> m; int l; int r; int arr[n]; int pos = 0; int neg = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] == -1) { neg++; } else { pos++; } } int mn = min(neg, pos); for (int i = 0; i < m; i++) { cin >> l >> r; int c = 0; if (l == r) { cout << 0 << endl; c++; } if (c == 0) { if ((abs(l - r) + 1) / 2 <= mn && (abs(l - r) + 1) % 2 == 0) { cout << 1 << endl; } else { cout << 0 << endl; } } } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int m = 1e9 + 7; int bin_pow(int x, int k) { if (k == 0) return 1; int g = bin_pow(x, k / 2); g = (1ll * g * g) % m; if (k % 2 > 0) g = (1ll * g * x) % m; return g; } signed main() { iostream::sync_with_stdio(0); cin.tie(0); setlocale(LC_ALL, Russian ); int tt, n, p, i, j, r, second, ans, add; vector<int> read, k, cnt, st; cin >> tt; for (; tt > 0; tt--) { cin >> n >> p; read.assign(n, 0); k.clear(); cnt.clear(); st.clear(); for (i = 0; i < n; i++) cin >> read[i]; if (p == 1) { if (n % 2 > 0) cout << 1 n ; else cout << 0 n ; continue; } sort(read.begin(), read.end()); for (i = 0; i < n; i++) { j = i + 1; while (j < n && read[i] == read[j]) j++; k.push_back(read[i]); cnt.push_back(j - i); i = j - 1; } st.push_back(bin_pow(p, k[0])); for (i = 1; i < k.size(); i++) st.push_back((1ll * st[i - 1] * bin_pow(p, k[i] - k[i - 1])) % m); ans = 0; for (i = k.size() - 1; i >= 0; i--) { if (cnt[i] % 2 == 0) continue; j = i - 1; second = 1; while (j >= 0) { for (r = 0; r < k[j + 1] - k[j] && second <= n; r++) second *= p; if (r < k[j + 1] - k[j] || second > n) break; add = min(second, cnt[j]); second -= add; ans = (ans - 1ll * cnt[j] * st[j] + 2ll * m * m) % m; cnt[j] -= add; if (second == 0) break; j--; } if (second > 0) { while (j >= 0) { ans = (ans - 1ll * cnt[j] * st[j] + 2ll * m * m) % m; j--; } ans = (ans + st[i]) % m; break; } ans = 0; i = j + 1; } cout << ans << n ; } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1000000000; const int MOD = 1073741824; const int M = INF; const double RRR = 180.0 / PI; vector<vector<pair<int, int> > > g; vector<int> used; void dfs(int v, int l, int r) { used[v] = 1; for (int i = 0; i < g[v].size(); i++) { if (g[v][i].second >= l && g[v][i].second <= r) { continue; } int to = g[v][i].first; if (!used[to]) { dfs(to, l, r); } } } int main() { double TIME_START = clock(); int n, m; cin >> n >> m; used.resize(n); g.resize(n); int a, b; for (int i = 0; i < m; i++) { cin >> a >> b; a--; b--; g[a].push_back(make_pair(b, i)); g[b].push_back(make_pair(a, i)); } int k; cin >> k; int l, r; for (int i = 0; i < k; i++) { cin >> l >> r; l--; r--; int col = 0; used.assign(n, 0); for (int i = 0; i < n; i++) { if (!used[i]) { col++; dfs(i, l, r); } } cout << col << endl; } fprintf(stderr, n n%.15lf n n , (double)(clock() - TIME_START) / CLOCKS_PER_SEC); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dac vdma read
module ad_axis_dma_tx (
// vdma interface
dma_clk,
dma_rst,
dma_fs,
dma_valid,
dma_data,
dma_ready,
dma_ovf,
dma_unf,
// dac interface
dac_clk,
dac_rst,
dac_rd,
dac_valid,
dac_data,
// processor interface
dma_frmcnt);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam RDY_THRESHOLD_LO = 6'd40;
localparam RDY_THRESHOLD_HI = 6'd50;
// vdma interface
input dma_clk;
input dma_rst;
output dma_fs;
input dma_valid;
input [DW:0] dma_data;
output dma_ready;
output dma_ovf;
output dma_unf;
// dac interface
input dac_clk;
input dac_rst;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// processor interface
input [31:0] dma_frmcnt;
// internal registers
reg dac_start_m1 = 'd0;
reg dac_start = 'd0;
reg dac_resync_m1 = 'd0;
reg dac_resync = 'd0;
reg [ 5:0] dac_raddr = 'd0;
reg [ 5:0] dac_raddr_g = 'd0;
reg dac_rd_d = 'd0;
reg dac_rd_2d = 'd0;
reg dac_valid = 'd0;
reg [DW:0] dac_data = 'd0;
reg [31:0] dma_clkcnt = 'd0;
reg dma_fs = 'd0;
reg [ 5:0] dma_raddr_g_m1 = 'd0;
reg [ 5:0] dma_raddr_g_m2 = 'd0;
reg [ 5:0] dma_raddr = 'd0;
reg [ 5:0] dma_addr_diff = 'd0;
reg dma_ready = 'd0;
reg dma_almost_full = 'd0;
reg dma_almost_empty = 'd0;
reg dma_ovf = 'd0;
reg dma_unf = 'd0;
reg dma_resync = 'd0;
reg dma_start = 'd0;
reg dma_wr = 'd0;
reg [ 5:0] dma_waddr = 'd0;
reg [DW:0] dma_wdata = 'd0;
// internal signals
wire dma_wr_s;
wire [ 6:0] dma_addr_diff_s;
wire dma_ovf_s;
wire dma_unf_s;
wire [DW:0] dac_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dac read interface
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_start_m1 <= 'd0;
dac_start <= 'd0;
dac_resync_m1 <= 'd0;
dac_resync <= 'd0;
end else begin
dac_start_m1 <= dma_start;
dac_start <= dac_start_m1;
dac_resync_m1 <= dma_resync;
dac_resync <= dac_resync_m1;
end
if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
dac_raddr <= 6'd0;
end else if (dac_rd == 1'b1) begin
dac_raddr <= dac_raddr + 1'b1;
end
dac_raddr_g <= b2g(dac_raddr);
dac_rd_d <= dac_rd;
dac_rd_2d <= dac_rd_d;
dac_valid <= dac_rd_2d;
dac_data <= dac_rdata_s;
end
// generate fsync
always @(posedge dma_clk) begin
if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin
dma_clkcnt <= 16'd0;
end else begin
dma_clkcnt <= dma_clkcnt + 1'b1;
end
if (dma_clkcnt == 32'd1) begin
dma_fs <= 1'b1;
end else begin
dma_fs <= 1'b0;
end
end
// overflow or underflow status
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_raddr_g_m1 <= 'd0;
dma_raddr_g_m2 <= 'd0;
end else begin
dma_raddr_g_m1 <= dac_raddr_g;
dma_raddr_g_m2 <= dma_raddr_g_m1;
end
dma_raddr <= g2b(dma_raddr_g_m2);
dma_addr_diff <= dma_addr_diff_s[5:0];
if (dma_addr_diff >= RDY_THRESHOLD_HI) begin
dma_ready <= 1'b0;
end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin
dma_ready <= 1'b1;
end
if (dma_addr_diff > BUF_THRESHOLD_HI) begin
dma_almost_full <= 1'b1;
end else begin
dma_almost_full <= 1'b0;
end
if (dma_addr_diff < BUF_THRESHOLD_LO) begin
dma_almost_empty <= 1'b1;
end else begin
dma_almost_empty <= 1'b0;
end
dma_ovf <= dma_ovf_s;
dma_unf <= dma_unf_s;
dma_resync <= dma_ovf | dma_unf;
end
// vdma write
assign dma_wr_s = dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start <= 1'b0;
end else if (dma_wr_s == 1'b1) begin
dma_start <= 1'b1;
end
dma_wr <= dma_wr_s;
if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
dma_waddr <= 6'd0;
end else if (dma_wr == 1'b1) begin
dma_waddr <= dma_waddr + 1'b1;
end
dma_wdata <= dma_data;
end
// memory
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
.clka (dma_clk),
.wea (dma_wr),
.addra (dma_waddr),
.dina (dma_wdata),
.clkb (dac_clk),
.addrb (dac_raddr),
.doutb (dac_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int N, M; int timew, cnt; stack<int> si; int low[2000005], dep[2000005], siz[2000005], dfn[2000005], nex[2000005], las[2000005], Arrive[2000005], st[2000005], cnt1; bool isin[2000005]; void jt(int xx, int yy) { cnt++; nex[cnt] = las[xx]; las[xx] = cnt; Arrive[cnt] = yy; } void tarjan(int noww) { timew++; low[noww] = dfn[noww] = timew; si.push(noww); isin[noww] = true; for (int i = las[noww]; i; i = nex[i]) { if (!dfn[Arrive[i]]) { tarjan(Arrive[i]); low[noww] = min(low[noww], low[Arrive[i]]); } else if (isin[Arrive[i]]) low[noww] = min(low[noww], dfn[Arrive[i]]); } if (low[noww] == dfn[noww]) { cnt1++; int k = -1; while (k != noww) { k = si.top(); si.pop(); isin[k] = false; st[k] = cnt1; siz[cnt1]++; } } } void Clear() { cnt = 0; cnt1 = 0; timew = 0; for (int i = 1; i <= N; i++) las[i] = dep[i] = st[i] = siz[i] = dfn[i] = low[i] = dep[i] = 0; } int main() { int T; scanf( %d , &T); while (T--) { scanf( %d%d , &N, &M); Clear(); for (int i = 1; i <= M; i++) { int u, v; scanf( %d%d , &u, &v); if (u != v) jt(u, v); } for (int i = 1; i <= N; i++) if (!dfn[i]) tarjan(i); if (siz[st[1]] == N) { puts( No ); continue; } for (int i = 1; i <= N; i++) for (int j = las[i]; j; j = nex[j]) if (st[i] != st[Arrive[j]]) dep[st[i]]++; bool flag = false; for (int i = 1; i <= cnt1; i++) { if (!dep[i] && siz[i]) { flag = true; puts( Yes ); vector<int> ans[2]; for (int j = 1; j <= N; j++) ans[st[j] == i].push_back(j); printf( %d %d n , ans[1].size(), ans[0].size()); for (auto &i : ans[1]) printf( %d , i); cout << n ; for (auto &i : ans[0]) printf( %d , i); cout << n ; break; } } if (!flag) puts( No ); } return 0; }
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/10ps
module sdram_init (
// -- Clock & Reset
input sdram_clk,
input sdram_rst_,
// -- CKE
// input CKE_IN,
// output reg CKE_OUT,
// -- init output signals
output reg PAA = 0,
output reg SET_MODE
);
parameter
INIT_CNT = 16'h4000,
INIT_HALF_CNT = INIT_CNT >> 1;
/********************************************************/
// -- Internal Signals
reg [15:0] init_counter;
wire init_counter_done;
//wire init_counter_half_done;
assign init_counter_done = (init_counter == INIT_CNT);
//assign init_counter_half_done = (init_counter > INIT_HALF_CNT);
always @(posedge sdram_clk) begin
if (!sdram_rst_)
init_counter <= 'b0;
else if (!init_counter_done)
init_counter <= init_counter + 1'b1;
end
// -- Generate CKE_OUT
//always @(negedge sdram_clk or negedge sdram_rst_) begin
// if (!sdram_rst_)
// CKE_OUT <= 1'b0;
// else
// CKE_OUT <= CKE_IN && init_counter_half_done;
//end
// -- Generate PAA
// -- Wait at least 100us after providing stable sdram CLOCK signal
always @(posedge sdram_clk) begin
PAA <= init_counter_done;
end
// -- Generate SET_MODE
always @(posedge sdram_clk) begin
SET_MODE <= 1'b1;
end
endmodule /* module sdram_init (*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_4_V
`define SKY130_FD_SC_LS__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_4_V
|
#include <bits/stdc++.h> int main() { long long n, m; scanf( %lld %lld , &n, &m); long long res = 1, p = 2; while (m != 0) { if (m % 2 != 0) res = res * p % 1000000007; p = p * p % 1000000007; m >>= 1; } res--; p = res; res = 1; while (n != 0) { if (n % 2 != 0) res = res * p % 1000000007; p = p * p % 1000000007; n >>= 1; } printf( %lld , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18 + 1; inline long long input(void) { char t; long long x = 0; int neg = 0; t = getchar(); while ((t < 48 || t > 57) && t != - ) t = getchar(); if (t == - ) { neg = 1; t = getchar(); } while (t >= 48 && t <= 57) { x = (x << 3) + (x << 1) + t - 48; t = getchar(); } if (neg) x = -x; return x; } inline void output(long long x) { char a[20]; int i = 0, j; a[0] = 0 ; if (x < 0) { putchar( - ); x = -x; } if (x == 0) putchar( 0 ); while (x) { a[i++] = x % 10 + 48; x /= 10; } for (j = i - 1; j >= 0; j--) { putchar(a[j]); } putchar( n ); } int main() { long long n, i, a[200010], x[200010], sum, min = 1e9; n = input(); for (int i = 0; i < n; ++i) a[i] = input(); sort(a, a + n); for (int i = 0; i < n - 1; ++i) x[i] = a[i + 1] - a[i]; sum = 0; for (int i = 0; i < n / 2; ++i) sum += x[i]; min = sum; for (int i = n / 2; i < n - 1; ++i) { sum = sum + x[i] - x[i - n / 2]; if (sum < min) min = sum; } output(min); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long Max = 2e5 + 9, inf = 1e18; long long A[Max], B[Max], d[Max]; int find_nxt(long long id, long long x) { if (A[id] - B[id] >= x) return B[id] += x, id; d[id] = find_nxt(d[id], x - A[id] + B[id]), B[id] = A[id]; return d[id]; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, m, a, id, x; cin >> n; for (int i = 1; i <= n; i++) cin >> A[i], d[i] = i + 1; A[n + 1] = inf; cin >> m; while (m--) { cin >> a >> id; if (a == 1) { cin >> x; find_nxt(id, x); } else cout << B[id] << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> ve; const int MAX = 51; long long C[MAX][MAX]; void build() { for (int i = 0; i < MAX; ++i) for (int j = 0; j < MAX; ++j) C[i][j] = (j == 0) ? 1 : ((i == 0) ? 0 : C[i - 1][j - 1] + C[i - 1][j]); } double memo[MAX][MAX][MAX]; double solve(int i, int last, int mx) { if (i == m) { if (last != n) return 0; return mx; } double &ret = memo[i][last][mx]; if (ret == ret) return ret; ret = 0; for (int j = 0; j <= n - last; j++) { ret += C[n - last][j] * 1LL * solve(i + 1, last + j, max(mx, (j / ve[i]) + (j % ve[i] != 0))); } return ret; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); build(); cin >> n >> m; for (int i = 0; i < m; i++) { int x; cin >> x; ve.push_back(x); } memset(memo, -1, sizeof memo); cout << fixed << setprecision(20) << powl(1.0 / m, n) * solve(0, 0, 0) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long T, n, i, l, r, mid, res; scanf( %lld , &T); while (T--) { scanf( %lld , &n); l = 2; r = n - 1; res = n - 1; while (l <= r) { mid = (l + r) >> 1; if (mid * (mid - 1) / 2 + (n - mid) <= 2 * (n - mid)) l = mid + 1; else r = mid - 1; } res = max(res, min(l * (l - 1) / 2 + (n - l), 2 * (n - l))); res = max(res, min((l - 1) * (l - 2) / 2 + (n - l + 1), 2 * (n - l + 1))); printf( %lld n , res); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A2111OI_PP_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9+7, M = (1e9+7), MAXN = 1 * 2e5; int A[MAXN], C[MAXN]; int64_t modpow(int64_t a, int64_t b) { int64_t res = 1; for(; b; b >>= 1) { if(b&1) res=res*a%M; a=a*a%M; } return res; } void solve() { const int MOD = M; int N, M; cin >> N >> M; vector<string> G(N); for(int i = 0; i < N; i++) cin >> G[i]; int cnt = 0; for(int i = 0; i < N; i++) cnt += count(G[i].begin(), G[i].end(), # ); cerr << Count: << cnt << endl; int64_t x = modpow(2, cnt); if(cnt == N * M) { cout << (x - 1 + MOD) % MOD << endl; } else { cout << modpow(2, cnt) << endl; } } int main() { cin.tie(0)->sync_with_stdio(0); int T; cin >> T; while(T--) { solve(); } }
|
// UART transmitter.
module UART_TX(
input rst, clk, baud_edge, data_ready,
input [7:0] data,
output reg tx, data_accepted
);
localparam START = (1 << 0), DATA = (1 << 1), END = (1 << 2);
reg [7:0] data_reg;
reg [2:0] data_counter;
reg [3:0] state;
initial begin
tx <= 1;
data_accepted <= 0;
end
always @(posedge clk) begin
if(rst) begin
state <= END;
tx <= 1;
data_accepted <= 0;
end else if(baud_edge) begin
case(state)
START: begin
tx <= 0;
data_counter <= 0;
state <= DATA;
end
DATA: begin
tx <= data_reg[data_counter];
if(data_counter != 7) begin
data_counter <= data_counter + 1;
end else begin
state <= END;
data_counter <= 0;
end
end
END: begin
tx <= 1;
if(data_ready) begin
data_accepted <= 1;
data_reg <= data;
state <= START;
end
end
default: begin
tx <= 1;
state <= END;
end
endcase
end else begin
data_accepted <= 0;
end
end
endmodule
|
// Implementation of a 100% asynchronous "OR" function between
// request signals
// using arbitrer_r1_2ph
module or_r1_2ph (/*AUTOARG*/
// Outputs
a1, a2, r,
// Inputs
r1, r2, a, rstn
);
// Input ports
input r1;
output a1;
input r2;
output a2;
// output port
output r;
input a;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire r;
wire r1,r2;
wire a1,a2;
wire g1,g2;
wire d1,d2;
arbitrer_r1_2ph U_ARBITRER(
// Input ports
.r1 (r1),
.a1 (a1),
.r2 (r2),
.a2 (a2),
// Output ports
.g1 (g1),
.g2 (g2),
.d1 (d1),
.d2 (d2),
.rstn (rstn));
// Structure is similar to the call block
// replacing the xor by an or
// and also inside the decision-wait element
// If port #2 is one, then the output r
// is already one and ready (a==1)
// else we have to wait for a
mux2 U_MUX2_1(.z(d1pre),
.s(d2),
.a0(a),
.a1(g1));
mux2 U_MUX2_2(.z(d2pre),
.s(d1),
.a0(a),
.a1(g2));
//or2 U_OR2_1(.z(d1pre), .a(a), .b(d2));
//or2 U_OR2_2(.z(d2pre), .a(d1), .b(a));
// We need some memory to keep the feedback when state change
// on the other port
muller2 U_MULLER_ACK1(.a(g1),.b(d1pre),.rstn(rstn),.z(d1));
muller2 U_MULLER_ACK2(.a(g2),.b(d2pre),.rstn(rstn),.z(d2));
or2 U_OR2_OUT(.z(r), .a(g1), .b(g2));
endmodule // or_r1_2ph
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> v(n + 1); for (int i = 1; i <= n; ++i) cin >> v[i]; int x, y; scanf( %d %d , &x, &y); for (int i = 1; i <= n; ++i) { int a = 0, b = 0; for (int j = 1; j <= n; ++j) { if (j < i) a += v[j]; else b += v[j]; } if (x <= a and a <= y and x <= b and b <= y) return !printf( %d n , i); } puts( 0 ); }
|
#include <bits/stdc++.h> using namespace std; int heliqi; int main() { long long N, M, K; cin >> N >> M >> K; long long ans = -1; if (N + M < K + 2) { cout << -1 << endl; return 0; } long long t = 2; while (t--) { if (K < N) ans = max((N / (K + 1)) * M, ans); else ans = max(M / (K - N + 1 + 1), ans); swap(N, M); } cout << ans << endl; return 0; }
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*########################################################################
AXI WRAPPER FOR EMON BLOCK
########################################################################
*/
module axi_mon (/*AUTOARG*/
// Outputs
s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid,
emon_zero_flag,
// Inputs
s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_rready, erx_rdfifo_access, erx_rdfifo_wait,
erx_wrfifo_access, erx_wrfifo_wait, erx_wbfifo_access,
erx_wbfifo_wait, etx_rdfifo_access, etx_rdfifo_wait,
etx_wrfifo_access, etx_wrfifo_wait, etx_wbfifo_access,
etx_wbfifo_wait
);
//Register file parameters
/*
#####################################################################
COMPILE TIME PARAMETERS
######################################################################
*/
parameter DW = 32; //elink monitor register width
parameter AW = 32; //mmu table address width
parameter SW = DW/8; //mmu table address width
parameter MAW = 6; //register file address width
parameter MDW = 32; //
/*****************************/
/*AXI SLAVE INTERFACE (LITE) */
/*****************************/
//Global signals
input s_axi_aclk; //clock source for axi slave interfaces
input s_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
input [AW-1:0] s_axi_awaddr; //write address
input [2:0] s_axi_awprot; //write protection type
input s_axi_awvalid; //write address valid
output s_axi_awready; //write address ready
//Write data channel
input [DW-1:0] s_axi_wdata; //write data
input [SW-1:0] s_axi_wstrb; //write strobes
input s_axi_wvalid; //write valid
output s_axi_wready; //write channel ready
//Buffered write response channel
input s_axi_bready; //write ready
output [1:0] s_axi_bresp; //write response
output s_axi_bvalid; //write response valid
//Read address channel
input [AW-1:0] s_axi_araddr; //read address
input [2:0] s_axi_arprot; //read protection type
input s_axi_arvalid; //read address valid
output s_axi_arready; //read address ready
//Read data channel
output [DW-1:0] s_axi_rdata; //read data
output [1:0] s_axi_rresp; //read response
output s_axi_rvalid; //read valid
input s_axi_rready; //read ready
/*****************************/
/*EMON SIGNALS */
/*****************************/
input erx_rdfifo_access;
input erx_rdfifo_wait;
input erx_wrfifo_access;
input erx_wrfifo_wait;
input erx_wbfifo_access;
input erx_wbfifo_wait;
input etx_rdfifo_access;
input etx_rdfifo_wait;
input etx_wrfifo_access;
input etx_wrfifo_wait;
input etx_wbfifo_access;
input etx_wbfifo_wait;
output [5:0] emon_zero_flag;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire mi_access; // From axi_memif of axi_memif.v
wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
wire [MDW-1:0] mi_data_in; // From axi_memif of axi_memif.v
wire [DW-1:0] mi_data_out; // From emon of emon.v
wire mi_write; // From axi_memif of axi_memif.v
// End of automatics
/*****************************/
/*AXI INTERFACE */
/*****************************/
axi_memif axi_memif(/*AUTOINST*/
// Outputs
.s_axi_awready (s_axi_awready),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata[DW-1:0]),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.mi_addr (mi_addr[MAW-1:0]),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_data_in (mi_data_in[MDW-1:0]),
// Inputs
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_wdata (s_axi_wdata[DW-1:0]),
.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr[AW-1:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_rready (s_axi_rready),
.mi_data_out (mi_data_out[MDW-1:0]));
/*****************************/
/*EMON */
/*****************************/
emon emon(
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[DW-1:0]),
.emon_zero_flag (emon_zero_flag[5:0]),
// Inputs
.clk (clk),
.reset (reset),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[5:0]),
.mi_data_in (mi_data_in[DW-1:0]),
.erx_rdfifo_access (erx_rdfifo_access),
.erx_rdfifo_wait (erx_rdfifo_wait),
.erx_wrfifo_access (erx_wrfifo_access),
.erx_wrfifo_wait (erx_wrfifo_wait),
.erx_wbfifo_access (erx_wbfifo_access),
.erx_wbfifo_wait (erx_wbfifo_wait),
.etx_rdfifo_access (etx_rdfifo_access),
.etx_rdfifo_wait (etx_rdfifo_wait),
.etx_wrfifo_access (etx_wrfifo_access),
.etx_wrfifo_wait (etx_wrfifo_wait),
.etx_wbfifo_access (etx_wbfifo_access),
.etx_wbfifo_wait (etx_wbfifo_wait));
endmodule // axi_mon
// Local Variables:
// verilog-library-directories:("." "../axi")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_FUNCTIONAL_PP_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEV",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEV",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEV",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> struct outputer; struct outputable {}; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } const int N = 200000; struct Input { int n; int a[N]; vector<int> e[N]; bool read() { if (!(cin >> n)) { return 0; } for (int i = int(0); i < int(n); ++i) { scanf( %d , &a[i]); --a[i]; } for (int i = int(0); i < int(n - 1); ++i) { int x, y; scanf( %d%d , &x, &y); --x; --y; e[x].emplace_back(y); e[y].emplace_back(x); } return 1; } void init(const Input& input) { *this = input; } }; struct Data : Input { int ans; void write() { cout << ans << endl; } }; namespace Main { struct Solution : Data { int mx; array<int, 2> calc(int v, int pr) { array<int, 2> res{0, 0}; if (a[v] != -1) { res[a[v]] = 1; } for (int to : e[v]) { if (to == pr) { continue; } array<int, 2> cur = calc(to, v); for (int t = int(0); t < int(2); ++t) { umx(mx, res[t] + cur[!t]); } for (int t = int(0); t < int(2); ++t) { umx(res[t], cur[t]); if (a[v] == t) { umx(res[t], cur[!t] + 1); } } } for (int t = int(0); t < int(2); ++t) { umx(mx, res[t]); } return res; } void solve() { mx = 0; calc(0, -1); ans = mx / 2 + 1; } void clear() { for (int i = int(0); i < int(n); ++i) { e[i] = vector<int>(); } } }; } // namespace Main Main::Solution sol; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); int t; cin >> t; for (int i = int(0); i < int(t); ++i) { sol.read(); sol.solve(); sol.write(); sol.clear(); } return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/1ps
module system_tb();
reg sys_clk;
reg resetin;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
initial begin
resetin = 1'b0;
#200 resetin = 1'b1;
end
wire [24:0] flash_adr;
reg [31:0] flash_d;
reg [31:0] flash[0:32767];
initial $readmemh("bios.rom", flash);
always @(flash_adr) #110 flash_d = flash[flash_adr/2];
system system(
.clkin(sys_clk),
.resetin(resetin),
.flash_adr(flash_adr),
.flash_d(flash_d),
.uart_rxd(),
.uart_txd()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int main() { cin >> s; int n = s.size(); bool flag = 1; for (int i = 1; i < n; i++) if (!(s[i] >= A && s[i] <= Z )) flag = 0; if (flag) { for (int i = 0; i < n; i++) if ( a <= s[i] && s[i] <= z ) cout << (char)(s[i] + A - a ); else cout << (char)(s[i] + a - A ); cout << endl; } else cout << s << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[51]; long long c[51][51]; double dp[51][51][51]; bool state[51][51][51]; double cal(int stu, int room, int mval) { if (state[stu][room][mval]) return dp[stu][room][mval]; state[stu][room][mval] = true; double &ret = dp[stu][room][mval]; if (!stu) return ret = mval; if (!room) return ret = 0.0; for (int i = 0; i <= stu; i++) { int rval = i / a[room] + (i % a[room] != 0); ret += 1.0 * c[i][stu] * pow(1.0 / room, i) * pow(1.0 - 1.0 / room, stu - i) * cal(stu - i, room - 1, max(mval, rval)); } return ret; } int main() { int n, m, i; for (i = 1; i <= 50; i++) c[0][i] = c[i][i] = 1; for (i = 2; i <= 50; i++) for (n = 1; n < i; n++) c[n][i] = c[n - 1][i - 1] + c[n][i - 1]; scanf( %d %d , &n, &m); for (i = 1; i <= m; i++) scanf( %d , a + i); printf( %.20lf , cal(n, m, 0)); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m; long long q_pow(long long a, long long b, long long c) { if (b == 0) return 1; long long ret = q_pow(a, b / 2, c); ret = (ret * ret) % c; if (b & 1) ret = (ret * a) % c; return ret; } int main() { scanf( %d%d , &n, &m); long long ans = (q_pow(3, n, m) + m - 1) % m; cout << ans << endl; return 0; }
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#include <bits/stdc++.h> void parse(int size, std::string& input, int& pos, int depth, int& max_depth, std::vector<std::vector<std::string> >& comments) { if (size <= pos) { return; } if (depth > max_depth) { max_depth = depth; comments.push_back(std::vector<std::string>()); } int end = pos; while (input[end++] != , ) { } comments[depth].push_back(input.substr(pos, end - pos - 1)); pos = end; while (end < size && input[end++] != , ) { } if (end == size) { ++end; } int children = std::stoi(input.substr(pos, end - pos - 1)); pos = end; for (int i = 0; i < children; ++i) { parse(size, input, pos, depth + 1, max_depth, comments); } } int main() { std::string input; std::cin >> input; std::vector<std::vector<std::string> > comments; int max_depth = -1, pos = 0, size = input.size(); while (pos < size) { parse(size, input, pos, 0, max_depth, comments); } std::cout << max_depth + 1 << std::endl; bool not_first; for (std::vector<std::string>& level : comments) { not_first = false; for (std::string& comment : level) { if (not_first) { std::cout << ; } else { not_first = true; } std::cout << comment; } std::cout << std::endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string a, s; int c(0); cin >> a >> s; sort(s.begin(), s.end()), reverse(s.begin(), s.end()); for (int i = 0; i < a.size(); i++) { if (a[i] < s[c]) a[i] = s[c++]; } cout << a << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, x, i, y, ans = 0, q; scanf( %d%d , &n, &x); y = int(sqrt(x)); if (n < y) y = n; for (i = 1; i <= y; i++) { if (x % i == 0) { q = x / i; if (q <= n) { if (i == q) ans++; else ans += 2; } } } if (x == 1) printf( %d n , 1); else printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long rr[] = {0, 1, 1, 1, 0, -1, -1, -1}; long long cc[] = {1, 1, 0, -1, -1, -1, 0, 1}; const long long mod = 1e9 + 7; const long long N = 300050; long long m, fact[N]; void pre() { fact[0] = 1; for (long long i = 1; i < N; i++) { fact[i] = (fact[i - 1] * i) % m; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long test = 1; while (test--) { long long n; cin >> n >> m; pre(); long long ans = 0; for (long long i = 1; i <= n; i++) { long long x = fact[n - i + 1] * (n - i + 1) % m; x = (x * fact[i]) % m; ans = (ans + x) % m; } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, a[100001]; long long sum = 0, x = 0, ans = 0; cin >> n; for (int i = 0; i < n; i++) cin >> a[i], sum += a[i]; sum = sum / n; for (int i = 0; i < n; i++) x += a[i] - sum, ans += abs(x); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace MincostMaxFlow { const int maxn(2e5 + 5); struct Edge { int to, next, w, f; }; int first[maxn], cnt, vis[maxn], dis[maxn], S, T, pe[maxn], pv[maxn], maxflow, mincost; Edge edge[maxn * 20]; queue<int> Q; inline void Init(int _S, int _T) { cnt = mincost = maxflow = 0, S = _S, T = _T; memset(first, -1, sizeof(first)); } inline void AddEdge(int u, int v, int w, int f) { edge[cnt] = (Edge){v, first[u], w, f}, first[u] = cnt++; edge[cnt] = (Edge){u, first[v], -w, 0}, first[v] = cnt++; } inline int SPFA() { int e, u, v, inf; memset(dis, 63, sizeof(dis)), inf = dis[0]; Q.push(S), dis[S] = 0, vis[S] = 1; while (!Q.empty()) { u = Q.front(), Q.pop(); for (e = first[u]; ~e; e = edge[e].next) if (edge[e].f && dis[u] + edge[e].w < dis[v = edge[e].to]) { dis[v] = dis[u] + edge[e].w, pv[v] = u, pe[v] = e; if (!vis[v]) vis[v] = 1, Q.push(v); } vis[u] = 0; } if (dis[T] >= 0) return 0; for (v = T; v ^ S; v = pv[v]) inf = min(inf, edge[pe[v]].f); maxflow += inf, mincost += dis[T] * inf; for (v = T; v ^ S; v = pv[v]) edge[pe[v]].f -= inf, edge[pe[v] ^ 1].f += inf; return 1; } inline int MCMF() { while (SPFA()) ; return mincost; } } // namespace MincostMaxFlow using MincostMaxFlow ::AddEdge; using MincostMaxFlow ::Init; using MincostMaxFlow ::MCMF; const int inf(1e7); int n, k, a[85], c[85], S, T; int main() { int i, j, tmp; scanf( %d%d , &n, &k), k = min(k, n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); for (i = 1; i <= n; ++i) scanf( %d , &c[i]); Init(S = 0, T = n + n + 2), tmp = n + n + 1, AddEdge(S, tmp, 0, k); for (i = 1; i <= n; ++i) { AddEdge(i, i + n, -inf, 1); for (j = i + 1; j <= n; ++j) if (a[j] == a[i]) AddEdge(i + n, j, 0, 1); else AddEdge(i + n, j, c[a[j]], 1); AddEdge(i + n, T, 0, 1), AddEdge(tmp, i, c[a[i]], 1); } printf( %d n , MCMF() + n * inf); return 0; }
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//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
module opicorv32_rv32_wrap (
irq,
pcpi_ready,
pcpi_wait,
pcpi_rd,
pcpi_wr,
mem_rdata,
mem_ready,
resetn,
clk,
trap,
mem_valid,
mem_instr,
mem_addr,
mem_wdata,
mem_wstrb,
mem_la_read,
mem_la_write,
mem_la_addr,
mem_la_wdata,
mem_la_wstrb,
pcpi_valid,
pcpi_insn,
pcpi_rs1,
pcpi_rs2,
eoi
);
input [31:0] irq;
input pcpi_ready;
input pcpi_wait;
input [31:0] pcpi_rd;
input pcpi_wr;
input [31:0] mem_rdata;
input mem_ready;
input resetn;
input clk;
output trap;
output mem_valid;
output mem_instr;
output [31:0] mem_addr;
output [31:0] mem_wdata;
output [3:0] mem_wstrb;
output mem_la_read;
output mem_la_write;
output [31:0] mem_la_addr;
output [31:0] mem_la_wdata;
output [3:0] mem_la_wstrb;
output pcpi_valid;
output [31:0] pcpi_insn;
output [31:0] pcpi_rs1;
output [31:0] pcpi_rs2;
output [31:0] eoi;
/* signal declarations */
wire [31:0] _9626;
wire [31:0] _9610;
wire [31:0] compare_eoi;
wire [31:0] _9628;
wire [31:0] _9629;
wire [31:0] _9611;
wire [31:0] compare_pcpi_rs2;
wire [31:0] _9631;
wire [31:0] _9632;
wire [31:0] _9612;
wire [31:0] compare_pcpi_rs1;
wire [31:0] _9634;
wire [31:0] _9635;
wire [31:0] _9613;
wire [31:0] compare_pcpi_insn;
wire [31:0] _9637;
wire _9638;
wire _9614;
wire compare_pcpi_valid;
wire _9640;
wire [3:0] _9641;
wire [3:0] _9615;
wire [3:0] compare_mem_la_wstrb;
wire [3:0] _9643;
wire [31:0] _9644;
wire [31:0] _9616;
wire [31:0] compare_mem_la_wdata;
wire [31:0] _9646;
wire [31:0] _9647;
wire [31:0] _9617;
wire [31:0] compare_mem_la_addr;
wire [31:0] _9649;
wire _9650;
wire _9618;
wire compare_mem_la_write;
wire _9652;
wire _9653;
wire _9619;
wire compare_mem_la_read;
wire _9655;
wire [3:0] _9656;
wire [3:0] _9620;
wire [3:0] compare_mem_wstrb;
wire [3:0] _9658;
wire [31:0] _9659;
wire [31:0] _9621;
wire [31:0] compare_mem_wdata;
wire [31:0] _9661;
wire [31:0] _9662;
wire [31:0] _9622;
wire [31:0] compare_mem_addr;
wire [31:0] _9664;
wire _9665;
wire _9623;
wire compare_mem_instr;
wire _9667;
wire _9668;
wire _9624;
wire compare_mem_valid;
wire _9670;
wire [269:0] _9607;
wire _9671;
wire [269:0] _9609;
wire _9625;
wire compare_trap;
wire _9673;
/* logic */
assign _9626 = _9607[269:238];
assign _9610 = _9609[269:238];
assign compare_eoi = _9610 ^ _9626;
assign _9628 = compare_eoi ^ _9626;
assign _9629 = _9607[237:206];
assign _9611 = _9609[237:206];
assign compare_pcpi_rs2 = _9611 ^ _9629;
assign _9631 = compare_pcpi_rs2 ^ _9629;
assign _9632 = _9607[205:174];
assign _9612 = _9609[205:174];
assign compare_pcpi_rs1 = _9612 ^ _9632;
assign _9634 = compare_pcpi_rs1 ^ _9632;
assign _9635 = _9607[173:142];
assign _9613 = _9609[173:142];
assign compare_pcpi_insn = _9613 ^ _9635;
assign _9637 = compare_pcpi_insn ^ _9635;
assign _9638 = _9607[141:141];
assign _9614 = _9609[141:141];
assign compare_pcpi_valid = _9614 ^ _9638;
assign _9640 = compare_pcpi_valid ^ _9638;
assign _9641 = _9607[140:137];
assign _9615 = _9609[140:137];
assign compare_mem_la_wstrb = _9615 ^ _9641;
assign _9643 = compare_mem_la_wstrb ^ _9641;
assign _9644 = _9607[136:105];
assign _9616 = _9609[136:105];
assign compare_mem_la_wdata = _9616 ^ _9644;
assign _9646 = compare_mem_la_wdata ^ _9644;
assign _9647 = _9607[104:73];
assign _9617 = _9609[104:73];
assign compare_mem_la_addr = _9617 ^ _9647;
assign _9649 = compare_mem_la_addr ^ _9647;
assign _9650 = _9607[72:72];
assign _9618 = _9609[72:72];
assign compare_mem_la_write = _9618 ^ _9650;
assign _9652 = compare_mem_la_write ^ _9650;
assign _9653 = _9607[71:71];
assign _9619 = _9609[71:71];
assign compare_mem_la_read = _9619 ^ _9653;
assign _9655 = compare_mem_la_read ^ _9653;
assign _9656 = _9607[70:67];
assign _9620 = _9609[70:67];
assign compare_mem_wstrb = _9620 ^ _9656;
assign _9658 = compare_mem_wstrb ^ _9656;
assign _9659 = _9607[66:35];
assign _9621 = _9609[66:35];
assign compare_mem_wdata = _9621 ^ _9659;
assign _9661 = compare_mem_wdata ^ _9659;
assign _9662 = _9607[34:3];
assign _9622 = _9609[34:3];
assign compare_mem_addr = _9622 ^ _9662;
assign _9664 = compare_mem_addr ^ _9662;
assign _9665 = _9607[2:2];
assign _9623 = _9609[2:2];
assign compare_mem_instr = _9623 ^ _9665;
assign _9667 = compare_mem_instr ^ _9665;
assign _9668 = _9607[1:1];
assign _9624 = _9609[1:1];
assign compare_mem_valid = _9624 ^ _9668;
assign _9670 = compare_mem_valid ^ _9668;
picorv32_rv32
the_picorv32_rv32
( .clk(clk), .resetn(resetn), .mem_ready(mem_ready), .mem_rdata(mem_rdata), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .irq(irq), .eoi(_9607[269:238]), .pcpi_rs2(_9607[237:206]), .pcpi_rs1(_9607[205:174]), .pcpi_insn(_9607[173:142]), .pcpi_valid(_9607[141:141]), .mem_la_wstrb(_9607[140:137]), .mem_la_wdata(_9607[136:105]), .mem_la_addr(_9607[104:73]), .mem_la_write(_9607[72:72]), .mem_la_read(_9607[71:71]), .mem_wstrb(_9607[70:67]), .mem_wdata(_9607[66:35]), .mem_addr(_9607[34:3]), .mem_instr(_9607[2:2]), .mem_valid(_9607[1:1]), .trap(_9607[0:0]) );
assign _9671 = _9607[0:0];
opicorv32_rv32
the_opicorv32_rv32
( .clk(clk), .resetn(resetn), .mem_ready(mem_ready), .mem_rdata(mem_rdata), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .irq(irq), .eoi(_9609[269:238]), .pcpi_rs2(_9609[237:206]), .pcpi_rs1(_9609[205:174]), .pcpi_insn(_9609[173:142]), .pcpi_valid(_9609[141:141]), .mem_la_wstrb(_9609[140:137]), .mem_la_wdata(_9609[136:105]), .mem_la_addr(_9609[104:73]), .mem_la_write(_9609[72:72]), .mem_la_read(_9609[71:71]), .mem_wstrb(_9609[70:67]), .mem_wdata(_9609[66:35]), .mem_addr(_9609[34:3]), .mem_instr(_9609[2:2]), .mem_valid(_9609[1:1]), .trap(_9609[0:0]) );
assign _9625 = _9609[0:0];
assign compare_trap = _9625 ^ _9671;
assign _9673 = compare_trap ^ _9671;
/* aliases */
/* output assignments */
assign trap = _9673;
assign mem_valid = _9670;
assign mem_instr = _9667;
assign mem_addr = _9664;
assign mem_wdata = _9661;
assign mem_wstrb = _9658;
assign mem_la_read = _9655;
assign mem_la_write = _9652;
assign mem_la_addr = _9649;
assign mem_la_wdata = _9646;
assign mem_la_wstrb = _9643;
assign pcpi_valid = _9640;
assign pcpi_insn = _9637;
assign pcpi_rs1 = _9634;
assign pcpi_rs2 = _9631;
assign eoi = _9628;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, I; vector<long long int> vec; vector<long long int> comp; long long int K; int main() { scanf( %lld %lld , &n, &I); for (int i = 1; i <= n; i++) { long long int a; scanf( %lld , &a); vec.push_back(a); } K = 1 << min((long long int)20, 8 * I / n); sort(vec.begin(), vec.end()); long long int pre = -1; for (int i = 1; i <= n; i++) { if (vec[i - 1] != pre) { comp.push_back(i); pre = vec[i - 1]; } } if (8 * I / n >= 20) { printf( 0 ); return 0; } int ans = 1000000000; for (int i = 0; i < comp.size(); ++i) { int num = comp[i] - 1 + (i + K < comp.size() ? n + 1 - comp[i + K] : 0); ans = min(num, ans); } printf( %d , ans); return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* Testbench for the non-synthesizable behavioral model for the
* data memory
*/
// Import the modules that will be tested for in this testbench
`include "datamem.v"
// Include definition of the control signals
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f datamem.f +gui
module tb_datamem ();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the data memory
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_output
wire [0:127] data_output;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// dm_ctrl_sig
reg [0:1] data_memory_control_signal;
// mem_ctrl_addr output signals
reg [0:31] memory_control_address;
// data_input
reg [0:127] data_input;
reg clock;
reg [0:31] counter;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
parameter size_of_input2 = 4'd8;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 10ns <==> 100 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of instr_mem() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "im"
*/
data_mem dm (
// instance_name(signal name),
// Signal name can be the same as the instance name
// data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig
data_output,data_input,memory_control_address,
clock,data_memory_control_signal);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//data_input=$random;
data_input=128'h71;
memory_control_address=32'd0;
data_memory_control_signal=`memnop;
counter=32'd1;
#29
//data_input=$random;
data_input=128'h72;
memory_control_address=counter;
data_memory_control_signal=`memwst;
counter=counter+32'd1;
// data_memory_control_signal=10;
/*
instruction_address=8'd200;
reset=1'b0;
*/
// Try reading the instruction memory without being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
//data_input=$random;
data_input=data_input+128'd1;
memory_control_address=counter;
data_memory_control_signal=`memwst;
//data_memory_control_signal=10;
counter=counter+32'd1;
end
counter=32'd1;
// Read the instruction memory after being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memwld;
//data_memory_control_signal=01;
counter=counter+32'd1;
end
// NOP operation - set the output to ZEROs
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memnop;
// data_memory_control_signal=10;
// counter=counter+32'd1;
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memwld;
//data_memory_control_signal=01;
counter=counter+32'd1;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
// Ask Bhatti what is the size of a byte - dependent on subfield?
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
|
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