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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-10; const int MOD = 998244353; const int INF = 0x3f3f3f3f; const int maxn = 1e3 + 10; const int maxm = 2e5 + 10; char s[maxn]; int len, arr[maxn]; pair<int, long long> dq[maxn]; int main() { scanf( %d%s , &len, s + 1); for (int i = 1; i <= len; ++i) s[len + i] = s[i]; int ans = 0; pair<int, long long> pos; for (int i = 1; i <= len; ++i) for (int j = i; j <= len; ++j) { int cnt = 0; swap(s[i], s[j]); swap(s[i + len], s[j + len]); int top = 500, bk = 499; for (int k = 1; k <= len * 2; ++k) { if (s[k] == ( ) arr[k] = ++cnt; else arr[k] = --cnt; } for (int k = 1; k <= len; ++k) { while (bk >= top && dq[bk].first > arr[k]) --bk; dq[++bk] = {arr[k], k}; } int pre = 0, res = 0; for (int k = 1; k <= len; ++k) { while (dq[top].second < k) ++top; while (bk >= top && dq[bk].first >= arr[k + len - 1]) --bk; dq[++bk] = {arr[k + len - 1], k + len - 1}; if (dq[top].first - pre >= 0 && arr[k + len - 1] - pre == 0) ++res; pre = arr[k]; } if (ans < res) { ans = res; pos = {i, j}; } swap(s[i], s[j]); swap(s[i + len], s[j + len]); } printf( %d n , ans); if (pos.first == 0) pos = {1, 1}; printf( %d %d n , pos.first, pos.second); return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(int x) { return (unsigned int)(8 * sizeof(int) - __builtin_clz(x)); } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.x) ^ (u(p.y) << 7); } }; } // namespace std template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; void fastIO() { ios::sync_with_stdio(false); } template <typename T, typename... Args> T max(T t, Args... args) { return max(max<T>(args...), t); } template <typename T, typename... Args> T min(T t, Args... args) { return min(min<T>(args...), t); } using PLL = pair<long long, unsigned long long>; class FFooFighters { public: void solve(std::istream& in, std::ostream& out) { fastIO(); int n; in >> n; vector<PLL> a(n); in >> a; unsigned long long mb = 1; unsigned long long res = 0; long long ds = 0; for (auto p : a) { ds += p.first; } for (int i = 0; i < 64; ++i) { long long cs = 0; for (auto p : a) { if (p.second >= mb && p.second < 2 * mb) { ds += p.first; long long nmask = p.second & res; if (__builtin_popcountll(nmask) % 2 == 1) cs -= p.first; else cs += p.first; } } if (cs != 0 && signbit(ds) == signbit(cs)) { res |= mb; } mb <<= 1; } out << res << endl; } }; int main() { FFooFighters solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = LLONG_MAX; long long gcd(long long x, long long y) { if (y == 0) return x; else return gcd(y, x % y); } long long power(long long x, unsigned long long y) { long long res = 1; x = x % MOD; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % MOD; y = y >> 1; x = (x * x) % MOD; } return res; } void solve() { long long n, m, b, c, d, ans = 0, one = 0; cin >> n; long long a[n]; for (long long i = (long long)0; i < n; i++) { cin >> a[i]; if (a[i] >= 2 * one) { a[i] -= 2 * one; ans += one + a[i] / 3; one = a[i] % 3; } else { one += a[i] % 2; one -= a[i] / 2; ans += a[i] / 2; } } cout << ans << n ; } int32_t main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t = 1; while (t--) solve(); }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; void qread(int &x) { int neg = 1; x = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) neg = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = 10 * x + c - 0 , c = getchar(); x *= neg; } const int maxn = 100005; int n, l, r, k, ans, ansu, ansv; vector<pair<int, int> > edge[maxn]; vector<int> num; int oriw[maxn], w[maxn], dep[maxn], lvl[maxn], son[maxn]; int pos[maxn], dis[maxn]; pair<int, int> val[maxn]; namespace Segtree { int sz; pair<int, int> t[maxn * 4]; void init(int _sz) { for (sz = 1; sz < _sz; sz <<= 1) ; for (int(i) = 0; (i) < sz << 1; i++) t[i] = make_pair(-1e9, -1e9); } void update(int v, pair<int, int> val) { v += sz - 1; t[v] = val; for (v >>= 1; v; v >>= 1) t[v] = max(t[v << 1], t[v << 1 | 1]); } pair<int, int> query(int l, int r) { pair<int, int> res = make_pair(-1e9, -1e9); for (l += sz - 1, r += sz - 1; l <= r; l >>= 1, r >>= 1) { if (l & 1) res = max(res, t[l]), l++; if ((r + 1) & 1) res = max(res, t[r]), r--; } return res; } } // namespace Segtree void prework1(int x, int p, int d) { dep[x] = lvl[x] = d; for (int(i) = 0; (i) < edge[x].size(); i++) { pair<int, int> y = edge[x][i]; if (y.first == p) continue; prework1(y.first, x, d + 1); if (!son[x] || lvl[y.first] > lvl[son[x]]) son[x] = y.first; lvl[x] = max(lvl[x], lvl[y.first]); } } void prework2(int x, int p) { pos[x] = ++k; if (son[x]) prework2(son[x], x); for (int(i) = 0; (i) < edge[x].size(); i++) { pair<int, int> y = edge[x][i]; if (y.first == p || y.first == son[x]) continue; prework2(y.first, x); } } void work(int x, int p, int cur) { val[pos[x]] = make_pair(cur, x); dis[x] = cur; Segtree::update(pos[x], make_pair(cur, x)); for (int(i) = 0; (i) < edge[x].size(); i++) { int y = edge[x][i].first; if (y == son[x]) work(y, x, cur + w[edge[x][i].second]); } for (int(i) = 0; (i) < edge[x].size(); i++) { int y = edge[x][i].first; if (y == p || y == son[x]) continue; work(y, x, cur + w[edge[x][i].second]); int tmp = lvl[y] - dep[y]; for (int(d) = 0; (d) < tmp + 1; d++) { int ql = max(l - d - 1, 0), qr = min(r - d - 1, lvl[x] - dep[x]); pair<int, int> val2 = Segtree::query(pos[x] + ql, pos[x] + qr); if (val[pos[y] + d].first + val2.first - 2 * dis[x] > ans) { ans = val[pos[y] + d].first + val2.first - 2 * dis[x]; ansu = val[pos[y] + d].second; ansv = val2.second; } } for (int(d) = 0; (d) < tmp + 1; d++) { val[pos[x] + d + 1] = max(val[pos[x] + d + 1], val[pos[y] + d]); Segtree::update(pos[x] + d + 1, val[pos[x] + d + 1]); } } pair<int, int> val2 = Segtree::query(pos[x] + l, pos[x] + min(r, lvl[x] - dep[x])); if (val2.first - dis[x] > ans) { ans = val2.first - dis[x]; ansu = x; ansv = val2.second; } } bool check(int x) { for (int(i) = 1; (i) <= n - 1; i++) { if (oriw[i] < x) w[i] = -1; else w[i] = 1; } Segtree::init(n); for (int(i) = 1; (i) <= n; i++) val[i] = make_pair(-1e9, -1e9); ans = -1e9; work(1, 0, 0); return ans >= 0; } int main() { scanf( %d%d%d , &n, &l, &r); for (int(i) = 1; (i) <= n - 1; i++) { int u, v; scanf( %d%d%d , &u, &v, &oriw[i]); edge[u].push_back(make_pair(v, i)); edge[v].push_back(make_pair(u, i)); num.push_back(oriw[i]); } prework1(1, 0, 0); prework2(1, 0); sort(num.begin(), num.end()); num.resize(unique(num.begin(), num.end()) - num.begin()); int l = 0, r = num.size(); while (r - l > 1) { int mid = (l + r) >> 1; if (check(num[mid])) l = mid; else r = mid; } check(num[l]); printf( %d %d n , ansu, ansv); return 0; }
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#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const int INF = 1 << 28; const long long INFL = 1LL << 62; int toi(string x) { int z; istringstream iss(x); iss >> z; return z; } string str[] = { YES , NO }; int modulo(int m, int n) { return m >= 0 ? m % n : (n - abs(m % n)) % n; } using namespace std; int arr[101] = {0}, n, m; int main() { cin >> n >> m; for (int i = 1, a, b, c; i <= m; i++) { cin >> a >> b >> c; arr[a] -= c; arr[b] += c; } int sum = 0; for (int i = 1; i <= n; i++) if (arr[i] > 0) sum += arr[i]; cout << sum << endl; return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:667772160 ) using namespace std; struct __isoff { __isoff() { if (0) freopen( input.txt , r , stdin), freopen( output.txt , w , stdout); srand( C + T + A + C + Y + M + B + A ); } ~__isoff() {} } __osafwf; const unsigned long long p1 = 31; const unsigned long long p2 = 29; const double eps = 1e-8; const double pi = acos(-1.0); const int infi = 1e9 + 7; const long long inf = 1e18 + 7; const long long dd = 2e5 + 7; const long long mod = 1e9 + 7; const int logc = 20; int up[dd][logc], H[dd], in[dd], out[dd], ti = 0; vector<int> P[dd]; void dfs(int v, int p = 0, int h = 0) { H[v] = h; in[v] = ti++; up[v][0] = p; for (int i = 1; i < logc; i++) { up[v][i] = up[up[v][i - 1]][i - 1]; } for (auto it : P[v]) { if (it != p) { dfs(it, v, h + 1); } } out[v] = ti++; } void build() { dfs(0); } bool is(int a, int b) { return in[a] <= in[b] && out[b] <= out[a]; } int lca(int a, int b) { if (is(a, b)) { return a; } if (is(b, a)) { return b; } for (int i = logc - 1; i >= 0; i--) { int t = up[a][i]; if (!is(t, b)) { a = t; } } return up[a][0]; } int dis(int a, int b) { return H[a] + H[b] - 2 * H[lca(a, b)]; } int main() { int n; cin >> n; vector<int> E; for (long long i = 0; i < (long long)n - 1; i++) { int t; cin >> t; t--; P[t].push_back(i + 1); E.push_back(i + 1); } build(); int a = 0, b = 0, l = 0; for (long long i = 0; i < (long long)n - 1; i++) { int t = E[i]; if (l < dis(a, t)) { l = dis(a, t); b = t; } if (l < dis(b, t)) { l = dis(b, t); a = t; } cout << l << n ; } }
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//This module implements a register file with enough ports to be
//relatively extensible. (namely, it has two)
module registerfile(
clk,
rst,
as1,
bs1,
cs1,
cw1,
cd1,
as2,
bs2,
cs2,
cw2,
cd2,
AD1,
BD1,
CD1,
WT1,
AD2,
BD2,
CD2,
WT2
);
input clk;
input rst;
//First port:
input [2:0] as1;
input [2:0] bs1;
input [2:0] cs1;
input cw1;
input [15:0] cd1;
output [15:0] AD1;
output [15:0] BD1;
output [15:0] CD1;
output WT1; //Wait signal.
//Second port:
input [2:0] as2;
input [2:0] bs2;
input [2:0] cs2;
input cw2;
input [15:0] cd2;
output [15:0] AD2;
output [15:0] BD2;
output [15:0] CD2;
output WT2; //Wait signal.
//Declare actual register storage:
reg [15:0] rDat [0:7];
assign AD1=rDat[as1];
assign AD2=rDat[as2];
assign BD1=rDat[bs1];
assign BD2=rDat[bs2];
assign CD1=rDat[cs1];
assign CD2=rDat[cs2];
//Block the first write port if the other is writing.
assign WT1=(cs1==cs2)&&cw2;
//Block the second write port if the other is writing.
assign WT2=(cs1==cs2)&&cw1;
always@(posedge clk or posedge rst) begin
if(rst) begin
rDat[0]<=0;
rDat[1]<=0;
rDat[2]<=0;
rDat[3]<=0;
rDat[4]<=0;
rDat[5]<=0;
rDat[6]<=0;
rDat[7]<=0;
end
else begin
if(cw1&&~WT1) begin
rDat[cs1]<=cd1;
end
if(cw2&&~WT2) begin
rDat[cs2]<=cd2;
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); bool flag = true; for (int i = 0; i < n; i++) { if (i == 0) { int l = a[1]; int r = a[2]; if (a[i] >= l + r) flag = false; } else if (i == n - 1) { int l = a[n - 3]; int r = a[n - 2]; if (a[i] >= l + r) flag = false; } else { int l, r; if (i + 2 > n - 1) r = a[n - 1]; else r = a[i + 2]; if (i - 2 < 0) l = a[0]; else l = a[i - 2]; if (a[i] >= l + r) flag = false; } } if (flag == false) cout << NO n ; else { cout << YES n ; cout << a[0] << ; int i = 1; while (i < n) { cout << a[i] << ; i = i + 2; } if (n % 2) i = n - 1; else i = n - 2; while (i >= 2) { cout << a[i] << ; i = i - 2; } } }
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//======================================================================
//
// fltcpu.v
// --------
// Top level file of the fltfpga cpu.
//
// For instruction format and details of the CPU see the
// fltcpu.md document.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fltcpu(
// Clock and reset.
input wire clk,
input wire reset_n,
output wire mem_cs,
output wire [3 : 0] mem_we,
output wire [31 : 0] mem_address,
input wire [31 : 0] mem_rd_data,
output wire [31 : 0] mem_wr_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Control states.
localparam CTRL_IDLE = 4'h0;
localparam CTRL_INSTR_READ = 4'h1;
localparam CTRL_INSTR_WAIT = 4'h2;
localparam CTRL_INSTR_STORE = 4'h3;
localparam CTRL_INSTR_EXE0 = 4'h4;
localparam CTRL_MEM_WRITE = 4'h5;
localparam CTRL_MEM_READ = 4'h6;
localparam CTRL_MEM_WAIT = 4'h7;
localparam CTRL_INSTR_EXE1 = 4'h8;
localparam CTRL_INSTR_DONE = 4'h9;
localparam CTRL_IRQ_START = 4'hc;
localparam CTRL_IRQ_DECODE = 4'hd;
localparam CTRL_IRQ_DONE = 4'he;
// Opcodes.
localparam OP_BRK = 6'h00;
localparam OP_NOP = 6'h01;
localparam OP_EXE = 6'h02;
localparam OP_AND = 6'h04;
localparam OP_OR = 6'h05;
localparam OP_XOR = 6'h06;
localparam OP_NOT = 6'h07;
localparam OP_ADD = 6'h08;
localparam OP_ADDI = 6'h09;
localparam OP_SUB = 6'h0a;
localparam OP_SUBI = 6'h0b;
localparam OP_MUL = 6'h0c;
localparam OP_MULI = 6'h0d;
localparam OP_ASL = 6'h10;
localparam OP_ASLI = 6'h11;
localparam OP_ASR = 6'h12;
localparam OP_ASRI = 6'h13;
localparam OP_ROL = 6'h14;
localparam OP_ROLI = 6'h15;
localparam OP_ROR = 6'h16;
localparam OP_RORI = 6'h17;
localparam OP_RD = 6'h20;
localparam OP_RDI = 6'h21;
localparam OP_RDC = 6'h22;
localparam OP_WR = 6'h28;
localparam OP_WRI = 6'h29;
localparam OP_MV = 6'h2a;
localparam OP_CMP = 6'h30;
localparam OP_CMPI = 6'h31;
localparam OP_BEQ = 6'h32;
localparam OP_BEQI = 6'h33;
localparam OP_BNEI = 6'h35;
localparam OP_JSR = 6'h38;
localparam OP_JSRI = 6'h39;
localparam OP_JMP = 6'h3a;
localparam OP_JMPI = 6'h3b;
localparam OP_RTS = 6'h3f;
// Instruction types.
localparam ITYPE_REG_REG = 2'h0;
localparam ITYPE_MEM_RD = 2'h1;
localparam ITYPE_MEM_WR = 2'h2;
localparam ITYPE_MEM_JMP = 2'h3;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] instruction_reg;
reg instruction_we;
reg [3 : 0] fltcpu_ctrl_reg;
reg [3 : 0] fltcpu_ctrl_new;
reg fltcpu_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [5 : 0] opcode;
wire [4 : 0] dst_addr;
wire [31 : 0] dst_wr_data;
wire [31 : 0] dst_rd_data;
reg dst_we;
wire [4 : 0] source0_addr;
wire [31 : 0] source0_data;
wire [4 : 0] source1_addr;
wire [31 : 0] source1_data;
wire [15 : 0] constant;
reg inc_pc;
reg ret_pc;
wire [31 : 0] pc;
wire zero_flag;
wire eq_data;
reg [1 : 0] instr_type;
reg tmp_mem_cs;
reg [3 : 0] tmp_mem_we;
reg [31 : 0] tmp_mem_address;
reg [31 : 0] tmp_mem_wr_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign mem_cs = tmp_mem_cs;
assign mem_we = tmp_mem_we;
assign mem_address = tmp_mem_address;
assign mem_wr_data = tmp_mem_wr_data;
assign opcode = instruction_reg[31 : 26];
assign dst_addr = instruction_reg[25 : 21];
assign source0_addr = instruction_reg[20 : 16];
assign source1_addr = instruction_reg[15 : 11];
assign constant = instruction_reg[15 : 00];
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
fltcpu_regfile regfile(
.clk(clk),
.reset_n(reset_n),
.src0_addr(source0_addr),
.src0_data(source0_data),
.src1_addr(source1_addr),
.src1_data(source1_data),
.dst_we(dst_we),
.dst_addr(dst_addr),
.dst_wr_data(dst_wr_data),
.zero_flag(zero_flag),
.inc(inc_pc),
.ret(ret_pc),
.pc(pc)
);
fltcpu_alu alu(
.clk(clk),
.reset_n(reset_n),
.opcode(opcode),
.src0_data(source0_data),
.src1_data(source1_data),
.dst_data(dst_wr_data),
.eq_data(eq_data)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
instruction_reg <= 32'h0;
fltcpu_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (instruction_we)
instruction_reg <= mem_rd_data;
if (fltcpu_ctrl_we)
fltcpu_ctrl_reg <= fltcpu_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// mem_access
//
// Memory access mux.
//----------------------------------------------------------------
always @*
begin : mem_access
if (instruction_we)
begin
end
else
begin
end
end // mem_access
//----------------------------------------------------------------
// instruction_decode
//
// Detect instruction type and select operands based on the
// current instruction.
//----------------------------------------------------------------
always @*
begin : select_operands
case (opcode)
OP_BRK, OP_NOP:
begin
end
OP_AND, OP_OR, OP_XOR, OP_NOT:
begin
end
OP_ADD, OP_ADDI, OP_SUB, OP_SUBI, OP_MUL, OP_MULI:
begin
end
OP_ASL, OP_ASLI, OP_ASR, OP_ASRI, OP_ROL, OP_ROLI, OP_ROR, OP_RORI:
begin
end
OP_MV:
begin
end
OP_CMP, OP_CMPI:
begin
instr_type = ITYPE_REG_REG;
end
OP_RD, OP_RDI, OP_RDC:
begin
instr_type = ITYPE_MEM_RD;
end
OP_WR, OP_WRI:
begin
instr_type = ITYPE_MEM_WR;
end
OP_BEQ, OP_BEQI, OP_BNEI:
begin
end
OP_JSR, OP_JSRI, OP_JMP, OP_JMPI, OP_RTS:
begin
instr_type = ITYPE_MEM_JMP;
end
default:
begin
end
endcase // case (opcode)
// Decode instruction types
end // select_operands
//----------------------------------------------------------------
// fltcpu_ctrl
//
// Main control FSM of the CPU.
//----------------------------------------------------------------
always @*
begin : fltcpu_ctrl
dst_we = 0;
instruction_we = 0;
inc_pc = 0;
ret_pc = 0;
tmp_mem_cs = 0;
tmp_mem_we = 0;
tmp_mem_address = 0;
fltcpu_ctrl_new = CTRL_IDLE;
fltcpu_ctrl_we = 0;
case (fltcpu_ctrl_reg)
CTRL_IDLE:
begin
fltcpu_ctrl_new = CTRL_INSTR_READ;
fltcpu_ctrl_we = 1;
end
CTRL_INSTR_READ:
begin
tmp_mem_cs = 1;
tmp_mem_address = pc;
fltcpu_ctrl_new = CTRL_INSTR_WAIT;
fltcpu_ctrl_we = 1;
end
CTRL_INSTR_WAIT:
begin
tmp_mem_cs = 1;
tmp_mem_address = pc;
fltcpu_ctrl_new = CTRL_INSTR_STORE;
fltcpu_ctrl_we = 1;
end
CTRL_INSTR_STORE:
begin
instruction_we = 1;
fltcpu_ctrl_new = CTRL_INSTR_STORE;
fltcpu_ctrl_we = 1;
end
CTRL_INSTR_EXE0:
begin
end
CTRL_MEM_WRITE:
begin
end
CTRL_MEM_READ:
begin
end
CTRL_MEM_WAIT:
begin
end
CTRL_INSTR_EXE1:
begin
end
CTRL_INSTR_DONE:
begin
end
CTRL_IRQ_START:
begin
end
CTRL_IRQ_DECODE:
begin
end
CTRL_IRQ_DONE:
begin
end
default:
begin
end
endcase // case (fltcpu_ctrl_reg)
end // fltcpu_ctrl
endmodule // fltcpu
//======================================================================
// EOF fltcpu.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e7 + 7; const int mod = 998244353; const long long INF = 1e18; long long jc[maxn]; long long n, k; long long inv2 = 499122177; void init() { jc[0] = 1; for (long long i = 1; i < maxn; i++) jc[i] = jc[i - 1] * i % mod; } long long exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1; y = 0; return a; } long long d = exgcd(b, a % b, y, x); y -= a / b * x; return d; } long long inv(long long a, long long n) { long long x, y; exgcd(a, n, x, y); return (x + n) % n; } long long C(long long n, long long m) { return jc[n] * inv(jc[m] * jc[n - m] % mod, mod) % mod; } long long qpow(long long x, int n) { long long res = 1; while (n) { if (n & 1) res = (res * x) % mod; x = (x * x) % mod; n /= 2; } return res; } void rua() { init(); scanf( %lld%lld , &n, &k); if (k >= n) { printf( 0 n ); return; } long long ans = 0; n -= k; for (int i = 0; i <= n; i += 2) ans = (ans + C(n, i) * qpow(n - i, n + k) % mod) % mod; for (int i = 1; i <= n; i += 2) ans = (ans - C(n, i) * qpow(n - i, n + k) % mod + mod) % mod; ans = ans * 2ll % mod * C(n + k, n) % mod; if (k == 0) ans = (ans * 499122177) % mod; printf( %lld n , ans); } int main() { rua(); return 0; }
|
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "simulation_includes.vh"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
//`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h00000035); //115200bps from 100 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, {24'h000000, char});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!`testbench.uart0_int)
@(posedge `testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h0, `testbench.read_word);
$display("TASK: UART Read = %c @ %d", `testbench.read_word, $time);
if (`testbench.read_word != expected)
begin
$display("FAIL: UART Read = 0x%h NOT 0x%h @ %d", `testbench.read_word[7:0], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge `testbench.clk);
end
endtask // uart_read_char
endmodule // uart_tasks
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_TB_V
`define SKY130_FD_SC_LS__A222O_TB_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_ls__a222o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_TB_V
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; while (a--) { int b, c; cin >> b >> c; int arr1[b], arr2[c]; set<int> check; for (int j = 0; j < b; j++) { cin >> arr1[j]; check.insert(arr1[j]); } int x = -1; for (int j = 0; j < c; j++) { cin >> arr2[j]; if (check.count(arr2[j])) x = arr2[j]; } if (x == -1) cout << NO n ; else { cout << YES n ; cout << 1 << << x << n ; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int x, y, z; long long int x1, y1, z1; cin >> x >> y >> z >> x1 >> y1 >> z1; long long int a[6]; for (long long int i = 0; i < 6; i++) cin >> a[i]; long long int sum = 0; if (y < 0) sum += a[0]; if (y > y1) sum += a[1]; if (x < 0) sum += a[4]; if (x > x1) sum += a[5]; if (z < 0) sum += a[2]; if (z > z1) sum += a[3]; cout << sum << n ; }
|
import "DPI-C" context function int init_socket();
import "DPI-C" context function void close_socket();
import "DPI-C" context function void senduart(input bit[7:0] in);
import "DPI-C" context function bit[8:0] recuart();
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
`ifdef DBGUART
init_socket();
`endif
end
final begin
`ifdef DBGUART
close_socket();
`endif
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_buf[8] && ~cs)
uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
senduart(bus_wr_val[7:0]);
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
if (bus_addr[3:0] == 4'b1100) begin
inter<=1'b1;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= (uart_buf[8] ? 32'b10 : 32'b0);
end
end
end
bus_ack <= cs;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXINT = 2147483647; const long long MAXLL = 9223372036854775807LL; const int MAX = 400000; long long n, q, col, pref[MAX], l, r, sum, ans, t[MAX]; string s; int main() { cin >> n >> q; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == 1 ) col++; pref[i] = col; } t[0] = 0; for (int i = 1; i <= 100005; i++) t[i] = (t[i - 1] + t[i - 1] + 1) % 1000000007; for (int i = 0; i < q; i++) { ans = 0, col = 0; cin >> l >> r; l--, r--; if (l == 0) sum = pref[r]; else sum = pref[r] - pref[l - 1]; if (t[r - l + 1] >= t[r - l + 1 - sum]) ans += t[r - l + 1] - t[r - l + 1 - sum]; else ans += t[r - l + 1] + 1000000007 - t[r - l + 1 - sum]; cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n); for (int i = 0; i < n; ++i) cin >> arr[i]; sort(arr.begin(), arr.end()); int i = 0, j = n - 1; vector<int> left; vector<int> right; while (i <= j) { right.push_back(arr[j--]); left.push_back(arr[i++]); } if ((arr.size() & 1) == 1) left.erase(left.begin() + left.size() - 1); int k = right.size() - 1; cout << k << n ; int p = 0; for (int i = 0; i < right.size(); i++) { cout << right[i] << ; if (p < left.size()) cout << left[p++] << ; } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
lpm_mult #(
.lpm_type ("lpm_mult"),
.lpm_widtha (A_DATA_WIDTH),
.lpm_widthb (B_DATA_WIDTH),
.lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH),
.lpm_representation ("SIGNED"),
.lpm_pipeline (3))
i_lpm_mult (
.clken (1'b1),
.aclr (1'b0),
.sclr (1'b0),
.sum (1'b0),
.clock (clk),
.dataa (data_a),
.datab (data_b),
.result (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long N = 1011; const long long INF = 5e16; namespace IO { inline long long read() { long long x = 0; bool f = 0; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) f ^= (ch == - ); for (; isdigit(ch); ch = getchar()) x = x * 10 + (ch ^ 48); return f ? -x : x; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 | 48); } inline void wrn(long long x) { write(x); putchar( ); } inline void wln(long long x) { write(x); putchar( n ); } inline void wlnn(long long x, long long y) { wrn(x); wln(y); } } // namespace IO using namespace IO; namespace Cesare { long long x, k, p; double Ans = 0, f[N][N]; int main() { x = read(), k = read(), p = read(); double Mul = p * 0.01, Add = 1.0 - Mul; for (register int i = 0; i <= k; ++i) for (register int j = x + i; !(j & 1); j >>= 1) ++f[0][i]; for (register int i = (1); i <= (k); ++i) for (register int j = (0); j <= (k); ++j) { if (j) f[i][j - 1] += f[i - 1][j] * Add; if (k >= (j << 1)) f[i][j << 1] += (f[i - 1][j] + 1) * Mul; } return printf( %.12lf n , f[k][0]), 0; } } // namespace Cesare int main() { return Cesare::main(); }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo_tb();
reg clk = 0;
reg rst = 1;
reg clear = 0;
initial #1000 rst = 0;
always #50 clk = ~clk;
reg [18:0] f19a;
wire [18:0] f19b, f19c, f19d;
wire [35:0] f36a, f36b;
reg f19a_sr = 0;
wire f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr;
wire f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr;
fifo_short #(.WIDTH(19)) fifo_short1
(.clk(clk),.reset(rst),.clear(clear),
.datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr),
.dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) );
fifo19_to_fifo36 fifo19_to_fifo36
(.clk(clk),.reset(rst),.clear(clear),
.f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr),
.f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) );
fifo_short #(.WIDTH(36)) fifo_short2
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr),
.dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) );
fifo36_to_fifo19 fifo36_to_fifo19
(.clk(clk),.reset(rst),.clear(clear),
.f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr),
.f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) );
fifo_short #(.WIDTH(19)) fifo_short3
(.clk(clk),.reset(rst),.clear(clear),
.datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr),
.dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) );
assign f19d_dr = 1;
always @(posedge clk)
if(f19a_sr & f19a_dr)
$display("18IN: %h", f19a);
always @(posedge clk)
if(f19d_sr & f19d_dr)
$display(" 18OUT: %h", f19d);
always @(posedge clk)
if(f36b_sr & f36b_dr)
$display(" 36: %h", f36b);
initial $dumpfile("fifo_tb.vcd");
initial $dumpvars(0,fifo_tb);
initial
begin
@(negedge rst);
@(posedge clk);
repeat (2)
begin
f19a <= 19'h1_AA01;
f19a_sr <= 1;
@(posedge clk);
f19a <= 19'h0_AA02;
repeat (4)
begin
@(posedge clk);
f19a <= f19a + 1;
end
f19a[18:16] <= 3'b010;
@(posedge clk);
f19a_sr <= 0;
f19a <= 19'h7_FFFF;
@(posedge clk);
end
#20000 $finish;
end
endmodule // longfifo_tb
|
`define AUTO_NBR_A_INST 2
module autoinst_crawford_array(/*AUTOARG*/
// Outputs
a_valid, a_data,
// Inputs
a_ready, clk, rst_n
);
// a interface
output [`AUTO_NBR_A_INST*1-1:0] a_valid;
output [`AUTO_NBR_A_INST*8-1:0] a_data;
input [`AUTO_NBR_A_INST*1-1:0] a_ready;
// clock interface
input clk;
input rst_n;
/*AUTOWIRE*/
// non-arrayed example
autoinst_crawford_array_a auto_a_0
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a auto_a_1
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
// Arrayed instances
// AUTOINST does not work for this one :-(
// Note it is tricky because I want clk and rst_n to fanout to both instances,
// but I want the valid signals to be discreatly tied to each submodule.
//autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
// (/*XXXAUTOINST*/
// // Outputs
// .a_valid (a_valid[1:0]),
// .a_data (a_data[15:0]),
// // Inputs
// .a_ready (a_ready[1:0]),
// .clk (clk),
// .rst_n (rst_n));
autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a #(.a(a),b) par [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sie_read O 64
// mav_sie_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sie_write_misa I 28
// mav_sie_write_wordxl I 64
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sie_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sie_write_misa, mav_sie_write_wordxl) -> mav_sie_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sie_read,
mav_sie_write_misa,
mav_sie_write_wordxl,
EN_mav_sie_write,
mav_sie_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sie_read
output [63 : 0] mv_sie_read;
// actionvalue method mav_sie_write
input [27 : 0] mav_sie_write_misa;
input [63 : 0] mav_sie_write_wordxl;
input EN_mav_sie_write;
output [63 : 0] mav_sie_write;
// signals for module outputs
wire [63 : 0] mav_sie_write, mav_write, mv_read, mv_sie_read;
// register rg_mie
reg [11 : 0] rg_mie;
reg [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_sie_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_sie_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
wire [11 : 0] MUX_rg_mie$write_1__VAL_3;
// remaining internal signals
wire [11 : 0] mie__h92, x__h467, x__h901;
wire seie__h132,
seie__h562,
ssie__h126,
ssie__h556,
stie__h129,
stie__h559,
ueie__h131,
ueie__h561,
usie__h125,
usie__h555,
utie__h128,
utie__h558;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h92 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sie_read
assign mv_sie_read = { 52'd0, x__h467 } ;
// actionvalue method mav_sie_write
assign mav_sie_write = { 52'd0, x__h901 } ;
assign CAN_FIRE_mav_sie_write = 1'd1 ;
assign WILL_FIRE_mav_sie_write = EN_mav_sie_write ;
// inputs to muxes for submodule ports
assign MUX_rg_mie$write_1__VAL_3 =
{ rg_mie[11],
1'b0,
seie__h562,
ueie__h561,
rg_mie[7],
1'b0,
stie__h559,
utie__h558,
rg_mie[3],
1'b0,
ssie__h556,
usie__h555 } ;
// register rg_mie
always@(EN_mav_write or
mie__h92 or
EN_reset or EN_mav_sie_write or MUX_rg_mie$write_1__VAL_3)
case (1'b1)
EN_mav_write: rg_mie$D_IN = mie__h92;
EN_reset: rg_mie$D_IN = 12'd0;
EN_mav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3;
default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ;
endcase
assign rg_mie$EN = EN_mav_write || EN_mav_sie_write || EN_reset ;
// remaining internal signals
assign mie__h92 =
{ mav_write_wordxl[11],
1'b0,
seie__h132,
ueie__h131,
mav_write_wordxl[7],
1'b0,
stie__h129,
utie__h128,
mav_write_wordxl[3],
1'b0,
ssie__h126,
usie__h125 } ;
assign seie__h132 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign seie__h562 = mav_sie_write_misa[18] && mav_sie_write_wordxl[9] ;
assign ssie__h126 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssie__h556 = mav_sie_write_misa[18] && mav_sie_write_wordxl[1] ;
assign stie__h129 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign stie__h559 = mav_sie_write_misa[18] && mav_sie_write_wordxl[5] ;
assign ueie__h131 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueie__h561 = mav_sie_write_misa[13] && mav_sie_write_wordxl[8] ;
assign usie__h125 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usie__h555 = mav_sie_write_misa[13] && mav_sie_write_wordxl[0] ;
assign utie__h128 = mav_write_misa[13] && mav_write_wordxl[4] ;
assign utie__h558 = mav_sie_write_misa[13] && mav_sie_write_wordxl[4] ;
assign x__h467 =
{ 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ;
assign x__h901 =
{ 2'd0,
seie__h562,
ueie__h561,
2'd0,
stie__h559,
utie__h558,
2'd0,
ssie__h556,
usie__h555 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; int main() { ios::sync_with_stdio(false); long long int MOD = 1000000007LL; string start, end; int k; while (cin >> start >> end >> k) { const int N = static_cast<int>(start.size()); pair<long long int, long long int> dp(make_pair(1LL, 0LL)); for (int i = 0; i < k; ++i) { pair<long long int, long long int> next; next.first = (dp.second * (N - 1)) % MOD; next.second = (dp.first + dp.second * (N - 2)) % MOD; swap(dp, next); } long long int ans = 0LL; if (start == end) ans += dp.first; for (int i = 1; i < N; ++i) { if (start.substr(i) + start.substr(0, i) == end) { ans += dp.second; ans %= MOD; } } cout << ans << endl; } return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/15/2015 08:47:07 AM
// Design Name:
// Module Name: SerialServo
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
input wire clk100MHz,
input wire clk1MHz,
input wire rst,
input wire ext_clk,
input wire ext_flush,
input wire serial,
input wire [CHANNEL_WIDTH-1:0] channel,
output wire pwm
*/
module SerialServo(
input wire clk100MHz,
input wire clk1MHz,
input wire rst,
input wire ext_clk,
input wire ext_flush,
input wire serial,
input wire [CHANNEL_WIDTH-1:0] channel,
output reg pwm
);
parameter POSITION_WIDTH = 11;
parameter CHANNEL_WIDTH = 5;
parameter BUFFER_LENGTH = 16;
reg [BUFFER_LENGTH-1:0] buffer;
reg [CHANNEL_WIDTH-1:0] channel_select;
reg [POSITION_WIDTH-1:0] position;
reg [CHANNEL_WIDTH-1:0] ser_channel;
reg [POSITION_WIDTH-1:0] ser_pos;
wire clk;
wire flush;
ExtToIntSync U0(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_clk),
.int_signal(clk)
);
ExtToIntSync U1(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_flush),
.int_signal(flush)
);
AngleToPWM U2 (
.pos(position),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(empty)
);
integer ptr;
always @(posedge clk or posedge rst) begin
if(rst) begin
position = 0;
buffer = 0;
ptr = 0;
end
else if(!flush) begin
if(ptr < 15) begin
buffer[(BUFFER_LENGTH-1)-ptr] = serial;
ptr = ptr + 1;
end
else begin
// Channel Select: 15th-11th bit (5 bit width)
channel_select = buffer[BUFFER_LENGTH-1:BUFFER_LENGTH-5];
// Position: 11th-0th bit (11 bit width)
position = buffer[BUFFER_LENGTH-6:0];
// Write to position file @ channel select point
// Make position a 11 bit signal and OR a 1 with it.
//position_file[channel_select] = (position << 1) | 1'b1;
ser_pos = position;
pwm = ext_clk;
//ser_pos = position;
ser_channel = channel_select;
// Reset buffer and ptr
buffer = 0;
ptr = 0;
end
end
else begin
position = 0;
buffer = 0;
ptr = 0;
end
end
endmodule
/*
parameter POSITION_WIDTH = 11;
parameter CHANNEL_WIDTH = 5;
parameter BUFFER_LENGTH = 16;
reg [BUFFER_LENGTH-1:0] buffer;
reg [CHANNEL_WIDTH-1:0] channel_select;
reg [POSITION_WIDTH-1:0] position;
wire clk;
wire flush;
wire empty;
assign pwm = position[0];
ExtToIntSync U0(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_clk),
.int_signal(clk)
);
ExtToIntSync U1(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_flush),
.int_signal(flush)
);
AngleToPWM U2 (
.pos(position),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(empty)
);
integer ptr;
//reg [2:0] state;
// parameter LISTENING = 0;
// parameter READING_SERIAL = 1;
// parameter SKIP = 2;
always @(posedge clk or posedge rst) begin
if(rst) begin
position = 1500;
buffer = 0;
ptr = 0;
end
else if(!flush) begin
if(ptr < 15) begin
buffer[(BUFFER_LENGTH-1)-ptr] = serial;
ptr = ptr + 1;
end
else begin
// Channel Select: 15th-11th bit (5 bit width)
channel_select = buffer[BUFFER_LENGTH-1:BUFFER_LENGTH-5];
// Position: 11th-0th bit (11 bit width)
if(channel_select == channel) begin
position = buffer[BUFFER_LENGTH-6:0];
end
// Reset buffer and ptr
buffer = 0;
ptr = 0;
end
end
else begin
position = 1500;
buffer = 0;
ptr = 0;
end
end
*/
// if(rst) begin
// position = 1500;
// buffer = 0;
// ptr = 0;
// state = 0;
// end
// else if(!flush) begin
// case(state)
// LISTENING: begin
// if(ptr < 5) begin
// buffer[(BUFFER_LENGTH-1)-ptr] = serial;
// end
// else begin
// buffer[(BUFFER_LENGTH-1)-ptr] = serial;
// // Channel Select: 15th-11th bit (5 bit width)
// channel_select = buffer[BUFFER_LENGTH-1:BUFFER_LENGTH-5];
// if(channel_select == channel) begin
// state = READING_SERIAL;
// end
// else begin
// state = SKIP;
// end
// end
// ptr = ptr + 1;
// end
// READING_SERIAL: begin
// if(ptr < 15) begin
// buffer[(BUFFER_LENGTH-1)-ptr] = serial;
// ptr = ptr + 1;
// end
// else begin
// buffer[(BUFFER_LENGTH-1)-ptr] = serial;
// // Position: 11th-0th bit (11 bit width)
// position = buffer[BUFFER_LENGTH-6:0];
// // Reset buffer and ptr
// buffer = 0;
// ptr = 0;
// state = LISTENING;
// end
// end
// SKIP: begin
// if(ptr == 15) begin
// buffer = 0;
// ptr = 0;
// state = LISTENING;
// end
// else begin
// ptr = ptr + 1;
// end
// end
// default: state = LISTENING;
// endcase
// end
// else begin
// position = 0;
// buffer = 0;
// ptr = 0;
// end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_BEHAVIORAL_PP_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module wb_bridge_16_32
#(parameter AWIDTH=16)
(input wb_clk, input wb_rst,
input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i,
input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o,
output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o,
output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i
);
reg [15:0] holding;
reg phase;
assign B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0};
assign B_cyc_o = A_cyc_i;
assign B_stb_o = A_stb_i;
assign B_we_o = A_we_i;
assign B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16];
assign B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2];
assign A_dat_o = {B_dat_i,holding};
assign A_ack_o = phase & B_ack_i;
always @(posedge wb_clk)
if(wb_rst)
phase <= 0;
else if(B_ack_i)
phase <= ~phase;
always @(posedge wb_clk)
if(~phase & B_ack_i)
holding <= B_dat_i;
endmodule // wb_bridge_16_32
|
#include <bits/stdc++.h> using namespace std; int32_t main() { int n, h; cin >> n >> h; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; int lo = 0; int hi = n - 1; int ans, mid; while (lo <= hi) { mid = lo + (hi - lo) / 2; vector<int> a(mid + 1); for (int i = 0; i < mid + 1; i++) a[i] = v[i]; sort(a.begin(), a.end()); int c = 0; int j = mid; int leftheight = h; while (j >= 0 && leftheight > 0) { if (a[j] <= leftheight) { leftheight -= a[j]; if (mid % 2 == 0 && j == 0) { c++; break; } else { j -= 2; c += 2; } } else break; } if (c >= (mid + 1)) { lo = mid + 1; ans = mid; } else hi = mid - 1; } cout << ans + 1 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_4_V
`define SKY130_FD_SC_HD__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 10050; const int D = 600050; const int M = 8000050; const int INF = 20000000; int s, t, nds; namespace Maxflow { int dis[D], q[M * 2], f, r, tot = 1; int head[D], to[M], nex[M], fl[M], now[D]; void addedge(int u, int v, int f) { tot++; to[tot] = v, nex[tot] = head[u], head[u] = tot, fl[tot] = f; tot++; to[tot] = u, nex[tot] = head[v], head[v] = tot, fl[tot] = 0; } bool spfa() { int i, j; q[f = r = 1] = s; for (i = 2; i <= nds; i++) dis[i] = INF; while (f <= r) { j = q[f++]; for (i = head[j]; i; i = nex[i]) { if (fl[i] && dis[to[i]] > dis[j] + 1) { dis[to[i]] = dis[j] + 1; q[++r] = to[i]; } } } return dis[t] != INF; } int dinic(int x, int flow) { if (x == t) return flow; for (int i = now[x]; i; now[x] = i = nex[i]) { if (fl[i] && dis[x] + 1 == dis[to[i]]) { int tmp = dinic(to[i], min(fl[i], flow)); if (tmp != 0) { fl[i] -= tmp; fl[i ^ 1] += tmp; return tmp; } } } return 0; } int maxflow() { int i, j, ans = 0; while (spfa()) { for (i = 1; i <= nds; i++) now[i] = head[i]; int tmp = 0; while (tmp = dinic(s, INF)) ans += tmp; } return ans; } } // namespace Maxflow using Maxflow ::addedge; int lc[M], rc[M], root[2 * N], typ; void build(int &p, int l, int r) { p = ++nds; if (l == r) { addedge(p, 2 + l, INF); return; } int md = l + r >> 1; build(lc[p], l, md); build(rc[p], md + 1, r); addedge(p, lc[p], INF); addedge(p, rc[p], INF); } void add(int &p, int las, int one, int l, int r, int x, int y) { p = ++nds; if (l == x && r == y) { if (typ == -1) { if (x == y) addedge(p, 2 + x, INF); else { lc[p] = lc[one]; rc[p] = rc[one]; addedge(p, lc[p], INF); addedge(p, rc[p], INF); } } return; } lc[p] = lc[las]; rc[p] = rc[las]; int md = l + r >> 1; if (y <= md) add(lc[p], lc[las], lc[one], l, md, x, y); else if (x > md) add(rc[p], rc[las], rc[one], md + 1, r, x, y); else { add(lc[p], lc[las], lc[one], l, md, x, md); add(rc[p], rc[las], rc[one], md + 1, r, md + 1, y); } addedge(p, lc[p], INF); addedge(p, rc[p], INF); } namespace io { const int L = (1 << 19) + 1; char ibuf[L], *iS, *iT, c; int f; inline char gc() { if (iS == iT) { iT = (iS = ibuf) + fread(ibuf, 1, L, stdin); return iS == iT ? EOF : *iS++; } return *iS++; } template <class I> void read(I &x) { for (f = 1, c = gc(); c < 0 || c > 9 ; c = gc()) if (c == - ) f = -1; for (x = 0; c <= 9 && c >= 0 ; c = gc()) x = x * 10 + (c & 15); x *= f; } }; // namespace io using io ::read; struct line { int dw, up, typ, x; line(int xx = 0, int y1 = 0, int y2 = 0, int tp = 0) { x = xx; dw = y1; up = y2; typ = tp; } inline bool operator<(const line &b) const { if (x == b.x) return typ < b.typ; return x < b.x; } } a[2 * N]; int n, m; int main() { int i, j, k, p, q; s = 1, read(n), read(m); t = 2, nds = 2 + n; build(root[0], 1, n); for (i = 1; i <= m; i++) { read(j), read(k), read(p), read(q); a[2 * i - 1] = line(k, j, p, 1); a[2 * i] = line(q + 1, j, p, -1); } sort(a + 1, a + 2 * m + 1); for (i = j = 1; i <= n; i++) { while (j <= 2 * m && a[j].x == i) typ = a[j].typ, add(root[j], root[j - 1], root[0], 1, n, a[j].dw, a[j].up), j++; addedge(2 + i, t, 1), addedge(s, root[j - 1], 1); } printf( %d n , Maxflow ::maxflow()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795l; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T> inline T abs(T x) { return x > T() ? x : -x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } const int N = 100100; struct Input { int n; vector<pair<int, int> > a[N]; int len[N]; int num[N], w[N]; int q; bool read() { if (scanf( %d , &n) != 1) return 0; for (int i = 0; i < int(n - 1); ++i) { int u, v; scanf( %d %d %d , &u, &v, &len[i]); u--, v--; a[u].push_back(make_pair(v, i)); a[v].push_back(make_pair(u, i)); } cin >> q; for (int i = 0; i < int(q); ++i) { scanf( %d %d , &num[i], &w[i]); num[i]--; } return 1; } void init(const Input& input) { *this = input; } }; struct Data : Input { long double ans[N]; void write() { for (int i = 0; i < int(q); ++i) { printf( %0.15lf n , (double)ans[i]); } } virtual void solve() {} virtual void clear() { *this = Data(); } }; struct Solution : Data { int sz[N]; int kol[N]; bool use[N]; int dfs(int v, int idx = -1) { use[v] = 1; sz[v] = 1; for (int i = 0; i < int(a[v].size()); ++i) { int to = a[v][i].first; if (use[to]) continue; sz[v] += dfs(to, a[v][i].second); } if (idx >= 0) kol[idx] = sz[v]; return sz[v]; } inline long double c(int a, int b) { if (a < b) return 0; if (b == 0) return 1; if (b == 1) return a; if (b == 2) { return (long double)a * (a - 1) / 2.0; } return (long double)a * (a - 1) * (a - 2) / 6.0; } inline long double get(int i) { return 2.0 * (long double)kol[i] * c((n - kol[i]), 2) + 2.0 * (long double)(n - kol[i]) * c(kol[i], 2); } void solve() { dfs(0); long double res = 0; for (int i = 0; i < int(n - 1); ++i) { res += get(i) * len[i]; } for (int i = 0; i < int(q); ++i) { res -= get(num[i]) * len[num[i]]; len[num[i]] = w[i]; res += get(num[i]) * len[num[i]]; ans[i] = res / c(n, 3); } } void clear() { *this = Solution(); } }; Solution sol; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); sol.read(); sol.solve(); sol.write(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; struct node { char s[10]; int len, i, v, num, ty; } p[N], q[3][N]; int n, vst[N], tot = 0, s[3] = {0}; int f[3][N] = {0}; struct data { char s[10]; int ty, c[2], len; } ans[N]; int F(char s[10]) { int i, ad = 0; for (i = 0; i < strlen(s); i++) { if (s[i] < 0 || s[i] > 9 ) return 0; if (ad == 0 && s[i] == 0 ) return 0; ad = ad * 10 + s[i] - 0 ; } return ad; } int main() { scanf( %d , &n); int i, j, k, t, n1 = 0, n2; for (i = 1; i <= n; i++) { scanf( %s%d , p[i].s, &p[i].v); p[i].len = strlen(p[i].s); p[i].num = F(p[i].s); n1 += p[i].v; } n2 = n - n1; for (i = 1; i <= n; i++) if (p[i].num && p[i].num <= n) { vst[p[i].num] = 1; if ((p[i].v && p[i].num <= n1) || (!p[i].v && p[i].num > n1)) p[i].ty = 3; else { if (p[i].v) p[i].ty = 2, q[2][++s[2]] = p[i]; else p[i].ty = 1, q[1][++s[1]] = p[i]; } } else p[i].ty = 0, q[0][++s[0]] = p[i]; for (i = 1; i <= n1; i++) if (!vst[i]) f[1][++f[1][0]] = i; for (i = n1 + 1; i <= n; i++) if (!vst[i]) f[2][++f[2][0]] = i; while (s[1] + s[2]) { if (f[1][0] + f[2][0]) { if (f[1][0] && s[2]) k = 1, t = 2; else k = 2, t = 1; ans[++tot].ty = 1; ans[tot].c[0] = q[t][s[t]].num; ans[tot].c[1] = f[k][f[k][0]]; f[t][++f[t][0]] = q[t][s[t]].num; f[k][0]--; s[t]--; } else { if (s[1]) k = 2; else k = 1; ans[++tot].ty = 1; ans[tot].c[0] = q[k][s[k]].num; ans[tot].c[1] = 999999; f[k][++f[k][0]] = q[k][s[k]].num; q[0][++s[0]] = q[k][s[k]]; q[0][s[0]].ty = q[0][s[0]].num = 0; q[0][s[0]].len = 6; for (t = 0; t < 6; t++) q[0][s[0]].s[t] = 9 ; s[k]--; } } while (s[0]) { k = 2 - q[0][s[0]].v; ans[++tot].ty = 2; ans[tot].len = q[0][s[0]].len; for (t = 0; t < ans[tot].len; t++) ans[tot].s[t] = q[0][s[0]].s[t]; ans[tot].c[0] = f[k][f[k][0]]; s[0]--; f[k][0]--; } printf( %d n , tot); for (i = 1; i <= tot; i++) { if (ans[i].ty == 1) printf( move %d %d n , ans[i].c[0], ans[i].c[1]); else { printf( move ); for (t = 0; t < ans[i].len; t++) printf( %c , ans[i].s[t]); printf( %d n , ans[i].c[0]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, f, a, b; vector<long long> V; long long ans; int main() { scanf( %lld %lld , &n, &f); for (int i = 1; i <= n; i++) { scanf( %lld %lld , &a, &b); if (a >= b) { V.push_back(0); ans += b; } else { if (a * 2 <= b) { V.push_back(a); } else { V.push_back(b - a); } ans += a; } } sort(V.begin(), V.end()); reverse(V.begin(), V.end()); for (int i = 0; i < f; i++) { ans += V[i]; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const int inf = 1e9 + 7; const int md = 1e9 + 7; const double eps = -1e5; using namespace std; int n, ans, x, y; bool a[1001][1001]; bool isin(int x, int y) { return x > 0 && x <= 1000 && y > 0 && y <= 1000; } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; a[x][y] = true; } for (int x = 1; x <= 1000; x++) for (int y = 1; y <= 1000; y++) if (a[x][y]) { for (int xx = x, yy = y; isin(xx, yy); xx--, yy--) ans += a[xx][yy]; ans--; for (int xx = x, yy = y; isin(xx, yy); xx++, yy--) ans += a[xx][yy]; ans--; for (int xx = x, yy = y; isin(xx, yy); xx--, yy++) ans += a[xx][yy]; ans--; for (int xx = x, yy = y; isin(xx, yy); xx++, yy++) ans += a[xx][yy]; ans--; } cout << ans / 2; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_SYMBOL_V
`define SKY130_FD_SC_MS__OR2B_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int dx4[] = {0, 0, +1, -1}; int dy4[] = {+1, -1, 0, 0}; int dx8[] = {+1, 0, -1, 0, +1, +1, -1, -1}; int dy8[] = {0, +1, 0, -1, +1, -1, +1, -1}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline bool isIntege(double num) { return (num == (int)num); } inline bool collinear(int x1, int y1, int x2, int y2, int x3, int y3) { return (y1 - y2) * (x1 - x3) == (y1 - y3) * (x1 - x2); } inline double coDist(double x1, double y1, double x2, double y2) { return sqrt(((x1 - x2) * (x1 - x2)) + ((y1 - y2) * (y1 - y2))); } inline double TriangleAreaWithSide(double a, double b, double c) { double s = (a + b + c) / 2; double area = sqrt(s * (s - a) * (s - b) * (s - c)); return area; } inline double area3(double x1, double y1, double x2, double y2, double x3, double y3) { double A = abs((x1 * y2 + x2 * y3 + x3 * y1) - (y1 * x2 + y2 * x3 + y3 * x1)); A /= 2.0; return A; } inline long double degreetoradian(long double x) { long double val = PI * x; val /= (180.0); return val; } inline void normal(long long &a) { a %= 1000000007; (a < 0) && (a += 1000000007); } template <typename T> inline T gcd(T a, T b) { T c; while (b) { c = b; b = a % b; a = c; } return a; } inline long long modMul(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a * b) % 1000000007; } inline long long modAdd(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a + b) % 1000000007; } inline long long modSub(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, 1000000007 - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } inline bool equalTo(double a, double b) { if (fabs(a - b) <= eps) return true; else return false; } inline bool notEqual(double a, double b) { if (fabs(a - b) > eps) return true; else return false; } inline bool lessThan(double a, double b) { if (a + eps < b) return true; else return false; } inline bool lessThanEqual(double a, double b) { if (a < b + eps) return true; else return false; } inline bool greaterThan(double a, double b) { if (a > b + eps) return true; else return false; } inline bool greaterThanEqual(double a, double b) { if (a + eps > b) return true; else return false; } inline string to_s(int t) { stringstream ss; ss << t; return ss.str(); } struct edge { int p, q, w; }; bool cmp(edge &a, edge &b) { return a.w < b.w; } template <typename first, typename second> ostream &operator<<(ostream &os, const pair<first, second> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename T> ostream &operator<<(ostream &os, const multiset<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename first, typename second> ostream &operator<<(ostream &os, const map<first, second> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } clock_t tStart = clock(); void faltu() { cerr << n ; } template <typename T> void faltu(T a[], int n) { for (int i = 0; i < n; ++i) cerr << a[i] << ; cerr << n ; } template <typename T, typename... hello> void faltu(T arg, const hello &...rest) { cerr << arg << ; faltu(rest...); } const int mx = 1e5 + 5; bool cnt[mx]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, k; cin >> n >> k; long long g; cin >> g; for (int i = 1; i < n; i++) { long long x; cin >> x; g = gcd(x, g); } vector<long long> st; for (long long i = 0, j = 0; i < k; i++, j += g) { int z = j % k; if (!cnt[z]) st.emplace_back(z), cnt[z] = 1; } cout << st.size() << n ; for (int i = 0; i < k; i++) { if (cnt[i]) cout << i << ; } }
|
#include <bits/stdc++.h> const int N = 1000005; int fa[N], h[N], nxt[N], adj[N], a[N], u, v, t, id[N], Id, ans[N], f[N], n, tot, m; inline int fd(register int x) { return fa[x] == x ? x : fa[x] = fd(fa[x]); } inline void add() { nxt[++t] = h[u], h[u] = t, adj[t] = v, id[t] = Id, nxt[++t] = h[v], h[v] = t, adj[t] = u, id[t] = Id; } inline void mer() { register int t1 = fd(u), t2 = fd(v); if (t1 != t2) fa[t1] = t2, add(); } inline void dfs(register int x) { for (register int i = h[x], j; i; i = nxt[i]) if ((j = adj[i]) != f[x]) f[j] = x, dfs(j), a[x] += a[j], ans[id[i]] = (i & 1 ? a[j] : -a[j]); } inline void fr(int &num) { num = 0; char c = getchar(); int p = 1; while (c < 0 || c > 9 ) c == - ? p = -1, c = getchar() : c = getchar(); while (c >= 0 && c <= 9 ) num = num * 10 + c - 0 , c = getchar(); num *= p; } int main() { fr(n); for (register int i = 1; i <= n; ++i) fr(a[i]), tot += a[i], fa[i] = i; if (tot) return puts( Impossible ), 0; puts( Possible ); fr(m); for (Id = 1; Id <= m; ++Id) fr(u), fr(v), mer(); dfs(1); for (register int i = 1; i <= m; ++i) printf( %d n , ans[i]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/06/2014 01:08:23 PM
// Design Name:
// Module Name: seg_scroll_QU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Seg_Scroll_QU(
input clk,
input clr,
input [19:0] scroll_datain_QU,
output [15:0] scroll_dataout_QU
);
reg [26:0] q;
reg [23:0] msg_array;
always @(posedge clk_3 or posedge clr)
begin
if(clr==1)
begin
msg_array [19:0] <= scroll_datain_QU[19:0];
msg_array [23:20] <= 'hC;
end
else
begin
msg_array [19:0] <= msg_array[23:4];
msg_array [23:20] <= msg_array[3:0];
end
end
assign scroll_dataout_QU[15:0] = msg_array[15:0];
// 3 Hz scroll clk generator
always @(posedge clk or posedge clr)
begin
if(clr==1)
q<=0;
else
q<=q+1;
end
assign clk_3 = q[26];
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_mux.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: The limit block and the _po_cntlr block both manipulate
// the phaser out and the POC. This block muxes those commands
// together, and encapsulates logic required for meeting phaser
// setup and wait times.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_mux #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy,
po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel,
po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req,
// Inputs
clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right,
lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec,
lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec,
ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt,
oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam PO_WAIT = 15;
localparam POW_WIDTH = clogb2(PO_WAIT);
localparam ONE = 1;
localparam TWO = 2;
input clk;
input rst;
input ocd_ktap_right, ocd_ktap_left;
input lim2poc_ktap_right;
output ktap_at_left_edge, ktap_at_right_edge;
assign ktap_at_left_edge = ocd_ktap_left;
assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right;
input lim2poc_rdy;
input ocd_edge_detect_rdy;
output mmcm_edge_detect_rdy;
assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy;
// po_stg3_incdec and po_en_stg3 are deprecated and should be removed.
output po_stg3_incdec;
output po_en_stg3;
assign po_stg3_incdec = 1'b0;
assign po_en_stg3 = 1'b0;
reg [1:0] po_setup_ns, po_setup_r;
always @(posedge clk) po_setup_r <= #TCQ po_setup_ns;
input lim2stg2_inc;
input lim2stg2_dec;
input lim2stg3_inc;
input lim2stg3_dec;
input ocd2stg2_inc;
input ocd2stg2_dec;
input ocd_cntlr2stg2_dec;
input ocd2stg3_inc;
input ocd2stg3_dec;
wire setup_po =
lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec ||
ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec;
always @(*) begin
po_setup_ns = po_setup_r;
if (rst) po_setup_ns = 2'b00;
else if (setup_po) po_setup_ns = 2'b11;
else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01;
end
reg po_en_stg23_r;
wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01;
always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns;
output po_en_stg23;
assign po_en_stg23 = po_en_stg23_r;
wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec;
reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns;
reg po_stg23_sel_r;
// Reset to zero at the end. Makes adjust stg2 at end of centering
// get the correct value of po_counter_read_val.
wire po_stg23_sel_ns = ~rst && (setup_po
? sel_stg3
? 1'b1
: 1'b0
: po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0]));
always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns;
output po_stg23_sel;
assign po_stg23_sel = po_stg23_sel_r;
wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc;
reg po_stg23_incdec_r;
wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r);
always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns;
output po_stg23_incdec;
assign po_stg23_incdec = po_stg23_incdec_r;
always @(posedge clk) po_wait_r <= #TCQ po_wait_ns;
always @(*) begin
po_wait_ns = po_wait_r;
if (rst) po_wait_ns = {POW_WIDTH{1'b0}};
else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0];
else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0];
end
wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns);
reg po_rdy_r;
always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns;
output po_rdy;
assign po_rdy = po_rdy_r;
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6;
output [5:0] wl_po_fine_cnt_sel;
assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0];
input lim2init_prech_req;
input ocd_prech_req;
output oclk_prech_req;
assign oclk_prech_req = ocd_prech_req || lim2init_prech_req;
endmodule // mig_7series_v4_0_ddr_phy_ocd_mux
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:49:39 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_0_stub.v
// Design : gcd_block_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const long long INF = 1e17 + 7; const int N = 1e4 + 7; const int M = 5e6 + 7; long long x[N], y[N]; long long ax, ay, bx, by, a, b, t; signed main() { ios::sync_with_stdio(false); cin >> x[0] >> y[0] >> ax >> ay >> bx >> by; int n = 0; for (; x[n] < INF && y[n] < INF; n++) { x[n + 1] = x[n] * ax + bx; y[n + 1] = y[n] * ay + by; if (x[n + 1] >= INF || y[n + 1] >= INF) break; } cin >> a >> b >> t; long long ans = 0; for (int l = 0; l <= n; l++) { for (int r = l; r <= n; r++) { unsigned long long to = min(abs(a - x[l]) + abs(b - y[l]), abs(a - x[r]) + abs(b - y[r])); to += abs(x[l] - x[r]) + abs(y[l] - y[r]); if (to <= t) ans = max(ans, r - l + 1ll); } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:24:03 06/11/2014
// Design Name:
// Module Name: Valid_Monitor
// Project Name:
// Target Devices:
// Tool versions:
// Description: 1. Snooping the state of valid bits of every entry in Reserve station.
// 2. Output the first free entry ID(i.e.,FE_ID) of the RS.
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Valid_Monitor(clk, rst_n, Valid, FE_ID);
input clk;
input rst_n;
input [7:0] Valid;
output reg [3:0] FE_ID; //the first empty RS
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
FE_ID <= 4'h0;
end
else
begin
casex(Valid)
8'bxxxx_xxx1:begin
FE_ID <= 4'h1;
end
8'bxxxx_xx10:begin
FE_ID <= 4'h2;
end
8'bxxxx_x100:begin
FE_ID <= 4'h3;
end
8'bxxxx_1000:begin
FE_ID <= 4'h4;
end
8'bxxx1_0000:begin
FE_ID <= 4'h5;
end
8'bxx10_0000:begin
FE_ID <= 4'h6;
end
8'bx100_0000:begin
FE_ID <= 4'h7;
end
8'b1000_0000:begin
FE_ID <= 4'h8;
end
default:begin
FE_ID <= 4'h0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3010; int n; struct edge { int ne, to; edge(int N = 0, int T = 0) : ne(N), to(T) {} } e[MAXN << 1]; int fir[MAXN], num = 0; inline void join(int a, int b) { e[++num] = edge(fir[a], b); fir[a] = num; } int pa[MAXN][MAXN], siz[MAXN][MAXN]; void pre(int u, int fa, const int rt) { siz[rt][u] = 1; pa[rt][u] = fa; for (int i = fir[u]; i; i = e[i].ne) { int v = e[i].to; if (v == fa) continue; pre(v, u, rt); siz[rt][u] += siz[rt][v]; } } long long f[MAXN][MAXN]; long long dfs(int u, int v) { if (u == v) return 0ll; if (f[u][v]) return f[u][v]; return f[u][v] = max(dfs(u, pa[u][v]), dfs(pa[v][u], v)) + 1ll * siz[v][u] * siz[u][v]; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); join(u, v); join(v, u); } for (int i = 1; i <= n; i++) pre(i, 0, i); long long ans = 0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) ans = max(ans, dfs(i, j)); printf( %lld n , ans); return 0; }
|
// $Id: c_mat_mult.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// matrix multiplication
//==============================================================================
module c_mat_mult
(input_a, input_b, result);
`include "c_constants.v"
// matrix dimensions
parameter dim1_width = 1;
parameter dim2_width = 1;
parameter dim3_width = 1;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_XOR;
// first input matrix
input [0:dim1_width*dim2_width-1] input_a;
// second input matrix
input [0:dim2_width*dim3_width-1] input_b;
output [0:dim1_width*dim3_width-1] result;
wire [0:dim1_width*dim3_width-1] result;
generate
genvar row;
for(row = 0; row < dim1_width; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < dim3_width; col = col + 1)
begin:cols
wire [0:dim2_width-1] products;
genvar idx;
for(idx = 0; idx < dim2_width; idx = idx + 1)
begin:idxs
c_binary_op
#(.num_ports(2),
.width(1),
.op(prod_op))
prod
(.data_in({input_a[row*dim2_width+idx],
input_b[idx*dim3_width+col]}),
.data_out(products[idx]));
end
c_binary_op
#(.num_ports(dim2_width),
.width(1),
.op(sum_op))
sum
(.data_in(products),
.data_out(result[row*dim3_width+col]));
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char ara[55][55]; bool ok(int i, int j) { if (i >= n || j < 0 || j >= n) return false; if (ara[i][j] == # ) return false; return true; } int main() { while (cin >> n) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> ara[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ara[i][j] == . ) { if (ok(i + 1, j) && ok(i + 1, j - 1) && ok(i + 1, j + 1) && ok(i + 2, j)) { ara[i][j] = ara[i + 1][j] = ara[i + 1][j - 1] = ara[i + 1][j + 1] = ara[i + 2][j] = # ; } } } } bool flag = true; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ara[i][j] == . ) { flag = false; } } } cout << (flag ? YES n : NO n ); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; stringstream output; inline void eOP(); inline void solve() { int n, x, y; cin >> n >> x >> y; string s; cin >> s; char p = 1 ; long long cnt = 0; for (char c : s) { if (p == 1 && c == 0 ) { ++cnt; } p = c; } long long result = 0; if (cnt) { result += y; --cnt; } result += cnt * (min(x, y)); output << result; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); size_t t = 1; for (int i = 0; i < t; ++i) { solve(); } eOP(); } inline void eOP() { cout << output.str(); output.str(string()); exit(0); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_1_V
`define SKY130_FD_SC_LP__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_1_V
|
#include <bits/stdc++.h> void read(int& x) { x = 0; char c; do { c = getchar(); } while (c < 0 || c > 9 ); while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } } using namespace std; int n, m, f[1000 + 5][1000 + 5], ans, sum[1000 + 5]; int s[100000 + 5][3], as[100000 + 5]; vector<int> v[100000 + 5]; void place(int x, int y) { f[x][y] = !f[x][y]; ans++; sum[x]++; } void remove(int x, int y) { f[x][y] = !f[x][y]; ans--; sum[x]--; } void invert(int x) { f[x][0] = !f[x][0]; ans -= sum[x]; sum[x] = m - sum[x]; ans += sum[x]; } void dfs(int k) { int o = 0, t, x, y, i; t = s[k][0]; x = s[k][1]; y = s[k][2]; if (t == 1) if (f[x][y] ^ f[x][0] ^ 1) place(x, y); else o = 1; if (t == 2) if (f[x][y] ^ f[x][0]) remove(x, y); else o = 1; if (t == 3) invert(x); as[k] = ans; for (i = 0; i < v[k].size(); i++) dfs(v[k][i]); if (o) return; if (t == 1) remove(x, y); if (t == 2) place(x, y); if (t == 3) invert(x); } int main() { int q, x, y, i; read(n); read(m); read(q); for (i = 1; i <= q; i++) { read(s[i][0]); read(s[i][1]); if (s[i][0] < 3) read(s[i][2]); if (s[i][0] < 4) v[i - 1].push_back(i); else v[s[i][1]].push_back(i); } dfs(0); for (i = 1; i <= q; i++) printf( %d n , as[i]); }
|
module jt_sfg01(
input rst, // pin 25 (MSX 15) RESET
//inout reg [ 7:0] dio, // pins 43-50 IO(MSX 33-40) DATA BUS
output [ 7:0] sfg_dbi, // pins 43-50 IO(MSX 33-40) DATA BUS
input [ 7:0] sfg_dbo, // pins 43-50 IO(MSX 33-40) DATA BUS
input [15:0] addr, // pins 27-42 O (MSX 17-32) ADDRESS BUS
input clk, // pin 52 O (MSX 42) CLOCK 3.579545Mhz
// bus control
input wr_n, // pin 23 O (MSX 13) WRITE Request from CPU
input rd_n, // pin 24 O (MSX 14) READ Request from CPU
input slt3_n, // pin 14 O (MSX 04) SLOT Select signal
input iorq_n, // pin 21 O (MSX 11) I/O Request from CPU
input mi, // pin 19 O (MSX 09) M1 Signal from CPU
output int_n, // pin 18 I (MSX 08) Maskable INTERRUPT request, open collector signal
output wait_n, // pin 17 I (MSX 07) WAIT request, open collector signal
output oe_n, // ROM OE_n
output [15:0] left,
output [15:0] right
// midi
// input midi_rx,
// output midi_tx,
// keyboard control
);
// ADDRESS TABLE (A2-A0)
// #3FF0 (R) FM Status register
// #3FF0 (W) FM Address register
// #3FF1 (R/W) FM Data register
//
// #3FF2 (R/W) Yamaha external keyboard (YK-01 or YK-10) I/O address.
// #3FF3 (W) MIDI IRQ vector address
// #3FF4 (W) External IRQ vector address
// #3FF5 (R/W) MIDI UART Data read and write buffer
// #3FF6 (R) MIDI UART Status Register
// #3FF6 (W) MIDI UART Command Register
// glue logic
wire ce_n = &addr[13:7]; // IC105 and IC106
wire ic106_4 = ~(addr[6] & ce_n);
wire ic106_2 = ~(addr[5] & addr[4]);
wire ic107_3 = ~(~ic106_4 & ~ic106_2); // this is just an OR but I want to follow the schematic
wire ic107_4 = ~(~ic107_3 & ~addr[3]);
wire cs_n = ~(~ic107_4 & ~slt3_n); // ic107_1
assign busdir_n = ~(~iorq_n & ~mi); // ic107_2
assign wait_n = 1'b1; // No usamos el wait
// OPM_n == 0 --> CS_n --> YM2151
wire opm_n = !(!cs_n && addr[2:1]==2'b00); // OPM active when CS (0x3FF0-0x3FF8) and addr[2:1] =00
// wire [7:0] opm_dout;
// reg [7:0] rom_dout;
assign oe_n = !(!ce_n && !slt3_n);
// Data bus is IO so this manages hight impedance for Output Enable
/*
always @(woe_n) begin
oe_n <= woe_n;
if( !woe_n )
dio <= ( !opm_n ? opm_dout : 8'd0 ) | rom_dout;
else
dio <= 8'hzz;
end
*/
// assign midi_tx = 1'b0;
jt51(
.clk ( clk ), // main clock
.rst ( rst ), // reset
.cs_n ( opm_n ), // chip select
.wr_n ( wr_n ), // write
.a0 ( addr[0] ),
// .d_in ( dio ), // data in
// .d_out ( opm_dout ), // data out
.d_in ( sfg_dbo ), // data in
.d_out ( sfg_dbi ), // data out
.irq_n ( int_n ), // I do not synchronize this signal
// Low resolution output (same as real chip)
//output sample, // marks new output sample
//output signed [15:0] left,
//output signed [15:0] right,
// Full resolution output
//output signed [15:0] xleft,
//output signed [15:0] xright,
// unsigned outputs for sigma delta converters, full resolution
//output [15:0] dacleft,
//output [15:0] dacright
//.xleft ( left),
//.xright (right)
.left ( left),
.right (right)
);
/*
always @(*)
casex( {addr[7:0], ce_n, slt3_n} )
{ 8'hxx, 1'b1, 1'bx } : rom_dout = 8'd0;
{ 8'hxx, 1'bx, 1'b1 } : rom_dout = 8'd0;
{ 8'h80, 1'b0, 1'b0 } : rom_dout = 8'h4d;
{ 8'h81, 1'b0, 1'b0 } : rom_dout = 8'h43;
{ 8'h82, 1'b0, 1'b0 } : rom_dout = 8'h48;
{ 8'h83, 1'b0, 1'b0 } : rom_dout = 8'h46;
{ 8'h84, 1'b0, 1'b0 } : rom_dout = 8'h4d;
{ 8'h85, 1'b0, 1'b0 } : rom_dout = 8'h30;
default: rom_dout = 8'd0;
endcase
*/
endmodule // jt_sfg01
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:25:45 06/10/2015
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(
input clk_50M,
//input btn,
input rst_n,
input RegNumPlus,
//vga
output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b,
//lcd
output lcd_rs,
output lcd_rw,
output lcd_e,
output[3:0] lcd_d,
output flash_ce,
//keyboard
input PS2C,
input PS2D,
//Serial Port
input RxD,
output TxD
);
wire clk;
assign clk = clk_50M;
/*
pbdebounce pb1 (
.clk(clk_50M),
.button(btn),
.pbreg(clk)
);*/
//RegNumControl
reg[4:0] RegNum;
pbdebounce pb2 (
.clk(clk_50M),
.button(RegNumPlus),
.pbreg(rnp)
);
always@(posedge rnp) begin
RegNum <= RegNum + 1;
end
//MainBoard
wire[31:0] RegData,ProgramCounter,IR;
wire[31:0] ExtraOut;
MainBoard mb(
//clk
.clk(clk),
.clk_50M(clk_50M),
//for debug
.RegNum(RegNum),
.RegData(RegData),
.ProgramCounter(ProgramCounter),
.IR(IR),
.ExtraOut(ExtraOut),
//vag
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
//keyboard
.PS2C(PS2C),
.PS2D(PS2D),
//Serial Port
.RxD(RxD),
.TxD(TxD)
);
//LCD_Display
wire[127:0] num128;
assign num128 = {
ProgramCounter | {3'h0,RegNum,24'h0},
RegData,
ExtraOut,
IR
};
LCD_dis lcd (
.clk(clk_50M),
.num(num128),
.reset(rst_n),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_e(lcd_e),
.lcd_d(lcd_d),
.flash_ce(flash_ce)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 10, MOD = 1e9 + 7; int n, x[MAX_N], y[MAX_N], ordered_x[MAX_N], ordered_y[MAX_N], x_n, y_n, ans = 1; int fa[MAX_N * 2], node_cnt[MAX_N * 2], edge_cnt[MAX_N * 2]; void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &x[i], &y[i]); ordered_x[i] = x[i]; ordered_y[i] = y[i]; } sort(ordered_x + 1, ordered_x + n + 1); x_n = unique(ordered_x + 1, ordered_x + n + 1) - ordered_x - 1; for (int i = 1; i <= n; i++) x[i] = lower_bound(ordered_x + 1, ordered_x + x_n + 1, x[i]) - ordered_x; sort(ordered_y + 1, ordered_y + n + 1); y_n = unique(ordered_y + 1, ordered_y + n + 1) - ordered_y - 1; for (int i = 1; i <= n; i++) y[i] = lower_bound(ordered_y + 1, ordered_y + y_n + 1, y[i]) - ordered_y; for (int i = 1; i <= x_n + y_n; i++) fa[i] = i; } int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void merge(int a, int b) { fa[find(a)] = find(b); } void solve() { for (int i = 1; i <= n; i++) merge(x[i], x_n + y[i]); for (int i = 1; i <= x_n; i++) node_cnt[find(i)]++; for (int i = 1; i <= y_n; i++) node_cnt[find(x_n + i)]++; for (int i = 1; i <= n; i++) edge_cnt[find(x[i])]++; for (int i = 1; i <= x_n + y_n; i++) { if (fa[i] != i) continue; int fac = 1; for (int j = 1; j <= node_cnt[i]; j++) fac = fac * 2 % MOD; if (edge_cnt[i] < node_cnt[i]) fac--; ans = (long long)ans * fac % MOD; } printf( %d n , ans); } int main() { init(); solve(); }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void ckmax(T& x, T y) { x = (y > x ? y : x); } template <typename T> inline void ckmin(T& x, T y) { x = (y < x ? y : x); } namespace Fread { const int SIZE = 1 << 21; char buf[SIZE], *S, *T; inline char getchar() { if (S == T) { T = (S = buf) + fread(buf, 1, SIZE, stdin); if (S == T) return n ; } return *S++; } } // namespace Fread namespace Fwrite { const int SIZE = 1 << 21; char buf[SIZE], *S = buf, *T = buf + SIZE; inline void flush() { fwrite(buf, 1, S - buf, stdout); S = buf; } inline void putchar(char c) { *S++ = c; if (S == T) flush(); } struct NTR { ~NTR() { flush(); } } ztr; } // namespace Fwrite namespace Fastio { struct Reader { template <typename T> Reader& operator>>(T& x) { char c = Fread ::getchar(); T f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = Fread ::getchar(); } x = 0; while (c >= 0 && c <= 9 ) { x = x * 10 + (c - 0 ); c = Fread ::getchar(); } x *= f; return *this; } Reader& operator>>(char& c) { c = Fread ::getchar(); while (c == n || c == ) c = Fread ::getchar(); return *this; } Reader& operator>>(char* str) { int len = 0; char c = Fread ::getchar(); while (c == n || c == ) c = Fread ::getchar(); while (c != n && c != ) { str[len++] = c; c = Fread ::getchar(); } str[len] = 0 ; return *this; } Reader() {} } cin; const char endl = n ; struct Writer { template <typename T> Writer& operator<<(T x) { if (x == 0) { Fwrite ::putchar( 0 ); return *this; } if (x < 0) { Fwrite ::putchar( - ); x = -x; } static int sta[45]; int top = 0; while (x) { sta[++top] = x % 10; x /= 10; } while (top) { Fwrite ::putchar(sta[top] + 0 ); --top; } return *this; } Writer& operator<<(char c) { Fwrite ::putchar(c); return *this; } Writer& operator<<(char* str) { int cur = 0; while (str[cur]) Fwrite ::putchar(str[cur++]); return *this; } Writer& operator<<(const char* str) { int cur = 0; while (str[cur]) Fwrite ::putchar(str[cur++]); return *this; } Writer() {} } cout; } // namespace Fastio const int MAXN = 1000, MAXM = 3e4; const int INF = 2e9 + 233; int n, m, s, t; struct EDGE { int nxt, to, w, id; } edge[MAXM * 2 + 5]; int head[MAXN + 5], tot; inline void add_edge(int u, int v, int w, int id) { edge[++tot].nxt = head[u]; edge[tot].to = v; edge[tot].w = w; edge[tot].id = id; head[u] = tot; } pair<int, pair<int, int> > ans; int dfn[MAXN + 5], ofn[MAXN + 5], cnt_dfn; int fa[MAXN + 5], fw[MAXN + 5], fid[MAXN + 5]; int num[MAXN + 5]; long long sum[MAXN + 5], sumid[MAXN + 5]; unsigned long long sumhash[MAXN + 5]; map<unsigned long long, bool> vis; int id[MAXN + 5], lca[MAXN + 5]; set<pair<int, int> > S[MAXN + 5]; vector<pair<int, int> > to_del[MAXN + 5]; int an[MAXN + 5][10], dep[MAXN + 5]; int get_lca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); for (int i = 9; i >= 0; --i) { if (dep[an[u][i]] >= dep[v]) { u = an[u][i]; } } if (u == v) return u; for (int i = 9; i >= 0; --i) { if (an[u][i] != an[v][i]) { u = an[u][i]; v = an[v][i]; } } return an[u][0]; } int l(int id) { int x = edge[id * 2].to; int y = edge[id * 2 - 1].to; if (dfn[x] < dfn[y]) swap(x, y); return x; } void dfs(int u) { dfn[u] = ++cnt_dfn; an[u][0] = fa[u]; dep[u] = dep[fa[u]] + 1; for (int i = 1; i <= 9; ++i) { an[u][i] = an[an[u][i - 1]][i - 1]; } for (int i = head[u]; i; i = edge[i].nxt) { int v = edge[i].to; if (edge[i].id == fid[u]) continue; if (!dfn[v]) { fa[v] = u; fw[v] = edge[i].w; fid[v] = edge[i].id; dfs(v); num[u] += num[v]; sum[u] += sum[v]; sumid[u] += sumid[v]; sumhash[u] += sumhash[v]; if (((int)(S[id[u]]).size()) < ((int)(S[id[v]]).size())) { swap(id[u], id[v]); } for (set<pair<int, int> >::iterator it = S[id[v]].begin(); it != S[id[v]].end(); ++it) { S[id[u]].insert(*it); } } else if (dfn[v] < dfn[u]) { num[u]++; num[v]--; sum[u] += edge[i].w; sum[v] -= edge[i].w; sumid[u] += edge[i].id; sumid[v] -= edge[i].id; S[id[u]].insert(make_pair(dfn[u], edge[i].id)); to_del[v].push_back(make_pair(dfn[u], edge[i].id)); unsigned long long hashw = (((unsigned long long)rand() << 30) ^ (rand() << 15) ^ rand()); while (vis[hashw]) { hashw = (((unsigned long long)rand() << 30) ^ (rand() << 15) ^ rand()); } vis[hashw] = 1; sumhash[u] += hashw; sumhash[v] -= hashw; } } for (int i = 0; i < ((int)(to_del[u]).size()); ++i) { S[id[u]].erase(to_del[u][i]); } assert(((int)(S[id[u]]).size()) == num[u]); if (num[u] >= 2) { lca[u] = get_lca(l(S[id[u]].begin()->second), l(S[id[u]].rbegin()->second)); } ofn[u] = cnt_dfn; } int main() { srand((unsigned long long)time(0) ^ (unsigned long long)(new char)); Fastio ::cin >> n >> m; Fastio ::cin >> s >> t; for (int i = 1; i <= m; ++i) { int u, v, w; Fastio ::cin >> u >> v >> w; add_edge(u, v, w, i); add_edge(v, u, w, i); } for (int i = 1; i <= n; ++i) { id[i] = i; } ans = make_pair(INF, make_pair(INF, INF)); dfs(s); if (!dfn[t]) { Fastio ::cout << 0 << Fastio ::endl; Fastio ::cout << 0 << Fastio ::endl; Fastio ::cout << Fastio ::endl; return 0; } for (int u = t; u != s; u = fa[u]) { if (num[u] == 0) { ckmin(ans, make_pair(fw[u], make_pair(fid[u], 0))); } else if (num[u] == 1) { ckmin(ans, make_pair(fw[u] + (int)sum[u], make_pair(fid[u], (int)sumid[u]))); int x = l(sumid[u]); for (int v = x; v != u; v = fa[v]) { if (num[v] == 1) { if (dfn[get_lca(t, x)] < dfn[v]) { ckmin(ans, make_pair(fw[u] + fw[v], make_pair(fid[u], fid[v]))); } } } } else { int x = lca[u]; for (int v = x; v != u; v = fa[v]) { if (num[u] == num[v] && sum[u] == sum[v] && sumid[u] == sumid[v] && sumhash[u] == sumhash[v]) { if (dfn[get_lca(t, x)] < dfn[v]) { ckmin(ans, make_pair(fw[u] + fw[v], make_pair(fid[u], fid[v]))); } } } } } if (ans.first == INF) { Fastio ::cout << -1 << Fastio ::endl; return 0; } Fastio ::cout << ans.first << Fastio ::endl; if (ans.second.second == 0) { Fastio ::cout << 1 << Fastio ::endl; Fastio ::cout << ans.second.first << Fastio ::endl; } else { Fastio ::cout << 2 << Fastio ::endl; Fastio ::cout << ans.second.first << << ans.second.second << Fastio ::endl; } return 0; }
|
module etx(/*AUTOARG*/
// Outputs
tx_active, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, cclk_p, cclk_n, chip_nreset, txrd_wait,
txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet, etx_nreset,
tx_lclk_div4,
// Inputs
sys_clk, sys_nreset, soft_reset, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter ETYPE = 0;
parameter TARGET = "GENERIC";
//Reset and clocks
input sys_clk; // clock for fifos
input sys_nreset; // reset for fifos
input soft_reset; // software controlled reset
output tx_active; // tx ready to transmit
//Transmit signals for IO
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
//Epiphany Chip Signals
output cclk_p,cclk_n;
output chip_nreset;
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
output etx_nreset;
output tx_lclk_div4;
input etx_cfg_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] tx_data_slow; // From etx_core of etx_core.v
wire [3:0] tx_frame_slow; // From etx_core of etx_core.v
wire tx_lclk90; // From etx_clocks of etx_clocks.v
wire tx_lclk_io; // From etx_clocks of etx_clocks.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_access; // From etx_core of etx_core.v
wire tx_burst; // From etx_core of etx_core.v
wire [PW-1:0] tx_packet; // From etx_core of etx_core.v
wire tx_rd_wait; // From etx_io of etx_io.v
wire tx_wr_wait; // From etx_io of etx_io.v
wire txrd_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrd_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrd_fifo_wait; // From etx_core of etx_core.v
wire txrr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrr_fifo_wait; // From etx_core of etx_core.v
wire txwr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txwr_fifo_wait; // From etx_core of etx_core.v
wire etx_io_nreset;
/************************************************************/
/*Clocks */
/************************************************************/
etx_clocks etx_clocks (.etx_io_nreset (),
/*AUTOINST*/
// Outputs
.tx_lclk_io (tx_lclk_io),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.etx_nreset (etx_nreset),
.chip_nreset (chip_nreset),
.tx_active (tx_active),
// Inputs
.sys_nreset (sys_nreset),
.soft_reset (soft_reset),
.sys_clk (sys_clk));
/************************************************************/
/*FIFOs */
/************************************************************/
etx_fifo #(.TARGET(TARGET))
etx_fifo (/*AUTOINST*/
// Outputs
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
.txrd_fifo_access (txrd_fifo_access),
.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
.txrr_fifo_access (txrr_fifo_access),
.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
.txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
// Inputs
.sys_nreset (sys_nreset),
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.txrd_fifo_wait (txrd_fifo_wait),
.txrr_fifo_wait (txrr_fifo_wait),
.txwr_fifo_wait (txwr_fifo_wait));
/***********************************************************/
/*ELINK CORE LOGIC */
/***********************************************************/
/*etx_core AUTO_TEMPLATE ( .tx_access (tx_access),
.tx_burst (tx_burst),
.tx_io_ack (tx_io_ack),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait),
.tx_packet (tx_packet[PW-1:0]),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.\(.*\)_full (\1_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam etx_core.ID=ID;
etx_core etx_core (.clk (tx_lclk_div4),
.nreset (etx_nreset),
/*AUTOINST*/
// Outputs
.tx_data_slow (tx_data_slow[63:0]),
.tx_frame_slow (tx_frame_slow[3:0]),
.txrd_wait (txrd_fifo_wait), // Templated
.txrr_wait (txrr_fifo_wait), // Templated
.txwr_wait (txwr_fifo_wait), // Templated
.etx_cfg_access (etx_cfg_access), // Templated
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.tx_rd_wait (tx_rd_wait), // Templated
.tx_wr_wait (tx_wr_wait), // Templated
.txrd_access (txrd_fifo_access), // Templated
.txrd_packet (txrd_fifo_packet[PW-1:0]), // Templated
.txrd_full (txrd_wait), // Templated
.txrr_access (txrr_fifo_access), // Templated
.txrr_packet (txrr_fifo_packet[PW-1:0]), // Templated
.txrr_full (txrr_wait), // Templated
.txwr_access (txwr_fifo_access), // Templated
.txwr_packet (txwr_fifo_packet[PW-1:0]), // Templated
.txwr_full (txwr_wait), // Templated
.etx_cfg_wait (etx_cfg_wait)); // Templated
/***********************************************************/
/*TRANSMIT I/O LOGIC */
/***********************************************************/
/*etx_io AUTO_TEMPLATE (
.nreset (etx_io_nreset),
);
*/
etx_io #(.ETYPE(ETYPE))
etx_io (
/*AUTOINST*/
// Outputs
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait),
// Inputs
.tx_lclk_io (tx_lclk_io),
.tx_lclk_div4 (tx_lclk_div4),
.tx_lclk90 (tx_lclk90),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.tx_data_slow (tx_data_slow[63:0]),
.tx_frame_slow (tx_frame_slow[3:0]));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
|
//======================================================================
//
// rosc_entropy.v
// --------------
// Fake ring oscillator based entropy source. This module SHOULD ONLY
// be used during simulation of the Cryptech True Random Number
// Generator (trng). The module DOES NOT provide any real entropy.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = 32'h00000000;
assign error = 0;
assign security_error = 0;
assign entropy_enabled = 1;
assign entropy_data = 32'haa55aa55;
assign entropy_valid = 1;
assign debug = 8'h42;
endmodule // ringosc_entropy
//======================================================================
// EOF ringosc_entropy.v
//======================================================================
|
#include <bits/stdc++.h> int solve(int n, int m, std::vector<int> const& costs) { int chosen_row_minimum = -1; for (int i = 0; i < n; ++i) { auto min = std::min_element(costs.cbegin() + i * m, costs.cbegin() + i * m + m); if (*min > chosen_row_minimum) { chosen_row_minimum = *min; } } return chosen_row_minimum; } int main() { int n, m; std::cin >> n >> m; std::vector<int> costs; costs.reserve(n * m); costs.insert(costs.end(), std::istream_iterator<int>(std::cin), std::istream_iterator<int>()); assert(n * m == (int)costs.size()); int chosen_row_minimum = solve(n, m, costs); printf( %d n , chosen_row_minimum); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_fifo_filler.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Fifo interface between sd card and wishbone clock domains ////
//// and DMA engine eble to write/read to/from CPU memory ////
//// ////
//// Author(s): ////
//// - Marek Czerski, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson () ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module sd_fifo_filler(
input wb_clk,
input rst,
//WB Signals
output [31:0] wbm_adr_o,
output wbm_we_o,
output [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
//Data Master Control signals
input en_rx_i,
input en_tx_i,
input [31:0] adr_i,
//Data Serial signals
input sd_clk,
input [31:0] dat_i,
output [31:0] dat_o,
input wr_i,
input rd_i,
output sd_full_o,
output sd_empty_o,
output wb_full_o,
output wb_empty_o
);
`define FIFO_MEM_ADR_SIZE 4
`define MEM_OFFSET 4
wire reset_fifo;
wire fifo_rd;
reg [31:0] offset;
reg fifo_rd_ack;
reg fifo_rd_reg;
assign fifo_rd = wbm_cyc_o & wbm_ack_i;
assign reset_fifo = !en_rx_i & !en_tx_i;
assign wbm_we_o = en_rx_i & !wb_empty_o;
assign wbm_cyc_o = en_rx_i ? en_rx_i & !wb_empty_o : en_tx_i & !wb_full_o;
assign wbm_stb_o = en_rx_i ? wbm_cyc_o & fifo_rd_ack : wbm_cyc_o;
generic_fifo_dc_gray #(
.dw(32),
.aw(`FIFO_MEM_ADR_SIZE)
) generic_fifo_dc_gray0 (
.rd_clk(wb_clk),
.wr_clk(sd_clk),
.rst(!(rst | reset_fifo)),
.clr(1'b0),
.din(dat_i),
.we(wr_i),
.dout(wbm_dat_o),
.re(en_rx_i & wbm_cyc_o & wbm_ack_i),
.full(sd_full_o),
.empty(wb_empty_o),
.wr_level(),
.rd_level()
);
generic_fifo_dc_gray #(
.dw(32),
.aw(`FIFO_MEM_ADR_SIZE)
) generic_fifo_dc_gray1 (
.rd_clk(sd_clk),
.wr_clk(wb_clk),
.rst(!(rst | reset_fifo)),
.clr(1'b0),
.din(wbm_dat_i),
.we(en_tx_i & wbm_cyc_o & wbm_stb_o & wbm_ack_i),
.dout(dat_o),
.re(rd_i),
.full(wb_full_o),
.empty(sd_empty_o),
.wr_level(),
.rd_level()
);
assign wbm_adr_o = adr_i+offset;
always @(posedge wb_clk or posedge rst)
if (rst) begin
offset <= 0;
fifo_rd_reg <= 0;
fifo_rd_ack <= 1;
end
else begin
fifo_rd_reg <= fifo_rd;
fifo_rd_ack <= fifo_rd_reg | !fifo_rd;
if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
offset <= offset + `MEM_OFFSET;
else if (reset_fifo)
offset <= 0;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: Sdram_RD_FIFO.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_RD_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [8:0] sub_wire1;
wire [15:0] q = sub_wire0[15:0];
wire [8:0] wrusedw = sub_wire1[8:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 16,
dcfifo_mixed_widths_component.lpm_widthu = 9,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 16,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_bb.v FALSE
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Local Clock Buffer for I/O
// /___/ /\ Filename : BUFIO.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 05/30/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFIO
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "BUFIO";
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
buf B1 (O, I);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int x, t, a, b, da, db; cin >> x >> t >> a >> b >> da >> db; if (x == 0) { cout << YES << endl; return 0; } for (int i = 0; i < t; i++) { if (a - da * i == x) { cout << YES << endl; return 0; } if (b - db * i == x) { cout << YES << endl; return 0; } } for (int i = 0; i < t; i++) { for (int j = 0; j < t; j++) { if (a - da * i + b - db * j == x) { cout << YES << endl; return 0; } } } cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const long long INF = 4e18 + 42; long long l[N]; char type[N]; void get_stam(long long need, long long &stam, long long &have, long long &ans, long long cost); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> l[i]; } for (int i = 1; i <= n; ++i) { cin >> type[i]; } long long swim_res = 0, walk_res = INF; long long stam = 0, s_fly = 0, w_fly = 0, ans = 0; for (int i = 1; i <= n; ++i) { if (type[i] == L ) { get_stam(l[i] - stam, stam, s_fly, ans, 1); get_stam(l[i] - stam, stam, w_fly, ans, 2); get_stam(l[i] - stam, stam, swim_res, ans, 3); get_stam(l[i] - stam, stam, walk_res, ans, 5); stam -= l[i]; ans += l[i]; } else if (type[i] == W ) { long long fly = min(2 * l[i], stam + l[i]), swim = 2 * l[i] - fly; stam += (swim - fly) / 2; ans += (3 * swim + fly) / 2; s_fly += fly; swim_res = INF; } else { get_stam(l[i] - stam, stam, s_fly, ans, 1); long long fly = min(2 * l[i], stam + l[i]), walk = 2 * l[i] - fly; stam += (walk - fly) / 2; ans += (5 * walk + fly) / 2; w_fly += fly; } } cout << ans << endl; } void get_stam(long long need, long long &stam, long long &have, long long &ans, long long cost) { if (need <= 0) { return; } long long take = min(have, need); ans += cost * take; have -= take; stam += take; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; set<int> vec; for (int i = 0; i < n; i++) { int d; cin >> d; vec.insert(d); } cout << vec.size() << n ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
package defs;
function automatic integer max;
input integer a;
input integer b;
max = (a > b) ? a : b;
endfunction
function automatic integer log2;
input integer value;
value = value >> 1;
for (log2 = 0; value > 0; log2 = log2 + 1)
value = value >> 1;
endfunction
function automatic integer ceil_log2;
input integer value;
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
endfunction
endpackage
module sub();
import defs::*;
parameter RAND_NUM_MAX = "";
localparam DATA_RANGE = RAND_NUM_MAX + 1;
localparam DATA_WIDTH = ceil_log2(DATA_RANGE);
localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1));
endmodule
module t(/*AUTOARG*/
// Inputs
clk
);
import defs::*;
parameter WHICH = 0;
parameter MAX_COUNT = 10;
localparam MAX_EXPONENT = log2(MAX_COUNT);
localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1);
input clk;
generate
if (WHICH == 1)
begin : which_true
sub sub_true();
defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT;
end
else
begin : which_false
sub sub_false();
defparam sub_false.RAND_NUM_MAX = MAX_COUNT;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int left_[105], right_[105], mark[105]; int main() { int n, j; std::ios::sync_with_stdio(0); while (~scanf( %d , &n)) { int ans = 0; memset(left_, 0, sizeof(left_)); memset(right_, 0, sizeof(right_)); memset(mark, 0, sizeof(mark)); for (int i = 1; i <= n; i++) { scanf( %d %d , &left_[i], &right_[i]); if (left_[i] == 0) mark[++ans] = i; } for (int i = 1; i < ans; i++) { for (j = mark[i]; right_[j] != 0; j = right_[j]) ; left_[mark[i + 1]] = j; right_[j] = mark[i + 1]; } for (int i = 1; i <= n; i++) printf( %d %d n , left_[i], right_[i]); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, flag; cin >> t; while (t--) { string s1, s2; cin >> s1 >> s2; flag = 0; for (i = 0; i < s1.length(); i++) { if (find(s2.begin(), s2.end(), s1[i]) == s2.end()) flag++; } if (flag == s1.length()) cout << NO << endl; else cout << YES << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; string a; int main() { cin >> a; cout << a; for (int i = a.size() - 1; i >= 0; i--) cout << a[i]; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int T; cin >> T; while (T--) { string s[9]; for (long long int i = 0; i < 9; i++) { cin >> s[i]; } for (long long int i = 0; i < 9; i++) { for (long long int j = 0; j < 9; j++) { if (s[i][j] == 3 ) s[i][j] = 1 ; } } for (long long int i = 0; i < 9; i++) { cout << s[i] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, m, x, y, ans; bool b; int main() { scanf( %d%d , &n, &k); ans = n * 2 - k - 1; for (int i = 1; i <= k; i++) { scanf( %d , &m); b = 0; for (int j = 1; j <= m; j++) { scanf( %d , &x); if (j == 1 && x == 1) b = 1; if ((b) && j > 1 && x > y + 1) { ans -= (j - 2) * 2; b = 0; } if ((b) && j == m) ans -= (m - 1) * 2; y = x; } } printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105000; const int mod = 1e9 + 7; vector<int> xloc[maxn], po[maxn]; vector<int> side[maxn], blk; long long ans = 1; long long c[maxn][2]; int vis[maxn], vis_cnt; int d[maxn]; long long g[maxn][2][2]; long long f[maxn][2]; void dfs(int u, int id) { if (vis[u]) return; vis[u] = id; blk.push_back(u); for (int i = (0), iend = ((int)side[u].size() - 1); i <= iend; i++) { int v = side[u][i]; if (vis[v]) continue; dfs(v, id); } } void dp(int id, int l1, int r1, int l2, int r2) { for (int i = (0), iend = (blk.size() + 10); i <= iend; i++) for (int j = (0), jend = (1); j <= jend; j++) for (int k = (0), kend = (1); k <= kend; k++) g[i][j][k] = 0; for (int i = (l1), iend = (r1); i <= iend; i++) g[0][0][i] = 1; if ((!po[blk[0]][1]) || (abs(po[blk[0]][0]) == abs(po[blk[1]][0]) || abs(po[blk[0]][0]) == abs(po[blk[1]][1]))) swap(po[blk[0]][0], po[blk[0]][1]); for (int i = (1), iend = ((int)blk.size() - 1); i <= iend; i++) if (abs(po[blk[i]][1]) == abs(po[blk[i - 1]][1])) swap(po[blk[i]][0], po[blk[i]][1]); for (int i = (1), iend = (blk.size()); i <= iend; i++) { int x = blk[i - 1]; for (int j = (0), jend = (1); j <= jend; j++) { for (int p = (0), pend = (1); p <= pend; p++) { for (int q = (0), qend = (1); q <= qend; q++) { g[i][((((po[x][0]) < 0) ^ p) | (((po[x][1]) < 0) ^ q)) ^ j][q] += g[i - 1][j][p]; g[i][((((po[x][0]) < 0) ^ p) | (((po[x][1]) < 0) ^ q)) ^ j][q] %= mod; } } } } for (int j = (0), jend = (1); j <= jend; j++) { for (int k = (l2), kend = (r2); k <= kend; k++) { c[id][j] += g[blk.size()][j][k]; c[id][j] %= mod; } } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = (1), iend = (n); i <= iend; i++) { int k, loc; scanf( %d , &k); while (k--) { scanf( %d , &loc); po[i].push_back(loc); xloc[abs(loc)].push_back(i); } } for (int i = (1), iend = (m); i <= iend; i++) { if (xloc[i].size() == 2) { side[xloc[i][0]].push_back(xloc[i][1]); side[xloc[i][1]].push_back(xloc[i][0]); d[xloc[i][0]]++; d[xloc[i][1]]++; } else if (!xloc[i].size()) ans *= 2, ans %= mod; } for (int i = (1), iend = (n); i <= iend; i++) { if (vis[i]) continue; blk.clear(); vis_cnt++; dfs(i, vis_cnt); if (blk.size() == 1) { if (po[blk[0]].size() == 1) c[vis_cnt][0] = 1, c[vis_cnt][1] = 1; else if (abs(po[blk[0]][0]) != abs(po[blk[0]][1])) c[vis_cnt][0] = 1, c[vis_cnt][1] = 3; else if (po[blk[0]][0] == po[blk[0]][1]) c[vis_cnt][0] = 1, c[vis_cnt][1] = 1; else c[vis_cnt][0] = 0, c[vis_cnt][1] = 2; continue; } int rt = 0; for (int j = (0), jend = ((int)blk.size() - 1); j <= jend; j++) { if (d[blk[j]] == 1) { rt = blk[j]; break; } } if (rt) { for (int j = (0), jend = ((int)blk.size() - 1); j <= jend; j++) vis[blk[j]] = 0; blk.clear(); dfs(rt, vis_cnt); int x = blk[0]; int l1 = 0, r1 = 1, l2 = 0, r2 = 1; if (po[x].size() == 1) po[x].push_back(0), r1 = 0; x = blk.back(); if (po[x].size() == 1) po[x].push_back(0), r2 = 0; dp(vis_cnt, l1, r1, l2, r2); continue; } dp(vis_cnt, 0, 0, 0, 0); dp(vis_cnt, 1, 1, 1, 1); } f[0][0] = 1; for (int i = (0), iend = (vis_cnt - 1); i <= iend; i++) { for (int l = (0), lend = (1); l <= lend; l++) { for (int x = (0), xend = (1); x <= xend; x++) { f[i + 1][l ^ x] += f[i][l] * c[i + 1][x] % mod; f[i + 1][l ^ x] %= mod; } } } printf( %lld , f[vis_cnt][1] * ans % mod); return 0; }
|
#include <bits/stdc++.h> using namespace std; int color[100005]; vector<int> DSK[100005]; int num = 0, block_size; int S[100005], E[100005], c[100005]; struct query { int l, r, k, id; } Q[100005]; void DFS(int u, int pre) { S[u] = ++num; c[num] = color[u]; for (int i = 0; i < DSK[u].size(); i++) { int w = DSK[u][i]; if (w != pre) DFS(w, u); } E[u] = num; } int cnt[100005], ans[100005], res[100005]; void add(int i) { cnt[c[i]]++; ans[cnt[c[i]]]++; } void del(int i) { ans[cnt[c[i]]]--; cnt[c[i]]--; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) cin >> color[i]; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; DSK[u].push_back(v); DSK[v].push_back(u); } DFS(1, -1); for (int i = 1; i <= m; i++) { int v, k; cin >> v >> k; Q[i] = {S[v], E[v], k, i}; } block_size = sqrt(n); sort(Q + 1, Q + 1 + m, [](const query &a, const query &b) { if (a.l / block_size == b.l / block_size) return a.r < b.r; return a.l / block_size < b.l / block_size; }); int curL = 1, curR = 0; for (int i = 1; i <= m; i++) { int L = Q[i].l, R = Q[i].r; while (curL > L) { add(curL - 1); curL--; } while (curR < R) { add(curR + 1); curR++; } while (curL < L) { del(curL); curL++; } while (curR > R) { del(curR); curR--; } res[Q[i].id] = ans[Q[i].k]; } for (int i = 1; i <= m; i++) cout << res[i] << n ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2 * 1e5 + 1; int l[N], r[N], pos[30]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); string s, t; cin >> s >> t; int n = s.size(), m = t.size(); memset(pos, -1, sizeof pos); for (int i = 0, j = 0; i < n; i++) { if (j < m && s[i] == t[j]) l[i] = pos[s[i] - a ] = j++; else l[i] = pos[s[i] - a ]; } memset(pos, 0x3f, sizeof pos); for (int i = n - 1, j = m - 1; i >= 0; i--) { if (j >= 0 && s[i] == t[j]) r[i] = pos[s[i] - a ] = j--; else r[i] = pos[s[i] - a ]; } bool ok = 1; for (int i = 0; i < n; i++) ok &= (l[i] >= r[i]); cout << (ok ? Yes : No ) << endl; return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S37>:1'
// Non-tunable mask parameter
//'<S37>:1:8'
//'<S37>:1:10'
assign y1 = u[17:9];
//'<S37>:1:14'
assign y = y1;
endmodule // controllerHdl_MATLAB_Function_block
|
#include<cstdio> #include<cstring> #include<algorithm> using namespace std; int t,n,m,f[100005]; int main() { scanf( %d ,&t); while(t--) { memset(f,0,sizeof(f)); scanf( %d%d ,&n,&m); for(int i=1;i<=n;i++) for(int j=1;j<=m;j++) { int x; scanf( %d ,&x); f[i+j]^=x; } int fl=0; for(int i=1;i<=n+m;i++) if(f[i]) fl=1; if(fl) printf( Ashish n ); else printf( Jeel n ); } return 0; }
|
`timescale 1ns/100ps
`define DEBUG 1
`include "../define.v"
`include "../regfile.v"
`include "../pipeline_CPU.v"
`include "../hilo_reg.v"
`include "../BranchControl.v"
`include "../HazardControl.v"
`include "../ForwardControl.v"
`include "../IF.v"
`include "../IF_ID.v"
`include "../ID.v"
`include "../ID_EX.v"
`include "../EX.v"
`include "../ALU.v"
`include "../decoder.v"
`include "../EX_MEM.v"
`include "../MEM.v"
`include "../RM_ctrl.v"
`include "../WM_ctrl.v"
`include "../MEM_WB.v"
`include "../utilities/dffe.v"
`include "../utilities/mux2x1.v"
`include "../utilities/mux4x1.v"
`include "rom.v"
`include "memory.v"
module SOPC;
reg clk;
reg rst;
wire[`RegDataWidth-1:0] data_from_mem;
wire[`MemAddrWidth-1:0] mem_addr;
wire[3:0] mem_byte_slct;
wire[`RegDataWidth-1:0] data_to_write_mem;
wire mem_we;
wire mem_re;
wire[`InstDataWidth-1:0] inst_from_rom;
wire[`InstAddrWidth-1:0] rom_addr;
wire rom_ce;
supply1 vcc;
supply0 gnd;
pipeline_CPU CPU(
.clk(clk),
.rst(rst),
.data_from_mem(data_from_mem),
.mem_addr(mem_addr),
.mem_byte_slct(mem_byte_slct),
.data_to_write_mem(data_to_write_mem),
.mem_we(mem_we),
.mem_re(mem_re),
.inst_from_rom(inst_from_rom),
.rom_addr(rom_addr),
.rom_ce(rom_ce)
);
rom #(.InstMemNum(32)) ROM(
.rst(gnd),
.ce(rom_ce),
.addr(rom_addr),
.inst(inst_from_rom)
);
memory RAM(
.rst(rst),
.ce(mem_re),
.data_i(data_to_write_mem),
.addr_i(mem_addr),
.we(mem_we),
.byte_slct(mem_byte_slct),
.data_o(data_from_mem)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
$dumpfile("test_info/bitwise/bitwise.vcd");
$dumpvars;
$readmemh("test_info/bitwise/bitwise.data", ROM.rom_data, 0, 10);
rst = `RstEnable;
#3 rst = ~`RstEnable;
#70 $finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:35:17 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/crash_pixel/crash_pixel_stub.v
// Design : crash_pixel
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module crash_pixel(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXM = 500 + 5; const int MAXN = 500 + 5; const int MAXQ = 300 + 5; const int MAXK = 800 + 5; const int P = 5; const int MOD = 1e9 + 7; int n, m, q, a[MAXN][MAXK]; int inv[P], ans = 1; char buf[MAXM]; int main() { for (int i = 0; i < P; i++) inv[i] = i * i * i % P; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , buf + 1); for (int j = 1; j <= m; j++) a[j][i] = buf[j] - a ; } scanf( %d , &q); for (int i = 1; i <= q; i++) { scanf( %s , buf + 1); for (int j = 1; j <= m; j++) a[j][i + n] = buf[j] - a ; } int cur = 1, r = 0; for (int i = 1; i <= m && cur <= n; i++) { while (cur <= n) { int t = i; for (int j = i + 1; j <= m; j++) if (a[j][cur]) t = j; for (int j = 1; j <= n + q; j++) swap(a[i][j], a[t][j]); if (a[i][cur]) break; cur++; } if (cur == n + 1) break; for (int j = cur + 1; j <= n + q; j++) a[i][j] = a[i][j] * inv[a[i][cur]] % P; a[i][cur] = 1; for (int j = i + 1; j <= m; j++) { for (int k = cur + 1; k <= n + q; k++) { a[j][k] -= a[j][cur] * a[i][k] % P; if (a[j][k] < 0) a[j][k] += P; } a[j][cur] = 0; } r++; } for (int i = 1; i <= n - r; i++) ans = ans * 5ll % MOD; for (int i = 1; i <= q; i++) { int x = ans; for (int j = 1; j <= m; j++) { bool flg = 1; for (int k = 1; k <= n; k++) flg &= (a[j][k] == 0); flg &= (a[j][n + i] > 0); if (flg) x = 0; } printf( %d n , x); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; long long n; cin >> n; cin >> s; cin >> t; sort(s.begin(), s.end()); sort(t.begin(), t.end()); long long cnt = 0; long long i = 0; long long j = 0; while (i < n && j < n) { if (s[i] <= t[j]) { cnt++; i++; j++; } else j++; } cout << s.length() - cnt << endl; cnt = 0; i = 0; j = 0; while (i < n && j < n) { if (s[i] < t[j]) { cnt++; i++; j++; } else j++; } cout << cnt << endl; }
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const long double pi = acos(-1.0); const long long inf = 1e+9; const long long inf64 = inf * inf; #pragma comment(linker, /STACK:36777216 ) template <typename T> istream &operator>>(istream &, vector<T> &); template <typename T> ostream &operator<<(ostream &, const vector<T> &); void solve() { int m; cin >> m; string s; cin >> s; int n = s.size(); vector<int> cnt(26); for (int i = 0; i < n; i++) cnt[s[i] - a ]++; for (char t = a ; t <= z ; t++) { int last = -1; bool fl = 1; int count = 0; for (int i = 0; i < n; i++) { if (s[i] < t) { if (i - last > m) { fl = 0; break; } last = i; } if (s[i] == t) { int pos = -1; int pos2 = -1; for (int j = last + 1; j < n && j < last + 1 + m; j++) { if (s[j] < t) pos = j; if (s[j] == t) pos2 = j; } if (pos > i) { last = pos; i = pos; continue; } if (pos2 != -1) { i = pos2; last = pos2; count++; } else { fl = 0; break; } } if (n - last <= m) break; } if (fl && n - last <= m) { string ans = ; for (char z = a ; z < t; z++) ans += string(cnt[z - a ], z); ans += string(count, t); cout << ans << endl; return; } } } int main() { solve(); return 0; } template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (int i = 0; i < v.size(); ++i) is >> v[i]; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); ++i) os << v[i]; return os; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a * b / gcd(a, b); } struct data { int num; int init; }; bool byNum(const data &left, const data &right) { return left.num > right.num; } bool descend(const int &left, const int &right) { return left > right; } data total[105]; pair<int, int> pile[105]; int sisa[105], card[105]; int main(void) { int temp, n, i, j; scanf( %d , &n); for (i = 0; i <= n - 1; i++) { scanf( %d , &card[i]); sisa[i] = 0; for (j = 0; j <= card[i] / 2 - 1; j++) { scanf( %d , &temp); pile[i].first += temp; } if (card[i] % 2) { scanf( %d , &temp); sisa[i] = temp; } for (j = 0; j <= card[i] / 2 - 1; j++) { scanf( %d , &temp); pile[i].second += temp; } total[i].num = pile[i].first + sisa[i] + pile[i].second; total[i].init = i; } sort(total, total + n, byNum); sort(sisa, sisa + n, descend); long long a = 0, b = 0; for (i = 0; i <= n - 1; i++) { a += pile[total[i].init].first; b += pile[total[i].init].second; } for (i = 0; i <= n - 1; i++) { if (i % 2) b += sisa[i]; else a += sisa[i]; if (!sisa[i]) break; } cout << a << << b << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<long long>> v; map<int, pair<int, int>> mp; int main() { int k; scanf( %i , &k); v.resize(k + 1); for (int i = 1; i <= k; i++) { int x; scanf( %i , &x); v[i].push_back(0); for (int j = 1; j <= x; ++j) { int y; scanf( %i , &y); v[i][0] += y; v[i].push_back(y); } } for (int i = 1; i <= k; ++i) { for (int j = 1; j < v[i].size(); ++j) { long long x = v[i][0] - v[i][j]; if (mp[x].first && mp[x].first != i) { cout << YES << endl << mp[x].first << << mp[x].second << endl << i << << j; return 0; } else { mp[x] = make_pair(i, j); } } } printf( NO ); return 0; }
|
#include <algorithm> #include <iostream> #include <sstream> #include <string> #include <vector> #include <queue> #include <set> #include <map> #include <cstdio> #include <cstdlib> #include <cctype> #include <cmath> #include <cstring> #include <list> #include <cassert> #include <climits> #include <bitset> #include <chrono> #include <random> using namespace std; #define PB push_back #define MP make_pair #define SZ(v) ((int)(v).size()) #define FOR(i,a,b) for(int i=(a);i<(b);++i) #define REP(i,n) FOR(i,0,n) #define FORE(i,a,b) for(int i=(a);i<=(b);++i) #define REPE(i,n) FORE(i,0,n) #define FORSZ(i,a,v) FOR(i,a,SZ(v)) #define REPSZ(i,v) REP(i,SZ(v)) std::mt19937 rnd((int)std::chrono::steady_clock::now().time_since_epoch().count()); typedef long long ll; ll gcd(ll a, ll b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 5000; const int MAXC = 20; int n, num, den; char s[MAXN + 1]; vector<char> ans; int mp[26]; char c[MAXC]; int nc; int a[MAXN]; int fst[MAXC], lst[MAXC], cnt[MAXC]; bool ok[1 << MAXC]; bool can[1 << MAXC]; void solve() { nc = 0; REP(i, 26) mp[i] = -1; REP(i, n) { int x = s[i] - a ; if (mp[x] == -1) c[nc] = a + x, mp[x] = nc, nc++; a[i] = mp[x]; } REP(i, nc) fst[i] = INT_MAX, lst[i] = INT_MIN, cnt[i] = 0; REP(i, n) fst[a[i]] = min(fst[a[i]], i), lst[a[i]] = max(lst[a[i]], i), ++cnt[a[i]]; //printf( c: ); REP(i, nc) printf( %c , c[i]); puts( ); FOR(mask, 1, 1 << nc) { int maskfst = INT_MAX, masklst = INT_MIN, maskcnt = 0; REP(i, nc) if (mask&(1 << i)) maskfst = min(maskfst, fst[i]), masklst = max(masklst, lst[i]), maskcnt += cnt[i]; ok[mask] = num*(masklst - maskfst + 1) <= maskcnt*den; //printf( %s[%x] [%d..%d] cnt=%d n , ok[mask] ? ok : fail , mask, maskfst, masklst, maskcnt); } can[0] = true; FOR(mask, 1, 1 << nc) { can[mask] = false; if (ok[mask]) REP(i, nc) if ((mask&(1 << i)) != 0 && can[mask ^ (1 << i)]) { can[mask] = true; } REP(i, nc) { int lmask = mask&((2 << i) - 1), rmask = mask^lmask; if (can[lmask] && can[rmask]) can[mask] = true; } } ans.clear(); REP(i, nc) if (can[(1 << nc) - 1 - (1 << i)]) ans.PB(c[i]); sort(ans.begin(), ans.end()); } void run() { scanf( %d%d%d , &n, &num, &den); scanf( %s , s); assert(strlen(s) == n); solve(); printf( %d , SZ(ans)); REPSZ(i, ans) printf( %c , ans[i]); puts( ); } int main() { //int ncase; scanf( %d , &ncase); FORE(i, 1, ncase) run(); return 0; }
|
#include <bits/stdc++.h> const int MX = 1e6 + 23; const long long MOD = 998244353; int read() { char k = getchar(); int x = 0; while (k < 0 || k > 9 ) k = getchar(); while (k >= 0 && k <= 9 ) x = x * 10 + k - 0 , k = getchar(); return x; } int n, m, c[MX], w[MX]; int a[MX], b[MX]; struct Choice { int w, id; bool operator<(const Choice &B) const { return w > B.w; } }; int cho[MX]; void solve() { n = read(), m = read(); for (int i = 1; i <= n; ++i) { c[i] = read(); a[i] = c[i] / 100; b[i] = c[i] % 100; if (!b[i]) cho[i] = 1; } long long ans = 0; std::priority_queue<Choice> q; for (int i = 1; i <= n; ++i) { w[i] = read(); if (m >= b[i]) { if (b[i]) { q.push((Choice){(100 - b[i]) * w[i], i}); } } else { if (!q.empty() && q.top().w <= (100 - b[i]) * w[i]) { ans += q.top().w; q.pop(); q.push((Choice){(100 - b[i]) * w[i], i}); } else { ans += (100 - b[i]) * w[i]; } m += 100; } m -= b[i]; } printf( %lld n , ans); while (!q.empty()) { cho[q.top().id] = 1; q.pop(); } for (int i = 1; i <= n; ++i) { if (cho[i]) { printf( %d %d n , a[i], b[i]); } else printf( %d %d n , a[i] + 1, 0); } } int main() { int T = 1; for (int i = 1; i <= T; ++i) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int a[30], b[30]; char s[1000005]; struct st { long long int x, y; } ara[30]; bool comp(struct st x1, struct st x2) { return x1.y < x2.y; }; int main() { long long int i, j, k, l, m, n, ans = 1LL, t; scanf( %lld %lld , &n, &k); scanf( %s , s); m = strlen(s); for (i = 1; i <= m; i++) { j = s[i - 1] - a ; l = (((ans - a[j]) % 1000000007) + 1000000007) % 1000000007; ans = (ans + l) % 1000000007; a[j] = (a[j] + l) % 1000000007; b[j] = i; } for (i = 0; i < k; i++) ara[i] = {a[i], b[i]}; sort(ara, ara + k, comp); for (i = 0; i < k; i++) a[i] = ara[i].x; for (i = 1; i <= n; i++) { l = (((ans - a[0]) % 1000000007) + 1000000007) % 1000000007; ans = (ans + l) % 1000000007; a[0] = (a[0] + l) % 1000000007; t = a[0]; for (j = 0; j <= k - 2; j++) a[j] = a[j + 1]; a[j] = t; } printf( %lld n , ((ans % 1000000007) + 1000000007) % 1000000007); return 0; }
|
#include<bits/stdc++.h> using namespace std; #define ll long long int int main() { int t; cin>>t; while(t--) { ll n; cin>>n; vector<ll>a(n); for(ll i=0;i<n;i++) { cin>>a[i]; } ll maxi=INT_MIN; for(ll i=n-1;i>-1;i--) { ll total=0; total+=a[i]; if(i+a[i]<n) { total+=a[i+a[i]]; } a[i]=total; maxi=max<ll>(maxi,total); } //cout<< t ; cout<<maxi<< n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, x, ans, num, n, fa[2001]; while (scanf( %d , &n) != EOF) { for (i = 1; i <= n; i++) { scanf( %d , &fa[i]); } ans = 1; for (i = 1; i <= n; i++) { num = 1; x = i; while (fa[x] != -1) { num++; x = fa[x]; } if (num > ans) ans = num; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int a, long long int b) { return (a * b) / gcd(a, b); } long long int dp[200001][18]; void solve() { long long int n, m, rc, cc, rb, cb, tim = 0; cin >> n >> m >> rc >> cc >> rb >> cb; long long int dx = 1, dy = 1; while ((rc != rb) && (cc != cb)) { if ((rc == n) || (rc == 0)) dx = -dx; if ((cc == m) || (cc == 0)) dy = -dy; rc = rc + dx; cc = cc + dy; tim++; } cout << tim << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long int t = 1; for (long long int i = 1; i <= 200000; i++) { for (long long int j = 0; j < 18; j++) { dp[i][j] = dp[i - 1][j] + (((1 << j) & i) == 0); } } cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int nax = 3e5 + 5; long long n, x1, x2; array<long long, 2> c[nax]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> x1 >> x2; for (int i = 0; i < n; i++) cin >> c[i][0], c[i][1] = i; sort(c, c + n); for (int rep = 0; rep < 2; rep++) { int best = n - 1; for (; ~best; --best) if (c[best][0] >= (x2 + n - best - 1) / (n - best)) break; if (best == -1) continue; for (int k = 1; k < n; k++) { int j = lower_bound(c, c + n, array<long long, 2>{(x1 + k - 1) / k}) - c; if (j + k - 1 >= best) continue; cout << Yes n ; if (rep == 0) { cout << k << << n - best << n ; for (int i = j; i < j + k; i++) cout << c[i][1] + 1 << ; cout << n ; for (int i = best; i < n; i++) cout << c[i][1] + 1 << ; cout << n ; } else { cout << n - best << << k << n ; for (int i = best; i < n; i++) cout << c[i][1] + 1 << ; cout << n ; for (int i = j; i < j + k; i++) cout << c[i][1] + 1 << ; cout << n ; } exit(0); } swap(x1, x2); } cout << No n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; template <typename T> inline T Abs(T x) { return (x >= 0) ? x : -x; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> string toStr(T x) { stringstream st; st << x; string s; st >> s; return s; } inline int nextInt() { int x; if (scanf( %d , &x) != 1) throw; return x; } inline long long nextInt64() { long long x; if (scanf( %I64d , &x) != 1) throw; return x; } inline double nextDouble() { double x; if (scanf( %lf , &x) != 1) throw; return x; } const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double EPS = 1E-9; const long double PI = 3.1415926535897932384626433832795; const int MAXN = 100100; unsigned long long d[MAXN], ans; vector<int> g[MAXN]; int n; unsigned long long DFS(int v, int prev) { if (prev != -1) g[v].erase(find((g[v]).begin(), (g[v]).end(), prev)); d[v] = 0; long long sum2 = 0; for (int i = 0; i < (int)(g[v].size()); i++) { unsigned long long cur = DFS(g[v][i], v); sum2 += 1LL * d[v] * cur; d[v] += cur; } d[v]++; ans -= sqr(sum2); ans -= 2LL * sum2 * ((n - d[v] + 1) * d[v] - 1); ans -= 2LL * (d[v] - 1) * ((n - d[v] + 1) * d[v] - 1) - sqr(d[v] - 1); return d[v]; } int main() { n = nextInt(); for (int i = 0; i < (int)(n - 1); i++) { int v = nextInt() - 1; int u = nextInt() - 1; g[v].push_back(u); g[u].push_back(v); } ans = sqr(1LL * n * (n - 1) / 2); DFS(0, -1); cout << ans << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_a.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
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#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) template <class S, class T> ostream& operator<<(ostream& os, const pair<S, T>& p) { return os << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& os, const vector<T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, const unordered_set<T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class S, class T> ostream& operator<<(ostream& os, const unordered_map<S, T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, const set<T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, const multiset<T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class S, class T> ostream& operator<<(ostream& os, const map<S, T>& p) { os << [ ; for (auto& it : p) os << it << ; return os << ] ; } template <class T> void dbs(string str, T t) { cerr << str << : << t << n ; } template <class T, class... S> void dbs(string str, T t, S... s) { long long idx = str.find( , ); cerr << str.substr(0, idx) << : << t << , ; dbs(str.substr(idx + 1), s...); } template <class T> void prc(T a, T b) { cerr << [ ; for (T i = a; i != b; ++i) { if (i != a) cerr << , ; cerr << *i; } cerr << ] n ; } long long power(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = (res * x) % 1000000007; y = y / 2, x = (x * x) % 1000000007; } return res % 1000000007; } long long dp[500001][2]; vector<vector<pair<long long, long long> > > arr(500001); long long n, k; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { return ((dp[a.first][1] + a.second - dp[a.first][0]) > (dp[b.first][1] + b.second - dp[b.first][0])); } void dfs(long long u, long long par) { vector<pair<long long, long long> > temp; for (auto v : arr[u]) { if (v.first != par) { dfs(v.first, u); temp.push_back(v); } } if ((long long)temp.size() == 0) return; sort(temp.begin(), temp.end(), cmp); long long ma = 0; for (long long i = 0; i < (min((long long)temp.size(), k - 1)); i++) { long long v = temp[i].first; if (dp[v][1] + temp[i].second - dp[v][0] > 0) ma += (dp[v][1] + temp[i].second); else ma += dp[v][0]; } for (long long i = k - 1; i < (long long)temp.size(); i++) ma += dp[temp[i].first][0]; dp[u][1] = ma; ma = 0; for (long long i = 0; i < (min((long long)temp.size(), k)); i++) { long long v = temp[i].first; if (dp[v][1] + temp[i].second - dp[v][0] > 0) ma += (dp[v][1] + temp[i].second); else ma += dp[v][0]; } for (long long i = k; i < (long long)temp.size(); i++) ma += dp[temp[i].first][0]; dp[u][0] = ma; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { arr.clear(); cin >> n >> k; arr.resize(n + 1); long long i; for (i = 0; i < n - 1; i++) { long long u, v, w; cin >> u >> v >> w; arr[u].push_back(make_pair(v, w)); arr[v].push_back(make_pair(u, w)); } for (i = 0; i <= n; i++) dp[i][0] = 0, dp[i][1] = 0; dfs(1, 0); cout << max(dp[1][0], dp[1][1]) << n ; } }
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#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) class BIT { public: vector<int> bit; int size_ = 0; void init(int sz) { size_ = sz + 2; bit.resize(size_ + 2, 0); } void add(int pos, int x) { pos++; while (pos <= size_) { bit[pos] += x; pos += (pos & -pos); } } int sum(int pos) { int s = 0; pos++; while (pos >= 1) { s += bit[pos]; pos -= (pos & -pos); } return s; } int searchs(int pos) { int cl = 0, cr = size_ + 1, cm, minx = (1 << 30); for (int i = 0; i < 22; i++) { cm = ((cl + cr) >> 1); int v = sum(cm); if (v >= pos) { minx = min(minx, cm); cr = cm; } else { cl = cm; } } return minx; } }; int N, A[1 << 18]; int Q, K[1 << 18], P[1 << 18], ans[1 << 18]; vector<pair<int, int>> rem; vector<int> G[1 << 18]; BIT Z; int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &A[i]); scanf( %d , &Q); for (int i = 1; i <= Q; i++) scanf( %d%d , &K[i], &P[i]); for (int i = 1; i <= N; i++) rem.push_back(make_pair(-A[i], i)); for (int i = 1; i <= Q; i++) G[K[i]].push_back(i); sort(rem.begin(), rem.end()); Z.init(N + 2); for (int i = 1; i <= N; i++) { Z.add(rem[i - 1].second, 1); for (int j = 0; j < G[i].size(); j++) { int idx = G[i][j]; int val = Z.searchs(P[idx]); ans[idx] = A[val]; } } for (int i = 1; i <= Q; i++) printf( %d n , ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; int x, cnt; int main() { cin >> x; while (x > 0) { if (x % 2 == 1) { cnt++; } x /= 2; } cout << cnt << endl; }
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/* 西江月·证明 即得易见平凡，仿照上例显然；留作习题答案略，读者自证不难。 反之亦然同理，推论自然成立；略去过程Q.E.D.，由上可知证毕。 result of thinking: Pure. 主要是非内、外向树的情形容易遗漏. AC: */ #include <bits/stdc++.h> using namespace std; typedef long long ll; typedef unsigned long long ull; typedef long double ldouble; template<class T> bool chmin(T &x, const T &y) { return x > y ? (x = y, true) : false; } template<class T> bool chmax(T &x, const T &y) { return x < y ? (x = y, true) : false; } #define maxn 1000005 const ll mod = 998244353; const ll inv2 = 499122177; const ll inv6 = 166374059; int n; ll f[maxn], r[maxn], df[maxn]; int main() { scanf( %d , &n); f[0] = r[0] = 1; for (int i = 1; i <= n; i++) { f[i] = (f[i - 1] * f[i - 1] % mod * inv2 + 3 * f[i - 1] * inv2 + 1) % mod; r[i] = (f[i] + (f[i - 1] * f[i - 1] % mod * f[i - 1] + f[i - 1] * f[i - 1] * 3 + f[i - 1] * 2) % mod * inv6) % mod; } ll ans = ((r[n] - r[n - 1]) * 2 - 1) % mod; df[0] = f[0]; for (int i = 1; i <= n; i++) df[i] = f[i] - f[i - 1]; for (int i = 1; i <= n - 2; i++) { (ans += (df[i] - df[i - 1]) * (df[n - 1 - i] - 1)) %= mod; } printf( %lld n , (ans + mod) % mod); return 0; }
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#include <bits/stdc++.h> using namespace std; inline void read(long long &num) { num = 0; long long f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { num = num * 10 + c - 48; c = getchar(); } num *= f; } const long long maxn = 1e5 + 7; long long n, a[maxn], al, t; signed main() { read(n); al = 0; for (long long i = 1; i <= n; ++i) read(a[i]), al ^= a[i]; if (!(n & 1) && al) { puts( NO ); return 0; } if (!(n & 1)) --n; puts( YES ); cout << n - 1 << endl; for (long long i = 1; i <= n - 2; i += 2) cout << i << << i + 1 << << i + 2 << endl; for (long long i = 1; i <= n - 2; i += 2) cout << i << << i + 1 << << n << endl; return 0; }
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