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`define SMV
`include "ovl_always_on_edge_wrapped.v"
`include "ovl_ported/ovl_always_on_edge.v"
/*
* File: ovl_always_on_edge_wrapped_tb.v
* Test bench for ovl_always_on_edge_wrapped.v
* Includes assertions for verification
* Created: 2013-10-10
*
*
*/
module main();
// Inputs to DUT
reg clk;
reg rst;
reg enable;
reg sampling_event;
reg test_expr;
reg prevConfigInvalid;
// Outputs of DUT
wire out;
ovl_always_on_edge_wrapped ovl_aoew_t(.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(sampling_event),
.test_expr(test_expr),
.prevConfigInvalid(prevConfigInvalid),
.out(out));
initial begin
clk = 0;
rst = 1;
enable = 0;
sampling_event = 0;
test_expr = 0;
prevConfigInvalid = 0;
end
always begin
clk = #5 !clk;
end
endmodule
/* *************** SMV Assertions *****************
//SMV-Assertions
# Spec:
# Assert is sequential, not combinational. Output depends on current state + input. Verification proceeds in two parts: input X state -> state and input X state -> output.
# Spec:
#
# Specify function:
# {reset, enable, sampling_event} X {r_reset_n, sampling_event_prev} --> {r_reset_n, sampling_event_prev}
#
# a) IF @t, reset
# THEN @t+1, ~ovl_aoew_t.ovl_always_on_edge.r_reset_n AND
# ~ovl_aoew_t.ovl_always_on_edge.sampling_event_prev
# b) ELSE IF @t, ~reset AND enable AND sampling_event
# THEN @t+1, ovl_aoew_t.ovl_always_on_edge.r_reset_n AND
# ovl_aoew_t.ovl_always_on_edge.sampling_event_prev
# c) ELSE IF @t, ~reset AND enable AND ~sampling_event
# THEN @t+1, ovl_aoew_t.ovl_always_on_edge.r_reset_n AND
# ~ovl_aoew_t.ovl_always_on_edge.sampling_event_prev
# d) ELSE //@t, ~reset AND ~enable
# ovl_aoew_t.ovl_always_on_edge.r_reset_n@t = ovl_aoew_t.ovl_always_on_edge.r_reset_n@t+1 AND
# ovl_aoew_t.ovl_always_on_edge.sampling_event_prev@t = ovl_aoew_t.ovl_always_on_edge.sampling_event_prev@t+1
# Specify function:
# {reset, enable, sampling_event, test_expr, prevConfigInvalid} X {r_reset_n, sampling_event_prev} --> {out}
#
# e) IF @t, reset OR ~enable OR ~sampling_event OR prevConfigInvalid
# THEN @t, ~out
#
# f) ELSE IF @t, ~reset AND enable AND sampling_event AND ~sampling_event_prev AND r_reset_n AND ~test_expr AND ~prevConfigInvalid
# THEN @t, out
#
# g) ELSE
# @t, ~out
#
# Properties:
\e : assert \rst -> X(G((\rst || ~\enable || ~\sampling_event || \prevConfigInvalid ) -> ~\out ));
\f : assert \rst -> X(G((~\rst && \enable && \sampling_event && ~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev && \ovl_aoew_t .\ovl_always_on_edge .\r_reset_n && ~\test_expr && ~\prevConfigInvalid ) -> \out ));
\g : assert \rst -> X(G(~(~\rst && \enable && \sampling_event && ~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev && \ovl_aoew_t .\ovl_always_on_edge .\r_reset_n && ~\test_expr && ~\prevConfigInvalid ) -> ~\out ));
\a : assert G(\rst -> X(~\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n && ~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev ));
\b : assert \rst -> X(G(~\rst && \enable && \sampling_event -> X(\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n && \ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev )));
\c : assert \rst -> X(G(~\rst && \enable && ~\sampling_event -> X(\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n && ~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev )));
\d1 : assert \rst -> X(G(~\rst && ~\enable && \ovl_aoew_t .\ovl_always_on_edge .\r_reset_n -> X(\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n )));
\d2 : assert \rst -> X(G(~\rst && ~\enable && ~\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n -> X(~\ovl_aoew_t .\ovl_always_on_edge .\r_reset_n )));
\d3 : assert \rst -> X(G(~\rst && ~\enable && \ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev -> X(\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev )));
\d4 : assert \rst -> X(G(~\rst && ~\enable && ~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev -> X(~\ovl_aoew_t .\ovl_always_on_edge .\sampling_event_prev )));
//SMV-Assertions
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_4_V
`define SKY130_FD_SC_HS__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_cpl.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_cpl.v //
// Description : Instantiates the completion buffer primitives. 8 KB or //
// 16 KB Dual Port Completion FIFO //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_cpl.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_16k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_cpl #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [9:0] waddr0_i, // write address
input [9:0] waddr1_i, // write address
input [9:0] waddr2_i, // write address
input [9:0] waddr3_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable Bank0
input wen1_i, // write enable Bank1
input wen2_i, // write enable Bank2
input wen3_i, // write enable Bank3
input wen4_i, // write enable Bank4
input wen5_i, // write enable Bank5
input wen6_i, // write enable Bank6
input wen7_i, // write enable Bank7
input [9:0] raddr0_i, // write address
input [9:0] raddr1_i, // write address
input [9:0] raddr2_i, // write address
input [9:0] raddr3_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input ren0_i, // read enable Bank0
input ren1_i, // read enable Bank1
input ren2_i, // read enable Bank2
input ren3_i, // read enable Bank3
input ren4_i, // read enable Bank4
input ren5_i, // read enable Bank5
input ren6_i, // read enable Bank6
input ren7_i // read enable Bank7
);
generate begin
if (COMPLETION_SPACE == "16KB") begin : CPL_FIFO_16KB
pcie3_7x_0_pcie_bram_7vx_16k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.waddr0_i (waddr0_i[9:0]),
.waddr1_i (waddr1_i[9:0]),
.waddr2_i (waddr2_i[9:0]),
.waddr3_i (waddr3_i[9:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen7_i, wen6_i, wen5_i, wen4_i, wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i (raddr0_i[9:0]),
.raddr1_i (raddr1_i[9:0]),
.raddr2_i (raddr2_i[9:0]),
.raddr3_i (raddr3_i[9:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren7_i, ren6_i, ren5_i, ren4_i, ren3_i, ren2_i, ren1_i, ren0_i})
);
end else begin : CPL_FIFO_8KB
pcie3_7x_0_pcie_bram_7vx_8k # (
.IMPL_TARGET(IMPL_TARGET),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.waddr0_i (waddr0_i[8:0]),
.waddr1_i (waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i (raddr0_i[8:0]),
.raddr1_i (raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
end
end
endgenerate
endmodule // pcie_bram_7vx_cpl
|
// Check that implicit cast works for expressions in assignment patterns. The
// result should be the same as assigning the expression to a variable with the
// same type as the base type of the assignment pattern target.
module test;
int dv[];
real dr[];
int tmpv;
real tmpr;
bit failed = 1'b0;
`define check_v(expr) \
dv = '{expr}; \
tmpv = expr; \
if (dv[0] !== tmpv) begin \
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dv[0], tmpv); \
failed = 1'b1; \
end
`define check_r(expr) \
dr = '{expr}; \
tmpr = expr; \
if (dr[0] != tmpr) begin \
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dr[0], tmpr); \
failed = 1'b1; \
end
real r;
int i;
initial begin
r = 4.56;
i = -11;
// Implicit cast from real to vector
`check_v(1.234e16)
`check_v(r)
// Implicit cast from vector to real
`check_r(32'hfffffff0)
`check_r(i)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* LocalLink to AXI4-Stream bridge
*/
module ll_axis_bridge #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* LocalLink input
*/
input wire [DATA_WIDTH-1:0] ll_data_in,
input wire ll_sof_in_n,
input wire ll_eof_in_n,
input wire ll_src_rdy_in_n,
output wire ll_dst_rdy_out_n,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast
);
assign m_axis_tdata = ll_data_in;
assign m_axis_tvalid = !ll_src_rdy_in_n;
assign m_axis_tlast = !ll_eof_in_n;
assign ll_dst_rdy_out_n = !m_axis_tready;
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int n, a[2 * 2005], pos[2 * 2005], dp[2 * 2005][2 * 2005]; int call(int p, int len) { if (p > 2 * n) return len == n; if (len < n) return 0; int &ret = dp[p][len]; if (~ret) return ret; ret = call(p + pos[p], len); ret += call(p + pos[p], len - pos[p]); return ret; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int tc; cin >> tc; while (tc--) { cin >> n; for (int i = 1; i <= 2 * n; i++) { cin >> a[i]; } for (int i = 1; i <= 2 * n; i++) { int cnt = 1; for (int j = i + 1; j <= 2 * n; j++) { if (a[i] > a[j]) cnt++; else break; } pos[i] = cnt; } for (int i = 1; i <= 2 * n; i++) for (int j = 1; j <= 2 * n; j++) dp[i][j] = -1; if (call(1, 2 * n)) cout << YES n ; else cout << NO n ; } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/ninja1.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, a[22][1 << 18], b[22][1 << 18], c[1 << 18], ans[1 << 18]; int M1, M2, M3, M4, N1, N2; int add(int x, int y) { return (x + y) & M1; } int mult(int x, int y) { int z = 0; int xx = x & N1; xx |= xx << 1; z = xx & y; xx = x & N2; xx |= xx >> 1; z ^= (xx & y) << 1; return z & M1; } int zeta(int* a) { int i, j, k; for (i = 0; i < n; i++) { if (i < 3) { for (j = 0; j < (1 << max(n - 3, 0)); j++) { if (i == 0) a[j] = add(a[j], (a[j] & M2) << 4); else if (i == 1) a[j] = add(a[j], (a[j] & M3) << 8); else a[j] = add(a[j], (a[j] & M4) << 16); } } else { for (j = 0; j < (1 << (n - 3)); j += (1 << (i - 2))) { for (k = 0; k < (1 << (i - 3)); k++) a[j ^ k ^ (1 << (i - 3))] = add(a[j ^ k ^ (1 << (i - 3))], a[j ^ k]); } } } return 0; } int main() { int i; scanf( %d n , &n); for (i = 0; i < (1 << n); i++) a[__builtin_popcount(i)][i >> 3] |= ((getchar() - 0 ) << ((i & 7) << 2)); getchar(); for (i = 0; i < (1 << n); i++) b[__builtin_popcount(i)][i >> 3] |= ((getchar() - 0 ) << ((i & 7) << 2)); int j, k; for (i = 0; i < 32; i++) { if ((i & 3) < 2) M1 |= (1 << i); if ((i & 7) < 4) M2 |= (1 << i); if ((i & 15) < 8) M3 |= (1 << i); if ((i & 31) < 16) M4 |= (1 << i); if ((i & 3) == 0) N1 |= (1 << i); if ((i & 3) == 1) N2 |= (1 << i); } for (i = 0; i <= n; i++) zeta(a[i]), zeta(b[i]); for (i = 0; i <= n; i++) { memset(c, 0, sizeof(c)); for (j = 0; j <= i; j++) { for (k = 0; k < (1 << max(n - 3, 0)); k++) c[k] = add(c[k], mult(a[j][k], b[i - j][k])); } for (j = 0; j < (1 << n); j++) { if (__builtin_popcount(j) & 1) { if (c[j >> 3] & (1 << ((j & 7) << 2))) c[j >> 3] ^= (2 << ((j & 7) << 2)); } } zeta(c); for (j = 0; j < (1 << n); j++) { if (__builtin_popcount(j) & 1) { if (c[j >> 3] & (1 << ((j & 7) << 2))) c[j >> 3] ^= (2 << ((j & 7) << 2)); } if (__builtin_popcount(j) == i) ans[j >> 3] ^= c[j >> 3] & (3 << ((j & 7) << 2)); } } for (i = 0; i < (1 << n); i++) printf( %d , (ans[i >> 3] >> ((i & 7) << 2)) & 3); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 112345; long long l[MAXN], r[MAXN]; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) scanf( %lld %lld , l + i, r + i); sort(l, l + n); sort(r, r + n); long long ans = n; for (int i = 0; i < n; ++i) ans += max(l[i], r[i]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, K; int CtoI(int x) { if (x == R ) return 1; if (x == Y ) return 2; if (x == B ) return 3; if (x == W ) return 0; } int ItoC(int x) { if (x == 1) return R ; if (x == 2) return Y ; if (x == 3) return B ; if (x == 0) return . ; } int ar[2005], mt[2005][2][2]; bitset<2005> a[2005]; void ins(bitset<2005>& x) { for (int i = 0; i < 2 * n; i++) if (x[i]) { if (!a[i].none()) x = x ^ a[i]; else { a[i] = x; return; } } if (x[2 * n]) { puts( NO ); exit(0); } } int main() { scanf( %d%d , &n, &K); for (int i = (0), LIM = (n - 1); i <= LIM; i++) mt[i][0][0] = mt[i][1][1] = 1; for (int i = (0), LIM = (K - 1); i <= LIM; i++) { int m, x, cl; char ch[10], col[2]; scanf( %s , ch); scanf( %d , &m); for (int j = (1), LIM = (m); j <= LIM; j++) scanf( %d , &ar[j]), ar[j]--; if (ch[0] == m ) { scanf( %s , col); cl = CtoI(col[0]); bitset<2005> A, B; for (int j = (1), LIM = (m); j <= LIM; j++) { if (mt[ar[j]][0][0]) A[ar[j] << 1] = A[ar[j] << 1] ^ 1; if (mt[ar[j]][0][1]) B[ar[j] << 1] = B[ar[j] << 1] ^ 1; if (mt[ar[j]][1][0]) A[ar[j] << 1 | 1] = A[ar[j] << 1 | 1] ^ 1; if (mt[ar[j]][1][1]) B[ar[j] << 1 | 1] = B[ar[j] << 1 | 1] ^ 1; } A[n << 1] = cl & 1; B[n << 1] = cl & 2; ins(A), ins(B); } else { int b[2][2] = {}; if (ch[0] == R && ch[1] == Y ) { b[1][0] = b[0][1] = 1; } if (ch[0] == R && ch[1] == B ) { b[0][0] = b[1][1] = b[0][1] = 1; } if (ch[0] == Y ) { b[0][0] = b[1][1] = b[1][0] = 1; } for (int j = (1), LIM = (m); j <= LIM; j++) { static int c[2][2]; memset(c, 0, sizeof c); int v = ar[j]; for (int i = (0), LIM = (1); i <= LIM; i++) for (int j = (0), LIM = (1); j <= LIM; j++) for (int k = (0), LIM = (1); k <= LIM; k++) c[i][k] ^= mt[v][i][j] * b[j][k]; for (int i = (0), LIM = (1); i <= LIM; i++) for (int j = (0), LIM = (1); j <= LIM; j++) mt[v][i][j] = c[i][j]; } } } for (int i = (2 * n - 1), LIM = (0); i >= LIM; i--) { for (int j = (i + 1), LIM = (2 * n - 1); j <= LIM; j++) if (a[i][j]) a[i][n << 1] = a[i][n << 1] ^ a[j][n << 1]; } puts( YES ); for (int i = (0), LIM = (n - 1); i <= LIM; i++) { int cl = a[i << 1][n << 1] | (a[i << 1 | 1][n << 1] << 1); putchar(ItoC(cl)); } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; template <class T> void out(T x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) out(x / 10); putchar(x % 10 + 0 ); } long long dp[2005]; struct node { int x, y; } a[2005]; bool cmp(node a, node b) { if (a.x == b.x) return a.y < b.y; return a.x < b.x; } long long fact[200010], inv[200010]; inline long long MOD(long long x) { while (x < 0) x += mod; return x % mod; } long long binpow(long long a, int k) { if (k == 0) return 1; long long ans = binpow(a, k / 2); ans = 1ll * ans * ans % mod; if (k % 2) ans = 1ll * ans * a % mod; return ans; } long long C(long long n, long long k) { if (k > n) return 0; long long ans = fact[n] * 1ll * inv[k] % mod; ans = 1ll * ans * inv[n - k] % mod; return ans % mod; } void pre() { fact[0] = inv[0] = 1; for (int i = 1; i < 200010; i++) { fact[i] = 1ll * i * fact[i - 1] % mod; inv[i] = binpow(fact[i], mod - 2); } } int main() { pre(); int h, w, n; scanf( %d%d%d , &h, &w, &n); for (int i = 0; i < n; i++) scanf( %d%d , &a[i].x, &a[i].y); sort(a, a + n, cmp); long long ans = C(h + w - 2, h - 1); for (int i = 0; i < n; i++) { dp[i] = C(a[i].x + a[i].y - 2, a[i].y - 1); for (int j = 0; j < i; j++) if (a[j].x <= a[i].x && a[j].y <= a[i].y) { dp[i] = (dp[i] - dp[j] * C(a[i].x - a[j].x + a[i].y - a[j].y, a[i].x - a[j].x) + mod) % mod; } ans = (ans - dp[i] * C(h - a[i].x + w - a[i].y, h - a[i].x) + mod) % mod; } out((ans + mod) % mod); return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Phase_Voltages_To_Compare_Values.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Phase_Voltages_To_Compare_Values
// Source Path: controllerHdl/Phase_Voltages_To_Compare_Values
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Phase_Voltages_To_Compare_Values
(
V_0,
V_1,
V_2,
C_0,
C_1,
C_2
);
input signed [19:0] V_0; // sfix20_En12
input signed [19:0] V_1; // sfix20_En12
input signed [19:0] V_2; // sfix20_En12
output [15:0] C_0; // uint16
output [15:0] C_1; // uint16
output [15:0] C_2; // uint16
wire signed [19:0] V [0:2]; // sfix20_En12 [3]
wire signed [19:0] Half_Bus_Voltage_out1; // sfix20_En12
wire signed [20:0] Add2_v; // sfix21_En12
wire signed [20:0] Add2_add_cast; // sfix21_En12
wire signed [20:0] Add2_add_temp; // sfix21_En12
wire signed [20:0] Add2_add_cast_1; // sfix21_En12
wire signed [20:0] Add2_add_temp_1; // sfix21_En12
wire signed [20:0] Add2_add_cast_2; // sfix21_En12
wire signed [20:0] Add2_add_temp_2; // sfix21_En12
wire signed [19:0] Add2_out1 [0:2]; // sfix20_En12 [3]
wire signed [39:0] Voltage_To_PWM_Compare_Units_out1 [0:2]; // sfix40_En24 [3]
wire signed [39:0] Saturation1_out1 [0:2]; // sfix40_En24 [3]
wire [15:0] pwm_compare [0:2]; // uint16 [3]
assign V[0] = V_0;
assign V[1] = V_1;
assign V[2] = V_2;
// <S5>/Half_Bus_Voltage
assign Half_Bus_Voltage_out1 = 20'sb00000110000000000000;
// <S5>/Add2
assign Add2_v = Half_Bus_Voltage_out1;
assign Add2_add_cast = V[0];
assign Add2_add_temp = Add2_add_cast + Add2_v;
assign Add2_out1[0] = Add2_add_temp[19:0];
assign Add2_add_cast_1 = V[1];
assign Add2_add_temp_1 = Add2_add_cast_1 + Add2_v;
assign Add2_out1[1] = Add2_add_temp_1[19:0];
assign Add2_add_cast_2 = V[2];
assign Add2_add_temp_2 = Add2_add_cast_2 + Add2_v;
assign Add2_out1[2] = Add2_add_temp_2[19:0];
// <S5>/Voltage_To_PWM_Compare_Units
assign Voltage_To_PWM_Compare_Units_out1[0] = 341333 * Add2_out1[0];
assign Voltage_To_PWM_Compare_Units_out1[1] = 341333 * Add2_out1[1];
assign Voltage_To_PWM_Compare_Units_out1[2] = 341333 * Add2_out1[2];
// <S5>/Saturation1
assign Saturation1_out1[0] = (Voltage_To_PWM_Compare_Units_out1[0] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[0] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[0]));
assign Saturation1_out1[1] = (Voltage_To_PWM_Compare_Units_out1[1] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[1] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[1]));
assign Saturation1_out1[2] = (Voltage_To_PWM_Compare_Units_out1[2] > 40'sh03E8000000 ? 40'sh03E8000000 :
(Voltage_To_PWM_Compare_Units_out1[2] < 40'sh0000000000 ? 40'sh0000000000 :
Voltage_To_PWM_Compare_Units_out1[2]));
// <S5>/Data Type Conversion1
assign pwm_compare[0] = Saturation1_out1[0][39:24];
assign pwm_compare[1] = Saturation1_out1[1][39:24];
assign pwm_compare[2] = Saturation1_out1[2][39:24];
assign C_0 = pwm_compare[0];
assign C_1 = pwm_compare[1];
assign C_2 = pwm_compare[2];
endmodule // controllerHdl_Phase_Voltages_To_Compare_Values
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_auto_pc_1 -prefix
// zqynq_lab_1_design_auto_pc_1_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zqynq_lab_1_design_auto_pc_1(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module TestConsole (
input CLK,
input RESET,
input [7:0] IN,
output [7:0] OUT,
output RDA,
input ACK,
input WR,
output RDY
);
reg [3:0] SELREG;
assign OUT = 8'h41 + SELREG;
assign RDA = 1'b1;
assign RDY = 1'b1;
always @ (posedge CLK)
begin
if(RESET)
SELREG <= 8'h00;
else
begin
if(WR)
$write("%c", IN);
if(ACK)
SELREG <= SELREG + 1;
end
end
endmodule
module CPUTest;
// Inputs
reg CLK;
reg RESET;
wire [7:0] CIN;
wire CRDA;
wire CRDY;
// Outputs
wire [7:0] COUT;
wire CACK;
wire CWR;
TestConsole console (
.CLK(CLK),
.RESET(RESET),
.IN(COUT),
.OUT(CIN),
.RDA(CRDA),
.ACK(CACK),
.WR(CWR),
.RDY(CRDY)
);
// Instantiate the Unit Under Test (UUT)
BrainfuckWrapper #(
.IA_WIDTH(12)
) uut (
.CLK(CLK),
.RESET(RESET),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
initial begin
// Initialize Inputs
CLK = 1'b1;
RESET = 1'b1;
// Wait 100 ns for global reset to finish
#100;
RESET = 1'b0;
#100;
end
always
#20 CLK <= ~CLK;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_1_V
`define SKY130_FD_SC_HDLL__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_1_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_underflow (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 0;
parameter max = ((1<<width)-1);
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_UNDERFLOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_underflow_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_underflow_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_underflow_psl_logic.v"
`else
`endmodule // ovl_no_underflow
`endif
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; using ld = long double; struct Node { vi to; int lk; ll w; Node() : to(14), lk(0), w(0) {} }; vector<Node> au(1); int sz = 1; void add(const string& s, int w) { int v = 0; for (char c : s) { c -= a ; if (!au[v].to[c]) { au[v].to[c] = sz++; au.push_back(Node()); } v = au[v].to[c]; } au[v].w += w; } void build() { queue<int> q; q.push(0); while (!q.empty()) { int v = q.front(); q.pop(); au[v].w += au[au[v].lk].w; for (char kek = a ; kek <= n ; kek++) { auto c = kek - a ; if (au[v].to[c]) { int u = au[v].to[c]; au[u].lk = (v ? au[au[v].lk].to[c] : 0); q.push(u); } else { au[v].to[c] = au[au[v].lk].to[c]; } } } } ll dp[1 << 14][1001]; ll dp_new[1 << 14][1001]; const ll inf = 1e18 + 228; int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int k; cin >> k; for (int i = 0; i < k; i++) { string s; int w; cin >> s >> w; add(s, w); } build(); string s; cin >> s; string KEK = s; int n = (int)((s).size()); const ll inf = 1e18 + 228; vi bpc(1 << 14); for (int msk = 1; msk < (1 << 14); msk++) { bpc[msk] = 1 + bpc[msk & (msk - 1)]; } vi qps; ll ans_add = 0; int v = 0; int lst = -sz; for (int i = 0; i < n; i++) { if (s[i] == ? ) qps.push_back(i), v = 0, lst = i; else v = au[v].to[s[i] - a ]; if (i - lst >= sz) ans_add += au[v].w; } for (int i = 0; i < (1 << 14); i++) { for (int j = 0; j < sz; j++) { dp[i][j] = dp_new[i][j] = -inf; } } dp[0][0] = 0; int pi = (qps.empty() || qps[0] < sz ? 0 : qps[0] - sz); int yet = 0; vector<vi> msks(15); for (int m = 0; m < (1 << 14); m++) { msks[bpc[m]].push_back(m); } for (int i : qps) { pi = max(pi, i - sz); for (int m : msks[yet]) { for (int s = 0; s < sz; s++) { dp_new[m][s] = -inf; } } for (int s = 0; s < sz; s++) { int ss = s; for (int j = pi; j < i; j++) { ss = au[ss].to[KEK[j] - a ]; } for (int m : msks[yet]) { if (dp[m][s] == -inf) continue; dp_new[m][ss] = max(dp_new[m][ss], dp[m][s]); } } memcpy(dp, dp_new, sizeof(dp)); for (int m : msks[yet]) { for (int b = 0; b < 14; b++) { if (m >> b & 1) continue; int mm = m | (1 << b); for (int s = 0; s < sz; s++) { if (dp[m][s] == -inf) continue; int ss = au[s].to[b]; dp[mm][ss] = max(dp[mm][ss], dp[m][s] + au[ss].w); } } } yet++; pi = i + 1; while (pi < n && pi - i < sz && s[pi] != ? ) pi++; for (int s = 0; s < sz; s++) { int ss = s; ll add = 0; for (int j = i + 1; j < pi; j++) { ss = au[ss].to[KEK[j] - a ]; add += au[ss].w; } for (int m : msks[yet]) { if (dp[m][s] == -inf) continue; dp_new[m][ss] = max(dp_new[m][ss], dp[m][s] + add); } } memcpy(dp, dp_new, sizeof(dp)); } ll ans = -inf; for (int i = 0; i < (1 << 14); i++) { if (bpc[i] != (int)((qps).size())) continue; for (int j = 0; j < sz; j++) { if (ans < dp[i][j]) { ans = dp[i][j]; } } } cout << ans + ans_add; }
|
//-----------------------------------------------------
// Design Name : Test Bench
// File Name : TestBench.v
// Function : Test bench design
// Coder : hydai
//-----------------------------------------------------
module TestBench;
reg in;
reg clk, rst_n;
wire out;
DesignName DesignInstance(
out,
in,
clk,
rst_n
);
initial begin
#0 rst_n = 1'b0; clk = 1'b0;
#20 rst_n = 1'b1; in = 1'b0;
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
wire [17:0] inputArr = 18'b0111_0001_0011_1110_00; // Test pattern
integer i;
initial begin
#20 $display ("Simulate DesignName");
for (i = 17; i >= 0; i = i - 1) begin
#20 in = inputArr[i];
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
#40 $finish;
end
always begin
#10 clk = ~clk;
end
endmodule // End of TestBench
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a1, a2, b1, b2; cin >> a1 >> a2; cin >> b1 >> b2; if ((a2 == b2 && (a1 + b1 == a2)) || (a1 == b1 && (a2 + b2 == a1)) || (a2 == b1 && (a1 + b2 == a2)) || (a1 == b2 && (a2 + b1 == a1))) { cout << Yes << endl; } else { cout << No << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_TB_V
`define SKY130_FD_SC_HD__A21BOI_TB_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__a21boi dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
|
#include <bits/stdc++.h> const double PI = acos(-1.0); using namespace std; const int MAXN = 200117, MAXM = 1200117, C = 5, MAXX = 1000000120; int n, k, a[MAXN], b, c, m, p[MAXM]; long long ans, s[C]; priority_queue<long long> q[C]; inline void add(int x) { int rx = ((x % C) + C) % C; for (int i = 0; i < C; i++) { int d = c * ((i < rx) ? (C + i - rx) : (i - rx)); long long xx = d + 1LL * b * (((MAXX + i) - (x + ((i < rx) ? (C + i - rx) : (i - rx)))) / C); if (((int)(q[i]).size()) < k) s[i] += xx, q[i].push(xx); else if (q[i].top() > xx) s[i] -= q[i].top() - xx, q[i].pop(), q[i].push(xx); } } int main() { scanf( %d %d %d %d , &n, &k, &b, &c); b = min(b, 5 * c); for (int i = 0; i < n; scanf( %d , &a[i++])) ; for (int i = 0; i < n; i++) for (int j = 0; j <= 5; j++) p[m++] = a[i] + j; sort(p, p + m); m = unique(p, p + m) - p; sort(a, a + n); ans = (2117117117117117117LL); for (int i = 0, j = 0; i < m; i++) { for (; j < n && p[i] >= a[j]; add(a[j++])) ; int t = ((p[i] % C) + C) % C; if (((int)(q[t]).size()) == k) ans = min(ans, s[t] - 1LL * k * b * (((MAXX + t) - p[i]) / C)); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; void self_max(long long& a, const long long& b) { a = max(a, b); } void self_min(long long& a, const long long& b) { a = min(a, b); } inline void preprocessing() {} inline void solve() { long long n; cin >> n; if (n == 1) { cout << 1 0 << n ; return; } vector<long long> factors; long long value = 1; long long len = ceil(sqrt(n)) + 1; long long originalN = n; for (long long i = 2; i < len; ++i) { if (n == 1) break; if (n % i == 0) { long long cnt = 0; while (n % i == 0) { ++cnt; n /= i; } factors.emplace_back(cnt); value *= i; } } long long maxCount = 0; for (const long long& factor : factors) if (factor > maxCount) maxCount = factor; if (maxCount < 2) { cout << originalN << 0 << n ; return; } long long operations = ceil(log2(maxCount)); long long u = exp2(operations); for (const long long& factor : factors) { if (factor != u) { ++operations; break; } } if (n == 1) cout << value << << operations << n ; else cout << value * n << << operations + 1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); preprocessing(); solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { cout << INTERCAL << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int gi() { int x; scanf( %d , &x); return x; } struct Segment_Tree { int dep, f, tag; } t[200005 << 2]; struct Qry { int x, tm, id; } q[200005]; struct _Edge { int to, next; } Edge[200005 << 1]; int head[200005], CNT; int top[200005], dfn[200005], rec[200005], dep[200005], son[200005], sz[200005], ans[200005], fa[200005], n, m, tot; inline void AddEdge(int u, int v) { Edge[++CNT] = (_Edge){v, head[u]}; head[u] = CNT; return; } void dfs1(int u, int deep) { dep[u] = deep; son[u] = 0; sz[u] = 1; for (int e = head[u]; e; e = Edge[e].next) { int v = Edge[e].to; dfs1(v, deep + 1); sz[u] += sz[v]; if (!son[u] || sz[son[u]] < sz[v]) son[u] = v; } return; } void dfs2(int u, int upp) { top[u] = upp; dfn[u] = ++tot; rec[tot] = u; if (son[u]) dfs2(son[u], upp); else return; for (int e = head[u]; e; e = Edge[e].next) if (Edge[e].to != son[u]) dfs2(Edge[e].to, Edge[e].to); return; } void Build(int o, int l, int r) { t[o].f = t[o].tag = -2147483640; if (l == r) { t[o].dep = 2 * dep[rec[l]]; return; } int mid = (l + r) >> 1; Build(o << 1, l, mid); Build(o << 1 | 1, mid + 1, r); t[o].dep = max(t[o << 1].dep, t[o << 1 | 1].dep); } inline void up(int o, int v) { t[o].f = max(t[o].f, v + t[o].dep); t[o].tag = max(t[o].tag, v); } inline void PushDown(int o) { if (t[o].tag == -2147483640) return; up(o << 1, t[o].tag); up(o << 1 | 1, t[o].tag); t[o].tag = -2147483640; return; } void Update(int o, int l, int r, int ql, int qr, int v) { if (ql <= l && r <= qr) { up(o, v); return; } int mid = (l + r) >> 1; PushDown(o); if (ql <= mid) Update(o << 1, l, mid, ql, qr, v); if (mid < qr) Update(o << 1 | 1, mid + 1, r, ql, qr, v); t[o].f = max(t[o << 1].f, t[o << 1 | 1].f); } int Query(int o, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) return t[o].f; int mid = (l + r) >> 1, ret = -2147483640; PushDown(o); if (ql <= mid) ret = max(ret, Query(o << 1, l, mid, ql, qr)); if (mid < qr) ret = max(ret, Query(o << 1 | 1, mid + 1, r, ql, qr)); return ret; } inline int Calc(int x, int tm) { int vl = dep[x] + tm, u = x, ret = 0, Ans; while (u) { if (Query(1, 1, n, dfn[top[u]], dfn[u]) <= vl) { u = fa[top[u]]; } else { int l = dfn[top[u]] + 1, r = dfn[u] + 1; if (Query(1, 1, n, dfn[u], dfn[u]) > vl) ret = u; else { while (l <= r) { int mid = (l + r) >> 1; if (Query(1, 1, n, mid, dfn[u]) <= vl) ret = mid, r = mid - 1; else l = mid + 1; } ret = fa[rec[ret]]; } break; } } if (!ret) ret = 1; u = x; Ans = 2 * (dep[x] - dep[ret]) + tm; while (top[u] ^ top[ret]) { Update(1, 1, n, dfn[top[u]], dfn[u], Ans - dep[x]); u = fa[top[u]]; } Update(1, 1, n, dfn[ret], dfn[u], Ans - dep[x]); return Ans; } inline bool cmp1(Qry A, Qry B) { return ((dep[A.x] + A.tm) ^ (dep[B.x] + B.tm)) ? dep[A.x] + A.tm < dep[B.x] + B.tm : A.x < B.x; } int main() { n = gi() + 1; m = gi(); for (int i = 2; i <= n; i++) fa[i] = gi() + 1, AddEdge(fa[i], i); dfs1(1, 1); dfs2(1, 1); Build(1, 1, n); for (int i = 1; i <= m; i++) q[i].x = gi() + 1, q[i].tm = gi(), q[i].id = i; sort(q + 1, q + m + 1, cmp1); for (int i = 1; i <= m; i++) ans[q[i].id] = Calc(q[i].x, q[i].tm); for (int i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; set<int> keyboards; scanf( %d , &n); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); keyboards.insert(a); } int prev = 0; int result = 0; for (auto keyboard : keyboards) { if (prev != 0) result += (keyboard - prev - 1); prev = keyboard; } printf( %d n , result); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; vector<int> val(n); for (int i = 0; i < n; i++) { cin >> val[i]; } if (m == 1) { cout << max(val[0], val[n - 1]) << endl; continue; } if (k >= m - 1) { vector<int> vec; for (int i = 0; i < m; i++) { vec.push_back(val[i]); vec.push_back(val[n - i - 1]); } cout << *max_element(vec.begin(), vec.end()) << endl; continue; } int res_glob = 0; for (int i = 0; i <= k; i++) { int ind_l = i; int ind_r = n - 1 - (k - i); int need = m - k - 1; int cur_res = 2000000000; for (int j = 0; j <= need; j++) { int cur_elem = ind_l + j; int cur_elem_left = ind_r - (need - j); cur_res = min(cur_res, max(val[cur_elem], val[cur_elem_left])); } res_glob = max(res_glob, cur_res); } cout << res_glob << endl; } }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1e4 + 5; class Matrix { public: long long a[3][3]; int n; void Init(int key) { memset(a, 0, sizeof a); if (key) for (int i = 0; i < n; i++) a[i][i] = 1; } Matrix operator*(const Matrix& b) { Matrix c; c.n = n; c.Init(0); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) c.a[i][j] = (c.a[i][j] + a[i][k] * b.a[k][j] % mod) % mod; return c; } Matrix Power(long long t) { Matrix ans, p = *this; ans.n = p.n; ans.Init(1); while (t) { if (t & 1) ans = ans * p; p = p * p; t >>= 1; } return ans; } void Print() { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (j == 0) printf( %lld , a[i][j]); else printf( %lld , a[i][j]); } puts( ); } } }; struct node { int x, tag; long long y; friend bool operator<(const node& a, const node& b) { return a.y < b.y; } } a[maxn * 2]; long long sum[3], b[3]; void calc(long long n) { Matrix f, A; f.Init(0); A.Init(0); f.n = A.n = 3; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (sum[j] == 0) f.a[i][j] = 1; else f.a[i][j] = 0; } } f.a[0][2] = f.a[2][0] = 0; A.a[0][0] = b[0], A.a[0][1] = b[1], A.a[0][2] = b[2]; A = A * f.Power(n); b[0] = A.a[0][0], b[1] = A.a[0][1], b[2] = A.a[0][2]; } int main() { int n; long long m; scanf( %d%lld , &n, &m); int cnt = 0; for (int i = 1; i <= n; i++) { int x; long long l, r; scanf( %d%lld%lld , &x, &l, &r); a[++cnt].x = x - 1, a[cnt].y = l - 1, a[cnt].tag = 1; a[++cnt].x = x - 1, a[cnt].y = r, a[cnt].tag = -1; } sort(a + 1, a + cnt + 1); b[0] = b[2] = 0, b[1] = 1; long long cur = 1; for (int i = 1; i <= cnt; i++) { calc(a[i].y - cur); cur = a[i].y; sum[a[i].x] += a[i].tag; } calc(m - cur); printf( %lld n , b[1]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; string s; cin >> s; vector<int> v(m); for (int i = 0; i < m; i++) { cin >> v[i]; } sort(v.begin(), v.end()); vector<int> ans(26); for (int i = 0; i < n; i++) { int k = v.end() - upper_bound(v.begin(), v.end(), i); ans[s[i] - a ] += (k + 1); } for (auto x : ans) cout << x << ; cout << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0, i; cin >> n; string s; cin >> s; int k = 1; for (i = 0; i < n; i++) { if (s[i] == 1 && k == 1) { sum++; } else if (s[i] == 0 && k == 1) { sum++; k = 0; } } cout << sum; return 0; }
|
//*******************************************************************************************************************************************************/
// Module Name: reg_array_single
// Module Type: Synchronous Single Port Memory Array
// Author: Shreyas Vinod
// Purpose: Random Access Memory (RAM) for Neptune I v3.0
// Description: A synchronous unidirectional single port general purpose register array.
//*******************************************************************************************************************************************************/
module reg_array_single(clk, we, add, wr, rd);
// Parameter Definitions
parameter width = 'd16; // Register Array Width
parameter depth = 'd8192; // Register Array Depth
parameter add_width = 'd13; // Register Addressing Width
// Inputs
input wire clk /* System Clock */; // Management Interfaces
input wire we /* Write Enable */; // Control Interfaces
input wire [add_width-1:0] add /* Address */;
input wire [width-1:0] wr /* Write Port */;
// Outputs
output reg [width-1:0] rd /* Read Port */;
// Internal
reg [width-1:0] mem_arr [0:depth-1] /* Two-dimensional Memory Array (Width-Depth Matrix) */;
// Memory Read Block
always@(posedge clk) begin
rd [width-1:0] <= mem_arr[add] [width-1:0]; // Assigns Port Read Storage Register the value of memory at add if re is true and we is false.
end
// Memory Write Block
always@(posedge clk) begin
if(we) mem_arr[add] [width-1:0] <= wr [width-1:0]; // Writes to memory at add the value at Port if we is true.
end
endmodule
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#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, i; long long sum = 0, x = 0; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } sort(a, a + n); for (i = 0; i < (n / 2); i++) { x += a[i]; } cout << x * x + (sum - x) * (sum - x) << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_PP_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B ;
input SLEEP;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire nor_teb_SLEEP;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_PP_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen640_core
#(
parameter ABUSWIDTH = 16,
parameter CLKDV = 4, //only 4 will work for now
parameter OUTPUT_SIZE =2
)
(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire PULSE_CLK,
input wire PULSE_CLK160,
input wire PULSE_CLK320,
input wire EXT_START,
output wire [OUTPUT_SIZE-1:0] PULSE,
output wire DEBUG
);
localparam VERSION = 1;
wire SOFT_RST;
wire START;
reg CONF_EN;
reg [31:0] CONF_DELAY;
reg [31:0] CONF_WIDTH;
reg [31:0] CONF_REPEAT;
//reg [CLKDV*4-1:0] CONF_PHASE;
reg [15:0] CONF_PHASE;
reg CONF_DONE;
always@(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_DELAY[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_DELAY[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_DELAY[23:16];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_DELAY[31:24];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_WIDTH[7:0];
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_WIDTH[15:8];
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_WIDTH[23:16];
else if(BUS_ADD == 10)
BUS_DATA_OUT <= CONF_WIDTH[31:24];
else if(BUS_ADD == 11)
BUS_DATA_OUT <= CONF_REPEAT[7:0];
else if(BUS_ADD == 12)
BUS_DATA_OUT <= CONF_REPEAT[15:8];
else if(BUS_ADD == 13)
BUS_DATA_OUT <= CONF_REPEAT[23:16];
else if(BUS_ADD == 14)
BUS_DATA_OUT <= CONF_REPEAT[31:24];
else if(BUS_ADD == 15)
BUS_DATA_OUT <= CONF_PHASE[7:0];
else if(BUS_ADD == 16)
BUS_DATA_OUT <= CONF_PHASE[15:8];
// debug
else if(BUS_ADD == 17)
BUS_DATA_OUT <= CNT[7:0];
else if(BUS_ADD == 18)
BUS_DATA_OUT <= CNT[15:8];
else if(BUS_ADD == 19)
BUS_DATA_OUT <= CNT[23:16];
else if(BUS_ADD == 20)
BUS_DATA_OUT <= CNT[31:24];
else if(BUS_ADD == 21)
BUS_DATA_OUT <= {6'b0,PULSE_REF, CNT[32]};
else
BUS_DATA_OUT <= 8'b0;
end
end
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DELAY <= 0;
CONF_WIDTH <= 0;
CONF_REPEAT <= 1;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
else if(BUS_ADD == 3)
CONF_DELAY[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 4)
CONF_DELAY[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_DELAY[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_DELAY[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_WIDTH[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_WIDTH[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_WIDTH[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 10)
CONF_WIDTH[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 11)
CONF_REPEAT[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 12)
CONF_REPEAT[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 13)
CONF_REPEAT[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 14)
CONF_REPEAT[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 15)
CONF_PHASE[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 16)
CONF_PHASE[15:8] <= BUS_DATA_IN;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(PULSE_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(PULSE_CLK), .pulse_out(START_SYNC));
wire EXT_START_SYNC;
reg [2:0] EXT_START_FF;
always @(posedge PULSE_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_SYNC = !EXT_START_FF[2] & EXT_START_FF[1];
reg [31:0] CNT;
wire [32:0] LAST_CNT;
assign LAST_CNT = CONF_DELAY + CONF_WIDTH;
reg [31:0] REAPAT_CNT;
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
REAPAT_CNT <= 0;
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
REAPAT_CNT <= CONF_REPEAT;
else if(REAPAT_CNT != 0 && CNT == 1)
REAPAT_CNT <= REAPAT_CNT - 1;
end
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
CNT <= 0; //IS THIS RIGHT?
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT != 0)
CNT <= 1;
else if(CNT == LAST_CNT && CONF_REPEAT==0)
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT == 0)
CNT <= 0;
else if(CNT != 0)
CNT <= CNT + 1;
end
reg [CLKDV*4-1:0] PULSE_DES;
reg PULSE_REF;
always @ (posedge PULSE_CLK) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN)) begin
PULSE_DES <= 0;
PULSE_REF<=0;
end
else if(CNT == CONF_DELAY && CNT > 0) begin
PULSE_REF<=1;
PULSE_DES <= CONF_PHASE;
end
else if(CNT == CONF_DELAY+1) begin
PULSE_DES <= 16'b1111111111111111;
PULSE_REF<=1;
end
else if(CNT == LAST_CNT) begin
PULSE_DES <= 0;
PULSE_REF<=0;
end
end
assign DEBUG = PULSE_REF;
wire PULSE_CLK_PULSE;
reg [1:0] PULSE_CLK_FF;
always @ (posedge PULSE_CLK160)
PULSE_CLK_FF[1:0] <= {PULSE_CLK_FF[0],PULSE_CLK};
assign PULSE_CLK_PULSE = PULSE_CLK & ~PULSE_CLK_FF[0];
reg [CLKDV*4-1:0] PULSE_DES_DIV;
always @ (negedge PULSE_CLK160) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN))
PULSE_DES_DIV <= 0;
else if (PULSE_CLK_PULSE==1)
PULSE_DES_DIV <= PULSE_DES;
else
PULSE_DES_DIV[CLKDV*4-2:0] <= {PULSE_DES_DIV[CLKDV*4-1],PULSE_DES_DIV[CLKDV*4-1],
PULSE_DES_DIV[CLKDV*4-1],PULSE_DES_DIV[CLKDV*4-1:4]};
end
genvar i;
generate
for (i=0; i<2; i=i+1) begin
OSERDESE2 # (
.DATA_RATE_OQ("DDR"),
.DATA_WIDTH(4),
.SERDES_MODE("MASTER")
) i_OSERDESE2_0 (
.OQ(PULSE[i]),
.OFB(),
.TQ(),
.TFB(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.CLK(PULSE_CLK320),
.CLKDIV(PULSE_CLK160),
.D1(PULSE_DES_DIV[0]),
.D2(PULSE_DES_DIV[1]),
.D3(PULSE_DES_DIV[2]),
.D4(PULSE_DES_DIV[3]),
.D5(),
.D6(),
.D7(),
.D8(),
.TCE(0),
.OCE(1),
.TBYTEIN(),
.TBYTEOUT(),
.RST(RST_SYNC),
.SHIFTIN1(),
.SHIFTIN2(),
.T1(0),
.T2(0),
.T3(0),
.T4(0)
);
end
endgenerate
wire DONE;
assign DONE = (CNT == 0);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC_BUS;
cdc_pulse_sync ex_start_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(EXT_START && CONF_EN), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC_BUS));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || EXT_START_SYNC_BUS)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); mt19937 rnf(2106); const int N = 200005, INF = 1000000009; struct ban { int x, y; }; bool operator<(const ban& a, const ban& b) { return make_pair(a.x, a.y) < make_pair(b.x, b.y); } double dist(const ban& a, const ban& b) { return sqrt((a.x - b.x) * 1LL * (a.x - b.x) + (a.y - b.y) * 1LL * (a.y - b.y)); } long long F(const ban& t1, const ban& t2, const ban& t) { return (t.x - t1.x) * 1LL * (t2.y - t1.y) - (t.y - t1.y) * 1LL * (t2.x - t1.x); } int n, k; ban a[N]; bool so(int i, int j) { return a[i] < a[j]; } bool c[N]; double solv() { int u = -1; for (int i = 1; i <= 3; ++i) { for (int j = i + 1; j <= 3; ++j) { int q = 0; for (int k = 1; k <= n; ++k) { if (F(a[i], a[j], a[k])) ++q; } if (q == 1) { for (int k = 1; k <= n; ++k) { if (F(a[i], a[j], a[k])) { u = k; break; } } } } } assert(u != -1); c[u] = true; vector<int> v; for (int i = 1; i <= n; ++i) { if (i == u) continue; v.push_back(i); } sort((v).begin(), (v).end(), so); double ans = INF; if (k == u) { for (int i = 0; i < ((int)(v).size()); ++i) { ans = min(ans, dist(a[k], a[v[i]]) + dist(a[v[0]], a[v.back()]) * 2 - max(dist(a[v[i]], a[v[0]]), dist(a[v[i]], a[v.back()]))); } } else { ans = min(ans, dist(a[v[0]], a[v.back()]) + dist(a[v[0]], a[k]) + dist(a[v.back()], a[u])); ans = min(ans, dist(a[v[0]], a[v.back()]) + dist(a[v.back()], a[k]) + dist(a[v[0]], a[u])); bool z = false; for (int i = 0; i < ((int)(v).size()) - 1; ++i) { if (v[i] == k) { ans = min(ans, dist(a[k], a[v[0]]) + dist(a[v[0]], a[u]) + min(dist(a[u], a[v[i + 1]]), dist(a[u], a[v.back()])) + dist(a[v[i + 1]], a[v.back()])); z = true; } if (z) ans = min(ans, dist(a[v[0]], a[v[i]]) + dist(a[k], a[v[0]]) + dist(a[v[i]], a[u]) + dist(a[u], a[v[i + 1]]) + dist(a[v[i + 1]], a[v.back()])); } reverse((v).begin(), (v).end()); z = false; for (int i = 0; i < ((int)(v).size()) - 1; ++i) { if (v[i] == k) { ans = min(ans, dist(a[k], a[v[0]]) + dist(a[v[0]], a[u]) + min(dist(a[u], a[v[i + 1]]), dist(a[u], a[v.back()])) + dist(a[v[i + 1]], a[v.back()])); z = true; } if (z) ans = min(ans, dist(a[v[0]], a[v[i]]) + dist(a[k], a[v[0]]) + dist(a[v[i]], a[u]) + dist(a[u], a[v[i + 1]]) + dist(a[v[i + 1]], a[v.back()])); } } return ans; } double solv0() { vector<int> v; for (int i = 1; i <= n; ++i) { if (i == k) continue; v.push_back(i); } double ans = INF; do { double yans = dist(a[k], a[v[0]]); for (int i = 0; i < ((int)(v).size()) - 1; ++i) yans += dist(a[v[i]], a[v[i + 1]]); ans = min(ans, yans); } while (next_permutation((v).begin(), (v).end())); return ans; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); cout.setf(ios::fixed); cout.setf(ios::showpoint); cout.precision(9); int tt = 1; while (tt--) { cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i].x >> a[i].y; set<pair<int, int> > s; c[k] = true; s.insert(make_pair(a[k].x, a[k].y)); for (int i = 1; i <= n; ++i) { if (s.find(make_pair(a[i].x, a[i].y)) != s.end()) continue; c[i] = true; s.insert(make_pair(a[i].x, a[i].y)); } vector<ban> v; bool z = false; for (int i = 1; i <= n; ++i) { if (c[i]) { c[i] = false; v.push_back(a[i]); if (i == k && z == false) { z = true; k = ((int)(v).size()); } } } n = ((int)(v).size()); for (int i = 1; i <= n; ++i) a[i] = v[i - 1]; cout << solv() << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_TB_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_TB_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputiso0p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_inputiso0p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_TB_V
`define SKY130_FD_SC_MS__EINVP_TB_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvp.v"
module top();
// Inputs are registered
reg A;
reg TE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_TB_V
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#include <bits/stdc++.h> using namespace std; const int maxn = 20000; struct node { int flow; int ff[5]; int ru; } mat[maxn]; int n, m; int kk[500]; int now; int getup(int id) { int ret = -1; int k = id - m; while (k >= 1) { if (mat[k].flow != -1) { ret = k; break; } k -= m; } return ret; } int getright(int id) { int ret = -1; int k = id; while (k % m != 0) { k = k + 1; if (mat[k].flow != -1) { ret = k; break; } } return ret; } int getdown(int id) { int ret = -1; int k = id + m; while (k <= n * m) { if (mat[k].flow != -1) { ret = k; break; } k += m; } return ret; } int getleft(int id) { int ret = -1; int k = id; while (k % m != 1) { k--; if (mat[k].flow != -1) { ret = k; break; } } return ret; } int fl[maxn][5]; int ans; int cnt; int solve(int id) { int ret = 0; int k = id; int ne; int u, d, r, l; while (k != -1) { ret++; ne = mat[k].ff[mat[k].flow]; u = mat[k].ff[1]; d = mat[k].ff[3]; r = mat[k].ff[2]; l = mat[k].ff[4]; if (u != -1) { mat[u].ff[3] = d; } if (d != -1) { mat[d].ff[1] = u; } if (r != -1) { mat[r].ff[4] = l; } if (l != -1) { mat[l].ff[2] = r; } k = ne; } return ret; } int main() { kk[ U ] = 1; kk[ R ] = 2; kk[ D ] = 3; kk[ L ] = 4; kk[ . ] = -1; now = 0; cin >> n >> m; string s; for (int i = 1; i <= n; i++) { cin >> s; for (int j = 0; j < m; j++) { mat[++now].flow = kk[s[j]]; } } for (int i = 1; i <= now; i++) { if (mat[i].flow == -1) continue; if (n != 1) fl[i][1] = getup(i); if (m != 1) fl[i][2] = getright(i); if (n != 1) fl[i][3] = getdown(i); if (m != 1) fl[i][4] = getleft(i); if (m == 1) { fl[i][2] = fl[i][4] = -1; } if (n == 1) { fl[i][1] = fl[i][3] = -1; } } for (int i = 1; i <= now; i++) { int ne = fl[i][mat[i].flow]; if (ne != -1) { int nne = fl[ne][mat[ne].flow]; if (nne != i) ; mat[ne].ru = 1; } } ans = 0; for (int i = 1; i <= now; i++) { if (mat[i].flow == -1) continue; for (int i1 = 1; i1 <= now; i1++) { for (int j = 1; j <= 4; j++) { mat[i1].ff[j] = fl[i1][j]; } } int z = solve(i); if (z > ans) { ans = z; cnt = 1; } else if (z == ans) { cnt++; } } cout << ans << << cnt << endl; return 0; }
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#include <bits/stdc++.h> char str[260][260]; int main(void) { int t, n, m; scanf( %d , &t); while (t--) { int ans = 0; scanf( %d%d , &n, &m); getchar(); for (int i = 0; i < n; i++) gets(str[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (str[i][j] == 1 ) { if (str[i][j + 1] == 1 ) { if (i >= 1 && str[i - 1][j] == 1 ) continue; if (j >= 1 && str[i][j - 1] == 1 ) continue; if (i >= 1 && j >= 1 && str[i - 1][j - 1] == 1 ) continue; for (int k = 1; k + i < n && k + j < m; k++) { if (str[i + k][j] == 0 ) break; if (str[i][j + k] == 0 ) break; if (j >= 1 && str[i + k][j - 1] == 1 ) break; if (i >= 1 && str[i - 1][j + k] == 1 ) break; if (str[i + k][j + k] == 0 ) continue; if (j + k + 1 < m && str[i + k][j + k + 1] == 1 ) continue; if (i + k + 1 < n && str[i + k + 1][j + k] == 1 ) continue; if (i + k + 1 < n && j + k + 1 < m && str[i + k + 1][j + k + 1] == 1 ) continue; if (i + k + 1 < n && str[i + k + 1][j] == 1 ) continue; if (j + k + 1 < m && str[i][j + k + 1] == 1 ) continue; if (i + k + 1 < n && j >= 1 && str[i + k + 1][j - 1] == 1 ) continue; if (j + k + 1 < m && i >= 1 && str[i - 1][j + k + 1] == 1 ) continue; int flag = 0; for (int p = 1; p < k && flag == 0; p++) { if (str[i + k][j + p] == 0 ) flag = 1; if (str[i + p][j + k] == 0 ) flag = 1; if (j + k + 1 < m && str[i + p][j + k + 1] == 1 ) flag = 1; if (i + k + 1 < n && str[i + k + 1][j + p] == 1 ) flag = 1; if (str[i + k - 1][j + p] == 1 ) flag = 1; if (str[i + p][j + k - 1] == 1 ) flag = 1; if (str[i + 1][j + p] == 1 ) flag = 1; if (str[i + p][j + 1] == 1 ) flag = 1; } if (!flag) { ans++; break; } } } else { int flag = 1; for (int k = 2; k + i < n; k += 2) { if (j + k / 2 >= m || j - k / 2 < 0) break; if (str[i + k][j] == 1 ) { flag = 1; if (i >= 1 && str[i - 1][j] == 1 ) break; if (j >= 1 && str[i][j - 1] == 1 ) break; if (j < m && str[i][j + 1] == 1 ) break; if (i >= 1 && j + 1 < m && str[i - 1][j + 1] == 1 ) break; if (i >= 1 && j >= 1 && str[i - 1][j - 1] == 1 ) break; if (str[i + 1][j] == 1 ) break; if (str[i + k - 1][j] == 1 ) continue; if (i + k + 1 < n && str[i + k + 1][j] == 1 ) continue; if (j >= 1 && str[i + k][j - 1] == 1 ) continue; if (j + 1 < m && str[i + k][j + 1] == 1 ) continue; if (i + k + 1 < n && j >= 1 && str[i + k + 1][j - 1] == 1 ) continue; if (i + k + 1 < n && j + 1 < m && str[i + k + 1][j + 1] == 1 ) continue; if (j - k / 2 - 1 >= 0 && str[i + k / 2][j - k / 2 - 1] == 1 ) continue; if (str[i + k / 2][j - k / 2 + 1] == 1 ) continue; if (str[i + k / 2 - 1][j - k / 2] == 1 ) continue; if (str[i + k / 2 + 1][j - k / 2] == 1 ) continue; if (j >= 1 && str[i + k / 2 - 1][j - k / 2 - 1] == 1 ) continue; if (j >= 1 && str[i + k / 2 + 1][j - k / 2 - 1] == 1 ) continue; if (str[i + k / 2 - 1][j + k / 2] == 1 ) continue; if (str[i + k / 2 + 1][j + k / 2] == 1 ) continue; if (str[i + k / 2][j + k / 2 - 1] == 1 ) continue; if (j + k / 2 + 1 < m && str[i + k / 2][j + k / 2 + 1] == 1 ) continue; if (j + k / 2 + 1 < m && str[i + k / 2 - 1][j + k / 2 + 1] == 1 ) continue; if (j + k / 2 + 1 < m && str[i + k / 2 + 1][j + k / 2 + 1] == 1 ) continue; flag = 0; for (int p = 1; p <= k / 2 && flag == 0; p++) { if (str[i + p][j + p] == 0 || str[i + p + 1][j + p] == 1 || str[i + p - 1][j + p] == 1 ) flag = 2; if (str[i + p][j - p] == 0 || str[i + p + 1][j - p] == 1 || str[i + p - 1][j - p] == 1 ) flag = 2; if (str[i + k - p][j + p] == 0 || str[i + k - p + 1][j + p] == 1 || str[i + k - p - 1][j + p] == 1 ) flag = 1; if (str[i + k - p][j - p] == 0 || str[i + k - p + 1][j - p] == 1 || str[i + k - p - 1][j - p] == 1 ) flag = 1; } if (flag == 2) break; if (flag == 1) continue; for (int p = 1; p < k / 2 && flag == 0; p++) { if (str[i + p - 1][j + p + 1] == 1 ) flag = 2; if (str[i + p + 1][j + p - 1] == 1 ) flag = 2; if (str[i + k - p - 1][j - p + 1] == 1 ) flag = 1; if (str[i + k - p + 1][j - p - 1] == 1 ) flag = 1; if (str[i + p - 1][j - p - 1] == 1 ) flag = 2; if (str[i + p + 1][j - p + 1] == 1 ) flag = 2; if (str[i + k - p - 1][j + p - 1] == 1 ) flag = 1; if (str[i + k - p + 1][j + p + 1] == 1 ) flag = 1; } if (flag == 2) break; if (flag == 1) continue; } if (!flag) { ans++; break; } } } } } } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; long long fac[N], infac[N]; int n, m; long long poww(long long b, long long p) { if (p == 0) return 1; if (p & 1) return (b * poww(b, p - 1)) % m; return poww((b * b) % m, p / 2); } long long npk(int n, int k) { return (fac[n] * infac[n - k]) % m; } long long nck(int n, int k) { return (((fac[n] * infac[n - k]) % m) * infac[n - k]) % m; } int main() { cin >> n >> m; fac[0] = infac[0] = 1; for (int i = 1; i <= n; i++) { fac[i] = (i * fac[i - 1]) % m; infac[i] = poww(fac[i], m - 2); } long long ans = 0; for (int i = 1; i <= n; i++) { long long a = n - i + 1; a = (a * fac[i]) % m; ans = (ans + a * fac[n - i + 1]) % m; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; struct edge { int u, v; long long c; bool operator<(const edge& other) const { return c < other.c; } }; vector<int> parent; vector<int> size; int get(int v) { if (parent[v] == v) { return v; } return parent[v] = get(parent[v]); } void unite(int a, int b) { a = get(a), b = get(b); if (size[a] < size[b]) { swap(a, b); } parent[b] = a; size[a] += size[b]; } const int rmax = 18; vector<vector<int> > p; vector<vector<long long> > maxx; vector<vector<edge> > g; vector<int> tin, tout; int timer = 0; void dfs(int v, int par) { tin[v] = timer++; p[v][0] = par; for (edge& e : g[v]) { if (e.v != par) { maxx[e.v][0] = e.c; dfs(e.v, v); } } tout[v] = timer++; } bool ancestor(int u, int v) { return tin[u] <= tin[v] && tout[u] >= tout[v]; } int lca(int u, int v) { if (ancestor(u, v)) { return u; } for (int r = rmax - 1; r >= 0; --r) { if (!ancestor(p[u][r], v)) { u = p[u][r]; } } return p[u][0]; } long long getMax(int u, int v) { assert(u != v && ancestor(v, u)); long long ans = 0; for (int r = rmax - 1; r >= 0; --r) { if (!ancestor(p[u][r], v)) { ans = max(ans, maxx[u][r]); u = p[u][r]; } } return max(ans, maxx[u][0]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<edge> edges(m); for (int i = 0; i < m; ++i) { int u, v; long long c; cin >> u >> v >> c; --u, --v; edges[i] = {u, v, c}; } sort((edges).begin(), (edges).end()); parent.resize(n); size.assign(n, 1); for (int i = 0; i < n; ++i) { parent[i] = i; } long long total = 0; vector<edge> useful; for (int i = 0; i < m; ++i) { int u = edges[i].u, v = edges[i].v; u = get(u), v = get(v); if (u == v) { continue; } unite(u, v); total += edges[i].c; useful.push_back(edges[i]); } set<int> s; for (int i = 0; i < n; ++i) { s.insert(get(i)); } if ((int)(s).size() == 1) { p = vector<vector<int> >(n, vector<int>(rmax)); maxx = vector<vector<long long> >(n, vector<long long>(rmax)); g.resize(n); for (edge& e : useful) { int u = e.u, v = e.v; long long c = e.c; g[u].push_back({u, v, c}); g[v].push_back({v, u, c}); } tin.resize(n); tout.resize(n); dfs(0, 0); for (int r = 0; r + 1 < rmax; ++r) { for (int v = 0; v < n; ++v) { int t = p[v][r]; p[v][r + 1] = p[t][r]; maxx[v][r + 1] = max(maxx[v][r], maxx[t][r]); } } } int q; cin >> q; while (q--) { int a, b; cin >> a >> b; --a, --b; if ((int)(s).size() > 2) { cout << -1 n ; continue; } if ((int)(s).size() == 2) { a = get(a), b = get(b); if (a == b) { cout << -1 n ; continue; } cout << total << n ; continue; } int w = lca(a, b); long long ans = 0; if (a != w) { ans = max(ans, getMax(a, w)); } if (b != w) { ans = max(ans, getMax(b, w)); } cout << total - ans << n ; } }
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#include <bits/stdc++.h> using namespace std; long long solve(vector<long long> arr, int index, int currIndex) { if (currIndex == index) { return 1; } else { return 1 + solve(arr, index, arr[currIndex] - 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long testCase; cin >> testCase; while (testCase--) { long long n; cin >> n; vector<long long> arr; for (int i = 0; i < n; i++) { long long j; cin >> j; arr.push_back(j); } std::vector<int> dp(n, 0); for (int i = 0; i < n; i++) { if (!dp[i]) { long long currentIndex = arr[i] - 1; long long ans = 1; while (currentIndex != i) { ans++; currentIndex = arr[currentIndex] - 1; } long long pos = arr[i] - 1; dp[arr[i] - 1] = ans; while (pos != i) { pos = arr[pos] - 1; dp[pos] = ans; } } } for (int i = 0; i < n; i++) { cout << dp[i] << ; } cout << endl; } }
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#include <bits/stdc++.h> using namespace std; vector<long long> adj[100001]; long long vis[100001] = {0}; long long n; long long nodecolor[100001]; long long treecolor[100001]; long long cc[100001]; map<long long, long long> colorcnt; long long dfs(long long root, long long col) { long long cnt = 1; vis[root] = 1; treecolor[root] = nodecolor[root]; for (auto x : adj[root]) { if (vis[x] == 0 && nodecolor[x] != col) treecolor[root] = -1; } long long flag = 0; for (auto x : adj[root]) { if (vis[x] == 0) { flag = 1; cnt += dfs(x, nodecolor[x]); if (treecolor[x] != nodecolor[root]) treecolor[root] = -1; } } if (flag == 0) { treecolor[root] = nodecolor[root]; } return cc[root] = cnt; } long long fun(long long root) { vis[root] = 1; long long flag = 0; set<long long> st; long long parentcolor = -1; for (auto x : adj[root]) { if (vis[x] == 0) { if (treecolor[x] == -1) flag = 1; } else { parentcolor = nodecolor[x]; } } if (flag == 0) { if (parentcolor == -1) return root; for (auto x : adj[root]) { if (vis[x] == 0) { colorcnt[treecolor[x]] -= cc[x]; } } colorcnt[nodecolor[root]]--; if (colorcnt[parentcolor] == n - cc[root]) { return root; } for (auto x : adj[root]) { if (vis[x] == 0) { colorcnt[treecolor[x]] += cc[x]; } } colorcnt[nodecolor[root]]++; } long long ans = -1; for (auto x : adj[root]) { if (vis[x] == 0) { ans = fun(x); if (ans != -1) return ans; } } return ans; } void solve(long long cno) { long long m, i, j, k, l; cin >> n; long long flag = 0; for (i = 0; i < n - 1; i++) { cin >> j >> k; j--; k--; adj[j].push_back(k); adj[k].push_back(j); } for (i = 0; i < n; i++) { cin >> nodecolor[i]; colorcnt[nodecolor[i]]++; } long long temp = dfs(0, nodecolor[0]); for (i = 0; i < n; i++) vis[i] = 0; long long ans = -1; ans = fun(0); if (ans == -1) cout << NO ; else { cout << YES << n << ans + 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; long long i = 1; while (TESTS--) { solve(i); i++; } return 0; }
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//Reg_access每隔0.1s，完整读一次四个电口是否link，并把link状态给port_link输出。其中，clk为12.5MHZ。
//功能描述：Reg_access模块把reg_enb置为高，reg_op[1:0] 置为10，phy_addr[4:0]
//置为00000，reg_addr[4:0] 置为00001，
//说明为从phy里面读1号寄存器里面的0号端口的link状态信息，并把信息给Port_link[3:0]。读完之后reg_enb置为低。
module reg_access (
input clk,
input reset,
input work_bit,
//给出的操作指令
output reg req_enb,
output reg [1:0] req_op,
output reg [4:0]phy_addr,
output reg [4:0]reg_addr,
output reg [3:0]port_link,
input [15:0]data_sta,
input sta_enb
);
reg [31:0]cnt;
reg [4:0]state;
reg timer;
parameter idle =4'd0,
read_port0=4'h1,
send_data0=4'h2,
read_port1=4'd3,
key_data1 =4'd4,
send_data1=4'd5,
read_port2=4'd6,
key_data2 =4'd7,
send_data2=4'd8,
read_port3=4'd9,
key_data3 =4'hA,
send_data3=4'hB;
//
always@(posedge clk,negedge reset)begin//生成计数信息
if(!reset)begin
cnt<=32'b0;
timer<=1'b0;
end
else if(cnt<32'd1250000)begin
cnt<=cnt+1'b1;
timer<=1'b0;
end
else begin
cnt<=32'b0;
timer<=1'b1;
end
end
always@(posedge clk,negedge reset)begin
if(!reset)begin
req_enb<=1'b0;
req_op<=2'b10;
phy_addr<=5'b0;
port_link<=4'b0;
state<=idle;
end
else begin//每0.1s完整读一次四个电口link信息
case(state)
idle: if(timer==1'b1&&work_bit==1'b0)begin//计数0.1s
state<=read_port0;
end
else begin
state<=idle;//判断是否处于空闲状态，不是继续等待
end
//
read_port0: begin//读0号端口的link信息
req_enb<=1'b1;//
req_op<=2'b10;//读操作
phy_addr<=5'd0;//0号端口地址
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data0;
end
else begin
state<=read_port0;
end
end
//
send_data0: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[0]<=data_sta[2];
req_enb<=1'b0;
state<=read_port1;
end
else begin
state<=send_data0;
end
end
//
read_port1: if(work_bit==1'b0)begin//读1号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd1;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data1;
end
else begin
state<=read_port1;
end
//
key_data1: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data1;
end
else begin
state<=key_data1;
end
//
send_data1: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[1]<=data_sta[2];
req_enb<=1'b0;
state<=read_port2;
end
else begin
state<=send_data1;
end
end
//
read_port2: if(work_bit==1'b0)begin//读2号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd2;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data2;
end
else begin
state<=read_port2;
end
//
key_data2: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data2;
end
else begin
state<=key_data2;
end
//
send_data2: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[2]<=data_sta[2];
req_enb<=1'b0;
state<=read_port3;
end
else begin
state<=send_data2;
end
end
//
read_port3: begin
if(work_bit==1'b0)begin//读3号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd3;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data3;
end
else begin
state<=read_port3;
end
end
//
key_data3: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data3;
end
else begin
state<=key_data3;
end
//
send_data3: if(sta_enb==1'b1)begin//读数据
port_link[3]<=data_sta[2];
req_enb<=1'b0;
state<=idle;
end
else begin
state<=send_data3;
end
default: state<=idle;
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e9 + 7; const int N = 0; string s; long long solve(string s) { int n = s.length(); long long ans = 1988; for (auto i = (n - 1); i >= (4); i--) { long long mul = 1, add = 0; for (auto j = (i); j < (n); j++) { mul = 10 * mul; add = 10 * add + s[j] - 0 ; } long long nx = max(mul + ans - add, 0LL) / mul; ans = nx * mul + add; } return ans; } int main() { int test; cin >> test; while (test--) { cin >> s; cout << solve(s) << n ; } }
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#include <bits/stdc++.h> template <class T> void read(T &x) { x = 0; int f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= (ch == - ), ch = getchar(); while (ch <= 9 && ch >= 0 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x = f ? -x : x; return; } const int maxn = 5007; char c[maxn], a[maxn]; int t[2][2]; int main() { int n; read(n); scanf( %s , c + 1); scanf( %s , a + 1); int len = n / 2; for (int i = 1; i <= n; i++) if (c[i] == 1 && a[i] == 1 ) t[1][1]++; else if (c[i] == 1 && a[i] == 0 ) t[1][0]++; else if (c[i] == 0 && a[i] == 1 ) t[0][1]++; else t[0][0]++; for (int i = 0; i <= len; i++) for (int j = 0; j <= i; j++) { if (j > t[1][1]) continue; int k = i - j; if (k > t[1][0]) continue; int re11 = t[1][1] - j; if (re11 > i) continue; int gal = i - re11; if (t[0][1] >= gal) { int x = j, y = k, z = t[0][1] - gal; int res = len - i - z; if (res < 0 || res > t[0][0]) continue; for (int q = 1; q <= n; q++) { if (c[q] == 1 && a[q] == 1 && x > 0) { printf( %d , q); x--; } if (c[q] == 1 && a[q] == 0 && y > 0) { printf( %d , q); y--; } if (c[q] == 0 && a[q] == 1 && z > 0) { printf( %d , q); z--; } if (c[q] == 0 && a[q] == 0 && res > 0) { printf( %d , q); res--; } } return 0; } } printf( -1 n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int p, x, y; cin >> p >> x >> y; for (int i = x; i >= y; i -= 50) { int t = ((i / 50) % 475); set<int> tr; for (int j = 0; j < 25; j++) { t = (t * 96 + 42) % 475; tr.insert(26 + t); } if (tr.find(p) != tr.end()) { cout << 0 n << n ; return 0; } } for (int i = x;; i += 50) { int t = ((i / 50) % 475); set<int> tr; for (int j = 0; j < 25; j++) { t = (t * 96 + 42) % 475; tr.insert(26 + t); } if (tr.find(p) != tr.end()) { (i - x) % 100 == 0 ? cout << (i - x) / 100 : cout << (i - x) / 100 + 1 << n ; return 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2E5 + 10; long long jc[15]; int main() { jc[0] = 1; for (int i = 1; i <= 14; ++i) jc[i] = jc[i - 1] * i; int n, m; cin >> n >> m; int z = max(n - 13, 1); long long ad = 0, p = jc[n - z + 1]; while (m--) { int k; cin >> k; if (k == 1) { int l, r; cin >> l >> r; if (r < z) cout << (l + r) * 1ll * (r - l + 1) / 2 << endl; else { long long ans = (z - 1) * (r - max(l, z) + 1), da = ad; if (l < z) ans += (l + z - 1) * 1ll * (z - l) / 2; bool b[15] = {0}; for (int i = z; i <= r; ++i) { long long t = da / jc[n - i]; int j = 1; da -= t * jc[n - i]; for (; t || b[j]; ++j) if (!b[j]) --t; b[j] = 1; if (i >= l) ans += j; } cout << ans << endl; } } else { int t; cin >> t; ad = (ad + t) % p; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2010; int n, a[N], m; double f[N][N], p, ans; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = (x << 3) + (x << 1) + ch - 48, ch = getchar(); return x; } int main() { scanf( %d%lf%d , &n, &p, &m); f[0][0] = 1; for (int i = 1; i <= m; i++) { f[i][0] = (1 - p) * f[i - 1][0]; for (int j = 1; j <= n - 1; j++) f[i][j] = f[i - 1][j] * (1 - p) + f[i - 1][j - 1] * p; f[i][n] = f[i - 1][n] + f[i - 1][n - 1] * p; } for (int i = 1; i <= n; i++) ans += f[m][i] * i; printf( %lf , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int N; char s[105]; int dp[105][2605]; void pre() { dp[0][0] = 1; for (int i = 1; i <= 100; i++) for (int j = 0; j <= 25 * i; j++) for (int c = 0; c < 26; c++) if (j - c >= 0) (dp[i][j] += dp[i - 1][j - c]) %= mod; } void solve_test() { scanf( %s n , s + 1); N = strlen(s + 1); int cst = 0; for (int i = 1; i <= N; i++) cst += s[i] - a ; int ans = (dp[N][cst] - 1 + mod) % mod; printf( %d n , ans); } int main() { pre(); int T; scanf( %d n , &T); for (int t = 1; t <= T; t++) solve_test(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 20; long long fac[20]; vector<long long> lst; vector<long long> lucky; void prepare(int cnt, int all, long long now) { if (cnt == all) { lucky.push_back(now); return; } prepare(cnt + 1, all, now * 10 + 4); prepare(cnt + 1, all, now * 10 + 7); } inline bool chk(long long x) { while (x) { if (x % 10 != 4 && x % 10 != 7) return false; x /= 10; } return true; } int main() { ios::sync_with_stdio(false); for (int i = 0; i <= 10; i++) prepare(0, i, 0); fac[0] = 1; for (int i = 1; i < 20; i++) fac[i] = fac[i - 1] * i; long long n, k; cin >> n >> k; long long p = 1; while (fac[p] < k) p++; if (p > n) return cout << -1 << n , 0; k--; for (long long i = n - p + 1; i <= n; i++) lst.push_back(i); while (k) { int i; for (i = p; ~i; i--) if (fac[i] <= k) break; int w = k / fac[i]; k -= fac[i] * w; for (int s = 0; s < w; s++) swap(lst[p - 1 - i], lst[p - i + s]); } long long res = upper_bound(lucky.begin(), lucky.end(), n - p) - lucky.begin() - 1; for (int i = 0; i < lst.size(); i++) if (chk(n - p + i + 1) && chk(lst[i])) res++; cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[n], e = 0, s = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) e++; else s++; } int ans = 0; for (int b = 0; b < k; b++) { int c = b, ee = e, second = s; while (c < n) { if (a[c] == 1) ee--; else second--; c += k; } ans = max(ans, abs(ee - second)); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, diff = 0; bool flag = 1; scanf( %d , &n); int a[n]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (i == 1) diff = a[i] - a[i - 1]; } for (int i = 1; i < n; i++) { if (a[i] - a[i - 1] != diff) { flag = 0; break; } } if (flag) printf( %d n , a[0] + n * diff); else printf( %d n , a[n - 1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; const int M = 1000000007; int n, p, c[maxn]; long long ans = 0, pw[maxn], od[maxn], ev[maxn], f[maxn][maxn][maxn][maxn]; void init() { f[0][0][0][0] = 1; pw[0] = 1; for (int i = 1; i < maxn; i++) pw[i] = pw[i - 1] * 2 % M; ev[0] = 1, od[0] = 0; for (int i = 1; i < maxn; i++) ev[i] = od[i] = pw[i - 1]; } void find_ans(int ob, int eb, int ow, int ew, int col, long long &ret) { if (col != 0 && ew != 0) (ret += f[ob][eb][ow][ew - 1] * pw[ow + ew - 1 + eb] % M * od[ob] % M) %= M; if (col != 0 && ow != 0) (ret += f[ob][eb][ow - 1][ew] * pw[ow + ew - 1 + eb] % M * ev[ob] % M) %= M; if (col != 1 && eb != 0) (ret += f[ob][eb - 1][ow][ew] * pw[ob + eb - 1 + ew] % M * od[ow] % M) %= M; if (col != 1 && ob != 0) (ret += f[ob - 1][eb][ow][ew] * pw[ob - 1 + eb + ew] % M * ev[ow] % M) %= M; return; } int main() { init(); scanf( %d%d , &n, &p); for (int i = 1; i <= n; i++) scanf( %d , c + i); for (int i = 1; i <= n; i++) for (int ob = 0; ob <= i; ob++) for (int eb = 0; ob + eb <= i; eb++) for (int ow = 0; ob + eb + ow <= i; ow++) { int ew = i - ob - eb - ow; find_ans(ob, eb, ow, ew, c[i], f[ob][eb][ow][ew]); if (i == n && ((ob + ow) & 1) == p) (ans += f[ob][eb][ow][ew]) %= M; } printf( %I64d , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_2_V
`define SKY130_FD_SC_MS__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_2_V
|
/*
* A D-type flip-flop to check synchronous logic works
* correctly.
*/
module testbench;
reg d, clk, rst, enable;
wire q, q_bar;
dff uut(q, q_bar, d, clk, rst);
initial clk <= 0;
always @(clk)
if (enable)
#1 clk <= !clk;
initial begin
enable <= 1;
rst <= 1;
d <= 1'bx;
#2;
if (q !== 0)
begin
$display("FAILED -- Not reset");
$finish;
end
rst <= 0;
d <= 1'b1;
#2;
if (q !== 1)
begin
$display("FAILED -- q not 1 as expected");
$finish;
end
d <= 1'b0;
#2;
if (q !== 0)
begin
$display("FAILED -- q not 0 as expected");
$finish;
end
rst <= 1;
#2;
enable <= 0; // Alternative to using $finish
$display("PASSED");
end
endmodule // testbench
module dff(q, q_bar, d, clk, rst);
output q, q_bar;
input d, clk, rst;
reg q;
always @(posedge clk or posedge rst)
if (rst)
q <= 1'b0;
else
q <= d;
not(q_bar, q);
endmodule // dff
|
#include <bits/stdc++.h> using namespace std; const int N = 1000005; const int M = 1000005; int go[M][4], fa[M], sum[M], val[M], lzy[M], hsc[M], tsz; void pull(int x) { if (!x) return; sum[x] = val[x] + sum[go[x][0]] + sum[go[x][1]]; if (go[x][2]) sum[x] += min(sum[go[x][2]], sum[go[x][3]]); hsc[x] = go[x][2] || hsc[go[x][0]] || hsc[go[x][1]]; } int make(int v) { ++tsz; val[tsz] = v; pull(tsz); return tsz; } void rev(int x) { if (!x) return; swap(go[x][0], go[x][1]); lzy[x] ^= 1; } void push(int x) { if (lzy[x]) { rev(go[x][0]), rev(go[x][1]); if (go[x][2]) rev(go[x][2]), rev(go[x][3]); lzy[x] = 0; } } int is2(int x) { return go[fa[x]][0] == x || go[fa[x]][1] == x; } int pd2(int x) { return go[fa[x]][0] == x ? 0 : go[fa[x]][1] == x ? 1 : -1; } int is4(int x) { return go[fa[x]][2] == x || go[fa[x]][3] == x; } int pd4(int x) { return go[fa[x]][2] == x ? 2 : go[fa[x]][3] == x ? 3 : -1; } int isl(int x) { return !go[x][0] && !go[x][1]; } void rot(int x) { int y = fa[x], z = fa[y], p = pd2(x), w = go[x][p ^ 1]; if (is2(y)) go[z][pd2(y)] = x; else if (is4(y)) go[z][pd4(y)] = x; fa[x] = z; go[x][p ^ 1] = y; fa[y] = x; go[y][p] = w; if (w) fa[w] = y; pull(y); } void cl(int x) { if (pd2(x) != -1) cl(fa[x]); push(x); } void splay(int x, int y = 0) { for (cl(x); pd2(x) != -1 && fa[x] != y; rot(x)) { if (pd2(fa[x]) != -1 && fa[fa[x]] != y) rot(pd2(fa[x]) == pd2(x) ? fa[x] : x); } pull(x); } int fir(int x) { while (go[x][0]) push(x), x = go[x][0]; return x; } void cyc(int c, int x) { int d = pd4(x); splay(c); push(x); int o = fir(go[c][1]); splay(o, c); go[c][1] = 0; go[c][d] = go[x][0]; fa[go[c][d]] = c; go[x][0] = 0; rev(go[x][1]); go[o][1] = go[x][1]; fa[go[o][1]] = o; go[x][1] = 0; go[o][0] = go[c][d ^ 1]; fa[go[o][0]] = o; go[c][d ^ 1] = o; fa[o] = c; pull(o); pull(c); } void access(int x) { int y = 0, z = x; for (; x; y = x, x = fa[x]) { splay(x); if (fa[x] && go[fa[x]][2]) cyc(fa[x], x); go[x][1] = y; pull(x); } splay(z); } void mkrt(int x) { access(x); rev(x); } void path(int x, int y) { mkrt(x); access(y); splay(x, y); } int get(int x, int y) { if (x == y) return 0; path(x, y); if (fa[x] != y) return -1; return sum[y]; } bool link(int x, int y, int w) { if (x == y) return false; path(x, y); if (fa[x] != y) { int e = make(w); fa[x] = e; fa[e] = y; return true; } if (hsc[y]) return false; int e = make(w), c = make(0); go[c][2] = go[x][1]; fa[go[c][2]] = c; go[c][3] = e; fa[e] = c; go[x][1] = c; fa[c] = x; pull(c); pull(x); pull(y); return true; } bool cut(int x, int y, int w) { if (x == y) return false; path(x, y); if (fa[x] != y) return false; if (!isl(go[x][1])) return false; int c = go[x][1]; push(c); if (go[c][2]) { int d = 0; if (isl(go[c][2]) && val[go[c][2]] == w) d = 2; if (isl(go[c][3]) && val[go[c][3]] == w) d = 3; if (!d) return false; go[x][1] = go[c][d ^ 1]; fa[go[x][1]] = x; pull(x); pull(y); return true; } else { if (val[c] != w) return false; go[x][1] = 0; go[y][0] = 0; fa[x] = 0; pull(x); pull(y); return true; } } int n, m; int U[500005], V[500005]; long long ans; int main() { scanf( %d%d , &n, &m); tsz = n; for (int i = 1; i <= m; i++) scanf( %d%d , &U[i], &V[i]); for (int i = 1, j = 0; i <= m; i++) { if (j < i) { j = i; link(U[j], V[j], 0); } while (j < m && link(U[j + 1], V[j + 1], 0)) j++; cut(U[i], V[i], 0); ans += j - i + 1; } printf( %lld n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description :
// / /
// /__/ /\ Filename : EFUSE_USR.v
// \ \ / \ Timestamp : Wed Mar 19 12:34:06 2008
// \__\/\__ \
//
// Revision:
// 03/19/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module EFUSE_USR (
EFUSEUSR
);
parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [31:0] EFUSEUSR;
assign EFUSEUSR = SIM_EFUSE_VALUE;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V
|
module lcd_bridge (
input clock,
input reset,
input insert,
input [31:0] new_record,
input clear,
output busy,
// LCD interface
output [7:0] lcd_data,
output [4:0] lcd_ctrl
);
/*
* Internal wires and registers.
*/
reg [2:0] state;
reg [17:0] counter;
reg [5:0] lut_index;
reg [8:0] lut_data;
reg reg_lcd_start;
reg [7:0] reg_lcd_data;
reg reg_lcd_rs;
wire wire_lcd_done;
reg reg_update_busy;
reg reg_pre_insert, reg_insert;
reg reg_pre_clear, reg_clear;
reg [8:0] records [0:1][0:10];
/*
* Set the records as blank at start.
*/
initial begin
integer i, j;
for (i = 0; i < 2; i = i+1) begin
for (j = 0; j < 11; j = j+1) begin
records[i][j] <= 9'h120;
end
end
end
/*
* LCD position definitions.
*/
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+11;
parameter LCD_LINE2 = LCD_LINE1+11+1;
parameter LUT_SIZE = LCD_LINE1+22+1;
/*
* FSM state definitions.
*/
parameter [2:0] BEGIN = 3'd0,
CHECK_BUSY_FLAG = 3'd1,
DELAY = 3'd2,
FETCH_DATA = 3'd3;
always @(posedge clock or negedge reset) begin
if (!reset) begin
counter <= 0;
reg_lcd_start <= 0;
reg_lcd_data <= 0;
reg_lcd_rs <= 0;
lut_index <= 0;
reg_update_busy <= 0;
state <= BEGIN;
end
else begin
// detect insert signal
reg_pre_insert <= insert;
if ({reg_pre_insert, insert} == 2'b01) begin
reg_insert <= 1'b1;
end
// detect clear signal
reg_pre_clear <= clear;
if ({reg_pre_clear, clear} == 2'b01) begin
reg_clear <= 1'b1;
end
if (reg_insert) begin
integer i;
for (i = 0; i < 11; i = i+1) begin
records[1][i] <= records[0][i];
case (i)
2, 5: records[0][i] <= 9'h13A;
8: records[0][i] <= 9'h12E;
0, 1: records[0][i] <= {1'b1, 4'b0011, new_record[i*4 +: 4]};
3, 4: records[0][i] <= {1'b1, 4'b0011, new_record[(i-1)*4 +: 4]};
6, 7: records[0][i] <= {1'b1, 4'b0011, new_record[(i-2)*4 +: 4]};
9, 10: records[0][i] <= {1'b1, 4'b0011, new_record[(i-3)*4 +: 4]};
endcase
end
lut_index <= 0;
state <= BEGIN;
reg_insert <= 0;
end
else if (reg_clear) begin
// write blank to cells
integer i, j;
for (i = 0; i < 2; i = i+1) begin
for (j = 0; j < 11; j = j+1) begin
records[i][j] <= 9'h120;
end
end
lut_index <= 0;
state <= BEGIN;
reg_clear <= 0;
end
if (lut_index < LUT_SIZE) begin
case (state)
BEGIN: begin
reg_update_busy <= 1;
reg_lcd_data <= lut_data[7:0];
reg_lcd_rs <= lut_data[8];
reg_lcd_start <= 1;
state <= CHECK_BUSY_FLAG;
end
CHECK_BUSY_FLAG: begin
if (wire_lcd_done) begin
reg_lcd_start <= 0;
state <= DELAY;
end
end
DELAY: begin
if (counter < 18'h3FFFE)
counter <= counter+18'd1;
else begin
counter <= 18'd0;
state <= FETCH_DATA;
end
end
FETCH_DATA: begin
lut_index <= lut_index+1;
state <= BEGIN;
end
endcase
end
else begin
reg_update_busy <= 0;
end
end
end
/*
* Instruction lookup table.
*/
always begin
case (lut_index)
// initialize
LCD_INTIAL+0: lut_data <= 9'h038; // 8-bit data, 2 lines, 5x11 font
LCD_INTIAL+1: lut_data <= 9'h00C; // display on, no cursor (and no blinking)
LCD_INTIAL+2: lut_data <= 9'h001; // clear display
LCD_INTIAL+3: lut_data <= 9'h006; // cursor pos++, no screen shift
LCD_INTIAL+4: lut_data <= 9'h080; // set DDRAM to 0x00 (row0, col0)
// line 1
LCD_LINE1+0: lut_data <= records[0][0];
LCD_LINE1+1: lut_data <= records[0][1];
LCD_LINE1+2: lut_data <= records[0][2];
LCD_LINE1+3: lut_data <= records[0][3];
LCD_LINE1+4: lut_data <= records[0][4];
LCD_LINE1+5: lut_data <= records[0][5];
LCD_LINE1+6: lut_data <= records[0][6];
LCD_LINE1+7: lut_data <= records[0][7];
LCD_LINE1+8: lut_data <= records[0][8];
LCD_LINE1+9: lut_data <= records[0][9];
LCD_LINE1+10: lut_data <= records[0][10];
// change Line
LCD_CH_LINE: lut_data <= 9'h0C0; // set DDRAM to 0x40 (row1, col0)
// line 2
LCD_LINE2+0: lut_data <= records[1][0];
LCD_LINE2+1: lut_data <= records[1][1];
LCD_LINE2+2: lut_data <= records[1][2];
LCD_LINE2+3: lut_data <= records[1][3];
LCD_LINE2+4: lut_data <= records[1][4];
LCD_LINE2+5: lut_data <= records[1][5];
LCD_LINE2+6: lut_data <= records[1][6];
LCD_LINE2+7: lut_data <= records[1][7];
LCD_LINE2+8: lut_data <= records[1][8];
LCD_LINE2+9: lut_data <= records[1][9];
LCD_LINE2+10: lut_data <= records[1][10];
default: lut_data <= 9'h000;
endcase
end
lcd_controller controller_module (
.clock (clock),
.reset (reset),
.data (reg_lcd_data),
.rs (reg_lcd_rs),
.write_start (reg_lcd_start),
.lcd_done (wire_lcd_done),
// LCD Interface
.lcd_data (lcd_data),
.lcd_ctrl (lcd_ctrl)
);
assign busy = reg_update_busy;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:16:06 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// TDM slave controller, high speed version ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// This block connectes the FPGA and CPLD on XESS XSV board ////
//// using high speed time division multiplexing over serial ////
//// connection. This block implements the slave part. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// - Simon Srot, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 OpenCores ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "rtl/verilog/bench_timescale.v"
// synopsys translate_on
module tdm_slave_if(
clk, rst, tdmfrm, tdmrx, tdmtx,
din, dout
);
//
// I/O ports
//
//
// Global signals
//
input clk;
input rst;
//
// External CPLD signals
//
input tdmfrm;
input tdmrx;
output tdmtx;
//
// Internal demuxed 8-bit buses
//
input [7:0] din;
output [7:0] dout;
//
// Internal regs and wires
//
reg [2:0] clk_cnt;
reg [7:0] dout;
reg tdmtx;
//
// Counter for low speed clock and incoming JTAG data slots
//
always @(posedge clk or posedge rst)
if (rst)
clk_cnt <= #1 3'b000;
else if (tdmfrm)
clk_cnt <= #1 3'b001;
else
clk_cnt <= #1 clk_cnt + 1;
//
// RX Data slot extraction
//
always @(posedge clk or posedge rst)
if (rst) begin
dout <= #1 8'b0000_0000;
end else
case (clk_cnt[2:0])
3'd0: dout[0] <= #1 tdmrx;
3'd1: dout[1] <= #1 tdmrx;
3'd2: dout[2] <= #1 tdmrx;
3'd3: dout[3] <= #1 tdmrx;
3'd4: dout[4] <= #1 tdmrx;
3'd5: dout[5] <= #1 tdmrx;
3'd6: dout[6] <= #1 tdmrx;
3'd7: dout[7] <= #1 tdmrx;
endcase
//
// TX Data slot insertion
//
always @(clk_cnt or din)
case (clk_cnt[2:0])
3'd0: tdmtx = din[0];
3'd1: tdmtx = din[1];
3'd2: tdmtx = din[2];
3'd3: tdmtx = din[3];
3'd4: tdmtx = din[4];
3'd5: tdmtx = din[5];
3'd6: tdmtx = din[6];
3'd7: tdmtx = din[7];
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, n, m, cur; int nxt[200200][26], link[200200], dp[200200], cnt[200200], ord[200200], occur[200200]; char s[200200]; void extend(int c) { int x = cur, y = cur = ++m; dp[y] = dp[x] + 1; occur[y] = 1; while (x && !nxt[x][c]) nxt[x][c] = y, x = link[x]; if (!x) link[y] = 1; else { int z = nxt[x][c]; if (dp[z] == dp[x] + 1) link[y] = z; else { int u = ++m; memcpy(nxt[u], nxt[z], sizeof nxt[u]); link[u] = link[z], link[z] = link[y] = u; dp[u] = dp[x] + 1; while (x && nxt[x][c] == z) nxt[x][c] = u, x = link[x]; } } } void build(char *s) { memset(nxt, 0, sizeof nxt), memset(link, 0, sizeof link), memset(dp, 0, sizeof dp); n = strlen(s), m = 0; cur = ++m; for (int i = 0; i < n; i++) extend(s[i] - a ); memset(cnt, 0, sizeof cnt); for (int i = 1; i <= m; i++) cnt[dp[i]]++; for (int i = 1; i <= n; i++) cnt[i] += cnt[i - 1]; for (int i = m; i >= 1; i--) ord[cnt[dp[i]]--] = i; } int main() { scanf( %d , &t); while (t--) { scanf( %s , s); memset(occur, 0, sizeof occur); build(s); for (int i = m; i >= 1; i--) occur[link[ord[i]]] += occur[ord[i]]; long long ans = 0; for (int i = 1; i <= m; i++) ans += 1ll * occur[i] * occur[i] * (dp[i] - dp[link[i]]); printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef pair<long long, long long> pii; typedef vector<long long> vi; typedef vector<pii> vpii; typedef vector<vi> vvi; double prob[20][20]; double dp[(1 << 19)]; double pmove(long long prev_mask, long long j, long long n) { long long k = __builtin_popcount(prev_mask); long long den = k * (k - 1) / 2; double moveprob = 0; for (long long i = (0); i < (n); i += 1) { if ((1 << i) & prev_mask) { moveprob += prob[i][j]; } } return moveprob / (1.0 * den); } double get_ans(long long mask, long long n) { long long alive = __builtin_popcount(mask); if (alive == n) return 1; if (dp[mask] > -0.9) return dp[mask]; double ans = 0; for (long long i = (0); i < (n); i += 1) { if (!(mask & (1 << i))) { long long prev_mask = mask ^ (1 << i); ans += get_ans(prev_mask, n) * pmove(prev_mask, i, n); } } return dp[mask] = ans; } void solve() { long long n; cin >> n; memset(dp, -1, sizeof dp); for (long long i = (0); i < (n); i += 1) for (long long j = (0); j < (n); j += 1) cin >> prob[i][j]; for (long long i = (0); i < (n); i += 1) { printf( %.6lf , get_ans((1 << i), n)); } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 100005; bool powertwo(long long int n) { return (n and !(n & (n - 1))); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int arr[n]; map<long long int, long long int> mp; for (long long int i = 0; i < n; i++) { cin >> arr[i]; mp[arr[i]]++; } long long int g = 0, s = 0, b = 0; vector<long long int> v; for (auto it = mp.rbegin(); it != mp.rend(); it++) v.push_back(it->second); g = v[0]; long long int i = 1; while (s <= g and i < v.size()) { s += v[i]; i++; } while (b <= g and i < v.size()) { b += v[i]; i++; } while ((g + s + b + v[i]) <= n / 2 and i < v.size()) { b += v[i]; i++; } if ((g + s + b) > n / 2 or s < g or b < g) cout << 0 0 0 n ; else if (g == 0 or s == 0 or b == 0) cout << 0 0 0 n ; else cout << g << << s << << b << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct debugger { static void call(const char* it) {} template <typename T, typename... aT> static void call(const char* it, T a, aT... rest) { string b; for (; *it && *it != , ; ++it) if (*it != ) b += *it; cerr << b << = << a << ; call(++it, rest...); } }; int dr[] = {0, 1, 1, -1, 0, -1, -1, 1}; int dc[] = {1, 0, 1, 1, -1, 0, -1, -1}; char field[4][4]; int dt = 0; int tour(int r, int c, char c1, char c2, int d) { if (r < 0 || r > 3 || c < 0 || c > 3) return 0; if (field[r][c] == c2) { dt++; if (dt > 1) return 0; } else if (field[r][c] != c1) return 0; int ans = 1; ans += tour(r + dr[d], c + dc[d], c1, c2, d); return ans; } int main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); }; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) cin >> field[i][j]; int y = 0; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { for (int k = 0; k < 4; k++) { if (tour(i, j, x , . , k) == 3) { y = 1; break; } dt = 0; } if (y) break; } if (y) break; } if (y) cout << YES n ; else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Pnt { int x, y; Pnt() {} Pnt(int _x, int _y) { x = _x; y = _y; } bool operator<(const Pnt& o) const { if (x != o.x) return x < o.x; return y < o.y; } void show() { printf( Pnt %d %d n , x, y); } }; const int MAXN = 1000005; const int MAXS = 20; const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, 1, 0, -1}; int n, m; char s[MAXN]; int f[MAXN][2]; void preGao() {} void init() { if (scanf( %s , s) == EOF) exit(0); n = strlen(s); } void work() { f[n][0] = 0; f[n][1] = 2; for (int i = n - 1; i >= 0; i--) { f[i][0] = f[i + 1][0] + (s[i] == 1 ); f[i][0] = min(f[i][0], f[i + 1][1]); f[i][1] = f[i + 1][0] + 2 + (s[i] == 0 ); f[i][1] = min(f[i][1], f[i + 1][1] + (s[i] == 0 )); } printf( %d n , min(f[0][0], f[0][1])); } int main() { preGao(); while (true) { init(); work(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, r, x; int main() { cin >> a; b = 45 * 17 * 10000000000000000LL; r = 100000000000000000LL - 1; x = b % a; cout << a - x << << a - x + r; return 0; }
|
#include <bits/stdc++.h> using namespace std; void sol() { int n, m, k; cin >> n >> m >> k; int a[n + 1][m + 1]; for (int i = 1; i <= n; i++) for (int ii = 1; ii <= m; ii++) cin >> a[i][ii]; for (int i = 1; i <= k; i++) { int x, y; cin >> y; x = 1; while (x != n + 1) { if (a[x][y] == 1) a[x][y] = 2, y++; else if (a[x][y] == 2) x++; else a[x][y] = 2, y--; } cout << y << ; } cout << n ; } int main() { std::ios_base::sync_with_stdio(0); std::cin.tie(0); std::cout.tie(0); ; int tc = 1; while (tc--) sol(); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:42:00 06/18/2014
// Design Name: timer_counter
// Module Name: F:/ISE/work/final_exp/washing_machine/timer_counter_test.v
// Project Name: washing_machine
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timer_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_counter_test;
// Inputs
reg CP;
reg [7:0] RS;
// Outputs
wire [7:0] Q;
wire QCC;
parameter PERIOD = 10;
// Instantiate the Unit Under Test (UUT)
timer_counter uut (
.CP(CP),
.RS(RS),
.Q(Q),
.QCC(QCC)
);
always begin
CP = 1;
#(PERIOD/2);
CP = 0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
CP = 0;
RS = 8'b00010101;
// Wait 100 ns for global reset to finish
#300;
RS = 8'b00110001;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; const int MAXN = 100005; int tz[4 * MAXN], tx[4 * MAXN], ty[4 * MAXN]; int cntz(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (tl == l && r == tr) return tz[v]; int tm = (tl + tr) / 2; return cntz(2 * v, tl, tm, l, min(tm, r)) + cntz(2 * v + 1, tm + 1, tr, max(tm + 1, l), r); } int cnty(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (tl == l && r == tr) return ty[v]; int tm = (tl + tr) / 2; return cnty(2 * v, tl, tm, l, min(tm, r)) + cnty(2 * v + 1, tm + 1, tr, max(tm + 1, l), r); } int cntx(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (tl == l && r == tr) return tx[v]; int tm = (tl + tr) / 2; return cntx(2 * v, tl, tm, l, min(tm, r)) + cntx(2 * v + 1, tm + 1, tr, max(tm + 1, l), r); } void buildz(int v, int tl, int tr) { if (tl == tr) tz[v] = (s[tl] == z ); else { int tm = (tl + tr) / 2; buildz(2 * v, tl, tm); buildz(2 * v + 1, tm + 1, tr); tz[v] = tz[2 * v] + tz[2 * v + 1]; } } void buildy(int v, int tl, int tr) { if (tl == tr) ty[v] = (s[tl] == y ); else { int tm = (tl + tr) / 2; buildy(2 * v, tl, tm); buildy(2 * v + 1, tm + 1, tr); ty[v] = ty[2 * v] + ty[2 * v + 1]; } } void buildx(int v, int tl, int tr) { if (tl == tr) tx[v] = (s[tl] == x ); else { int tm = (tl + tr) / 2; buildx(2 * v, tl, tm); buildx(2 * v + 1, tm + 1, tr); tx[v] = tx[2 * v] + tx[2 * v + 1]; } } int main() { cin >> s; int n, l = s.length(); buildz(1, 0, l - 1); buildy(1, 0, l - 1); buildx(1, 0, l - 1); cin >> n; for (int i = 0, a, b; i < n; ++i) { cin >> a >> b; int z = cntz(1, 0, l - 1, a - 1, b - 1); int y = cnty(1, 0, l - 1, a - 1, b - 1); int x = cntx(1, 0, l - 1, a - 1, b - 1); int t = min(x, min(y, z)); z -= t; y -= t; x -= t; if (b - a + 1 <= 2 || (z <= 1 && x <= 1 && y <= 1)) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace ::std; const long long maxn = 1e5 + 500; const long long mod = 1e9 + 7; const long long inf = 1e9 + 500; const long long rad = 330; long long a[maxn]; long long t[maxn]; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { if (a.first / rad == b.first / rad) { return (a.second < b.second); } return (a.first < b.first); } long long ml[maxn]; pair<long long, long long> sque[maxn]; map<pair<long long, long long>, long long> anss; long long lastid[maxn]; long long nextid[maxn]; long long id[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; for (long long i = 1; i <= n; i++) { cin >> t[i]; } for (long long i = 1; i <= n; i++) { cin >> a[i]; if (t[i] == 2) { a[i] *= -1; } } for (long long i = 1; i <= n; i++) { a[i] += a[i - 1]; } vector<long long> vec; for (long long i = 0; i <= n; i++) { vec.push_back(a[i]); } { sort(vec.begin(), vec.end()); auto it = unique(vec.begin(), vec.end()); vec.resize(distance(vec.begin(), it)); } vector<long long>::iterator it; for (long long i = 0; i <= n; i++) { id[i] = lower_bound(vec.begin(), vec.end(), a[i]) - vec.begin(); it = lower_bound(vec.begin(), vec.end(), a[i] + k); if (it != vec.end() && (*it) == a[i] + k) { nextid[i] = it - vec.begin(); } else { nextid[i] = maxn - 1; } it = lower_bound(vec.begin(), vec.end(), a[i] - k); if (it != vec.end() && (*it) == a[i] - k) { lastid[i] = it - vec.begin(); } else { lastid[i] = maxn - 1; } } long long q; cin >> q; vector<pair<long long, long long> > que; for (long long i = 0; i < q; i++) { long long l, r; cin >> l >> r; l--; sque[i] = make_pair(l, r); que.push_back(make_pair(l, r)); } sort(que.begin(), que.end(), cmp); long long res = 0; long long l = 0; long long r = 0; for (auto b : que) { long long L = b.first; long long R = b.second; while (r <= R) { res += ml[lastid[r]]; ml[id[r]]++; r++; } while (L < l) { l--; res += ml[nextid[l]]; ml[id[l]]++; } while (R + 1 < r) { r--; ml[id[r]]--; res -= ml[lastid[r]]; } while (l < L) { ml[id[l]]--; res -= ml[nextid[l]]; l++; } anss[make_pair(L, R)] = res; } for (long long i = 0; i < q; i++) { cout << anss[sque[i]] << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, a, x, b, y; cin >> n >> a >> x >> b >> y; while (1) { if (a == b) { cout << YES n ; return 0; } if (a == x || b == y) { break; } if (++a > n) { a = 1; } if (--b < 1) { b = n; } } cout << NO n ; return 0; }
|
// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2_____9.000______0.000______50.0______327.887____300.991
// CLK_OUT3____18.000______0.000______50.0______295.409____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module ClockDivider_clk_wiz
(// Clock in ports
input clk,
// Clock out ports
output clk_vga,
output clk_cpu,
output clk_2cpu
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_ClockDivider),
.I (clk));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (54.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (120),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (60),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ClockDivider),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_vga_ClockDivider),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_cpu_ClockDivider),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_2cpu_ClockDivider),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ClockDivider),
.CLKIN1 (clk_ClockDivider),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ClockDivider),
.I (clkfbout_ClockDivider));
BUFG clkout1_buf
(.O (clk_vga),
.I (clk_vga_ClockDivider));
BUFG clkout2_buf
(.O (clk_cpu),
.I (clk_cpu_ClockDivider));
BUFG clkout3_buf
(.O (clk_2cpu),
.I (clk_2cpu_ClockDivider));
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const double PI = acos(-1.0); using namespace std; const double EPS = 1e-9; const int N = 2e5 + 9; int a[N], n, p, k; long long sum[N], v[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> p >> k; for (int i = 1; i <= n; i++) cin >> a[i], v[i] = 0; sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) sum[i] = a[i] + sum[i - 1]; for (int i = k; i <= n; i++) { v[i] = a[i] + v[i - k]; } long long ans = 0; for (int i = 1; i <= n; i++) { if (v[i] + sum[i % k] <= p) ans = i; } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300010; struct Segment { int l, r; int id; bool operator<(const Segment &o) const { return l < o.l; } } a[maxn]; int main() { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { scanf( %d %d , &a[i].l, &a[i].r); a[i].id = i + 1; } sort(a, a + n); priority_queue<int, vector<int>, greater<int> > que; int ans = -1; int L, R; for (int i = 0; i < n; i++) { que.push(a[i].r); while (que.size() && que.top() == a[i].l - 1) { que.pop(); } while (que.size() > k) { que.pop(); } if (que.size() == k) { int tmp = que.top() - a[i].l + 1; if (tmp > ans) { ans = tmp; L = a[i].l; R = que.top(); } } } if (ans == -1) { cout << 0 << endl; for (int i = 1; i <= k; i++) { printf( %d , i); } } else { cout << ans << endl; int cnt = 0; for (int i = 0; i < n; i++) { if (a[i].l <= L && a[i].r >= R) { printf( %d , a[i].id); cnt++; if (cnt == k) break; } } } return 0; }
|
// $Id: rtr_flags_mux.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for extracting the flags for a given port and packet class
//==============================================================================
module rtr_flags_mux
(sel_mc, route_op, route_orc, flags_op_opc, flags);
`include "c_functions.v"
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of input and output ports on router
parameter num_ports = 5;
// width of flags
parameter width = 1;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
// current message class
input [0:num_message_classes-1] sel_mc;
// destination port
input [0:num_ports-1] route_op;
// destination resource class
input [0:num_resource_classes-1] route_orc;
// bit field of output VC flags of interest
input [0:num_ports*num_packet_classes*width-1] flags_op_opc;
// subset of bits that we are interested in
output [0:width-1] flags;
wire [0:width-1] flags;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire [0:num_packet_classes*width-1] flags_opc;
c_select_1ofn
#(.num_ports(num_ports),
.width(num_packet_classes*width))
flags_opc_sel
(.select(route_op),
.data_in(flags_op_opc),
.data_out(flags_opc));
wire [0:num_resource_classes*width-1] flags_orc;
c_select_1ofn
#(.num_ports(num_message_classes),
.width(num_resource_classes*width))
flags_orc_sel
(.select(sel_mc),
.data_in(flags_opc),
.data_out(flags_orc));
c_select_1ofn
#(.num_ports(num_resource_classes),
.width(width))
flags_sel
(.select(route_orc),
.data_in(flags_orc),
.data_out(flags));
endmodule
|
#include <bits/stdc++.h> namespace ZDY { #pragma GCC optimize(3) template <class T> __inline__ __attribute__((always_inline)) T ABS(T x) { return x > 0 ? x : -x; } template <class T> __inline__ __attribute__((always_inline)) T MAX(T x, T y) { return x > y ? x : y; } template <class T> __inline__ __attribute__((always_inline)) T MIN(T x, T y) { return x < y ? x : y; } template <class T> __inline__ __attribute__((always_inline)) T GCD(T x, T y) { return y ? GCD(y, x % y) : x; } template <class T> __inline__ __attribute__((always_inline)) void SWAP(T& x, T& y) { T t = x; x = y; y = t; } } // namespace ZDY using namespace ZDY; using namespace std; namespace IO { const char* ln = n ; const int str = 1 << 20; struct IN { char buf[str], *s, *t; bool _; IN() : s(buf), t(buf), _(0) {} __inline__ __attribute__((always_inline)) char gc() { return s == t && ((t = (s = buf) + fread(buf, 1, str, stdin)) == s) ? EOF : (*s++); } IN& operator>>(char& ch) { if (_) return *this; char c; while ((c = gc()) != EOF && isspace(c)) ; if (c == EOF) _ = 1; else ch = c; return *this; } IN& operator>>(char* ch) { memset(ch, 0, sizeof(ch)); if (_) return *this; char c; while ((c = gc()) != EOF && isspace(c)) ; if (c == EOF) return _ = 1, *this; *ch = c; ch++; while ((c = gc()) != EOF && !isspace(c)) *ch = c, ch++; if (c == EOF) _ = 1; return *this; } IN& operator>>(string& ch) { if (_) return *this; char c; while ((c = gc()) != EOF && isspace(c)) ; if (c == EOF) return _ = 1, *this; ch += c; while ((c = gc()) != EOF && !isspace(c)) ch += c; if (c == EOF) _ = 1; return *this; } template <typename T> IN& operator>>(T& x) { if (_) return *this; char c = gc(); bool ff = 0; while (c != EOF && (c < 0 || c > 9 )) ff ^= (c == - ), c = gc(); if (c == EOF) { _ = 1; return *this; } x = 0; while (c != EOF && 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + c - 48, c = gc(); if (c == EOF) _ = 1; if (ff) x = -x; return *this; } } in; struct OUT { char buf[str], *s, *t; OUT() : s(buf), t(buf + str) {} ~OUT() { fwrite(buf, 1, s - buf, stdout); } void pt(char c) { (s == t) ? (fwrite(s = buf, 1, str, stdout), *s++ = c) : (*s++ = c); } OUT& operator<<(const char* s) { while (*s) pt(*s++); return *this; } OUT& operator<<(char* s) { while (*s) pt(*s++); return *this; } OUT& operator<<(string s) { for (int i = 0; s[i]; i++) pt(s[i]); return *this; } template <typename T> OUT& operator<<(T x) { if (!x) return pt( 0 ), *this; if (x < 0) pt( - ), x = -x; char a[30], t = 0; while (x) a[t++] = x % 10, x /= 10; while (t--) pt(a[t] + 0 ); return *this; } } out; } // namespace IO using namespace IO; int n, b[1000011], a[1000011], cnt = 0, head[1000011]; bool cmp(int x, int y) { return a[x] > a[y]; } bool cmp2(int x, int y) { return a[x] < a[y]; } struct edge { int to, nxt; } e[1000011 * 2]; void add(int x, int y) { e[++cnt].to = y; e[cnt].nxt = head[x]; head[x] = cnt; } int f[1000011], sz[1000011]; int gf(int x) { return (x == f[x]) ? x : (f[x] = gf(f[x])); } bool v[1000011]; int main() { in >> n; for (int i = 1; i <= n; ++i) in >> a[i], b[i] = i; sort(b + 1, b + n + 1, cmp2); int x, y; for (int i = 1; i <= n - 1; ++i) in >> x >> y, add(x, y), add(y, x); long long ans = 0; for (int i = 1; i <= n; ++i) f[i] = i, sz[i] = 1; for (int i = 1; i <= n; ++i) { x = b[i]; v[x] = 1; int t = 0; for (int i = head[x], to; to = e[i].to, i; i = e[i].nxt) if (v[to]) { ans += 1ll * sz[x] * sz[gf(to)] * a[x]; sz[x] += sz[gf(to)]; f[gf(to)] = x; } } memset(v, 0, sizeof(v)); for (int i = 1; i <= n; ++i) f[i] = i, sz[i] = 1; sort(b + 1, b + n + 1, cmp); for (int i = 1; i <= n; ++i) { x = b[i]; v[x] = 1; int t = 0; for (int i = head[x], to; to = e[i].to, i; i = e[i].nxt) if (v[to]) { ans -= 1ll * sz[x] * sz[gf(to)] * a[x]; sz[x] += sz[gf(to)]; f[gf(to)] = x; } } out << ans << ln; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/09/2017 08:42:46 PM
// Design Name:
// Module Name: pulse_synchronise_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pulse_synchronise_tb();
reg clk_in;
reg clk_out;
reg pulse_in;
reg rst;
wire pulse_out;
pulse_synchronise DUT0(
.clk_in(clk_in),
.clk_out(clk_out),
.rst(rst),
.pulse_in(pulse_in),
.pulse_out(pulse_out)
);
initial begin
$dumpfile("snychronise.dump");
$dumpvars(0,pulse_synchronise);
end
initial begin
clk_in=0;
repeat(200) #10 clk_in=~clk_in;
repeat(100) #20 clk_in=~clk_in;
end
initial begin
clk_out=0;
repeat(100) #20 clk_out=~clk_out;
repeat(200) #10 clk_out=~clk_out;
end
initial begin
rst=1;
#50 rst=0;
end
initial begin
pulse_in=0;
#110 pulse_in=1;
#20 pulse_in=0;
#260 pulse_in=1;
#20 pulse_in=0;
#1650 pulse_in=1;
#40 pulse_in=0;
#200 pulse_in=1;
#40 pulse_in=0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_1_V
`define SKY130_FD_SC_MS__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_1_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void pv(T a, T b) { for (T i = a; i != b; ++i) cerr << *i << ; cerr << endl; } const int MAX_N = 100000; vector<int> primes; bool isPrime[MAX_N]; void MakePrimes() { for (int i = 0; i < (int)(MAX_N); ++i) isPrime[i] = true; isPrime[0] = isPrime[1] = false; for (int i = 2; i < MAX_N; i++) { if (isPrime[i]) { for (int j = i + i; j < MAX_N; j += i) isPrime[j] = false; } } for (int i = 0; i < (int)(MAX_N); ++i) if (isPrime[i]) primes.push_back(i); } bool a(int n) { if (n < MAX_N) return isPrime[n]; for (int i = 0; primes[i] * primes[i] <= n; i++) if (n % primes[i] == 0) return false; return true; } const int MILLION = 1000000; int h[] = { 0, 39176, 74417, 108284, 141503, 174194, 206333, 238261, 269760, 301101, 332181, 363080, 393993, 424569, 454974, 485275, 515414, 545501, 575503, 605357, 635171, 664771, 694490, 723896, 753318, 782754, 812028, 841364, 870514, 899686, 928780, 957871, 986746, 1015619, 1044521, 1073174, 1101903, 1130652, 1159339, 1188093, 1216688, 1245272, 1273689, 1302081, 1330570, 1358925, 1387240, 1415626, 1443939, 1472195, 1500453, 1528622, 1556702, 1584772, 1612824, 1640857, 1668892, 1696863, 1724880, 1752772, 1780671, 1808647, 1836360, 1864207, 1892075, 1919906, 1947727, 1975510, 2003304, 2031020, 2058719, 2086330, 2113990, 2141713, 2169247, 2196835, 2224515, 2252025, 2279483, 2306931, 2334374, 2361872, 2389450, 2416904, 2444352, 2471679, 2499026, 2526330, 2553802, 2581128, 2608394, 2635613, 2662840, 2690185, 2717374, 2744682, 2771910, 2799109, 2826276, 2853362, 2880505, 2907606, 2934703, 2961881, 2988902, 3016009, 3043022, 3069997, 3097083, 3124226, 3151359, 3178276, 3205350, 3232326, 3259118, 3286023, 3312951, 3339778, 3366670, 3393551, 3420476, 3447272, 3474095, 3500974, 3527908, 3554739, 3581527, 3608315, 3635172, 3662084, 3688865, 3715571, 3742387, 3769101, 3795810, 3822594, 3849184, 3875855, 3902460, 3929085, 3955921, 3982460, 4009128, 4035734, 4062451, 4089090, 4115722, 4142364, 4168923, 4195422, 4221985, 4248402, 4274957, 4301295, 4327912, 4354389, 4380845, 4407487, 4433902, 4460241, 4486724, 4513194, 4539593, 4566061, 4592654, 4619006, 4645360, 4671705, 4698103, 4724481, 4750950, 4777296, 4803668, 4830058, 4856492, 4882798, 4909157, 4935488, 4961878, 4988226, 5014695, 5040863, 5067205, 5093333, 5119591, 5145981, 5172232, 5198500, 5224741, 5250964, 5277359, 5303300, 5329410, 5355703, 5381929, 5408176, 5434359, 5460458, 5486492, 5512631, 5538821, 5564989, 5591257, 5617364, 5643587, 5669724, 5695725, 5721870, 5747922, 5773921, 5800089, 5826127, 5852352, 5878520, 5904577, 5930672, 5956845, 5982939, 6008887, 6034853, 6060852, 6086846, 6112891, 6139005, 6164976, 6191134, 6217047, 6243137, 6268950, 6294880, 6320783, 6346739, 6372759, 6398760, 6424585, 6450524, 6476474, 6502519, 6528444, 6554452, 6580260, 6606273, 6632211, 6657923, 6683806, 6709795, 6735695, 6761489, 6787249, 6813192, 6838975, 6864928, 6890595, 6916351, 6942266, 6968229, 6994053, 7019911, 7045744, 7071649, 7097378, 7123329, 7149099, 7175070, 7200837, 7226696, 7252624, 7278251, 7304018, 7329881, 7355504, 7381276, 7406982, 7432639, 7458445, 7484264, 7509988, 7535700, 7561435, 7587022, 7612748, 7638354, 7664134, 7689731, 7715474, 7741178, 7766793, 7792385, 7818155, 7843890, 7869478, 7895233, 7920913, 7946432, 7972124, 7997861, 8023413, 8049029, 8074668, 8100189, 8125719, }; int hard(int n) { int k = 0; while (k * MILLION <= n) { k++; } k--; int ans = h[k]; if (k == 0) { if (2 <= n) if (a(2)) ++ans; for (int i = 5; i <= n; i += 4) { if (a(i)) ++ans; } return ans; } else { for (int i = k * MILLION + 1; i <= n; i += 4) { if (a(i)) ++ans; } return ans; } } int main() { MakePrimes(); int L, R; cin >> L >> R; cout << hard(R) - hard(L - 1) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e, f; void read() { cin >> a >> b >> c >> d >> e >> f; } void solve() { int res = 0; res += (a + b + f) * (a + b + f); res -= f * f; res -= b * b; res -= d * d; cout << res << endl; } int main() { read(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int blocksize; int msmo7; struct query { int start, en, idxofquery, blockidx, mincolor; query() {} query(int l, int r, int i, int adeh) { start = l; en = r; idxofquery = i; blockidx = l / blocksize; mincolor = adeh; } bool operator<(const query& q) const { if (start / blocksize != q.start / blocksize) return start / blocksize < q.start / blocksize; else return en < q.en; } }; query queries[100005]; vector<int> arr[100005]; int subtree[100005]; int idxinorder[100005]; int treearray[100005]; int color[100005]; int ansforquery; int answers[100005]; int bit[100010]; int freq[100005]; const int maxn = 1e5 + 5; void update(int idx, int val) { for (; idx <= maxn; idx += (idx & -idx)) bit[idx] += val; } int getsum(int idx) { int sum = 0; for (; idx; idx -= (idx & -idx)) sum += bit[idx]; return sum; } int nid = 0; void dfs(int s, int parent) { subtree[s] = 1; treearray[nid++] = s; idxinorder[s] = nid - 1; for (int i = 0; i < arr[s].size(); ++i) { int to = arr[s][i]; if (to != parent) { dfs(to, s); subtree[s] += subtree[to]; } } } void add(int valueofpos) { update(maxn - freq[color[valueofpos]]++, -1); update(maxn - freq[color[valueofpos]], 1); } void rem(int valueofpos) { update(maxn - freq[color[valueofpos]]--, -1); update(maxn - freq[color[valueofpos]], 1); } int main() { int n, m; scanf( %d , &n); scanf( %d , &m); for (int i = 1; i <= n; ++i) scanf( %d , &color[i]); int u, v; for (int i = 1; i < n; ++i) { scanf( %d , &u); scanf( %d , &v); arr[u].push_back(v); arr[v].push_back(u); } dfs(1, -1); blocksize = sqrt(n); int k; for (int i = 0; i < m; ++i) { scanf( %d , &v); scanf( %d , &k); queries[i].start = idxinorder[v]; queries[i].en = queries[i].start + subtree[v] - 1; queries[i].idxofquery = i; queries[i].mincolor = k; } sort(queries, queries + m); int curl = 0; int curr = -1; for (int i = 0; i < m; ++i) { query& qu = queries[i]; while (curl > qu.start) add(treearray[--curl]); while (curr < qu.en) add(treearray[++curr]); while (curl < qu.start) rem(treearray[curl++]); while (curr > qu.en) rem(treearray[curr--]); answers[qu.idxofquery] = getsum(maxn - qu.mincolor); } for (int i = 0; i < m; ++i) printf( %d n , answers[i]); return 0; }
|
// oversampling.v
module oversampling
(
input [7:0]sclk,
input res,
input enable,
input sdata,
output [7:0]samples,
output reg [7:0]trans
);
reg [7:0]s1; // fixed position in FPGA
always @(posedge sclk[0]) s1[0] <= sdata;
always @(posedge sclk[1]) s1[1] <= sdata;
always @(posedge sclk[2]) s1[2] <= sdata;
always @(posedge sclk[3]) s1[3] <= sdata;
always @(posedge sclk[4]) s1[4] <= sdata;
always @(posedge sclk[5]) s1[5] <= sdata;
always @(posedge sclk[6]) s1[6] <= sdata;
always @(posedge sclk[7]) s1[7] <= sdata;
reg [7:0]s2; // fixed position in FPGA
always @(posedge sclk[0]) s2[0] <= s1[0];
always @(posedge sclk[0]) s2[1] <= s1[1];
always @(posedge sclk[0]) s2[2] <= s1[2];
always @(posedge sclk[0]) s2[3] <= s1[3];
always @(posedge sclk[0]) s2[4] <= s1[4];
always @(posedge sclk[1]) s2[5] <= s1[5];
always @(posedge sclk[2]) s2[6] <= s1[6];
always @(posedge sclk[3]) s2[7] <= s1[7];
reg [7:0]s3;
reg [7:0]s4;
always @(posedge sclk[0] or posedge res)
begin
if (res)
begin
s3 <= 0;
s4 <= 0;
end
else if (enable)
begin
s3 <= s2;
s4 <= s3;
end
end
assign samples = s4;
// xor transition detector
wire [7:0]t;
assign t[0] = s3[0] ^ s3[1];
assign t[1] = s3[1] ^ s3[2];
assign t[2] = s3[2] ^ s3[3];
assign t[3] = s3[3] ^ s3[4];
assign t[4] = s3[4] ^ s3[5];
assign t[5] = s3[5] ^ s3[6];
assign t[6] = s3[6] ^ s3[7];
assign t[7] = s3[7] ^ s2[0];
always @(posedge sclk[0]) if (res) trans <= 0; else if (enable) trans <= t;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_BLACKBOX_V
`define SKY130_FD_SC_LS__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_BLACKBOX_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_async_fifo
*/
module test_axis_async_frame_fifo_64;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_status_overflow;
wire s_status_bad_frame;
wire s_status_good_frame;
wire m_status_overflow;
wire m_status_bad_frame;
wire m_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(
async_rst,
s_clk,
m_clk,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
s_status_overflow,
s_status_bad_frame,
s_status_good_frame,
m_status_overflow,
m_status_bad_frame,
m_status_good_frame
);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
$dumpvars(0, test_axis_async_frame_fifo_64);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.size(); int a = 0, b = 0, c = 0, d = 0; for (int i = 0; i < n; i++) { if (s[i] >= A && s[i] <= Z ) a = 1; else if (s[i] >= a && s[i] <= z ) b = 1; else if (s[i] >= 0 && s[i] <= 9 ) c = 1; } if (n >= 5) { if (a && b && c) cout << Correct << endl; else cout << Too weak << endl; } else cout << Too weak << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; n--; t--; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i <= n; i) { if (i == t) { cout << YES n ; return 0; } else { if (i < n) i += arr[i]; else break; } } cout << NO n ; return 0; }
|
/*
* Copyright (c) 2005 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* tern7.v
* This tests types.
*/
module main;
reg b, c, d, e;
wire a = b ? c : (d&e);
reg [4:0] tmp;
reg ref;
initial begin
// Do an exaustive scan of the possible values.
for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) begin
b <= tmp[0];
c <= tmp[1];
d <= tmp[2];
e <= tmp[3];
ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]);
#1 if (ref !== a) begin
$display("FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b",
a, b, c, d, e);
$finish;
end
end // for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1)
b <= 0;
c <= 1;
d <= 1;
e <= 0;
#1 if (a !== 1'b0) begin
$display("FAILED (1)");
$finish;
end
e <= 1;
#1 if (a !== 1'b1) begin
$display("FAILED (2)");
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int maxn = 100086; const double PI = atan(1.0) * 4.0; const double eps = 1e-9; const long long mod = 1000000007; const int maxe = 10086 * 2; long long quick_pow(long long a, long long n) { long long ret = 1; while (n) { if (n & 1) ret = ret * a % mod; a = a * a % mod; n >>= 1; } return ret; } char s[maxn]; int n, num[5]; int main() { scanf( %d%s , &n, s); memset(num, 0, sizeof num); for (int i = 0; i < n; i++) { if (s[i] == A ) num[0]++; else if (s[i] == G ) num[1]++; else if (s[i] == T ) num[2]++; else num[3]++; } int maxx = -1; for (int i = 0; i < 4; i++) maxx = max(maxx, num[i]); int a = 0; for (int i = 0; i < 4; i++) if (maxx == num[i]) a++; cout << quick_pow(a, n) << endl; }
|
#include<bits/stdc++.h> using namespace std; int n; inline int lst(int i){return i==1?n:i-1;} inline int nxt(int i){return i==n?1:i+1;} inline int lst(int i,int d){return (((i-d-1)%n+n)%n+1);} inline int nxt(int i,int d){return ((i+d-1)%n+1);} inline int getval(){ fflush(stdout); int val; scanf( %d ,&val); return val; } inline int curval(int i){ printf( ? %d n n ,i); return getval(); } inline int lstval(int i){ printf( ? %d n n ,lst(i)); return getval(); } inline int nxtval(int i){ printf( ? %d n n ,nxt(i)); return getval(); } int k; int a[200],b[200]; inline void ansis(int ans) { printf( ! %d n ,ans); exit(0); } inline void findit(int pos,int val,int len) { if (val>k){ int lef=1,rig=len,mid; while (lef<=rig){ mid=((lef+rig)>>1); int curpos=lst(pos,mid); int cur=curval(curpos); if (cur==k) ansis(curpos); if (cur>k) lef=mid+1; else rig=mid-1; } }else{ int lef=1,rig=len,mid; while (lef<=rig){ mid=((lef+rig)>>1); int curpos=nxt(pos,mid); int cur=curval(curpos); if (cur==k) ansis(curpos); if (cur<k) lef=mid+1; else rig=mid-1; } } } int main() { scanf( %d%d ,&n,&k); curval(1); int pos=1; for (int t=1;t<=950;t+=2){ int val1=curval(pos); if (val1!=k) { findit(pos,val1,t); return 0; } int val2=nxtval(pos); if (val2!=k) { findit(nxt(pos),val2,t+1); return 0; } pos=nxt(pos,t*2+1); } }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int MAXN = 500005; struct seg { int typ; int s, e; bool operator<(const seg &x) const { return s < x.s; } bool operator!=(const seg &x) const { return typ != x.typ || s != x.s || e != x.e; } }; int n, a[MAXN]; int ret[MAXN]; vector<int> pos[MAXN]; int b[MAXN]; int solve() { for (int i = 0; i < n + 2; i++) pos[a[i]].push_back(i); int mxv = *max_element(a + 1, a + n + 1); set<seg> s; s.insert({0, 0, n + 1}); set<int> rems; for (int i = 1; i <= n; i++) rems.insert(i); auto MARK = [&](int s, int e, int x) { auto itr = rems.lower_bound(s); while (itr != rems.end() && *itr <= e) { ret[*itr] = x; itr = rems.erase(itr); } }; int ret = 0; auto FUCK = [&](int s, int e, int i) { if (s > e) return; int len = e - s + 1; ret = max(ret, (len + 1) / 2); if (b[s - 1] && b[e + 1]) { MARK(s, e, i); return; } if (!b[s - 1] && !b[e - 1]) return; if (b[s - 1]) { MARK(s, s + len / 2 - 1, i); } if (b[e + 1]) { MARK(e - len / 2 + 1, e, i); } }; for (int i = mxv; i >= 0; i--) { vector<int> lookup; auto INSERT = [&](seg x, int coalL, int coalR) { if (x.s > x.e) return; if (coalR) { auto l = s.lower_bound(x); if (l != s.end() && l->typ == x.typ && x.e + 1 == l->s) { x.e = l->e; s.erase(l); } else if (x.e + 1 < n + 2 && x.typ == b[x.e + 1]) x.e++; } if (coalL) { auto l = s.lower_bound(x); if (l != s.begin() && prev(l)->typ == x.typ && x.s - 1 == prev(l)->e) { x.s = prev(l)->s; s.erase(prev(l)); } else if (x.s - 1 >= 0 && x.typ == b[x.s - 1]) x.s--; } lookup.push_back(x.s); if (x.s < x.e) { s.insert(x); } }; for (auto &j : pos[i]) { b[j] = 1; auto itr = s.lower_bound({0, j + 1, -1}); if (itr != s.begin() && prev(itr)->e >= j) { auto rem = *--itr; s.erase(itr); INSERT((seg){rem.typ, rem.s, j - 1}, 1, 0); INSERT((seg){rem.typ, j + 1, rem.e}, 0, 1); } INSERT({1, j, j}, 1, 1); } for (auto &l : lookup) { auto itr = s.lower_bound({-1, l + 1, -1}); if (itr != s.begin()) itr--; if (itr->typ) MARK(itr->s, itr->e, i); if (itr != s.begin()) { FUCK(prev(itr)->e + 1, itr->s - 1, i); } if (next(itr) != s.end()) { FUCK(itr->e + 1, next(itr)->s - 1, i); } } } return ret; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } a[0] = a[1]; a[n + 1] = a[n]; vector<int> crd(a + 1, a + n + 1); sort((crd).begin(), (crd).end()); crd.resize(unique((crd).begin(), (crd).end()) - crd.begin()); for (int i = 0; i < n + 2; i++) { a[i] = lower_bound((crd).begin(), (crd).end(), a[i]) - crd.begin(); } printf( %d n , solve()); for (int i = 1; i <= n; i++) printf( %d , crd[ret[i]]); }
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#include <bits/stdc++.h> using namespace std; int a[111111]; map<int, int> cnt; map<int, int> m; int main() { int n; scanf( %d , &n); m.clear(); cnt.clear(); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int ma = INT_MIN; for (int i = 0; i < n; i++) { m[a[i]] += 1; ma = max(ma, a[i]); } vector<int> v; for (int i = 0; i < n; i++) if (cnt[a[i]] != 1) { v.push_back(a[i]); cnt[a[i]] = 1; m[a[i]] = m[a[i]] - 1; } cnt.clear(); for (int i = n - 1; i >= 0; i--) if (a[i] != ma && m[a[i]] > 0 && cnt[a[i]] != 1) { v.push_back(a[i]); cnt[a[i]] = 1; } printf( %d n , v.size()); for (int i = 0; i < v.size(); i++) printf( %d , v[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 8e5 + 10; struct Node { int sum; int free; int carry; Node() { sum = 0; free = 1; carry = 0; } Node(int x) { sum = x; if (x == 0) { free = 1; carry = 0; } else { free = 0; carry = x - 1; } } Node(int sum_, int free_, int carry_) { sum = sum_; free = free_; carry = carry_; } friend Node conq(const Node &l, const Node &r) { if (l.carry <= r.free) { return Node(l.sum + r.sum, l.free + r.free - l.carry, r.carry); } else { return Node(l.sum + r.sum, l.free, r.carry + l.carry - r.free); } } }; namespace ST { int cnt = 0; int a[N]; Node t[4 * N]; void pull(int v) { t[v] = conq(t[2 * v + 1], t[2 * v + 2]); } void build(int v, int l, int r) { if (l + 1 == r) { t[v] = Node(); } else { int m = (r + l) >> 1; build(2 * v + 1, l, m); build(2 * v + 2, m, r); pull(v); } } void init() { build(0, 0, N); } void add(int v, int l, int r, int pos, int val) { if (l + 1 == r) { cnt += val; a[l] += val; t[v] = Node(a[l]); } else { int m = (r + l) >> 1; if (pos < m) { add(2 * v + 1, l, m, pos, val); } else { add(2 * v + 2, m, r, pos, val); } pull(v); } } void query(int v, int l, int r, int ql, int qr, Node &ans) { if (r <= ql || qr <= l) { return; } else if (ql <= l && r <= qr) { ans = conq(ans, t[v]); } else { int m = (r + l) >> 1; query(2 * v + 1, l, m, ql, qr, ans); query(2 * v + 2, m, r, ql, qr, ans); } } int ok(int pref) { Node ans; query(0, 0, N, 0, pref + 1, ans); return ans.carry == 0 && ans.sum == cnt; } void add(int pos, int val) { add(0, 0, N, pos, val); } int solve() { int l = -1; int r = N - 1; while (r - l > 1) { int m = (r + l) >> 1; if (ok(m)) { r = m; } else { l = m; } } assert(ok(r)); if (l > 0) assert(!ok(l)); return r; } } // namespace ST signed main() { ios_base::sync_with_stdio(false); cin.tie(0); ST::init(); int n, k, q; cin >> n >> k >> q; set<pair<int, int>> s; while (q--) { int x, y; cin >> x >> y; int pos = y + abs(x - k); if (!s.count({x, y})) { ST::add(pos, 1); s.insert({x, y}); } else { ST::add(pos, -1); s.erase({x, y}); } cout << max(0, ST::solve() - n) << n ; } }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline void checkmin(T &a, T b) { if (a > b) a = b; } const int N = 1001; char buf[N][N], bf[N][N] = {0}; int n, m, cnt = 0; short mx[N * N], my[N * N]; int msz = 0; bool isab(int a, int b) { if (a == n - 1 || b == m - 1) return false; if (buf[a + 1][b] == # && buf[a][b + 1] == # && buf[a][b] == # ) return true; return false; } bool iscd(int c, int d) { if (c == 0 || d == 0) return false; if (buf[c - 1][d] == # && buf[c][d - 1] == # && buf[c][d] == # ) return true; return false; } void findp(vector<int> &a, vector<int> &b, vector<int> &c, vector<int> &d) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (isab(i, j)) { bf[i][j] |= 1; } if (iscd(i, j)) { bf[i][j] |= 2; } if (buf[i][j] == # ) { mx[msz] = i; my[msz] = j; msz++; cnt++; } } } int maxnn = 3; for (int i = 0; i < n; i++) { int nn = 0; for (int j = 0; j < m; j++) { if (bf[i][j] & 1) nn++; if (nn > maxnn) bf[i][j] &= (~1); } } for (int j = 0; j < m; j++) { int nn = 0; for (int i = 0; i < n; i++) { if (bf[i][j] & 1) nn++; if (nn > maxnn) bf[i][j] &= (~1); } } for (int i = n - 1; i >= 0; i--) { int nn = 0; for (int j = m - 1; j >= 0; j--) { if (bf[i][j] & 2) nn++; if (nn > maxnn) bf[i][j] &= (~2); } } for (int j = m - 1; j >= 0; j--) { int nn = 0; for (int i = n - 1; i >= 0; i--) { if (bf[i][j] & 2) nn++; if (nn > maxnn) bf[i][j] &= (~2); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (bf[i][j] & 1) { a.push_back(i); b.push_back(j); } if (bf[i][j] & 2) { c.push_back(i); d.push_back(j); } } } if (n == 1000 && m == 1000 && a.size() > 16) cout << a.size() << << c.size() << endl; } void valid(vector<int> &a, vector<int> &b, vector<int> &c, vector<int> &d, vector<int> &aa, vector<int> &bb, vector<int> &cc, vector<int> &dd) { int asz = a.size(), csz = c.size(); for (int i = 0; i < asz; i++) { for (int j = 0; j < csz; j++) { if (c[j] - a[i] >= 2 && d[j] - b[i] >= 2) { aa.push_back(a[i]); bb.push_back(b[i]); cc.push_back(c[j]); dd.push_back(d[j]); } } } } bool ok(int a, int b, int c, int d, int aa, int bb, int cc, int dd) { if ((c - a + d - b + cc - aa + dd - bb) * 2 < cnt) return false; for (int i = a; i <= c; i++) if (buf[i][b] != # || buf[i][d] != # ) return false; for (int i = aa; i <= cc; i++) if (buf[i][bb] != # || buf[i][dd] != # ) return false; for (int i = b; i <= d; i++) if (buf[a][i] != # || buf[c][i] != # ) return false; for (int i = bb; i <= dd; i++) if (buf[aa][i] != # || buf[cc][i] != # ) return false; for (int mi = 0; mi < msz; mi++) { int i = mx[mi], j = my[mi]; bf[i][j] = buf[i][j]; } for (int i = a; i <= c; i++) bf[i][b] = . , bf[i][d] = . ; for (int i = aa; i <= cc; i++) bf[i][bb] = . , bf[i][dd] = . ; for (int i = b; i <= d; i++) bf[a][i] = . , bf[c][i] = . ; for (int i = bb; i <= dd; i++) bf[aa][i] = . , bf[cc][i] = . ; for (int mi = 0; mi < msz; mi++) { int i = mx[mi], j = my[mi]; if (bf[i][j] == # ) return false; } printf( YES n ); printf( %d %d %d %d n , a + 1, b + 1, c + 1, d + 1); printf( %d %d %d %d n , aa + 1, bb + 1, cc + 1, dd + 1); return true; } bool valid2(vector<int> &a, vector<int> &b, vector<int> &c, vector<int> &d, vector<int> &aa, vector<int> &bb, vector<int> &cc, vector<int> &dd) { aa.clear(), bb.clear(), cc.clear(), dd.clear(); int sz = a.size(); bool res = false; for (int i = 0; i < sz; i++) { for (int j = 0; j < sz; j++) { if (ok(a[i], b[i], c[i], d[i], a[j], b[j], c[j], d[j])) { res = true; return res; } } } return res; } void solve() { cin >> n >> m; for (int i = 0; i < n; i++) scanf( %s , buf[i]); vector<int> a, b, c, d; vector<int> aa, bb, cc, dd; findp(a, b, c, d); bool res = true; if (cnt > (n + m) * 4) res = false; if (res) { valid(a, b, c, d, aa, bb, cc, dd); res = valid2(aa, bb, cc, dd, a, b, c, d); } if (!res) cout << NO << endl; } int main() { solve(); return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_SYMBOL_V
/**
* udp_dlatch$P_pp$PG: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; priority_queue<long long int> dif; vector<long long int> vec; long long int a[1000000], b[1000000]; int main() { long long int x, d, contador = 0, i; long long int pot, exp; cin >> x >> d; while (x > 0) { x++; pot = 1; exp = 0; while (pot <= x) { pot = pot * 2; exp++; } for (i = 0; i < exp - 1; i++) { vec.push_back(d * contador + 1); } contador++; x = x - pot / 2; } cout << vec.size() << n ; for (i = 0; i < vec.size(); i++) cout << vec[i] << ; }
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#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long INF = 1000LL * 1000 * 1000 * 1000 * 1000 * 1000; const int inf = 1000 * 1000 * 1000; const long double PI = acos(-1.0); const long long mod1 = inf + 7; const long long mod2 = inf + 9; const int MAXN = 1000005; const long double EPS = 1e-11; int hp = 179; int invert(bool a) { return ((a & 1) + 1) & 1; } vector<vector<int>> bfst(vector<bool> &a) { vector<bool> x; for (int i = a.size() - 6; i < a.size(); ++i) { x.push_back(a[i]); } if (x == vector<bool>{0, 0, 00, 00, 0, 0}) { return {{}}; } if (x == vector<bool>{1, 0, 0, 0, 0, 0}) { return {{2, 4, 6}}; } if (x == vector<bool>{0, 0, 0, 0, 0, 1}) { return {{5, 8, 11}, {2, 5, 8}}; } if (x == vector<bool>{0, 0, 0, 0, 1, 0}) { return {{4, 7, 10}, {3, 5, 7}}; } if (x == vector<bool>{0, 0, 0, 0, 1, 1}) { return {{4, 7, 10}, {3, 7, 11}}; } if (x == vector<bool>{0, 0, 0, 1, 0, 0}) { return {{5, 7, 9}, {3, 5, 7}}; } if (x == vector<bool>{0, 0, 0, 1, 0, 1}) { return {{7, 9, 11}, {3, 5, 7}}; } if (x == vector<bool>{0, 0, 0, 1, 1, 0}) { return {{10, 8, 9}, {2, 5, 8}}; } if (x == vector<bool>{0, 0, 0, 1, 1, 1}) { return {{11, 9, 10}}; } if (x == vector<bool>{1, 1, 0, 1, 1, 1}) { return {{11, 9, 10}, {5, 7, 6}}; } if (x == vector<bool>{1, 1, 1, 1, 1, 1}) { return {{6, 7, 8}, {11, 9, 10}}; } if (x == vector<bool>{0, 0, 1, 0, 0, 0}) { return {{8, 5, 2}}; } if (x == vector<bool>{0, 0, 1, 0, 0, 1}) { return {{5, 8, 11}}; } if (x == vector<bool>{0, 0, 1, 0, 1, 0}) { return {{6, 8, 10}, {4, 5, 6}}; } if (x == vector<bool>{0, 0, 1, 0, 1, 1}) { return {{5, 8, 11}, {10, 5, 0}}; } if (x == vector<bool>{0, 0, 1, 1, 0, 0}) { return {{7, 8, 9}, {3, 5, 7}}; } if (x == vector<bool>{0, 0, 1, 1, 0, 1}) { return {{5, 8, 11}, {1, 5, 9}}; } if (x == vector<bool>{0, 0, 1, 1, 1, 0}) { return {{10, 9, 8}}; } if (x == vector<bool>{0, 0, 1, 1, 1, 1}) { return {{9, 10, 11}, {8, 5, 2}}; } if (x == vector<bool>{0, 1, 0, 0, 0, 0}) { return {{3, 5, 7}}; } if (x == vector<bool>{0, 1, 0, 0, 0, 1}) { return {{3, 7, 11}}; } if (x == vector<bool>{0, 1, 0, 0, 1, 0}) { return {{4, 7, 10}}; } if (x == vector<bool>{0, 1, 0, 0, 1, 1}) { return {{9, 10, 11}, {5, 7, 9}}; } if (x == vector<bool>{0, 1, 0, 1, 0, 0}) { return {{5, 7, 9}}; } if (x == vector<bool>{0, 1, 0, 1, 0, 1}) { return {{7, 9, 11}}; } if (x == vector<bool>{0, 1, 0, 1, 1, 0}) { return {{4, 7, 10}, {1, 5, 9}}; } if (x == vector<bool>{0, 1, 0, 1, 1, 1}) { return {{9, 10, 11}, {3, 5, 7}}; } if (x == vector<bool>{0, 1, 1, 0, 0, 0}) { return {{6, 7, 8}, {4, 5, 6}}; } if (x == vector<bool>{0, 1, 1, 0, 0, 1}) { return {{5, 8, 11}, {3, 5, 7}}; } if (x == vector<bool>{0, 1, 1, 0, 1, 0}) { return {{6, 8, 10}, {5, 6, 7}}; } if (x == vector<bool>{0, 1, 1, 0, 1, 1}) { return {{9, 10, 11}, {7, 8, 9}}; } if (x == vector<bool>{0, 1, 1, 1, 0, 0}) { return {{7, 8, 9}}; } if (x == vector<bool>{0, 1, 1, 1, 0, 1}) { return {{7, 9, 11}, {2, 5, 8}}; } if (x == vector<bool>{0, 1, 1, 1, 1, 0}) { return {{8, 9, 10}, {3, 5, 7}}; } if (x == vector<bool>{0, 1, 1, 1, 1, 1}) { return {{3, 7, 11}, {8, 9, 10}}; } if (x == vector<bool>{1, 0, 0, 0, 0, 1}) { return {{1, 6, 11}}; } if (x == vector<bool>{1, 0, 0, 0, 1, 0}) { return {{2, 6, 10}}; } if (x == vector<bool>{1, 0, 0, 0, 1, 1}) { return {{9, 10, 11}, {3, 6, 9}}; } if (x == vector<bool>{1, 0, 0, 1, 0, 0}) { return {{3, 6, 9}}; } if (x == vector<bool>{1, 0, 0, 1, 0, 1}) { return {{7, 9, 11}, {5, 6, 7}}; } if (x == vector<bool>{1, 0, 0, 1, 1, 0}) { return {{8, 9, 10}, {4, 6, 8}}; } if (x == vector<bool>{1, 0, 0, 1, 1, 1}) { return {{9, 10, 11}, {4, 5, 6}}; } if (x == vector<bool>{1, 0, 1, 0, 0, 0}) { return {{4, 6, 8}}; } if (x == vector<bool>{1, 0, 1, 0, 0, 1}) { return {{5, 8, 11}, {4, 5, 6}}; } if (x == vector<bool>{1, 0, 1, 0, 1, 0}) { return {{6, 8, 10}}; } if (x == vector<bool>{1, 0, 1, 0, 1, 1}) { return {{5, 8, 11}, {2, 6, 10}}; } if (x == vector<bool>{1, 0, 1, 1, 0, 0}) { return {{4, 6, 8}, {1, 5, 9}}; } if (x == vector<bool>{1, 0, 1, 1, 0, 1}) { return {{7, 9, 11}, {6, 7, 8}}; } if (x == vector<bool>{1, 0, 1, 1, 1, 0}) { return {{8, 9, 10}, {4, 5, 6}}; } if (x == vector<bool>{1, 0, 1, 1, 1, 1}) { return {{9, 10, 11}, {4, 6, 8}}; } if (x == vector<bool>{1, 1, 0, 0, 0, 0}) { return {{5, 6, 7}}; } if (x == vector<bool>{1, 1, 0, 0, 0, 1}) { return {{3, 7, 11}, {4, 5, 6}}; } if (x == vector<bool>{1, 1, 0, 0, 1, 0}) { return {{4, 7, 10}, {4, 5, 6}}; } if (x == vector<bool>{1, 1, 0, 0, 1, 1}) { return {{3, 7, 11}, {2, 6, 10}}; } if (x == vector<bool>{1, 1, 0, 1, 0, 0}) { return {{5, 7, 9}, {4, 5, 6}}; } if (x == vector<bool>{1, 1, 0, 1, 0, 1}) { return {{7, 9, 11}, {4, 5, 6}}; } if (x == vector<bool>{1, 1, 0, 1, 1, 0}) { return {{3, 6, 9}, {4, 7, 10}}; } if (x == vector<bool>{1, 1, 0, 1, 1, 1}) { return {{9, 10, 11}, {5, 6, 7}}; } if (x == vector<bool>{1, 1, 1, 0, 0, 0}) { return {{6, 7, 8}}; } if (x == vector<bool>{1, 1, 1, 0, 0, 1}) { return {{5, 8, 11}, {5, 6, 7}}; } if (x == vector<bool>{1, 1, 1, 0, 1, 0}) { return {{6, 8, 10}, {3, 5, 7}}; } if (x == vector<bool>{1, 1, 1, 0, 1, 1}) { return {{6, 8, 10}, {3, 7, 11}}; } if (x == vector<bool>{1, 1, 1, 1, 0, 0}) { return {{7, 8, 9}, {4, 5, 6}}; } if (x == vector<bool>{1, 1, 1, 1, 0, 1}) { return {{7, 9, 11}, {4, 6, 8}}; } if (x == vector<bool>{1, 1, 1, 1, 1, 0}) { return {{5, 6, 7}, {8, 9, 10}}; } assert(false); } signed main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); ; int n; cin >> n; vector<bool> a(n); for (int i = 0; i < n; ++i) { int x; cin >> x; if (x) a[i] = 1; } if (n < 13) { map<vector<bool>, int> d; map<vector<bool>, vector<int>> p; map<vector<bool>, int> used; d[a] = 0; used[a] = 1; queue<vector<bool>> q; q.push(a); while (q.size()) { vector<bool> v = q.front(); q.pop(); for (int lg = 1; 2 * lg < n; ++lg) { for (int i = 0; i + 2 * lg < n; ++i) { vector<bool> t = v; t[i] = invert(t[i]); t[i + lg] = invert(t[i + lg]); t[i + 2 * lg] = invert(t[i + 2 * lg]); if (!used[t]) { used[t] = 1; d[t] = d[v] + 1; p[t] = {i, i + lg, i + 2 * lg}; q.push(t); } } } } vector<bool> x = a; for (int i = 0; i < n; ++i) { x[i] = 0; } if (used[x] == 0) { cout << NO ; return 0; } cout << YES << endl; vector<vector<int>> ans; while (x != a) { ans.push_back(p[x]); vector<int> pp = p[x]; for (int i = 0; i < 3; ++i) { x[pp[i]] = invert(x[pp[i]]); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { for (int j = 0; j < 3; ++j) { cout << ans[i][j] + 1 << ; } cout << endl; } return 0; } int k = n - 1; vector<vector<int>> ans; while (k >= 13) { vector<bool> help; for (int i = k - 11; i < k + 1; ++i) { help.push_back(a[i]); } auto xx = bfst(help); vector<bool> tmp = vector<bool>(a.begin() + k - 11, a.begin() + k + 1); if (xx.size() == 1 && xx[0].size() == 0) { k -= 6; continue; } for (vector<int> i : xx) { ans.push_back({i[0] + k - 11, i[1] + k - 11, i[2] + k - 11}); tmp[i[0]] = invert(tmp[i[0]]); tmp[i[1]] = invert(tmp[i[1]]); tmp[i[2]] = invert(tmp[i[2]]); } for (int i = k - 11; i < k + 1; ++i) { a[i] = tmp[i + 11 - k]; } k -= 6; } map<vector<bool>, int> d; map<vector<bool>, vector<int>> p; map<vector<bool>, bool> used; d[vector<bool>(a.begin(), a.begin() + k + 1)] = 0; used[vector<bool>(a.begin(), a.begin() + k + 1)] = 1; queue<vector<bool>> q; q.push(vector<bool>(a.begin(), a.begin() + k + 1)); while (q.size()) { vector<bool> v = q.front(); q.pop(); for (int lg = 1; 2 * lg <= k; ++lg) { for (int i = 0; i + 2 * lg <= k; ++i) { vector<bool> t = v; t[i] = invert(t[i]); t[i + lg] = invert(t[i + lg]); t[i + 2 * lg] = invert(t[i + 2 * lg]); if (!used[t]) { used[t] = 1; d[t] = d[v] + 1; p[t] = {i, i + lg, i + 2 * lg}; q.push(t); } } } } vector<bool> x = vector<bool>(a.begin(), a.begin() + k + 1); for (int i = 0; i <= k; ++i) { x[i] = 0; } cout << YES << endl; while (x != vector<bool>(a.begin(), a.begin() + k + 1)) { ans.push_back(p[x]); vector<int> pp = p[x]; for (int i = 0; i < 3; ++i) { x[pp[i]] = invert(x[pp[i]]); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { for (int j = 0; j < 3; ++j) { cout << ans[i][j] + 1 << ; } cout << endl; } }
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