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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $
//
// $Date: 2009-01-19 20:29:26 $
// $Revision: 1.12 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`include "i2c_timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
`include "i2c_master_byte_ctrl.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
// wire wb_wacc = wb_we_i & wb_ack_o;
// SWM: use Avalon timing instead...
wire wb_wacc = wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsys parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsys parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_0 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//-------------------------------------------------------------------
//-- genromleds_tb.v
//-- Banco de pruebas para el secuenciador de luces, implementado con
//-- una memoria rom generica
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
module genromleds_tb();
//-- Para la simulacion se usa un retraso de 2 ciclos de reloj
parameter DELAY = 2;
parameter ROMFILE = "rom1.list";
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del componente
wire [4:0] leds;
//-- Instanciar el componente
genromleds #(.DELAY(DELAY), .ROMFILE(ROMFILE))
dut(
.clk(clk),
.leds(leds)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("genromleds_tb.vcd");
$dumpvars(0, genromleds_tb);
# 140 $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, c0, d0, hsl; int a[15], b[15], c[15], d[15]; int dp[1005][15]; bool dpf[1005][15]; int proc(int x, int num) { if (num == 0) { return 0; } else if (dpf[x][num]) { return dp[x][num]; } else { int &ret = dp[x][num]; ret = 0; dpf[x][num] = true; for (int i = 0; (i <= (a[num] / b[num])) && (x >= c[num] * i); i++) { ret = max(ret, proc(x - c[num] * i, num - 1) + d[num] * i); } return ret; } } int main() { scanf( %d %d %d %d , &n, &m, &c0, &d0); for (int i = 1; i <= m; i++) { scanf( %d %d %d %d , &a[i], &b[i], &c[i], &d[i]); } hsl = 0; for (int i = 0; i <= n; i++) { hsl = max(hsl, proc(i, m) + ((n - i) / c0) * d0); } printf( %d n , hsl); }
|
#include <bits/stdc++.h> using namespace std; int e[1010][1010]; int main(void) { int n, a, b; scanf( %d%d%d , &n, &a, &b); if (a > 1 && b > 1) { printf( NO n ); return 0; } int x = n - max(a, b) + 1; if (x <= 0 || ((n == 2 || n == 3) && x == n)) { printf( NO n ); return 0; } printf( YES n ); for (int i = 0; i < x - 1; i++) e[i][i + 1] = e[i + 1][i] = 1; if (b != 1) for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i != j) e[i][j] = 1 - e[i][j]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %d , e[i][j]); puts( ); } return 0; }
|
#include <bits/stdc++.h> int main() { char c, str[100]; int i; scanf( %c , &c); getchar(); gets(str); if (c == L ) { for (i = 0; i < strlen(str); i++) { if (str[i] == q ) { str[i] = w ; } else if (str[i] == w ) { str[i] = e ; } else if (str[i] == r ) { str[i] = t ; } else if (str[i] == t ) { str[i] = y ; } else if (str[i] == y ) { str[i] = u ; } else if (str[i] == u ) { str[i] = i ; } else if (str[i] == i ) { str[i] = o ; } else if (str[i] == o ) { str[i] = p ; } else if (str[i] == a ) { str[i] = s ; } else if (str[i] == s ) { str[i] = d ; } else if (str[i] == d ) { str[i] = f ; } else if (str[i] == f ) { str[i] = g ; } else if (str[i] == g ) { str[i] = h ; } else if (str[i] == h ) { str[i] = j ; } else if (str[i] == j ) { str[i] = k ; } else if (str[i] == k ) { str[i] = l ; } else if (str[i] == l ) { str[i] = ; ; } else if (str[i] == z ) { str[i] = x ; } else if (str[i] == x ) { str[i] = c ; } else if (str[i] == c ) { str[i] = v ; } else if (str[i] == v ) { str[i] = b ; } else if (str[i] == b ) { str[i] = n ; } else if (str[i] == n ) { str[i] = m ; } else if (str[i] == m ) { str[i] = , ; } else if (str[i] == , ) { str[i] = . ; } else if (str[i] == . ) { str[i] = / ; } else if (str[i] == e ) { str[i] = r ; } } } else if (c == R ) { for (i = 0; i < strlen(str); i++) { if (str[i] == w ) { str[i] = q ; } else if (str[i] == e ) { str[i] = w ; } else if (str[i] == r ) { str[i] = e ; } else if (str[i] == t ) { str[i] = r ; } else if (str[i] == y ) { str[i] = t ; } else if (str[i] == u ) { str[i] = y ; } else if (str[i] == i ) { str[i] = u ; } else if (str[i] == o ) { str[i] = i ; } else if (str[i] == p ) { str[i] = o ; } else if (str[i] == s ) { str[i] = a ; } else if (str[i] == d ) { str[i] = s ; } else if (str[i] == f ) { str[i] = d ; } else if (str[i] == g ) { str[i] = f ; } else if (str[i] == h ) { str[i] = g ; } else if (str[i] == j ) { str[i] = h ; } else if (str[i] == k ) { str[i] = j ; } else if (str[i] == l ) { str[i] = k ; } else if (str[i] == ; ) { str[i] = l ; } else if (str[i] == x ) { str[i] = z ; } else if (str[i] == c ) { str[i] = x ; } else if (str[i] == v ) { str[i] = c ; } else if (str[i] == b ) { str[i] = v ; } else if (str[i] == n ) { str[i] = b ; } else if (str[i] == m ) { str[i] = n ; } else if (str[i] == , ) { str[i] = m ; } else if (str[i] == . ) { str[i] = , ; } else if (str[i] == / ) { str[i] = . ; } } } printf( %s , str); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long n; cin >> n; long long d = 0; vector<long long> v; vector<long long> a; long long val = 0; map<long long, long long> m; long long start = 0, end = -1, count = 0; for (long long i = 0; i < (long long)n; i++) { cin >> val; if (i == 0) { if (val < 0) { count++; break; } else { v.push_back(val); m[val]++; } } else { if (val > 0) { if (m[val] >= m[-val] && m[val] == 0) { v.push_back(val); m[val]++; } else { count++; break; } } else { if (v.size() == 0 && start != end) { d++; end = i; a.push_back(end - start + 1); start = i + 1; m.clear(); } if (m[val] >= m[-val]) { count++; break; } else { m[val]++; for (long long j = 0; j < v.size(); j++) { if (v[j] == (-val)) { v.erase(v.begin() + j); break; } } } if (v.size() == 0 && start != end) { d++; end = i; a.push_back(end - start + 1); start = i + 1; m.clear(); } } } } if (v.size() != 0 || count > 0) { cout << -1 << n ; } else { cout << d << n ; for (long long i = 0; i < a.size(); i++) { cout << a[i] << ; } cout << n ; } return 0; }
|
module FSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5005; const int maxm = maxn * 2; const int maxe = 200005; const int mod = 1e9 + 7; int n, a, b; string str; int cc[26][maxn][26]; int exist[26]; int main() { cin >> str; n = str.length(); for (int i = 0; i < n; i++) { int idx = str[i] - a ; exist[idx]++; for (int j = 1; j < n; j++) { int pos = (i + j) % n; int idx2 = str[pos] - a ; cc[idx][j][idx2]++; } } double ans = 0; for (int i = 0; i < 26; i++) { double cccc = 0; for (int j = 1; j < n; j++) { double tp = 0; for (int ii = 0; ii <= n; ii++) { if (str[ii] - a != i) continue; int pos = (ii + j) % n; int idx2 = str[pos] - a ; if (cc[i][j][idx2] == 1) tp++; } cccc = max(cccc, tp); } ans += cccc; } printf( %.15lf n , ans / n); return 0; }
|
//Instruction decoder
`include "verilog/mips_instr_defines.v"
module decode
(
input wire[31:0] instr_dec_i,
input wire sign_ext_i,
output wire[4:0] rt_dec_o,
output wire[4:0] rs_dec_o,
output wire[4:0] rd_dec_o,
output wire[5:0] op_dec_o,
output wire[5:0] funct_dec_o,
output wire[4:0] shamt_dec_o,
output wire[25:0] target_dec_o,
output wire[31:0] sign_imm_dec_o,
output wire is_r_type_dec_o,
output wire is_i_type_dec_o,
output wire is_j_type_dec_o,
output wire use_link_reg_dec_o
);
//Populate the output fields using the input instruction
wire[4:0] rt_dec;
wire[4:0] rs_dec;
wire[4:0] rd_dec;
wire[5:0] op_dec;
wire[5:0] funct_dec;
wire[4:0] shamt_dec;
wire[25:0] target_dec;
wire[31:0] sign_imm_dec;
wire is_r_type_dec;
wire is_i_type_dec;
wire is_j_type_dec;
wire use_link_reg_dec;
assign rt_dec_o = rt_dec;
assign rs_dec_o = rs_dec;
assign rd_dec_o = rd_dec;
assign op_dec_o = op_dec;
assign funct_dec_o = funct_dec;
assign shamt_dec_o = shamt_dec;
assign target_dec_o = target_dec;
assign sign_imm_dec_o = sign_imm_dec;
assign is_r_type_dec_o = is_r_type_dec;
assign is_i_type_dec_o = is_i_type_dec;
assign is_j_type_dec_o = is_j_type_dec;
assign use_link_reg_dec_o = use_link_reg_dec;
assign sign_imm_dec = (sign_ext_i) ? {{16{instr_dec_i[15]}},instr_dec_i[15:0]} :
{16'b0, instr_dec_i[15:0]};
assign rd_dec = instr_dec_i[15:11];
assign rt_dec = instr_dec_i[20:16];
assign rs_dec = instr_dec_i[25:21];
assign op_dec = instr_dec_i[31:26];
assign target_dec = instr_dec_i[25:0];
assign funct_dec = instr_dec_i[5:0];
assign shamt_dec = instr_dec_i[10:6];
assign is_r_type_dec = (op_dec == 6'h0);
assign is_i_type_dec = ((op_dec != 6'h0) && ((op_dec != `J) && (op_dec != `JAL)));
assign is_j_type_dec = ((op_dec == `J) || (op_dec == `JAL));
assign use_link_reg_dec = (((op_dec == `BVAR) && ((rt_dec == `BLTZAL) || (rt_dec == `BGEZAL))) ||
((is_r_type_dec) && ((funct_dec == `JALR))) ||
((is_j_type_dec) && ((op_dec == `JAL))));
endmodule
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int ans = 1e9, n, a[2000 + 5], b[2000 + 5], cnt, num[720 + 5], A[6], c[720 + 5][5]; int id[10][10][10][10], f[15000005], q[15000005], top; void dfs(int x, int v) { ++cnt; num[cnt] = x - 1; id[A[1]][A[2]][A[3]][A[4]] = cnt; for (int j = 1; j < x; ++j) c[cnt][j] = A[j]; if (x > 4) return; for (int i = v; i <= 9; ++i) A[x] = i, dfs(x + 1, i); A[x] = 0; } inline int ID(int x, int y, int z) { return x * 720 * 10 + y * 10 + z; } void Try(int x, int y, int z, int v) { int d = ID(x, y, z); if (v < f[d]) f[q[++top] = d] = v; } int main() { dfs(1, 1); memset(f, 40, sizeof(f)); n = read(); for (int i = 1; i <= n; ++i) a[i] = read(), b[i] = read(); f[q[top = 1] = ID(0, id[0][0][0][0], 1)] = 0; for (int i = 1; i <= top; ++i) { int x = q[i] / 720 / 10, y = (q[i] / 10) % 720, z = q[i] % 10, v = f[q[i]]; if (z < 9) Try(x, y, z + 1, v + 1); if (z > 1) Try(x, y, z - 1, v + 1); int nn = 0; for (int j = 1; j <= num[y]; ++j) if (c[y][j] != z) A[++nn] = c[y][j]; for (int j = nn + 1; j <= 4; ++j) A[j] = 0; Try(x, id[A[1]][A[2]][A[3]][A[4]], z, v + (num[y] - nn)); if (x < n && a[x + 1] == z && num[y] < 4) { int nn = 0, k = 1; for (; k <= num[y]; ++k) if (c[y][k] <= b[x + 1]) A[++nn] = c[y][k]; else break; A[++nn] = b[x + 1]; for (; k <= num[y]; ++k) A[++nn] = c[y][k]; while (nn < 4) A[++nn] = 0; Try(x + 1, id[A[1]][A[2]][A[3]][A[4]], z, v + 1); } } for (int i = 1; i <= 9; ++i) ans = min(ans, f[ID(n, id[0][0][0][0], i)]); cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b, w, x, c; cin >> a >> b >> w >> x >> c; long long delta = c - a; if (delta <= 0) { cout << 0 << endl; } else { double k = (1.0 * delta * x - b) / (w - x); long long t = ceil(delta + k); cout << t << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; int A[n][m], row[n], col[m]; char c; memset(row, 0, sizeof(row)); memset(col, 0, sizeof(col)); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> c; if (c == . ) A[i][j] = 0; else A[i][j] = 1; } } for (int i = 0; i < n; ++i) { if (row[i] == 0) { for (int j = 0; j < m; ++j) { if (A[i][j] == 1 && col[j]) { cout << No << endl; return 0; } } vector<int> X; for (int j = i + 1; j < n; ++j) { int ans = 1; if (row[j]) continue; for (int k = 0; k < m; ++k) { if (A[i][k] != A[j][k]) { ans = 0; break; } } if (ans == 1) X.push_back(j); } for (int j = 0; j < X.size(); ++j) row[X[j]] = 1; for (int j = 0; j < m; ++j) if (A[i][j]) col[j] = 1; } } cout << Yes << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, otv = 0, otv1 = 0; cin >> n; vector<long long> v(n); for (long long j = 0; j < n; j++) { cin >> v[j]; } for (long long j = 1; j < n; j++) { if (v[j] != v[0]) { otv = j; } } for (long long j = 0; j < n - 1; j++) { if (v[j] != v[n - 1]) { otv1 = n - 1 - j; cout << max(otv, otv1); return 0; } } cout << max(otv, otv1); }
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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_gen
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 16384,
parameter OUT_BITS = 16
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SEQ_EXT_START,
input wire SEQ_CLK,
output wire [OUT_BITS-1:0] SEQ_OUT
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH)) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
seq_gen_core
#(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES),
.OUT_BITS(OUT_BITS)
) i_seq_gen_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SEQ_EXT_START(SEQ_EXT_START),
.SEQ_CLK(SEQ_CLK),
.SEQ_OUT(SEQ_OUT)
);
endmodule
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#include <bits/stdc++.h> using namespace std; inline void pisz(int n) { printf( %d n , n); } const int MAX_N = 200010; int n; char a[MAX_N]; char b[MAX_N]; double s1[26][MAX_N]; double s2[26][MAX_N]; void precompute() { s1[b[1] - A ][1] = 1UL; for (int(i) = (2); (i) <= (n); ++i) { for (int(j) = 0; (j) < (26); ++(j)) { s1[j][i] = s1[j][i - 1]; if (j == b[i] - A ) { s1[j][i] = (double)(s1[j][i] + i); } } } s2[b[n] - A ][n - 1] = 1UL; for (int(i) = (n - 2); (i) >= (1); --i) { for (int(j) = 0; (j) < (26); ++(j)) { s2[j][i] = s2[j][i + 1]; if (j == b[i + 1] - A ) { s2[j][i] = (double)(s2[j][i] + (double)(n - (i + 1UL) + 1UL)); } } } } int main() { char c; scanf( %d , &n); scanf( %s , a + 1); scanf( %s , b + 1); precompute(); double num_of_substrings = 0UL; for (int(l) = (1); (l) <= (n); ++l) { num_of_substrings += (double)((double)((double)(n - l) + 1UL) * (double)((double)(n - l) + 1UL)); } double count = 0UL; for (int(i) = (1); (i) <= (n); ++i) { c = a[i]; count = (double)(count + (double)((double)(n - i + 1UL) * s1[c - A ][i])); count = (double)(count + (double)(i * s2[c - A ][i])); } double res = (count * 1.0) / (num_of_substrings); printf( %.9f n , res); return 0; }
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//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 08:51:06
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module RecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef pair<int, int> pii; typedef long double ld; #define F first #define S second const int MOD = 998244353;// XXX const int C = 26;// XXX void add(int &x, int y){ x += y; while (x >= MOD) x -= MOD; while (x < 0) x += MOD; } int fix(int x){ while (x >= MOD) x -= MOD; while (x < 0) x += MOD; return x; } int pw(int a, int b){ int ret = 1; while (b){ if (b & 1) ret = 1ll*ret*a%MOD; b >>= 1; a = 1ll*a*a%MOD; } return ret; } int mul(int a, int b) { return (ll) a * b % MOD; } const int MAXN = 405; const int MAXE = 605; int n, m, d[MAXN][MAXN], ans[MAXN][MAXN]; pii edges[MAXE]; int onPath[MAXN], foundLen[MAXN], numPar[MAXN]; void solve() { cin >> n >> m; memset(d, 63, sizeof(d)); for(int i = 0; i < m; i++) { int a, b; cin >> a >> b; --a; --b; edges[i] = {a, b}; d[a][b] = d[b][a] = 1; } for(int i = 0; i < n; i++) d[i][i] = 0; for(int k = 0; k < n; k++) for(int i = 0; i < n; i++) for(int j = 0; j < n; j++) d[i][j] = min(d[i][j], d[i][k] + d[k][j]); for(int u = 0; u < n; u++) { for(int v = 0; v < n; v++) { bool ok = 1; int cnt = 1; memset(onPath, 0, sizeof(onPath)); memset(numPar, 0, sizeof(numPar)); memset(foundLen, 0, sizeof(foundLen)); for(int w = 0; w < n; w++) { if(d[u][w] + d[v][w] == d[u][v]) { onPath[w] = 1; if(foundLen[d[u][w]]) ok = 0; foundLen[d[u][w]] = 1; } } for(int len = 0; len <= d[u][v]; len++) if(!foundLen[len]) ok = 0; for(int e = 0; e < m; e++) { for(int rot = 0; rot < 2; rot++) { auto &[a, b] = edges[e]; if(!onPath[a]) { if(d[u][a] == d[u][b] + 1 && d[v][a] == d[v][b] + 1) { ++numPar[a]; } } swap(a, b); } } for(int w = 0; w < n; w++) if(!onPath[w]) cnt = mul(cnt, numPar[w]); if(ok) ans[u][v] = cnt; } } for(int u = 0; u < n; u++) { for(int v = 0; v < n; v++) { cout << ans[u][v] << ; } cout << n ; } } int main(){ ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); // cout << fixed << setprecision(6); int te = 1; // cin >> te; for (int w = 1; w <= te; w++){ // cout << Case # << w << : ; solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_2_V
`define SKY130_FD_SC_HD__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_2_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int MAXN = 3005; int r, c, n, k; pair<int, int> v[MAXN]; int prv[MAXN], nxt[MAXN]; vector<int> y[MAXN], x[MAXN]; int pos[MAXN]; int num[MAXN]; int cnt; long long ans; int res; bool cmp_x(int num1, int num2) { return v[num1].first < v[num2].first; } bool cmp_y(int num1, int num2) { return v[num1].second < v[num2].second; } int trivia(int x1, int x2) { int cnt[MAXN]; memset(cnt, 0, sizeof(cnt)); for (int yy = 1; yy <= c; yy++) { for (int i = 0; i < y[yy].size(); i++) { if (x1 <= v[y[yy][i]].first && v[y[yy][i]].first <= x2) { cnt[yy]++; } } } int res = 0; for (int yy1 = 1; yy1 <= c; yy1++) { int cur = 0; for (int y2 = yy1; y2 <= c; y2++) { cur += cnt[y2]; if (cur >= k) { res++; } } } return res; } void solve() { scanf( %d%d%d%d , &r, &c, &n, &k); for (int i = 1; i <= n; i++) { scanf( %d%d , &v[i].first, &v[i].second); y[v[i].second].push_back(i); x[v[i].first].push_back(i); } for (int i = 1; i <= r; i++) { sort(x[i].begin(), x[i].end(), cmp_y); } for (int i = 1; i <= c; i++) { sort(y[i].begin(), y[i].end(), cmp_x); } v[n + 1].second = c + 1; for (int i = 1; i <= r; i++) { cnt = 0; res = 0; for (int j = 1; j <= c; j++) { for (int h = (int)y[j].size() - 1; h >= 0; h--) { int curnum = y[j][h]; if (v[curnum].first < i) { break; } pos[curnum] = ++cnt; num[cnt] = curnum; prv[cnt] = cnt - 1; nxt[cnt - 1] = cnt; } } nxt[cnt] = cnt + 1; num[cnt + 1] = n + 1; nxt[cnt + 1] = 0; for (int j = k; j <= cnt; j++) { res += (v[num[j + 1]].second - v[num[j]].second) * (v[num[j - k + 1]].second); } for (int j = r; j >= i; j--) { ans += res; for (int h = 0; h < x[j].size(); h++) { vector<int> all; all.reserve(k << 1); int back = 0; int p = prv[pos[x[j][h]]]; while (p && all.size() < k - 1) { all.push_back(p); p = prv[p]; } back = all.size(); reverse(all.begin(), all.end()); if (p) { res += (v[num[nxt[pos[x[j][h]]]]].second - v[num[pos[x[j][h]]]].second) * (v[num[p]].second); } p = pos[x[j][h]]; while (p && all.size() <= k + back) { all.push_back(p); p = nxt[p]; } for (int l = max(k - 1, back); l + 1 < all.size(); l++) { res -= (v[num[all[l + 1]]].second - v[num[all[l]]].second) * (v[num[all[l - k + 1]]].second); } for (int l = max(k, back + 1); l + 1 < all.size(); l++) { res += (v[num[all[l + 1]]].second - v[num[all[l]]].second) * (v[num[all[l - k]]].second); } prv[nxt[pos[x[j][h]]]] = prv[pos[x[j][h]]]; nxt[prv[pos[x[j][h]]]] = nxt[pos[x[j][h]]]; } } } printf( %I64d n , ans); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); srand(1313); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 4e5 + 10; int sum[mx]; int x[mx]; int n, m; void add(int x) { while (x <= 2 * n + 1) { sum[x]++; x += x & (-x); } } int query(int x) { int ans = 0; while (x) { ans += sum[x]; x -= x & (-x); } return ans; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &x[i]); int cnt = n + 1; long long int a = 0, b = 0; add(cnt); for (int i = 1; i <= n; i++) { if (x[i] < m) cnt--; else cnt++; a += query(cnt - 1); add(cnt); } cnt = n + 1; memset(sum, 0, sizeof(sum)); add(cnt); for (int i = 1; i <= n; i++) { if (x[i] <= m) cnt--; else cnt++; b += query(cnt - 1); add(cnt); } printf( %I64d n , a - b); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long INFL = 1e18 + 123; const double PI = atan2(0, -1); mt19937 tw(960172); long long rnd(long long x, long long y) { static uniform_int_distribution<long long> d; return d(tw) % (y - x + 1) + x; } int cross(int x1, int y1, int x2, int y2) { return x1 * y2 - y1 * x2; } bool inside(int x, int y, vector<pair<int, int> > poly) { int s1 = 0, s2 = 0; for (int i = 0; i < ((int)(poly).size()); ++i) { int next = (i + 1) % ((int)(poly).size()); int tmp = cross(poly[i].first - x, poly[i].second - y, poly[next].first - x, poly[next].second - y); s1 += tmp; s2 += abs(tmp); } return abs(s1) == s2; } void solve() { vector<pair<int, int> > poly[2]; for (int i = 0; i < 2; ++i) { for (int j = 0; j < 4; ++j) { int x, y; cin >> x >> y; poly[i].push_back({x, y}); } } for (int x = -150; x <= 150; ++x) { for (int y = -150; y <= 150; ++y) { if (inside(x, y, poly[0]) && inside(x, y, poly[1])) { cout << YES n ; return; } } } cout << NO n ; } int main() { cerr << fixed << setprecision(15); cout << fixed << setprecision(15); ios::sync_with_stdio(false); int tests = 1; for (int it = 1; it <= tests; ++it) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool setmax(T &_a, T _b) { if (_a < _b) { _a = _b; return true; } return false; } inline void Boost() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int main() { int n, k; cin >> n >> k; map<string, pair<vector<int>, vector<int> > > m1; map<string, vector<int> > m2; for (int i = 0; i < n; i++) { string s, rs; int val; cin >> s >> val; rs = s; reverse(rs.begin(), rs.end()); if (s == rs) { auto it = m2.find(s); if (it == m2.end()) m2.insert({s, {val}}); else it->second.push_back(val); } else { auto it = m1.find(s); if (it != m1.end()) { it->second.first.push_back(val); } else { it = m1.find(rs); if (it != m1.end()) it->second.second.push_back(val); else m1.insert({s, {{val}, {}}}); } } } int ans = 0, bonus = 0; for (auto &it : m1) { auto &v1 = it.second.first; auto &v2 = it.second.second; sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); while (!v1.empty() && !v2.empty()) { int cur = v1.back() + v2.back(); if (cur < 0) break; ans += cur; v1.pop_back(); v2.pop_back(); } } for (auto &it : m2) { auto &v = it.second; sort(v.begin(), v.end()); while (v.size() >= 2 && v[v.size() - 2] > 0) { ans += v[v.size() - 2] + v[v.size() - 1]; v.pop_back(); v.pop_back(); } if (v.size() >= 2 && v[v.size() - 2] + v[v.size() - 1] > 0) { assert(v[v.size() - 2] <= 0); ans += v[v.size() - 2] + v[v.size() - 1]; setmax(bonus, -v[v.size() - 2]); } else if (v.size() >= 1 && v.back() > 0) setmax(bonus, v.back()); } cout << ans + bonus; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, i, s, a1, b1, m; cin >> t; while (t--) { cin >> n >> m; if (n < m) { cout << 0 n ; continue; } if (n == m) cout << n % 10 << n ; else { long long int a[10] = {}, b[11] = {}; for (i = 1; i <= 10; i++) { a[i - 1] = (m * i) % 10; b[i] += a[i - 1] + b[i - 1]; } a1 = n / m; b1 = a1 % 10; a1 = a1 / 10; s = a1 * b[10] + b[b1]; cout << s << n ; } } return 0; }
|
module main;
// Declare word1 as a VARIABLE
struct packed {
logic [7:0] high;
logic [7:0] low;
} word1;
// Declare word2, word3 as a NET
wire struct packed {
logic [7:0] high;
logic [7:0] low;
} word2, word3;
assign word2.high = word1.high;
assign word2.low = word1.low;
assign {word3.high, word3.low} = {word1.low, word1.high};
initial begin
word1 = 16'haa_55;
if (word1.high !== 8'haa || word1.low !== 8'h55) begin
$display("FAILED: word1 = %h, word1.high = %h, word1.low = %h",
word1, word1.high, word1.low);
$finish;
end
#1 /* Make sure word2 assign propagates */;
if (word2.high !== 8'haa || word2.low !== 8'h55) begin
$display("FAILED: word2 = %h, word2.high = %h, word2.low = %h",
word1, word2.high, word2.low);
$finish;
end
/* and also for word3 */
if (word3.low !== 8'haa || word3.high !== 8'h55) begin
$display("FAILED: word3 = %h, word3.high = %h, word3.low = %h (should be reverse)",
word1, word3.high, word3.low);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; struct station { int pos, price; } a[200003]; int T[800008], d, n, m; long long cnt; bool comp(station A, station B) { return (A.pos < B.pos); } void Build_MinIT(int, int, int); int Find_Min(int, int, int, int, int); int main() { scanf( %d %d %d , &d, &n, &m); for (int i = 1; i <= m; i++) scanf( %d %d , &a[i].pos, &a[i].price); sort(a + 1, a + 1 + m, comp); a[++m].pos = d; for (int i = 1; i <= m; i++) { if (a[i].pos - a[i - 1].pos > n) { cout << -1; return 0; } } if (n >= d) { cout << 0; return 0; } a[200002].price = 1E+9; Build_MinIT(1, m, 1); int i = 0, j = 1, t = n; while (j <= m) { while (a[i].price < a[j].price && a[j].pos - a[i].pos <= n && j <= m) j++; if (a[j].pos - a[i].pos <= n) { cnt += (long long)(a[j].pos - (a[i].pos + t)) * a[i].price; t = 0; i = j++; } else { int k = Find_Min(i + 1, j - 1, 1, m, 1); cnt += (long long)(n - t) * a[i].price; t = a[i].pos + n - a[k].pos; i = k; } } cout << cnt; return 0; } void Build_MinIT(int L, int R, int v) { if (L == R) { T[v] = L; return; } int m = (L + R) / 2; Build_MinIT(L, m, v * 2); Build_MinIT(m + 1, R, v * 2 + 1); T[v] = (a[T[v * 2]].price < a[T[v * 2 + 1]].price ? T[v * 2] : T[v * 2 + 1]); } int Find_Min(int l, int r, int L, int R, int v) { if (l > r) return 200002; if (l == L && r == R) return T[v]; int m = (L + R) / 2; int x = Find_Min(l, min(r, m), L, m, v * 2), y = Find_Min(max(l, m + 1), r, m + 1, R, v * 2 + 1); return (a[x].price < a[y].price ? x : y); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_2_V
`define SKY130_FD_SC_HDLL__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_2_V
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module fifomem
#(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4, // Number of mem address bits
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire wclk,
input wire wclken,
input wire [ADDRSIZE-1:0] waddr,
input wire [DATASIZE-1:0] wdata,
input wire wfull,
input wire rclk,
input wire rclken,
input wire [ADDRSIZE-1:0] raddr,
output wire [DATASIZE-1:0] rdata
);
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
reg [DATASIZE-1:0] rdata_r;
always @(posedge wclk) begin
if (wclken && !wfull)
mem[waddr] <= wdata;
end
generate
if (FALLTHROUGH == "TRUE")
begin : fallthrough
assign rdata = mem[raddr];
end
else
begin : registered_read
always @(posedge rclk) begin
if (rclken)
rdata_r <= mem[raddr];
end
assign rdata = rdata_r;
end
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; int n, a[N], b[N], p[N]; int main() { if (fopen( 180F.in , r )) freopen( 180F.in , r , stdin); scanf( %d n , &n); for (int i = 1; i <= n; i++) { scanf( %d , a + i); } for (int i = 1; i <= n; i++) { scanf( %d , b + i); } for (int i = 1; i <= n; i++) { p[a[i]] = b[i]; } for (int i = 1; i <= n; i++) { printf( %d , p[i]); } }
|
/*
* Synchronous read 1r1w content addressable memory module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w_sync, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input w_set_not_clear_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Metadata useful for an external replacement policy
// Whether there's an empty entry in the tag array
, output [safe_els_lp-1:0] w_empty_o
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// Latch the read request for a synchronous read
logic [tag_width_p-1:0] r_tag_r;
logic r_v_r;
bsg_dff
#(.width_p(1+tag_width_p))
r_tag_reg
(.clk_i(clk_i)
,.data_i({r_v_i, r_tag_i})
,.data_o({r_v_r, r_tag_r})
);
// Read from asynchronous unmanaged CAM
bsg_cam_1r1w_unmanaged
#(.els_p(safe_els_lp)
,.tag_width_p(tag_width_p)
,.data_width_p(data_width_p)
)
cam
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_set_not_clear_i(w_set_not_clear_i)
,.w_tag_i(w_tag_i)
,.w_data_i(w_data_i)
,.w_empty_o(w_empty_o)
,.r_v_i(r_v_r)
,.r_tag_i(r_tag_r)
,.r_data_o(r_data_o)
,.r_v_o(r_v_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_sync_unmanaged)
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_NIOS_II_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
SOC_NIOS_II_jtag_debug_module_tck the_SOC_NIOS_II_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
SOC_NIOS_II_jtag_debug_module_sysclk the_SOC_NIOS_II_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic SOC_NIOS_II_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam SOC_NIOS_II_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// SOC_NIOS_II_jtag_debug_module_phy.sld_instance_index = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_ir_width = 2,
// SOC_NIOS_II_jtag_debug_module_phy.sld_mfg_id = 70,
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_action = "",
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_n_scan = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_total_length = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_type_id = 34,
// SOC_NIOS_II_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; vector<string> nap(n); for (int i = 0; i < n; ++i) cin >> nap[i]; vector<vector<int> > dp(26); for (int i = 0; i < 26; ++i) for (int j = 0; j < 26; ++j) dp[i].push_back(0); for (int i = 0; i < n; ++i) { int dl = nap[i].size(); for (char c = a ; c <= z ; ++c) { if (dp[c - a ][nap[i][0] - a ] != 0) { dp[c - a ][nap[i][dl - 1] - a ] = max(dp[c - a ][nap[i][dl - 1] - a ], dp[c - a ][nap[i][0] - a ] + dl); } } dp[nap[i][0] - a ][nap[i][dl - 1] - a ] = max(dp[nap[i][0] - a ][nap[i][dl - 1] - a ], dl); } int odp = 0; for (int i = 0; i < 26; ++i) odp = max(odp, dp[i][i]); cout << odp; return 0; }
|
// nios_tester_mm_interconnect_0_avalon_st_adapter_008.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_tester_mm_interconnect_0_avalon_st_adapter_008 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_tester_mm_interconnect_0_avalon_st_adapter_008_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//---------------------------------------------------------------------
//
// Company: UNSW
// Original Author: Lingkan Gong
// Project Name: XDRS Demo
//
// Create Date: 12/06/2010
// Design Name: xbuscore
//
//---------------------------------------------------------------------
`timescale 1ns/1ns
module xbuscore
(
input clk ,
input rstn ,
//-- to/from xbus master0----
input ma0_req ,
output reg xbm0_gnt ,
input ma0_select ,
input [31:0] ma0_addr ,
input [31:0] ma0_data ,
input ma0_rnw ,
input [3:0] ma0_be ,
output reg xbm0_ack ,
output reg [31:0] xbm0_data ,
//-- to/from xbus master1----
input ma1_req ,
output reg xbm1_gnt ,
input ma1_select ,
input [31:0] ma1_addr ,
input [31:0] ma1_data ,
input ma1_rnw ,
input [3:0] ma1_be ,
output reg xbm1_ack ,
output reg [31:0] xbm1_data ,
//-- to/from xbus master2----
input ma2_req ,
output reg xbm2_gnt ,
input ma2_select ,
input [31:0] ma2_addr ,
input [31:0] ma2_data ,
input ma2_rnw ,
input [3:0] ma2_be ,
output reg xbm2_ack ,
output reg [31:0] xbm2_data ,
//-- to/from xbus master3----
input ma3_req ,
output reg xbm3_gnt ,
input ma3_select ,
input [31:0] ma3_addr ,
input [31:0] ma3_data ,
input ma3_rnw ,
input [3:0] ma3_be ,
output reg xbm3_ack ,
output reg [31:0] xbm3_data ,
//-- to/from xbus slave----
output reg xbs_select ,
output reg [31:0] xbs_addr ,
output reg [31:0] xbs_data ,
output reg xbs_rnw ,
output reg [3:0] xbs_be ,
input sl_ack ,
input [31:0] sl_data
);
`define IDLE 4'h0
`define ARBIT 4'h1
`define TXFER 4'h2
reg [3:0] state_c, state_n;
wire isc_has_request;
wire isc_transfering;
reg [3:0] maid; // current master id
//-------------------------------------------------------------------
// Switch/Mux
//-------------------------------------------------------------------
// current master id
always @(posedge clk or negedge rstn) begin
if (~rstn)
maid <= 4'b0;
else begin
if (state_c == `ARBIT) begin
if (xbm0_gnt == 1'b1) begin maid <= 4'h0; end
else if (xbm1_gnt == 1'b1) begin maid <= 4'h1; end
else if (xbm2_gnt == 1'b1) begin maid <= 4'h2; end
else if (xbm3_gnt == 1'b1) begin maid <= 4'h3; end
else begin maid <= 4'h0; end
end
end
end
always @(*) begin
case (maid)
4'h0: begin
xbs_select = ma0_select ;
xbs_addr = ma0_addr ;
xbs_data = ma0_data ;
xbs_rnw = ma0_rnw ;
xbs_be = ma0_be ;
xbm0_ack = sl_ack ;
xbm0_data = sl_data ;
end
4'h1: begin
xbs_select = ma1_select ;
xbs_addr = ma1_addr ;
xbs_data = ma1_data ;
xbs_rnw = ma1_rnw ;
xbs_be = ma1_be ;
xbm1_ack = sl_ack ;
xbm1_data = sl_data ;
end
4'h2: begin
xbs_select = ma2_select ;
xbs_addr = ma2_addr ;
xbs_data = ma2_data ;
xbs_rnw = ma2_rnw ;
xbs_be = ma2_be ;
xbm2_ack = sl_ack ;
xbm2_data = sl_data ;
end
4'h3: begin
xbs_select = ma3_select ;
xbs_addr = ma3_addr ;
xbs_data = ma3_data ;
xbs_rnw = ma3_rnw ;
xbs_be = ma3_be ;
xbm3_ack = sl_ack ;
xbm3_data = sl_data ;
end
default: begin
xbs_select = 1'b0;
xbs_addr = 32'b0;
xbs_data = 32'b0;
xbs_rnw = 1'b0;
xbs_be = 4'b0;
xbm0_ack = 1'b0;
xbm0_data = 32'b0;
xbm1_ack = 1'b0;
xbm1_data = 32'b0;
xbm2_ack = 1'b0;
xbm2_data = 32'b0;
xbm3_ack = 1'b0;
xbm3_data = 32'b0;
end
endcase
end
//-------------------------------------------------------------------
// Main FSM
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= `IDLE;
else
state_c <= state_n;
end
assign isc_has_request = ma0_req || ma1_req || ma2_req || ma3_req;
assign isc_transfering = xbs_select;
always @(*) begin
{xbm0_gnt,xbm1_gnt,xbm2_gnt,xbm3_gnt} = {1'b0,1'b0,1'b0,1'b0};
case (state_c)
`IDLE: begin state_n = (isc_has_request)? `ARBIT:`IDLE; end
`ARBIT:begin
if (ma0_req == 1'b1) begin xbm0_gnt = 1'b1; end
else if (ma1_req == 1'b1) begin xbm1_gnt = 1'b1; end
else if (ma2_req == 1'b1) begin xbm2_gnt = 1'b1; end
else if (ma3_req == 1'b1) begin xbm3_gnt = 1'b1; end
else begin end
state_n = `TXFER;
end
`TXFER:begin state_n = (isc_transfering)? `TXFER: (isc_has_request)? `ARBIT:`IDLE; end
default: begin state_n = `IDLE; end
endcase
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(*) begin
if (state_c==`IDLE) state_ascii <= "IDLE";
else if (state_c==`ARBIT) state_ascii <= "ARBIT";
else if (state_c==`TXFER) state_ascii <= "TXFER";
else state_ascii <= "ERROR";
end
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:65777216 ) using namespace std; char s[1111][1111]; int n, m; int best; int now; int v[1111][1111]; vector<pair<int, int> > c; bool u[1111][1111]; void dfs(int x, int y) { if (u[x][y]) return; u[x][y] = true; for (int dx(-1); dx < (2); dx++) for (int dy(-1); dy < (2); dy++) { int nx = dx + x; int ny = dy + y; if (nx >= 0 && nx < n && ny >= 0 && ny < m) if (s[nx][ny] == 0 ) dfs(nx, ny); else c.push_back(pair<int, int>(nx, ny)); else c.push_back(pair<int, int>(-1, -1)); } } int startx, starty; int dfs2(int x, int y, int prevx = -1, int prevy = -1) { if (x == startx && y == starty && prevx != -1) return 0; int res = 1; for (int dx(-1); dx < (2); dx++) for (int dy(-1); dy < (2); dy++) if (abs(dx) + abs(dy) == 1) { int nx = x + dx; int ny = y + dy; if (nx >= 0 && nx < n && ny >= 0 && ny < m && v[nx][ny] == v[x][y]) if (nx != prevx || ny != prevy) { res += dfs2(nx, ny, x, y); if (prevx == -1) return res; } } return res; } int main() { cin >> n >> m; for (int i(0); i < (n); i++) scanf( %s , s[i]); for (int i(1); i < (n); i++) for (int j(1); j < (m); j++) if (s[i][j] == 1 && s[i][j - 1] == 1 && s[i - 1][j - 1] == 1 && s[i - 1][j] == 1 ) best = 4; for (int i(0); i < (n); i++) for (int j(0); j < (m); j++) if (s[i][j] == 0 && !u[i][j]) { c.clear(); dfs(i, j); now++; bool good = 1; int num = 0; for (int k(0); k < (c.size()); k++) if (c[k].first == -1) { good = 0; break; } else if (v[c[k].first][c[k].second] != now) v[c[k].first][c[k].second] = now, num++; for (int k(0); k < (c.size()); k++) { int num = 0; for (int dx(-1); dx < (2); dx++) for (int dy(-1); dy < (2); dy++) if (abs(dx) + abs(dy) == 1) { int nx = c[k].first + dx; int ny = c[k].second + dy; if (nx >= 0 && nx < n && ny >= 0 && ny < m && s[nx][ny] == 1 ) if (v[nx][ny] == now) num++; } if (num != 2) { good = 0; break; } } if (good && num > 4) { startx = c[0].first; starty = c[0].second; if (dfs2(c[0].first, c[0].second) == num) best = max(best, num); } } cout << best << endl; return 0; }
|
// file: SysMon_exdes.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the generated VHDL file containing the
// System Monitor instantiation.
//----------------------------------------------------------------------------
`timescale 1ns / 1 ps
module SysMon_exdes(
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
BUSY_OUT, // ADC Busy signal
CHANNEL_OUT, // Channel Selection Outputs
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
EOC_OUT, // End of Conversion Signal
EOS_OUT, // End of Sequence Signal
JTAGBUSY_OUT, // JTAG DRP transaction is in progress signal
JTAGLOCKED_OUT, // DRP port lock request has been made by JTAG
JTAGMODIFIED_OUT, // Indicates JTAG Write to the DRP has occurred
VP_IN, // Dedicated Analog Input Pair
VN_IN);
input VP_IN;
input VN_IN;
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
output BUSY_OUT;
output [4:0] CHANNEL_OUT;
output [15:0] DO_OUT;
output DRDY_OUT;
output EOC_OUT;
output EOS_OUT;
output JTAGBUSY_OUT;
output JTAGLOCKED_OUT;
output JTAGMODIFIED_OUT;
wire GND_BIT;
wire [2:0] GND_BUS3;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_USER_TEMP_ALARM;
assign GND_BIT = 0;
SysMon
sysmon_wiz_inst (
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(DCLK_IN),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.BUSY_OUT(BUSY_OUT),
.CHANNEL_OUT(CHANNEL_OUT[4:0]),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.EOC_OUT(EOC_OUT),
.EOS_OUT(EOS_OUT),
.JTAGBUSY_OUT(JTAGBUSY_OUT),
.JTAGLOCKED_OUT(JTAGLOCKED_OUT),
.JTAGMODIFIED_OUT(JTAGMODIFIED_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
|
`timescale 1ns/1ns
// CRC16
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// 2 direction module.
// inclk, inbit generate crc
// outclk, outbit read out crc.
module crc16(reset, crcinclk, crcbitin, crcoutclk, crcbitout, crcdone);
input reset, crcinclk, crcbitin, crcoutclk;
output crcbitout, crcdone;
reg [15:0] crc;
/*
// working code
reg [3:0] bitoutcounter;
wire crcdone;
assign crcbitout = ~crc[~bitoutcounter];
//assign crcbitout = 0;
assign crcdone = (bitoutcounter == 15);
always @ (posedge crcoutclk or posedge reset) begin
if (reset) begin
bitoutcounter <= 0;
end else if (!crcdone) begin
bitoutcounter <= bitoutcounter + 4'd1;
end // ~reset
end // always
always @ (posedge crcinclk or posedge reset) begin
if (reset) begin
crc <= 'hFFFF;
end else begin
crc[0] <= crcbitin ^ crc[15];
crc[1] <= crc[0];
crc[2] <= crc[1];
crc[3] <= crc[2];
crc[4] <= crc[3];
crc[5] <= crc[4] ^ crcbitin ^ crc[15];
crc[6] <= crc[5];
crc[7] <= crc[6];
crc[8] <= crc[7];
crc[9] <= crc[8];
crc[10] <= crc[9];
crc[11] <= crc[10];
crc[12] <= crc[11] ^ crcbitin ^ crc[15];
crc[13] <= crc[12];
crc[14] <= crc[13];
crc[15] <= crc[14];
end // ~reset
end // always
*/
reg [3:0] bitoutcounter;
wire crcdone;
assign crcbitout = crc[~bitoutcounter];
//assign crcbitout = 0;
assign crcdone = (bitoutcounter == 15);
always @ (posedge crcoutclk or posedge reset) begin
if (reset) begin
bitoutcounter <= 0;
end else if (!crcdone) begin
bitoutcounter <= bitoutcounter + 4'd1;
end // ~reset
end // always
always @ (posedge crcinclk or posedge reset) begin
if (reset) begin
crc <= 'h0000;
end else begin
crc[0] <= ~(crcbitin ^ ~crc[15]);
crc[1] <= crc[0];
crc[2] <= crc[1];
crc[3] <= crc[2];
crc[4] <= crc[3];
crc[5] <= ~(~crc[4] ^ crcbitin ^ ~crc[15]);
crc[6] <= crc[5];
crc[7] <= crc[6];
crc[8] <= crc[7];
crc[9] <= crc[8];
crc[10] <= crc[9];
crc[11] <= crc[10];
crc[12] <= ~(~crc[11] ^ crcbitin ^ ~crc[15]);
crc[13] <= crc[12];
crc[14] <= crc[13];
crc[15] <= crc[14];
end // ~reset
end // always
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m, nex[2000000], hea[2000000], wen[2000000], val[2000000], aid[2000000], root2, root1, len, maxx; struct segment_tree { int a[2000000][2], lazy[2000000], fa[1000000], dep[1000000], in[1000000], out[1000000], m; void pushdown(int k) { if (!lazy[k]) return; swap(a[k << 1][0], a[k << 1][1]); swap(a[(k << 1) | 1][0], a[(k << 1) | 1][1]); lazy[k << 1] ^= 1; lazy[(k << 1) | 1] ^= 1; lazy[k] = 0; } void update1(int l, int r, int k, int x, int y, int z) { if (l == r) { a[k][z] = y; return; } int mid = (l + r) >> 1; if (x <= mid) update1(l, mid, k << 1, x, y, z); if (x > mid) update1(mid + 1, r, (k << 1) | 1, x, y, z); a[k][0] = max(a[k << 1][0], a[(k << 1) | 1][0]); a[k][1] = max(a[k << 1][1], a[(k << 1) | 1][1]); } void update2(int l, int r, int k, int x, int y) { if (l >= x && r <= y) { lazy[k] ^= 1; swap(a[k][0], a[k][1]); return; } pushdown(k); int mid = (l + r) >> 1; if (x <= mid) update2(l, mid, k << 1, x, y); if (y > mid) update2(mid + 1, r, (k << 1) | 1, x, y); a[k][0] = max(a[k << 1][0], a[(k << 1) | 1][0]); a[k][1] = max(a[k << 1][1], a[(k << 1) | 1][1]); } void build(int x, int y, int z) { int a = 0; in[x] = ++m; dep[x] = dep[y] + 1; for (int i = hea[x]; i; i = nex[i]) if (wen[i] != y) { ++a; fa[aid[i]] = wen[i]; build(wen[i], x, z ^ val[i]); } update1(1, n, 1, in[x], dep[x], z); out[x] = m; } void revers(int x) { update2(1, n, 1, in[fa[x]], out[fa[x]]); } } st1, st2; void add(int x, int y, int z, int p) { ++len; nex[len] = hea[x]; wen[len] = y; val[len] = z; aid[len] = p; hea[x] = len; } void dfs(int x, int y, int z) { if (z >= maxx) maxx = z, root1 = x; for (int i = hea[x]; i; i = nex[i]) if (wen[i] != y) dfs(wen[i], x, z + 1); } void dfs1(int x, int y, int z) { if (z >= maxx) maxx = z, root2 = x; for (int i = hea[x]; i; i = nex[i]) if (wen[i] != y) dfs1(wen[i], x, z + 1); } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); add(x, y, z, i); add(y, x, z, i); } dfs(1, 0, 0); dfs1(root1, 0, 0); st1.build(root1, 0, 0); st2.build(root2, 0, 0); scanf( %d , &m); for (int i = 1; i <= m; i++) { int x; scanf( %d , &x); st1.revers(x); st2.revers(x); printf( %d n , max(st1.a[1][0], st2.a[1][0]) - 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 51; struct BIT { int x[MAXN]; inline void add(int pos, int val); inline int query(int pos); }; BIT bit; int n, tp, res, totd, r; int x[MAXN], d[MAXN], st[MAXN], f[MAXN], g[MAXN]; long long int dsc[MAXN]; inline int read() { register int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } inline void BIT::add(int pos, int val) { for (; pos; pos -= pos & -pos) { x[pos] = max(x[pos], val); } } inline int BIT::query(int pos) { int res = 0; for (; pos <= totd; pos += pos & -pos) { res = max(res, x[pos]); } return res; } int main() { n = read(); for (register int i = 0; i <= n + 1; i++) { x[i] = read(); } for (register int i = 1; i <= n; i++) { d[i] = read(); } for (register int i = 1; i <= n; i++) { while (tp && x[i] > (long long int)2 * d[st[tp]] + x[f[st[tp]]]) { tp--; } f[i] = st[tp]; while (tp && (long long int)2 * d[i] + x[f[i]] >= (long long int)2 * d[st[tp]] + x[f[st[tp]]]) { tp--; } st[++tp] = i; } st[tp = 0] = n + 1, res = x[n + 1]; for (register int i = n; i; i--) { while (tp && x[i] < x[g[st[tp]]] - (long long int)2 * d[st[tp]]) { tp--; } g[i] = st[tp]; while (tp && x[g[i]] - (long long int)2 * d[i] <= x[g[st[tp]]] - (long long int)2 * d[st[tp]]) { tp--; } st[++tp] = i; } for (register int i = 1; i <= n; i++) { if (x[g[i]] - x[f[i]] <= 2 * d[i]) { return puts( 0 ), 0; } } for (register int i = 1; i <= n; i++) { res = min(res, x[g[i]] - x[f[i]]); x[i] - x[f[i]] < (long long int)2 * d[i] ? dsc[++totd] = (long long int)2 * d[i] + x[f[i]] : 1; f[i] == 0 && x[g[i]] - x[i] < (long long int)2 * d[i] ? res = min(res, x[i]) : 1; g[i] == n + 1 && x[i] - x[f[i]] < (long long int)2 * d[i] ? res = min(res, x[n + 1] - x[i]) : 1; } sort(dsc + 1, dsc + totd + 1), totd = unique(dsc + 1, dsc + totd + 1) - dsc - 1; for (register int i = 1; i <= n; i++) { if (x[g[i]] - x[i] < (long long int)2 * d[i]) { r = lower_bound(dsc + 1, dsc + totd + 1, x[g[i]] - (long long int)2 * d[i]) - dsc; if (r = bit.query(r)) { res = min(res, x[i] - r); } } if (x[i] - x[f[i]] < (long long int)2 * d[i]) { r = lower_bound(dsc + 1, dsc + totd + 1, x[f[i]] + (long long int)2 * d[i]) - dsc; bit.add(r, x[i]); } } printf( %.1lf n , res * 0.5); }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 * 100 + 10; int a[MAXN], b[MAXN]; int dp[MAXN][310]; vector<int> vec1[MAXN], vec[MAXN]; long long n, m, second, E; bool ok(int k) { long long need = second; for (int i = k - 1; i < n; i++) if (dp[i][k] < m) need = min(need, (long long)(i + 1 + dp[i][k] + 1)); need += k * E; if (need <= second) return true; return false; } int bs(int s, int e) { if (e - s <= 1) return s; int m = (s + e) / 2; return ok(m) ? bs(m, e) : bs(s, m); } int main() { cin >> n >> m >> second >> E; for (int i = 0; i < n; i++) cin >> a[i], vec1[a[i]].push_back(i); for (int i = 0; i < m; i++) cin >> b[i], vec[b[i]].push_back(i); for (int i = 0; i < MAXN; i++) vec[i].push_back(m); for (int i = 0; i < n; i++) for (int j = 0; j < 301; j++) dp[i][j] = m; for (int i = 0; i < n; i++) for (int j = 0; j < min(min((int)m, i + 1), 300) + 1; j++) { if (j == 0) dp[i][j] = -1; else if (i == 0) dp[i][j] = vec[a[i]][lower_bound(vec[a[i]].begin(), vec[a[i]].end(), 0) - vec[a[i]].begin()]; else dp[i][j] = min(dp[i - 1][j], (dp[i - 1][j - 1] >= m) ? (int)m : vec[a[i]] [(int)(lower_bound(vec[a[i]].begin(), vec[a[i]].end(), dp[i - 1][j - 1] + 1) - vec[a[i]].begin())]); } cout << bs(0, min({(int)m, (int)n, 300}) + 1) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n; long long arr[200011]; long long sum[200011]; bool check(int k) { int i; for (i = 1; i <= n; i++) sum[i] = 0; for (i = n; i >= 3; i--) { if (sum[i] + arr[i] < k) return 0; long long d = (sum[i] + arr[i] - k) / 3; long long d3 = d * 3; d3 = min(d3, arr[i]); sum[i - 2] += d3 / 3 * 2; sum[i - 1] += d3 / 3; } return sum[2] + arr[2] >= k && sum[1] + arr[1] >= k; } int main() { cin.tie(nullptr); cout.tie(nullptr); ios::sync_with_stdio(false); int t; cin >> t; while (t--) { cin >> n; int i; for (i = 1; i <= n; i++) cin >> arr[i]; int l = 0, r = 1e9 + 5, mid; while (l + 1 < r) { mid = l + r >> 1; if (check(mid)) l = mid; else r = mid; } cout << l << n ; } return 0; }
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module system ( input CLK,
//DE0 ADC
output ADC_CS,
output ADC_SCLK,
output ADC_SDO,
input ADC_SDI,
//DE0 USER IO
input [1:0] BTNS,
input [3:0] DIP_SW,
output [7:0] LEDS );
//==================WIRE DECLARATIONS============================//
wire CLK_CPU, CLK_MEM, CLK_1M, RESET, RUN, I_SOURCE;
wire [31:0] INST_RD, CPU_RD, CPU_WD, STACK_MEM_WD, STACK_MEM_RD,
INST_D_RD, INST_D_WD;
wire [29:0] INST_ADDR, CPU_ADDR, STACK_MEM_A, INST_D_A;
wire [3:0] CPU_BE, STACK_MEM_BE;
wire CPU_WE, STACK_MEM_WE, INST_D_WE;
//JTAG signals
wire JTAG_WE;
wire [31:0] JTAG_WD, JTAG_RD, DEBUG_INST, CPU_INSTRUCTION;
//ADC signals
wire ADC_WE;
wire [31:0] ADC_RD, ADC_WD;
//USER IO
wire [31:0] USER_IO;
//Led signals
wire [31:0] LEDS_WD;
wire LEDS_WE;
//===================SYSTEM CLOCK================================//
pll main_pll(CLK, CLK_CPU, CLK_MEM, CLK_1M);
//======================THE CPU==================================//
mcpu the_cpu (.CLK ( CLK_CPU ),
.CLK_MEM ( CLK_MEM ),
.RESET ( RESET ),
.RUN ( RUN ),
//External inst memory iface
.INST_ADDR ( INST_ADDR ),
.INST_RD ( CPU_INSTRUCTION ),
//External data memory iface
.DATA_WE ( CPU_WE ),
.DATA_BE ( CPU_BE ),
.DATA_ADDR ( CPU_ADDR ),
.DATA_WD ( CPU_WD ),
.DATA_RD ( CPU_RD ));
//===================INSTRUCTION MEMORY==========================//
imem instr_mem( .CLK ( CLK_MEM ),
.DATA_A ( INST_D_A ),
.DATA_WE ( INST_D_WE ),
.DATA_WD ( INST_D_WD ),
.DATA_RD ( INST_D_RD ),
.MAIN_A ( INST_ADDR ),
.MAIN_RD ( INST_RD ));
//======================STACK SPACE==============================//
dmem stack_mem( .CLK ( CLK_MEM ),
.WE ( STACK_MEM_WE ),
.BE ( STACK_MEM_BE ),
.ADDR ( STACK_MEM_A ),
.WD ( STACK_MEM_WD ),
.RD ( STACK_MEM_RD ));
jtag jtag_m ( .CPU_CLK ( CLK_CPU ),
//CPU controls
.RESET ( RESET ), //cpu reset, 1 -- reset;
.RUN ( RUN ), //cpu run. 0 - pause, 1 - run. Pulsed in step-by-step
.I_SOURCE ( I_SOURCE ), //cpu instruction source; 0 for normal mem
//32bit DEBUG DATA PORT
.WE ( JTAG_WE ),
.WD ( JTAG_WD ),
.RD ( JTAG_RD ),
//32bit DEBUG INSTR PORT
.DEBUG_INST ( DEBUG_INST ), //cpu instruction from jtag
.MEM_INST ( INST_RD ), //current instruction from main mem
.INST_ADDR ( INST_ADDR )); //cpu inst memory address
mux2 isrc_mux (I_SOURCE, INST_RD,
DEBUG_INST, CPU_INSTRUCTION );
//=====================BUS CONTROLLER============================//
bus_controller bc( .CPU_ADDR ( CPU_ADDR ),
.CPU_WE ( CPU_WE ),
.CPU_BE ( CPU_BE ),
.CPU_WD ( CPU_WD ),
.CPU_RD ( CPU_RD ),
.STACK_MEM_A ( STACK_MEM_A ),
.STACK_MEM_BE ( STACK_MEM_BE ),
.STACK_MEM_WE ( STACK_MEM_WE ),
.STACK_MEM_WD ( STACK_MEM_WD ),
.STACK_MEM_RD ( STACK_MEM_RD ),
.CODE_MEM_A ( INST_D_A ),
.CODE_MEM_WE ( INST_D_WE ),
.CODE_MEM_WD ( INST_D_WD ),
.CODE_MEM_RD ( INST_D_RD ),
.JTAG_WE ( JTAG_WE ),
.JTAG_WD ( JTAG_WD ),
.JTAG_RD ( JTAG_RD ),
.ADC_WE ( ADC_WE ),
.ADC_WD ( ADC_WD ),
.ADC_RD ( ADC_RD ),
.USER_IO ( USER_IO ),
.LEDS_WE ( LEDS_WE ),
.LEDS_WD ( LEDS_WD ));
//========================LEDS===================================//
io8 led_reg( .CLK ( CLK_CPU ),
.WE ( LEDS_WE ),
.DATA_IN ( LEDS_WD ),
.IO_OUT ( LEDS ));
//======================USER INPUT===============================//
io6 user_io( .CLK_IO ( CLK_1M ),
.BTNS ( BTNS ),
.DIP_SW ( DIP_SW ),
.IO_OUT ( USER_IO ));
//=========================ADC===================================//
adc_interface the_adc( .CLK ( CLK_CPU ),
.CLK_1M ( CLK_1M ),
//processor interface
.DATA_IN ( ADC_WD ),
.DATA_OUT ( ADC_RD ),
.WR ( ADC_WE ),
//device interface
.CS ( ADC_CS ),
.SCLK ( ADC_SCLK ),
.SDO ( ADC_SDO ),
.SDI ( ADC_SDI ));
endmodule
//===============================================================//
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#include <bits/stdc++.h> long long m; long long from, to; long long x, y; int visit[2][1000010]; int main() { std::cin >> m; int i, time; int cs[2], ci[2], targ[2]; for (i = 0; i < 2; ++i) { std::cin >> from >> to >> x >> y; time = 1; int cur = from; while (true) { if (visit[i][cur]) { cs[i] = time - visit[i][cur]; ci[i] = visit[i][cur]; break; } visit[i][cur] = time; cur = (cur * x + y) % m; ++time; } targ[i] = visit[i][to]; } if (targ[0] == 0 || targ[1] == 0) { std::cout << -1; } else { bool oncyc[2]; for (i = 0; i < 2; ++i) oncyc[i] = (targ[i] >= ci[i]); if (!oncyc[0] && !oncyc[1]) { if (targ[0] != targ[1]) std::cout << -1; else std::cout << targ[0] - 1; } else if (!oncyc[0]) { if (targ[0] >= targ[1] && !((targ[0] - targ[1]) % cs[1])) std::cout << targ[0] - 1; else std::cout << -1; } else if (!oncyc[1]) { if (targ[1] >= targ[0] && !((targ[1] - targ[0]) % cs[0])) std::cout << targ[1] - 1; else std::cout << -1; } else { long long cur = targ[0]; for (i = 0; i <= m + 1; ++i) { if (cur >= targ[1] && (cur - targ[1]) % cs[1] == 0) break; cur += cs[0]; } if (i <= m + 1) std::cout << cur - 1; else std::cout << -1; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 101000; const double eps = 1e-9, g = 9.8; double V, angle, ca, sa, Y, K, x, y; int i, j, k, l, m, n, o, p; inline int sn(double x) { return x < -eps ? -1 : x > eps ? 1 : 0; } inline double Sqr(double x) { return x * x; } struct Point { double x, y; inline void read() { scanf( %lf%lf , &x, &y); } bool operator<(const Point &t) const { return x < t.x; } } wall[N], ans[N]; struct fire { double a, b; int i; fire() {} fire(double x, double y, int id) { a = x; b = y; i = id; } inline void read(int id) { scanf( %lf , &angle); ca = cos(angle); sa = sin(angle); a = g / (2 * Sqr(V * ca)); b = sa / ca; i = id; ans[i].x = (b / a); ans[i].y = 0; } bool operator<(const fire &t) const { double b1 = b - K * a, b2 = t.b - K * t.a; return (b1 < b2) || (!sn(b1 - b2) && (i < t.i)); } } Tfire, P; set<fire> F; set<fire>::iterator pos; int main() { scanf( %d%lf , &n, &V); K = (double)0.455555; for (i = 1; i <= n; i++) { Tfire.read(i); F.insert(Tfire); } scanf( %d , &m); for (i = 1; i <= m; i++) wall[i].read(); sort(wall + 1, wall + m + 1); for (i = 1; i <= m; i++) { K = wall[i].x; Y = wall[i].y / wall[i].x; while (1) { pos = F.lower_bound(fire(0, Y + eps, N)); if (pos == F.begin()) break; pos--; P = (*pos); j = P.i; if (ans[j].x > wall[i].x) { ans[j].x = wall[i].x; ans[j].y = (-P.a) * Sqr(wall[i].x) + wall[i].x * P.b; } F.erase(pos); } } for (i = 1; i <= n; i++) printf( %.9lf %.9lf n , ans[i].x, ans[i].y); return 0; }
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#include <bits/stdc++.h> using namespace std; using SI = set<int>; using ULL = unsigned long long; using LL = long long; using VI = vector<int>; using LD = long double; using PULL = pair<ULL, ULL>; using UI = unsigned int; using PLL = pair<LL, LL>; using PDD = pair<LD, LD>; using MII = map<int, int>; using TDD = pair<PDD, LD>; using TLL = pair<PLL, LL>; using PII = pair<int, int>; using TII = pair<PII, int>; using QDD = pair<PDD, PDD>; using QII = pair<PII, PII>; using QLL = pair<PLL, PLL>; using STII = set<TII>; using VTII = vector<TII>; using MTII = map<TII, TII>; using MITII = map<int, TII>; using UMITII = unordered_map<int, TII>; using SQII = set<QII>; using VQII = vector<QII>; using MQII = map<QII, QII>; using MIQII = map<int, QII>; using UMIQII = unordered_map<int, QII>; using SLL = set<LL>; using VLL = vector<LL>; using MLL = map<LL, LL>; using MILL = map<int, LL>; using UMILL = unordered_map<int, LL>; using SULL = set<ULL>; using VULL = vector<ULL>; using MULL = map<ULL, ULL>; using MIULL = map<int, ULL>; using UMIULL = unordered_map<int, ULL>; using SPULL = set<PULL>; using VPULL = vector<PULL>; using MPULL = map<PULL, PULL>; using MIPULL = map<int, PULL>; using UMIPULL = unordered_map<int, PULL>; using SQLL = set<QLL>; using VQLL = vector<QLL>; using MQLL = map<QLL, QLL>; using MIQLL = map<int, QLL>; using UMIQLL = unordered_map<int, QLL>; using SLD = set<LD>; using VLD = vector<LD>; using MLD = map<LD, LD>; using MILD = map<int, LD>; using UMILD = unordered_map<int, LD>; using SPDD = set<PDD>; using VPDD = vector<PDD>; using MPDD = map<PDD, PDD>; using MIPDD = map<int, PDD>; using UMIPDD = unordered_map<int, PDD>; using SVI = set<VI>; using VVI = vector<VI>; using MVI = map<VI, VI>; using MIVI = map<int, VI>; using UMIVI = unordered_map<int, VI>; using STLL = set<TLL>; using VTLL = vector<TLL>; using MTLL = map<TLL, TLL>; using MITLL = map<int, TLL>; using UMITLL = unordered_map<int, TLL>; using SUI = set<UI>; using VUI = vector<UI>; using MUI = map<UI, UI>; using MIUI = map<int, UI>; using UMIUI = unordered_map<int, UI>; using SPII = set<PII>; using VPII = vector<PII>; using MPII = map<PII, PII>; using MIPII = map<int, PII>; using UMIPII = unordered_map<int, PII>; using SPLL = set<PLL>; using VPLL = vector<PLL>; using MPLL = map<PLL, PLL>; using MIPLL = map<int, PLL>; using UMIPLL = unordered_map<int, PLL>; using SSI = set<SI>; using VSI = vector<SI>; using MSI = map<SI, SI>; using MISI = map<int, SI>; using UMISI = unordered_map<int, SI>; using SVVI = set<VVI>; using VVVI = vector<VVI>; using MVVI = map<VVI, VVI>; using MIVVI = map<int, VVI>; using UMIVVI = unordered_map<int, VVI>; using UMII = unordered_map<int, int>; ULL randULL() { return ((ULL)rand()) ^ ((ULL)rand() << 15) ^ ((ULL)rand() << 30) ^ ((ULL)rand() << 45) ^ ((ULL)rand() << 60); } using STDD = set<TDD>; using VTDD = vector<TDD>; using MTDD = map<TDD, TDD>; using MITDD = map<int, TDD>; using UMITDD = unordered_map<int, TDD>; using SQDD = set<QDD>; using VQDD = vector<QDD>; using MQDD = map<QDD, QDD>; using MIQDD = map<int, QDD>; using UMIQDD = unordered_map<int, QDD>; int popc(int x) { return __builtin_popcount(x); } int popc(UI x) { return __builtin_popcount(x); } int popc(LL x) { return __builtin_popcountll(x); } int popc(ULL x) { return __builtin_popcountll(x); } int ctz(int x) { return __builtin_ctz(x); } int ctz(UI x) { return __builtin_ctz(x); } int ctz(LL x) { return __builtin_ctzll(x); } int ctz(ULL x) { return __builtin_ctzll(x); } int clz(int x) { return __builtin_clz(x); } int clz(UI x) { return __builtin_clz(x); } int clz(LL x) { return __builtin_clzll(x); } int clz(ULL x) { return __builtin_clzll(x); } int bit_parity(int x) { return __builtin_parity(x); } int bit_parity(UI x) { return __builtin_parity(x); } int bit_parity(LL x) { return __builtin_parityll(x); } int bit_parity(ULL x) { return __builtin_parityll(x); } template <class T, class U> bool one_of(T x, U y) { return x == y; } template <class T, class U, class... V> bool one_of(T x, U y, V... z) { return x == y || one_of(x, z...); } template <class T> bool diff(T _) { return true; } template <class T, class... U> bool diff(T x, U... y) { return !one_of(x, y...) && diff(y...); } template <class T, class U> bool equal(T x, U y) { return x == y; } template <class T, class U, class... V> bool equal(T x, U y, V... z) { return x == y && equal(x, z...); } template <class T, class U> bool in_order(T x, U y) { return x <= y; } template <class T, class U, class... V> bool in_order(T x, U y, V... z) { return x <= y && in_order(y, z...); } template <class T, class U> bool in_strorder(T x, U y) { return x < y; } template <class T, class U, class... V> bool in_strorder(T x, U y, V... z) { return x < y && in_strorder(y, z...); } template <class T> void swap3(T &x, T &y, T &z) { swap(x, y); swap(x, z); } template <class T> pair<T, T> dup(T x) { return make_pair(x, x); } template <class T> pair<pair<T, T>, T> thrice(T x) { return make_pair(make_pair(x, x), x); } template <class T> pair<pair<T, T>, pair<T, T>> fourfold(T x) { return make_pair(make_pair(x, x), make_pair(x, x)); } template <class T, class U, class V> T safvec(const vector<T> &v, int i, U low, V high) { if (i < 0) return low; if (i >= ((int)(v).size())) return high; return v[i]; } template <class T, class U> T safar(T *a, int i, U low) { if (i < 0) return low; return a[i]; } template <class T, class U, class V> auto med(const T &a, const U &b, const V &c) -> decltype(1 ? a : (1 ? b : c)) { return my_min(my_max(a, b), my_max(my_min(a, b), c)); } namespace std { template <class T, class U> struct hash<pair<T, U>> { size_t operator()(const pair<T, U> &a) const { return (hash<T>()(a.first) * 1420343LL ^ hash<U>()(a.second) * 923275LL) % 1463984161; } }; } // namespace std template <class T, class U> auto my_min(const U &x, const T &y) -> decltype(1 ? x : y) { return x < y ? x : y; } template <class T, class U> bool mini(U &x, T y) { if (y < x) { x = y; return true; } return false; } template <class T, class U, class V> auto my_min(const T &a, const U &b, const V &c) -> decltype(1 ? a : (1 ? b : c)) { return my_min(a, my_min(b, c)); } template <class T, class U, class V, class W> auto my_min(const T &a, const U &b, const V &c, const W &d) -> decltype(1 ? a : (1 ? b : (1 ? c : d))) { return my_min(a, my_min(b, c, d)); } template <class T, class U> auto my_max(const U &x, const T &y) -> decltype(1 ? x : y) { return x > y ? x : y; } template <class T, class U> bool maxi(U &x, T y) { if (y > x) { x = y; return true; } return false; } template <class T, class U, class V> auto my_max(const T &a, const U &b, const V &c) -> decltype(1 ? a : (1 ? b : c)) { return my_max(a, my_max(b, c)); } template <class T, class U, class V, class W> auto my_max(const T &a, const U &b, const V &c, const W &d) -> decltype(1 ? a : (1 ? b : (1 ? c : d))) { return my_max(a, my_max(b, c, d)); } template <class T> T brange(int l, int r) { return ~(~((T)0) << (r - l + 1)) << l; } template <class T> T brange(int l, int r, int second) { return (brange<T>(l, l + (r - l) / second * second - 1) / brange<T>(0, second - 1)) | ((T)1 << (l + (r - l) / second * second)); } template <class T> auto O2kQ(T x, int i, int j) -> vector<typename remove_reference<decltype(*x.end())>::type> { vector<typename remove_reference<decltype(*x.end())>::type> ans; for (auto c : x) if ((--i < 0) & (j-- >= 0)) ans.push_back(c); return ans; } template <class T> vector<T> O2kQ(const T *x, int i, int j) { vector<T> ans; for (int _ = i; _ <= (int)(j); _++) ans.push_back(x[_]); return ans; } int CON_BOUND = 10; string E0ms() { return ; } template <class T> string E0ms(T x) { stringstream os; os << boolalpha << x; return os.str(); } template <class T, class... U> string E0ms(T x, U... y) { return E0ms(x) + , + E0ms(y...); } string SqC6(bool x) { return x ? true : false ; } template <class T> typename enable_if<is_integral<T>::value, string>::type SqC6(T r) { string a; for (int i = 8 * sizeof(T) - 1; i >= (int)(0); i--) { if (i % 5 == 4) a += . ; a += 0 + !!(((T)1 << i) & r); } return a; } template <class T, class C> string SqC6(pair<T, C>); template <class T> auto SqC6(T x) -> decltype(x.end(), string()) { string a = ; for (auto c : x) { if (((int)(a).size())) a += , ; a += SqC6(c); } return { + a + }_ + to_string(((int)(x).size())); } template <class T, class C> string SqC6(pair<T, C> x) { return < + SqC6(x.first) + , + SqC6(x.second) + > ; } template <class T, int N> T &arrp(T a[][N], PII x) { return a[x.first][x.second]; } const int mod = 1e9 + 7; LL mpow(LL b, int e) { LL ans = 1; while (e) { if (e & 1) ans = ans * b % mod; b = b * b % mod; e /= 2; } return ans; } struct zet_p { int v; int get() { return v; } zet_p(LL x = 0) { v = x % mod; } zet_p operator+(zet_p x) { return (v + x.v) % mod; } zet_p operator-(zet_p x) { return v - x.v; } zet_p operator*(zet_p x) { return v * 1ll * x.v; } zet_p operator/(zet_p a) { return v * mpow(a.v, mod - 2); } }; const bool deb = false; struct frac_mod { int n, d; frac_mod(int x = 0) { n = x % mod; d = 1; } frac_mod(int x, int y) { n = x; d = y; } frac_mod operator+(frac_mod x) { return {(int)((x.d * 1ll * n + d * 1ll * x.n) % mod), x.d * d % mod}; } frac_mod operator-(frac_mod x) { return {(int)((n * 1ll * x.d - x.n * 1ll * d) % mod), x.d * d % mod}; } frac_mod operator*(frac_mod x) { return {(int)((n * (LL)x.n) % mod), (int)((d * (LL)x.d) % mod)}; } frac_mod operator/(frac_mod x) { return {(int)(n * (LL)x.d % mod), (int)(d * (LL)x.n % mod)}; } int get() { int ans = n * mpow(d, mod - 2) % mod; if (ans < 0) ans += mod; return ans; } }; template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator+( frac_mod x, T y) { return x + frac_mod(y); } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator+( T x, frac_mod y) { return frac_mod(x) + y; } template <class T> frac_mod &operator+=(frac_mod &x, T y) { return x = x + y; } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator-( frac_mod x, T y) { return x - frac_mod(y); } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator-( T x, frac_mod y) { return frac_mod(x) - y; } template <class T> frac_mod &operator-=(frac_mod &x, T y) { return x = x - y; } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator*( frac_mod x, T y) { return x * frac_mod(y); } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator*( T x, frac_mod y) { return frac_mod(x) * y; } template <class T> frac_mod &operator*=(frac_mod &x, T y) { return x = x * y; } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator/( frac_mod x, T y) { return x / frac_mod(y); } template <class T> typename enable_if<is_arithmetic<T>::value, frac_mod>::type operator/( T x, frac_mod y) { return frac_mod(x) / y; } template <class T> frac_mod &operator/=(frac_mod &x, T y) { return x = x / y; } template <class T, class C> ostream &operator<<(ostream &ans, pair<T, C> x) { return ans << < << x.first << , << x.second << > ; } template <class T> auto operator<<(ostream &o, T x) -> typename enable_if<!is_same<T, string>::value, decltype(x.end(), o)>::type { o << { ; int i = 0; for (auto c : x) { if (i++ == ((int)(x).size()) - 1 || ((int)(x).size()) < CON_BOUND + 2 || i < CON_BOUND) { if (i - 1 && (i != ((int)(x).size()) || ((int)(x).size()) < CON_BOUND + 2)) o << , ; o << c; } if (i == CON_BOUND && ((int)(x).size()) > CON_BOUND + 1) o << ... ; } return o << }_ << x.size(); } string b7Pe(string x) { int dep = 0; for (char c : x) { for (char d : ([{ ) if (c == d) dep++; for (char d : }]) ) if (c == d) dep--; for (char d : +-*/%^<>=&|?, ) if (c == d && !dep) return ( + x + ) ; } return x; } template <class T, class U> pair<U, T> pinv(pair<T, U> x) { return make_pair(x.second, x.first); } template <class T> struct Wt71 { T c; int l, r, L, R; }; template <class T> ostream &operator<<(ostream &o, Wt71<T> M) { o << n ; for (int i = M.l; i <= (int)(M.r); i++) { o << << i << : | ; for (int j = M.L; j <= (int)(M.R); j++) { o << M.c[i][j] << ((j - M.L + 1) % 5 ? : ; ); } o << n ; } return o; } template <class T> Wt71<T> q9cX(T a, int i, int j, int k, int q) { return {a, i, j, k, q}; } int primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, 941, 947, 953, 967, 971, 977, 983, 991, 997}, big_primes[] = {1307533217, 1336158883, 1339172111, 1367797777, 1376837461, 1399436671, 1426555723, 1440115249, 1444635091, 1489833511, 1553111299, 1562150983, 1587763421, 1610362631, 1652547823, 1666107349, 1700759471, 1782116627, 1797182767, 1810742293, 1818275363, 1892099449, 1904152361, 1919218501, 1940311097, 1944830939, 1968936763, 1977976447, 1985509517, 1990029359}, gens[] = {1, 2, 3, 5, 2, 11, 3, 14, 19, 11, 17, 32, 30, 34, 29, 19, 34, 31, 63, 33, 5, 63, 53, 58, 40, 83, 21, 18, 99, 33, 106, 40, 85, 109, 40, 77, 91, 120, 105, 91, 79, 53, 182, 10, 184, 48, 48, 150, 168, 72, 65, 46, 31, 216, 101, 134, 163, 147, 93, 42, 69, 7, 151, 308, 112, 12, 227, 185, 214, 305, 163, 234, 154, 316, 3, 11, 233, 390, 271, 173, 82, 407, 13, 135, 414, 391, 177, 293, 426, 432, 337, 281, 385, 103, 95, 152, 12, 371, 390, 77, 532, 34, 287, 73, 308, 493, 258, 549, 528, 411, 12, 283, 614, 596, 622, 309, 91, 511, 287, 433, 585, 123, 2, 170, 183, 341, 459, 322, 333, 337, 507, 718, 82, 517, 396, 315, 565, 48, 362, 617, 776, 425, 584, 231, 578, 395, 127, 27, 506, 435, 727, 659, 697, 385, 290, 109, 430, 422, 344, 849, 513, 453, 852, 920, 152, 482, 653, 271}, big_gens[] = {661761153, 1315209189, 235649158, 80905954, 861543922, 677870461, 332266749, 1192707557, 820697698, 93737534, 1395132003, 176849700, 1113502216, 860516128, 1543755630, 328298286, 1219407972, 1407392293, 733053145, 400000570, 1081174233, 847228024, 1516266762, 83276926, 500618997, 44975430, 47827763, 1411328206, 151880843, 19696955}; LL vbig_primes[] = { 1223771071LL, 2557943639LL, 4625922079LL, 8465729693LL, 16196062793LL, 32628322457LL, 64355194333LL, 128143942897LL, 256728067087LL, 512368953949LL, 1024440714547LL, 2048302681847LL, 4096121499499LL, 8192933500519LL, 16384652744209LL, 32768255472209LL, 65536007832649LL, 131072225217863LL, 262144391360893LL, 524288060819213LL, 1048576249040491LL, 2097152266756471LL, 4194304028438527LL, 8388608209001387LL, 16777216572671047LL, 33554432072300339LL, 67108864903274897LL, 134217728402776373LL, 268435456069367221LL, 536870912016065747LL}; const int inf = 1e9, NONE = -1; const LL llinf = 3e18; const char *sc2 = %d%d , *sc3 = %d%d%d , *sc4 = %d%d%d%d , *pr2 = %d %d n , *pr3 = %d %d %d n , *pr4 = %d %d %d %d n ; VI factor(int x) { VI ans; for (int p = 2; p * p <= x; ++p) while (x % p == 0) { ans.push_back(p); x /= p; } if (x > 1) ans.push_back(x); return ans; } template <class T, class B, class C, class D> auto operator+(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first + y.first), decltype(x.second + y.second)> { return make_pair(x.first + y.first, x.second + y.second); } template <class T, class B, class C> auto operator+(pair<T, B> x, C y) -> pair<decltype(x.first + y), decltype(x.second + y)> { return make_pair(x.first + y, x.second + y); } template <class T, class C, class D> auto operator+(T x, pair<C, D> y) -> pair<decltype(x + y.first), decltype(x + y.second)> { return make_pair(x + y.first, x + y.second); } template <class T, class B, class C, class D> auto operator-(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first - y.first), decltype(x.second - y.second)> { return make_pair(x.first - y.first, x.second - y.second); } template <class T, class B, class C> auto operator-(pair<T, B> x, C y) -> pair<decltype(x.first - y), decltype(x.second - y)> { return make_pair(x.first - y, x.second - y); } template <class T, class C, class D> auto operator-(T x, pair<C, D> y) -> pair<decltype(x - y.first), decltype(x - y.second)> { return make_pair(x - y.first, x - y.second); } template <class T, class B, class C, class D> auto operator/(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first / y.first), decltype(x.second / y.second)> { return make_pair(x.first / y.first, x.second / y.second); } template <class T, class B, class C> auto operator/(pair<T, B> x, C y) -> pair<decltype(x.first / y), decltype(x.second / y)> { return make_pair(x.first / y, x.second / y); } template <class T, class C, class D> auto operator/(T x, pair<C, D> y) -> pair<decltype(x / y.first), decltype(x / y.second)> { return make_pair(x / y.first, x / y.second); } template <class T, class B, class C, class D> auto operator*(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first * y.first), decltype(x.second * y.second)> { return make_pair(x.first * y.first, x.second * y.second); } template <class T, class B, class C> auto operator*(pair<T, B> x, C y) -> pair<decltype(x.first * y), decltype(x.second * y)> { return make_pair(x.first * y, x.second * y); } template <class T, class C, class D> auto operator*(T x, pair<C, D> y) -> pair<decltype(x * y.first), decltype(x * y.second)> { return make_pair(x * y.first, x * y.second); } template <class T, class B, class C, class D> auto operator%(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first % y.first), decltype(x.second % y.second)> { return make_pair(x.first % y.first, x.second % y.second); } template <class T, class B, class C> auto operator%(pair<T, B> x, C y) -> pair<decltype(x.first % y), decltype(x.second % y)> { return make_pair(x.first % y, x.second % y); } template <class T, class C, class D> auto operator%(T x, pair<C, D> y) -> pair<decltype(x % y.first), decltype(x % y.second)> { return make_pair(x % y.first, x % y.second); } template <class T, class B, class C, class D> auto operator&(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first & y.first), decltype(x.second & y.second)> { return make_pair(x.first & y.first, x.second & y.second); } template <class T, class B, class C> auto operator&(pair<T, B> x, C y) -> pair<decltype(x.first & y), decltype(x.second & y)> { return make_pair(x.first & y, x.second & y); } template <class T, class C, class D> auto operator&(T x, pair<C, D> y) -> pair<decltype(x & y.first), decltype(x & y.second)> { return make_pair(x & y.first, x & y.second); } template <class T, class B, class C, class D> auto operator|(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first | y.first), decltype(x.second | y.second)> { return make_pair(x.first | y.first, x.second | y.second); } template <class T, class B, class C> auto operator|(pair<T, B> x, C y) -> pair<decltype(x.first | y), decltype(x.second | y)> { return make_pair(x.first | y, x.second | y); } template <class T, class C, class D> auto operator|(T x, pair<C, D> y) -> pair<decltype(x | y.first), decltype(x | y.second)> { return make_pair(x | y.first, x | y.second); } template <class T, class B, class C, class D> auto operator^(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first ^ y.first), decltype(x.second ^ y.second)> { return make_pair(x.first ^ y.first, x.second ^ y.second); } template <class T, class B, class C> auto operator^(pair<T, B> x, C y) -> pair<decltype(x.first ^ y), decltype(x.second ^ y)> { return make_pair(x.first ^ y, x.second ^ y); } template <class T, class C, class D> auto operator^(T x, pair<C, D> y) -> pair<decltype(x ^ y.first), decltype(x ^ y.second)> { return make_pair(x ^ y.first, x ^ y.second); } template <class T, class B, class C, class D> auto operator&&(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first && y.first), decltype(x.second && y.second)> { return make_pair(x.first && y.first, x.second && y.second); } template <class T, class B, class C> auto operator&&(pair<T, B> x, C y) -> pair<decltype(x.first && y), decltype(x.second && y)> { return make_pair(x.first && y, x.second && y); } template <class T, class C, class D> auto operator&&(T x, pair<C, D> y) -> pair<decltype(x && y.first), decltype(x && y.second)> { return make_pair(x && y.first, x && y.second); } template <class T, class B, class C, class D> auto operator||(pair<T, B> x, pair<C, D> y) -> pair<decltype(x.first || y.first), decltype(x.second || y.second)> { return make_pair(x.first || y.first, x.second || y.second); } template <class T, class B, class C> auto operator||(pair<T, B> x, C y) -> pair<decltype(x.first || y), decltype(x.second || y)> { return make_pair(x.first || y, x.second || y); } template <class T, class C, class D> auto operator||(T x, pair<C, D> y) -> pair<decltype(x || y.first), decltype(x || y.second)> { return make_pair(x || y.first, x || y.second); } template <class T, class B> pair<T, B> &operator++(pair<T, B> &x) { ++x.first, ++x.second; return x; } template <class T, class B> pair<T, B> operator++(pair<T, B> &x, int _) { return make_pair(x.first++, x.second++); } template <class T, class B> pair<T, B> &operator--(pair<T, B> &x) { --x.first, --x.second; return x; } template <class T, class B> pair<T, B> operator--(pair<T, B> &x, int _) { return make_pair(x.first--, x.second--); } template <class T, class B, class C, class D> pair<T, B> &operator+=(pair<T, B> &x, pair<C, D> y) { x.first += y.first; x.second += y.second; return x; } template <class T, class B, class C> pair<T, B> &operator+=(pair<T, B> &x, C y) { x.first += y; x.second += y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator-=(pair<T, B> &x, pair<C, D> y) { x.first -= y.first; x.second -= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator-=(pair<T, B> &x, C y) { x.first -= y; x.second -= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator*=(pair<T, B> &x, pair<C, D> y) { x.first *= y.first; x.second *= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator*=(pair<T, B> &x, C y) { x.first *= y; x.second *= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator/=(pair<T, B> &x, pair<C, D> y) { x.first /= y.first; x.second /= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator/=(pair<T, B> &x, C y) { x.first /= y; x.second /= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator%=(pair<T, B> &x, pair<C, D> y) { x.first %= y.first; x.second %= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator%=(pair<T, B> &x, C y) { x.first %= y; x.second %= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator^=(pair<T, B> &x, pair<C, D> y) { x.first ^= y.first; x.second ^= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator^=(pair<T, B> &x, C y) { x.first ^= y; x.second ^= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator&=(pair<T, B> &x, pair<C, D> y) { x.first &= y.first; x.second &= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator&=(pair<T, B> &x, C y) { x.first &= y; x.second &= y; return x; } template <class T, class B, class C, class D> pair<T, B> &operator|=(pair<T, B> &x, pair<C, D> y) { x.first |= y.first; x.second |= y.second; return x; } template <class T, class B, class C> pair<T, B> &operator|=(pair<T, B> &x, C y) { x.first |= y; x.second |= y; return x; } template <class T, class B> auto operator*(pair<T, B> x) -> pair<typename remove_reference<decltype(*x.first)>::type, typename remove_reference<decltype(*x.second)>::type> { return make_pair(*x.first, *x.second); } template <class T, class B> auto operator~(pair<T, B> x) -> pair<typename remove_reference<decltype(~x.first)>::type, typename remove_reference<decltype(~x.second)>::type> { return make_pair(~x.first, ~x.second); } template <class T, class B> auto operator!(pair<T, B> x) -> pair<typename remove_reference<decltype(!x.first)>::type, typename remove_reference<decltype(!x.second)>::type> { return make_pair(!x.first, !x.second); } template <class T, class B> auto operator-(pair<T, B> x) -> pair<typename remove_reference<decltype(-x.first)>::type, typename remove_reference<decltype(-x.second)>::type> { return make_pair(-x.first, -x.second); } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator+(zet_p x, T y) { return x + zet_p(y); } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator+(T x, zet_p y) { return zet_p(x) + y; } template <class T> zet_p &operator+=(zet_p &x, T y) { return x = x + y; } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator-(zet_p x, T y) { return x - zet_p(y); } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator-(T x, zet_p y) { return zet_p(x) - y; } template <class T> zet_p &operator-=(zet_p &x, T y) { return x = x - y; } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator*(zet_p x, T y) { return x * zet_p(y); } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator*(T x, zet_p y) { return zet_p(x) * y; } template <class T> zet_p &operator*=(zet_p &x, T y) { return x = x * y; } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator/(zet_p x, T y) { return x / zet_p(y); } template <class T> typename enable_if<is_arithmetic<T>::value, zet_p>::type operator/(T x, zet_p y) { return zet_p(x) / y; } template <class T> zet_p &operator/=(zet_p &x, T y) { return x = x / y; } void jGB4A(); const int MN = 1e5 + 44; SPII best[MN]; void add(SPII &se, PII val) { ; auto pre = se.upper_bound(make_pair(val.first, inf)); pre--; if (pre->second > val.second) { ; return; } while (pre != se.end() && pre->second <= val.second) { if (pre->first >= val.first) se.erase(pre++); else pre++; } se.insert(val); ; } int main() { SPII test; for (int i = 0; i < (int)(10); i++) test.insert(make_pair(i * 3, i * 3)); add(test, make_pair(6, 6)); add(test, make_pair(6, 7)); add(test, make_pair(6, 6)); add(test, make_pair(0, 7)); ; ; ; ; cerr << setprecision(10); int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= (int)(n); i++) { best[i].insert(make_pair(-inf, 0)); } for (int i = 0; i < (int)(m); i++) { int a, b, x; scanf( %d%d%d , &a, &b, &x); auto it = best[a].upper_bound(make_pair(x, -inf)); ; ; it--; ; add(best[b], make_pair(x, it->second + 1)); } int ans = 0; for (int i = 1; i <= (int)(n); i++) { auto l = best[i].end(); l--; maxi(ans, l->second); } printf( %d n , ans); jGB4A(); } void jGB4A() { #pragma GCC diagnostic ignored -Woverflow ; ; ; ; ; ; ; ; ; ; while (deb && getchar() != EOF) ; exit(0); }
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#include <bits/stdc++.h> using namespace std; const int P = 1000000007; const int N = 1010000; int fail[N]; int go[N][26], len[N], diff[N], anc[N], lst; int n; char str[N]; int p; int s[N]; int f[N], g[N]; void addChar(int c, int ww) { int x = lst; while (s[ww] != s[ww - len[x] - 1]) { x = fail[x]; } if (!go[x][c]) { len[p] = len[x] + 2; int k = fail[x]; while (s[ww] != s[ww - len[k] - 1]) k = fail[k]; fail[p] = go[k][c]; go[x][c] = p; diff[p] = len[p] - len[fail[p]]; if (diff[p] == diff[fail[p]]) anc[p] = anc[fail[p]]; else anc[p] = fail[p]; p++; } lst = go[x][c]; } void init() { p = 2; len[0] = 0; len[1] = -1; fail[0] = 1; fail[1] = 0; f[0] = 1; lst = 1; } int main() { scanf( %s , str + 1); n = strlen(str + 1); if (n & 1) { printf( 0 n ); return 0; } for (int i = (int)1; i <= (int)n / 2; i++) { s[i * 2 - 1] = str[i] - a ; s[i * 2] = str[n + 1 - i] - a ; } s[0] = -1; init(); for (int i = (int)1; i <= (int)n; i++) { addChar(s[i], i); for (int x = lst; x; x = anc[x]) { g[x] = f[i - (len[anc[x]] + diff[x])]; if (anc[x] != fail[x]) { g[x] = (g[x] + g[fail[x]]) % P; } if (i % 2 == 0) f[i] = (f[i] + g[x]) % P; } } printf( %d n , f[n]); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 9; const long long mod1 = 1000000; ostringstream convert; long long n, m, cur, dp[100][300]; long long res; long long nbb = 0, nss = 0, ncc = 0, wmin, wmax; long long nb, ns, nc, pb, ps, pc, mx = 0; string s, s2; string a[1000]; long long vis[10000] = {0}, wpers[10000]; vector<string> v, vnode; map<string, long long> mp; set<long long> st; stack<double> stk; long long dx[] = {0, 1, -1, 0}; long long dy[] = {1, 0, 0, -1}; int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long i, j = 1, k = 0, d, p, q, l, r, pos, idx = -1, nbx, sumf = 0, test; long long sum2 = 0, lg = 1, op; long long x, lastx = 0, val1 = 0; long long y = 1, z = 0; char c; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; } for (k = 0; k <= 100; k++) for (i = 1; i <= n; i++) { s = a[i]; j = 1; if (!vis[i]) for (j = 1; j <= n; j++) { s2 = a[j]; if (!vis[i] && !vis[j] && !strstr(s2.c_str(), s.c_str())) break; } if (j == n + 1) { v.push_back(s); vis[i] = 1; } } if (v.size() == n) { cout << YES n ; for (i = 0; i < v.size(); i++) cout << v[i] << endl; } else cout << NO ; }
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/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Include definition of the control signals
`include "control.h"
// Non-synthesizable behavioral RTL model for the instruction memory
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Data output read from the data memory
output [0:127] data_out;
// ===============================================================
// Input signals
// Data input stored into the data memory
input [0:127] data_in;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input [0:31] mem_ctrl_addr;
// Clock signal
input clk;
// Control signals for the data memory
input [0:1] dm_ctrl_sig;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:127] data_out; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [127:0] data_mem [255:0]; // Store the data here
// Store instruction address in the instruction memory
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",data_mem);
end
// A change in the instruction address activates this...
always @(posedge clk)
begin
/**
* Check the control signal and implement the appropriate
* function
*/
case(dm_ctrl_sig)
`memwld:
begin
// Read the data from the memory
data_out<=data_mem[mem_ctrl_addr];
end
`memwst:
begin
// Write the data to the memory
data_mem[mem_ctrl_addr]<=data_in;
$display("Value written to data mem",data_mem[mem_ctrl_addr],"#");
end
`memnop:
begin
data_out<=128'd0;
end
default:
begin
data_out<=128'd0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int l, r, x, y, k; scanf( %d%d%d%d%d , &x, &y, &l, &r, &k); int L = (int)ceil(1.0 * x / k), R = (int)floor(1.0 * y / k); if (R < L || R < l || r < L) puts( NO ); else puts( YES ); return 0; }
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/*
* Instruction decoder for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_decode (
input clk,
input rst,
input [7:0] opcode,
input [7:0] modrm,
input rep,
input block,
input exec_st,
input div_exc,
input ld_base,
input div,
input tfl,
output tflm,
output need_modrm,
output need_off,
output need_imm,
output off_size,
output imm_size,
input [2:0] sop_l,
input intr,
input ifl,
output iflm,
output reg inta,
output ext_int,
input nmir,
output reg nmia,
input wr_ss,
output iflss,
// to microcode
output [`MICRO_ADDR_WIDTH-1:0] seq_addr,
output [3:0] src,
output [3:0] dst,
output [3:0] base,
output [3:0] index,
output [1:0] seg,
output [2:0] f,
// from microcode
input end_seq,
input use_eintp
);
// Net declarations
wire [`MICRO_ADDR_WIDTH-1:0] base_addr;
reg [`MICRO_ADDR_WIDTH-1:0] seq;
reg dive;
reg tfle;
reg tfld;
reg ifld;
reg iflssd;
reg ext_irq;
reg ext_nmi;
reg old_ext_irq;
reg old_ext_nmi;
reg [4:0] div_cnt;
// Module instantiations
zet_opcode_deco opcode_deco (opcode, modrm, rep, sop_l, base_addr, need_modrm,
need_off, need_imm, off_size, imm_size, src, dst,
base, index, seg);
// Assignments
assign seq_addr = (tfle ? `INTT : (dive ? `INTD
: (ext_int ? (use_eintp ? `EINTP : `EINT) : base_addr))) + seq;
assign f = opcode[7] ? modrm[5:3] : opcode[5:3];
assign iflm = ifl & ifld;
assign tflm = tfl & tfld;
assign iflss = !wr_ss & iflssd;
// Behaviour
always @(posedge clk)
ifld <= rst ? 1'b0 : (exec_st ? ifld : ifl);
always @(posedge clk)
tfld <= rst ? 1'b0 : (exec_st ? tfld : tfl);
always @(posedge clk)
if (rst)
iflssd <= 1'b0;
else
begin
if (!exec_st)
iflssd <= 1'b1;
else if (wr_ss)
iflssd <= 1'b0;
end
// seq
always @(posedge clk)
seq <= rst ? `MICRO_ADDR_WIDTH'd0
: block ? seq
: end_seq ? `MICRO_ADDR_WIDTH'd0
: |div_cnt ? seq
: exec_st ? (seq + `MICRO_ADDR_WIDTH'd1) : `MICRO_ADDR_WIDTH'd0;
// div_cnt - divisor counter
always @(posedge clk)
div_cnt <= rst ? 5'd0
: ((div & exec_st) ? (div_cnt==5'd0 ? 5'd18 : div_cnt - 5'd1) : 5'd0);
// dive
always @(posedge clk)
if (rst) dive <= 1'b0;
else dive <= block ? dive
: (div_exc ? 1'b1 : (dive ? !end_seq : 1'b0));
// tfle
always @(posedge clk)
if (rst) tfle <= 1'b0;
else tfle <= block ? tfle
: ((((tflm & !tfle) & iflss) & exec_st & end_seq) ? 1'b1 : (tfle ? !end_seq : 1'b0));
// ext_irq
always @(posedge clk)
if (rst) ext_irq <= 1'b0;
else ext_irq <= block ? ext_irq
: ((!nmir & intr & iflm & iflss & exec_st & end_seq) ? 1'b1
: (ext_irq ? !end_seq : 1'b0));
// ext_nmi
always @(posedge clk)
if (rst) ext_nmi <= 1'b0;
else ext_nmi <= block ? ext_nmi
: ((nmir & iflss & exec_st & end_seq) ? 1'b1
: (ext_nmi ? !end_seq : 1'b0));
assign ext_int = ext_irq | ext_nmi;
// old_ext_int
always @(posedge clk) old_ext_irq <= rst ? 1'b0 : ext_irq;
// old_ext_int
always @(posedge clk) old_ext_nmi <= rst ? 1'b0 : ext_nmi;
// inta
always @(posedge clk)
inta <= rst ? 1'b0 : (!old_ext_irq & ext_irq);
// nmia
always @(posedge clk)
nmia <= rst ? 1'b0 : (!old_ext_nmi & ext_nmi);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`include "../../models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X ;
wire pwrgood1_out_x2;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
buf buf0 (X , pwrgood1_out_x2 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char a[53][53] = {5}; int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { char x; cin >> x; if (x == a || x == f || x == c || x == e ) a[i][j] = x; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { string c = ; c += a[i][j]; c += a[i][j + 1]; c += a[i + 1][j]; c += a[i + 1][j + 1]; sort(c.begin(), c.end()); if (c == acef ) ans += 1; } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_2_V
`define SKY130_FD_SC_LP__HA_2_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_PP_SYMBOL_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A one bit data synchronization module, where data is synchronized
// by passing through 2 registers of the destination clock
module SyncBit (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
assign dD_OUT = dSyncReg2 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY (sD_IN == 1'b1) ? 1'b1 : 1'b0 ;
end // if ( sEN )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
dSyncReg2 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // BitSync
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam and Mohammad
// Create Date: 20:16:03 10/24/2015
// Design Name: The top-level data unit of the design
// Module Name: MasterDataUnitI2C
// Summary: This holds all of the data that is read and written.
//////////////////////////////////////////////////////////////////////////////////
module MasterDataUnitI2C(BaudRate,ClockFrequency,SentData,BaudEnable,Clock,ReadOrWrite,Reset,Select,ShiftOrHold,StartStopAck,WriteLoad,ReceivedData,SCL,SDA);
input [19:0] BaudRate; // up to
input [29:0] ClockFrequency; // up to 1GHz
input [LENGTH-1:0] SentData;
input BaudEnable;
input Clock;
input ReadOrWrite;
input Reset;
input Select;
input ShiftOrHold;
input StartStopAck;
input WriteLoad;
output [LENGTH-1:0] ReceivedData;
output SCL;
inout SDA;
parameter LENGTH = 8;
assign SCL = ClockI2C;
wire ClockI2C;
BaudRateGeneratorI2C BaudUnit(BaudEnable,ClockI2C,Reset,Clock,BaudRate,ClockFrequency);
wire ShiftDataIn, ShiftDataOut;
ShiftRegisterI2C2015fall ShiftUnit(SentData,Clock,Reset,ShiftDataIn,ShiftOrHold,WriteLoad,ReceivedData,ShiftDataOut,ClockI2C);
SDAmodule SDAUnit(SDA,ReadOrWrite,Select,StartStopAck,ShiftDataIn,ShiftDataOut);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_ecc_dec.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_ecc_dec
// Description: Decodes the result from the ecc checking block
// into a 64 bit value that is used to correct single bit errors.
// Correction is performed by e ^ data.
*/
module sparc_exu_ecc_dec (/*AUTOARG*/
// Outputs
e,
// Inputs
q
) ;
input [6:0] q;
output [63:0] e;
assign e[0] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[1] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[2] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[3] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[4] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[5] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[6] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[7] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[8] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[9] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[10] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[11] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[12] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[13] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[14] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[15] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[16] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[17] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[18] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[19] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[20] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[21] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[22] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[23] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[24] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[25] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[26] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[27] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[28] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[29] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[30] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[31] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[32] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[33] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[34] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[35] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[36] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[37] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[38] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[39] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[40] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[41] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[42] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[43] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[44] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[45] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[46] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[47] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[48] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[49] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[50] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[51] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[52] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[53] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[54] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[55] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[56] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[57] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[58] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[59] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[60] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[61] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[62] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[63] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
endmodule // sparc_exu_ecc_dec
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; reverse(t.begin(), t.end()); if (s == t) cout << YES ; else cout << NO ; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:36:35 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xlconcat_0_0_sim_netlist.v
// Design : design_1_xlconcat_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_xlconcat_0_0,xlconcat,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconcat,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(In0,
In1,
dout);
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
wire [0:0]In0;
wire [0:0]In1;
assign dout[1] = In1;
assign dout[0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
////////////////////////////////////////////////////////////////////////////////
// Design Name: aurora_64b66b_0_gt_common_wrapper
//
// Module aurora_64b66b_0_gt_common_wrapper
`timescale 1ns / 1ps
(* core_generation_info = "aurora_64b66b_0,aurora_64b66b_v11_1_3,{c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=3.125,c_gt_type=gtx,c_qpll=false,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125.0,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=true,c_user_k=false,flow_mode=UFC,interface_mode=Streaming,dataflow_config=Duplex}" *)
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_0_gt_common_wrapper
(
output gt_qpllclk_quad1_out,
output gt_qpllrefclk_quad1_out,
input GT0_GTREFCLK0_COMMON_IN,
//----------------------- Common Block - QPLL Ports ------------------------
output GT0_QPLLLOCK_OUT,
input GT0_QPLLLOCKDETCLK_IN,
output GT0_QPLLREFCLKLOST_OUT,
//----------------------- Common Block - DRP Ports ------------------------
input [7:0] qpll_drpaddr_in,
input [15:0] qpll_drpdi_in,
input qpll_drpclk_in,
input qpll_drpen_in,
input qpll_drpwe_in,
output [15:0] qpll_drpdo_out,
output qpll_drprdy_out
);
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "TRUE"; // Set to "TRUE" to speed up sim reset
//***************************** Wire Declarations *****************************
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
//_________________________________________________________________________
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("4.0"),
//----------------COMMON BLOCK---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (10'b0000100000),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (1'b1),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_i
(
//--------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (qpll_drpaddr_in),
.DRPCLK (qpll_drpclk_in),
.DRPDI (qpll_drpdi_in),
.DRPDO (qpll_drpdo_out),
.DRPEN (qpll_drpen_in),
.DRPRDY (qpll_drprdy_out),
.DRPWE (qpll_drpwe_in),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt_qpllclk_quad1_out),
.QPLLOUTREFCLK (gt_qpllrefclk_quad1_out),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (tied_to_ground_i),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.RCALENB (tied_to_vcc_i),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b11111),
.PMARSVD (8'b00000000),
.QPLLDMONITOR ()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e6; const long long MOD = 1e9 + 7; const long long N = 1e6 + 7; const long long N_N = 1e3; const int INF = 1e9 + 228; const long double eps = 1e-12; long long n, a[N], ans, l, ans1; int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 2; i <= n; ++i) { if (a[i - 1] > a[i]) { ans++; ans1 = i; } } if (ans > 1) { cout << -1; } if (ans == 0) { cout << 0; } if (ans == 1) { if (a[1] >= a[ans1] && a[1] >= a[n]) { cout << n - ans1 + 1; } else cout << -1; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dist(int x, int y) { if (y > x) return (y - x); else return (12 - x + y); } int main() { int i, j, q, r, t; string a, b, c; cin >> a >> b >> c; map<string, int> m; m[ C ] = 1; m[ C# ] = 2; m[ D ] = 3; m[ D# ] = 4; m[ E ] = 5; m[ F ] = 6; m[ F# ] = 7; m[ G ] = 8; m[ G# ] = 9; m[ A ] = 10; m[ B ] = 11; m[ H ] = 12; int x, y, z; x = m[a]; y = m[b]; z = m[c]; if (dist(x, y) == 3 && dist(y, z) == 4) cout << minor ; else if (dist(x, y) == 4 && dist(y, z) == 3) cout << major ; else if (dist(x, z) == 3 && dist(z, y) == 4) cout << minor ; else if (dist(x, z) == 4 && dist(z, y) == 3) cout << major ; else if (dist(y, x) == 3 && dist(x, z) == 4) cout << minor ; else if (dist(y, x) == 4 && dist(x, z) == 3) cout << major ; else if (dist(y, z) == 3 && dist(z, x) == 4) cout << minor ; else if (dist(y, z) == 4 && dist(z, x) == 3) cout << major ; else if (dist(z, x) == 3 && dist(x, y) == 4) cout << minor ; else if (dist(z, x) == 4 && dist(x, y) == 3) cout << major ; else if (dist(z, y) == 3 && dist(y, x) == 4) cout << minor ; else if (dist(z, y) == 4 && dist(y, x) == 3) cout << major ; else cout << strange ; return 0; }
|
#include <bits/stdc++.h> using namespace std; std::vector<long long> digit(long long num) { string str, s; std::vector<long long> v; str = to_string(num); for (int i = 0; i < str.size(); ++i) { s = str[i]; v.push_back(stoi(s)); } return v; } void solve() { long long num, best; cin >> num; std::vector<long long> arr(num + 11); std::vector<long long> d; arr[0] = 0; for (int i = 1; i < 10; ++i) { arr[i] = 1; } for (int i = 10; i <= num; ++i) { best = 2000000000000000000; d = digit(i); for (auto y : d) { if (y != 0) { best = min(best, arr[i - y] + 1); } } arr[i] = best; } cout << arr[num] << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); int tt = 1; while (tt--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, a, b, c = 0; cin >> n >> x; while (n--) { cin >> a >> b; if (x == a || x == b || x == 7 - a || x == 7 - b) c++; x = 7 - x; } if (c > 0) cout << NO << endl; else cout << YES << endl; return 0; }
|
/*
Microcode Execute
Microcode Op
31:24, Opcode
23, Last Uop (Reset to Start)
*/
`include "ArithAlu.v"
`include "MemAlu.v"
`include "GpReg.v"
`include "MemTile.v"
`include "DecOp.v"
/*
module ExUop(
clk,
istrWord,
uopWord,
uopCmd,
idRegD,
idRegS,
idRegT,
idImm
);
*/
module ExUop(clk);
input clk; //clock
/*
input[31:0] istrWord; //source instruction word
input[31:0] uopWord; //uop word
input[7:0] uopCmd;
input[6:0] idRegD; //Source Opcode D (or N)
input[6:0] idRegS; //Source Opcode S (or M)
input[6:0] idRegT; //Source Opcode T
input[31:0] idImm; //Source Immediate
*/
reg[31:0] istrWord; //source instruction word
reg[31:0] uopWord; //uop word
reg[7:0] uopCmd;
reg[6:0] idRegD; //Source Opcode D (or N)
reg[6:0] idRegS; //Source Opcode S (or M)
reg[6:0] idRegT; //Source Opcode T
reg[31:0] idImm; //Source Immediate
reg[11:0] idUopPc; //Instruction Uop PC
parameter[7:0] UOP_BRINST = 8'h00; //Branch Decoded Instruction
parameter[7:0] UOP_ADDI = 8'h01;
parameter[7:0] UOP_SUBI = 8'h02;
parameter[7:0] UOP_MULI = 8'h03;
parameter[7:0] UOP_ANDI = 8'h04;
parameter[7:0] UOP_ORI = 8'h05;
parameter[7:0] UOP_XORI = 8'h06;
parameter[7:0] UOP_SHLI = 8'h07;
parameter[7:0] UOP_SHRI = 8'h08;
parameter[7:0] UOP_SARI = 8'h09;
parameter[7:0] UOP_ADDCI = 8'h0A;
parameter[7:0] UOP_CMPEQI = 8'h0B;
parameter[7:0] UOP_CMPGTI = 8'h0C;
parameter[7:0] UOP_CMPGEI = 8'h0D;
parameter[7:0] UOP_CMPHSI = 8'h0E;
parameter[7:0] UOP_CMPHII = 8'h0F;
parameter[7:0] UOP_GETINST = 8'h10; //Fetch Instruction
parameter[7:0] UOP_ADDQ = 8'h11;
parameter[7:0] UOP_SUBQ = 8'h12;
parameter[7:0] UOP_MULQ = 8'h13;
parameter[7:0] UOP_ANDQ = 8'h14;
parameter[7:0] UOP_ORQ = 8'h15;
parameter[7:0] UOP_XORQ = 8'h16;
parameter[7:0] UOP_SHLQ = 8'h17;
parameter[7:0] UOP_SHRQ = 8'h18;
parameter[7:0] UOP_SARQ = 8'h19;
parameter[7:0] UOP_ADDCQ = 8'h1A;
parameter[7:0] UOP_CMPEQQ = 8'h1B;
parameter[7:0] UOP_CMPGTQ = 8'h1C;
parameter[7:0] UOP_CMPGEQ = 8'h1D;
parameter[7:0] UOP_CMPHSQ = 8'h1E;
parameter[7:0] UOP_CMPHIQ = 8'h1F;
parameter[7:0] UOP_LEAB = 8'h21;
parameter[7:0] UOP_LEAW = 8'h22;
parameter[7:0] UOP_LEAI = 8'h23;
parameter[7:0] UOP_LEAQ = 8'h24;
parameter[7:0] UOP_LEAV = 8'h25;
parameter[7:0] UOP_MOVLDB = 8'h31;
parameter[7:0] UOP_MOVLDW = 8'h32;
parameter[7:0] UOP_MOVLDI = 8'h33;
parameter[7:0] UOP_MOVLDQ = 8'h34;
parameter[7:0] UOP_MOVLDUB = 8'h36;
parameter[7:0] UOP_MOVLDUW = 8'h37;
parameter[7:0] UOP_MOVSTB = 8'h39;
parameter[7:0] UOP_MOVSTW = 8'h3A;
parameter[7:0] UOP_MOVSTI = 8'h3B;
parameter[7:0] UOP_MOVSTQ = 8'h3C;
reg[63:0] iDataD;
reg[63:0] iDataS;
reg[63:0] iDataT;
reg[63:0] tData2D;
reg[6:0] tIdReg2D;
reg tIsWr2D;
reg tIsQw2D;
reg[63:0] oData2D;
reg[6:0] oIdReg2D;
reg oIsWr2D;
reg oIsQw2D;
// ArithAlu alu1;
// MemAlu agu1;
GpReg regs(clk,
oIsWr2D, oIsWr2D, oIdReg2D, oData2D,
idRegD, iDataD, idRegS, iDataS, idRegT, iDataT);
reg[63:0] tDataAluD;
reg[31:0] regSr;
reg[31:0] tRegSr;
reg[63:0] regPc;
reg[63:0] regNextPc;
reg[3:0] aluCmd;
reg[3:0] tAluSr;
ArithAlu alu1(clk, aluCmd,
iDataS, iDataT, tDataAluD, regSr[3:0], tAluSr);
reg[63:0] tDataAguD;
reg[2:0] aguCmd;
MemAlu agu1(clk, aguCmd,
iDataS, iDataT[31:0], idImm, tDataAguD);
reg memRd;
reg memWr;
reg[2:0] memCmd;
reg[47:0] memAddr;
reg[63:0] memRdValue;
reg[63:0] memWrValue;
MemTile mem1(clk, memRd, memWr, memCmd,
memAddr, memRdValue, memWrValue);
reg[1:0] idStepPc;
DecOp dec1(clk, istrWord,
idRegD, idRegS, idRegT, idImm, idUopPc, idStepPc);
reg[63:0] tRegStepPc;
reg[11:0] uopPc;
reg[11:0] uopNextPc;
reg[31:0] uopPgm[4096];
always @ (clk)
begin
uopWord=uopPgm[uopPc];
if(uopWord[23])
uopNextPc=12'h000;
else
uopNextPc=uopPc+1;
uopCmd=uopWord[31:24];
regPc[31: 0]=regs.regs[regs.REG_PC_LO];
regPc[63:32]=regs.regs[regs.REG_PC_HI];
regNextPc=regPc;
regSr=regs.regs[regs.REG_SR];
case(uopCmd[7:4])
4'h0:
begin
if(uopCmd[3:0]==4'h0)
begin
uopNextPc=idUopPc;
tRegStepPc[63:3]=61'h0;
tRegStepPc[2:1]=idStepPc[1:0];
tRegStepPc[0]=1'b0;
regNextPc=regPc+tRegStepPc;
end
else
begin
aluCmd=uopCmd[3:0];
tData2D=tDataAluD;
tIsWr2D=aluCmd<alu1.UOP_CMPEQ;
tIsQw2D=1'b0;
if(aluCmd<alu1.UOP_ADDC)
tRegSr=regSr;
else
begin
tRegSr[31:1]=regSr[31:1];
tRegSr[0]=tAluSr[0];
end
end
end
4'h1:
begin
if(uopCmd[3:0]==4'h0)
begin
memAddr[47:0]=regPc[47:0];
memCmd=mem1.MD_DWORD;
memRd=1'b1;
memWr=1'b0;
istrWord=memRdValue[31:0];
tData2D=tDataAguD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
tRegSr=regSr;
end
else
begin
aluCmd=uopCmd[3:0];
tData2D=tDataAluD;
tIsWr2D=aluCmd<alu1.UOP_CMPEQ;
tIsQw2D=1'b1;
if(aluCmd<alu1.UOP_ADDC)
tRegSr=regSr;
else
begin
tRegSr[31:1]=regSr[31:1];
tRegSr[0]=tAluSr[1];
end
end
end
4'h2:
begin
aguCmd=uopCmd[2:0];
tData2D=tDataAguD;
tIsWr2D=1'b1;
tIsQw2D=1'b1;
tRegSr=regSr;
end
4'h3:
begin
aguCmd=uopCmd[2:0];
memCmd=uopCmd[2:0];
memAddr=tDataAguD[47:0];
tIsWr2D=uopCmd[3];
tIsQw2D=uopCmd[2];
tRegSr=regSr;
memWrValue=iDataD;
tData2D=memRdValue;
if(uopCmd[3])
begin
memRd=1'b0;
memWr=1'b1;
end
else
begin
memRd=1'b1;
memWr=1'b0;
end
end
default: begin
tData2D=iDataD;
tIsWr2D=1'b0;
tIsQw2D=1'b0;
tRegSr=regSr;
end
endcase
end
always @ (posedge clk) begin
oData2D <= tData2D;
oIsWr2D <= tIsWr2D;
oIsQw2D <= tIsQw2D;
// regSr <= tRegSr;
regs.regs[regs.REG_SR] <= tRegSr;
uopPc <= uopNextPc;
regs.regs[regs.REG_PC_LO] <= regNextPc[31: 0];
regs.regs[regs.REG_PC_HI] <= regNextPc[63:32];
end
endmodule
|
//-----------------------------------------------------------------------------
// Title : GT Common wrapper
// Project : 10GBASE-R
//-----------------------------------------------------------------------------
// File : ten_gig_eth_pcs_pma_ip_GT_Common_wrapper.v
//-----------------------------------------------------------------------------
// Description: This file contains the
// 10GBASE-R Transceiver GT Common block.
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
module ten_gig_eth_pcs_pma_ip_GT_Common_wrapper # (
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware
(
input refclk,
input qplllockdetclk,
input qpllreset,
output qplllock,
output qpllrefclklost,
output qplloutclk,
output qplloutrefclk
);
//***************************** Parameter Declarations ************************
parameter QPLL_FBDIV_TOP = 66;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
wire GT0_GTREFCLK0_COMMON_IN;
wire GT0_QPLLLOCKDETCLK_IN;
wire GT0_QPLLRESET_IN;
wire GT0_QPLLLOCK_OUT;
wire GT0_QPLLREFCLKLOST_OUT;
wire gt0_qplloutclk_i;
wire gt0_qplloutrefclk_i;
assign GT0_GTREFCLK0_COMMON_IN = refclk;
assign GT0_QPLLLOCKDETCLK_IN = qplllockdetclk;
assign GT0_QPLLRESET_IN = qpllreset;
assign qplllock = GT0_QPLLLOCK_OUT;
assign qpllrefclklost = GT0_QPLLREFCLKLOST_OUT;
assign qplloutclk = gt0_qplloutclk_i;
assign qplloutrefclk = gt0_qplloutrefclk_i;
//_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTHE2_COMMON____________________________________
GTHE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("2.0"),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h0480181),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h05E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1),
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000),
.QPLL_RP_COMP (1'b0),
.QPLL_VTRL_RESET (2'b00),
.RCAL_CFG (2'b00)
)
gthe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.BGRCALOVRDENB (tied_to_vcc_i),
.PMARSVDOUT (),
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt0_qplloutclk_i),
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_ground_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (GT0_QPLLRESET_IN),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1002, M = 10002; pair<int, long long> dp[N][M]; map<long long, int> di; bool vis[N][M]; int nxt[N][M]; long long a[N], b[N], k; int T[M][N]; int n; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { scanf( %d %lld , &n, &k); for (int i = 0; i < n; ++i) { scanf( %lld , b + i); a[i] = gcd(b[i], k); } if (k == 1) return printf( %d n%ld n , 1, min_element(b, b + n) - b + 1), 0; vector<long long> divisor; for (long long i = 1; i * i <= k; ++i) if (k % i == 0) { divisor.push_back(i); divisor.push_back(k / i); } sort(divisor.begin(), divisor.end()); divisor.resize(unique(divisor.begin(), divisor.end()) - divisor.begin()); int m = divisor.size(); for (int i = 0; i < m; ++i) di[divisor[i]] = i; for (int i = 0; i < m; ++i) for (int j = 0; j < n; ++j) T[i][j] = di[divisor[i] / gcd(divisor[i], a[j])]; nxt[n][0] = -1; dp[n][0] = {0, 0}; for (int i = 1; i < m; ++i) dp[n][i] = {n + 1, 0}; for (int i = 0; i < m; ++i) for (int j = n - 1; j >= 0; --j) { pair<int, long long> ans1 = dp[j + 1][i]; pair<int, long long> ans2 = dp[j + 1][T[i][j]]; ans2.first += 1; ans2.second += b[j]; if (ans1 <= ans2) { nxt[j][i] = nxt[j + 1][i]; dp[j][i] = ans1; } else { nxt[j][i] = j; dp[j][i] = ans2; } } pair<int, long long> ans = dp[0][m - 1]; if (ans.first > n) return puts( -1 ), 0; printf( %d n , ans.first); int pos = 0; int nx = m - 1; while (pos != -1) { if (nxt[pos][nx] != pos) pos = nxt[pos][nx]; else { nx = T[nx][pos]; printf( %d , pos + 1); pos += 1; } } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 55; int n, k, dp[N][N]; long long a[N], sum[N], dq; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i]; for (int i = 60; i >= 0; i--) { dq |= (long long)1 << i; dp[0][0] = 1; for (int j = 1; j <= n; j++) for (int l = 1; l <= k; l++) { dp[j][l] = 0; for (int o = j - 1; o >= 0; o--) if (((sum[j] - sum[o]) & dq) == dq) dp[j][l] |= dp[o][l - 1]; } if (!dp[n][k]) dq ^= (long long)1 << i; } printf( %lld , dq); }
|
#include <bits/stdc++.h> const int MAXINT = 2147483640; const long long MAXLL = 9223372036854775800LL; const long long MAXN = 1123456; const long long MOD = 1123456769; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); srand(time(0)); vector<int> v; int n, m, i, h; char c; cin >> n; for (i = 1; i <= n; i++) { cin >> h >> c >> m; v.push_back(h * 60 + m); } sort(v.begin(), v.end()); v.push_back(24 * 60 + v[0]); int mx = 0; for (i = 1; i < v.size(); i++) { mx = max(mx, v[i] - v[i - 1] - 1); } h = mx / 60; m = mx % 60; if (h < 10) cout << 0; cout << h << : ; if (m < 10) cout << 0; cout << m << n ; return 0; }
|
#include <bits/stdc++.h> int main() { int n, k, i, j; int hols, arr[1000]; int temp, loop, flag = 0; scanf( %d%d , &n, &k); scanf( %d , &hols); for (i = 0; i <= n; i++) { arr[i] = 0; } for (i = 0; i < hols; i++) { scanf( %d , &temp); arr[temp] = 2; } for (i = 0; i <= n;) { for (j = i; j < i + k; j++) { if (arr[j] == 2) { flag = 1; loop = j; } } if (flag == 1) { flag = 0; i = loop; } else { i = i + k; } arr[i] = 1; } int min = 0; for (i = 1; i <= n; i++) { if (arr[i] == 1 || arr[i] == 2) min++; } printf( %d , min); return 0; }
|
`timescale 1ns / 1ps
// synopsys template
module MUX
(
IN0,
IN1,
SEL,
F
);
input IN0, IN1, SEL;
output F;
assign F = (~SEL&IN0)|(SEL&IN1);
endmodule
module HADDER
(
IN0,
IN1,
SUM,
COUT
);
input IN0, IN1;
output SUM, COUT;
assign SUM = IN0^IN1;
assign COUT = IN0&IN1;
endmodule
module FADDER
(
IN0,
IN1,
CIN,
COUT,
SUM
);
input IN0, IN1, CIN;
output COUT, SUM;
assign SUM = IN0^IN1^CIN;
assign COUT = ((CIN&IN0)|(CIN&IN1)|(IN0&IN1));
endmodule
module AND
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = A&B;
endmodule
module ANDN
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = A&~B;
endmodule
module NAND
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A&B);
endmodule
module NANDN
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A&~B);
endmodule
module OR
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = A|B;
endmodule
module ORN
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = A|~B;
endmodule
module NOR
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A|B);
endmodule
module NORN
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A|~B);
endmodule
module XOR
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = A^B;
endmodule
module XNOR
(
A,
B,
Z
);
input A, B;
output Z;
assign Z = ~(A^B);
endmodule
module IV
(
A,
Z
);
input A;
output Z;
assign Z = ~A;
endmodule
module DFF
(
CLK,
RST,
D,
I,
Q
);
input CLK, RST, D, I;
output Q;
reg Q;
always @(posedge CLK or posedge RST) begin
if (RST) begin
Q <= I;
end else begin
Q <= D;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; constexpr int MAXN = 1003; constexpr int MAXC = 10004; int n; ll w, b, x; int c[MAXN]; ll cost[MAXN]; ll dp[MAXN][MAXC]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> w >> b >> x; for (int i = 0; i < n; ++i) cin >> c[i]; for (int i = 0; i < n; ++i) cin >> cost[i]; memset(dp, -1, sizeof(dp)); dp[0][0] = w; for (int i = 0; i < n; ++i) { for (int j = 0; j < MAXC and dp[i][j] > -1; ++j) { for (ll k = 0; k <= c[i] and dp[i][j] - cost[i] * k >= 0; ++k) { dp[i + 1][j + k] = max( dp[i + 1][j + k], min(w + (j + k) * b, dp[i][j] + x - cost[i] * k)); } } } int ans = 0; for (int j = 0; j < MAXC; ++j) { if (dp[n][j] != -1) ans = max(ans, j); } cout << ans << n ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_multiplier_1_1 -prefix
// affine_block_ieee754_fp_multiplier_1_1_ affine_block_ieee754_fp_multiplier_0_0_stub.v
// Design : affine_block_ieee754_fp_multiplier_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_multiplier,Vivado 2016.4" *)
module affine_block_ieee754_fp_multiplier_1_1(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int powmod(long long int a, int b, int n) { long long int rm = 1; while (b) { if (b % 2) { rm = (rm * a) % n; } a = (a * a) % n; b /= 2; } return rm; } int main() { int n; long long int a[110]; cin >> n; for (int i = (int)1; i <= (int)n; i++) cin >> a[i]; long long int cost = 0; for (long long int i = 1; i <= n; ++i) { cost = cost + (a[i] - 1) * i + 1; } cout << cost << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, t; string s; int puc(int k, int t) { vector<int> v(n + 1, 0); v[n - 1] = (s[n - 1] == H ); for (int i = n - 2; i >= 0; --i) v[i] = v[i + 1] + (s[i] == H ); int nh = 0, ns = 0; for (int i = 0; i < int(n); ++i) { if (s[i] == H ) ++nh; else if (s[i] == S ) ++ns; } if (k + ns < nh) return 0; int zk = k; int ret = 0; int qui = -1, q = 0; for (int i = 0; i < n; ++i) { if (s[i] == S ) { ++k; --ns; } else if (s[i] == H ) { --nh; if (k > 0) --k; else if (qui == -1) { qui = i; q = 1; } else ++q; } if (nh == 0 and k >= q) { if (qui == -1 and ret < t) return true; if (ret + (i - qui) < t) return true; break; } ++ret; } k = zk; int ult = -1; int r = 0; int ans = 0; for (int i = 0; i < int(n); ++i) { if (s[i] == S ) ++k; if (k >= r and ult != -1) { ans += i - ult; if (v[i] > 0) ans += i - ult; k -= r; ult = -1; r = 0; } if (s[i] == H ) { if (k > 0) --k; else if (ult == -1) { ult = i; r = 1; } else ++r; } if (ult == -1 and v[i + 1] == 0) break; ++ans; } return (ult == -1 and ans < t); } int main() { cin >> n >> t; cin >> s; int lo = 0, hi = n, m; while (hi - lo > 5) { int m = (lo + hi) / 2; if (puc(m, t)) hi = m; else lo = m; } bool trobat = 0; if (puc(0, t)) { cout << 0 << endl; trobat = true; } for (int k = lo; !trobat and k <= hi; ++k) { if (puc(k, t)) { cout << k << endl; trobat = true; } } if (!trobat) cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const double PI = 3.141592653589793; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } struct Pt { double x, y; Pt(double a = 0, double b = 0) : x(a), y(b) {} bool operator==(const Pt& p) const { return p.x == x && p.y == y; } bool operator<(const Pt& p) const { return x == p.x ? y > p.y : x < p.x; } Pt operator-(const Pt& p) const { return {x - p.x, y - p.y}; } Pt operator+(const Pt& p) const { return {x + p.x, y + p.y}; } Pt operator/(const double c) const { return {x / c, y / c}; } Pt operator*(const double c) const { return {x * c, y * c}; } Pt vetor(const Pt& o) const { return o - (*this); } double dot(const Pt& b) const { return (x * b.x) + (y * b.y); } double sq() const { return (x * x) + (y * y); } double dist(const Pt& b) { return sqrt((b - *this).sq()); } double cross(const Pt& b) const { return (x * b.y) - (y * b.x); } double cross(const Pt& a, const Pt& b) const { return (a - *this).cross(b - *this); } double angle(Pt& a, Pt& b) const { a = vetor(a), b = vetor(b); return acos(1.0 * a.dot(b) / sqrt(1.0 * a.dot(a) * b.dot(b))); } } pts[101000]; Pt obj; Pt perp(Pt p) { return {-p.y, p.x}; } ostream& operator<<(ostream& os, Pt p) { return os << ( << p.x << , << p.y << ) ; } template <typename F> int sgn(F x) { return (F(0) < x) - (x < F(0)); } struct Line { double A, B, C; Line() {} Line(const Pt& de, const Pt& pa) { A = de.y - pa.y; B = pa.x - de.x; C = -A * de.x - B * de.y; } }; bool mORe(double a, double b) { return a <= b || fabs(a - b) <= EPS; } struct Seg { Pt A, B; Seg() {} Seg(Pt a, Pt b) : A(a), B(b) { if (B < A) swap(A, B); } bool inDouble(const Pt& Pt) { return mORe(min(A.x, B.x), Pt.x) && mORe(Pt.x, max(A.x, B.x)) && mORe(min(A.y, B.y), Pt.y) && mORe(Pt.y, max(A.y, B.y)); } bool inter(Seg& o, Pt& res) { Line l1 = Line(A, B), l2 = Line(o.A, o.B); double dx = Pt(l1.C, l1.B).cross(Pt(l2.C, l2.B)); double dy = Pt(l1.A, l1.C).cross(Pt(l2.A, l2.C)); double d = Pt(l1.A, l1.B).cross(Pt(l2.A, l2.B)); if (d == 0) return false; res = Pt(-dx / d, -dy / d); if (!inDouble(res) || !o.inDouble(res)) return false; return true; } }; int n, p, q; void solve() { vector<Pt> chain; int sz = 0; for (int i = 0; i < n; i++) { while (sz >= 2 && chain[sz - 2].cross(chain[sz - 1], pts[i]) >= 0) chain.pop_back(), sz--; chain.emplace_back(pts[i]); sz++; } vector<Seg> linhas; for (int i = 1; i < chain.size(); i++) { linhas.emplace_back(chain[i - 1], chain[i]); } Seg teste = {Pt(0, 0), obj * 1000002.0}; for (Seg linha : linhas) { Pt res; if (linha.inter(teste, res)) { printf( %.12f n , max(obj.x / res.x, obj.y / res.y)); return; } } } int main() { scanf( %d%d%d , &n, &p, &q); obj = {(double)p, (double)q}; int x, y; int maxx = 0, maxy = 0; for (int i = 0; i < n; i++) { scanf( %d%d , &x, &y); pts[i] = {(double)x, (double)y}; maxx = max(maxx, x); maxy = max(maxy, y); } pts[n] = {0.0, (double)maxy}; pts[n + 1] = {(double)maxx, 0.0}; n += 2; sort(pts, pts + n); solve(); return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ?
(address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:38 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_processing_system7_0_0/zybo_zynq_design_processing_system7_0_0_stub.v
// Design : zybo_zynq_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module zybo_zynq_design_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int b) { if (b == 0) return 1; if (b == 1) return a; long long int r = power(a, b / 2) % 1000000007; if (b % 2 == 0) return (r * r) % 1000000007; else return (((r * r) % 1000000007) * a) % 1000000007; } int prime[1000009]; int sumprime[1000009]; void sieve(int n) { prime[0] = prime[1] = 1; for (int i = 2; i <= sqrt(n); i++) { if (!prime[i]) { for (int j = 2 * i; j <= n; j = j + i) { prime[j]++; } } } for (int i = 1; i <= n; i++) { if (!prime[i]) { sumprime[i] = sumprime[i - 1] + 1; } else { sumprime[i] = sumprime[i - 1]; } } } bool comp(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return (a.second < b.second); } const int N = 5 * 1e5 + 9; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; int n = s.length(); int flag = 0; map<char, int> mp; mp[ A ]++; mp[ H ]++; mp[ I ]++; mp[ M ]++; mp[ O ]++; mp[ o ]++; mp[ T ]++; mp[ U ]++; mp[ V ]++; mp[ v ]++; mp[ W ]++; mp[ w ]++; mp[ X ]++; mp[ x ]++; mp[ Y ]++; mp[ b ]++; mp[ d ]++; mp[ p ]++; mp[ q ]++; if (n % 2) { char c = s[n / 2]; if (c == p || c == q || c == d || c == b ) { flag++; } } for (int i = 0; i < n; i++) { if (mp.find(s[i]) == mp.end()) { flag++; break; } if (s[i] == b ) { if (s[n - i - 1] != d ) { flag++; break; } continue; } if (s[i] == d ) { if (s[n - i - 1] != b ) { flag++; break; } continue; } if (s[i] == p ) { if (s[n - i - 1] != q ) { flag++; break; } continue; } if (s[i] == q ) { if (s[n - i - 1] != p ) { flag++; break; } continue; } if (s[i] != s[n - i - 1]) { flag++; break; } } if (flag) { cout << NIE n ; return 0; } cout << TAK n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long hit(long long n) { return ((1 + n) * n) / 2; } int main() { long long m, n; scanf( %lld%lld , &n, &m); long long hasilmin, hasilmax; hasilmin = hit(n / m) * (n % m) + hit(n / m - 1) * (m - n % m); hasilmax = hit(n - m); printf( %lld %lld n , hasilmin, hasilmax); return 0; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Sun Oct 4 22:06:59 2015
// Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/cmbarker/Private/Atari7800/lab3sound/lab3sound.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module blk_mem_gen_0(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[16:0],dina[15:0],clkb,enb,addrb[16:0],doutb[15:0]" */;
input clka;
input ena;
input [0:0]wea;
input [16:0]addra;
input [15:0]dina;
input clkb;
input enb;
input [16:0]addrb;
output [15:0]doutb;
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_8_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_6_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const long double E = 1e-7; const int MOD = 1e9 + 7; const long long MAX = 1e6 + 1; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, k; cin >> n >> k; int ar[n]; for (int i = 0; i < n; i++) cin >> ar[i]; int ans = INT_MIN; int a[n], b[n]; for (int i = 0; i < n; i++) for (int j = i; j < n; j++) { int A = j - i + 1; int B = n - A; copy(ar + i, ar + j + 1, a); copy(ar, ar + i, b); copy(ar + j + 1, ar + n, b + i); sort(a, a + A); sort(b, b + B); for (int l = 0, r = B - 1, q = k; l < A && r >= 0 && a[l] < b[r] && q; l++, r--, --q) swap(a[l], b[r]); int sum = 0; for (int i = 0; i < A; i++) sum += a[i]; ans = max(ans, sum); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> tedad; int main() { long long a; string s; cin >> a; cin >> s; long long ans = 0; for (int i = 0; i < s.size(); i++) { for (int j = i, sum = 0; j < s.size(); j++) { sum += s[j] - 48; tedad[sum]++; } } if (!a) { ans += tedad[0] * s.size() * (s.size() + 1); ans -= pow(tedad[0], 2); cout << ans; return 0; } for (int i = 1; i * i < a + 1; i++) { if (a % i == 0) { ans += tedad[i] * tedad[a / i]; if (i != a / i) ans += tedad[i] * tedad[a / i]; } } cout << ans; return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video in stream between color spaces on the DE *
* boards. *
* *
******************************************************************************/
module Video_System_Color_Space_Converter (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 23;
parameter OW = 23;
parameter EIW = 1;
parameter EOW = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EIW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [OW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EOW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [OW: 0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [EOW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IW: 0] data;
reg startofpacket;
reg endofpacket;
reg [EIW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 2'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'b0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data = ~stream_out_valid |
(stream_out_ready & stream_out_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_YCrCb_to_RGB_converter YCrCb_to_RGB (
// Inputs
.clk (clk),
.clk_en (transfer_data),
.reset (reset),
.Y (data[ 7: 0]),
.Cr (data[23:16]),
.Cb (data[15: 8]),
.stream_in_startofpacket (startofpacket),
.stream_in_endofpacket (endofpacket),
.stream_in_empty (empty),
.stream_in_valid (valid),
// Bidirectionals
// Outputs
.R (converted_data[23:16]),
.G (converted_data[15: 8]),
.B (converted_data[ 7: 0]),
.stream_out_startofpacket (converted_startofpacket),
.stream_out_endofpacket (converted_endofpacket),
.stream_out_empty (converted_empty),
.stream_out_valid (converted_valid)
);
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This is a check of the implementation of division and multiplication
* within more complex expressions.
*/
module test;
task mod;
input [31:0] a;
input [15:0] b;
output [31:0] out;
begin
out = a-(a/b)*b;
end
endtask
reg [31:0] result,c, nl;
initial begin
c = 13; nl = 3;
mod(c, nl, result);
$display("13 %% 3 = %d", result);
if (result !== 32'h00_00_00_01) begin
$display("FAILED -- result is %b", result);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> int main() { int n; while (scanf( %d , &n) != EOF) { if (n % 2 == 1) { printf( -1 n ); continue; } printf( 2 1 ); for (int i = 3; i < n; i = i + 2) printf( %d %d , i + 1, i); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string to_string(string s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } class segtree { public: struct node { long long mn = 0; long long add = 0; void apply(int l, int r, long long v) { mn += v; add += v; } }; node unite(const node &a, const node &b) const { node res; res.mn = min(a.mn, b.mn); return res; } inline void push(int x, int l, int r) { int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); if (tree[x].add != 0) { tree[x + 1].apply(l, y, tree[x].add); tree[z].apply(y + 1, r, tree[x].add); tree[x].add = 0; } } inline void pull(int x, int z) { tree[x] = unite(tree[x + 1], tree[z]); } int n; vector<node> tree; void build(int x, int l, int r) { if (l == r) { return; } int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); build(x + 1, l, y); build(z, y + 1, r); pull(x, z); } template <typename M> void build(int x, int l, int r, const vector<M> &v) { if (l == r) { tree[x].apply(l, r, v[l]); return; } int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); build(x + 1, l, y, v); build(z, y + 1, r, v); pull(x, z); } node get(int x, int l, int r, int ll, int rr) { if (ll <= l && r <= rr) { return tree[x]; } int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); push(x, l, r); node res{}; if (rr <= y) { res = get(x + 1, l, y, ll, rr); } else { if (ll > y) { res = get(z, y + 1, r, ll, rr); } else { res = unite(get(x + 1, l, y, ll, rr), get(z, y + 1, r, ll, rr)); } } pull(x, z); return res; } template <typename... M> void modify(int x, int l, int r, int ll, int rr, const M &...v) { if (ll <= l && r <= rr) { tree[x].apply(l, r, v...); return; } int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); push(x, l, r); if (ll <= y) { modify(x + 1, l, y, ll, rr, v...); } if (rr > y) { modify(z, y + 1, r, ll, rr, v...); } pull(x, z); } int find_first_knowingly(int x, int l, int r, const function<bool(const node &)> &f) { if (l == r) { return l; } push(x, l, r); int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); int res; if (f(tree[x + 1])) { res = find_first_knowingly(x + 1, l, y, f); } else { res = find_first_knowingly(z, y + 1, r, f); } pull(x, z); return res; } int find_first(int x, int l, int r, int ll, int rr, const function<bool(const node &)> &f) { if (ll <= l && r <= rr) { if (!f(tree[x])) { return -1; } return find_first_knowingly(x, l, r, f); } push(x, l, r); int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); int res = -1; if (ll <= y) { res = find_first(x + 1, l, y, ll, rr, f); } if (rr > y && res == -1) { res = find_first(z, y + 1, r, ll, rr, f); } pull(x, z); return res; } int find_last_knowingly(int x, int l, int r, const function<bool(const node &)> &f) { if (l == r) { return l; } push(x, l, r); int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); int res; if (f(tree[z])) { res = find_last_knowingly(z, y + 1, r, f); } else { res = find_last_knowingly(x + 1, l, y, f); } pull(x, z); return res; } int find_last(int x, int l, int r, int ll, int rr, const function<bool(const node &)> &f) { if (ll <= l && r <= rr) { if (!f(tree[x])) { return -1; } return find_last_knowingly(x, l, r, f); } push(x, l, r); int y = (l + r) >> 1; int z = x + ((y - l + 1) << 1); int res = -1; if (rr > y) { res = find_last(z, y + 1, r, ll, rr, f); } if (ll <= y && res == -1) { res = find_last(x + 1, l, y, ll, rr, f); } pull(x, z); return res; } segtree(int _n) : n(_n) { assert(n > 0); tree.resize(2 * n - 1); build(0, 0, n - 1); } template <typename M> segtree(const vector<M> &v) { n = v.size(); assert(n > 0); tree.resize(2 * n - 1); build(0, 0, n - 1, v); } node get(int ll, int rr) { assert(0 <= ll && ll <= rr && rr <= n - 1); return get(0, 0, n - 1, ll, rr); } node get(int p) { assert(0 <= p && p <= n - 1); return get(0, 0, n - 1, p, p); } template <typename... M> void modify(int ll, int rr, const M &...v) { assert(0 <= ll && ll <= rr && rr <= n - 1); modify(0, 0, n - 1, ll, rr, v...); } int find_first(int ll, int rr, const function<bool(const node &)> &f) { assert(0 <= ll && ll <= rr && rr <= n - 1); return find_first(0, 0, n - 1, ll, rr, f); } int find_last(int ll, int rr, const function<bool(const node &)> &f) { assert(0 <= ll && ll <= rr && rr <= n - 1); return find_last(0, 0, n - 1, ll, rr, f); } }; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, tt; cin >> n >> tt; vector<int> p(n); vector<int> w(n); for (int i = 1; i < n; i++) { cin >> p[i] >> w[i]; p[i]--; } vector<vector<int>> qs(n); vector<int> L(tt), R(tt), v(tt); vector<long long> res(tt, -1); for (int i = 0; i < tt; i++) { cin >> v[i] >> L[i] >> R[i]; v[i]--; L[i]--; R[i]--; qs[v[i]].push_back(i); } vector<long long> dst(n); for (int i = 1; i < n; i++) { dst[i] = dst[p[i]] + w[i]; } vector<int> is_leaf(n, 1); for (int i = 1; i < n; i++) { is_leaf[p[i]] = 0; } const long long inf = (long long)1e18; for (int i = 0; i < n; i++) { if (!is_leaf[i]) { dst[i] = inf; } } segtree st(dst); vector<int> stk; vector<int> to(n, n - 1); for (int i = 0; i < n; i++) { while (!stk.empty() && stk.back() != p[i]) { int u = stk.back(); to[u] = i - 1; stk.pop_back(); } stk.push_back(i); } 42; stk.clear(); for (int i = 0; i < n; i++) { while (!stk.empty() && stk.back() != p[i]) { int u = stk.back(); st.modify(0, n - 1, -w[u]); st.modify(u, to[u], 2 * w[u]); stk.pop_back(); } stk.push_back(i); st.modify(0, n - 1, w[i]); st.modify(i, to[i], -2 * w[i]); for (int id : qs[i]) { res[id] = st.get(L[id], R[id]).mn; } } for (int i = 0; i < tt; i++) { cout << res[i] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long i, j, k, n, t, s, p[100009], d[100009], a[100009]; int main() { cin >> n; for (i = 1; i <= n; i++) cin >> p[i]; for (i = 1; i <= n; i++) if (!d[i]) { k = 0; j = i; while (d[j] == 0) { d[j] = 1; j = p[j]; k++; } d[i] = 1; k = max(1LL, k); a[++t] = k; } sort(a + 1, a + t + 1); for (i = 1; i <= t - 2; i++) s += a[i] * 1LL * a[i]; k = a[t - 1] + a[t]; s += k * 1LL * k; cout << s; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_BLACKBOX_V
`define SKY130_FD_SC_MS__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_BLACKBOX_V
|
`timescale 1ns/10ps
module hps_design_PLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("100.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK video output
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: rk_video.v
//
module rk_video(
input clk50mhz,
output hr,
output vr,
output cce,
output [3:0] r,
output [3:0] g,
output [3:0] b,
input[3:0] line,
input[6:0] ichar,
input vsp,
input lten,
input rvv,
input videomode
);
reg[1:0] state;
reg[9:0] h_cnt;
reg[9:0] v_cnt;
reg[2:0] d_cnt;
reg[5:0] data;
wire[7:0] fdata;
assign hr = h_cnt >= 10'd478 && h_cnt < 10'd530 ? 1'b0 : 1'b1;
assign vr = v_cnt >= 10'd608 && v_cnt < 10'd614 ? 1'b0 : 1'b1;
assign cce = d_cnt==3'b000 && state==2'b01;
assign r = data[5] ? (videomode ? 4'b0011 : 4'b1000): 4'b0;
assign g = data[5] ? (videomode ? 4'b1000 : 4'b1000): 4'b0;
assign b = data[5] ? (videomode ? 4'b0011 : 4'b1000): 4'b0;
font from(.addra({ichar[6:0],line[2:0]}), .clka(clk50mhz), .douta(fdata));
always @(posedge clk50mhz)
begin
casex (state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b1x: state <= 2'b00;
endcase
if (state==2'b00) begin
if (d_cnt==3'b101) begin
data <= lten ? 6'h3F : vsp ? 6'b0 : fdata[5:0]^{6{rvv}};
end else
data <= {data[4:0],1'b0};
if (h_cnt+1'b1 == 10'd533) begin
h_cnt <= 0; d_cnt <= 0;
if (v_cnt+1'b1 == 10'd625 ) begin
v_cnt <= 0;
end else begin
v_cnt <= v_cnt+1'b1;
end
end else begin
h_cnt <= h_cnt+1'b1;
if (d_cnt+1'b1 == 3'b110) begin
d_cnt <= 0;
end else
d_cnt <= d_cnt+1'b1;
end
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_8_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_0_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region_or
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
//======================================================================
//
// blockmem_rw32_r128.v
// --------------------
// Test implementation of a block memory that has different data
// widths on external (api) and internal ports.
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem_rw32_r128(
input wire clk,
input wire api_we,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [05 : 0] internal_addr,
output wire [127 : 0] internal_rd_data
);
//----------------------------------------------------------------
// Regs and memories.
//----------------------------------------------------------------
reg [31 : 0] mem0 [0 : 63];
reg [31 : 0] mem1 [0 : 63];
reg [31 : 0] mem2 [0 : 63];
reg [31 : 0] mem3 [0 : 63];
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] muxed_api_rd_data;
reg [31 : 0] mem0_api_rd_data;
reg [31 : 0] mem1_api_rd_data;
reg [31 : 0] mem2_api_rd_data;
reg [31 : 0] mem3_api_rd_data;
reg [31 : 0] mem0_int_rd_data;
reg [31 : 0] mem1_int_rd_data;
reg [31 : 0] mem2_int_rd_data;
reg [31 : 0] mem3_int_rd_data;
reg mem0_we;
reg mem1_we;
reg mem2_we;
reg mem3_we;
//----------------------------------------------------------------
// Assignmets.
//----------------------------------------------------------------
assign api_rd_data = muxed_api_rd_data;
assign internal_rd_data = {mem3_int_rd_data, mem2_int_rd_data,
mem1_int_rd_data, mem0_int_rd_data};
//----------------------------------------------------------------
// Reg updates.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update_mem0
if (mem0_we)
mem0[api_addr[7 : 2]] <= api_wr_data;
mem0_api_rd_data <= mem0[api_addr[7 : 2]];
mem0_int_rd_data <= mem0[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem1
if (mem1_we)
mem1[api_addr[7 : 2]] <= api_wr_data;
mem1_api_rd_data <= mem1[api_addr[7 : 2]];
mem1_int_rd_data <= mem1[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem2
if (mem2_we)
mem2[api_addr[7 : 2]] <= api_wr_data;
mem2_api_rd_data <= mem2[api_addr[7 : 2]];
mem2_int_rd_data <= mem2[internal_addr];
end
always @ (posedge clk)
begin : reg_update_mem3
if (mem3_we)
mem3[api_addr[7 : 2]] <= api_wr_data;
mem3_api_rd_data <= mem3[api_addr[7 : 2]];
mem3_int_rd_data <= mem3[internal_addr];
end
//----------------------------------------------------------------
// api_mux
//----------------------------------------------------------------
always @*
begin : api_mux
mem0_we = 1'b0;
mem1_we = 1'b0;
mem2_we = 1'b0;
mem3_we = 1'b0;
case (api_addr[1 : 0])
0:
begin
muxed_api_rd_data = mem0_api_rd_data;
mem0_we = api_we;
end
1:
begin
muxed_api_rd_data = mem1_api_rd_data;
mem1_we = api_we;
end
2:
begin
muxed_api_rd_data = mem2_api_rd_data;
mem2_we = api_we;
end
3:
begin
muxed_api_rd_data = mem3_api_rd_data;
mem3_we = api_we;
end
default:
begin
end
endcase // case (api_addr[1 : 0])
end // api_mux
endmodule // blockmem_rw32_r128
//======================================================================
// eof blockmem_rw32_r128.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int n, ans; bool pd(int n) { for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } int main() { scanf( %d , &n); if (pd(n)) puts( 1 ); else if (n % 2 == 0 || pd(n - 2)) puts( 2 ); else puts( 3 ); return 0; }
|
`include "FpuFp32_Add.v"
`include "FpuFp32_Mul.v"
`include "FpuFp32_Rcp.v"
module FpuFp32(
/* verilator lint_off UNUSED */
clk,
opMode,
srca,
srcb,
dst
);
input clk;
input[3:0] opMode;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
parameter[3:0] OP_NONE = 4'h00;
parameter[3:0] OP_ADD = 4'h01;
parameter[3:0] OP_SUB = 4'h02;
parameter[3:0] OP_MUL = 4'h03;
parameter[3:0] OP_DIV = 4'h04;
parameter[3:0] OP_ABS = 4'h05;
parameter[3:0] OP_NEG = 4'h06;
parameter[3:0] OP_RCP = 4'h07;
parameter[3:0] OP_SQRT = 4'h08;
reg fpaIsSub;
reg[31:0] fpaDst;
FpuFp32_Add fpadd(clk, fpaIsSub, srca, srcb, fpaDst);
reg[31:0] fpmSrcB;
reg[31:0] fpmDst;
FpuFp32_Mul fpmul(clk, srca, fpmSrcB, fpmDst);
// FpuFp32_Mul fpmul(clk, srca, srcb, fpmDst);
reg[31:0] fpRcpDst;
FpuFp32_Rcp fprcp(clk, srcb, fpRcpDst);
// reg[31:0] fpdDst;
// FpuFp32_Mul fpdiv(clk, srca, fpRcpDst, fpdDst);
assign fpaIsSub = (opMode==OP_SUB);
assign fpmSrcB = (opMode==OP_DIV) ? fpRcpDst : srcb;
reg[31:0] tDst;
always @ (opMode) begin
// fpmSrcB = srcb;
case(opMode)
OP_ADD: begin
tDst = fpaDst;
end
OP_SUB: begin
tDst = fpaDst;
end
OP_MUL: begin
// fpmSrcB = srcb;
tDst = fpmDst;
end
OP_DIV: begin
// fpmSrcB = fpRcpDst;
// fpmSrcB = srcb;
tDst = fpmDst;
end
OP_ABS: begin
tDst[31] = 0;
tDst[30:0] = srcb[30:0];
end
OP_NEG: begin
tDst[31] = !srcb[31];
tDst[30:0] = srcb[30:0];
end
OP_RCP: begin
tDst = fpRcpDst;
end
OP_SQRT: begin
tDst = ((srcb-32'h3F80_0000)>>>1)+32'h3F80_0000;
end
default: begin
tDst = srcb;
end
endcase
dst = tDst;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops ) using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; int read_int() { bool minus = false; int result = 0; char ch; ch = getchar(); while (1) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (1) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = result * 10 + (ch - 0 ); } if (minus) return -result; else return result; } const int MAX = 2e5 + 10; unsigned char v[MAX]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n = read_int(); for (int i = 0; i < n; i++) v[i] = read_int(); int q = read_int(); while (q--) { int l = read_int(), r = read_int(); unsigned char x = read_int(), y = read_int(); l--, r--; for (int i = l; i <= r; i++) v[i] = v[i] == x ? y : v[i]; } for (int i = 0; i < n; i++) cout << int(v[i]) << ; cout << n ; exit(0); }
|
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