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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_1_V
`define SKY130_FD_SC_HDLL__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_1_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); long long t; cin >> t; while (t--) { long long n; cin >> n; string a; cin >> a; string last = a; for (long long i = 0; i <= n; ++i) { string s; s = a; for (long long k = 1; k < n; ++k) { if (a[k - 1] == A ) { s[k] = A ; } } a = s; if (a == last) { cout << i << n ; break; } last = a; } } }
|
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 9;
parameter BLK_RAM_TYPE = "AUTO";
parameter ADDR_DEPTH = 2**ADDR_WIDTH;
input [DATA_WIDTH -1:0] data_a;
input wren_a;
input [ADDR_WIDTH -1:0] address_a;
input clock_a;
output [DATA_WIDTH -1:0] q_a;
input [DATA_WIDTH -1:0] data_b;
input wren_b;
input [ADDR_WIDTH -1:0] address_b;
input clock_b;
output [DATA_WIDTH -1:0] q_b;
wire [35:0] do_b;
wire [35:0] din_a;
assign din_a =data_a;
assign q_b =do_b;
RAMB16_S36_S36 U_RAMB16_S36_S36 (
.DOA ( ),
.DOB (do_b[31:0] ),
.DOPA ( ),
.DOPB (do_b[35:32] ),
.ADDRA (address_a ),
.ADDRB (address_b ),
.CLKA (clock_a ),
.CLKB (clock_b ),
.DIA (din_a[31:0] ),
.DIB ( ),
.DIPA (din_a[35:32] ),
.DIPB ( ),
.ENA (1'b1 ),
.ENB (1'b1 ),
.SSRA (1'b0 ),
.SSRB (1'b0 ),
.WEA (wren_a ),
.WEB (1'b0 ));
endmodule
|
// Library - static, Cell - th44w322, View - schematic
// LAST TIME SAVED: May 23 18:01:00 2014
// NETLIST TIME: May 23 18:01:20 2014
`timescale 1ns / 1ns
module th44w322 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w322";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net45), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net45), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(net036), .d(net047));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net047), .d(net32));
pfet_b P10 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net32));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net49));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: if_id
// File: if_id.v
// Author: Lei Silei
// E-mail:
// Description: IF/ID½×¶ÎµÄ¼Ä´æÆ÷
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module if_id(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
input wire[`InstAddrBus] if_pc,
input wire[`InstBus] if_inst,
output reg[`InstAddrBus] id_pc,
output reg[`InstBus] id_inst
);
always @ (posedge clk) begin
if (rst == `RstEnable) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if(flush == 1'b1 ) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if(stall[1] == `Stop && stall[2] == `NoStop) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if(stall[1] == `NoStop) begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, i, j = 1, j2 = 0, j3, k, h = 1; string s; cin >> s; for (i = 1; i < s.length(); ++i) { if (j < h) j = h; if (h == s.length()) break; if (s[i - 1] != s[i] && i != 0) h++; else if (i == 0 && s[i] != s[s.length() - 1]) h++; else h = 1; if (i == s.length() - 1 && j2 == 0) { i = -1; j2 = 1; } } if (j < h) j = h; cout << j << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e9 + 1; const long long INFLL = 1e18 + 1; struct Graph { struct edge { int c, f, link, to, ind; int c2 = 0; edge() {} edge(int c, int f, int link, int to, int ind) : c(c), f(f), link(link), to(to), ind(ind) {} }; vector<vector<edge>> g; int s, t, n; Graph(int N, int S, int T) { n = N; s = S, t = T; g.resize(n); } vector<int> usd; int dfs(int v, int now) { usd[v] = 1; if (v == t) return now; for (auto &e : g[v]) { if (usd[e.to] || e.f == e.c) continue; int x = dfs(e.to, min(now, e.c - e.f)); if (x == 0) continue; e.f += x; g[e.to][e.link].f -= x; return x; } return 0; } int Ford_Fulkerson() { int ans = 0; while (1) { usd.assign(n, 0); int d = dfs(s, INF); ans += d; if (d == 0) break; } return ans; } void add_not_dir(int a, int b, int c, int i) { g[a].emplace_back(c, 0, g[b].size(), b, i); g[b].emplace_back(c, 0, g[a].size() - 1, a, i); } void add_dir(int a, int b, int c, int i) { g[a].emplace_back(c, 0, g[b].size(), b, i); g[b].emplace_back(0, 0, g[a].size() - 1, a, i); } int Edmonds_Karp() { int ans = 0; while (1) { queue<int> q; vector<int> p(n, -1), dist(n, INF), mn(n, INF); q.push(s); dist[s] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (auto &e : g[v]) { if (e.f == e.c || dist[e.to] != INF) continue; p[e.to] = v; q.push(e.to); dist[e.to] = dist[v] + 1; mn[e.to] = min(mn[v], e.c - e.f); } } if (dist[t] == INF) break; vector<int> path; int now = t; while (now != -1) { path.emplace_back(now); now = p[now]; } reverse((path).begin(), (path).end()); int F = mn[t]; ans += F; for (int i = 0; i < (int)path.size() - 1; i++) { int v = path[i]; for (auto &e : g[v]) { if (e.to == path[i + 1] && e.c - e.f >= F) { e.f += F; g[e.to][e.link].f -= F; break; } } } } return ans; } vector<int> d, uk; int dfs_Dinic(int v, int now) { if (v == t || now == 0) return now; for (int i = uk[v]; i < (int)g[v].size(); i++) { if (d[g[v][i].to] == d[v] + 1) { int can = g[v][i].c2 - g[v][i].f; int x = dfs_Dinic(g[v][i].to, min(can, now)); if (x != 0) { g[v][i].f += x; g[g[v][i].to][g[v][i].link].f -= x; return x; } } uk[v]++; } return 0; } bool bfs() { d.assign(n, INF); d[s] = 0; deque<int> q; q.push_back(s); while (!q.empty()) { int v = q.front(); q.pop_front(); for (auto &e : g[v]) { if (e.f < e.c2 && d[e.to] == INF) { d[e.to] = d[v] + 1; q.push_back(e.to); } } } return d[t] != INF; } long long Dinic() { long long ans = 0; while (bfs()) { uk.assign(n, 0); while (1) { int d = dfs_Dinic(s, INF); if (d == 0) break; ans += d; } } return ans; } long long Fast_Dinic() { long long ans = 0; for (int j = 29; j >= 0; j--) { for (int i = 0; i < n; i++) { for (int k = 0; k < (int)g[i].size(); k++) { if (g[i][k].c & (1 << j)) g[i][k].c2 += (1 << j); } } ans += Dinic(); } return ans; } }; bool is_prime(int x) { for (int i = 2; i * i <= x; i++) { if (x % i == 0) return false; } return true; } vector<int> usd; vector<vector<int>> gr; void dfs_ans(int v, vector<int> &comp) { comp.emplace_back(v); usd[v] = 1; for (auto &to : gr[v]) { if (!usd[to]) dfs_ans(to, comp); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> a(n); int cnt0 = 0, cnt1 = 0; for (auto &c : a) { cin >> c; if (c % 2 == 0) cnt0++; else cnt1++; } if (cnt0 != cnt1) { cout << Impossible ; return 0; } Graph g(n + 2, n, n + 1); for (int i = 0; i < n; i++) { if (a[i] % 2 == 1) { g.add_dir(n, i, 2, -1); } else { g.add_dir(i, n + 1, 2, i); } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (a[i] % 2 == 1 && a[j] % 2 == 0) { if (is_prime(a[i] + a[j])) { g.add_dir(i, j, 1, -1); } } } } int x = g.Edmonds_Karp(); if (x != 2 * cnt0) { cout << Impossible ; return 0; } gr.resize(n); vector<vector<int>> ans; for (int i = 0; i < n; i++) { for (auto &e : g.g[i]) { if (e.f == 1) { gr[i].emplace_back(e.to); gr[e.to].emplace_back(i); } } } usd.assign(n, 0); for (int i = 0; i < n; i++) { if (!usd[i]) { ans.emplace_back(vector<int>()); dfs_ans(i, ans.back()); } } cout << ans.size() << n ; for (auto &c : ans) { cout << c.size() << ; for (auto &l : c) { cout << l + 1 << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> int main(void) { int x1, y1, x2, y2, temp; int n; int x[1001], y[1001], r[1001]; int i, j; int people, blanket = 0; scanf( %d%d%d%d%d , &x1, &y1, &x2, &y2, &n); for (i = 0; i < n; i++) { scanf( %d%d%d , &x[i], &y[i], &r[i]); r[i] = r[i] * r[i]; } if (x1 > x2) { temp = x1; x1 = x2; x2 = temp; } if (y1 > y2) { temp = y1; y1 = y2; y2 = temp; } for (i = x1; i < x2; i++) { for (j = 0; j < n; j++) { if (r[j] >= (i - x[j]) * (i - x[j]) + (y1 - y[j]) * (y1 - y[j])) break; if (j == n - 1) { blanket++; } } } for (i = x1 + 1; i <= x2; i++) { for (j = 0; j < n; j++) { if (r[j] >= (i - x[j]) * (i - x[j]) + (y2 - y[j]) * (y2 - y[j])) break; if (j == n - 1) { blanket++; } } } for (i = y1 + 1; i <= y2; i++) { for (j = 0; j < n; j++) { if (r[j] >= (i - y[j]) * (i - y[j]) + (x1 - x[j]) * (x1 - x[j])) break; if (j == n - 1) { blanket++; } } } for (i = y1; i < y2; i++) { for (j = 0; j < n; j++) { if (r[j] >= (i - y[j]) * (i - y[j]) + (x2 - x[j]) * (x2 - x[j])) break; if (j == n - 1) { blanket++; } } } printf( %d , blanket); }
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : dd_sync
-- Author : mammenx
-- Associated modules:
-- Function : This module synchronizes a signal (of parameterized
width) to the destination clock.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module dd_sync #(WIDTH = 1, STAGES = 2, RST_VAL = 0)
(
//--------------------- Misc Ports (Logic) -----------
clk,
rst_n,
data_i,
data_sync_o
//--------------------- Interfaces --------------------
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
input clk;
input rst_n;
input [WIDTH-1:0] data_i;
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
output [WIDTH-1:0] data_sync_o;
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
reg [WIDTH-1:0] sync_pipe_f [0:STAGES-1];
//----------------------- Internal Wire Declarations ----------------------
//----------------------- Internal Interface Declarations -----------------
//----------------------- FSM Declarations --------------------------------
//----------------------- Start of Code -----------------------------------
genvar i;
generate
for(i=0; i<STAGES; i++)
begin : SYNC
always@(posedge clk, negedge rst_n)
begin
if(~rst_n)
begin
sync_pipe_f[i] <= RST_VAL;
end
else
begin
sync_pipe_f[i] <= (i == 0) ? data_i : sync_pipe_f[i-1];
end
end
end
endgenerate
assign data_sync_o = sync_pipe_f[STAGES-1];
endmodule // dd_sync
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-06-2014 03:30:07 PM][mammenx] Moved to Verilog
[08-06-2014 11:32:22 AM][mammenx] Corrected multi-dimension order for sync_pipe_f
[08-06-2014 11:11:26 AM][mammenx] Added RST_VAL parameter
[08-06-2014 11:09:00 AM][mammenx] Initial Version
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <>
//
// Create Date: 12/30/2016 11:00:20 AM
// Design Name:
// Module Name: azimuth_signal_generator_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module azimuth_signal_generator_sim;
localparam SIZE = 3200;
localparam FSIZE = SIZE / 4;
localparam HHIGH = {FSIZE{1'b1}};
localparam HLOW = {FSIZE{1'b0}};
reg EN;
reg CLK;
parameter PERIOD = 10;
parameter TRIG_PERIOD = 30000*PERIOD;
parameter US_PERIOD = 10*PERIOD;
// clock
initial begin
EN = 1'b0;
CLK = 1'b0;
repeat(4) #PERIOD CLK = ~CLK;
EN = 1'b1;
forever #PERIOD CLK = ~CLK; // generate a clock
end
// Inputs
reg TRIG;
reg US_CLK;
reg [SIZE-1:0] DATA = {HLOW, HHIGH, HLOW, HHIGH};
// output
wire GEN_SIGNAL;
wire clk_rise, trig_rise;
initial begin
TRIG = 0;
@(posedge EN);
TRIG = 1;
@(posedge CLK);
TRIG = 0;
forever #TRIG_PERIOD TRIG = ~TRIG;
end
initial begin
US_CLK = 0;
forever #US_PERIOD US_CLK = ~US_CLK;
end
edge_detect ed_clk (
.async_sig(US_CLK),
.clk(CLK),
.rise(clk_rise)
);
edge_detect ed_trig (
.async_sig(TRIG),
.clk(CLK),
.rise(trig_rise)
);
azimuth_signal_generator #(SIZE) uut (
.EN(EN),
.TRIG(trig_rise),
.CLK_PE(clk_rise),
.SYS_CLK(CLK),
.DATA(DATA),
.GEN_SIGNAL(GEN_SIGNAL)
);
endmodule
|
// megafunction wizard: %CRC Compiler v11.0%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// check_ip_altcrc
// ============================================================
// Generated by CRC Compiler 11.0 [Altera, IP Toolbench 1.3.0 Build 157]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module check_ip (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
crcbad,
crcvalid);
input clk;
input [127:0] data;
input datavalid;
input [3:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output crcbad;
output crcvalid;
check_ip_altcrc check_ip_altcrc_inst(
.clk(clk),
.data(data),
.datavalid(datavalid),
.empty(empty),
.endofpacket(endofpacket),
.reset_n(reset_n),
.startofpacket(startofpacket),
.crcbad(crcbad),
.crcvalid(crcvalid));
endmodule
// =========================================================
// CRC Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, CRC Compiler Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="CRC Compiler" version="11.0" build="157" iptb_version="1.3.0 Build 157" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="check_ip_altcrc" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "p_wordsize" value="128" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_crccheck" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_inbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_outbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lanes" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_fwdpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_initvalue" value="0xFFFFFFFF" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_bckpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_generator" value="1_0000_0100_1100_0001_0001_1101_1011_0111" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lsb" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_symbol_lsb" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_true_output" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_reverse" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_start_offset" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_channels" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_optimize" value="speed" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_use_all_ones" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_datapath" value="128 bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_genname" value="CRC-32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_negate_checksum" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_cbx_hdl_language" value="verilog" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="check_ip_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="check_ip.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR3B_BEHAVIORAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, a[100010], new_arr[100010], new_arr1[100010], arr[100010]; int x = 1000000; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { new_arr[i] = min((i + 1), (n - i)); new_arr1[i] = a[i] - new_arr[i]; if (new_arr1[i] >= 0) { arr[new_arr1[i]]++; } } for (int i = 0; i < 100000; i++) { x = min(x, n - arr[i]); } cout << x; }
|
#include <bits/stdc++.h> using namespace std; long long q, t; bool f(long long x) { for (long long i = 2; i * i <= x; i++) if (x % i == 0) return false; return true; } int main() { ios::sync_with_stdio(false); cin >> q; while (q--) { long long ans = 0; cin >> t; { if (t == 2) { cout << -1 << endl; continue; } if (t == 9) { cout << 1 << endl; continue; } if (t % 2 == 1) { t -= 9; if (t < 4) { cout << -1 << endl; continue; } else ans++; } if (t % 4 == 0) cout << t / 4 + ans << endl; else if (t % 4 == 2) cout << t / 4 + ans << endl; else if (t % 6 == 0) cout << t / 6 + ans << endl; else if (t % 6 == 4) cout << t / 6 + 1 + ans << endl; else cout << 1 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long binPow(long long a, long long b) { long long x = 1, y = a; while (b) { if (b & 1) x = (x * y) % mod; y = (y * y) % mod; b >>= 1; } return x % mod; } long long inverserEuler(int n) { return binPow(n, mod - 2); } long long C(int k, int n) { vector<long long> f(n + 1, 1); for (int i = 2; i <= n; i++) f[i] = (f[i - 1] * i) % mod; return (f[n] * ((inverserEuler(f[k]) * inverserEuler(f[n - k])) % mod) % mod) % mod; } void trunghieu() { int n; cin >> n; int a[n], i, j; map<int, int> cnt; for (i = 0; i < n; ++i) cin >> a[i], cnt[a[i]]++; if (cnt.size() == 2) { map<int, int>::iterator it; it = cnt.begin(); int n1 = it->second, x1 = it->first; it++; int n2 = it->second, x2 = it->first; ; if (n1 == n2) cout << YES << endl << x1 << << x2; else cout << NO ; } else cout << NO ; } int main() { ios::sync_with_stdio(false); cin.tie(); trunghieu(); return 0; }
|
//-----------------------------------------------------------------------------
// For reading TI tags, we need to place the FPGA in pass through mode
// and pass everything through to the ARM
//-----------------------------------------------------------------------------
module lo_passthru(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg, divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
reg [7:0] pck_divider;
reg ant_lo;
// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
// which is high for (divisor+1) pck0 cycles and low for the same duration
// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
ant_lo = !ant_lo;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
// the antenna is modulated when ssp_dout = 1, when 0 the
// antenna drivers stop modulating and go into listen mode
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign pwr_lo = ant_lo && ssp_dout;
assign pwr_hi = 1'b0;
assign adc_clk = 1'b0;
assign ssp_din = cross_lo;
assign dbg = cross_lo;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:23:42 09/12/2015
// Design Name: Seven_seg
// Module Name: Z:/share/ISE/CPUFly/tests/Seven_seg_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Seven_seg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Seven_seg_test;
// Inputs
reg clk;
reg reset;
reg [31: 0] DAT_I;
reg STB;
reg WE;
// Outputs
wire [31:0] DAT_O;
wire ACK;
wire [7:0] Segment;
wire [3:0] AN;
wire [15: 0] debug_data_hold;
// Instantiate the Unit Under Test (UUT)
Seven_seg uut (
.clk(clk),
.reset(reset),
.DAT_I(DAT_I),
.STB(STB),
.DAT_O(DAT_O),
.ACK(ACK),
.WE(WE),
.Segment(Segment),
.AN(AN),
.debug_data_hold(debug_data_hold)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
DAT_I = 0;
STB = 0;
WE = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
#50 DAT_I = 32'h00001234;
STB = 1;
#50 STB = 0;
end
always begin
#25 clk = ~clk;
end
endmodule
|
`timescale 1ns / 1ps
//__________________________________________________uart_tx
`define RDY 2'b11
`define LOAD_BIT 2'b01
`define SEND_BIT 2'b00
`define STOP 2'b10
//__________Test Bench
`define BIT_TMR_MAX 10'd869 // test bench <-- 115200 : tb #1738
//`define BIT_TMR_MAX 4'd10417//14'b10100010110000 // 14'd1023
//______________________________________________________________________
// `define BIT_INDEX_MAX 4'd10
module uart_tx(
input clk,
input rst,
input send,
input [7:0] data_tx,
output done,
output txd
);
reg [9:0] bitTmr;
//wire bitDone;
reg [3:0] bitIndex;
wire txBit;
//reg [9:0] txdata_tx;
reg [1:0] txState;
assign done = (txState == `STOP) ? 1'b1 : 1'b0;
assign txd = (txState == `SEND_BIT) ? txBit : 1'b1;
//{1'b1,data_tx[7:0],1'b0}
assign txBit =( (bitIndex == 0) ? 1'b0 :
( (bitIndex == 1) ? data_tx[0] :
( (bitIndex == 2) ? data_tx[1] :
( (bitIndex == 3) ? data_tx[2] :
( (bitIndex == 4) ? data_tx[3] :
( (bitIndex == 5) ? data_tx[4] :
( (bitIndex == 6) ? data_tx[5] :
( (bitIndex == 7) ? data_tx[6] :
( (bitIndex == 8) ? data_tx[7] :
1'b1
)
)
)
)
)
)
)
)
);
always@(posedge clk) begin
if(rst)
txState<= `RDY;
else
case(txState)
`RDY :
begin
bitIndex <= 0;
bitTmr <= 0;
if(send == 1'b1)
txState<=`SEND_BIT;
else
txState<=`RDY;
end
`SEND_BIT :
begin
if (bitTmr == `BIT_TMR_MAX-1)
begin
bitTmr <=0;
if (bitIndex == 4'd10-1)
begin
txState<=`STOP;
end
else
begin
bitIndex <= bitIndex + 1'b1;
txState<=`SEND_BIT;
end
end
else
begin
bitTmr <= bitTmr + 1'b1;
txState <= `SEND_BIT;
end
end
`STOP :
begin
if(send == 1'b1)
txState<=txState;
else //if(send == 1'b0)
txState<=`RDY;
end
default :
txState <= `RDY;
endcase
end
/*
always@(posedge clk) begin
if(rst)
bitTmr <= 0;
else
if(txState[0] == 1) // if(txState == `RDY)
bitTmr <= 0;
else
if(bitDone)
bitTmr <= 0;
else
bitTmr <= bitTmr +1 ;
end
assign bitDone = (bitTmr == `BIT_TMR_MAX) ? 1 : 0;
always@(posedge clk) begin
if(rst)
bitIndex <= 0;
else
if(txState[1] == 1) // if(txState == `RDY)
bitIndex <= 0;
else
if(txState == `LOAD_BIT)
bitIndex <= bitIndex +1 ;
else
bitIndex <= bitIndex;
end
*/
/*
always@(posedge clk) begin
if(rst)
txdata_tx <= 0;
else
if(txState[1] == 0) // if(send == 1'b1)
txdata_tx <= {1'b1,data_tx,1'b0} ;
else
txdata_tx <= 10'b1_1111_1111_1;
end
always@(posedge clk) begin
if(rst)
txBit <= 1'b1;
else
if(txState[1] == 1) // if(txState == `RDY)
txBit <= 1'b1 ;
else //if(txState == `LOAD_BIT)
txBit <= txdata_tx[bitIndex];
end
assign txd = rst ? 1 : txBit;
*/
//assign ready = (txState == `RDY) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { int k, n; cin >> n >> k; int val[100000]; int awake[100000]; for (int i = 0; i < n; ++i) { cin >> val[i]; } int sum = 0; int extra = 0; int max = 0; for (int i = 0; i < n; ++i) { cin >> awake[i]; if (awake[i]) { sum += val[i]; val[i] = 0; } if (i < k) { extra += val[i]; } else { extra = extra + val[i] - val[i - k]; } if (extra > max) { max = extra; } } sum += max; cout << sum << endl; return 0; }
|
// megafunction wizard: %LPM_ABS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_abs
// ============================================================
// File Name: ABS.v
// Megafunction Name(s):
// lpm_abs
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ABS (
data,
result);
input [29:0] data;
output [29:0] result;
wire [29:0] sub_wire0;
wire [29:0] result = sub_wire0[29:0];
lpm_abs lpm_abs_component (
.data (data),
.result (sub_wire0),
.overflow ());
defparam
lpm_abs_component.lpm_type = "LPM_ABS",
lpm_abs_component.lpm_width = 30;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: OptionalOverflowOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "30"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ABS"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
// Retrieval info: USED_PORT: data 0 0 30 0 INPUT NODEFVAL data[29..0]
// Retrieval info: USED_PORT: result 0 0 30 0 OUTPUT NODEFVAL result[29..0]
// Retrieval info: CONNECT: @data 0 0 30 0 data 0 0 30 0
// Retrieval info: CONNECT: result 0 0 30 0 @result 0 0 30 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long dp[55][2]; int main() { long long X, Y; scanf( %lld %lld , &Y, &X); dp[51][0] = 1; for (int i = 50; i >= 0; i--) { for (int flag = 0; flag <= 1; flag++) { bool x = (X >> i) & 1, y = (Y >> i) & 1; if (x) dp[i][flag] += dp[i + 1][(flag + 1) / 2] * (flag != y) * 2; else { dp[i][flag] += dp[i + 1][(flag + 2) / 2] * (flag == y); dp[i][flag] += dp[i + 1][0] * (flag == y); } } } if (!X) assert(dp[0][0] - (X == Y) * 2 == (!(Y & 1))); printf( %lld n , dp[0][0] - (X == Y) * 2); return 0; }
|
module TopLevel(clk,
key_in,
switch_in,
switch_second,
type_in,
s_out,
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RW,
LCD_RS,
LCD_DATA
);
input [3:0] key_in;
input clk;// 50Mhz clock signal
input switch_in; // switch of settime of countdowner
input [15:0] switch_second; // set time of countdowner
input type_in; // 7seg display timer or countdowner;
output [63:0] s_out;
wire [63:0] seg_o;
assign s_out = ~seg_o;
output LCD_ON, LCD_BLON, LCD_EN, LCD_RW, LCD_RS;
output [7:0] LCD_DATA;
assign LCD_ON = 1;
assign LCD_BLON = 1;
wire [1:0] lcd_func;
wire [7:0] lcd_data;
assign LCD_RS = lcd_func[1];
assign LCD_RW = lcd_func[0];
assign LCD_DATA = lcd_data;
wire [31:0] second;
wire [31:0] second_tmp;
wire [31:0] second_countdown;
wire [2:0] key_press;
reg slow_clk;
integer slow_clk_counter;
initial begin
slow_clk <= 0;
slow_clk_counter <= 0;
end
always@(negedge clk) begin
if (slow_clk_counter == 9) begin
slow_clk_counter <= 0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_counter <= slow_clk_counter + 1;
end
end
Timer timer(slow_clk, key_press, second);
Settime settime(switch_in, switch_second, clk, second_tmp);
// I use key_press as well becasue I am lazy.....
Countdowner countdowner(slow_clk, second_tmp, key_press, second_countdown);
Display7seg display7seg(second, second_countdown, type_in, seg_o);
wire [127:0] show_time;
ShowTime showTime(second, show_time);
LCDDisplay lcdDisplay(slow_clk, key_press, show_time, LCD_EN, lcd_func, lcd_data);
// I remember TA said press means 1 to 0. Need some try.
ButtonSignal buttonSignal(slow_clk, key_in, key_press);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long last = -1; void dfs(long long s, vector<vector<pair<long long, long long>>> grf, vector<long long> &vis, long long &cost) { vis[s] = 1; last = s; for (auto x : grf[s]) { long long v = x.first, d = x.second; if (vis[v] == 0) { cost += d; dfs(v, grf, vis, cost); } } } signed main() { long long n; cin >> n; vector<vector<pair<long long, long long>>> grf(n + 1); long long sum = 0; for (long long i = 0; i < n; i++) { long long u, v, w; cin >> u >> v >> w; grf[u].push_back({v, w}); grf[v].push_back({u, 0}); sum += w; } long long cost = 0; vector<long long> vis(n + 1, 0); dfs(1, grf, vis, cost); if (last != 1) { for (auto x : grf[last]) { if (x.first == 1) cost += x.second; } } cout << min(cost, sum - cost); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9; struct node { int i, j, bal; char scoba; node() {} node(long long _i, long long _j, long long _k, char _scoba) : i(_i), j(_j), bal(_k), scoba(_scoba) {} }; node p[210][210][410]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s, t; cin >> s >> t; long long n = s.size(), m = t.size(); vector<vector<vector<long long> > > dp( n + 1, vector<vector<long long> >(m + 1, vector<long long>(410, inf))); dp[0][0][0] = 0; for (long long i = 0; i <= n; ++i) { for (long long j = 0; j <= m; ++j) { for (long long k = 0; k <= 410; ++k) { if (dp[i][j][k] == inf) continue; long long nxti = i + (i < n && s[i] == ( ), nxtj = j + (j < m && t[j] == ( ); if (k + 1 < 410 && dp[nxti][nxtj][k + 1] > dp[i][j][k] + 1) { dp[nxti][nxtj][k + 1] = dp[i][j][k] + 1; p[nxti][nxtj][k + 1] = node(i, j, k, ( ); } nxti = i + (i < n && s[i] == ) ), nxtj = j + (j < m && t[j] == ) ); if (k > 0 && dp[nxti][nxtj][k - 1] > dp[i][j][k] + 1) { dp[nxti][nxtj][k - 1] = dp[i][j][k] + 1; p[nxti][nxtj][k - 1] = node(i, j, k, ) ); } } } } long long curi = n, curj = m, cur_balance = 0; for (long long i = 0; i < 410; ++i) { if (dp[n][m][cur_balance] + cur_balance > dp[n][m][i] + i && dp[n][m][i] != inf) { cur_balance = i; } } string ans = ; long long temp = cur_balance; while (curi > 0 || curj > 0 || cur_balance) { node a = p[curi][curj][cur_balance]; long long ni = a.i; long long nj = a.j; long long nbal = a.bal; ans += a.scoba; curi = a.i; curj = a.j; cur_balance = a.bal; } while (temp--) ans = ) + ans; reverse(ans.begin(), ans.end()); cout << ans; return 0; }
|
module fx2_test(
FX2_CLK,
FX2_WU2,
FX2_FIFOADR, FX2_FD,
FX2_flags,
FX2_PKTEND,
FX2_SLOE, FX2_SLWR, FX2_SLRD,
LED, Push_button,
LASER0_EN,
LASER1_EN,
LASER2_EN,
LASER3_EN
);
input FX2_CLK;
input [2:0] FX2_flags;
input Push_button;
output FX2_WU2;
output [1:0] FX2_FIFOADR;
output FX2_PKTEND;
output FX2_SLOE;
output FX2_SLWR;
output FX2_SLRD;
output [1:0] LED;
output LASER0_EN;
output LASER1_EN;
output LASER2_EN;
output LASER3_EN;
inout [7:0] FX2_FD;
// FX2 inputs
wire FIFO_RD, FIFO_WR, FIFO_PKTEND, FIFO_DATAIN_OE;
wire FX2_SLRD = ~FIFO_RD;
wire FX2_SLWR = ~FIFO_WR;
assign FX2_SLOE = ~FIFO_DATAIN_OE;
assign FX2_PKTEND = ~FIFO_PKTEND;
wire FIFO2_empty = ~FX2_flags[0]; wire FIFO2_data_available = ~FIFO2_empty;
wire FIFO6_full = ~FX2_flags[1]; wire FIFO6_ready_to_accept_data = ~FIFO6_full;
wire FIFO8_full = ~FX2_flags[2]; wire FIFO8_ready_to_accept_data = ~FIFO8_full;
wire [1:0] FIFO_FIFOADR;
assign FX2_FIFOADR = FIFO_FIFOADR;
assign FX2_WU2 = 1'b0;
assign FIFO_FIFOADR = 2'b10;
assign FX2_FD = 8'hAB;
assign FIFO_RD = 0;
assign FIFO_WR = FIFO6_ready_to_accept_data;
assign FIFO_DATAIN_OE = 0;
assign FIFO_PKTEND = 0;
assign LED[0] = FX2_SLWR;
assign LED[1] = FX2_FIFOADR[0];
assign LASER0_EN = FIFO6_ready_to_accept_data;
assign LASER1_EN = FX2_SLOE;
assign LASER2_EN = FX2_SLWR;
assign LASER3_EN = FX2_CLK;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300000; int n, m, q, p[MAXN + 3], rk[MAXN + 3], dia[MAXN + 3], type, x, y, dist[MAXN + 3]; bool flag[MAXN + 3]; vector<int> adj[MAXN + 3]; int ceil(int n) { if (!n) return 0; return (n - 1) / 2 + 1; } int find(int x) { return (p[x] == x ? x : (p[x] = find(p[x]))); } void join(int x, int y) { x = find(x); y = find(y); if (x == y) return; if (rk[x] < rk[y]) swap(x, y); rk[x] += rk[y]; p[y] = x; } void join2(int x, int y) { x = find(x); y = find(y); if (x == y) return; if (rk[x] < rk[y]) swap(x, y); dia[x] = max(max(dia[x], dia[y]), ceil(dia[x]) + ceil(dia[y]) + 1); rk[x] += rk[y]; p[y] = x; } int calDia(int p) { queue<int> q; q.push(p); flag[p] = true; dist[p] = 0; int u, v; while (!q.empty()) { u = q.front(); q.pop(); for (int i = 0; i < (int)adj[u].size(); ++i) { v = adj[u][i]; if (!flag[v]) { flag[v] = true; dist[v] = dist[u] + 1; q.push(v); } } } q.push(u); flag[u] = false; dist[u] = 0; while (!q.empty()) { u = q.front(); q.pop(); for (int i = 0; i < (int)adj[u].size(); ++i) { v = adj[u][i]; if (flag[v]) { flag[v] = false; dist[v] = dist[u] + 1; q.push(v); } } } return dist[u]; } int main() { scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= n; ++i) p[i] = i, rk[i] = 1; for (int i = 1; i <= m; ++i) { scanf( %d %d , &x, &y); join(x, y); adj[x].push_back(y); adj[y].push_back(x); } for (int i = 1; i <= n; ++i) if (find(i) == i) { dia[i] = calDia(i); } while (q-- > 0) { scanf( %d %d , &type, &x); if (type == 1) { printf( %d n , dia[find(x)]); } else { scanf( %d , &y); join2(x, y); } } return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module altera_up_av_config_auto_init (
// Inputs
clk,
reset,
clear_error,
ack,
transfer_complete,
rom_data,
// Bidirectionals
// Outputs
data_out,
transfer_data,
rom_address,
auto_init_complete,
auto_init_error,
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter ROM_SIZE = 50;
parameter AW = 5; // Auto Initialize ROM's address width
parameter DW = 23; // Auto Initialize ROM's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
input [DW: 0] rom_data;
// Bidirectionals
// Outputs
output reg [DW: 0] data_out;
output reg transfer_data;
output reg [AW: 0] rom_address;
output reg auto_init_complete;
output reg auto_init_error;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire toggle_next_transfer;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
data_out <= 'h0;
else
data_out <= rom_data;
end
always @(posedge clk)
begin
if (reset)
transfer_data <= 1'b0;
else if (auto_init_complete | transfer_complete)
transfer_data <= 1'b0;
else
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
rom_address <= 'h0;
else if (toggle_next_transfer)
rom_address <= rom_address + 'h1;
end
always @(posedge clk)
begin
if (reset)
auto_init_complete <= 1'b0;
else if (toggle_next_transfer & (rom_address == (ROM_SIZE - 1)))
auto_init_complete <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
auto_init_error <= 1'b0;
else if (toggle_next_transfer & ack)
auto_init_error <= 1'b1;
else if (clear_error)
auto_init_error <= 1'b0;
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign toggle_next_transfer = transfer_data & transfer_complete;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> const int N = 29; const int K = 10; const int MOD = 1e9 + 7; int n, m, k; int g[N][N]; int s[N][N][K]; int state[N][N]; int f[N]; bool ch[N]; int fac[N]; int inv[N]; int ans; inline void init() { scanf( %d%d%d , &n, &m, &k); if (n + m - 1 > k) { puts( 0 ); exit(0); } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &g[i][j]); } inline int pow_mod(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % MOD; a = 1ll * a * a % MOD, b >>= 1; } return ret; } inline int P(int n, int m) { return 1ll * fac[n] * inv[n - m] % MOD; } void dfs(int x, int y, int tot, int tot2) { if (tot > k) return; if (y == m + 1) x++, y = 1; if (x == n + 1) { ans = (ans + P(k - tot2, tot - tot2)) % MOD; return; } state[x][y] = state[x - 1][y] | state[x][y - 1]; if (g[x][y]) { if (f[g[x][y]]) { if (((state[x][y] >> (f[g[x][y]] - 1)) & 1)) return; state[x][y] ^= (1 << (f[g[x][y]] - 1)); dfs(x, y + 1, tot, tot2); state[x][y] ^= (1 << (f[g[x][y]] - 1)); } else { for (int i = 1; i <= tot + 1; ++i) if (!((state[x][y] >> (i - 1)) & 1) && !ch[i]) { state[x][y] ^= (1 << (i - 1)); f[g[x][y]] = i, ch[i] = true; dfs(x, y + 1, std::max(i, tot), tot2 + 1); f[g[x][y]] = 0, ch[i] = false; state[x][y] ^= (1 << (i - 1)); } } } else { for (int i = 1; i <= tot + 1; ++i) if (!((state[x][y] >> (i - 1)) & 1)) { state[x][y] ^= (1 << (i - 1)); dfs(x, y + 1, std::max(i, tot), tot2); state[x][y] ^= (1 << (i - 1)); } } } inline void solve() { fac[0] = inv[0] = 1; for (int i = 1; i <= k; ++i) { fac[i] = 1ll * fac[i - 1] * i % MOD; inv[i] = 1ll * inv[i - 1] * pow_mod(i, MOD - 2) % MOD; } memset(s, 0, sizeof s); dfs(1, 1, 0, 0); std::cout << ans << std::endl; } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const float pi = acos(-1.0); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) { long long int n; cin >> n; cout << 0 << << 0 << << n; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_TB_V
`define SKY130_FD_SC_LP__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_TB_V
|
#include <bits/stdc++.h> using namespace std; typedef struct trie { char c; bool win, lose; struct trie *alphabet[26]; } trie; void addString(trie *T, char *s); trie *initTrie(char c); void dfs(trie *T); int main() { int i, n, k; char s[100005]; trie *T = initTrie( 0 ); scanf( %d%d , &n, &k); for (i = 0; i < n; i++) { scanf( %s , s); addString(T, s); } dfs(T); if (!(T->win)) printf( Second n ); else if (T->win && T->lose) printf( First n ); else if (T->win && !(T->lose)) { if (k % 2) printf( First n ); else printf( Second n ); } return 0; } void dfs(trie *T) { int i, flag = 1; for (i = 0; i < 26; i++) { if (T->alphabet[i]) { flag = 0; dfs(T->alphabet[i]); T->win |= !(T->alphabet[i]->win); T->lose |= !(T->alphabet[i]->lose); } } if (flag) { T->win = false; T->lose = true; } } trie *initTrie(char c) { int i; trie *T = (trie *)malloc(sizeof(trie)); T->win = T->lose = false; T->c = c; for (i = 0; i < 26; i++) T->alphabet[i] = NULL; return T; } void addString(trie *T, char *s) { int len = strlen(s), i; for (i = 0; i < len; i++) { if (T->alphabet[s[i] - a ] == NULL) T->alphabet[s[i] - a ] = initTrie(s[i]); T = T->alphabet[s[i] - a ]; } }
|
(* *********************************************************************)
(* *)
(* The Compcert verified compiler *)
(* *)
(* Xavier Leroy, INRIA Paris-Rocquencourt *)
(* *)
(* Copyright Institut National de Recherche en Informatique et en *)
(* Automatique. All rights reserved. This file is distributed *)
(* under the terms of the INRIA Non-Commercial License Agreement. *)
(* *)
(* *********************************************************************)
(** Bounded and unbounded iterators *)
Require Import Axioms.
Require Import Coqlib.
Require Import Wfsimpl.
(** This modules defines several Coq encodings of a general "while" loop.
The loop is presented in functional style as the iteration
of a [step] function of type [A -> B + A]:
<<
let rec iterate step a =
match step a with
| inl b -> b
| inr a' -> iterate step a'
>>
This iteration cannot be defined directly in Coq using [Fixpoint],
because Coq is a logic of total functions, and therefore we must
guarantee termination of the loop.
*)
(** * Terminating iteration *)
(** We first implement the case where termination is guaranteed because
the current state [a] decreases at each iteration. *)
Module WfIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Variable ord: A -> A -> Prop.
Hypothesis ord_wf: well_founded ord.
Hypothesis step_decr: forall a a', step a = inr _ a' -> ord a' a.
Definition step_info (a: A) : {b | step a = inl _ b} + {a' | step a = inr _ a' & ord a' a}.
Proof.
caseEq (step a); intros. left; exists b; auto. right; exists a0; auto.
Defined.
Definition iterate_F (a: A) (rec: forall a', ord a' a -> B) : B :=
match step_info a with
| inl (exist b P) => b
| inr (exist2 a' P Q) => rec a' Q
end.
Definition iterate (a: A) : B := Fix ord_wf iterate_F a.
(** We now prove an invariance property [iterate_prop], similar to the Hoare
logic rule for "while" loops. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iterate_prop:
forall a, P a -> Q (iterate a).
Proof.
intros a0. pattern a0. apply well_founded_ind with (R := ord). auto.
intros. unfold iterate; rewrite unroll_Fix. unfold iterate_F.
destruct (step_info x) as [[b U] | [a' U V]].
exploit step_prop; eauto. rewrite U; auto.
apply H. auto. exploit step_prop; eauto. rewrite U; auto.
Qed.
End ITERATION.
End WfIter.
(** * Bounded iteration *)
(** The presentation of iteration shown above is predicated on the existence
of a well-founded ordering that decreases at each step of the iteration.
In several parts of the CompCert development, it is very painful to define
such a well-founded ordering and to prove decrease, even though we know our
iterations always terminate.
In the presentation below, we choose instead to bound the number of iterations
by an arbitrary constant. [iterate] then becomes a function that can fail,
of type [A -> option B]. The [None] result denotes failure to reach
a result in the number of iterations prescribed, or, in other terms,
failure to find a solution to the dataflow problem. The compiler
passes that exploit dataflow analysis (the [Constprop], [CSE] and
[Allocation] passes) will, in this case, either fail ([Allocation])
or turn off the optimization pass ([Constprop] and [CSE]).
Since we know (informally) that our computations terminate, we can
take a very large constant as the maximal number of iterations.
Failure will therefore never happen in practice, but of
course our proofs also cover the failure case and show that
nothing bad happens in this hypothetical case either. *)
Module PrimIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Definition num_iterations := 1000000000000%positive.
(** The simple definition of bounded iteration is:
<<
Fixpoint iterate (niter: nat) (a: A) {struct niter} : option B :=
match niter with
| O => None
| S niter' =>
match step a with
| inl b => b
| inr a' => iterate niter' a'
end
end.
>>
This function is structural recursive over the parameter [niter]
(number of iterations), represented here as a Peano integer (type [nat]).
However, we want to use very large values of [niter]. As Peano integers,
these values would be much too large to fit in memory. Therefore,
we must express iteration counts as a binary integer (type [positive]).
However, Peano induction over type [positive] is not structural recursion,
so we cannot define [iterate] as a Coq fixpoint and must use
Noetherian recursion instead. *)
Definition iter_step (x: positive)
(next: forall y, Plt y x -> A -> option B)
(s: A) : option B :=
match peq x xH with
| left EQ => None
| right NOTEQ =>
match step s with
| inl res => Some res
| inr s' => next (Ppred x) (Ppred_Plt x NOTEQ) s'
end
end.
Definition iter: positive -> A -> option B := Fix Plt_wf iter_step.
(** The [iterate] function is defined as [iter] up to
[num_iterations] through the loop. *)
Definition iterate := iter num_iterations.
(** We now prove the invariance property [iterate_prop]. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iter_prop:
forall n a b, P a -> iter n a = Some b -> Q b.
Proof.
apply (well_founded_ind Plt_wf
(fun p => forall a b, P a -> iter p a = Some b -> Q b)).
intros. unfold iter in H1. rewrite unroll_Fix in H1. unfold iter_step in H1.
destruct (peq x 1). discriminate.
specialize (step_prop a H0).
destruct (step a) as [b'|a'] eqn:?.
inv H1. auto.
apply H with (Ppred x) a'. apply Ppred_Plt; auto. auto. auto.
Qed.
Lemma iterate_prop:
forall a b, iterate a = Some b -> P a -> Q b.
Proof.
intros. apply iter_prop with num_iterations a; assumption.
Qed.
End ITERATION.
End PrimIter.
(** * General iteration *)
(* An implementation using classical logic and unbounded iteration,
in the style of Yves Bertot's paper, "Extending the Calculus
of Constructions with Tarski's fix-point theorem".
As in the bounded case, the [iterate] function returns an option type.
[None] means that iteration does not terminate.
[Some b] means that iteration terminates with the result [b]. *)
Require Import Classical.
Require Import ClassicalDescription.
Require Import Max.
Module GenIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Definition B_le (x y: option B) : Prop := x = None \/ y = x.
Definition F_le (x y: A -> option B) : Prop := forall a, B_le (x a) (y a).
Definition F_iter (next: A -> option B) (a: A) : option B :=
match step a with
| inl b => Some b
| inr a' => next a'
end.
Lemma F_iter_monot:
forall f g, F_le f g -> F_le (F_iter f) (F_iter g).
Proof.
intros; red; intros. unfold F_iter.
destruct (step a) as [b | a']. red; auto. apply H.
Qed.
Fixpoint iter (n: nat) : A -> option B :=
match n with
| O => (fun a => None)
| S m => F_iter (iter m)
end.
Lemma iter_monot:
forall p q, (p <= q)%nat -> F_le (iter p) (iter q).
Proof.
induction p; intros.
simpl. red; intros; red; auto.
destruct q. elimtype False; omega.
simpl. apply F_iter_monot. apply IHp. omega.
Qed.
Lemma iter_either:
forall a,
(exists n, exists b, iter n a = Some b) \/
(forall n, iter n a = None).
Proof.
intro a. elim (classic (forall n, iter n a = None)); intro.
right; assumption.
left. generalize (not_all_ex_not nat (fun n => iter n a = None) H).
intros [n D]. exists n. generalize D.
case (iter n a); intros. exists b; auto. congruence.
Qed.
Definition converges_to (a: A) (b: option B) : Prop :=
exists n, forall m, (n <= m)%nat -> iter m a = b.
Lemma converges_to_Some:
forall a n b, iter n a = Some b -> converges_to a (Some b).
Proof.
intros. exists n. intros.
assert (B_le (iter n a) (iter m a)). apply iter_monot. auto.
elim H1; intro; congruence.
Qed.
Lemma converges_to_exists:
forall a, exists b, converges_to a b.
Proof.
intros. elim (iter_either a).
intros [n [b EQ]]. exists (Some b). apply converges_to_Some with n. assumption.
intro. exists (@None B). exists O. intros. auto.
Qed.
Lemma converges_to_unique:
forall a b, converges_to a b -> forall b', converges_to a b' -> b = b'.
Proof.
intros a b [n C] b' [n' C'].
rewrite <- (C (max n n')). rewrite <- (C' (max n n')). auto.
apply le_max_r. apply le_max_l.
Qed.
Lemma converges_to_exists_uniquely:
forall a, exists! b, converges_to a b .
Proof.
intro. destruct (converges_to_exists a) as [b CT].
exists b. split. assumption. exact (converges_to_unique _ _ CT).
Qed.
Definition iterate (a: A) : option B :=
proj1_sig (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)).
Lemma converges_to_iterate:
forall a b, converges_to a b -> iterate a = b.
Proof.
intros. unfold iterate.
destruct (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)) as [b' P].
simpl. apply converges_to_unique with a; auto.
Qed.
Lemma iterate_converges_to:
forall a, converges_to a (iterate a).
Proof.
intros. unfold iterate.
destruct (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)) as [b' P].
simpl; auto.
Qed.
(** Invariance property. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iter_prop:
forall n a b, P a -> iter n a = Some b -> Q b.
Proof.
induction n; intros until b; intro H; simpl.
congruence.
unfold F_iter. generalize (step_prop a H).
case (step a); intros. congruence.
apply IHn with a0; auto.
Qed.
Lemma iterate_prop:
forall a b, iterate a = Some b -> P a -> Q b.
Proof.
intros. destruct (iterate_converges_to a) as [n IT].
rewrite H in IT. apply iter_prop with n a. auto. apply IT. auto.
Qed.
End ITERATION.
End GenIter.
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (b != 0) { long long c = a % b; a = b; b = c; } return a; } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } bool C() { long long n, k; cin >> n >> k; long long lcmk = 1; for (long long i = 1; i <= k; ++i) { lcmk = lcm(lcmk, i); if (lcmk > n + 1) return false; } if ((n + 1) % lcmk == 0) return true; else return false; } int main() { if (C()) cout << Yes ; else cout << No ; return 0; }
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_wakeup_cell.v
//
// *Module Description:
// Generic Wakeup cell
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_wakeup_cell (
// OUTPUTs
wkup_out, // Wakup signal (asynchronous)
// INPUTs
scan_clk, // Scan clock
scan_mode, // Scan mode
scan_rst, // Scan reset
wkup_clear, // Glitch free wakeup event clear
wkup_event // Glitch free asynchronous wakeup event
);
// OUTPUTs
//=========
output wkup_out; // Wakup signal (asynchronous)
// INPUTs
//=========
input scan_clk; // Scan clock
input scan_mode; // Scan mode
input scan_rst; // Scan reset
input wkup_clear; // Glitch free wakeup event clear
input wkup_event; // Glitch free asynchronous wakeup event
//=============================================================================
// 1) AND GATE
//=============================================================================
// Scan stuff for the ASIC mode
`ifdef ASIC
wire wkup_rst;
omsp_scan_mux scan_mux_rst (
.scan_mode (scan_mode),
.data_in_scan (scan_rst),
.data_in_func (wkup_clear),
.data_out (wkup_rst)
);
wire wkup_clk;
omsp_scan_mux scan_mux_clk (
.scan_mode (scan_mode),
.data_in_scan (scan_clk),
.data_in_func (wkup_event),
.data_out (wkup_clk)
);
`else
wire wkup_rst = wkup_clear;
wire wkup_clk = wkup_event;
`endif
// Wakeup capture
reg wkup_out;
always @(posedge wkup_clk or posedge wkup_rst)
if (wkup_rst) wkup_out <= 1'b0;
else wkup_out <= 1'b1;
endmodule // omsp_wakeup_cell
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
#include <bits/stdc++.h> using namespace std; int arr[200005]; int ans[200005]; int n, m; bool vis[200005]; int s = 0, e = -1; int main() { scanf( %d %d , &n, &m); vector<pair<int, int> > q(m); for (int i = 0; i < n; ++i) scanf( %d , arr + i); for (int i = 0; i < m; ++i) scanf( %d %d , &q[i].first, &q[i].second); int b = -1; for (int i = m - 1; i >= 0; --i) { if (b >= q[i].second) vis[i] = 1; b = max(b, q[i].second); } int i; bool r = 0; for (i = 0; i < m; ++i) { if (!vis[i]) { sort(arr, arr + q[i].second); if (q[i].first == 1) { s = 0, e = q[i].second - 1; } else { s = 0, e = q[i].second - 1, r = 1; } for (int j = q[i].second; j < n; ++j) ans[j] = arr[j]; break; } } for (; i < m; ++i) { if (vis[i]) continue; if (r) { while (e - s + 1 > q[i].second) { ans[e - s] = arr[s]; ++s; } } else { while (e - s + 1 > q[i].second) { ans[e - s] = arr[e]; --e; } } if (q[i].first == 1) { ans[e - s] = arr[e]; --e; r = 0; } else { ans[e - s] = arr[s]; ++s; r = 1; } } if (r) { while (e >= s) { ans[e - s] = arr[s]; ++s; } } else { while (e >= s) { ans[e - s] = arr[e]; --e; } } for (int i = 0; i < n; ++i) printf( %d , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T t) { return t < 0 ? -t : t; } const long long modn = 1000000007; inline long long mod(long long x) { return x % modn; } const int MAXN = 312345; int n, m; vector<long long> s[4]; struct pd { long long x; int i[3]; pd(long long xx, int ii, int iii) { x = xx; i[1] = ii; i[2] = iii; } pd() {} bool operator<(const struct pd &o) const { return (x < o.x || (x == o.x && i[1] < o.i[1])); } } dp[MAXN]; bool cmp(int a, int b) { return a > b; } int main() { scanf( %d %d , &n, &m); long long res = 0; for (int a = 0; a < n; a++) { long long w, val; scanf( %lld %lld , &w, &val); s[w].push_back(val); if (w == 3) res += val; } for (int i = 1; i <= 3; i++) sort(s[i].begin(), s[i].end(), cmp); dp[0] = (pd){0, 0, 0}; for (int i = 0; i < m; i++) { dp[i + 1] = max(dp[i], dp[i + 1]); if (dp[i].i[1] != s[1].size()) dp[i + 1] = max(dp[i + 1], pd(dp[i].x + s[1][dp[i].i[1]], dp[i].i[1] + 1, dp[i].i[2])); if (dp[i].i[2] != s[2].size()) dp[i + 2] = max(dp[i + 2], pd(dp[i].x + s[2][dp[i].i[2]], dp[i].i[1], dp[i].i[2] + 1)); ; } int i = 0, j = 0; long long ans = 0; for (int k = s[3].size(); k >= 0; k--) { if (m < 3 * k) { if (k > 0) { res -= s[3][k - 1]; } continue; } int sob = m - 3 * k; ans = max(ans, res + dp[sob].x); if (k > 0) res -= s[3][k - 1]; } printf( %lld n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__AND4B_PP_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; long long x[maxn], y[maxn]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long s = 0, sx = 0, sy = 0; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; sx += x[i]; sy += y[i]; s += (n - 1) * (x[i] * x[i]) + (n - 1) * (y[i] * y[i]); } for (int i = 0; i < n; i++) { s -= ((x[i] * (sx - x[i])) + (y[i] * (sy - y[i]))); } cout << s; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:10240000 ) using namespace std; const int MAXN = 100010; int a[MAXN], cnt[MAXN]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } memset(cnt, 0, sizeof(cnt)); int sta = 1, num = 0; while (num < k) { if (cnt[a[sta]] == 0) { num++; } cnt[a[sta]]++; sta++; if (sta > n) { break; } } if (num < k) { printf( -1 -1 n ); } else { int old = 1, l = 1, r = sta - 1; int m = r - l + 1; for (int i = sta; i <= n; i++) { int j = old + 1; cnt[a[old]]--; if (j < i) { while (a[j] == a[old]) { cnt[a[old]]--; j++; if (j == i) { break; } } } if (cnt[a[old]] == 0) { num--; } old = j; j = i; while (num < k) { if (cnt[a[j]] == 0) { num++; } cnt[a[j]]++; j++; if (j > n) { break; } } if (num < k) { break; } i = j - 1; int tmp = i - old + 1; if (tmp < m) { m = tmp; l = old; r = i; } } memset(cnt, 0, sizeof(cnt)); for (int i = l; i <= r; i++) { cnt[a[i]]++; } while (cnt[a[l]] > 1) { cnt[a[l]]--; l++; } printf( %d %d n , l, r); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string second, a = 1968 ; string rem[10]; cin >> second; int zero = 0; bool one = 0, six = 0, eight = 0, nine = 0; string alt = ; for (int i = 0; i < second.size(); i++) { if (second[i] == 0 ) zero++; if (second[i] == 1 && one) alt += second[i]; if (second[i] == 6 && six) alt += second[i]; if (second[i] == 8 && eight) alt += second[i]; if (second[i] == 9 && nine) alt += second[i]; if (second[i] == 1 ) one = 1; else if (second[i] == 6 ) six = 1; else if (second[i] == 8 ) eight = 1; else if (second[i] == 9 ) nine = 1; else if (second[i] != 0 ) alt += second[i]; } int t = 1, mo = 0; for (int i = 0; i < zero; i++) { t = (t * 10) % 7; } int ft = t; do { int m = 0; t = ft; for (int i = 4 - 1; i >= 0; i--) { m = (m + t * (a[i] - 0 )) % 7; t = (t * 10) % 7; } rem[m] = a; } while (next_permutation(a.begin(), a.end())); for (int i = alt.size() - 1; i >= 0; i--) { mo = (mo + (alt[i] - 0 ) * t) % 7; t = (t * 10) % 7; } rem[7] = rem[0]; cout << alt << rem[7 - mo]; for (int i = 0; i < zero; i++) cout << 0; return 0; }
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
/*
* Wishbone 2 port multiplexer
*/
module wb_mux_2 #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire rst,
/*
* Wishbone master input
*/
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
/*
* Wishbone slave 0 output
*/
output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
output wire wbs0_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
output wire wbs0_stb_o, // STB_O strobe output
input wire wbs0_ack_i, // ACK_I acknowledge input
input wire wbs0_err_i, // ERR_I error input
input wire wbs0_rty_i, // RTY_I retry input
output wire wbs0_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 0 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
/*
* Wishbone slave 1 output
*/
output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
output wire wbs1_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
output wire wbs1_stb_o, // STB_O strobe output
input wire wbs1_ack_i, // ACK_I acknowledge input
input wire wbs1_err_i, // ERR_I error input
input wire wbs1_rty_i, // RTY_I retry input
output wire wbs1_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 1 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs1_addr_msk // Slave address prefix mask
);
wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
wire wbs0_sel = wbs0_match;
wire wbs1_sel = wbs1_match & ~(wbs0_match);
wire master_cycle = wbm_cyc_i & wbm_stb_i;
wire select_error = ~(wbs0_sel | wbs1_sel) & master_cycle;
// master
assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
wbs1_sel ? wbs1_dat_i :
{DATA_WIDTH{1'b0}};
assign wbm_ack_o = wbs0_ack_i |
wbs1_ack_i;
assign wbm_err_o = wbs0_err_i |
wbs1_err_i |
select_error;
assign wbm_rty_o = wbs0_rty_i |
wbs1_rty_i;
// slave 0
assign wbs0_adr_o = wbm_adr_i;
assign wbs0_dat_o = wbm_dat_i;
assign wbs0_we_o = wbm_we_i & wbs0_sel;
assign wbs0_sel_o = wbm_sel_i;
assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
// slave 1
assign wbs1_adr_o = wbm_adr_i;
assign wbs1_dat_o = wbm_dat_i;
assign wbs1_we_o = wbm_we_i & wbs1_sel;
assign wbs1_sel_o = wbm_sel_i;
assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[109], d; void nhap() { scanf( %d n , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); } void qs(int l, int r) { int x = a[(l + r) / 2]; int i = l; int j = r; while (i <= j) { while (a[i] < x) i++; while (a[j] > x) j--; if (i <= j) { int tmp = a[i]; a[i] = a[j]; a[j] = tmp; i++; j--; } } if (i < r) qs(i, r); if (j > l) qs(l, j); } void xuli() { qs(1, n); for (int i = 2; i <= n; i += 2) { int s = a[i] - a[i - 1]; if (s != 0) d = d + s; } printf( %d , d); } int main() { nhap(); xuli(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_2_V
`define SKY130_FD_SC_HS__OR4_2_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_2_V
|
#include<bits/stdc++.h> typedef long long int ll; typedef long double ld; typedef std::vector<ll> vi; typedef std::vector<std::vector<ll> > vv; typedef std::vector<std::pair<ll,ll> > pii; #define mod 1000000007 #define IO ios_base::sync_with_stdio(false);cin.tie(NULL); #define fo(i,a,b) for(i=a;i<b;i++) #define forr(i,a,b) for(i=a;i>=b;i--) #define mp make_pair #define pb(x) push_back(x) #define fi first #define se second #define print(vec,a,b) for(ll i=a;i<b;i++) cout<<vec[i]<< ;cout<<endl; #define all(a) a.begin(),a.end() #define input(vec,a,b) for(ll i = a;i<b;i++) cin>>vec[i]; #define ms(a,val) memset(a,val,sizeof(a)) using namespace std; const int N = 2e5+ 5; ll expo_pow(ll x, ll y) { if (y == 0) return 1; y = y % (mod - 1); x %= mod; if (y == 0) y = mod - 1; ll res = 1; while (y) { if (y & 1) res = (res * x) % mod; x = (x * x) % mod; y >>= 1; } return res; } ll modInverse(ll a, ll m = mod) { return expo_pow(a, m - 2); } void solve(){ ll i,j,n,m; ll a,b,d; cin>>a>>b>>d; if(a > b) { if((1 + d)*b >= a) cout<< YES <<endl; else cout<< NO <<endl; } else if(b > a) { if((1 + d)*a >= b) cout<< YES <<endl; else cout<< NO <<endl; } else cout<< YES <<endl; } int main() { IO; ll t=1,i; cin>>t; while(t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long n, w; cin >> n >> w; vector<long long> arr(n); for (long long i = 0; i < n; ++i) cin >> arr[i]; vector<long long> runsum(n); long long min_elem = arr[0]; long long max_elem = arr[0]; vector<long long> run(n); long long cur = 0; long long tillnow = -1e9; for (long long i = 0; i < n; ++i) { cur = max(arr[i], cur + arr[i]); tillnow = max(tillnow, cur); } if (tillnow > w) { cout << 0 << endl; return 0; } max_elem = tillnow; cur = 0; tillnow = 1e9; for (long long i = 0; i < n; ++i) { cur = min(arr[i], cur + arr[i]); tillnow = min(tillnow, cur); } if (tillnow < -w) { cout << 0 << endl; return 0; } min_elem = tillnow; long long answer = w - max(abs(max_elem), abs(min_elem)) + 1; cout << answer << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[2][100010]; long long MOD = 1000000007; int main() { string s1, s2; int k; while (cin >> s1 >> s2 >> k) { s1 = s1 + s1; int cntS = 0, cntD = 0; for (int i = 0; i < s2.size(); ++i) if (s1.substr(i, s2.size()) == s2) cntS++; else cntD++; if (s1.substr(0, s2.size()) == s2) dp[0][0] = 1, dp[1][0] = 0; else dp[0][0] = 0, dp[1][0] = 1; for (int i = 1; i <= k; ++i) { dp[0][i] = dp[0][i - 1] * (cntS - 1) + dp[1][i - 1] * (cntS); dp[1][i] = dp[0][i - 1] * (cntD) + dp[1][i - 1] * (cntD - 1); dp[0][i] %= MOD; dp[1][i] %= MOD; } cout << dp[0][k] << endl; } return 0; }
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_watchdog.v
//
// *Module Description:
// Watchdog Timer
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_watchdog (
// OUTPUTs
nmi_evt, // NMI Event
per_dout, // Peripheral data output
wdtifg_set, // Set Watchdog-timer interrupt flag
wdtpw_error, // Watchdog-timer password error
wdttmsel, // Watchdog-timer mode select
// INPUTs
aclk_en, // ACLK enable
dbg_freeze, // Freeze Watchdog counter
mclk, // Main system clock
nmi, // Non-maskable interrupt (asynchronous)
nmie, // Non-maskable interrupt enable
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
puc, // Main system reset
smclk_en, // SMCLK enable
wdtie // Watchdog timer interrupt enable
);
// OUTPUTs
//=========
output nmi_evt; // NMI Event
output [15:0] per_dout; // Peripheral data output
output wdtifg_set; // Set Watchdog-timer interrupt flag
output wdtpw_error; // Watchdog-timer password error
output wdttmsel; // Watchdog-timer mode select
// INPUTs
//=========
input aclk_en; // ACLK enable
input dbg_freeze; // Freeze Watchdog counter
input mclk; // Main system clock
input nmi; // Non-maskable interrupt (asynchronous)
input nmie; // Non-maskable interrupt enable
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input puc; // Main system reset
input smclk_en; // SMCLK enable
input wdtie; // Watchdog timer interrupt enable
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register addresses
parameter WDTCTL = 9'h120;
// Register one-hot decoder
parameter WDTCTL_D = (512'h1 << WDTCTL);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Register address decode
reg [511:0] reg_dec;
always @(per_addr)
case ({per_addr,1'b0})
WDTCTL : reg_dec = WDTCTL_D;
default: reg_dec = {512{1'b0}};
endcase
// Read/Write probes
wire reg_write = |per_wen & per_en;
wire reg_read = ~|per_wen & per_en;
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
wire [511:0] reg_rd = reg_dec & {512{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// WDTCTL Register
//-----------------
// WDTNMI & WDTSSEL are not implemented and therefore masked
reg [7:0] wdtctl;
wire wdtctl_wr = reg_wr[WDTCTL];
always @ (posedge mclk or posedge puc)
if (puc) wdtctl <= 8'h00;
else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7;
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire wdttmsel = wdtctl[4];
//============================================================================
// 3) REGISTERS
//============================================================================
// Data output mux
wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}};
wire [15:0] per_dout = wdtctl_rd;
//=============================================================================
// 4) NMI GENERATION
//=============================================================================
// Synchronization state
reg [2:0] nmi_sync;
always @ (posedge mclk or posedge puc)
if (puc) nmi_sync <= 3'h0;
else nmi_sync <= {nmi_sync[1:0], nmi};
// Edge detection
wire nmi_re = ~nmi_sync[2] & nmi_sync[0] & nmie;
wire nmi_fe = nmi_sync[2] & ~nmi_sync[0] & nmie;
// NMI event
wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
//=============================================================================
// 5) WATCHDOG TIMER
//=============================================================================
// Watchdog clock source selection
//---------------------------------
wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
// Watchdog 16 bit counter
//--------------------------
reg [15:0] wdtcnt;
wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
always @ (posedge mclk or posedge puc)
if (puc) wdtcnt <= 16'h0000;
else if (wdtcnt_clr) wdtcnt <= 16'h0000;
else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
// Interval selection mux
//--------------------------
reg wdtqn;
always @(wdtctl or wdtcnt)
case(wdtctl[1:0])
2'b00 : wdtqn = wdtcnt[15];
2'b01 : wdtqn = wdtcnt[13];
2'b10 : wdtqn = wdtcnt[9];
default: wdtqn = wdtcnt[6];
endcase
// Watchdog event detection
//-----------------------------
reg wdtqn_dly;
always @ (posedge mclk or posedge puc)
if (puc) wdtqn_dly <= 1'b0;
else wdtqn_dly <= wdtqn;
wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error;
endmodule // omsp_watchdog
`include "openMSP430_undefines.v"
|
#include <bits/stdc++.h> int main() { char s[105]; int i, n, j; scanf( %d , &n); getchar(); for (i = 0; i < n; i++) { scanf( %c , &s[i]); } for (i = 0; i < n; i++) { if (s[i] == o && s[i + 1] == g && s[i + 2] == o ) { printf( *** ); for (j = i + 3; j < n; j += 2) { if (s[j] == g && s[j + 1] == o ) { continue; } else { break; } } i = j - 1; } else printf( %c , s[i]); } printf( n ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> int n, i; char s[100005]; long long a[270], r; int main() { scanf( %s , s); n = strlen(s); for (i = 0; i < n; i++) a[s[i]]++; for (i = 0; i < 270; i++) r += a[i] * a[i]; printf( %I64d n , r); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1001; const int M = 300000; int n, m, a[N], b[N]; vector<bool> g[M]; pair<int, int> p[N]; priority_queue<pair<int, int> > q; bool solve(int x) { if (x == 0) return true; for (int i = 1; i <= n; i++) b[i] = a[i] - x; int sum = 0; for (int i = 1; i <= n; i++) sum += b[i]; sort(b + 1, b + n + 1); reverse(b + 1, b + n + 1); if (sum & 1) { b[1]--; b[2]--; b[3]--; } sort(b + 1, b + n + 1); reverse(b + 1, b + n + 1); if (b[n] < 0) return false; for (int i = 1; i <= n; i++) if (b[i] > 0) q.push(make_pair(b[i], i)); while (!q.empty()) { pair<int, int> v = q.top(); q.pop(); if (q.empty()) return false; pair<int, int> u = q.top(); q.pop(); v.first--; u.first--; if (v.first > 0) q.push(v); if (u.first > 0) q.push(u); } return true; } void getSolution(int x) { if (x == 0) { m = 0; for (int i = 1; i < n; i++) { for (int j = 1; j <= 100; j++) { m++; for (int k = 1; k <= n; k++) if (k == i || k == i + 1) g[m][k - 1] = true; else g[m][k - 1] = false; } } return; } for (int i = 1; i <= n; i++) b[i] = a[i] - x; for (int i = 1; i <= n; i++) if (b[i] > 0) q.push(make_pair(b[i], i)); int sum = 0; for (int i = 1; i <= n; i++) sum += b[i]; int game = 0; while (!q.empty()) { game++; if (sum & 1) { pair<int, int> a = q.top(); q.pop(); if (q.empty()) assert(false); pair<int, int> b = q.top(); q.pop(); if (q.empty()) assert(false); pair<int, int> c = q.top(); q.pop(); for (int j = 1; j <= n; j++) if (j == a.second || j == b.second || j == c.second) g[game][j - 1] = true; else g[game][j - 1] = false; a.first--; b.first--; c.first--; if (a.first > 0) q.push(a); if (b.first > 0) q.push(b); if (c.first > 0) q.push(c); sum -= 3; } else { pair<int, int> a = q.top(); q.pop(); if (q.empty()) assert(false); pair<int, int> b = q.top(); q.pop(); for (int j = 1; j <= n; j++) if (j == a.second || j == b.second) g[game][j - 1] = true; else g[game][j - 1] = false; a.first--; b.first--; if (a.first > 0) q.push(a); if (b.first > 0) q.push(b); } } m = game; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int minval = a[1]; for (int i = 2; i <= n; i++) minval = min(minval, a[i]); for (int i = 1; i <= 10000; i++) g[i].resize(n); int ans = 0; for (int i = minval; i >= 0; i--) if (solve(i)) { ans = i; break; } cout << ans << endl; getSolution(ans); cout << m << endl; for (int i = 1; i <= m; i++) { for (int j = 0; j < g[i].size(); j++) cout << g[i][j]; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using lli = long long; using lld = long double; using ulli = unsigned long long int; using pll = pair<lli, lli>; using ttt = pair<lli, pll>; using vttt = vector<ttt>; using vll = vector<pll>; using vl = vector<lli>; using vi = vector<int>; using vvi = vector<vector<int>>; using cd = complex<lld>; const double PI = acos(-1); vvi adj, dist; pll get(vi vect) { cout << ? << ((lli)(vect).size()); for (auto& x : vect) cout << << x; cout << n ; cout.flush(); pll ans; cin >> ans.first >> ans.second; return ans; } void dfs(int v, int p, int dis) { dist[dis].push_back(v); for (auto& x : adj[v]) if (x != p) { dfs(x, v, dis + 1); } } pll check(int val) { if (dist[val].empty()) return {1000000007, 1000000007}; return get(dist[val]); } int tejas_919(int kkkk) { lli n, m, k, q, u, v, temp = 0, ans = 0; cin >> n; adj = vvi(n + 2); dist = vvi(n + 2); for (int i = 1; i < n; i++) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } int root, pdist; { vi vect; for (int i = 1; i < n + 1; i++) vect.push_back(i); tie(root, pdist) = get(vect); } dfs(root, root, 0); int l = (pdist + 1) / 2, r = pdist, cdis; root = -1; while (l <= r) { int mid = (l + r) / 2; tie(temp, cdis) = check(mid); if (cdis == pdist) { l = mid + 1; root = temp; } else r = mid - 1; } if (root < 0) root = get(dist[l - 1]).first; dist = vvi(n + 2); dfs(root, root, 0); ans = get(dist[pdist]).first; cout << ! << root << << ans << n ; cout.flush(); string s; cin >> s; return 0; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(10); int t = 1; cin >> t; for (int i = 0; i < t; i++) { tejas_919(i + 1); } {}; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_pwrgood_pp$P (
UDP_OUT,
UDP_IN ,
VPWR
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_PP_SYMBOL_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
input sys_clk,
input sdram_rst,
input tim_cas,
input [1:0] tim_wr,
input read,
input write,
output reg precharge_safe
);
reg [3:0] counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter <= 4'd0;
precharge_safe <= 1'b1;
end else begin
if(read) begin
/* see p.26 of datasheet :
* "A Read burst may be followed by, or truncated with, a Precharge command
* to the same bank. The Precharge command should be issued x cycles after
* the Read command, where x equals the number of desired data element
* pairs"
*/
counter <= 4'd8;
precharge_safe <= 1'b0;
end else if(write) begin
counter <= {2'b10, tim_wr};
precharge_safe <= 1'b0;
end else begin
if(counter == 4'b1)
precharge_safe <= 1'b1;
if(~precharge_safe)
counter <= counter - 4'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string a, b; int nex[1000006], f1[1000006], f2[1000006]; long long xa[1000006], xb[1000006], mu[1000006]; const long long base = 1000000007; int main() { getline(cin, a); getline(cin, b); if (a.length() != b.length()) { cout << -1 -1 ; return 0; } int n = a.length(); nex[n - 1] = n; for (int i = n - 2; i >= 0; i--) { int j = nex[i + 1]; while (j < n && a[j - 1] != a[i]) j = nex[j]; if (j - 1 >= 0 && a[i] == a[j - 1]) nex[i] = j - 1; else nex[i] = j; } int j = n; for (int i = 0; i <= n - 1; i++) { while (j < n && b[i] != a[j - 1]) j = nex[j]; if (j - 1 >= 0 && b[i] == a[j - 1]) j--; f1[i] = j; } mu[0] = 1; for (int i = 1; i <= n; i++) mu[i] = (mu[i - 1] * 95) % base; xa[0] = a[0] - 32; for (int i = 1; i <= n - 1; i++) xa[i] = (xa[i - 1] + mu[i] * (a[i] - 32)) % base; xb[0] = b[0] - 32; for (int i = 1; i <= n - 1; i++) xb[i] = (xb[i - 1] + mu[i] * (b[i] - 32)) % base; int res1 = -1, res2 = -1; for (int i = 0; i <= n - 2 && a[i] == b[n - i - 1]; i++) { if (a[i] != b[n - i - 1]) break; int j = f1[n - i - 2]; if (j < n && (j == i + 1 || (xa[j - 1] - xa[i] + base) % base == (xb[j - i - 2] * mu[i + 1]) % base)) { res1 = i; res2 = j; } } cout << res1 << << res2; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline , fast-math , unroll-loops , no-stack-protector ) #pragma GCC target( popcnt,tune=native ) using namespace std; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; int f, qr; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char x) { *oS++ = x; if (oS == oT) flush(); } template <class T> inline void getc(T &x) { for (c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); !((c >= 0 && c <= 9 ) || (c >= a && c <= z ) || (c >= A && c <= Z )); c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) ; x = c; } template <class I> inline void rd(I &x) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; for (x = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) x = x * 10 + (c & 15); x *= f; } template <class I> inline void print(I x) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = -x; while (x) qu[++qr] = x % 10 + 0 , x /= 10; while (qr) putc(qu[qr--]); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io ::getc; using io ::print; using io ::putc; using io ::rd; const int MAXN = 100 + 5; const int MOD = 1e9 + 7; int mo(int x, int y) { return (x + y) >= MOD ? (x + y - MOD) : (x + y); } int sub(int x, int y) { return x < y ? (x - y + MOD) : (x - y); } int ksm(int x, int y) { int res = 1; for (; y; y >>= 1, x = 1ll * x * x % MOD) if (y & 1) res = 1ll * res * x % MOD; return res; } void fix(int &x, const int &v) { x = (x + v) >= MOD ? (x + v - MOD) : (x + v); } int n, m; bool vis[MAXN][MAXN]; vector<int> e[MAXN][MAXN]; void add(int x, int y, vector<int> t) { vis[x][y] = 1; e[x][y] = t; } struct Node { vector<int> g[MAXN][MAXN]; vector<int> solvemid() { vector<int> nxt, res, now; for (int x = 1; x <= n; x++) for (int y = 1; y <= n; y++) for (int i = 0; i + 1 < e[x][y].size(); i++) if (e[x][y][i] == x && e[x][y][i + 1] == y) { now.clear(); nxt = e[x][y]; bool flag = 1; do { now = nxt; nxt.clear(); flag = (now.size() <= (2 * n + 1)); for (int i = 0; i + 1 < now.size() && flag; i++) { if (!vis[now[i]][now[i + 1]]) { flag = 0; break; } nxt.insert(nxt.end(), e[now[i]][now[i + 1]].begin(), e[now[i]][now[i + 1]].end()); } } while (flag && now != nxt); if (flag) { if (!res.size()) res = nxt; g[nxt[0]][nxt.back()].push_back(nxt.size() - 1); } break; } return res; } void solvefront() { vector<int> nxt, res, now, Cnt; for (int x = 1; x <= n; x++) for (int y = 1; y <= n; y++) if (e[x][y].size() && e[x][y].back() == x) { now.clear(); nxt.clear(); nxt.push_back(x); bool flag = 1; do { now = nxt; nxt.clear(); flag = (now.size() <= (2 * n + 1)); nxt = e[now[0]][y]; reverse(nxt.begin(), nxt.end()); for (int i = 0; i + 1 < now.size() && flag; i++) { if (!vis[now[i + 1]][now[i]]) { flag = 0; break; } nxt.insert(nxt.end(), e[now[i + 1]][now[i]].rbegin(), e[now[i + 1]][now[i]].rend()); } } while (flag && now != nxt); if (flag) g[nxt.back()][y].push_back(nxt.size()); } } void solveend() { vector<int> nxt, res, now, Cnt; for (int x = 1; x <= n; x++) for (int y = 1; y <= n; y++) if (e[x][y].size() && e[x][y][0] == y) { now.clear(); nxt.clear(); nxt.push_back(y); bool flag = 1; do { now = nxt; nxt.clear(); flag = (now.size() <= (2 * n + 1)); nxt = e[x][now[0]]; for (int i = 0; i + 1 < now.size() && flag; i++) { if (!vis[now[i]][now[i + 1]]) { flag = 0; break; } nxt.insert(nxt.end(), e[now[i]][now[i + 1]].begin(), e[now[i]][now[i + 1]].end()); } } while (flag && now != nxt); if (flag) g[x][nxt.back()].push_back(nxt.size()); } } int dp[MAXN][MAXN][MAXN]; void solveA() { for (int i = 1; i <= n; i++) dp[i][i][0] = 1; for (int i = 0; i <= n * 2; i++) for (int s = 1; s <= n; s++) for (int l = 1; l <= n; l++) for (int r = 1; r <= n; r++) for (auto &len : g[l][r]) if (i + len <= 2 * n + 1) fix(dp[s][r][i + len], dp[s][l][i]); } } A, B, C; int dp[MAXN][MAXN][MAXN], dp0[MAXN][MAXN][MAXN], ans[MAXN][MAXN]; int main() { rd(n); rd(m); for (int i = 1, a, b, K; i <= m; i++) { rd(a); rd(b); rd(K); vector<int> v; v.resize(K); for (int i = 0; i < K; i++) rd(v[i]); add(a, b, v); } A.solvefront(); vector<int> res = B.solvemid(); C.solveend(); A.solveA(); for (int i = 0; i <= n * 2; i++) for (int s = 1; s <= n; s++) for (int l = 1; l <= n; l++) for (int r = 1; r <= n; r++) for (auto &len : B.g[l][r]) if (i + len <= 2 * n) fix(dp[s][r][i + len], A.dp[s][l][i]); for (int i = 0; i <= n * 2; i++) for (int s = 1; s <= n; s++) for (int l = 1; l <= n; l++) for (int r = 1; r <= n; r++) for (auto &len : C.g[l][r]) if (i + len <= 2 * n) fix(dp[s][r][i + len], dp[s][l][i]); for (int l = 1; l <= n; l++) for (int mid = 1; mid <= n; mid++) if (vis[l][mid] && e[l][mid].empty()) for (int r = 1; r <= n; r++) for (int i = 0; i + 1 <= 2 * n; i++) fix(dp0[l][r][i + 1], dp[mid][r][i]); for (int l = 1; l <= n; l++) for (int r = 1; r <= n; r++) for (int len = 1; len <= 2 * n; len++) fix(ans[r][len], dp[l][r][len]); for (int i = 1; i <= 2 * n; i++) for (int l = 1; l <= n; l++) for (int r = 1; r <= n; r++) for (int len = 1; len + i <= 2 * n; len++) fix(ans[r][len + i], 1ll * ans[l][i] * dp0[l][r][len] % MOD); for (int i = 1; i <= 2 * n; i++) { int aa = 0; for (int s = 1; s <= n; s++) fix(aa, ans[s][i]); print(aa); putc( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBP_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_32x24.v,v $
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_4_V
`define SKY130_FD_SC_HS__SEDFXTP_4_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_4_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10, LOG = 23, MAX = 1e6 + 10, M = 1e9 + 7; long long n; long long mark[N], level[N], par[N][LOG + 10], arr[MAX], cnt[N], tavan[MAX]; vector<long long> g[N]; map<pair<long long, long long>, long long> mp; void DFS(long long v) { mark[v] = 1; for (long long u : g[v]) { if (!mark[u]) { level[u] = level[v] + 1; par[u][0] = v; DFS(u); } } } long long DFS2(long long v) { mark[v] = 2; for (long long u : g[v]) { if (mark[u] != 2) cnt[v] += DFS2(u); } return cnt[v]; } long long getpar(long long v, long long dis) { long long cnt = 0; while (dis) { if (dis % 2) v = par[v][cnt]; cnt++; dis /= 2; } return v; } long long MOD(long long a) { return (((a % M) + M) % M); } void UPDATE() { for (long long i = 1; i <= LOG; i++) { for (long long node = 1; node <= n; node++) par[node][i] = par[par[node][i - 1]][i - 1]; } tavan[0] = 1; for (long long i = 1; i < MAX; i++) { tavan[i] = MOD(tavan[i - 1] * 2); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long u, v, x, q, ans = 0; cin >> n; for (long long i = 0; i < n - 1; i++) { cin >> u >> v >> x; mp[{u, v}] = x; g[u].push_back(v); g[v].push_back(u); } DFS(1); UPDATE(); cin >> q; arr[0] = 1; for (long long i = 1; i <= q; i++) { cin >> arr[i]; long long lca; v = arr[i]; u = arr[i - 1]; cnt[u]++; cnt[v]++; if (level[v] < level[u]) swap(v, u); v = getpar(v, level[v] - level[u]); if (v == u) lca = v; else { for (long long j = LOG; j >= 0; j--) { if (par[v][j] != par[u][j]) { v = par[v][j]; u = par[u][j]; } } lca = par[v][0]; } cnt[lca] -= 2; } DFS2(1); for (long long i = 1; i <= n; i++) { v = i; u = par[i][0]; if ((mp.count({v, u}) && mp[{v, u}]) || (mp.count({u, v}) && mp[{u, v}])) { if (cnt[v] % 2 == 0) ans += tavan[cnt[v] / 2] - 1; else { if (mp.count({v, u})) ans += tavan[(cnt[v] + 1) / 2] - 1; else ans += tavan[cnt[v] / 2] - 1; } ans = MOD(ans); } } cout << ans; return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/16.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> m >> n; map<int, vector<pair<int, int>>> matrix; vector<int> cnt(n, m), mag(m, n); int cnt2 = m; for (int i = 0; i < m; ++i) { for (int j = 0; j < n; ++j) { int a; cin >> a; matrix[a].push_back(make_pair(j, i)); } } int ans = -1; for (auto &elem : matrix) { ans = elem.first; bool ok = 1; for (auto &pr : elem.second) { int i = pr.first, j = pr.second; --cnt[i]; --mag[j]; if (cnt[i] == 0) { ok = 0; break; } if (mag[j] == 1) --cnt2; } if (!ok || cnt2 == 0) break; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); srand(time(NULL)); int tt = 1; cin >> tt; while (tt--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 110000; int s1, s2; int n, a[N]; int mi[17][N * 2], ma[17][N * 2]; int BB[N * 2]; int getmi(int l, int r) { return min(mi[BB[r - l + 1]][l], mi[BB[r - l + 1]][r - (1 << BB[r - l + 1]) + 1]); } int getma(int l, int r) { return max(ma[BB[r - l + 1]][l], ma[BB[r - l + 1]][r - (1 << BB[r - l + 1]) + 1]); } void init() { for (int j = (int)0; j <= (int)16; j++) for (int i = (int)(1 << j); i <= (int)(1 << (j + 1)) - 1; i++) BB[i] = j; for (int i = (int)1; i <= (int)n; i++) { mi[0][i] = ma[0][i] = a[i]; } for (int j = (int)1; j <= (int)16; j++) for (int i = (int)1; i <= (int)n - (1 << j) + 1; i++) { mi[j][i] = min(mi[j - 1][i], mi[j - 1][i + (1 << (j - 1))]); ma[j][i] = max(ma[j - 1][i], ma[j - 1][i + (1 << (j - 1))]); } } bool f[N], g[N]; bool check(int S) { for (int i = (int)0; i <= (int)n; i++) f[i] = g[i] = 0; f[0] = g[0] = 1; int maf, mag; maf = mag = 0; for (int i = (int)0; i <= (int)n - 1; i++) { bool f1 = (i <= maf); bool f2 = (i <= mag); if (f1) { int now = a[i]; if (i == 0) now = s1; int l = i + 1; int r = n; int rt = 0; while (l < r) { int mid = (l + r) >> 1; if ((abs(getma(i + 1, mid) - now) > S) || (abs(getmi(i + 1, mid) - now) > S)) r = mid; else l = mid + 1, rt = mid; } if (!(abs((getma(i + 1, l) - now) > S) || (abs(getmi(i + 1, l) - now) > S))) rt = l; mag = max(mag, rt); } if (f2) { int now = a[i]; if (i == 0) now = s2; int l = i + 1; int r = n; int rt = 0; while (l < r) { int mid = (l + r) >> 1; if ((abs(getma(i + 1, mid) - now) > S) || (abs(getmi(i + 1, mid) - now) > S)) r = mid; else l = mid + 1, rt = mid; } if (!((abs(getma(i + 1, l) - now) > S) || (abs(getmi(i + 1, l) - now) > S))) rt = l; maf = max(maf, rt); } } return (maf == n) || (mag == n); } int main() { scanf( %d%d%d , &n, &s1, &s2); for (int i = (int)1; i <= (int)n; i++) scanf( %d , &a[i]); init(); int L = abs(s1 - s2); int R = 1000000000; int ans = 0; while (L < R) { int mid = (L + R) >> 1; if (check(mid)) ans = mid, R = mid; else L = mid + 1; } if (check(L)) ans = L; cout << ans << endl; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate 3.1.2E always reg_lvalue <= # (mintypmax_expression) constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
# 3; /* Wait till here to verify didn't see 2ns delay! */
if(value1 !== 4'hx)
$display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \n");
#12 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 <= # (2:10:17) 4'h5 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; void _fill_int(int* p, int val, int rep) { int i; for (i = 0; i < rep; i++) p[i] = val; } signed long long GETi() { signed long long i; scanf( %lld , &i); return i; } int N, A[100001]; void solve() { int f, i, j, k, l, x, y; cin >> N; for (i = 0; i < N; i++) cin >> A[i]; sort(A, A + N); if (N == 1) return (void)printf( -1 n ); if (A[0] == A[N - 1]) return (void)printf( 1 n%d n , A[0]); if (N == 2 && (A[1] - A[0]) % 2 == 0) return (void)printf( 3 n%d %d %d n , A[0] - (A[1] - A[0]), A[0] + (A[1] - A[0]) / 2, A[1] + (A[1] - A[0])); int mi = A[1] - A[0]; for (i = 0; i < N - 1; i++) mi = min(mi, A[i + 1] - A[i]); x = -1; for (i = 0; i < N - 1; i++) { if (A[i + 1] - A[i] == mi) continue; else if (A[i + 1] - A[i] == 2 * mi && x == -1) x = i; else return (void)printf( 0 n ); } if (x == -1) (void)printf( 2 n%d %d n , A[0] - mi, A[N - 1] + mi); else (void)printf( 1 n%d n , A[x] + mi); } int main(int argc, char** argv) { string s; if (argc == 1) ios::sync_with_stdio(false); for (int i = 1; i < argc; i++) s += argv[i], s += n ; for (int i = s.size() - 1; i >= 0; i--) ungetc(s[i], stdin); solve(); return 0; }
|
#include <bits/stdc++.h> #define maxn 10 using namespace std; int n, m; map<vector<int>, int> f, g; int a[maxn], b[maxn], c[maxn][maxn]; int main(){ scanf( %d%d , &n, &m); vector<int> v; for(int i = 1;i <= n;i++) scanf( %d , &a[i]); for(int i = 1;i <= m;i++) scanf( %d , &b[i]); for(int i = 1;i <= n;i++) for(int j = 1;j <= m;j++) scanf( %d , &c[i][j]); f[vector<int>(n + 1)] = 0; for(int j = 1;j <= m;j++){ for(map<vector<int>, int>::iterator it = f.begin();it != f.end();++it){ vector<int> v = it->first; v[n] = 0; if(g.find(v) == g.end()) g[v] = it->second; else g[v] = min(g[v], it->second); } swap(f, g), g.clear(); for(int i = 1;i <= n;i++){ for(map<vector<int>, int>::iterator it = f.begin();it != f.end();++it){ vector<int> v = it->first; for(int k = 0;k <= min(a[i] - v[i - 1], b[j] - v[n]);k++){ vector<int> w = v; w[i - 1] += k, w[n] += k; if(g.find(w) == g.end()) g[w] = it->second + (k ? c[i][j] : 0); else g[w] = min(g[w], it->second + (k ? c[i][j] : 0)); } } swap(f, g), g.clear(); } } int ans = 1e9; for(map<vector<int>, int>::iterator it = f.begin();it != f.end();++it){ vector<int> v = it->first; bool tag = false; for(int i = 0;i < n;i++){ if(v[i] < a[i + 1]){ tag = true; break; } } if(!tag) ans = min(ans, it->second); } printf( %d , ans == 1e9 ? -1 : ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
|
`default_nettype none
`timescale 1ns / 1ps
// Main board module.
module s6atlys(
// Global clock
input wire CLK_100M,
// onboard HDMI OUT
//output wire HDMIOUTCLKP,
//output wire HDMIOUTCLKN,
//output wire HDMIOUTD0P,
//output wire HDMIOUTD0N,
//output wire HDMIOUTD1P,
//output wire HDMIOUTD1N,
//output wire HDMIOUTD2P,
//output wire HDMIOUTD2N,
//output wire HDMIOUTSCL,
//output wire HDMIOUTSDA,
// LEDs
output wire [7:0] LED,
// Switches
input wire [7:0] SW,
// Buttons
input wire [5:0] BTN,
// PMOD Connector
inout wire [7:0] JB
);
//
// Initialize outputs -- remove these when they're actually used
//
// Audio output
//assign AUD_L = 0;
//assign AUD_R = 0;
// VGA output
//assign VGA_R = 0;
//assign VGA_G = 0;
//assign VGA_B = 0;
//assign VGA_HSYNC = 0;
//assign VGA_VSYNC = 0;
//
// Clocks (GameBoy clock runs at ~4.194304 MHz)
//
// FPGABoy runs at 33.33 MHz, mostly to simplify the video controller.
// Certain cycle sensitive modules, such as the CPU and Timer are
// internally clocked down to the GameBoy's normal speed.
//
// Core Clock: 33.33 MHz
wire coreclk, core_clock;
DCM_SP core_clock_dcm (.CLKIN(CLK_100M), .CLKFX(coreclk), .RST(1'b0));
defparam core_clock_dcm.CLKFX_DIVIDE = 6;
defparam core_clock_dcm.CLKFX_MULTIPLY = 2;
defparam core_clock_dcm.CLKDV_DIVIDE = 3.0;
defparam core_clock_dcm.CLKIN_PERIOD = 10.000;
BUFG core_clock_buf (.I(coreclk), .O(core_clock));
// Initial Reset
wire reset_init, reset;
SRL16 reset_sr(.D(1'b0), .CLK(core_clock), .Q(reset_init),
.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
// HDMI Clocks
// TODO: No idea what these look like yet.
// Joypad Clock: 1 KHz
wire pulse_1khz;
reg clock_1khz;
divider#(.DELAY(33333)) div_1ms (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_1khz)
);
// CLS Clock: 200 Khz
wire pulse_200khz;
reg clock_200khz;
divider#(.DELAY(166)) div_5us (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_200khz)
);
//
// CPU clock - overflows every 8 cycles
//
reg [2:0] clock_divider;
wire cpu_clock;
BUFG cpu_clock_buf(.I(clock_divider[2]), .O(cpu_clock));
//
// Switches
//
// SW0-SW4 - Breakpoints Switches (Not Implemented)
// SW5 - Step Clock
// SW6 - Step Enable
// SW7 - Power (Reset)
//
wire reset_sync, step_sync, step_enable;
debounce debounce_step_sync(reset_init, core_clock, SW[5], step_sync);
debounce debounce_step_enable(reset_init, core_clock, SW[6], step_enable);
debounce debounce_reset_sync(reset_init, core_clock, !SW[7], reset_sync);
assign reset = (reset_init || reset_sync);
// Game Clock
wire clock;
BUFGMUX clock_mux(.S(step_enable), .O(clock),
.I0(core_clock), .I1(step_sync));
//
// Buttons
//
// BTN0 - Not Implemented
// BTN1 - Joypad
// BTN2 - PC SP
// BTN3 - AF BC
// BTN4 - DE HL
//
reg [1:0] mode;
wire mode0_sync, mode1_sync, mode2_sync, mode3_sync;
debounce debounce_mode0_sync(reset_init, core_clock, BTN[2], mode0_sync);
debounce debounce_mode1_sync(reset_init, core_clock, BTN[3], mode1_sync);
debounce debounce_mode2_sync(reset_init, core_clock, BTN[4], mode2_sync);
debounce debounce_mode3_sync(reset_init, core_clock, BTN[1], mode3_sync);
//
// GameBoy
//
// GB <-> Cartridge + WRAM
wire [15:0] A;
wire [7:0] Di;
wire [7:0] Do;
wire wr_n, rd_n, cs_n;
// GB <-> VRAM
wire [15:0] A_vram;
wire [7:0] Di_vram;
wire [7:0] Do_vram;
wire wr_vram_n, rd_vram_n, cs_vram_n;
// GB <-> Display Adapter
wire [1:0] pixel_data;
wire pixel_clock;
wire pixel_latch;
wire hsync, vsync;
// GB <-> Joypad Adapter
wire [3:0] joypad_data;
wire [1:0] joypad_sel;
// GB <-> Audio Adapter
wire audio_left, audio_right;
// GB <-> CLS SPI
wire [15:0] PC;
wire [15:0] SP;
wire [15:0] AF;
wire [15:0] BC;
wire [15:0] DE;
wire [15:0] HL;
wire [15:0] A_cpu;
wire [7:0] Di_cpu;
wire [7:0] Do_cpu;
gameboy gameboy (
.clock(clock),
.cpu_clock(cpu_clock),
.reset(reset),
.reset_init(reset_init),
.A(A),
.Di(Di),
.Do(Do),
.wr_n(wr_n),
.rd_n(rd_n),
.cs_n(cs_n),
.A_vram(A_vram),
.Di_vram(Di_vram),
.Do_vram(Do_vram),
.wr_vram_n(wr_vram_n),
.rd_vram_n(rd_vram_n),
.cs_vram_n(cs_vram_n),
.pixel_data(pixel_data),
.pixel_clock(pixel_clock),
.pixel_latch(pixel_latch),
.hsync(hsync),
.vsync(vsync),
.joypad_data(joypad_data),
.joypad_sel(joypad_sel),
.audio_left(audio_left),
.audio_right(audio_right),
// debug output
.dbg_led(LED),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.A_cpu(A_cpu),
.Di_cpu(Di_cpu),
.Do_cpu(Do_cpu)
);
// Internal ROMs and RAMs
reg [7:0] tetris_rom [0:32767];
initial begin
$readmemh("data/tetris.hex", tetris_rom, 0, 32767);
end
wire [7:0] Di_wram;
// WRAM
async_mem #(.asz(8), .depth(8192)) wram (
.rd_data(Di_wram),
.wr_clk(clock),
.wr_data(Do),
.wr_cs(!cs_n && !wr_n),
.addr(A),
.rd_cs(!cs_n && !rd_n)
);
// VRAM
async_mem #(.asz(8), .depth(8192)) vram (
.rd_data(Di_vram),
.wr_clk(clock),
.wr_data(Do_vram),
.wr_cs(!cs_vram_n && !wr_vram_n),
.addr(A_vram),
.rd_cs(!cs_vram_n && !rd_vram_n)
);
assign Di = A[14] ? Di_wram : tetris_rom[A];
// Joypad Adapter
wire [15:0] joypad_state;
joypad_snes_adapter joypad_adapter(
.clock(clock_1khz),
.reset(reset),
.button_sel(joypad_sel),
.button_data(joypad_data),
.button_state(joypad_state),
.controller_data(JB[4]),
.controller_clock(JB[5]),
.controller_latch(JB[6])
);
cls_spi cls_spi(
.clock(clock_200khz),
.reset(reset),
.mode(mode),
.ss(JB[0]),
.mosi(JB[1]),
.miso(JB[2]),
.sclk(JB[3]),
.A(A_cpu),
.Di(Di_cpu),
.Do(Do_cpu),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.joypad_state(joypad_state)
);
// driver for divider clocks and debug elements
always @(posedge core_clock) begin
if (reset_init) begin
clock_1khz <= 1'b0;
clock_200khz <= 1'b0;
mode <= 2'b0;
end else begin
if (pulse_1khz)
clock_1khz <= !clock_1khz;
if (pulse_200khz)
clock_200khz <= !clock_200khz;
if (mode0_sync)
mode <= 2'b00;
else if (mode1_sync)
mode <= 2'b01;
else if (mode2_sync)
mode <= 2'b10;
else if (mode3_sync)
mode <= 2'b11;
end
end
always @(posedge clock) begin
if (reset_init) begin
clock_divider <= 1'b0;
end else begin
if (step_enable)
clock_divider <= clock_divider + 4;
else
clock_divider <= clock_divider + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; string col[1000]; int main() { cin >> n >> col[0]; for (int i = 1; i < 1000; ++i) col[i] = col[0]; for (int i = 0, a, b; i < n; ++i) { scanf( %d%d , &a, &b); char now = col[0][i]; for (int j = b; j < 1000; j += a) { now = 0 + 1 - now; for (int t = j; t < min(1000, j + a); ++t) col[t][i] = now; } } int ans = 0; for (int i = 0; i < 1000; ++i) ans = max(ans, (int)count(col[i].begin(), col[i].end(), 1 )); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int c[100005], n, m; map<int, int> f; int lowbit(int x) { return x & (-x); } void add(int x, int j) { while (x < 100005) { c[x] += j; x += lowbit(x); } } int sum(int x) { int s = 0; while (x > 0) { s += c[x]; x -= lowbit(x); } return s; } struct node { int id; int num; } a[100005]; bool cmp_id(node A, node B) { return A.id < B.id; } bool cmp_num(node A, node B) { return A.num < B.num; } int main() { int i, j, k, m, cnt, ans, tem; while (scanf( %d , &n) != EOF) { f.clear(); cnt = 1; ans = 0; for (i = 1; i <= n; i++) { scanf( %d , &a[i].num); a[i].id = i; } sort(a + 1, a + 1 + n, cmp_num); for (i = 1; i <= n; i++) if (f[a[i].num] == 0) f[a[i].num] = cnt++; sort(a + 1, a + 1 + n, cmp_id); for (i = 1; i <= n; i++) a[i].num = f[a[i].num]; for (i = 1; i <= n; i++) add(a[i].num, 1); for (i = n; i >= 1; i--) { tem = sum(a[i].num); add(a[i].num, -1); if (tem == i) ans++; else { int ant = a[i].num; while (i--) { ant = min(a[i].num, ant); int tp = sum(ant); add(a[i].num, -1); if (sum(ant) == i - 1) break; } ans++; } } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline bool checkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool checkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int MAXN = 2600 / 2; const int MAXM = 51; const int MMAX = MAXN * MAXM + MAXN + MAXM + 100; const int di[] = {0, 0, 1, 0, -1}; const int dj[] = {0, 1, 0, -1, 0}; struct Graph { public: int n, m; int adj[MAXN][MAXM]; void init() { n = m = 0; memset(adj, 0, sizeof(adj)); } void insert(int u, int v) { n = max(n, v + 1); m = max(m, v + 1); adj[u][v] = 1; } int find_ans() { build_dlx(); for (int ans = 0; ans <= n; ++ans) { if (dfs(0, ans)) { return ans; } } return -1; } private: int head; int U[MMAX], D[MMAX], L[MMAX], R[MMAX], CN[MMAX], RN[MMAX]; void addUD(const int &a, const int &h) { U[a] = h; D[a] = D[h]; U[D[h]] = a; D[h] = a; CN[a] = h; } void addLR(const int &a, const int &h) { L[a] = h; R[a] = R[h]; L[R[h]] = a; R[h] = a; RN[a] = h; } void add(const int &k, const int &r, const int &c) { addUD(k, c); addLR(k, r); } void remove(const int &k) { for (int j = R[k]; j != k; j = R[j]) { for (int i = D[j]; i != j; i = D[i]) { L[R[i]] = L[i]; R[L[i]] = R[i]; } D[U[j]] = D[j]; U[D[j]] = U[j]; } } void unremove(const int &k) { for (int j = L[k]; j != k; j = L[j]) { D[U[j]] = j; U[D[j]] = j; for (int i = U[j]; i != j; i = U[i]) { L[R[i]] = i; R[L[i]] = i; } } } void build_dlx() { head = MMAX - 1; U[head] = D[head] = L[head] = R[head] = head; int cnt = 0; for (int i = 0; i < m; i++) { U[cnt] = D[cnt] = cnt; addLR(cnt++, head); } for (int i = 0; i < n; i++) { L[cnt] = R[cnt] = cnt; addUD(cnt++, head); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (adj[i][j]) { addLR(cnt, m + i); addUD(cnt, j); cnt++; } } } int h() { int hash[MAXM] = {}; int ans = 0; for (int c = R[head]; c != head; c = R[c]) { if (hash[c] == 0) { hash[c] = 1; ++ans; for (int j = D[c]; j != c; j = D[j]) { for (int i = R[j]; i != j; i = R[i]) { if (CN[i] != head) { hash[CN[i]] = 1; } } } } } return ans; } bool dfs(int k, int lim) { if (k + h() > lim) { return false; } if (R[head] == head) { return true; } int c; c = R[head]; L[R[c]] = L[c]; R[L[c]] = R[c]; for (int i = D[c]; i != c; i = D[i]) { L[R[i]] = L[i]; R[L[i]] = R[i]; } for (int i = D[c]; i != c; i = D[i]) { remove(RN[i]); if (dfs(k + 1, lim)) { return true; } unremove(RN[i]); } for (int i = U[c]; i != c; i = U[i]) { L[R[i]] = i; R[L[i]] = i; } L[R[c]] = c; R[L[c]] = c; return false; } } G; int N, M; int change(const int &i, const int &j) { return i * M + j; } int main() { while (scanf( %d%d , &N, &M) == 2) { G.init(); for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { for (int p = 0; p < 5; p++) { int ii = i + di[p], jj = j + dj[p]; if (0 <= ii && ii < N && 0 <= jj && jj < M) { G.insert(change(i, j), change(ii, jj)); } } } } int res = G.find_ans(); printf( %d n , M * N - res); } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const char nl = n ; using vi = vector<int>; using vll = vector<ll>; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); template <typename... Args, template <typename...> typename T> string to_string(T<Args...> const &); string to_string(string const &s) { return + s + ; } string to_string(char const &c) { return to_string(string(1, c)); } string to_string(char const *c) { return to_string(string(c)); } string to_string(bool const &b) { return (b ? T : F ); } template <typename... Args> string to_string(pair<Args...> const &p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename... Args, template <typename...> typename T> string to_string(T<Args...> const &S) { string s = { ; for (auto const &e : S) s += + to_string(e); s += } ; return s; } template <typename Tail> void debug_out(Tail t) { cerr << [ << to_string(t) << ] << endl; } template <typename Head, typename... Tail> void debug_out(Head h, Tail... t) { cerr << << to_string(h) << , ; debug_out(t...); } template <typename T> void dbr(T lb, T ub) { cerr << { ; for (auto it = lb; it != ub; it++) cerr << << to_string(*it); cerr << } << endl; } template <typename T, typename Comp = less<T>> bool smin(T &mem, T const &v, Comp const &cmp = Comp()) { return cmp(v, mem) ? mem = v, true : false; } template <typename T, typename Comp = less<T>> bool smax(T &mem, T const &v, Comp const &cmp = Comp()) { return cmp(mem, v) ? mem = v, true : false; } const string getEnvVar(string const &key) { char *val = getenv(key.c_str()); return val == NULL ? string( ) : string(val); } vector<string> splitString(const string &str, const string &delim = ) { vector<string> tokens; size_t prev = 0, pos = 0; do { pos = str.find(delim, prev); if (pos == string::npos) pos = str.length(); string token = str.substr(prev, pos - prev); if (!token.empty()) tokens.push_back(token); prev = pos + delim.length(); } while (pos < str.length() && prev < str.length()); return tokens; } void header() { ios::sync_with_stdio(false); cin.tie(nullptr); } int main() { header(); string enc, dec = ; cin >> enc; for (int i = 0; i < enc.length(); i++) { if (enc[i] == . ) { dec += 0 ; } else { if (enc[i + 1] == . ) dec += 1 ; else dec += 2 ; i++; } } cout << dec << endl; }
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// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A register synchronization module across clock domains.
// Uses a Handshake Pulse protocol to trigger the load on
// destination side registers
// Transfer takes 3 dCLK for destination side to see data,
// sRDY recovers takes 3 dCLK + 3 sCLK
module SyncRegister(
sCLK,
sRST_N,
dCLK,
sEN,
sRDY,
sD_IN,
dD_OUT
);
parameter width = 1 ;
parameter init = { width {1'b0 }} ;
// Source clock domain ports
input sCLK ;
input sRST_N ;
input sEN ;
input [width -1 : 0] sD_IN ;
output sRDY ;
// Destination clock domain ports
input dCLK ;
output [width -1 : 0] dD_OUT ;
wire dPulse ;
reg [width -1 : 0] sDataSyncIn ;
reg [width -1 : 0] dD_OUT ;
// instantiate a Handshake Sync
SyncHandshake sync( .sCLK(sCLK), .sRST_N(sRST_N),
.dCLK(dCLK),
.sEN(sEN), .sRDY(sRDY),
.dPulse(dPulse) ) ;
always @(posedge sCLK or negedge sRST_N)
begin
if (sRST_N == 0)
begin
sDataSyncIn <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N == 0)
else
begin
if ( sEN )
begin
sDataSyncIn <= `BSV_ASSIGNMENT_DELAY sD_IN ;
end // if ( sEN )
end // else: !if(sRST_N == 0)
end // always @ (posedge sCLK or negedge sRST_N)
// Transfer the data to destination domain when dPulsed is asserted.
// Setup and hold time are assured since at least 2 dClks occured since
// sDataSyncIn have been written.
always @(posedge dCLK or negedge sRST_N)
begin
if (sRST_N == 0)
begin
dD_OUT <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N == 0)
else
begin
if ( dPulse )
begin
dD_OUT <= `BSV_ASSIGNMENT_DELAY sDataSyncIn ;// clock domain crossing
end // if ( dPulse )
end // else: !if(sRST_N == 0)
end // always @ (posedge dCLK or negedge sRST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sDataSyncIn = {((width + 1)/2){2'b10}} ;
dD_OUT = {((width + 1)/2){2'b10}} ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // RegisterSync
`ifdef testBluespec
module testSyncRegister() ;
parameter dsize = 8;
wire sCLK, sRST_N, dCLK ;
wire sEN ;
wire sRDY ;
reg [dsize -1:0] sCNT ;
wire [dsize -1:0] sDIN, dDOUT ;
ClockGen#(20,9,10) sc( sCLK );
ClockGen#(11,12,26) dc( dCLK );
initial
begin
sCNT = 0;
$dumpfile("SyncRegister.dump");
$dumpvars(5) ;
$dumpon ;
#100000 $finish ;
end
SyncRegister #(dsize)
dut( sCLK, sRST_N, dCLK,
sEN, sRDY, sDIN,
dDOUT ) ;
assign sDIN = sCNT ;
assign sEN = sRDY ;
always @(posedge sCLK)
begin
if (sRDY )
begin
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
end
end // always @ (posedge sCLK)
endmodule // testSyncFIFO
`endif
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate function w/ single input
module main ();
reg [31:0] val1,val2 ;
reg error;
function [31:0] myfunc ;
input [31:0] in1 ;
myfunc = in1 ;
endfunction
initial
begin
error = 0;
val1 = myfunc(32'h0) ;
if(val1 != 32'h0)
begin
$display("FAILED - function3.11B - func(lit) != lit ");
error = 1;
end
val2 = 32'h12345678 ;
val1 = myfunc(val2);
if(val1 != val2)
begin
$display("FAILED - function3.11B - func(reg var) != reg var ");
error = 1;
end
if(myfunc(32'h10101010) != 32'h10101010)
begin
$display("FAILED - function3.11B - if(func(reg var) != reg var) ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; void adskiy_razgon() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const int mxN = 1e+9 + 7; const long long INF = 1e+18 + 7; long long nod(long long a, long long b) { if (b > a) { swap(a, b); } while (b > 0) { a %= b; swap(a, b); } return a; } long long nok(long long a, long long b) { return a * b / nod(a, b); } void sp(long long a, double b) { cout << fixed << setprecision(a) << b; } long long binpow(long long a, long long n) { if (n == 0) { return 1; } if (n % 2 == 1) { return binpow(a, n - 1) * a; } else { long long b = binpow(a, n / 2); return b * b; } } void solve() { int n, m, t; cin >> n >> m >> t; cout << ((n - m) * t + m - 1) / m; } int main() { adskiy_razgon(); long long t = 1; for (int i = 1; i <= t; ++i) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 5; const int INF = (int)1e9 + 9; const int MOD = (int)1e9 + 7; void go(int x) { cout << x; exit(0); } vector<int> g[N]; set<int> st[N]; int c[N]; bool used[N]; int main() { int n, m, cnt = -1, ans = -1; cin >> n >> m; for (int i = 1; i <= n; i++) { scanf( %d , &c[i]); used[c[i]] = 1; } for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); used[c[u]] = 1; used[c[v]] = 1; if (c[u] == c[v]) { continue; } st[c[u]].insert(c[v]); st[c[v]].insert(c[u]); } for (int i = 1; i <= 1e5; i++) { if (used[i] && (int)st[i].size() > cnt) { cnt = (int)st[i].size(); ans = i; } } cout << ans << endl; }
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// megafunction wizard: %In-System Sources and Probes%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; char s[1111][1111]; int d[1111][1111]; queue<pair<int, int> > Q; vector<pair<int, int> > v; int n, m, lim; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; void check(int x, int y, int z) { if (x < 0 || x >= n || y < 0 || y >= m) return; if (s[x][y] == T ) return; if (s[x][y] == S ) lim = z; d[x][y] = z; if ( 0 <= s[x][y] && s[x][y] <= 9 ) v.push_back(make_pair(s[x][y] - 0 , z)); s[x][y] = T ; Q.push(make_pair(x, y)); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (s[i][j] == E ) Q.push(make_pair(i, j)); while (!Q.empty()) { pair<int, int> now = Q.front(), tmp; Q.pop(); for (int dir = 0; dir < 4; dir++) check(now.first + dx[dir], now.second + dy[dir], d[now.first][now.second] + 1); } int ans = 0; for (vector<pair<int, int> >::iterator ii = v.begin(); ii != v.end(); ii++) if (ii->second <= lim) ans += ii->first; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9 + 7; const int N = (int)1e5 + 10; struct qq { int l, r, i, w; }; int t[4 * N], ans[2 * N]; pair<int, int> p[2 * N]; vector<qq> qx[N], qy[N]; void upd(int pos, int val, int v = 1, int l = 1, int r = N - 10) { if (l == r) { t[v] = val; return; } int m = (l + r) >> 1; if (pos <= m) { upd(pos, val, v + v, l, m); } else { upd(pos, val, v + v + 1, m + 1, r); } t[v] = min(t[v + v], t[v + v + 1]); } int get(int l, int r, int v = 1, int tl = 1, int tr = N - 10) { if (l > r || tr < l || tl > r) { return inf; } if (l <= tl && tr <= r) { return t[v]; } int tm = (tl + tr) >> 1; return min(get(l, r, v + v, tl, tm), get(l, r, v + v + 1, tm + 1, tr)); } inline bool cmp(pair<int, int> f, pair<int, int> s) { return f.second < s.second || (f.second == s.second && f.first < s.first); } int main() { int n, m, k, q; scanf( %d %d %d %d , &n, &m, &k, &q); for (int i = 1; i <= k; i++) { int x, y; scanf( %d %d , &x, &y); p[i] = {x, y}; } for (int i = 1; i <= q; i++) { int ax, ay, bx, by; scanf( %d %d %d %d , &ax, &ay, &bx, &by); qx[bx].emplace_back(qq({ay, by, i, ax})); qy[by].emplace_back(qq({ax, bx, i, ay})); } sort(p + 1, p + k + 1); int ptr = 1; for (int i = 1; i < N; i++) { while (ptr <= k && p[ptr].first == i) { upd(p[ptr].second, i); ptr++; } for (auto j : qx[i]) { ans[j.i] |= ((get(j.l, j.r) >= j.w) ? 1 : 0); } } memset(t, 0, sizeof(t)); ptr = 1; sort(p + 1, p + k + 1, cmp); for (int i = 1; i < N; i++) { while (ptr <= k && p[ptr].second == i) { upd(p[ptr].first, i); ptr++; } for (auto j : qy[i]) { ans[j.i] |= ((get(j.l, j.r) >= j.w) ? 1 : 0); } } for (int i = 1; i <= q; i++) { if (ans[i] == 1) puts( YES ); else puts( NO ); } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdr_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdr_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_bufp3_pa_l, arbpc0_pcxdp_q0_hold_bufp3_pa,
arbpc0_pcxdp_qsel0_bufp3_pa_l, arbpc0_pcxdp_qsel1_bufp3_pa,
arbpc0_pcxdp_shift_bufp3_px_l, arbpc2_pcxdp_grant_bufp3_pa_l,
arbpc2_pcxdp_q0_hold_bufp3_pa, arbpc2_pcxdp_qsel0_bufp3_pa_l,
arbpc2_pcxdp_qsel1_bufp3_pa, arbpc2_pcxdp_shift_bufp3_px_l
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_bufp3_pa_l;
input arbpc0_pcxdp_q0_hold_bufp3_pa;
input arbpc0_pcxdp_qsel0_bufp3_pa_l;
input arbpc0_pcxdp_qsel1_bufp3_pa;
input arbpc0_pcxdp_shift_bufp3_px_l;
input arbpc2_pcxdp_grant_bufp3_pa_l;
input arbpc2_pcxdp_q0_hold_bufp3_pa;
input arbpc2_pcxdp_qsel0_bufp3_pa_l;
input arbpc2_pcxdp_qsel1_bufp3_pa;
input arbpc2_pcxdp_shift_bufp3_px_l;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp3_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp3_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp3_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp3_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp3_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp3_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp3_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp3_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp3_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp3_px_l;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int val; int type; } N[500000]; int main() { long long n, a, b, c, d, start, len; cin >> n >> a >> b >> c >> d >> start >> len; for (int i = 1; i <= n; i++) { cin >> N[i].val >> N[i].type; } long long s = 1, t = 1, sum_st = start, ans = 0; long long low = 0; N[0].val = -1; for (int s = 1; s <= n; s++) { while (t <= n && N[t].val - N[s].val <= len) { if (N[t].type == 1) ans += c; else if (N[t].type == 0) ans -= d; low = min(low, ans); t++; } if (sum_st + low >= 0) { cout << N[s - 1].val + 1 << endl; return 0; } if (N[s].type == 1) { ans -= c; low -= c; sum_st += a; } else { ans += d; low += d; sum_st -= b; } if (sum_st < 0) { cout << -1 << endl; return 0; } } cout << N[n].val + 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long p = 1e9 + 7; int n, a[2505], mx, s, ch, ans; long long f[100005]; long long ksm(long long x, int y) { long long sun = 1; x %= p; while (y) { if (y & 1) sun = sun * x % p; y >>= 1; x = x * x % p; } return sun; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), mx = max(a[i], mx), s += a[i]; f[1] = ksm(s - 1, 2) * ksm(s, p - 2) % p; ch = f[1]; for (int i = 2; i <= mx; i++) { ch = (ch - ksm(s - i + 1, p - 2) * (s - 1) % p + p) % p; f[i] = (f[i - 1] + ch) % p; } for (int i = 1; i <= n; i++) ans = (ans + f[a[i]]) % p; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; uint64_t getSeed() { auto ptr = new char; delete ptr; return (uint64_t)ptr + chrono::high_resolution_clock::now().time_since_epoch().count(); } mt19937 rnd(getSeed()); ll rndVal(uint64_t a, uint64_t b) { return uniform_int_distribution<uint64_t>(a, b)(rnd); } constexpr uint64_t MOD = (1ull << 61) - 1; inline uint64_t mod(uint64_t x) { x++; x = (x & MOD) + (x >> 61); x = (x & MOD) + (x >> 61); return x - 1; } uint64_t mulmod(const uint64_t a, const uint64_t b) { uint64_t ha = a >> 32, la = uint32_t(a), hb = b >> 32, lb = uint32_t(b); uint64_t h = ha * hb, m = ha * lb + la * hb, l = la * lb; return mod((l & MOD) + (l >> 61) + (m >> 29) + (m << 35 >> 3) + (h << 3)); } struct Hash { vector<uint64_t> h; vector<uint64_t> p; void build(const string& s, const uint64_t base) { int n = s.size(); h.resize(n + 1); p.resize(n + 1); h[0] = 1; p[0] = 1; for (int i = 0; i < n; i++) { h[i + 1] = mod(mulmod(h[i], base) + s[i] + 130); p[i + 1] = mulmod(p[i], base); } } void build(const string& s) { build(s, rndVal(258, MOD - 1)); } uint64_t query(int l, int r) { return mod(h[r + 1] + MOD - mulmod(h[l], p[r - l + 1])); } }; string s, t; int main() { ios::sync_with_stdio(false); cin >> s >> t; int ns = s.size(), nt = t.size(); uint64_t base = rndVal(258, MOD - 1); Hash hash; hash.build(t, base); int rep = 0; for (int i = 0; i < nt - 1; i++) { if (hash.query(0, i) == hash.query(nt - i - 1, nt - 1)) rep = i + 1; } int has[2] = {0, 0}; for (auto c : s) has[c - 0 ]++; int needs[2] = {0, 0}; for (auto c : t) needs[c - 0 ]++; if (needs[0] > has[0] or needs[1] > has[1]) { cout << s << endl; return 0; } cout << t; has[0] -= needs[0]; has[1] -= needs[1]; for (int i = 0; i < rep; i++) needs[t[i] - 0 ]--; while (has[0] >= needs[0] and has[1] >= needs[1]) { for (int i = rep; i < nt; i++) { cout << t[i]; has[t[i] - 0 ]--; } } while (has[0]) { cout << 0 ; has[0]--; } while (has[1]) { cout << 1 ; has[1]--; } cout << endl; }
|
/* ͬ²½ FIFO 4*128 */
// Ò»ÖÖ4bit 128Éî¶ÈµÄ ͬ²½FIFOÉè¼Æ
// @`13
// 2017Äê6ÔÂ6ÈÕ
// ¹þ¶û±õ¹¤Òµ´óѧ£¨Íþº££© EDA¿Î³ÌÉè¼Æ
module fifo(clock,reset,read,write,fifo_in,fifo_out,fifo_empty,fifo_full);
parameter DEPTH = 128; // 128 Éî
parameter DEPTH_BINARY = 7; // Éî¶ÈµÄ¶þ½øÖÆλÊý
parameter WIDTH = 4; // 4bit¿í
parameter MAX_CONT = 7'b1111111; // ¼ÆÊýÆ÷×î´óÖµ127 [0~127]
// LED µÆµÄ¶þ½øÖƱíʾ
parameter
reg0=7'b0000001,
reg1=7'b1001111,
reg2=7'b0010010,
reg3=7'b0000110,
reg4=7'b1001100,
reg5=7'b0100100,
reg6=7'b0100000,
reg7=7'b0001101,
reg8=7'b0000000,
reg9=7'b0000100,
rega=7'b0001000,
regb=7'b1100000,
regc=7'b0110001,
regd=7'b1000010,
rege=7'b0110000,
regf=7'b0111000;
input clock,reset,read,write; // ʱÖÓ£¬ÖØÖ㬶Á¿ª¹Ø£¬Ð´¿ª¹Ø
input [WIDTH-1:0]fifo_in; // FIFO Êý¾ÝÊäÈë
output[WIDTH-1:0]fifo_out; // FIFO Êý¾ÝÊä³ö
output fifo_empty,fifo_full; // ¿Õ±êÖ¾,Âú±êÖ¾
reg [WIDTH-1:0]fifo_out; // Êý¾ÝÊä³ö¼Ä´æÆ÷
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128Éî¶È 8¿í¶ÈµÄ RAM ¼Ä´æÆ÷
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // ¶ÁÖ¸Õ룬дָÕ룬¼ÆÊýÆ÷ ³¤¶ÈΪ2^7
wire fifo_empty,fifo_full; // ¿Õ±êÖ¾,Âú±êÖ¾
initial
begin
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
end
assign fifo_empty = (counter == 0); //±ê־λ¸³Öµ
assign fifo_full = (counter == DEPTH-1);
always@(posedge clock) // ʱÖÓͬ²½Çý¶¯
if(reset) // Reset ÖØÖÃFIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // ÏàÓ¦¶Áд¿ª¹Ø
2'b00:; //ûÓжÁдָÁî
2'b01: //дָÁÊý¾ÝÊäÈëFIFO
begin
if (counter < DEPTH - 1) // ÅжÏÊÇ·ñ¿Éд
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //¶ÁÖ¸ÁÊý¾Ý¶Á³öFIFO
begin
if (counter > 0) // ÅжÏÊÇ·ñ¿É¶Á
begin
fifo_out = ram[read_ptr];
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //¶ÁдָÁîͬʱ£¬Êý¾Ý¿ÉÒÔÖ±½ÓÊä³ö
begin
if(counter == 0)
fifo_out = fifo_in; // Ö±½ÓÊä³ö
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule
//module debouncing(
//BJ_CLK, //²É¼¯Ê±ÖÓ£¬40Hz
//RESET, //ϵͳ¸´Î»Ðźŵ͵çƽÓÐЧ
//BUTTON_IN, //°´¼üÊäÈëÐźÅ
//BUTTON_OUT //Ïû¶¶ºóµÄÊä³öÐźÅ
//);
//
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
//
// output BUTTON_OUT;
//
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
//
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
//
//endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_SYMBOL_V
`define SKY130_FD_SC_HS__DLRTP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-6; int ROUND(double x) { return (int)(x + 0.5); } bool ISINT(double x) { return fabs(ROUND(x) - x) <= EPS; } bool ISEQUAL(double x, double y) { return fabs(x - y) <= EPS * max(1.0, max(fabs(x), fabs(y))); } double SQSUM(double x, double y) { return x * x + y * y; } template <class T> bool INRANGE(T x, T a, T b) { return a <= x && x <= b; } void split1(const string& str, vector<string>& out) { string::size_type st = 0; string::size_type next = 0; int word_num = 0; string tmp = str; do { next = tmp.find( , st); string word = tmp.substr(st, next - st); if (word.length() >= 1) { out.push_back(word); } st = next + 1; } while (next != string::npos); } int main() { int n; scanf( %d , &n); vector<string> team_names; for (int i = 0; i < n; i++) { char str[256]; scanf( %s , str); team_names.push_back(string(str)); } map<string, pair<int, pair<int, int> > > mp; for (int i = 0; i < n * (n - 1) / 2; i++) { char str[256]; char str2[256]; scanf( %s %s , str, str2); for (int k = 0; k < 256; k++) { if (str[k] == - || str[k] == : ) { str[k] = ; } if (str2[k] == - || str2[k] == : ) { str2[k] = ; } } vector<string> vs; split1(string(str), vs); vector<string> vs2; split1(string(str2), vs2); string team1, team2; int goal1, goal2; team1 = vs[0]; team2 = vs[1]; goal1 = atoi(vs2[0].c_str()); goal2 = atoi(vs2[1].c_str()); mp[team1].first += goal1 > goal2 ? 3 : goal1 == goal2 ? 1 : 0; mp[team1].second.first += goal1 - goal2; mp[team1].second.second += goal1; mp[team2].first += goal2 > goal1 ? 3 : goal2 == goal1 ? 1 : 0; mp[team2].second.first += goal2 - goal1; mp[team2].second.second += goal2; } map<pair<int, pair<int, int> >, string> inv_mp; { map<string, pair<int, pair<int, int> > >::iterator it; for (it = mp.begin(); it != mp.end(); it++) { inv_mp[it->second] = it->first; } } vector<string> winners; { map<pair<int, pair<int, int> >, string>::reverse_iterator inv_it = inv_mp.rbegin(); for (int i = 0; i < n / 2; inv_it++, i++) { winners.push_back(inv_it->second); } } sort(winners.begin(), winners.end()); for (int i = 0; i < ((int)winners.size()); i++) { printf( %s n , winners[i].c_str()); } return 0; }
|
/**
\file "inverters-watch2.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters-watch2.v,v 1.2 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
$prsim_cmd("watch in1 out3");
end
initial #45 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e9; const int SIZE = 2e5 + 5; const int MOD = 1e9 + 7; void solve(int CASE) { long long x; cin >> x; vector<long long> res; for (long long i = 1; i <= x; i *= 2LL) { res.push_back(i); x -= i; } if (x) res.push_back(x); sort(res.begin(), res.end()); cout << res.size() - 1 << endl; for (int i = 1; i < res.size(); i++) cout << res[i] - res[i - 1] << ; cout << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int IT; cin >> IT; for (int i = 1; i <= IT; i++) { solve(i); }; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_TB_V
`define SKY130_FD_SC_MS__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, x; scanf( %d , &n); priority_queue<int, vector<int>, greater<int> > que; long long ans = 0; for (int i = 0; i < n; i++) { scanf( %d , &x); if (que.empty() || que.top() > x) que.push(x); else { ans += x - que.top(); que.pop(); que.push(x); que.push(x); } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int convert(int k) { if (k < 2) return k; else if (k < 5) return k - 1; else return k - 2; } int main() { string s[6]; int A[6][6] = {3, 3, 4, 4, 3, 3, 3, 3, 4, 4, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 2, 2, 1, 1, 2, 2, 1, 1, 1, 1, 2, 2, 1, 1}; for (int i = 0; i < 6; i++) { cin >> s[i]; } int best = 0, besti = 0, bestj = 0; for (int i = 0; i < 6; i++) { for (int j = 0; j < 8; j++) { if (s[i][j] == . ) { if (A[i][convert(j)] > best) { best = A[i][convert(j)]; besti = i; bestj = j; } } } } s[besti][bestj] = P ; for (int i = 0; i < 6; i++) { cout << s[i] << endl; } return 0; }
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`include "defines.v"
module ex_mem (
input wire rst,
input wire clk,
input wire[`RegAddrBus] ex_waddr,
input wire ex_we,
input wire[`RegBus] ex_wdata,
input wire ex_whilo,
input wire[`RegBus] ex_hi,
input wire[`RegBus] ex_lo,
input wire[5:0] stall,
input wire[`DoubleRegBus] hilo_i,
input wire[1:0] cnt_i,
input wire[`AluOpBus] ex_aluop,
input wire[`RegBus] ex_mem_addr,
input wire[`RegBus] ex_reg2,
input wire[`RegBus] ex_cp0_reg_data,
input wire[`RegAddrBus] ex_cp0_reg_waddr,
input wire ex_cp0_reg_we,
input wire flush,
input wire[`RegBus] ex_excepttype,
input wire[`RegBus] ex_current_inst_addr,
input wire ex_current_inst_loaded,
input wire ex_is_in_delayslot,
output reg[`RegAddrBus] mem_waddr,
output reg mem_we,
output reg[`RegBus] mem_wdata,
output reg mem_whilo,
output reg[`RegBus] mem_hi,
output reg[`RegBus] mem_lo,
output reg[`DoubleRegBus] hilo_o,
output reg[1:0] cnt_o,
output reg[`AluOpBus] mem_aluop,
output reg[`RegBus] mem_mem_addr,
output reg[`RegBus] mem_reg2,
output reg[`RegBus] mem_cp0_reg_data,
output reg[`RegAddrBus] mem_cp0_reg_waddr,
output reg mem_cp0_reg_we,
output reg[`RegBus] mem_excepttype,
output reg[`RegBus] mem_current_inst_addr,
output reg mem_current_inst_loaded,
output reg mem_is_in_delayslot
);
always @(posedge clk) begin
if (rst == `RstEnable) begin
mem_waddr <= `NOPRegAddr;
mem_we <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= `EXE_OP_NOP_NOP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_data <= `ZeroWord;
mem_cp0_reg_waddr <= 5'b0000;
mem_cp0_reg_we <= `WriteDisable;
mem_excepttype <= `ZeroWord;
mem_current_inst_addr <= `ZeroWord;
mem_current_inst_loaded <= `NotLoaded;
mem_is_in_delayslot <= `NotInDelaySlot;
end
else if (flush == `Flush) begin
mem_waddr <= `NOPRegAddr;
mem_we <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= `EXE_OP_NOP_NOP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_data <= `ZeroWord;
mem_cp0_reg_waddr <= 5'b0000;
mem_cp0_reg_we <= `WriteDisable;
mem_excepttype <= `ZeroWord;
mem_current_inst_addr <= `ZeroWord;
mem_current_inst_loaded <= `NotLoaded;
mem_is_in_delayslot <= `NotInDelaySlot;
end
else if (stall[3] == `StallEnable && stall[4] == `StallDisable) begin
mem_waddr <= `NOPRegAddr;
mem_we <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
hilo_o <= hilo_i;
cnt_o <= cnt_i;
mem_aluop <= `EXE_OP_NOP_NOP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_data <= `ZeroWord;
mem_cp0_reg_waddr <= 5'b0000;
mem_cp0_reg_we <= `WriteDisable;
mem_excepttype <= `ZeroWord;
mem_current_inst_addr <= `ZeroWord;
mem_current_inst_loaded <= `NotLoaded;
mem_is_in_delayslot <= `NotInDelaySlot;
end
else if (stall[3] == `StallDisable) begin
mem_waddr <= ex_waddr;
mem_we <= ex_we;
mem_wdata <= ex_wdata;
mem_whilo <= ex_whilo;
mem_hi <= ex_hi;
mem_lo <= ex_lo;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
mem_cp0_reg_data <= ex_cp0_reg_data;
mem_cp0_reg_waddr <= ex_cp0_reg_waddr;
mem_cp0_reg_we <= ex_cp0_reg_we;
mem_excepttype <= ex_excepttype;
mem_current_inst_addr <= ex_current_inst_addr;
mem_current_inst_loaded <= ex_current_inst_loaded;
mem_is_in_delayslot <= ex_is_in_delayslot;
end
else begin
hilo_o <= hilo_i;
cnt_o <= cnt_i;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int t, n, m, sum; int fa[1000010], sz[1000010]; vector<int> vec[1000010]; int find(int x) { if (x == fa[x]) return x; else return fa[x] = find(fa[x]); } int main() { ios_base::sync_with_stdio(false); t = 1; while (t--) { cin >> n >> m; for (int i = 1; i <= m; ++i) { vec[i].clear(); sz[i] = 0; fa[n + i] = n + i; } for (int i = 1; i <= n; ++i) { int x; cin >> x; sz[x + n]++; vec[x + n].push_back(i); fa[i] = x + n; } sum = 0; for (int i = 2; i <= n; ++i) { if (find(i) == find(i - 1)) { sum++; } } cout << n - sum - 1 << n ; for (int i = 1; i <= m - 1; ++i) { int x, y; cin >> x >> y; int fx = find(x + n), fy = find(y + n); if (sz[fx] < sz[fy]) { for (int j = 0; j < vec[fx].size(); ++j) { if ((vec[fx][j] > 1 && find(vec[fx][j] - 1) == fy)) sum++; if ((vec[fx][j] < n && find(vec[fx][j] + 1) == fy)) sum++; vec[fy].push_back(vec[fx][j]); sz[fy]++; } sz[fx] = 0; fa[fx] = fy; } else { for (int j = 0; j < vec[fy].size(); ++j) { if ((vec[fy][j] > 1 && find(vec[fy][j] - 1) == fx)) sum++; if ((vec[fy][j] < n && find(vec[fy][j] + 1) == fx)) sum++; vec[fx].push_back(vec[fy][j]); sz[fx]++; } sz[fy] = 0; fa[fy] = fx; } cout << n - sum - 1 << n ; } } return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_qsys_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int cmp(double x, double y) { if (fabs(x - y) < 1e-7) return 0; if (x < y) return -1; return 1; } float call(double a, double b) { double s1, s2; if (cmp(a / 4, b) <= 0) { s1 = b + a / 8; } else { double l1, l2, t1, t2; l1 = b * 4; t1 = b + b / 2; l2 = a - l1; t2 = 2 * b; s1 = (l1 * t1 + l2 * t2) / a; } return s1 / (2 * b); } int main() { int n, a, b; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &a, &b); if (b == 0) printf( 1 n ); else if (a == 0) printf( 0.5 n ); else printf( %.9lf n , call(a, b)); } }
|
#include <bits/stdc++.h> using namespace std; bool yes(int x1, int x2, int x3, int x4) { int num1 = (x1 + x2 + x3 + x4) / 4, num2 = (x2 + x3) / 2, num3 = x4 - x1; if (((x1 + x2 + x3 + x4) % 4 != 0) || ((x2 + x3) % 2 != 0) || num1 != num2 || num1 != num3 || x1 == -1 || x2 == -1 || x3 == -1 || x4 == -1) return false; if (x1 <= x2 && x2 <= x3 && x3 <= x4) return true; return false; } bool fun(int x1, int x2, int x3, int x4, vector<int> sol) { for (int i = 1; i <= 2000; i++) { vector<int> Sol = sol; int X1 = x1, X2 = x2, X3 = x3, X4 = x4; x1 = i; x4 = i * 3; if (x2 == -1 && x3 != -1) x2 = x4 + x1 - x3, sol.push_back(x2); else if (x2 != -1 && x3 == -1) x3 = x4 + x1 - x2, sol.push_back(x3); else if (x2 != -1 && x3 != -1 && x2 + x3 != x1 + x4) continue; if (yes(x1, x2, x3, x4)) { cout << YES n ; for (int i = 0; i < (int)sol.size(); i++) cout << sol[i] << n ; return true; } x1 = X1, x2 = X2, x3 = X3, x4 = X4, sol = Sol; } return false; } bool Fun(int x1, int x2, int x3, int x4, vector<int> sol) { for (int i = 1; i <= 2000; i++) { x2 = i; x3 = x4 + x1 - x2; vector<int> Sol = sol; sol.push_back(x2); sol.push_back(x3); if (yes(x1, x2, x3, x4)) { cout << YES n ; for (int I = 0; I < (int)sol.size(); I++) cout << sol[I] << endl; return true; } sol = Sol; } return false; } int main() { ios::sync_with_stdio(false); int n; cin >> n; int ar[4]; memset(ar, -1, sizeof(ar)); for (int i = 0; i < n; i++) cin >> ar[i]; if (n == 0) { cout << YES n1 n1 n3 n3 ; goto ss; } for (int i = 0; i < 4; i++) for (int i1 = 0; i1 < 4; i1++) for (int i2 = 0; i2 < 4; i2++) for (int i3 = 0; i3 < 4; i3++) { if (i == i1 || i == i2 || i == i3 || i1 == i2 || i1 == i3 || i2 == i3) continue; vector<int> sol; int x1 = ar[i], x2 = ar[i1], x3 = ar[i2], x4 = ar[i3]; if (x1 != -1 && x4 != -1) { if (x1 * 3 != x4) continue; } else if (x1 == -1 && x4 != -1) { x1 = x4 / 3; if (x4 % 3 != 0) continue; sol.push_back(x1); } else if (x1 != -1 && x4 == -1) { x4 = x1 * 3; sol.push_back(x4); } else if (x1 == -1 && x4 == -1) if (fun(x1, x2, x3, x4, sol)) goto ss; if (x2 == -1 && x3 == -1) { if (Fun(x1, x2, x3, x4, sol)) goto ss; } else if (x2 == -1) { x2 = x4 + x1 - x3; sol.push_back(x2); } else if (x3 == -1) { x3 = x4 + x1 - x2; sol.push_back(x3); } if (yes(x1, x2, x3, x4)) { cout << YES n ; for (int I = 0; I < (int)sol.size(); I++) cout << sol[I] << n ; goto ss; } } cout << NO ; ss: return 0; }
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