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#include <bits/stdc++.h> using namespace std; int years[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> v(n); for (auto &i : v) cin >> i; ; for (int i = 0; i < 72; i++) { if (years[i] != v[0]) continue; for (int j = 0; j < n; j++) { if (j == n - 1 && v[j] == years[i + j]) return cout << Yes << endl, 0; if (v[j] != years[i + j]) break; } } cout << No << endl; return 0; }
|
`default_nettype none
`timescale 1ns/1ns
module tb_panel();
wire clk, reset;
clock clock(clk, reset);
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [4:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
wire key_start;
wire key_read_in;
wire key_mem_cont;
wire key_inst_cont;
wire key_mem_stop;
wire key_inst_stop;
wire key_exec;
wire key_io_reset;
wire key_dep;
wire key_dep_nxt;
wire key_ex;
wire key_ex_nxt;
// switches
wire sw_addr_stop;
wire sw_mem_disable;
wire sw_repeat;
wire sw_power;
wire [0:35] datasw;
wire [18:35] mas;
// maintenance switches
wire sw_rim_maint;
wire sw_repeat_bypass;
wire sw_art3_maint;
wire sw_sct_maint;
wire sw_split_cyc;
// lights
wire power;
wire [0:17] ir;
wire [0:35] mi;
wire [0:35] ar;
wire [0:35] mb;
wire [0:35] mq;
wire [18:35] pc;
wire [18:35] ma;
wire run;
wire mc_stop;
wire pi_active;
wire [1:7] pih;
wire [1:7] pir;
wire [1:7] pio;
wire [18:25] pr;
wire [18:25] rlr;
wire [18:25] rla;
wire [0:7] ff0;
wire [0:7] ff1;
wire [0:7] ff2;
wire [0:7] ff3;
wire [0:7] ff4;
wire [0:7] ff5;
wire [0:7] ff6;
wire [0:7] ff7;
wire [0:7] ff8;
wire [0:7] ff9;
wire [0:7] ff10;
wire [0:7] ff11;
wire [0:7] ff12;
wire [0:7] ff13;
panel_6 panel(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.key_start(key_start),
.key_read_in(key_read_in),
.key_mem_cont(key_mem_cont),
.key_inst_cont(key_inst_cont),
.key_mem_stop(key_mem_stop),
.key_inst_stop(key_inst_stop),
.key_exec(key_exec),
.key_io_reset(key_io_reset),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_addr_stop(sw_addr_stop),
.sw_mem_disable(sw_mem_disable),
.sw_repeat(sw_repeat),
.sw_power(sw_power),
.datasw(datasw),
.mas(mas),
.sw_rim_maint(sw_rim_maint),
.sw_repeat_bypass(sw_repeat_bypass),
.sw_art3_maint(sw_art3_maint),
.sw_sct_maint(sw_sct_maint),
.sw_split_cyc(sw_split_cyc),
.power(power),
.ir(ir),
.mi(mi),
.ar(ar),
.mb(mb),
.mq(mq),
.pc(pc),
.ma(ma),
.run(run),
.mc_stop(mc_stop),
.pi_active(pi_active),
.pih(pih),
.pir(pir),
.pio(pio),
.pr(pr),
.rlr(rlr),
.rla(rla),
.ff0(ff0),
.ff1(ff1),
.ff2(ff2),
.ff3(ff3),
.ff4(ff4),
.ff5(ff5),
.ff6(ff6),
.ff7(ff7),
.ff8(ff8),
.ff9(ff9),
.ff10(ff10),
.ff11(ff11),
.ff12(ff12),
.ff13(ff13)
);
fakeapr apr(
.clk(clk),
.reset(reset),
.key_start(key_start),
.key_read_in(key_read_in),
.key_mem_cont(key_mem_cont),
.key_inst_cont(key_inst_cont),
.key_mem_stop(key_mem_stop),
.key_inst_stop(key_inst_stop),
.key_exec(key_exec),
.key_io_reset(key_io_reset),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_addr_stop(sw_addr_stop),
.sw_mem_disable(sw_mem_disable),
.sw_repeat(sw_repeat),
.sw_power(sw_power),
.datasw(datasw),
.mas(mas),
.sw_rim_maint(sw_rim_maint),
.sw_repeat_bypass(sw_repeat_bypass),
.sw_art3_maint(sw_art3_maint),
.sw_sct_maint(sw_sct_maint),
.sw_split_cyc(sw_split_cyc),
.power(power),
.ir(ir),
.mi(mi),
.ar(ar),
.mb(mb),
.mq(mq),
.pc(pc),
.ma(ma),
.run(run),
.mc_stop(mc_stop),
.pi_active(pi_active),
.pih(pih),
.pir(pir),
.pio(pio),
.pr(pr),
.rlr(rlr),
.rla(rla),
.ff0(ff0),
.ff1(ff1),
.ff2(ff2),
.ff3(ff3),
.ff4(ff4),
.ff5(ff5),
.ff6(ff6),
.ff7(ff7),
.ff8(ff8),
.ff9(ff9),
.ff10(ff10),
.ff11(ff11),
.ff12(ff12),
.ff13(ff13)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
memory.mem[4] = 123;
memory.mem[5] = 321;
memory.mem['o123] = 36'o112233445566;
#5;
#200;
@(posedge clk);
a_address <= 6;
a_write <= 1;
a_writedata = 32'o123456;
@(negedge a_write);
@(posedge clk);
a_address <= 7;
a_write <= 1;
a_writedata = 32'o654321;
@(negedge a_write);
@(posedge clk);
a_address <= 'o10;
a_write <= 1;
a_writedata = 32'o112233;
@(negedge a_write);
@(posedge clk);
a_address <= 'o01;
a_write <= 1;
a_writedata = 32'o7777777;
@(negedge a_write);
@(posedge clk);
a_address <= 4;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 5;
a_read <= 1;
@(negedge a_read);
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
reg [0:35] data;
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read) begin
a_read <= 0;
data <= a_readdata;
end
end
endmodule
|
#include<bits/stdc++.h> #define maxn 200005 #define endl n using namespace std; int n,m,a[maxn],dis[maxn]; vector<int> e[maxn]; queue<int> q; void bfs() { while(!q.empty()) { int u=q.front(); q.pop(); for(int i=0;i<e[u].size();i++) { int v=e[u][i]; if(dis[v]!=-1) continue; dis[v]=dis[u]+1; q.push(v); } } } int mx[maxn],ans[maxn],ok[maxn]; vector<int> b[maxn]; void bfs2(int tt) { while(!q.empty()) { int u=q.front(); q.pop(); for(int i=0;i<e[u].size();i++) { int v=e[u][i]; if(ok[v]) continue; ans[v]=max(ans[v],tt); if(mx[v]>=mx[u]-1) continue; mx[v]=mx[u]-1; q.push(v); } } } signed main() { ios::sync_with_stdio(0); cin>>n; for(int i=1,u,v;i<n;i++) { cin>>u>>v; e[u].push_back(v); e[v].push_back(u); } cin>>m; memset(dis,-1,sizeof(dis)); for(int i=1;i<=m;i++) { cin>>a[i]; ok[a[i]]=1; dis[a[i]]=0; q.push(a[i]); } bfs(); for(int i=1;i<=n;i++) b[dis[i]].push_back(i),ans[i]=dis[i]; for(int i=n;i>=1;i--) { if(b[i].size()==0) continue; while(!q.empty()) q.pop(); // q.clear(); for(int j=0;j<b[i].size();j++) { q.push(b[i][j]); if(mx[b[i][j]]>=i-1) continue; mx[b[i][j]]=i-1; ans[b[i][j]]=max(i,ans[b[i][j]]); } bfs2(i); } for(int i=1;i<=n;i++) cout<<ans[i]<< ; cout<<endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_1_V
`define SKY130_FD_SC_MS__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_1_V
|
#include <bits/stdc++.h> using namespace std; long long int f(long long int a, long long int b) { long long int z = b, x = 0; while (z > 1) { z /= 2; x++; } long long int y = pow(2, x); if (a == b) return a; else if (y <= a) return f(a - y, b - y) + y; else if (pow(2, x + 1) - 1 <= b) return pow(2, x + 1) - 1; else return y - 1; } int main() { long long int i, n, a, b; cin >> n; while (n--) { cin >> a >> b; long long int x = f(a, b); cout << x << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; int a[N], n; double f(double x) { double sum = 0, mn = 0, mx = 0, ans = 0; for (int i = 0; i < n; i++) { mn = min(mn, sum); mx = max(mx, sum); sum += a[i] - x; ans = max(ans, abs(sum - mn)); ans = max(ans, abs(sum - mx)); } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; double l = -1e4 - 7, r = 1e4 + 7; int t = 230; while (t--) { double mid1 = (2 * r + l) / 3; double mid2 = (2 * l + r) / 3; if (f(mid1) < f(mid2)) l = mid2; else r = mid1; } cout << setprecision(9) << fixed << f(l) << endl; return 0; }
|
module Prescaler(ins_o,ins_i,icm_i,rst_i,clk_i);
output ins_o;
input ins_i;
input [2:0] icm_i;
input rst_i;
input clk_i;
reg ins_o;
reg next_ins_o_reg;
reg [4:0] threshold_reg;
reg [4:0] next_counter_reg;
reg [4:0] counter_reg;
//threshold:
always @(icm_i )
begin
case(icm_i )
'h1, 'h2, 'h3 :
begin
threshold_reg =('h1);
end
'h4, 'h6 :
begin
threshold_reg =('h4);
end
'h5, 'h7 :
begin
threshold_reg =('h10);
end
default:
begin
threshold_reg =('h0);
end
endcase
end
//on_change:
always @(threshold_reg or counter_reg or ins_i )
begin
if (counter_reg ==threshold_reg )
begin
next_ins_o_reg =(0);
next_counter_reg =(0);
end
else if (ins_i )
begin
next_ins_o_reg =(1);
next_counter_reg =(counter_reg +1);
end
end
//registers:
always @(posedge clk_i or posedge rst_i )
begin
if (!rst_i &&clk_i )
begin
counter_reg <=(next_counter_reg );
ins_o <=(next_ins_o_reg );
end
else
begin
counter_reg <=(0);
ins_o <=(0);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int b[200010]; map<int, long long> S; long long solve() { S.clear(); long long df, ans = 0; for (int i = 0; i < n; i++) { df = b[i] - i; S[df] += (long long)b[i]; } map<int, long long>::iterator it; for (it = S.begin(); it != S.end(); it++) ans = max(ans, it->second); return ans; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> b[i]; cout << solve() << endl; }
|
#include <bits/stdc++.h> using namespace std; template <typename tp> inline void read(tp& x) { x = 0; char tmp; bool key = 0; for (tmp = getchar(); !isdigit(tmp); tmp = getchar()) key = (tmp == - ); for (; isdigit(tmp); tmp = getchar()) x = (x << 3) + (x << 1) + (tmp ^ 0 ); if (key) x = -x; } template <typename tp> inline void ckmn(tp& x, tp y) { x = x < y ? x : y; } template <typename tp> inline void ckmx(tp& x, tp y) { x = x < y ? y : x; } const int N = 100010; struct edge { int la, b; } con[N << 1]; int tot, first[N]; void add_edge(int from, int to) { con[++tot] = (edge){first[from], to}; first[from] = tot; } int n, m; vector<int> ans; void clear() { tot = 0; for (int i = (1); i <= (n); ++i) first[i] = 0; } int key = 0; int dep[N], vis[N], inp[N], num[N], mnv[N], dp[N]; void dfs(int pos) { vis[pos] = 1; inp[pos] = 1; mnv[pos] = pos; for (int i = first[pos]; i; i = con[i].la) { if (vis[con[i].b]) { if (inp[con[i].b]) { if (dep[con[i].b] < dep[mnv[pos]]) mnv[pos] = con[i].b; ++num[pos]; --num[con[i].b]; } else key = 1; } else { dep[con[i].b] = dep[pos] + 1; dfs(con[i].b); num[pos] += num[con[i].b]; if (dep[mnv[con[i].b]] < dep[mnv[pos]]) mnv[pos] = mnv[con[i].b]; } } inp[pos] = 0; } void fsd(int pos) { vis[pos] = 1; if (dep[pos] > 0) { if (num[pos] == 1) { dp[pos] = dp[mnv[pos]]; } } for (int i = first[pos]; i; i = con[i].la) if (!vis[con[i].b]) fsd(con[i].b); } bool doit(int rt) { key = 0; for (int i = (1); i <= (n); ++i) vis[i] = 0; for (int i = (1); i <= (n); ++i) num[i] = 0; dfs(rt); if (key) return false; for (int i = (1); i <= (n); ++i) dp[i] = 0; dp[rt] = 1; for (int i = (1); i <= (n); ++i) vis[i] = 0; fsd(rt); for (int i = (1); i <= (n); ++i) if (dp[i]) ans.push_back(i); return true; } void solve() { int x, y; int sed = 0; read(n), read(m); for (int i = (1); i <= (m); ++i) { read(x), read(y); add_edge(x, y); sed = (sed + (long long)233 * x) % 998244353; } srand(sed); ans.clear(); for (int _ = (1); _ <= (100); ++_) { int rt = ((rand() << 16ll) | rand()) % n + 1; if (doit(rt)) break; } if ((int)ans.size() * 5 < n) { puts( -1 ); } else { for (int i = (0); i <= ((int)ans.size() - 1); ++i) printf( %d , ans[i]); puts( ); } clear(); } int main() { int T; read(T); while (T--) solve(); return 0; }
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (lin64) Build Thu Jun 15 18:39:10 MDT 2017
//Date : Wed Jul 5 01:27:13 2017
//Host : saturn running 64-bit Ubuntu 16.10
//Command : generate_target fmrv32im_artya7_wrapper.bd
//Design : fmrv32im_artya7_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module fmrv32im_artya7_wrapper
(CLK100MHZ,
GPIO_ot,
UART_rx,
UART_tx,
gpio_i,
gpio_o);
input CLK100MHZ;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
input [31:0]gpio_i;
output [31:0]gpio_o;
wire CLK100MHZ;
wire [31:0]GPIO_ot;
wire UART_rx;
wire UART_tx;
wire [31:0]gpio_i;
wire [31:0]gpio_o;
fmrv32im_artya7 fmrv32im_artya7_i
(.CLK100MHZ(CLK100MHZ),
.GPIO_i(gpio_i),
.GPIO_o(gpio_o),
.GPIO_ot(GPIO_ot),
.UART_rx(UART_rx),
.UART_tx(UART_tx));
endmodule
|
// part of NeoGS project
//
// (c) NedoPC 2007-2019
module chan_ctrl
(
input wire clk, // 24.0 MHz
input wire rst_n,
// memory interface
output reg [ 6:0] rd_addr,
input wire [31:0] rd_data,
//
output reg [ 6:0] wr_addr,
output wire [31:0] wr_data,
output reg wr_stb,
// 37500 Hz period strobe (1-cycle strobe)
input wire sync_stb,
// channel enables
input wire [31:0] ch_enas,
// output data
output reg [ 7:0] out_data,
output reg out_stb_addr, // strobes address sequence (addrhi/mid/lo)
output reg out_stb_mix // strobes mix sequence (frac/vl/vr)
// sequence: addrhi, addrmid, addrlo; frac, vl, vr (6 bytes)
);
reg [ 5:0] curr_ch; // current channel number
wire stop = curr_ch[5];
// channel fetch state machine
reg [3:0] st;
reg [3:0] next_st;
// channel enable
wire ch_ena = ch_enas[curr_ch[4:0]];
// offset storage
reg [31:0] offset;
reg off_cy; // extra carry [32th bit]
// offset>=size flag
reg oversize;
// volumes storage
reg [5:0] vol_left;
reg [5:0] vol_right;
// miscellaneous
reg loopena;
reg surround;
// base address
reg [21:0] base;
// emit control
reg [1:0] addr_emit;
///////////////////////
// states definition //
///////////////////////
localparam ST_BEGIN = 4'd0;
localparam ST_GETOFFS = 4'd1; // when offset value arrives
localparam ST_GETADDVOL = 4'd2; // whed add and volumes arrive
localparam ST_GETSIZE = 4'd3; // size and part of base address arrive
localparam ST_GETLOOP = 4'd4; // when loop and last part of base address arrive
localparam ST_SAVEOFFS = 4'd5;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
localparam ST_NEXT = 4'd14;
localparam ST_WAIT = 4'd15;
always @(posedge clk)
if( st==ST_WAIT )
curr_ch[5:0] <= 6'd0;
else if( st==ST_NEXT )
curr_ch[5:0] <= curr_ch[5:0] + 6'd1;
always @(posedge clk, negedge rst_n)
if( !rst_n )
st <= ST_WAIT;
else
st <= next_st;
//
always @*
case( st )
//////////////////////////////////////////////////////////////////////
ST_BEGIN:
if( stop )
next_st = ST_WAIT;
else if( !ch_ena )
next_st = ST_NEXT;
else
next_st = ST_GETOFFS;
///////////////////////////////////////////////////////////////////////
ST_GETOFFS:
next_st = ST_GETADDVOL;
///////////////////////////////////////////////////////////////////////
ST_GETADDVOL:
next_st = ST_GETSIZE;
///////////////////////////////////////////////////////////////////////
ST_GETSIZE:
next_st = ST_GETLOOP;
///////////////////////////////////////////////////////////////////////
ST_GETLOOP:
next_st = ST_SAVEOFFS;
///////////////////////////////////////////////////////////////////////
ST_SAVEOFFS:
next_st = ST_NEXT;
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ST_NEXT:
next_st = ST_BEGIN;
///////////////////////////////////////////////////////////////////////
ST_WAIT:
if( sync_stb )
next_st = ST_BEGIN;
else
next_st = ST_WAIT;
////////////////////////////////////////////////
///////////////////////
default: next_st = ST_WAIT;
///////////////////////////////////////////////////////////////////////
endcase
// state memory address control
always @*
rd_addr[6:2] <= curr_ch[4:0];
always @*
wr_addr[6:2] <= curr_ch[4:0];
always @(posedge clk)
wr_addr[1:0] <= 2'd0;
//
always @(posedge clk)
if( st==ST_NEXT || st==ST_WAIT )
begin
rd_addr[1:0] <= 2'd0;
end
else if( st==ST_BEGIN || st==ST_GETOFFS || st==ST_GETADDVOL )
begin
rd_addr[1:0] <= rd_addr[1:0] + 2'd1;
end
// offset register control
always @(posedge clk)
if( st==ST_GETOFFS )
offset <= rd_data;
else if( st==ST_GETADDVOL )
{off_cy, offset} <= {1'b0, offset} + {1'b0, 14'd0, rd_data[31:14]};
else if( st==ST_GETLOOP )
offset[31:12] <= oversize ? (offset[31:12]+rd_data[27:8]) : offset[31:12]; // TODO: or maybe rd_data & {20{oversize}} ?
// offset overflow control
always @(posedge clk)
if( st==ST_GETSIZE )
oversize <= ( {off_cy,offset[31:12]} >= {1'b0, rd_data[27:8]} );
// offset writeback
always @(posedge clk)
wr_stb <= st==ST_SAVEOFFS;
//
assign wr_data = offset;
// volumes and miscellaneous
always @(posedge clk)
if( st==ST_GETADDVOL )
begin
vol_left <= rd_data[11:6];
vol_right <= rd_data[ 5:0];
loopena <= rd_data[13];
surround <= rd_data[12];
end
// base address calc
always @(posedge clk)
if( st==ST_GETSIZE )
base[15:8] <= rd_data[7:0];
else if( st==ST_GETLOOP )
base[21:16] <= rd_data[5:0];
else if( st==ST_SAVEOFFS )
begin
base[7:0] <= offset[19:12];
base[21:8] <= base[21:8] + {2'd0,offset[31:20]};
end
// emitting data to fifos
always @(posedge clk, negedge rst_n)
if( !rst_n )
addr_emit <= 2'd0;
else
addr_emit[1:0] <= {addr_emit[0], st==ST_NEXT};
//
always @(posedge clk)
if( st==ST_GETSIZE )
out_data <= offset[11:4];
else if( st==ST_GETLOOP )
out_data <= {2'd0, vol_left[5:0]};
else if( st==ST_SAVEOFFS )
out_data <= {2'd0, vol_right[5:0] ^ {6{surround}}};
else if( st==ST_NEXT )
out_data <= {2'd0, base[21:16]};
else if( addr_emit[0] )
out_data <= base[15:8];
else
out_data <= base[7:0];
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_mix <= 1'b0;
else
out_stb_mix <= (st==ST_GETSIZE) ||
(st==ST_GETLOOP) ||
(st==ST_SAVEOFFS) ;
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_addr <= 1'b0;
else
out_stb_addr <= (st==ST_NEXT) || addr_emit;
endmodule
|
#include <bits/stdc++.h> const int maxn = 5e5 + 10; using namespace std; int main() { string s; long long n; cin >> n; while (n--) { cin >> s; int b = 0, e = s.size() - 1; while (b < e && s[b] == s[e]) b++, e--; if (b >= e) cout << s << n ; else { string s1, s2, cmax; for (int i = b; i <= e; i++) { s1 += s[i]; s2 = s1; reverse(s2.begin(), s2.end()); if (s1 == s2) cmax = s1; } string s3, s4, cmax2; for (int i = e; i >= b; i--) { s3 += s[i]; s4 = s3; reverse(s4.begin(), s4.end()); if (s3 == s4) cmax2 = s3; } if (cmax.size() > cmax2.size()) cout << s.substr(0, b) << cmax << s.substr(e + 1) << endl; else cout << s.substr(0, b) << cmax2 << s.substr(e + 1) << endl; } } }
|
#include <bits/stdc++.h> using namespace std; struct MCMF { using F = int; const static F INF = 0x3f3f3f3f; struct Edge { int v, bro; F cap, cost; Edge() {} Edge(int _v, int _bro, F _cap, F _cost) : v(_v), bro(_bro), cap(_cap), cost(_cost) {} }; vector<Edge> e; vector<int> pos, pre; vector<F> dis; vector<bool> trk; int n, s, t, m; MCMF(int _n, int _s, int _t) : n(_n), s(_s), t(_t), m(0) { pos.assign(n, -1); pre.resize(n); dis.resize(n); trk.resize(n); e.reserve(4e5); } void add(int u, int v, F cap = INF, F cost = 0) { assert(u < n && v < n); e.emplace_back(v, pos[u], cap, cost); pos[u] = m++; e.emplace_back(u, pos[v], 0, -cost); pos[v] = m++; } bool spfa() { queue<int> q; fill(pre.begin(), pre.end(), -1); fill(dis.begin(), dis.end(), INF); fill(trk.begin(), trk.end(), false); dis[s] = 0; trk[s] = true; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); trk[u] = false; for (int i = pos[u]; i != -1; i = e[i].bro) { int v = e[i].v; if (e[i].cap > 0 && dis[v] > dis[u] + e[i].cost) { dis[v] = dis[u] + e[i].cost; pre[v] = i; if (!trk[v]) { trk[v] = true; q.push(v); } } } } return pre[t] != -1; } pair<F, F> mcmf() { F flow = 0, cost = 0; while (spfa()) { F f = INF; for (int i = pre[t]; i != -1; i = pre[e[i ^ 1].v]) f = min(f, e[i].cap); for (int i = pre[t]; i != -1; i = pre[e[i ^ 1].v]) { e[i].cap -= f; e[i ^ 1].cap += f; cost += e[i].cost * f; } flow += f; } return {flow, cost}; } }; void solve() { int n1, n2, m, r, b; cin >> n1 >> n2 >> m >> r >> b; string s1, s2; cin >> s1 >> s2; int L = n1 + n2, R = L + 1; int S = R + 1, T = S + 1; MCMF g(T + 1, S, T); vector<int> deg(S), demand(S); for (int _ = 0; _ < m; _++) { int x, y; cin >> x >> y; x--; y--; y += n1; deg[x]++; deg[y]++; demand[x]++; demand[y]--; g.add(x, y, 1, r); g.add(y, x, 1, b); } auto gg = []() { cout << -1; exit(0); }; for (int i = 0; i < n1; i++) { if (s1[i] != U && deg[i] == 0) gg(); if (s1[i] == R ) { g.add(L, i, deg[i] - 1); demand[i] -= deg[i] + 1; demand[L] += deg[i] + 1; } else if (s1[i] == B ) { g.add(L, i, deg[i] - 1); } else { g.add(L, i, deg[i] << 1); } } for (int i = 0; i < n2; i++) { int k = i + n1; if (s2[i] != U && deg[k] == 0) gg(); if (s2[i] == B ) { g.add(k, R, deg[k] - 1); } else if (s2[i] == R ) { g.add(k, R, deg[k] - 1); demand[k] += deg[k] + 1; demand[R] -= deg[k] + 1; } else { g.add(k, R, deg[k] << 1); } } g.add(R, L); int sum = 0; for (int i = 0; i < S; i++) { if (demand[i] > 0) { sum += demand[i]; g.add(i, T, demand[i]); } if (demand[i] < 0) { g.add(S, i, -demand[i]); } } int flow, cost; tie(flow, cost) = g.mcmf(); if (flow < sum) gg(); cout << cost << n ; for (int i = 0; i < m; i++) { if (g.e[i * 4 + 1].cap) { cout << R ; } else if (g.e[i * 4 + 3].cap) { cout << B ; } else { cout << U ; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/VCC.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / VCC Connection
// /___/ /\ Filename : VCC.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module VCC(P);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output P;
assign P = 1'b1;
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_TB_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_nr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_1_V
`define SKY130_FD_SC_LP__A2111OI_1_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long double m, n, c = 0, k = 0, a = 0, b = 0, d; cin >> m >> n >> c >> d; long double s1, s2, x, y; a = (3 * m) / 10; b = m - (m / 250) * c; x = (3 * n) / 10; y = n - (n / 250) * d; s1 = max(a, b); s2 = max(x, y); if (s1 > s2) cout << Misha << endl; else if (s1 < s2) cout << Vasya << endl; else cout << Tie << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long L, R; int n; cin >> n; while (n--) { cin >> L >> R; for (long long k = 0; k <= 60; ++k) { if ((1LL << k) & (L)) { continue; } else { if ((1LL << k) + L <= R) { L += (1LL << k); } else { break; } } } cout << L << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; vector<int> v(n); vector<int> c(m + 5, 0); for (int i = 0; i < n; i++) { cin >> v[i]; } int l = 0, r = 0; int res = 1; c[v[0] - 1]++; int maxC = 1; int maxI = v[0] - 1; while (r < n) { if (c[v[r] - 1] > maxC) { maxC = c[v[r] - 1]; maxI = v[r] - 1; } if (c[v[l] - 1] > maxC) { maxC = c[v[l] - 1]; maxI = v[l] - 1; } if (r - l + 1 - maxC > k) { if (v[l] - 1 == maxI) { maxC--; } c[v[l] - 1]--; l++; } else if (r == n - 1) { break; } else { r++; c[v[r] - 1]++; if (c[v[r] - 1] > maxC) { maxC = c[v[r] - 1]; maxI = v[r] - 1; } if (r - l + 1 - maxC <= k) { res = max(res, maxC); } } } cout << res; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file snescmd_buf.v when simulating
// the core, snescmd_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module snescmd_buf(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [9 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// New Serial Core
// For Enterpoint Cairnsmore1 Icarus Derived Bitstream
// By Paul Mumby
// Licensed Under GNU GPL V3
//////////////////////////////////////////////////////////////////////////////////
module serial_core #(parameter CLOCK=25000000, BAUD=57600, SAMPLE_POINT=8)(
clk,
rx,
tx,
rx_ready,
tx_ready,
data1,
data2,
data3,
word,
tx_busy,
rx_busy
);
// IO Declaration
//===================================================
input clk;
input rx;
output tx;
output rx_ready;
input tx_ready;
output [255:0] data1;
output [255:0] data2;
output [127:0] data3;
input [31:0] word;
output tx_busy;
output rx_busy;
//Wire & Register Declaration
//===================================================
reg uart_tx_ready = 0;
wire uart_rx_ready;
wire uart_tx_busy;
wire uart_rx_busy;
wire uart_error;
reg [7:0] uart_tx_byte;
wire [7:0] uart_rx_byte;
reg [3:0] tx_mux_state = 4'b0000;
reg [31:0] tx_word_copy;
`ifdef SIM
// 76 byte protocol excludes nonce
reg [607:0] rx_input_buffer = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
reg [607:0] rx_input_buffer;
`endif
//Module Instantiation
//===================================================
wire unused_rx_error;
uart #(.CLOCK(CLOCK),.BAUD(BAUD),.SAMPLE_POINT(SAMPLE_POINT)) UART_CORE (
.clk(clk),
.rx_pin(rx),
.tx_pin(tx),
.tx_start(uart_tx_ready),
.rx_data_ready(uart_rx_ready),
.rx_busy(uart_rx_busy),
.tx_busy(uart_tx_busy),
.tx_byte(uart_tx_byte),
.rx_byte(uart_rx_byte),
.rx_error(unused_rx_error)
);
//Assignments
//===================================================
assign tx_busy = (|tx_mux_state);
`ifdef SIM
// 76 byte protocol excludes nonce
assign data3 = { 32'h0000318f, rx_input_buffer[607:512] }; // Load test nonce (match at ~1042uS)
`else
assign data3 = { 32'd0, rx_input_buffer[607:512] }; // Load zero nonce
`endif
assign data2 = rx_input_buffer[511:256];
assign data1 = rx_input_buffer[255:0];
assign rx_ready = uart_rx_ready;
//Logic
//===================================================
//TX Handler
always @(posedge clk)
begin
if (!tx_busy && tx_ready)
begin
tx_mux_state <= 4'b1000;
tx_word_copy <= word;
end
else if (tx_mux_state[3] && ~tx_mux_state[0] && !uart_tx_busy)
begin
uart_tx_ready <= 1;
tx_mux_state <= tx_mux_state + 1;
uart_tx_byte <= tx_word_copy[31:24];
tx_word_copy <= (tx_word_copy << 8);
end
else if (tx_mux_state[3] && tx_mux_state[0])
begin
uart_tx_ready <= 0;
if (!uart_tx_busy) tx_mux_state <= tx_mux_state + 1;
end
end
//RX Handler
always @(posedge clk)
begin
if(uart_rx_ready)
begin
rx_input_buffer <= rx_input_buffer << 8;
rx_input_buffer[7:0] <= uart_rx_byte;
end
else
rx_input_buffer <= rx_input_buffer;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2010; struct point { point(int xx, int yy) : x(xx), y(yy) {} int x, y; }; int n, m; char a[N][N]; queue<point> q; int dx[4] = {-1, 1, 0, 0}; int dy[4] = {0, 0, -1, 1}; long long pp; bool uniq(int xx, int yy) { if (a[xx][yy] != . ) { return false; } int counter = 0; for (int i = 0; i < 4; ++i) { int x = xx + dx[i]; int y = yy + dy[i]; if (a[x][y] == . ) { ++counter; } } return (counter == 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 0; i <= n + 1; ++i) { for (int j = 0; j <= m + 1; ++j) { if (i == 0 || j == 0 || i == n + 1 || j == m + 1) { a[i][j] = * ; continue; } cin >> a[i][j]; if (a[i][j] == . ) { ++pp; } } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (a[i][j] == * ) { continue; } int counter = 0; if (a[i][j + 1] == . ) { ++counter; } if (a[i][j - 1] == . ) { ++counter; } if (a[i - 1][j] == . ) { ++counter; } if (a[i + 1][j] == . ) { ++counter; } if (counter == 0) { cout << Not unique ; return 0; } if (counter == 1) { q.push(point(i, j)); } } } while (true) { if (q.empty()) { break; } point cur = q.front(); q.pop(); if (a[cur.x][cur.y] != . ) { continue; } if (!uniq(cur.x, cur.y)) { cout << Not unique ; return 0; } int xx = cur.x; int yy = cur.y; for (int i = 0; i < 4; ++i) { xx += dx[i]; yy += dy[i]; if (a[xx][yy] == . ) { break; } xx -= dx[i]; yy -= dy[i]; } if (yy == cur.y) { if (xx < cur.x) { a[cur.x][cur.y] = v ; a[xx][yy] = ^ ; } else { a[xx][yy] = v ; a[cur.x][cur.y] = ^ ; } } if (xx == cur.x) { if (yy < cur.y) { a[cur.x][cur.y] = > ; a[xx][yy] = < ; } else { a[cur.x][cur.y] = < ; a[xx][yy] = > ; } } pp -= 2; for (int i = 0; i < 4; ++i) { if (uniq(xx + dx[i], yy + dy[i])) { q.push(point(xx + dx[i], yy + dy[i])); } } } if (pp > 0) { cout << Not unique ; return 0; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cout << a[i][j]; } cout << endl; } return 0; }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_mcb_8
*/
module test_wb_mcb_8;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [31:0] wb_adr_i = 0;
reg [7:0] wb_dat_i = 0;
reg wb_we_i = 0;
reg wb_stb_i = 0;
reg wb_cyc_i = 0;
reg mcb_cmd_empty = 0;
reg mcb_cmd_full = 0;
reg mcb_wr_empty = 0;
reg mcb_wr_full = 0;
reg mcb_wr_underrun = 0;
reg [6:0] mcb_wr_count = 0;
reg mcb_wr_error = 0;
reg [31:0] mcb_rd_data = 0;
reg mcb_rd_empty = 0;
reg mcb_rd_full = 0;
reg mcb_rd_overflow = 0;
reg [6:0] mcb_rd_count = 0;
reg mcb_rd_error = 0;
// Outputs
wire [7:0] wb_dat_o;
wire wb_ack_o;
wire mcb_cmd_clk;
wire mcb_cmd_en;
wire [2:0] mcb_cmd_instr;
wire [5:0] mcb_cmd_bl;
wire [31:0] mcb_cmd_byte_addr;
wire mcb_wr_clk;
wire mcb_wr_en;
wire [3:0] mcb_wr_mask;
wire [31:0] mcb_wr_data;
wire mcb_rd_clk;
wire mcb_rd_en;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
wb_adr_i,
wb_dat_i,
wb_we_i,
wb_stb_i,
wb_cyc_i,
mcb_cmd_empty,
mcb_cmd_full,
mcb_wr_empty,
mcb_wr_full,
mcb_wr_underrun,
mcb_wr_count,
mcb_wr_error,
mcb_rd_data,
mcb_rd_empty,
mcb_rd_full,
mcb_rd_overflow,
mcb_rd_count,
mcb_rd_error);
$to_myhdl(wb_dat_o,
wb_ack_o,
mcb_cmd_clk,
mcb_cmd_en,
mcb_cmd_instr,
mcb_cmd_bl,
mcb_cmd_byte_addr,
mcb_wr_clk,
mcb_wr_en,
mcb_wr_mask,
mcb_wr_data,
mcb_rd_clk,
mcb_rd_en);
// dump file
$dumpfile("test_wb_mcb_8.lxt");
$dumpvars(0, test_wb_mcb_8);
end
wb_mcb_8
UUT (
.clk(clk),
.rst(rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_cyc_i(wb_cyc_i),
.mcb_cmd_clk(mcb_cmd_clk),
.mcb_cmd_en(mcb_cmd_en),
.mcb_cmd_instr(mcb_cmd_instr),
.mcb_cmd_bl(mcb_cmd_bl),
.mcb_cmd_byte_addr(mcb_cmd_byte_addr),
.mcb_cmd_empty(mcb_cmd_empty),
.mcb_cmd_full(mcb_cmd_full),
.mcb_wr_clk(mcb_wr_clk),
.mcb_wr_en(mcb_wr_en),
.mcb_wr_mask(mcb_wr_mask),
.mcb_wr_data(mcb_wr_data),
.mcb_wr_empty(mcb_wr_empty),
.mcb_wr_full(mcb_wr_full),
.mcb_wr_underrun(mcb_wr_underrun),
.mcb_wr_count(mcb_wr_count),
.mcb_wr_error(mcb_wr_error),
.mcb_rd_clk(mcb_rd_clk),
.mcb_rd_en(mcb_rd_en),
.mcb_rd_data(mcb_rd_data),
.mcb_rd_empty(mcb_rd_empty),
.mcb_rd_full(mcb_rd_full),
.mcb_rd_overflow(mcb_rd_overflow),
.mcb_rd_count(mcb_rd_count),
.mcb_rd_error(mcb_rd_error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int SINF = 0x7fffffff; const long long LINF = 0x3fffffffffffffff; const long long SLINF = 0x7fffffffffffffff; const int MAXN = 300007; const int MAX = 130; int n; int a[MAXN]; int ps[MAXN]; int pc[MAXN][2]; void init(); void input(); void work(); int main() { init(); input(); work(); } void init() { ios::sync_with_stdio(false); } void input() { scanf( %d , &n); long long x; for (int i = 1; i <= n; ++i) { scanf( %I64d , &x); a[i] = __builtin_popcountll(x); } } void work() { for (int i = 1; i <= n; ++i) ps[i] = ps[i - 1] + a[i]; int mx; long long ans = 0; for (int i = 1; i <= n; ++i) { int j = i - 1; mx = a[i]; for (; j && i - j <= MAX; --j) { mx = (((mx) > (a[j])) ? (mx) : (a[j])); if ((ps[i] & 1) == (ps[j - 1] & 1) && mx * 2 <= ps[i] - ps[j - 1]) ++ans; } ans += pc[j][ps[i] & 1]; pc[i][0] = pc[i - 1][0], pc[i][1] = pc[i - 1][1]; ++pc[i][ps[i - 1] & 1]; } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_2_V
`define SKY130_FD_SC_HD__A31OI_2_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:50:47 03/17/2011
// Design Name:
// Module Name: contador_a
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/* Contador de 9 bits. Cuenta desde 000h hasta 19Fh.
Toma como entrada la señal de reloj maestro, y su salida más
lenta es de 64us. Cuenta píxeles dentro de una línea */
module clineas(
input wire clk,
output wire [8:0] cnt
);
reg [8:0] contador = 9'b0;
assign cnt = contador;
always @(negedge clk)
contador <= (contador==9'h19f)? 9'b0 : contador+1;
endmodule
/* Contador de 9 bits, cuyo reloj es la salida mas lenta del contador anterior.
Cuenta líneas dentro de un campo. Su salida más lenta es de 50Hz. */
module cframes(
input wire clk,
output wire [8:0] cnt
);
reg [8:0] contador = 9'b0;
assign cnt = contador;
always @(negedge clk)
contador <= (contador==9'h137)? 9'b0 : contador+1;
endmodule
/* El contador maestro consta de los dos contadores anteriores, en cascada (ripple). */
module master_cnt(
input wire clk,
output wire [17:0] cnt
);
wire [8:0] ca;
wire [8:0] cb;
assign cnt = {cb,ca};
clineas cnta (clk, ca);
cframes cntb (ca[8], cb);
endmodule
/* El generador de sincronismos toma algunas de las salidas del contador maestro
para implementar los pulsos de sincronismo de línea y cuadro. */
module gensync(
input wire c5,
input wire c6,
input wire c7,
input wire c8,
input wire c12,
input wire c13,
input wire c14,
input wire c15,
input wire c16,
output wire intr,
output wire sync);
wire line, field;
assign line = ~(c5 | c7) & c6 & c8;
assign field = c12 & c13 & c14 & c15 & c16;
assign sync = ~(line | field);
assign intr = ~field;
endmodule
/* Control del teclado, altavoz, micrófono y señal EAR */
module io(
input wire clk,
input wire en254r,
input wire en254w,
input wire [4:0] kbd,
input wire ear,
input wire d3,
output wire [5:0] dout,
output wire mic,
output wire spk
);
reg ffmic;
reg ffspk;
reg [5:0] ear_y_teclado;
assign dout = (!en254r)? ear_y_teclado : 6'bzzzzzz;
assign mic = ffmic;
assign spk = ffspk;
always @(posedge clk)
ear_y_teclado <= {ear,kbd};
/* El micrófono se activa con el bit D3 en escritura */
always @(posedge clk)
if (!en254w)
ffmic <= d3;
/* Implementación del comportamiento del altavoz. */
always @(posedge clk)
if (!en254r)
ffspk <= 1;
else if (!en254w)
ffspk <= 0;
endmodule
module decodificador(
input wire [15:0] a,
input wire mreq,
input wire iorq,
input wire rd,
input wire wr,
output wire romce,
output wire ramce,
output wire xramce,
output wire vramdec,
output wire en254r,
output wire en254w
);
wire en254;
/* Ecuaciones del 74LS138 */
assign romce = mreq | a[15] | a[14] | a[13] | rd;
assign ramce = mreq | a[15] | a[14] | ~a[13] | ~a[12]; /* modelo básico con 1K de RAM */
assign xramce = mreq | a[15] | ~a[14]; /* ampliación de 16K de user RAM */
assign vramdec = mreq | a[15] | a[14] | ~a[13] | a[12];
assign en254 = iorq | a[0]; /* Decodificación parcial del puerto 254 */
assign en254r = en254 | rd;
assign en254w = en254 | wr;
endmodule
/* Módulo de generación de video y arbitrador de acceso a memoria */
module videogen_and_cpuctrl(
input wire clk,
input wire [15:0] a, /* bus de direcciones CPU */
input wire wr,
input wire vramdec, /* El procesador quiere acceder a la VRAM */
input wire [17:0] cnt, /* Las salidas del contador maestro */
input wire [7:0] DinShiftR, /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
input wire videoinverso, /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
output wire cpuwait, /* Salida WAIT al procesador */
output wire [9:0] ASRAMVideo, /* Al bus de direcciones de la RAM de pantalla */
output wire [2:0] ACRAMVideo, /* Al bus de direcciones de la RAM de caracteres */
output wire sramce, /* Habilitación de la RAM de pantalla */
output wire cramce, /* Habilitación de la RAM de caracteres */
output wire scramoe, /* OE de ambas RAM's: de pantalla y de caracteres */
output wire scramwr, /* WE de ambas RAM's: de pantalla y de caracteres */
output wire video /* Señal de video, sin sincronismos */
);
wire vhold;
wire viden;
wire shld;
reg ffvideoi; /* biestable para guardar el estado de pixel invertido */
reg envramab; /* señal resultante del lío con la resistencia y el diodo */
reg [7:0] shiftreg;
assign viden = ~(cnt[16] & cnt[15]) & (~(cnt[17] | cnt[8]));
assign vhold = ~(a[10] & viden);
assign cpuwait = vhold | vramdec;
/* Esto implementa lo del diodo y la resistencia para el 74LS367 */
always @(posedge clk)
if (vhold)
envramab <= vramdec;
else
envramab <= vramdec | envramab;
assign cramce = ~(a[11] | envramab);
assign sramce = ~(envramab | cramce);
assign scramwr = envramab | wr;
assign scramoe = ~scramwr;
assign ASRAMVideo = {cnt[16:12],cnt[7:3]};
assign ACRAMVideo = cnt[11:9];
always @(posedge clk)
if (&cnt[2:0])
ffvideoi <= (videoinverso & viden);
assign shld = ~(&cnt[2:0] & viden);
/* 74LS166. Registro serializador */
always @(posedge clk)
if (shld)
shiftreg <= shiftreg<<1;
else
shiftreg <= DinShiftR;
/* La señal serializada se pasa por una puerta XOR que la invierte o no */
assign video = (shiftreg[7] ^ ffvideoi);
endmodule
module jace(
input wire clkm,
input wire clk,
output wire cpuclk,
input wire [15:0] a, /* bus de direcciones CPU */
input wire d3,
output wire [5:0] dout, /* bus de datos de la CPU */
input wire wr,
input wire vramdec,
output wire intr,
output wire cpuwait, /* Salida WAIT al procesador */
input wire en254r,
input wire en254w,
output wire sramce, /* Habilitación de la RAM de pantalla */
output wire cramce, /* Habilitación de la RAM de caracteres */
output wire scramoe, /* OE de ambas RAM's: de pantalla y de caracteres */
output wire scramwr, /* WE de ambas RAM's: de pantalla y de caracteres */
input wire [7:0] DinShiftR, /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
input wire videoinverso, /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
output wire [9:0] ASRAMVideo, /* Al bus de direcciones de la RAM de pantalla */
output wire [2:0] ACRAMVideo, /* Al bus de direcciones de la RAM de caracteres */
input wire [4:0] kbd,
input wire ear,
output wire mic,
output wire spk,
output wire sync,
output wire video /* Señal de video, sin sincronismos */
);
wire [17:0] c;
assign cpuclk = c[0];
master_cnt cont (clk, c);
gensync gsync (c[5],c[6],c[7],c[8],c[12],c[13],c[14],c[15],c[16],intr,sync);
io modulo_io (
.clk(clkm),
.en254r(en254r),
.en254w(en254w),
.kbd(kbd),
.ear(ear),
.d3(d3),
.dout(dout),
.mic(mic),
.spk(spk)
);
videogen_and_cpuctrl arbitrador(
.clk(clk),
.a(a), /* bus de direcciones CPU */
.wr(wr),
.vramdec(vramdec), /* El procesador quiere acceder a la VRAM */
.cnt(c), /* Las salidas del contador maestro */
.DinShiftR(DinShiftR), /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
.videoinverso(videoinverso), /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
.cpuwait(cpuwait), /* Salida WAIT al procesador */
.ASRAMVideo(ASRAMVideo), /* Al bus de direcciones de la RAM de pantalla */
.ACRAMVideo(ACRAMVideo), /* Al bus de direcciones de la RAM de caracteres */
.sramce(sramce), /* Habilitación de la RAM de pantalla */
.cramce(cramce), /* Habilitación de la RAM de caracteres */
.scramoe(scramoe), /* OE de ambas RAM's: de pantalla y de caracteres */
.scramwr(scramwr), /* WE de ambas RAM's: de pantalla y de caracteres */
.video(video) /* Señal de video, sin sincronismos */
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int a[111]; int memo[111][1 << 17]; pair<pair<int, int>, int> child[111][1 << 17]; int bt[66]; class MathFunction { private: long long sieve_size; bitset<1010> bs; vector<int> primes; public: int primeid[1010]; bool isPrime(long long N) { if (N <= sieve_size) return bs[N]; for (int i = 0; i < (int)primes.size(); i++) if (N % primes[i] == 0) return false; return true; } void sieve(long long upperbound) { sieve_size = upperbound + 1; bs.set(); bs[0] = bs[1] = 0; for (long long i = 2; i < sieve_size; i++) { if (bs[i]) { for (long long j = i * i; j < sieve_size; j += i) bs[j] = 0; primeid[(int)i] = primes.size(); primes.push_back((int)i); } } } vector<int> primeFactors(long long N) { vector<int> factors; long long idx = 0, pf = primes[idx]; while (N != 1 && (pf * pf <= N)) { while (N % pf == 0) { N /= pf; factors.push_back(pf); } pf = primes[++idx]; } if (N != 1) factors.push_back(N); return factors; } }; MathFunction mat; int dp(int pos, int bitmask) { if (pos == n) return 0; if (memo[pos][bitmask] >= 0) return memo[pos][bitmask]; int q = abs(1 - a[pos]) + dp(pos + 1, bitmask); child[pos][bitmask] = pair<pair<int, int>, int>(pair<int, int>(pos + 1, bitmask), 1); for (int i = 2; i < a[pos] + a[pos]; i++) { if ((bitmask & bt[i]) == 0) { int d = abs(i - a[pos]) + dp(pos + 1, bitmask | bt[i]); if (d < q) { q = d; child[pos][bitmask] = pair<pair<int, int>, int>( pair<int, int>(pos + 1, bitmask | bt[i]), i); } } } return memo[pos][bitmask] = q; } void printAns(int pos, int bitmask) { if (pos == n) return; pair<int, int> nx = child[pos][bitmask].first; int val = child[pos][bitmask].second; printf( %d , val); printAns(nx.first, nx.second); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } mat.sieve(100); bt[1] = 0; for (int i = 2; i <= 61; i++) { vector<int> v = mat.primeFactors(i); int b = 0; for (int j = 0; j < v.size(); j++) { if (mat.primeid[v[j]] <= 15) b |= (1 << mat.primeid[v[j]]); } bt[i] = b; } memset(memo, -1, sizeof memo); dp(0, 0); printAns(0, 0); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_1_V
`define SKY130_FD_SC_MS__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_1_V
|
// chris_pipelined.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_pipelined (
input wire [7:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire ins_irq0_irq, // ins_irq0.irq
output wire [31:0] avm_m0_address, // avm_m0.address
output wire avm_m0_read, // .read
input wire avm_m0_waitrequest, // .waitrequest
input wire [31:0] avm_m0_readdata, // .readdata
input wire avm_m0_readdatavalid, // .readdatavalid
output wire avm_m0_write, // .write
output wire [31:0] avm_m0_writedata, // .writedata
output wire [7:0] avm_m0_burstcount // .burstcount
);
// TODO: Auto-generated HDL template
/* system template generated
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
assign avs_s0_waitrequest = 1'b0;
assign ins_irq0_irq = 1'b0;
assign avm_m0_address = 32'b00000000000000000000000000000000;
assign avm_m0_read = 1'b0;
assign avm_m0_write = 1'b0;
assign avm_m0_writedata = 32'b00000000000000000000000000000000;
assign avm_m0_burstcount = 8'b00000000;
*/
reg reg_status_read;
reg reg_status_write;
//data out
reg [31:0] reg_data_out;
assign avs_s0_readdata = reg_data_out;
//logic connect;
assign avs_s0_waitrequest = reg_status_read || reg_status_write;
// begin register map;
wire [8:0] s_kernel_parameter;
wire s_input_image_addr; //input image address
wire s_output_image_addr; // output image address
wire s_module_control; // system control address
wire s_module_status; // system status address
reg [31:0] reg_kernel[8:0];
reg [31:0] reg_source_addr;
reg [31:0] reg_destination_addr;
reg [31:0] reg_control;
reg [31:0] reg_status;
assign s_kernel_parameter[0] = (avs_s0_address[3:0] == 4'b0000) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[1] = (avs_s0_address[3:0] == 4'b0001) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[2] = (avs_s0_address[3:0] == 4'b0010) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[3] = (avs_s0_address[3:0] == 4'b0011) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[4] = (avs_s0_address[3:0] == 4'b0100) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[5] = (avs_s0_address[3:0] == 4'b0101) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[6] = (avs_s0_address[3:0] == 4'b0110) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[7] = (avs_s0_address[3:0] == 4'b0111) & (avs_s0_write | avs_s0_read);
assign s_kernel_parameter[8] = (avs_s0_address[3:0] == 4'b1000) & (avs_s0_write | avs_s0_read);
assign s_input_image_addr = (avs_s0_address[3:0] == 4'b1001) & (avs_s0_write | avs_s0_read);
assign s_output_image_addr= (avs_s0_address[3:0] == 4'b1010) & (avs_s0_write | avs_s0_read);
assign s_module_control = (avs_s0_address[3:0] == 4'b1011) & (avs_s0_write | avs_s0_read);
assign s_module_status = (avs_s0_address[3:0] == 4'b1100) & (avs_s0_write | avs_s0_read);
// end register map
//Get data form master
always @(posedge clock_clk)
if (reset_reset) begin
reg_kernel[0] <= 32'h000;
reg_kernel[1] <= 32'h000;
reg_kernel[2] <= 32'h000;
reg_kernel[3] <= 32'h000;
reg_kernel[4] <= 32'h000;
reg_kernel[5] <= 32'h000;
reg_kernel[6] <= 32'h000;
reg_kernel[7] <= 32'h000;
reg_kernel[8] <= 32'h000;
reg_source_addr <= 32'h0000;
reg_destination_addr <= 32'h0000;
reg_control <= 32'h0000;
reg_status <= 32'h0000;
reg_status_write <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
reg_status_write <= 1'b1;
if (s_kernel_parameter[0]) begin
reg_kernel[0] <= avs_s0_writedata;
end
if (s_kernel_parameter[1]) begin
reg_kernel[1] <= avs_s0_writedata;
end
if (s_kernel_parameter[2]) begin
reg_kernel[2] <= avs_s0_writedata;
end
if (s_kernel_parameter[3]) begin
reg_kernel[3] <= avs_s0_writedata;
end
if (s_kernel_parameter[4]) begin
reg_kernel[4] <= avs_s0_writedata;
end
if (s_kernel_parameter[5]) begin
reg_kernel[5] <= avs_s0_writedata;
end
if (s_kernel_parameter[6]) begin
reg_kernel[6] <= avs_s0_writedata;
end
if (s_kernel_parameter[7]) begin
reg_kernel[7] <= avs_s0_writedata;
end
if (s_kernel_parameter[8]) begin
reg_kernel[8] <= avs_s0_writedata;
end
if (s_input_image_addr) begin
reg_source_addr <= avs_s0_writedata;
end
if (s_output_image_addr) begin
reg_destination_addr <= avs_s0_writedata;
end
if (s_module_control) begin
reg_control <= avs_s0_writedata;
end
if (s_module_status) begin
reg_status <= avs_s0_writedata;
end
end
//return data to master
always @(posedge clock_clk) begin
if (reset_reset) begin
reg_data_out <= 32'h0000;
reg_status_read <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
reg_status_read <= 1'b1;
if (s_kernel_parameter[0]) begin
reg_data_out <= reg_kernel[0];
end
if (s_kernel_parameter[1]) begin
reg_data_out <= reg_kernel[1];
end
if (s_kernel_parameter[2]) begin
reg_data_out <= reg_kernel[2];
end
if (s_kernel_parameter[3]) begin
reg_data_out <= reg_kernel[3];
end
if (s_kernel_parameter[4]) begin
reg_data_out <= reg_kernel[4];
end
if (s_kernel_parameter[5]) begin
reg_data_out <= reg_kernel[5];
end
if (s_kernel_parameter[6]) begin
reg_data_out <= reg_kernel[6];
end
if (s_kernel_parameter[7]) begin
reg_data_out <= reg_kernel[7];
end
if (s_kernel_parameter[8]) begin
reg_data_out <= reg_kernel[8];
end
if (s_input_image_addr) begin
reg_data_out <= reg_source_addr;
end
if (s_output_image_addr) begin
reg_data_out <= reg_destination_addr;
end
if (s_module_control) begin
reg_data_out <= reg_control;
end
if (s_module_status) begin
reg_data_out <= reg_status;
end
end
end
// rest the master;
always @(posedge clock_clk) begin
if (reset_reset) begin
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, r, l[210000], t[210000], ans, a[110000], b, x, y, c; int main() { scanf( %I64d%I64d , &n, &r); for (int i = 1; i <= n; i++) scanf( %I64d , &l[i]); for (int i = 1; i <= n; i++) scanf( %I64d , &t[i]); for (int i = 1; i <= n; i++) if (t[i] < l[i]) { printf( -1 n ); return 0; } b = 0; c = 0; for (int i = 1; i <= n; i++) { if (l[i] <= b) { b -= l[i]; c += l[i]; } else { l[i] -= b; t[i] -= b; c += b; b = 0; x = 2 * l[i] - t[i]; if (x > 0) { y = (x - 1) / r + 1; if (ans + y <= 100000) { for (int j = 1; j <= y; j++) a[++ans] = c + t[i] - x + r * (j - 1); } else ans += y; b = (r - x % r) % r; c += t[i]; } else c += 2 * l[i]; } } printf( %I64d n , ans); if (ans <= 100000) { for (int i = 1; i < ans; i++) printf( %I64d , a[i]); if (ans) printf( %I64d , a[ans]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int inf = 10000000; int arr[100005]; map<int, int> mm; int main() { int n, k; cin >> n >> k; for (int i = 0; i < (n); i++) { cin >> arr[i]; mm[arr[i]] = 1; } sort(arr, arr + n); int ans = 0; for (int i = n - 1; i >= 0; i--) { if (mm[arr[i]] == 0) continue; if (arr[i] % k != 0) { ans++; continue; } if (mm.find(arr[i] / k) != mm.end()) mm[arr[i] / k] = 0; ans++; } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_fpu_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_fpu_cmp (
so,
dbginit_l,
cluster_grst_l,
rclk,
si,
se,
adbginit_l,
gdbginit_l,
arst_l,
grst_l,
cluster_cken,
gclk
);
output so;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si;
input se;
input adbginit_l;
input gdbginit_l;
input arst_l;
input grst_l;
input cluster_cken;
input gclk;
cluster_header I0 (
.rclk (rclk ),
.so (so ),
.dbginit_l (dbginit_l ),
.cluster_grst_l (cluster_grst_l ),
.si (si ),
.se (se ),
.adbginit_l (adbginit_l ),
.gdbginit_l (gdbginit_l ),
.arst_l (arst_l ),
.grst_l (grst_l ),
.cluster_cken (cluster_cken ),
.gclk (gclk )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9 + 7, mod = (int)1e9 + 9, pw = 31, N = (int)1e5 + 123, M = (int)1e6 + 123; const double eps = 1e-11; const unsigned long long inf = 5e18 + 1; unsigned long long n, a, b, x, m, ans; bool check = 0; unsigned long long binpow(unsigned long long a, unsigned long long b) { unsigned long long rec = 0; while (b) { if (b % 2) { rec = rec + a; b--; } else { a = a + a; b /= 2; } if (rec > n || a > n) { check = 1; return 0; } } return rec; } long long gcd(long long x, long long y) { return (y ? gcd(y, x % y) : x); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n >> a >> b; ans = min(n, min(a, b) - 1); m = binpow(a, b / gcd(a, b)); if (check) { cout << ans / gcd(ans, n) << / << n / gcd(ans, n); return 0; } ans += ((n / m) - 1) * min(a, b); ans += min((n / m) * m + min(a, b) - 1, n) - (n / m) * m + 1; cout << ans / gcd(ans, n) << / << n / gcd(ans, n); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input [8:0] dac_address_ext,
input play,
input reset,
input palmode,
output sdout,
output mclk_out,
output lrck_out,
output sclk_out,
output DAC_STATUS
);
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
`ifdef MK2
`ifndef DEBUG
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`endif
`ifdef MK3
dac_buf snes_dac_buf (
.clock(clkin),
.wren(~we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [10 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(dac_address), // Bus [8 : 0]
.q(dac_data)); // Bus [31 : 0]
`endif
reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
wire mclk = cnt[2]; // mclk = clk/8
wire lrck = cnt[8]; // lrck = mclk/64
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] mclk_sreg;
reg [2:0] lrck_sreg;
reg [1:0] sclk_sreg;
assign mclk_out = ~mclk_sreg[2];
assign lrck_out = lrck_sreg[2];
assign sclk_out = sclk_sreg[1];
wire lrck_rising = ({lrck_sreg[0],lrck} == 2'b01);
wire lrck_falling = ({lrck_sreg[0],lrck} == 2'b10);
wire sclk_rising = ({sclk_sreg[0],sclk} == 2'b01);
wire sclk_falling = ({sclk_sreg[0],sclk} == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b00;
sclk_sreg = 2'b00;
mclk_sreg = 2'b00;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 1232 = 44100 * 16
21281370 / 709379 * 23520 = 44100 * 16
*/
reg [19:0] phaseacc = 0;
wire [14:0] phasemul = (palmode ? 23520 : 1232);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
reg [3:0] subcount = 0;
reg int_strobe = 0, comb_strobe = 0;
always @(posedge clkin) begin
int_strobe <= 0;
comb_strobe <= 0;
if(reset) begin
dac_address_r <= dac_address_ext;
phaseacc <= 0;
subcount <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv + phasemul;
subcount <= subcount + 1;
int_strobe <= 1;
if (subcount == 0) begin
comb_strobe <= 1;
dac_address_r <= dac_address_r + play_r;
end
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
parameter ST0_IDLE = 10'b1000000000;
parameter ST1_COMB1 = 10'b0000000001;
parameter ST2_COMB2 = 10'b0000000010;
parameter ST3_COMB3 = 10'b0000000100;
parameter ST4_INT1 = 10'b0000010000;
parameter ST5_INT2 = 10'b0000100000;
parameter ST6_INT3 = 10'b0001000000;
reg [63:0] ci[2:0], co[2:0], io[2:0];
reg [9:0] cicstate = 10'h200;
wire [63:0] bufi = {{16{dac_data[31]}}, dac_data[31:16], {16{dac_data[15]}}, dac_data[15:0]};
always @(posedge clkin) begin
if(reset) begin
cicstate <= ST0_IDLE;
{ci[2], ci[1], ci[0]} <= 192'h0;
{co[2], co[1], co[0]} <= 192'h0;
{io[2], io[1], io[0]} <= 192'h0;
end else if(int_strobe) begin
if(comb_strobe) cicstate <= ST1_COMB1;
else cicstate <= ST4_INT1;
end else begin
case(cicstate)
/****** COMB STAGES ******/
ST1_COMB1: begin
cicstate <= ST2_COMB2;
ci[0] <= bufi;
co[0][63:32] <= bufi[63:32] - ci[0][63:32];
co[0][31:0] <= bufi[31:0] - ci[0][31:0];
end
ST2_COMB2: begin
cicstate <= ST3_COMB3;
ci[1] <= co[0];
co[1][63:32] <= co[0][63:32] - ci[1][63:32];
co[1][31:0] <= co[0][31:0] - ci[1][31:0];
end
ST3_COMB3: begin
cicstate <= ST4_INT1;
ci[2] <= co[1];
co[2][63:32] <= co[1][63:32] - ci[2][63:32];
co[2][31:0] <= co[1][31:0] - ci[2][31:0];
end
/****** INTEGRATOR STAGES ******/
ST4_INT1: begin
io[0][63:32] <= co[2][63:32] + io[0][63:32];
io[0][31:0] <= co[2][31:0] + io[0][31:0];
cicstate <= ST5_INT2;
end
ST5_INT2: begin
io[1][63:32] <= io[0][63:32] + io[1][63:32];
io[1][31:0] <= io[0][31:0] + io[1][31:0];
cicstate <= ST6_INT3;
end
ST6_INT3: begin
io[2][63:32] <= io[1][63:32] + io[2][63:32];
io[2][31:0] <= io[1][31:0] + io[2][31:0];
cicstate <= ST0_IDLE;
end
default: begin
cicstate <= ST0_IDLE;
end
endcase
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
mclk_sreg <= {mclk_sreg[1:0], mclk};
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? io[2][59:44] : io[2][27:12];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T x) { return x * x; } long double pi = 3.1415926535897932384626433832795; long long mod = 1e9 + 7; const int N = 1e6 + 10; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } vector<vector<long long> > e(int n) { vector<vector<long long> > res; for (int i = 0; i < n; i++) { vector<long long> v; for (int j = 0; j < n; j++) { if (i == j) v.push_back(1); else v.push_back(0); } res.push_back(v); } return res; } vector<vector<long long> > zero(int n, int m) { vector<vector<long long> > res; for (int i = 0; i < n; i++) { vector<long long> v; for (int j = 0; j < m; j++) { v.push_back(0); } res.push_back(v); } return res; } vector<vector<long long> > operator^(vector<vector<long long> > b, vector<vector<long long> > a) { int n = b.size(), m = a[0].size(), K = a.size(); vector<vector<long long> > c = zero(n, m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int k = 0; k < K; k++) { c[i][j] += b[i][k] * a[k][j]; c[i][j] %= mod; } } } return c; } vector<vector<long long> > bin_pow(vector<vector<long long> > a, long long pw) { int n = a.size(); vector<vector<long long> > res = e(n); while (pw) { if (pw & 1ll) res = res ^ a; a = a ^ a; pw >>= 1; } return res; } long long n, k; int main() { cin >> n >> k; vector<vector<long long> > ans = zero(1, 16); ans[0][0] = 1; for (int i = 0; i < n; i++) { long long a, b, c; cin >> a >> b >> c; b = min(b, k); long long pw = b - a; vector<vector<long long> > m = zero(c + 1, c + 1); ans[0].resize(c + 1); for (int i = 0; i <= c; i++) { for (int j = -1; j <= +1; j++) { int ni = i + j; if (ni < 0 || ni > c) continue; m[i][ni] = 1; } } m = bin_pow(m, pw); ans = ans ^ m; } cout << ans[0][0]; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int dist[100010], n; vector<pair<int, int> > gr[100010]; void dfs() { memset(dist, -1, sizeof(dist)); dist[1] = 0; queue<int> q; q.push(1); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < gr[u].size(); i++) { int next = gr[u][i].first; if (dist[next] == -1) { dist[next] = dist[u] + 1; q.push(next); } } } } vector<pair<int, pair<int, int> > > ans; int v_ans = 0; int dp[100010]; map<pair<int, int>, int> mark; int calc_dp(int u) { if (dp[u] != -1) return dp[u]; if (u == 1) return dp[u] = 0; for (int i = 0; i < gr[u].size(); i++) { int next = gr[u][i].first; if (dist[next] == dist[u] - 1) dp[u] = max(dp[u], calc_dp(next) + gr[u][i].second); } return dp[u]; } void calc_ans(int u) { if (u == 1) { return; } for (int i = 0; i < gr[u].size(); i++) { int next = gr[u][i].first; if (dist[next] == dist[u] - 1 && dp[next] == dp[u] - gr[u][i].second) { calc_ans(next); mark[{min(next, u), max(next, u)}] = 1; break; } } } int main() { ios::sync_with_stdio(false); memset(dp, -1, sizeof(dp)); int m; cin >> n >> m; int cont = 0; vector<pair<int, pair<int, int> > > edges; for (int i = 0; i < m; i++) { int a, b, z; cin >> a >> b >> z; cont += z; gr[a].push_back({b, z}); gr[b].push_back({a, z}); edges.push_back({z, {min(a, b), max(a, b)}}); } dfs(); int v = calc_dp(n); cout << (cont - v) + (dist[n] - v) << endl; calc_ans(n); for (int i = 0; i < m; i++) { if (edges[i].first == 1 && !mark[edges[i].second]) cout << edges[i].second.first << << edges[i].second.second << 0 n ; if (edges[i].first == 0 && mark[edges[i].second]) cout << edges[i].second.first << << edges[i].second.second << 1 n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int k = 0; while (1) { k++; if (k % m == 0) n++; n--; if (n == 0) break; } cout << k; return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arbiter
*/
module test_arbiter;
// Parameters
localparam PORTS = 32;
localparam ARB_TYPE_ROUND_ROBIN = 0;
localparam ARB_BLOCK = 1;
localparam ARB_BLOCK_ACK = 0;
localparam ARB_LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
request,
acknowledge
);
$to_myhdl(
grant,
grant_valid,
grant_encoded
);
// dump file
$dumpfile("test_arbiter.lxt");
$dumpvars(0, test_arbiter);
end
arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
.ARB_BLOCK_ACK(ARB_BLOCK_ACK),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
//-----------------------------------------------------
// Design Name : serial_crc_ccitt
// File Name : serial_crc.v
// Function : CCITT Serial CRC
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module serial_crc_ccitt (
clk ,
reset ,
enable ,
init ,
data_in ,
crc_out
);
//-----------Input Ports---------------
input clk ;
input reset ;
input enable ;
input init ;
input data_in ;
//-----------Output Ports---------------
output [15:0] crc_out;
//------------Internal Variables--------
reg [15:0] lfsr;
//-------------Code Start-----------------
assign crc_out = lfsr;
// Logic to CRC Calculation
always @ (posedge clk)
if (reset) begin
lfsr <= 16'hFFFF;
end else if (enable) begin
if (init) begin
lfsr <= 16'hFFFF;
end else begin
lfsr[0] <= data_in ^ lfsr[15];
lfsr[1] <= lfsr[0];
lfsr[2] <= lfsr[1];
lfsr[3] <= lfsr[2];
lfsr[4] <= lfsr[3];
lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];
lfsr[6] <= lfsr[5];
lfsr[7] <= lfsr[6];
lfsr[8] <= lfsr[7];
lfsr[9] <= lfsr[8];
lfsr[10] <= lfsr[9];
lfsr[11] <= lfsr[10];
lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
lfsr[13] <= lfsr[12];
lfsr[14] <= lfsr[13];
lfsr[15] <= lfsr[14];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = int(1e9) + 7; long long pom[2][2] = {{0, 1}, {1, 1}}; void mulMat(long long *A, long long *B, int n) { long long res[2][2] = {{0}}; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) { res[i][j] += (*(A + i * n + k)) * (*(B + k * n + j)); if (res[i][j] >= MOD) res[i][j] %= MOD; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) *(A + i * n + j) = res[i][j]; } void fastExp(long long pot, long long *T) { while (pot) { if (pot & 1) { mulMat(T, pom[0], 2); } mulMat(pom[0], pom[0], 2); pot >>= 1; } pom[0][0] = 0; pom[0][1] = 1; pom[1][0] = 1; pom[1][1] = 1; } struct Node { long long mat[2][2]; Node() { mat[0][0] = 1; mat[0][1] = 0; mat[1][0] = 0; mat[1][1] = 1; } Node(int pot) { mat[0][0] = 1; mat[0][1] = 0; mat[1][0] = 0; mat[1][1] = 1; fastExp(pot, mat[0]); } }; void zbrojiMat(long long *resMat, long long *op1, long long *op2) { for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { *(resMat + i * 2 + j) = (*(op1 + i * 2 + j) + *(op2 + i * 2 + j)); if (*(resMat + i * 2 + j) >= MOD) *(resMat + i * 2 + j) -= MOD; } } int n, m; struct Node zeroe; struct segTree { struct Node arr[1 << 18]; struct Node lazy[1 << 18]; int offset; struct Node neutralElem; void normalInit(int n) { for (offset = 1; offset < n; offset *= 2) ; for (int i = 0; i < 2 * offset; i++) { arr[i] = zeroe; lazy[i] = neutralElem; } } struct Node mergeValues(struct Node l, struct Node r) { struct Node n; zbrojiMat(n.mat[0], l.mat[0], r.mat[0]); return n; } segTree(int n) { normalInit(n); } segTree(int n, int *data) { normalInit(n); for (int i = offset; i < offset + n; i++) arr[i] = Node(*(data + i - offset)); for (int i = offset - 1; i >= 1; i--) arr[i] = mergeValues(arr[i * 2], arr[i * 2 + 1]); } void updateRange(int lo, int hi, long long *x) { update(1, 0, offset, lo, hi + 1, x); } struct Node query(int lo, int hi) { return q(1, 0, offset, lo, hi + 1); } private: void prop(int node) { mulMat(arr[node * 2].mat[0], lazy[node].mat[0], 2); mulMat(arr[node * 2 + 1].mat[0], lazy[node].mat[0], 2); mulMat(lazy[node * 2].mat[0], lazy[node].mat[0], 2); mulMat(lazy[node * 2 + 1].mat[0], lazy[node].mat[0], 2); lazy[node] = neutralElem; } void update(int node, int lo, int hi, int qlo, int qhi, long long *T) { if (lo >= qhi or hi <= qlo) return; if (lo >= qlo && hi <= qhi) { mulMat(arr[node].mat[0], T, 2); mulMat(lazy[node].mat[0], T, 2); return; } prop(node); int mid = (lo + hi) / 2; if (node < offset) { update(node * 2, lo, mid, qlo, qhi, T); update(node * 2 + 1, mid, hi, qlo, qhi, T); arr[node] = mergeValues(arr[node * 2], arr[node * 2 + 1]); } } struct Node q(int node, int lo, int hi, int qlo, int qhi) { if (lo >= qhi || hi <= qlo) return zeroe; if (lo >= qlo && hi <= qhi) return arr[node]; prop(node); int mid = (lo + hi) / 2; return mergeValues(q(node * 2, lo, mid, qlo, qhi), q(node * 2 + 1, mid, hi, qlo, qhi)); } }; const int MAX = 100005; int data[MAX]; int main() { double start = clock(); zeroe.mat[0][0] = 0; zeroe.mat[1][1] = 0; cin >> n >> m; for (int i = 0; i < n; i++) scanf( %d , &data[i]); segTree *T = new segTree(n, data); if (n == 99395) ; for (int i = 0; i < m; i++) { int id; scanf( %d , &id); int l, r; scanf( %d%d , &l, &r); l--; r--; if (id == 1) { int x; scanf( %d , &x); long long Ti[2][2] = {{1, 0}, {0, 1}}; fastExp(x, Ti[0]); T->updateRange(l, r, Ti[0]); } else { printf( %d n , T->query(l, r).mat[0][1]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, l; string s, s1, s2; int main() { cin >> n; getline(cin, s); while (n--) { getline(cin, s); s1 = ; s2 = ; l = s.length(); for (int i = 0; i <= 4; i++) s1 += s[i]; for (int i = l - 5; i < l; i++) s2 += s[i]; if (s1 == miao. && s2 != lala. ) cout << Rainbow s << endl; else if (s1 != miao. && s2 == lala. ) cout << Freda s << endl; else cout << OMG>.< I don t know! << endl; } return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
wire [width-1:0] test_expr_i = ~test_expr;
wire [width-1:0] test_expr_i_1 = test_expr_i - {{width-1{1'b0}},1'b1};
wire inactive_val=(inactive==`OVL_ALL_ONES)?1'b1:1'b0;
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if ((test_expr ^ test_expr)=={width{1'b0}}) begin
// OK, test_expr contains no X/Z.
if ((inactive>`OVL_ALL_ONES) || (test_expr!={width{inactive_val}})) begin
if (( test_expr_i == {width{1'b0}}) ||
((test_expr_i & test_expr_i_1) != {width{1'b0}})) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more or less than 1 deasserted bits");
end
end
end
else begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
reg [width-1:0] one_colds_checked;
reg [width-1:0] prev_one_colds_checked;
`ifdef OVL_SYNTHESIS
`else
initial begin
one_colds_checked = {width{1'b0}};
prev_one_colds_checked = {width{1'b0}};
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (test_expr != prev_test_expr) begin
if (OVL_COVER_SANITY_ON) begin //sanity coverage
ovl_cover_t("test_expr_change covered");
end //sanity coverage
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (inactive == `OVL_ALL_ZEROS) begin
if (test_expr == {width{inactive_val}}) begin
ovl_cover_t("test_expr_all_zeros covered");
end
end
if (inactive == `OVL_ALL_ONES) begin
if (test_expr == {width{inactive_val}}) begin
ovl_cover_t("test_expr_all_ones covered");
end
end
end //corner coverage
end //test_expr != prev_test_expr
prev_test_expr <= test_expr;
if (OVL_COVER_CORNER_ON) begin //corner coverage2
if ((test_expr ^ test_expr)=={width{1'b0}}) begin
if ((inactive>`OVL_ALL_ONES) || (test_expr!={width{inactive_val}})) begin
if (!((test_expr_i == {width{1'b0}}) ||
(test_expr_i & test_expr_i_1) != {width{1'b0}})) begin
one_colds_checked <= one_colds_checked | (~test_expr);
end
end
end
prev_one_colds_checked <= one_colds_checked;
if ( (prev_one_colds_checked != one_colds_checked) &&
(one_colds_checked == {width{1'b1}}) ) begin
ovl_cover_t("all_one_colds_checked covered");
end
end //corner coverage2
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
one_colds_checked <= {width{1'b0}};
prev_one_colds_checked <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; vector<int> computer(100, 0); int n, q, free_computers; long s; int t, k, d; void question() { cin >> t >> k >> d; free_computers = 0; for (int j = 0; j < n && free_computers < k; j++) { if (computer[j] <= t) free_computers++; } if (k > free_computers) cout << -1 << n ; else { s = 0; for (int j = 0; j < n && k != 0; j++) { if (computer[j] <= t) { k--; computer[j] = d + t; s += j + 1; } } cout << s << n ; } } int main() { cin >> n >> q; for (int i = 0; i < q; i++) question(); return 0; }
|
/***************************************************************
** Author: Oswaldo Cadenas ()
** Date: September 26 2011
**
** Test: Intended to test parametric counter in timebase.vhd
** the counter has parameters: N for counter length and
VALUE to flag when the count reaches this value
**
** Four counter instances are created here:
** duv1 with counter default parameters for N and VALUE
** duv2 with N1, V1 for parameter N, VALUE respectively
** duv3 with N2, V2 for parameters N, VALUE respectively
** duv4 with N2 replacing N and VALUE left as default
**
** The test for a long time making sure each of the four counter flags TICK become one
**************************************************************************************/
module test;
parameter integer T = 25;
parameter integer N1 = 8;
parameter integer N2 = 17;
parameter integer V1 = 200;
parameter integer V2 = 17'h16C8A;
bit clk = 0, reset = 0;
wire [11:0] count1;
wire [N1-1:0] count2;
wire [N2-1:0] count3;
wire [N2-1:0] count4;
wire tick1, tick2, tick3, tick4;
reg tick1_reg, tick2_reg, tick3_reg, tick4_reg;
initial forever #(T) clk = !clk;
initial begin
@(negedge clk);
reset = 1'b1;
repeat(6) @(negedge clk);
reset = 1'b0;
end
// duv1 switch
always @(posedge clk, posedge reset)
if (reset) tick1_reg <= 1'b0;
else if (tick1) tick1_reg <= 1'b1;
// duv2 switch
always @(posedge clk, posedge reset)
if (reset) tick2_reg <= 1'b0;
else if (tick2) tick2_reg <= 1'b1;
// duv3 switch
always @(posedge clk, posedge reset)
if (reset) tick3_reg <= 1'b0;
else if (tick3) tick3_reg <= 1'b1;
// duv4 switch
always @(posedge clk, posedge reset)
if (reset) tick4_reg <= 1'b0;
else if (tick4) tick4_reg <= 1'b1;
initial begin
#(V2*2*T + 1000);
if (tick1_reg != 1 || tick2_reg != 1 || tick3_reg != 1 || tick4_reg != 1) begin
$display ("Counting FAILED");
$finish;
end
else begin
$display ("PASSED");
#20;
$finish;
end
end
timebase duv1 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick1), .count_value(count1) ); // default parameters
timebase #(.n(N1), .value(V1))
duv2 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick2), .count_value(count2) ); // N1, V1 parameters
timebase #(N2, V2)
duv3 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick3), .count_value(count3) ); // N2, V2 parameters
timebase #(.n(N2))
duv4 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick4), .count_value(count4) ); // only one parameter modified
endmodule
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
`ifndef INCLUDE_ISA
`include "ISA.v"
`endif
module ID (
input wire clk, // Clock
input wire rst_n, // Asynchronous reset active low
// pipeline in
input wire [`WIDTH - 1:0] IR_in,
input wire [`WIDTH - 3:0] PC_in,
// pipeline out
output wire [`WIDTH - 1:0] IR_out,
output wire [`WIDTH - 3:0] PC_out,
output wire [`WIDTH - 1:0] X,
output wire [`WIDTH - 1:0] Y,
// Reg in/out
output reg [`REG_ADDR_LEN - 1:0] Rd1_addr,
input wire [`WIDTH - 1:0] Rd1_data,
output reg Rd1_en,
input wire Rd1_st,
output reg [`REG_ADDR_LEN - 1:0] Rd2_addr,
input wire [`WIDTH - 1:0] Rd2_data,
output reg Rd2_en,
input wire Rd2_st,
input wire IsStall,
input wire IsFlush
);
wire [5:0] OpCode;
wire [4:0] Rd;
wire [4:0] Rs;
wire [4:0] Rt;
wire [4:0] Shamt;
wire [15:0] Imm;
wire [25:0] Tgt;
reg [`WIDTH-1:0] X_reg;
reg [`WIDTH-1:0] Y_reg;
assign OpCode = IR_in[31:26];
assign Rd = IR_in[25:21];
assign Rs = IR_in[20:16];
assign Rt = IR_in[15:11];
assign Shamt = IR_in[10:6];
assign Imm = IR_in[15:0];
assign Tgt = IR_in[25:0];
assign IR_out = (IsStall === 1)?IR_out:((IsFlush === 1)?`NOP:IR_in);
assign PC_out = (IsStall === 1)?PC_out:((IsFlush === 1)?`NOP:PC_in);
assign X = (Rd1_en == 1)? Rd1_data : Tgt;
assign Y = (Rd2_en == 1)? Rd2_data : sext16(Imm);
/*always @(negedge clk) begin
if(IsStall) begin
end else if(IsFlush) begin
//IR_out = `NOP;
end else begin
//IR_out = IR_in;
//PC_out = PC_in;
end
end
*/
always @(IR_out or PC_out) begin
Rd1_en = 0;
Rd2_en = 0;
case(OpCode)
`R_TYPE: begin
Rd1_addr <= Rs;
Rd1_en <= 1;
Rd2_addr <= Rt;
Rd2_en <= 1;
end
`I_TYPE, `LW, `LH, `LD: begin
Rd1_addr <= Rs;
Rd1_en <= 1;
//Y <= sext16(Imm);
end
`Branch: begin
Rd1_addr <= Rd;
Rd1_en <= 1;
//Y <= sext16(Imm);
end
`SD, `SH, `SW: begin
Rd1_addr <= Rd;
Rd1_en <= 1;
Rd2_addr <= Rs;
Rd2_en <= 1;
end
`J_TYPE: begin
//X <= Tgt;
end
`NOP: begin
end
`HALT: begin
end
endcase
end
always @(posedge Rd1_st) begin
//X = Rd1_data;
//Rd1_en = 0;
end
always @(posedge Rd2_st) begin
//Y = Rd2_data;
//Rd2_en = 0;
end
function [`WIDTH-1:0] sext16(
input [15:0] d_in);
begin
sext16[`WIDTH-1:0] = {{(`WIDTH-16){d_in[15]}}, d_in};
end
endfunction
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_regf(
input sys_clk,
input sys_rst,
/* ALU interface */
output reg ifb,
output [31:0] a,
output [31:0] b,
input [31:0] r,
input w_en,
/* Program Memory interface */
input [6:0] a_addr,
input [6:0] b_addr,
input [6:0] w_addr,
/* CSR interface */
input c_en,
input [6:0] c_addr,
output [31:0] c_do,
input [31:0] c_di,
input c_w_en,
/* Address Generator interface */
input [31:0] r0,
input [31:0] r1,
output err_stray
);
/* Triple-port RAM for most of the registers.
* R0 and R1 are overlaid on top of it.
*/
wire [6:0] p1_a;
wire [31:0] p1_d;
wire [6:0] p2_a;
wire [31:0] p2_d;
wire p3_en;
wire [6:0] p3_a;
wire [31:0] p3_d;
pfpu_tpram tpram(
.sys_clk(sys_clk),
.p1_a(p1_a),
.p1_d(p1_d),
.p2_a(p2_a),
.p2_d(p2_d),
.p3_en(p3_en),
.p3_a(p3_a),
.p3_d(p3_d)
);
/* Port 1 (RO) - Shared between ALU and CSR interface */
assign p1_a = c_en ? c_addr : a_addr;
reg p1_bram_en;
reg p1_overlay_en;
reg [31:0] p1_overlay;
always @(posedge sys_clk) begin
p1_bram_en <= 1'b0;
p1_overlay_en <= 1'b1;
if(p1_a == 7'd0) p1_overlay <= r0;
else if(p1_a == 7'd1) p1_overlay <= r1;
else begin
p1_bram_en <= 1'b1;
p1_overlay_en <= 1'b0;
p1_overlay <= 32'bx;
end
end
assign a = ({32{p1_bram_en}} & p1_d)|({32{p1_overlay_en}} & p1_overlay);
assign c_do = a;
/* Port 2 (RO) - Dedicated to ALU */
assign p2_a = b_addr;
reg p2_bram_en;
reg p2_overlay_en;
reg [31:0] p2_overlay;
always @(posedge sys_clk) begin
p2_bram_en <= 1'b0;
p2_overlay_en <= 1'b1;
if(p2_a == 7'd0) p2_overlay <= r0;
else if(p2_a == 7'd1) p2_overlay <= r1;
else begin
p2_bram_en <= 1'b1;
p2_overlay_en <= 1'b0;
p2_overlay <= 32'bx;
end
end
assign b = ({32{p2_bram_en}} & p2_d)|({32{p2_overlay_en}} & p2_overlay);
/* Port 3 (WO) - Shared between ALU and CSR interface */
assign p3_en = c_en ? c_w_en : w_en;
assign p3_a = c_en ? c_addr : w_addr;
assign p3_d = c_en ? c_di : r;
/* Catch writes to R2 and update the IF Branch */
always @(posedge sys_clk) begin
if(p3_en) begin
if(p3_a == 7'd2)
ifb <= p3_d != 32'd0;
end
end
/* Catch writes to register 0 */
assign err_stray = p3_en & (p3_a == 7'd0);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k, cnt = 0, ans; string s; vector<int> arr; int main(void) { ios ::sync_with_stdio(0); cin.tie(0); cin >> n >> a >> b >> k >> s; for (int i = 1; i <= n; ++i) { if (s[i - 1] == 0 ) { ++cnt; } else { cnt = 0; } if (cnt == b) { arr.emplace_back(i); cnt = 0; } } ans = int(arr.size()) - (a - 1); cout << ans << n ; for (int i = 0; i <= ans - 1; ++i) { cout << arr[i] << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, ans[100001], curr, deg[100001] = {0}; vector<pair<int, int>> adj[100001]; void dfs(long long u, long long p) { for (auto v : adj[u]) { if (v.first == p) { continue; } if (ans[v.second] == -1) { ans[v.second] = curr++; } dfs(v.first, u); } } void solve() { long long n; cin >> n; long long m; cin >> m; if (n > m || n % 2 != m % 2) { cout << -1 << endl; return; } if (n == m && n == 0) { cout << n << endl; return; } if (n == m) { cout << 1 << endl << n << endl; return; } long long x = (m - n) / 2; if ((x & n) == 0) { cout << 2 << endl << n + x << << x << endl; return; } { cout << 3 << endl << n << << x << << x << endl; return; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; solve(); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 6e5; const int oo = 1e9 + 5; int du[] = {-1, 0, 0, 1}; int dv[] = {0, -1, 1, 0}; const long long mod = 1e9 + 7; long long sqr(long long x) { return x * x; } int n, x, a[N + 5], ans; bool vis[N + 5]; int main() { ios_base::sync_with_stdio(false); cin >> n >> x; vis[x] = true; for (int i = 1; i < (1 << n); i++) { if (!vis[i]) a[ans++] = i; vis[i ^ x] = vis[i] = true; } cout << ans << endl; for (int i = 1; i <= ans; i++) cout << (a[i] ^ a[i - 1]) << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s1, s2; while (cin >> n) { vector<string> array(4); array[0] = |#.#.#.#.#.#.#.#.#.#.#.|D|) ; array[3] = |#.#.#.#.#.#.#.#.#.#.#.|.|) ; array[1] = |#.#.#.#.#.#.#.#.#.#.#.|.| ; array[2] = |#.......................| ; s1 = array[0].size() - 5, s2 = array[2].size() - 4; cout << +------------------------+ << endl; for (int j = 1; j < s1; j += 2) { for (long long i = 0; i < 4; i++) { if (!i || i == 3 && n) { if (!n) goto bara; else array[i][j] = O , n--; } else if (j == 1 && i == 2 && n) array[i][j] = O , n--; else if (i == 1 && n) if (!n) goto bara; else array[i][j] = O , n--; else if (!n) goto bara; } } bara:; for (long long i = 0; i < 4; i++) cout << array[i] << endl; cout << +------------------------+ << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(int test_number); int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.setf(ios::fixed); cout.precision(9); cerr.setf(ios::fixed); cerr.precision(3); int n = 1; for (int i = 0; i < n; i++) { solve(i); } } const int MAX_N = 300005; int n, n_edge, deg[MAX_N]; int point[MAX_N], head[MAX_N], next_edge[MAX_N]; bool line[MAX_N]; void add_edge(int u, int v) { point[n_edge] = v, next_edge[n_edge] = head[u], head[u] = n_edge++; point[n_edge] = u, next_edge[n_edge] = head[v], head[v] = n_edge++; } bool is_line(int u, int p) { int cnt = 0; for (int i = head[u]; i >= 0; i = next_edge[i]) { int v = point[i]; if (v == p) { continue; } if (!line[v]) { return false; } cnt++; if (cnt > 2) { return false; } } return true; } bool good(int u, int p, int lim) { int cnt = 0, all = 0; for (int i = head[u]; i >= 0; i = next_edge[i]) { int v = point[i]; if (v == p) { continue; } if (is_line(v, u)) { cnt++; } else if (!good(v, u, 1)) { return false; } all++; } if (all - cnt <= lim) { return true; } return false; } void dfs_line(int u, int p) { int cnt = 0, lst = -1; for (int i = head[u]; i >= 0; i = next_edge[i]) { int v = point[i]; if (v == p) { continue; } cnt++; lst = v; dfs_line(v, u); } if (cnt == 0 || (cnt == 1 && line[lst])) { line[u] = true; } } void solve(int test_number) { cin >> n; memset(head, -1, sizeof(head)); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; --u, --v; add_edge(u, v); deg[u]++; deg[v]++; } for (int root = 0; root < min(n, 50); root++) { memset(line, false, sizeof(line)); dfs_line(root, -1); if (good(root, -1, 2) || is_line(root, -1)) { cout << Yes << endl; return; } } cout << No << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
`ifdef ENABLE_SPLIT_VAR
`define SPLIT_VAR_COMMENT /* verilator split_var */
`else
`define SPLIT_VAR_COMMENT
/* verilator lint_off UNOPTFLAT */
`endif
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire o0;
wire [15:0] vec_i = crc[15:0];
wire [31:0] i = crc[31:0];
Test test(/*AUTOINST*/
// Outputs
.o0 (o0),
// Inputs
.clk (clk),
.i (i[1:0]));
// Aggregate outputs into a single result vector
// verilator lint_off WIDTH
wire [63:0] result = {o0};
// verilator lint_on WIDTH
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("o %b", o0);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb58b16c592557b30
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
o0,
// Inputs
clk, i
);
input wire clk;
input wire [1:0] i;
output reg o0;
typedef struct packed {
logic v0, v1;
} packed_type0;
packed_type0 value0 `SPLIT_VAR_COMMENT;
wire value0_v0;
assign value0.v0 = i[0];
assign value0.v1 = i[1] & !value0_v0;
assign value0_v0 = value0.v0;
always_ff @(posedge clk) begin
o0 <= |value0;
end
endmodule
`ifdef ENABLE_SPLIT_VAR
/* verilator lint_on UNOPTFLAT */
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_4_V
`define SKY130_FD_SC_HD__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_4_V
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (a == 0) { return b; } if (b == 0) { return a; } return gcd(b, a % b); } long long int power(long long int x, long long int n) { long long ans = 1; while (n > 0) { if (n & 1) ans = (ans * x) % 1000000007; x = (x * x) % 1000000007; n /= 2; } if (x == 0) ans = 0; return ans; } long long int getsum(int g, int a[], int n, int x) { long long int i = n - 1, tmp = 0, k = g, count = 0; while (i >= 0) { while (k != 0 && i >= 0) { tmp += max((long long)0, (a[i] - count)); i--; k--; } count++; k = g; } return tmp; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { int n, m, i; cin >> n >> m; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int lo = 1, hi = n, mid; while (lo < hi) { mid = lo + (hi - lo) / 2; long long int tmp = getsum(mid, a, n, m); if (tmp < m) { lo = mid + 1; } else { hi = mid; } } if (getsum(lo, a, n, m) >= m) { cout << lo; } else { cout << -1; } } }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_width (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIDTH";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if ((max_cks > 0) && (min_cks > max_cks)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal parameter values set where min_cks > max_cks");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_width_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_width_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_width_psl_logic.v"
`else
`endmodule // ovl_width
`endif
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops ) using namespace std; const long long large = 1e11, remi2 = 998244353; const long long remi = 1e9 + 7, inf = LLONG_MAX; const long double Pi = acos(-1); long long PowI(long long a, long long b, long long m) { long long ans = 1 % m; while (b > 0) { if (b % 2) ans = (((ans % m) * (a % m)) % m); a = (((a % m) * (a % m)) % m); b = (long long)(b / ((long long)2)); } return ans; } void Foxtrot() { long long n, k; cin >> n >> k; vector<long long> v(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); long long sum = 0; for (int i = 0; i < (n - (2 * k)); i++) { sum += v[i]; } for (long long i = n - 2 * k; i < (n - k); i++) { sum += (v[i] / v[i + k]); } cout << sum << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long T = 1; cin >> T; for (int i = 1; i < T + 1; i++) { Foxtrot(); } return 0; }
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (lin64) Build Thu Jun 15 18:39:10 MDT 2017
//Date : Fri Jun 23 10:19:08 2017
//Host : dshwdev running 64-bit Ubuntu 16.04.2 LTS
//Command : generate_target fmrv32im_artya7_wrapper.bd
//Design : fmrv32im_artya7_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module fmrv32im_artya7_wrapper
(CLK100MHZ,
GPIO_ot,
UART_rx,
UART_tx,
gpio_i,
gpio_o);
input CLK100MHZ;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
input [31:0]gpio_i;
output [31:0]gpio_o;
wire CLK100MHZ;
wire [31:0]GPIO_ot;
wire UART_rx;
wire UART_tx;
wire [31:0]gpio_i;
wire [31:0]gpio_o;
fmrv32im_artya7 fmrv32im_artya7_i
(.CLK100MHZ(CLK100MHZ),
.GPIO_i(gpio_i),
.GPIO_o(gpio_o),
.GPIO_ot(GPIO_ot),
.UART_rx(UART_rx),
.UART_tx(UART_tx));
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[101], res; int b[101]; int main() { int n, i, k, t; cin >> n >> k; for (i = 0; i < n; i++) { cin >> t; a[t]++; } while (1) { for (i = 1; i <= k; i++) b[i] = 0; t = 0; for (i = 1; i < k; i++) if (a[i] > 0) { a[i]--; b[i + 1]++; t = 1; } res++; for (i = 1; i <= k; i++) a[i] += b[i]; if (!t) break; } cout << res - 1 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple, single clock, simple dual port (SCSDP) ram
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
module scsdpram
#(
parameter C_WIDTH = 32,
parameter C_DEPTH = 1024
)
(
input CLK,
input RD1_EN,
input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
output [C_WIDTH-1:0] RD1_DATA,
input WR1_EN,
input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
input [C_WIDTH-1:0] WR1_DATA
);
`include "functions.vh"
reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
reg [C_WIDTH-1:0] rDataOut;
assign RD1_DATA = rDataOut;
always @(posedge CLK) begin
if (WR1_EN) begin
rMemory[WR1_ADDR] <= #1 WR1_DATA;
end
if(RD1_EN) begin
rDataOut <= #1 rMemory[RD1_ADDR];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 2 * acos(0.0); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rng_64(chrono::steady_clock::now().time_since_epoch().count()); const string DIGITS = 0123456789 ; const string ALPH = abcdefghijklmnopqrstuvwxyz ; template <class T0, class T1> inline ostream &operator<<(ostream &out, pair<T0, T1> &a) { return out << { << a.first << , << a.second << } ; } template <class T0, class T1, class T2> inline ostream &operator<<(ostream &out, tuple<T0, T1, T2> &a) { return out << { << get<0>(a) << , << get<1>(a) << , << get<2>(a) << } ; } template <class T0, class T1, class T2, class T3> inline ostream &operator<<(ostream &out, tuple<T0, T1, T2, T3> &a) { return out << { << get<0>(a) << , << get<1>(a) << , << get<2>(a) << , << get<3>(a) << } ; } template <class T> inline ostream &operator<<(ostream &out, vector<T> &a) { out << [ ; for (int i = 0; i < (int)(a.size()); ++i) out << a[i] << vector<string>{ , , ] }[i + 1 == a.size()]; return out; } void smain(); signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << setprecision(10) << fixed; smain(); return 0; } const int N = 510; int n, m; vector<string> t; vector<vector<int> > glav[4]; void kek(char p, int u) { vector<vector<int> > a(n, vector<int>(m)); auto b = a, c = a; for (int i = 0; i < n; i++) { int u = 0; string s = t[i]; for (int j = 0; j < m; j++) { if (s[j] == p) { a[i][j] = 1; u++; } else { a[i][j] = 0; u = 0; } b[i][j] = u; } } for (int i = 0; i < m; i++) { int u = 0; for (int j = n - 1; j >= 0; j--) { if (a[j][i] == 1) u++; else u = 0; c[j][i] = u; } } vector<vector<int> > ans(n, vector<int>(m)); for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < m; j++) { if (a[i][j] == 0) continue; if (j == 0 || i == n - 1) { ans[i][j] = 1; } else { int v = min(b[i][j], c[i][j]); ans[i][j] = min(ans[i + 1][j - 1] + 1, v); } } } glav[u] = ans; } int flex[N][N]; int lol[N][N][251]; int get(int r, int c, int k) { if (r < 0 || c < 0) return 0; return lol[r][c][k]; } int get(int r1, int c1, int r2, int c2, int k) { return get(r2, c2, k) - get(r1 - 1, c2, k) - get(r2, c1 - 1, k) + get(r1 - 1, c1 - 1, k); } void smain() { int q; cin >> n >> m >> q; string s; for (int i = 0; i < n; i++) { cin >> s; t.push_back(s); } kek( G , 0); kek( R , 1); kek( B , 2); kek( Y , 3); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int k = 1;; k++) { if (i + k >= n || j - k < 0) break; if (glav[0][i][j] >= k && glav[1][i][j - k] >= k && glav[2][i + k][j] >= k && glav[3][i + k][j - k] >= k) { flex[i][j] = k; } } } } for (int k = 1; k <= 250; k++) { for (int i = 0; i < n; i++) { int prev = 0; for (int j = 0; j < m; j++) { prev += (flex[i][j] == k); if (i) { lol[i][j][k] += lol[i - 1][j][k]; } lol[i][j][k] += prev; } } } while (q--) { int r1, c1, r2, c2; cin >> r1 >> c1 >> r2 >> c2; r1--; c1--; r2--; c2--; swap(c1, c2); int l = 0, r = 251; while (l + 1 < r) { int mid = l + r >> 1; int r3 = r2 - mid * 2 + 1; int c3 = c2 + mid * 2 - 1; bool flag = true; if (r3 < r1 || c3 > c1) flag = false; if (flag) { if (get(r1, c3, r3, c1, mid) == 0) flag = false; } if (flag) l = mid; else r = mid; } cout << 1LL * l * 2 * l * 2 << n ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Alex Solomatnikov.
interface hex2ram_if
(
input bit trigger
);
string instance_path = $sformatf("%m");
string testfile = "";
bit has_testfile = |($value$plusargs("testfile=%s", testfile));
bit armed = 1'b1;
bit armed_trigger;
initial begin
$display("successfully bound hex2ram_if to %s", instance_path);
armed = has_testfile && 1'b1;
end
assign armed_trigger = armed && trigger;
always @(posedge armed_trigger) begin
$display("%m(%0t): saw deassertion of reset", $time);
end
endinterface : hex2ram_if
module t
(
clk
);
input clk /*verilator clocker*/;
bit reset;
wire success;
SimpleTestHarness testHarness
(
.clk(clk),
.reset(reset),
.io_success(success)
);
integer cyc=0;
always @ (posedge clk) begin
cyc = cyc + 1;
if (cyc<10) begin
reset <= '0;
end
else if (cyc<20) begin
reset <= '1;
end
else if (cyc<30) begin
reset <= '0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset));
module testharness_ext
(
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [127:0] W0_data,
input [0:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [127:0] R0_data
);
reg [24:0] reg_R0_addr;
wire [127:0] R0_rdata_mask;
reg [127:0] ram [33554431:0];
wire [127:0] W0_wdata_mask;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask;
end
assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;;
assign R0_rdata_mask = 0;
assign W0_wdata_mask = 0;
endmodule
module SimpleTestHarness
(
input clk,
input reset,
output io_success);
wire [24:0] testharness_ext_R0_addr;
wire testharness_ext_R0_en;
wire testharness_ext_R0_clk;
wire [127:0] testharness_ext_R0_data;
wire [24:0] testharness_ext_W0_addr;
wire testharness_ext_W0_en;
wire testharness_ext_W0_clk;
wire [127:0] testharness_ext_W0_data;
wire [0:0] testharness_ext_W0_mask;
testharness_ext testharness_ext
(
.R0_addr(testharness_ext_R0_addr),
.R0_en(testharness_ext_R0_en),
.R0_clk(testharness_ext_R0_clk),
.R0_data(testharness_ext_R0_data),
.W0_addr(testharness_ext_W0_addr),
.W0_en(testharness_ext_W0_en),
.W0_clk(testharness_ext_W0_clk),
.W0_data(testharness_ext_W0_data),
.W0_mask(testharness_ext_W0_mask)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b, c; int main() { ios_base::sync_with_stdio(false); cin >> n >> a >> b >> c; if (n == 1) cout << 0 << endl; else if (c >= min(a, b)) cout << (n - 1) * min(a, b) << endl; else cout << min(a, b) + (n - 2) * c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int ansx, ansy; int a[300005][10]; int b[300005]; int check(long long x) { memset(b, 0, sizeof(b)); for (int i = 1; i <= n; i++) { int p = 0; for (int j = 1; j <= m; j++) { if (a[i][j] >= x) p += (1 << (j - 1)); } b[p] = i; } int k = (1 << m); int c = (1 << m) - 1; for (int i = 0; i <= k; i++) { for (int j = 0; j <= k; j++) { if (b[i] && b[j] && ((i | j) == c)) { ansx = b[i]; ansy = b[j]; return 1; } } } return 0; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); } } long long l = 0, r = 1e9; while (l <= r) { long long mid = (l + r) / 2; if (check(mid)) { l = mid + 1; } else { r = mid - 1; } } printf( %d %d n , ansx, ansy); }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool cmin(T &a_, T b_) { return a_ > b_ ? (a_ = b_, true) : false; } template <class T> bool cmax(T &a_, T b_) { return a_ < b_ ? (a_ = b_, true) : false; } template <class T> void OUT(T s_) { cout << s_ << n ; exit(0); } const int maxn = 1.0001e6; const long long mod = 998244353; long long n; long long gt[maxn]; long long power(long long a, long long b) { if (!b) return 1LL; long long c = power(a, b >> 1); c *= c; c %= mod; if (b & 1) { c *= a; c %= mod; } return c; } long long f(long long a, long long b) { if (a == b) return 1; return (gt[a] * power((gt[b] * gt[a - b]) % mod, mod - 2)) % mod; } void Fan_chipu() { cin >> n; gt[0] = 1; for (int i = (int)(1); i <= (int)(maxn - 1); ++i) gt[i] = gt[i - 1] * i, gt[i] %= mod; long long ans = 0LL; for (int i = (int)(0); i <= (int)(n); ++i) { ans += (f(n, i) * (((gt[i] - i + mod) * gt[n - i]) % mod)) % mod; ans %= mod; } cout << ans % mod << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); cout << fixed; Fan_chipu(); }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int maxn = 4; template <class T> struct Matrix { int r, c; T a[maxn][maxn]; Matrix() { memset(a, 0, sizeof a); } Matrix(int si) { memset(a, 0, sizeof a); r = c = si; for (int i = 0; i < si; i++) a[i][i] = 1; } Matrix operator*(Matrix &rhs) { Matrix<T> ret; ret.r = r; ret.c = rhs.c; for (int k = 0; k < c; ++k) for (int i = 0; i < ret.r; ++i) for (int j = 0; j < ret.c; ++j) ret.a[i][j] = (ret.a[i][j] + (long long)a[i][k] * rhs.a[k][j]) % mod; return ret; } Matrix operator^(long long b) { Matrix<T> ret, base = *this; int setret = 0; while (b) { if (b & 1) ret = (setret ? ret * base : base), setret = 1; base = base * base; b >>= 1; } return ret; } }; int P[1000000]; int KMP(string A, string B) { int l = A.length(); A = A + # + B; P[0] = -1; int x = -1, ret = 0; for (int i = (1); i < (A.length()); ++i) { while (x >= 0 && A[x + 1] != A[i]) x = P[x]; if (A[x + 1] == A[i]) x++; P[i] = x; if (P[i] == l - 1) ret++; } return ret; } Matrix<int> M; string fs[30]; string instr; long long k; int go() { if (k < 30) return KMP(instr, fs[k]); string A, B; int I; for (int i = 1; i < 30; i++) { if (fs[i].length() >= instr.length()) { B = fs[i + 1]; A = fs[i]; I = i; break; } } long long CA = KMP(instr, A); long long CB = KMP(instr, B); long long CBA = KMP(instr, B + A) - CB - CA; long long CAB = KMP(instr, A + B) - CA - CB; long long CBB = KMP(instr, B + B) - CB - CB; Matrix<int> co, POW; co.r = 1; co.c = 4; co.a[0][1] = 1; POW = M ^ (k - I - 1); co = co * POW; return (co.a[0][0] * (CBA + CA) + co.a[0][1] * CB + co.a[0][2] * CAB + co.a[0][3] * CBB) % mod; } int main() { ios_base::sync_with_stdio(0); M.r = M.c = 4; M.a[0][1] = M.a[0][2] = M.a[1][0] = M.a[1][1] = M.a[2][3] = M.a[3][2] = 1; fs[1] = a ; fs[2] = b ; for (int i = 3; i < 30; ++i) fs[i] = fs[i - 1] + fs[i - 2]; int m; cin >> k >> m; while (m--) { cin >> instr; cout << go() << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 4000; long long p[MAXN + 10], v[MAXN + 10], d[MAXN + 10]; bool lft[MAXN + 10]; int n; void print(int n) { for (int i = 0; i < n; i++) cout << p[i] << ; cout << endl; for (int i = 0; i < n; i++) cout << lft[i] << ; cout << endl; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> v[i] >> d[i] >> p[i]; int res = 0; for (int i = 0; i < n; i++) { if (lft[i]) continue; res++; long long f = 0, effect = 0; for (int j = i + 1; j < n; j++) { if (lft[j]) continue; p[j] -= max(0ll, v[i] - f++); p[j] -= effect; if (p[j] < 0) { lft[j] = true; effect += d[j]; } } } cout << res << endl; for (int i = 0; i < n; i++) if (!lft[i]) cout << i + 1 << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; vector<long long> arr; void solve() { cin >> n >> m >> k; arr.resize(n); for (long long i = 0; i < n; i++) cin >> arr[i]; vector<long long> b; long long l = arr[n - 1] - arr[0]; ; for (int i = 1; i < n; i++) { b.push_back(arr[i] - arr[i - 1]); } sort(b.begin(), b.end()); long long i = b.size() - 1; int ctr = k - 1; for (; ctr > 0; i--, ctr--) { l -= b[i]; l += 1; } l++; cout << l << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); struct Item { int c; int x; Item() : c(), x() {} Item(int _c, int _x) : c(_c), x(_x) {} }; const long long INF = (long long)1e16; const int N = 505; int n, m, k; vector<Item> a[N][N]; vector<Item> b[N][N]; long long s[N][N]; long long dp[N][N]; int DX[] = {0, 1, 1, 0}; int DY[] = {0, -1, 0, 1}; int main() { scanf( %d%d%d , &n, &m, &k); while (k--) { int x, y, d, t, c; scanf( %d%d%d%d%d , &x, &y, &d, &t, &c); vector<pair<int, int> > cur; for (int i = 0; i < 4; i++) { int xx = x + d * DX[i], yy = y + d * DY[i]; int tt = xx + yy; if (tt < t || (tt - t) % 4 != i) continue; cur.push_back(make_pair(xx, yy)); } if ((int)cur.size() > 2) throw; for (int i = 0; i < (int)cur.size(); i++) { s[cur[i].first][cur[i].second] += c; if (i == 1) { if (cur[0].first == cur[1].first) a[cur[1].first][cur[1].second].push_back(Item(c, cur[0].second)); else if (cur[0].second == cur[1].second) b[cur[1].first][cur[1].second].push_back(Item(c, cur[0].first)); } } } for (int x = 0; x < n; x++) for (int y = 0; y < m; y++) dp[x][y] = INF; dp[0][0] = 0; for (int x = 0; x < n; x++) for (int y = 0; y < m; y++) { long long w; w = dp[x][y]; for (int xx = x + 1; xx < n; xx++) { for (Item I : b[xx][y]) { if (I.x >= x) w -= I.c; } w += s[xx][y]; dp[xx][y] = min(dp[xx][y], w); } w = dp[x][y]; for (int yy = y + 1; yy < m; yy++) { for (Item I : a[x][yy]) { if (I.x >= y) w -= I.c; } w += s[x][yy]; dp[x][yy] = min(dp[x][yy], w); } } printf( %lld n , dp[n - 1][m - 1]); return 0; }
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/*
* Copyright (c) 2000 Yasuhisa Kato <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module drvz( clk, iA, iC, ioS );
input clk, iA, iC ;
inout ioS ;
assign ioS = (iC) ? iA : 'bz ;
endmodule
module main;
reg clk, c ;
initial begin clk = 0 ; forever #5 clk = ~clk ; end
initial begin c = 0 ; #40 $finish(0); end
wire a, b, s ;
assign a = 'b0 ;
assign b = 'b1 ;
always @(posedge clk) c <= ~c ;
drvz M ( clk, a, c, s ) ;
drvz N ( clk, b, ~c, s ) ; // line(A)
always @(posedge clk)
$display("%b %b %b", s, a, b );
endmodule
// expected output
// 1 0 1
// 0 0 1
// 1 0 1
// 0 0 1
// ivl 0.3 result
// x 0 1
// 0 0 1
// x 0 1
// 0 0 1
|
#include <bits/stdc++.h> using namespace std; vector<int> vec[201], v[201]; int afis[201], scor[201], n, test[201]; bool viz[201]; void elim(int val) { for (int i = 0; i < v[val].size(); i++) scor[v[val][i]]--; } bool incearca(int start) { int i, j; for (i = 1; i <= n; i++) { scor[i] = vec[i].size(); viz[i] = 0; } afis[1] = vec[start][0]; elim(vec[start][0]); afis[2] = vec[start][1]; elim(vec[start][1]); viz[vec[start][0]] = viz[vec[start][1]] = 1; for (int i = 3; i <= n; i++) { int cnt = 0; for (j = 1; j < n; j++) if (scor[j] == 1) cnt++; if (cnt >= 2 || cnt == 0) return 0; for (j = 1; j < n; j++) if (scor[j] == 1) { for (int k = 0; k < vec[j].size(); k++) if (!viz[vec[j][k]]) { viz[vec[j][k]] = 1; elim(vec[j][k]); afis[i] = vec[j][k]; break; } cnt = 0; for (int k = i; k >= i - vec[j].size() + 1; k--) test[++cnt] = afis[k]; sort(test + 1, test + cnt + 1); for (int a = 1, b = 0; b < vec[j].size(); a++, b++) if (test[a] != vec[j][b]) return 0; break; } if (j == n) return 0; } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t, i, k, j, a; cin >> t; while (t--) { cin >> n; for (i = 1; i <= n; i++) { vec[i].clear(); v[i].clear(); } for (i = 1; i < n; i++) { cin >> k; for (j = 1; j <= k; j++) { cin >> a; v[a].push_back(i); vec[i].push_back(a); } } for (i = 1; i < n; i++) if (vec[i].size() == 2) { if (incearca(i)) break; swap(vec[i][0], vec[i][1]); if (incearca(i)) break; swap(vec[i][0], vec[i][1]); } for (i = 1; i <= n; i++) cout << afis[i] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string a, b, tem; scanf( %d , &n); a = <3 ; for (int i = 0, j = 0; i < n; ++i) { cin >> tem; a += tem; a += <3 ; } cin >> b; int len1 = a.length(), po1 = 0, po2 = 0; int len2 = b.length(); while (1) { if (po1 == len1) { printf( yes n ); return 0; } if (po2 == len2) { printf( no n ); return 0; } if (a[po1] == b[po2]) po1++; po2++; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_SYMBOL_V
`define SKY130_FD_SC_HD__A21BO_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[1000005]; long long c[2000015]; long long n; int main() { ios_base::sync_with_stdio(0); cin >> n; long long ma = 0; for (int i = 0; i < n; i++) { cin >> a[i]; c[a[i]]++; ma = max(ma, a[i]); } long long ans = 0; for (int i = 0; i < 2000010; i++) { if (c[i] % 2 == 1) { c[i + 1] += c[i] / 2; c[i] = 1; } else { c[i + 1] += c[i] / 2; c[i] = 0; } } for (int i = 0; i < 2000010; i++) { ans += c[i]; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> a; char op[3]; long long res; void Gao(vector<long long> a) { if (a.size() == 1) { if (res == -1) res = a[0]; else res = min(res, a[0]); return; } vector<long long> tmp; for (int i = 0; i < a.size(); i++) for (int j = i + 1; j < a.size(); j++) { tmp.clear(); for (int k = 0; k < a.size(); k++) if (k != i && k != j) tmp.push_back(a[k]); if (op[4 - a.size()] == + ) tmp.push_back(a[i] + a[j]); else tmp.push_back(a[i] * a[j]); Gao(tmp); } } int main() { a.resize(4); for (int i = 0; i < 4; i++) cin >> a[i]; for (int i = 0; i < 3; i++) scanf( %c , &op[i]); res = -1; Gao(a); cout << res << endl; return 0; }
|
module ibex_fetch_fifo (
clk_i,
rst_ni,
clear_i,
in_valid_i,
in_ready_o,
in_addr_i,
in_rdata_i,
in_err_i,
out_valid_o,
out_ready_i,
out_addr_o,
out_rdata_o,
out_err_o
);
parameter [31:0] NUM_REQS = 2;
input wire clk_i;
input wire rst_ni;
input wire clear_i;
input wire in_valid_i;
output wire in_ready_o;
input wire [31:0] in_addr_i;
input wire [31:0] in_rdata_i;
input wire in_err_i;
output reg out_valid_o;
input wire out_ready_i;
output wire [31:0] out_addr_o;
output reg [31:0] out_rdata_o;
output reg out_err_o;
localparam [31:0] DEPTH = (NUM_REQS + 1);
wire [(((DEPTH - 1) >= 0) ? (((((DEPTH - 1) >= 0) ? DEPTH : (2 - DEPTH)) * 32) + -1) : ((((0 >= (DEPTH - 1)) ? (2 - DEPTH) : DEPTH) * 32) + (((DEPTH - 1) * 32) - 1))):(((DEPTH - 1) >= 0) ? 0 : ((DEPTH - 1) * 32))] rdata_d;
reg [(((DEPTH - 1) >= 0) ? (((((DEPTH - 1) >= 0) ? DEPTH : (2 - DEPTH)) * 32) + -1) : ((((0 >= (DEPTH - 1)) ? (2 - DEPTH) : DEPTH) * 32) + (((DEPTH - 1) * 32) - 1))):(((DEPTH - 1) >= 0) ? 0 : ((DEPTH - 1) * 32))] rdata_q;
wire [(DEPTH - 1):0] err_d;
reg [(DEPTH - 1):0] err_q;
wire [(DEPTH - 1):0] valid_d;
reg [(DEPTH - 1):0] valid_q;
wire [(DEPTH - 1):0] lowest_free_entry;
wire [(DEPTH - 1):0] valid_pushed;
wire [(DEPTH - 1):0] valid_popped;
wire [(DEPTH - 1):0] entry_en;
wire pop_fifo;
wire [31:0] rdata;
wire [31:0] rdata_unaligned;
wire err;
wire err_unaligned;
wire valid;
wire valid_unaligned;
wire aligned_is_compressed;
wire unaligned_is_compressed;
wire addr_incr_two;
wire [31:1] instr_addr_d;
reg [31:1] instr_addr_q;
wire instr_addr_en;
wire unused_addr_in;
assign rdata = (valid_q[0] ? rdata_q[((((DEPTH - 1) >= 0) ? 0 : (DEPTH - 1)) * 32)+:32] : in_rdata_i);
assign err = (valid_q[0] ? err_q[0] : in_err_i);
assign valid = (valid_q[0] | in_valid_i);
assign rdata_unaligned = (valid_q[1] ? {rdata_q[((((DEPTH - 1) >= 0) ? 1 : (-1 + (DEPTH - 1))) * 32)+:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]});
assign err_unaligned = (valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) : ((valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))));
assign valid_unaligned = (valid_q[1] ? 1'b1 : (valid_q[0] & in_valid_i));
assign unaligned_is_compressed = (rdata[17:16] != 2'b11);
assign aligned_is_compressed = (rdata[1:0] != 2'b11);
always @(*)
if (out_addr_o[1]) begin
out_rdata_o = rdata_unaligned;
out_err_o = err_unaligned;
if (unaligned_is_compressed)
out_valid_o = valid;
else
out_valid_o = valid_unaligned;
end
else begin
out_rdata_o = rdata;
out_err_o = err;
out_valid_o = valid;
end
assign instr_addr_en = (clear_i | (out_ready_i & out_valid_o));
assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed);
assign instr_addr_d = (clear_i ? in_addr_i[31:1] : (instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}));
always @(posedge clk_i)
if (instr_addr_en)
instr_addr_q <= instr_addr_d;
assign out_addr_o[31:1] = instr_addr_q[31:1];
assign out_addr_o[0] = 1'b0;
assign unused_addr_in = in_addr_i[0];
assign in_ready_o = ~valid_q[(DEPTH - NUM_REQS)];
assign pop_fifo = ((out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]));
generate
genvar g_fifo_next_i;
for (g_fifo_next_i = 0; (g_fifo_next_i < (DEPTH - 1)); g_fifo_next_i = (g_fifo_next_i + 1)) begin : g_fifo_next
if ((g_fifo_next_i == 0)) begin : g_ent0
assign lowest_free_entry[g_fifo_next_i] = ~valid_q[g_fifo_next_i];
end
else begin : g_ent_others
assign lowest_free_entry[g_fifo_next_i] = (~valid_q[g_fifo_next_i] & valid_q[(g_fifo_next_i - 1)]);
end
assign valid_pushed[g_fifo_next_i] = ((in_valid_i & lowest_free_entry[g_fifo_next_i]) | valid_q[g_fifo_next_i]);
assign valid_popped[g_fifo_next_i] = (pop_fifo ? valid_pushed[(g_fifo_next_i + 1)] : valid_pushed[g_fifo_next_i]);
assign valid_d[g_fifo_next_i] = (valid_popped[g_fifo_next_i] & ~clear_i);
assign entry_en[g_fifo_next_i] = ((valid_pushed[(g_fifo_next_i + 1)] & pop_fifo) | ((in_valid_i & lowest_free_entry[g_fifo_next_i]) & ~pop_fifo));
assign rdata_d[((((DEPTH - 1) >= 0) ? g_fifo_next_i : (0 - (g_fifo_next_i - (DEPTH - 1)))) * 32)+:32] = (valid_q[(g_fifo_next_i + 1)] ? rdata_q[((((DEPTH - 1) >= 0) ? (g_fifo_next_i + 1) : (0 - ((g_fifo_next_i + 1) - (DEPTH - 1)))) * 32)+:32] : in_rdata_i);
assign err_d[g_fifo_next_i] = (valid_q[(g_fifo_next_i + 1)] ? err_q[(g_fifo_next_i + 1)] : in_err_i);
end
endgenerate
assign lowest_free_entry[(DEPTH - 1)] = (~valid_q[(DEPTH - 1)] & valid_q[(DEPTH - 2)]);
assign valid_pushed[(DEPTH - 1)] = (valid_q[(DEPTH - 1)] | (in_valid_i & lowest_free_entry[(DEPTH - 1)]));
assign valid_popped[(DEPTH - 1)] = (pop_fifo ? 1'b0 : valid_pushed[(DEPTH - 1)]);
assign valid_d[(DEPTH - 1)] = (valid_popped[(DEPTH - 1)] & ~clear_i);
assign entry_en[(DEPTH - 1)] = (in_valid_i & lowest_free_entry[(DEPTH - 1)]);
assign rdata_d[((((DEPTH - 1) >= 0) ? (DEPTH - 1) : (0 - ((DEPTH - 1) - (DEPTH - 1)))) * 32)+:32] = in_rdata_i;
assign err_d[(DEPTH - 1)] = in_err_i;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
valid_q <= 1'sb0;
else
valid_q <= valid_d;
generate
genvar g_fifo_regs_i;
for (g_fifo_regs_i = 0; (g_fifo_regs_i < DEPTH); g_fifo_regs_i = (g_fifo_regs_i + 1)) begin : g_fifo_regs
always @(posedge clk_i)
if (entry_en[g_fifo_regs_i]) begin
rdata_q[((((DEPTH - 1) >= 0) ? g_fifo_regs_i : (0 - (g_fifo_regs_i - (DEPTH - 1)))) * 32)+:32] <= rdata_d[((((DEPTH - 1) >= 0) ? g_fifo_regs_i : (0 - (g_fifo_regs_i - (DEPTH - 1)))) * 32)+:32];
err_q[g_fifo_regs_i] <= err_d[g_fifo_regs_i];
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:58:59 04/05/2017
// Design Name:
// Module Name: Timing
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Timing(
output reg bunch_strb,
input store_strb,
input clk,
input [7:0] b1_strobe,
input [7:0] b2_strobe,
input [1:0] no_bunches,
input [3:0] no_samples,
input [7:0] sample_spacing,
output reg LUTcond
);
//parameter no_bunches=2;
//parameter no_samples=1;
//parameter sample_spacing=100; // Number of samples between consecutive bunches
reg [4:0] bunch_counter=0;
initial bunch_strb=0;
(* equivalent_register_removal = "no"*) reg [7:0] i;
reg [7:0] start_bunch_strb=0;
reg [7:0] end_bunch_strb=0;
//reg LUTcond;
// ***** Generate bunch strobe *****
reg strbA = 1'b0, strbB = 1'b0, strbC = 1'b0;//, strbD =1'b0;
always @ (posedge clk) begin
strbA <= (b2_strobe==i);
strbB <= (b2_strobe+sample_spacing==i);
strbC <= (strbA || strbB);
//strbD <= strbC;
LUTcond <= strbC;
//LUTcond<=i==b2_strobe+3|| i== b2_strobe+sample_spacing+3;
if (store_strb) begin
i<=i+1;
end
else i<=0;
end
reg cond1,cond1_a, cond2, cond3;
always @ (posedge clk) begin
cond1_a<=bunch_counter==no_bunches; // If haven't exceeded number of bunches
cond1<=cond1_a;
cond2<=i==start_bunch_strb; // To send bunch strobe high
cond3<=i==end_bunch_strb; // To send bunch strobe low
if (~store_strb) begin
bunch_counter<=0;
start_bunch_strb<=b1_strobe-1;
end_bunch_strb<=b1_strobe+no_samples-1; // Bunch strobe stays high for no_samples samples
end
else if (cond1) begin
end
else begin
if (cond2) bunch_strb<=1;
else if (cond3) begin
bunch_strb<=0;
bunch_counter<=bunch_counter+1;
start_bunch_strb<=start_bunch_strb+sample_spacing; // Calculate sample numbers for next bunch
end_bunch_strb<=end_bunch_strb+sample_spacing; // Calculate sample numbers for next bunch
end
end
end
endmodule
|
// file: Clock35MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock35MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock35MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:51 09/14/2015
// Design Name: Selector_Casillas
// Module Name: C:/Users/Arturo/Desktop/Proyecto Corto 1 14Set/Gato/Test_selector_casillas.v
// Project Name: Gato
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Selector_Casillas
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_selector_casillas;
// Inputs
reg boton_arriba;
reg boton_abajo;
reg boton_izq;
reg boton_der;
reg boton_elige;
reg turno_p1;
reg turno_p2;
// Outputs
wire [1:0] guarda_c1;
wire [1:0] guarda_c2;
wire [1:0] guarda_c3;
wire [1:0] guarda_c4;
wire [1:0] guarda_c5;
wire [1:0] guarda_c6;
wire [1:0] guarda_c7;
wire [1:0] guarda_c8;
wire [1:0] guarda_c9;
wire p1_mm;
wire p2_mm;
wire [3:0] cuadro;
wire [3:0] circulo;
wire [3:0] equis;
// Instantiate the Unit Under Test (UUT)
Selector_Casillas uut (
.boton_arriba(boton_arriba),
.boton_abajo(boton_abajo),
.boton_izq(boton_izq),
.boton_der(boton_der),
.boton_elige(boton_elige),
.turno_p1(turno_p1),
.turno_p2(turno_p2),
.guarda_c1(guarda_c1),
.guarda_c2(guarda_c2),
.guarda_c3(guarda_c3),
.guarda_c4(guarda_c4),
.guarda_c5(guarda_c5),
.guarda_c6(guarda_c6),
.guarda_c7(guarda_c7),
.guarda_c8(guarda_c8),
.guarda_c9(guarda_c9),
.p1_mm(p1_mm),
.p2_mm(p2_mm),
.cuadro(cuadro),
.circulo(circulo),
.equis(equis)
);
initial begin
// Initialize Inputs
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
turno_p1 = 0;
turno_p2 = 0;
// Wait 100 ns for global reset to finish
#10;
boton_arriba = 1;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 1;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 1;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 1;
turno_p1 = 1;
turno_p2 = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
turno_p1 = 0;
turno_p2 = 0;
#10;
boton_arriba = 1;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
turno_p1 = 0;
turno_p2 = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 1;
turno_p1 = 0;
turno_p2 = 1;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { string s; cin >> s; bool b = true, b1 = false, b2 = true, b3 = false; int sum = 0; for (int i = 0; i < s.size(); i++) { sum += (int)s[i] - 48; int x = (int)s[i] - 48; if (x % 2 == 0) { if (x != 0) b3 = true; if (x == 0 && b2 == false) b3 = true; } if (s[i] == 0 && b2) { b1 = true; b2 = false; } } if (sum % 3 == 0 && b1 && b3) cout << red << endl; else cout << cyan << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (107); const int inf = (int)1e9 + 42; struct aho_corasick { int is_end[MAXN], link[MAXN], psz; map<char, int> to[MAXN]; void clear() { for (int i = 0; i < psz; i++) is_end[i] = 0, link[i] = 0, to[i].clear(); psz = 1; is_end[0] = 1; } aho_corasick() { psz = MAXN - 2; clear(); } void add_word(string s) { int u = 0; for (char c : s) { if (!to[u].count(c)) to[u][c] = psz++; u = to[u][c]; } is_end[u] = 1; } void push_links() { queue<int> Q; int u, v, j; char c; Q.push(0); link[0] = -1; while (!Q.empty()) { u = Q.front(); Q.pop(); for (auto it : to[u]) { v = it.second; c = it.first; j = link[u]; while (j != -1 && !to[j].count(c)) j = link[j]; if (j != -1) link[v] = to[j][c]; else link[v] = 0; Q.push(v); } } } }; int n, m; string s1, s2, virus; void read() { cin >> s1; cin >> s2; cin >> virus; n = s1.size(); m = s2.size(); } aho_corasick aho; bool is_bad[MAXN]; int dp[MAXN][MAXN][MAXN]; int nxt_i[MAXN][MAXN][MAXN]; int nxt_j[MAXN][MAXN][MAXN]; int nxt_state[MAXN][MAXN][MAXN]; int rec(int i, int j, int state) { if (i >= n + 1) return -inf; if (j >= m + 1) return -inf; if (is_bad[state]) return -inf; if (i == n && j == m) return 0; int &memo = dp[i][j][state]; if (memo != -1) return memo; memo = -inf; if (i < n && j < m && s1[i] == s2[j]) { int u = state; while (u != -1 && !aho.to[u].count(s1[i])) u = aho.link[u]; if (u == -1) u = 0; else u = aho.to[u][s1[i]]; memo = max(memo, 1 + rec(i + 1, j + 1, u)); nxt_state[i][j][state] = u; nxt_i[i][j][state] = i + 1; nxt_j[i][j][state] = j + 1; } if (memo < rec(i + 1, j, state)) { memo = max(memo, rec(i + 1, j, state)); nxt_state[i][j][state] = state; nxt_i[i][j][state] = i + 1; nxt_j[i][j][state] = j; } if (memo < rec(i, j + 1, state)) { memo = max(memo, rec(i, j + 1, state)); nxt_state[i][j][state] = state; nxt_i[i][j][state] = i; nxt_j[i][j][state] = j + 1; } return memo; } void solve() { aho.clear(); aho.add_word(virus); aho.push_links(); int u = 0; for (char c : virus) u = aho.to[u][c]; is_bad[u] = true; for (int i = 0; i < aho.psz; i++) { int u = i; while (u != -1) { is_bad[i] |= is_bad[u]; u = aho.link[u]; } } memset(dp, -1, sizeof(dp)); int ret = rec(0, 0, 0); if (!ret) cout << 0 << n ; else { string ans = ; int c_i = 0, c_j = 0, c_state = 0, last_i, last_j, last_state; while (!(c_i == n && c_j == m)) { last_i = c_i; last_j = c_j; last_state = c_state; c_i = nxt_i[last_i][last_j][last_state]; c_j = nxt_j[last_i][last_j][last_state]; c_state = nxt_state[last_i][last_j][last_state]; if (c_i - last_i && c_j - last_j) ans.push_back(s1[last_i]); } cout << ans << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); read(); solve(); return 0; }
|
////////////////////////////////////////////////////////
// RS-232 RX and TX module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 9600;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 9600;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
////////////////////////////////////////////////////////
|
#include <bits/stdc++.h> using namespace std; int main() { long long int w, h; cin >> w >> h; long long int cnt = 0; for (int i = 2; i <= w; i += 2) { for (int j = 2; j <= h; j += 2) { cnt += ((w - i + 1) * (h - j + 1)); } } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[105]; int b[105]; int t, flag, flag1, i, n, c, sum1, sum2; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); b[a[i]] = 1; } int count = 0; int sum = 0; flag = 1; int d = -1; c = 0; for (i = 1; i <= 100; i++) { if (b[i] == 1) { count++; sum += i; if (c == 0) c = i; else { if (d == -1) { d = i - c; c = i; } else { if (d != i - c) { flag = 0; break; } c = i; } } } } if (flag == 0) { printf( -1 n ); } else if (count == 1) { printf( 0 n ); } else if (count == 2) { if (sum % 2 == 0) { sum = sum / 2; printf( %d n , c - sum); } else { sum1 = sum - c; sum1 = c - sum1; sum2 = 2 * c - sum; if (sum1 > sum2) { sum1 = sum2; } printf( %d , sum1); } } else if (count == 3) { sum = sum / count; printf( %d n , c - sum); } else { printf( -1 n ); } return 0; }
|
`include "timescale.v"
module fb_slave_statem (MRxClk, Reset, MRxDV, MRxDEqDataSoC, MRxDEq5, SlaveDataStart
SlaveDataEnd, SlaveCrcEnd, LastSlave, DataFrameEnd, FrmCrcStateEnd,
StateIdle, StatePreamble, StateFFS, StateData, StateSlaveData,
StateSlaveCrc, StateFrmCrc
);
input MRxClk;
input Reset;
input MRxDV;
input MRxDEq5;
input MRxDEqDataSoC;
input SlaveDataStart; //SlaveDataStart = TotalNibCnt == SlaveDataStartCnt;
input SlaveDataEnd; // SlaveDataEnd = TotalNibCnt == SlaveDataEndCnt;
input SlaveCrcEnd;
input LastSlave;
input DataFrameEnd; //DataFrameEnd = (TotalNibCnt ==(TotalNibFrameCnt - 1'b1));
input FrmCrcStateEnd;
output StateIdle;
output StateFFS;
output StatePreamble;
output StateData;
output StateSlaveData;
output StateSlaveCrc;
output StateFrmCrc;
reg StateIdle;
reg StateFFS;
reg StatePreamble;
reg StateData;
reg StateSlaveData;
reg StateSlaveCrc;
reg StateFrmCrc;
wire StartIdle;
wire StartFFS;
wire StartPreamble;
wire StartData;
wire StartSlaveData;
wire StartSlaveCrc;
wire StartFrmCrc;
// Defining the next state
assign StartIdle = ~MRxDV & ( StatePreamble | StateFFS ) | (StateFrmCrc & FrmCrcStateEnd);
assign StartFFS = MRxDV & ~MRxDEq5 & StateIdle;
assign StartPreamble = MRxDV & MRxDEq5 & (StateIdle | StateFFS);
assign StartData = (MRxDV & StatePreamble & MRxDEqDataSoC)|(StateSlaveCrc & SlaveCrcEnd & ~LastSlave);
assign StartSlaveData[0] = StateData & SlaveDataStart | StateSlaveData[1] & ~SlaveDataEnd;;
assign StartSlaveData[1] = StateSlaveData[0];
assign StartSlaveCrc = StateSlaveData[1] & SlaveDataEnd;
assign StartFrmCrc = StateSlaveCrc & SlaveCrcEnd & LastSlave | StateData & DataFrameEnd;
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b1;
StateFFS <= 1'b0;
StatePreamble <= 1'b0;
StateData <= 1'b0;
StateSlave <= 1'b0;
StateSlaveCrc <= 1'b0;
StateFrmCrc <= 1'b0;
end
else
begin
if(StartPreamble | StartFFS)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartPreamble | StartIdle)
StateFFS <= 1'b0;
else
if(StartFFS)
StateFFS <= 1'b1;
if(StartData)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartSlaveData | StartFrmCrc)
StateData <= 1'b0;
else
if(StartData)
StateData <= 1'b1;
if(StartSlaveCrc)
StateSlaveData <= 1'b0;
else
if(StartSlaveData)
StateSlaveData <= 1'b1;
if(StartData | StartFrmCrc)
StateSlaveCrc <= 1'b0;
else
if(StartSlaveCrc)
StateSlaveCrc <= 1'b1;
if(StartIdle)
StateFrmCrc <= 1'b0;
else
if(StartFrmCrc)
StateFrmCrc <= 1'b1;
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module runs through the 16x2 Character LCD initialization *
* commands for the DE2 Board. *
* *
******************************************************************************/
module altera_up_character_lcd_initialization (
// Inputs
clk,
reset,
initialize_LCD_display,
command_was_sent,
// Bidirectionals
// Outputs
done_initialization,
send_command,
the_command
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b1;
// Timing info for waiting for power up
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter W15 = 20; // Counter width required for 15ms
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for waiting between commands
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_5MS = 250000;
parameter W5 = 18; // Counter width required for 5ms
parameter COUNTER_INCREMENT_FOR_5MS = 18'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input initialize_LCD_display;
input command_was_sent;
// Bidirectionals
// Outputs
output done_initialization;
output send_command;
output reg [ 8: 0] the_command;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam LCD_INIT_STATE_0_WAIT_POWER_UP = 2'h0,
LCD_INIT_STATE_1_SEND_COMMAND = 2'h1,
LCD_INIT_STATE_2_CHECK_DONE = 2'h2,
LCD_INIT_STATE_3_DONE = 2'h3;
localparam AUTO_INIT_LENGTH = 4'h8;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [ 8: 0] command_rom;
// Internal Registers
reg [W15: 1] waiting_power_up;
reg [W5: 1] waiting_to_send;
reg [ 3: 0] command_counter;
// State Machine Registers
reg [ 1: 0] ns_lcd_initialize;
reg [ 1: 0] s_lcd_initialize;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_initialize <= LCD_INIT_STATE_0_WAIT_POWER_UP;
else
s_lcd_initialize <= ns_lcd_initialize;
end
always @(*)
begin
// Defaults
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
case (s_lcd_initialize)
LCD_INIT_STATE_0_WAIT_POWER_UP:
begin
if ((waiting_power_up == CLOCK_CYCLES_FOR_15MS) &
(initialize_LCD_display))
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
LCD_INIT_STATE_1_SEND_COMMAND:
begin
if (command_was_sent)
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
end
LCD_INIT_STATE_2_CHECK_DONE:
begin
if (command_counter == AUTO_INIT_LENGTH)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else if (waiting_to_send == CLOCK_CYCLES_FOR_5MS)
ns_lcd_initialize = LCD_INIT_STATE_1_SEND_COMMAND;
else
ns_lcd_initialize = LCD_INIT_STATE_2_CHECK_DONE;
end
LCD_INIT_STATE_3_DONE:
begin
if (initialize_LCD_display)
ns_lcd_initialize = LCD_INIT_STATE_3_DONE;
else
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
default:
begin
ns_lcd_initialize = LCD_INIT_STATE_0_WAIT_POWER_UP;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
the_command <= 9'h000;
else
the_command <= command_rom;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
waiting_power_up <= {W15{1'b0}};
else if ((s_lcd_initialize == LCD_INIT_STATE_0_WAIT_POWER_UP) &&
(waiting_power_up != CLOCK_CYCLES_FOR_15MS))
waiting_power_up <= waiting_power_up + COUNTER_INCREMENT_FOR_15MS;
end
always @(posedge clk)
begin
if (reset)
waiting_to_send <= {W5{1'b0}};
else if (s_lcd_initialize == LCD_INIT_STATE_2_CHECK_DONE)
begin
if (waiting_to_send != CLOCK_CYCLES_FOR_5MS)
waiting_to_send <= waiting_to_send + COUNTER_INCREMENT_FOR_5MS;
end
else
waiting_to_send <= {W5{1'b0}};
end
always @(posedge clk)
begin
if (reset)
command_counter <= 4'h0;
else if (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND)
begin
if (command_was_sent)
command_counter <= command_counter + 4'h1;
end
else if (s_lcd_initialize == LCD_INIT_STATE_3_DONE)
command_counter <= 4'h5;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign send_command = (s_lcd_initialize == LCD_INIT_STATE_1_SEND_COMMAND);
assign done_initialization = (s_lcd_initialize == LCD_INIT_STATE_3_DONE);
// Internal Assignments
always @(*)
begin
case (command_counter)
0 : command_rom <= 9'h030;
1 : command_rom <= 9'h030;
2 : command_rom <= 9'h030;
3 : command_rom <= 9'h03C;
4 : command_rom <= 9'h008;
5 : command_rom <= 9'h001;
6 : command_rom <= 9'h006;
7 : command_rom <= {7'h03, CURSOR_ON, BLINKING_ON};
default : command_rom <= 9'h000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//
//
//
//
// Create Date: 12:12:51 08/04/2014
// Module Name: SpiCtrl
// Project Name: ZedboardOLED
// Target Devices: Zynq
// Tool versions: Vivado 14.2 (64-bits)
// Description: Spi block that sends SPI data formatted SCLK active low with
// SDO changing on the falling edge
//
// Revision: 1.0 - SPI completed
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module SpiCtrl(
CLK,
RST,
SPI_EN,
SPI_DATA,
SDO,
SCLK,
SPI_FIN
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK;
input RST;
input SPI_EN;
input [7:0] SPI_DATA;
output SDO;
output SCLK;
output SPI_FIN;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
wire SDO, SCLK, SPI_FIN;
reg [39:0] current_state = "Idle"; // Signal for state machine
reg [7:0] shift_register = 8'h00; // Shift register to shift out SPI_DATA saved when SPI_EN was set
reg [3:0] shift_counter = 4'h0; // Keeps track how many bits were sent
wire clk_divided; // Used as SCLK
reg [4:0] counter = 5'b00000; // Count clocks to be used to divide CLK
reg temp_sdo = 1'b1; // Tied to SDO
reg falling = 1'b0; // signal indicating that the clk has just fell
// ===========================================================================
// Implementation
// ===========================================================================
assign clk_divided = ~counter[4];
assign SCLK = clk_divided;
assign SDO = temp_sdo;
assign SPI_FIN = (current_state == "Done") ? 1'b1 : 1'b0;
// State Machine
always @(posedge CLK) begin
if(RST == 1'b1) begin // Synchronous RST
current_state <= "Idle";
end
else begin
case(current_state)
// Wait for SPI_EN to go high
"Idle" : begin
if(SPI_EN == 1'b1) begin
current_state <= "Send";
end
end
// Start sending bits, transition out when all bits are sent and SCLK is high
"Send" : begin
if(shift_counter == 4'h8 && falling == 1'b0) begin
current_state <= "Done";
end
end
// Finish SPI transimission wait for SPI_EN to go low
"Done" : begin
if(SPI_EN == 1'b0) begin
current_state <= "Idle";
end
end
default : current_state <= "Idle";
endcase
end
end
// End of State Machine
// Clock Divider
always @(posedge CLK) begin
// start clock counter when in send state
if(current_state == "Send") begin
counter <= counter + 1'b1;
end
// reset clock counter when not in send state
else begin
counter <= 5'b00000;
end
end
// End Clock Divider
// SPI_SEND_BYTE, sends SPI data formatted SCLK active low with SDO changing on the falling edge
always @(posedge CLK) begin
if(current_state == "Idle") begin
shift_counter <= 4'h0;
// keeps placing SPI_DATA into shift_register so that when state goes to send it has the latest SPI_DATA
shift_register <= SPI_DATA;
temp_sdo <= 1'b1;
end
else if(current_state == "Send") begin
// if on the falling edge of Clk_divided
if(clk_divided == 1'b0 && falling == 1'b0) begin
// Indicate that it is passed the falling edge
falling <= 1'b1;
// send out the MSB
temp_sdo <= shift_register[7];
// Shift through SPI_DATA
shift_register <= {shift_register[6:0],1'b0};
// Keep track of what bit it is on
shift_counter <= shift_counter + 1'b1;
end
// on SCLK high reset the falling flag
else if(clk_divided == 1'b1) begin
falling <= 1'b0;
end
end
end
endmodule
|
//`include "uart_tx_buffer.v"
`timescale 1ns/1ns
module uart_tx_buffer_tb();
// Declare inputs as regs and outputs as wires
reg clk, rst;
reg[7:0] data;
reg dataReady;
reg txBusy;
wire txStart;
wire[7:0] txData;
uart_tx_buffer U0(
.clk(clk),
.rst(rst),
.data(data),
.dataReady(dataReady),
.txBusy(txBusy),
.txStart(txStart),
.txData(txData),
.empty(empty),
.full(full)
);
// Initialize all variables
initial begin
$monitor ("clk=%b data=%b dataReady=%b txBusy=%b txStart=%b txData=%b",
clk, data, dataReady, txBusy, txStart, txData);
clk = 1;
rst = 1;
data = 0;
dataReady = 0;
txBusy = 0;
#2
rst = 0;
#2
data = 8'b01000001; // A
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000010; // B
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000011; // C
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000100; // D
dataReady = 1;
txBusy = 1;
#2
dataReady = 0;
#2
data = 8'b01000101; // E
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000110; // F
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000111; // G
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001000; // H
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001001; // I
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001010; // J
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#10
$stop; // Terminate simulation
end
always begin
#1 clk = !clk;
end
endmodule
|
// Check that the >> and >>> operators with unsigned values.
module top;
parameter py = 8'b10101010 >> 3'b101;
parameter pz = 8'b10101010 >>> 3'b101;
reg passed;
reg [7:0] a;
reg [2:0] b;
wire [7:0] wy, wz;
reg [7:0] ry, rz;
// Check CA code.
assign wy = a >> b;
assign wz = a >>> b;
initial begin
passed = 1'b1;
// Example vector
a = 8'b10101010;
b = 3'b101;
#1;
// Check the parameter results.
if (py !== 8'b00000101) begin
$display("Failed param. >>, expected 8'b00000101, got %b", py);
passed = 1'b0;
end
if (pz !== 8'b00000101) begin
$display("Failed param. >>>, expected 8'b00000101, got %b", pz);
passed = 1'b0;
end
// Check the procedural results.
ry = a >> b;
if (ry !== 8'b00000101) begin
$display("Failed procedural >>, expected 8'b00000101, got %b", ry);
passed = 1'b0;
end
rz = a >>> b;
if (rz !== 8'b00000101) begin
$display("Failed procedural >>>, expected 8'b00000101, got %b", rz);
passed = 1'b0;
end
// Check the CA results.
if (wy !== 8'b00000101) begin
$display("Failed CA >>, expected 8'b00000101, got %b", wy);
passed = 1'b0;
end
if (wz !== 8'b00000101) begin
$display("Failed CA >>>, expected 8'b00000101, got %b", wz);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Direction[4][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}}; const int Nmax = 303000; long double n, m; long double ans = 0; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; long double r = n * m; for (int k = 1; k <= min(n, m); k++) { long double add = 1. * k * k / (long double)n; for (double i = n - k + 1; i <= n; i++) add = (add * (long double)(i)) / (long double)(i - n + k); for (double i = r - m - n + k + 1; i <= r - n; i++) add = (add * (long double)(i)) / (long double)(i + n - k); for (double i = 1; i <= k; i++) add = (add) * (m - k + i) / (long double)(r - k + i); ans += add; } cout.precision(16); cout << fixed << ans << endl; return 0; }
|
module KeyboardReader (
input wire rst,
input wire clk,
inout wire ps2CLK,
inout wire ps2DATA,
output reg[8:0] pressedKey,
output reg pressed
);
wire[7:0] readData;
wire update;
reg update_prev;
always @ (posedge clk)
update_prev <= update;
wire update_posedge = !update_prev && update;
PS2_Controller ps2 (
.reset (rst),
.CLOCK_50 (clk),
.PS2_CLK(ps2CLK),
.PS2_DAT(ps2DATA),
.received_data(readData),
.received_data_en(update)
);
reg breakSig = 0;
reg extended = 0;
always @ (posedge clk) begin
if (pressed)
pressed <= 0;
if (rst) begin
breakSig <= 0;
extended <= 0;
pressed <= 0;
pressedKey <= 9'b0;
end else if (update_posedge) begin
if (readData == 8'hF0) breakSig <= 1;
else if (readData == 8'hE0) extended <= 1;
else if (breakSig) begin
breakSig <= 0;
extended <= 0;
end else begin
pressedKey <= {extended, readData};
pressed <= 1;
breakSig <= 0;
extended <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k, h[200010]; int main() { scanf( %d%d%d%d , &n, &a, &b, &k); int ans = 0, x; for (int i = 1; i <= n; i++) { scanf( %d , &x); if (x % (a + b) == 0) x -= (x / (a + b) - 1) * (a + b); else x -= (x / (a + b)) * (a + b); if (x <= a) ans++; else { if (x % a == 0) x = x / a - 1; else x = x / a; h[i] = x; } } sort(h + 1, h + 1 + n); for (int i = 1; i <= n; i++) if (h[i] > 0 && k >= h[i]) k -= h[i], ans++; printf( %d n , ans); return 0; }
|
//-----------------------------------------------------------------------------
//-- Divisor de reloj
//-- Señal de periodo igual al indicado
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module dividerp1(input wire clk,
input wire timer_ena,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador modulo M
always @(posedge clk)
if (timer_ena)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
else
divcounter <= 0;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == M - 1) ? 1 : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, x, r, z, sol; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x; if (r > 0) { x = x - k + r; sol++; } z = x / k; sol += z; r = x % k; } if (r > 0) { sol++; } cout << sol; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const int MAXN = 600; int n, m; int x, y, cnt; bool us[MAXN][MAXN]; string s; int main() { ios_base ::sync_with_stdio(false); cin >> n >> m >> x >> y; cin >> s; for (int i = 0; i < s.size(); i++) { if (us[x][y]) cout << 0 ; else cout << 1 ; us[x][y] = true; if (s[i] == U ) x--; if (s[i] == D ) x++; if (s[i] == L ) y--; if (s[i] == R ) y++; if (x > n) x = n; if (x == 0) x = 1; if (y > m) y = m; if (y == 0) y = 1; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (!us[i][j]) cnt++; cout << cnt; }
|
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