text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 5; const int M = 1e6; const long long INF = (long long)(1e18); const int inf = 1e9; const long long MOD = 1000000007LL; long long n, m; long long a[MAX_N]; long long ans[MAX_N]; long long suff[MAX_N]; void solve() {} int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; long long s = 0LL; for (long long i = 1; i <= m; i++) { cin >> a[i]; s += a[i]; } bool ok = true; for (long long i = 1; i <= m; i++) { if (i - 1 + a[i] > n) { ok = false; break; } } if (s < n || !ok) { cout << -1; return 0; } for (long long i = m; i >= 1; i--) { suff[i] = suff[i + 1] + a[i]; ans[i] = max(i, n - suff[i] + 1); } for (long long i = 1; i <= m; i++) { cout << ans[i] << ; } return 0; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 10:22:00 11/21/2016
// Module Name: FORWARDING_UNIT
// Project Name: MIPS
// Description: Forwarding Unit implementation in the MIPS pipeline.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module FORWARDING_UNIT(
// Inputs from the ID/EX latch.
input [4:0] rs,
input [4:0] rt,
// Inputs from the EX/MEM latch.
input [4:0] five_bit_mux_out,
input [1:0] ex_mem_wb,
input [4:0] mem_Write_reg,
// Input form the MEM/WB latch.
input [1:0] mem_wb_wb,
// Outputs to the EX stage.
output reg [1:0] forward_a_sel,
output reg [1:0] forward_b_sel);
always @ * begin
forward_a_sel <= 2'b00;
forward_b_sel <= 2'b00;
// EX Hazard
if (ex_mem_wb[1] &&
(five_bit_mux_out != 0) && (five_bit_mux_out == rs))
begin
forward_a_sel <= 2'b10;
end
if (ex_mem_wb[1] &&
(five_bit_mux_out != 0) && (five_bit_mux_out == rt))
begin
forward_b_sel <= 2'b10;
end
// MEM Hazard
if (mem_wb_wb[1] && (mem_Write_reg != 0) &&
!(ex_mem_wb[1] && (five_bit_mux_out != 0) && (five_bit_mux_out != rs)) &&
(mem_Write_reg == rs))
begin
forward_a_sel <= 2'b01;
end
if (mem_wb_wb[1] && (mem_Write_reg != 0) &&
!(ex_mem_wb[1] && (five_bit_mux_out != 0) && (five_bit_mux_out != rt)) &&
(mem_Write_reg == rt))
begin
forward_b_sel <= 2'b01;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; const long long MOD = 100030001, H = 47; map<int, long long> d[N]; vector<int> adj[N]; set<pair<long long, int> > s; vector<pair<int, pair<long long, int> > > nei[N]; long long r[N], l[N], num[N], ch[N], h[3 * N], n, sz, ans, o = 10, c = 11; void add(int ind, int val) { auto it = s.lower_bound({ind, val}); if (it == s.end() || it->first != ind) s.insert({ind, val}); else { if (it->second + val != 0) s.insert({ind, it->second + val}); s.erase(it); } return; } void f(int v, int u) { add(d[v][v], -1); add(d[u][u], 1); add(d[v][u], 1); add(d[u][v], -1); return; } void DFS1(int v, int par = 0) { for (int u : adj[v]) { if (u != par) { DFS1(u, v); ch[v] += ch[u]; nei[v].push_back({d[u][v], {ch[u], u}}); } } ch[v]++; long long ans = o; sort(nei[v].begin(), nei[v].end()); for (auto u : nei[v]) { ans = ans * h[2 * u.second.first] % MOD; ans = (ans + u.first) % MOD; } d[v][par] = (ans * H + c) % MOD; return; } void DFS2(int v, int par = 0) { nei[v].clear(); for (int u : adj[v]) { nei[v].push_back({d[u][v], {ch[u], u}}); if (u == par) nei[v].back().second.first = n - ch[v]; } sort(nei[v].begin(), nei[v].end()); l[0] = o, r[nei[v].size() + 1] = c, num[nei[v].size() + 1] = 1; for (int i = 1; i <= nei[v].size(); i++) { auto u = nei[v][i - 1]; l[i] = (l[i - 1] * h[u.second.first * 2] + d[u.second.second][v]) % MOD; } for (int i = nei[v].size(); i > 0; i--) { auto u = nei[v][i - 1]; num[i] = num[i + 1] + u.second.first * 2; r[i] = (r[i + 1] + d[u.second.second][v] * h[num[i + 1]]) % MOD; } for (int i = 0; i < nei[v].size(); i++) { d[v][nei[v][i].second.second] = (l[i] * h[num[i + 2]] + r[i + 2]) % MOD; } for (int u : adj[v]) if (u != par) DFS2(u, v); add(d[v][par], 1); return; } void DFS3(int v, int par = 0) { if (s.size() > sz) { ans = v; sz = s.size(); } for (int u : adj[v]) { if (u != par) { f(v, u); DFS3(u, v); } } f(v, par); return; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int u, v; cin >> n; h[0] = 1; for (int i = 0; i <= n * 2 + 10; i++) h[i + 1] = h[i] * H % MOD; for (int i = 1; i < n; i++) { cin >> u >> v; adj[--u].push_back(--v); adj[v].push_back(u); } if (n == 1) { cout << 1 << endl; return 0; } DFS1(0); DFS2(0); DFS3(0); cout << ans + 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int INF = 2e18; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) { if (n % i == 0 || n % (i + 2) == 0) return false; } return true; } long long int exp(long long int x, long long int n) { long long int res = 1; while (n > 0) { if (n % 2 == 1) res = (res * x) % 1000000007; x = (x * x) % 1000000007; n = n / 2; } return res; } void null() { long long int n, l, r; cin >> n >> l >> r; vector<long long int> a, b; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; a.push_back(x); } for (long long int i = 0; i < n; i++) { long long int x; cin >> x; b.push_back(x); } for (long long int i = 0; i < l - 1; i++) { if (a[i] != b[i]) { cout << LIE ; return; } } for (long long int i = r; i < n; i++) { if (a[i] != b[i]) { cout << LIE ; return; } } cout << TRUTH ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t = 1; clock_t start, end; start = clock(); cout << fixed << setprecision(20); while (t--) { null(); } end = clock(); double time_taken = double(end - start) / double(CLOCKS_PER_SEC); }
|
#include <bits/stdc++.h> using namespace std; struct fast_ios { fast_ios() { cin.tie(nullptr), ios::sync_with_stdio(false), cout << fixed << setprecision(20); }; } fast_ios_; string solve(string S) { const int N = S.length(); int L = N; while (L % 2 == 0) L /= 2; while (L < N) { for (int i = 0; i < N; i += L * 2) { if (S.substr(i, L) > S.substr(i + L, L)) { for (int j = (0), j_end_ = (L); j < j_end_; j++) swap(S[i + j], S[i + j + L]); } } L *= 2; } return S; } int main() { string A, B; cin >> A >> B; cout << (solve(A) == solve(B) ? YES : NO ) << n ; }
|
module S3A3(C50, C1, Anodo1, D1);
input C50;
output reg C1=0;
output Anodo1=1;
output reg [6:0] D1=0;
reg [24:0] Ct1 = 0;
reg [3:0] unidades=0;
parameter [6:0] cero = 7'b0000001;
parameter [6:0] uno = 7'b0000001;
parameter [6:0] dos = 7'b0000001;
parameter [6:0] tres = 7'b0000001;
parameter [6:0] cuatro = 7'b0000001;
parameter [6:0] cinco = 7'b0000001;
parameter [6:0] seis = 7'b0000001;
parameter [6:0] siete = 7'b0000001;
parameter [6:0] ocho = 7'b0000001;
parameter [6:0] nueve = 7'b0000001;
parameter [6:0] guion = 7'b0000001;
assign Anodo = 1;
always @(posedge C50)
begin
Ct1 = Ct1+1;
if(Ct1==25_000_000)
begin
Ct1=0;
C1 = ~C1;
end
end
always @(posedge C1)
begin
unidades = unidades+1;
if(unidades==10)
unidades=0;
end
always @(unidades)
begin
case(unidades)
0: D1 = cero;
1: D1 = uno;
2: D1 = dos;
3: D1 = tres;
4: D1 = cuatro;
5: D1 = cinco;
6: D1 = seis;
7: D1 = siete;
8: D1 = ocho;
9: D1 = nueve;
default: D1 = guion;
endcase
end
endmodule
|
// file: Master_Clock_Divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____50.000______0.000______50.0______129.198_____89.971
// clk_out2___100.000______0.000______50.0______112.316_____89.971
// clk_out3___200.000______0.000______50.0_______98.146_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Master_Clock_Divider,clk_wiz_v5_3_2_0,{component_name=Master_Clock_Divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module Master_Clock_Divider
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
Master_Clock_Divider_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
// Status and control signals
.reset(reset),
.locked(locked),
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char symmetric[11] = { A , H , I , M , O , T , U , V , W , X , Y }; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool IsPalindrome(string str) { if (str.empty()) return false; long long int i = 0; long long int j = str.length() - 1; while (i < j) { if (str[i] != str[j]) { return false; } i++; j--; } return true; } long long int binpow(long long int a, long long int b) { if (b == 0) return 1; long long int res = binpow(a, b / 2); if (b % 2) return (res * res * a); return (res * res); } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int a, b; cin >> a >> b; long long int x = max(a, b); long long int y = a + b - x; if (a < 2 * b && b < 2 * a) cout << a << << b; else if (x % y == 0) { if ((x / y) % 2 == 0) { if (y == a) { cout << y << 0 ; } else { cout << 0 << y; } } else { cout << y << << y; } } else { while (a && b) { if (a >= 2 * b) a %= 2 * b; else if (b >= 2 * a) b %= 2 * a; else break; } cout << a << << b; } return 0; }
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [23:0] SNES_ADDR, // requested address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK
);
wire [23:0] SRAM_SNES_ADDR;
/* static mapper:
menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
);
assign SRAM_SNES_ADDR = (IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_SAVERAM;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } vector<int> v; signed main() { int n = read(), k = read() % 64, x = read(); for (int i = 1, x; i <= n; i++) x = read(), v.push_back(x); while (k--) { sort(v.begin(), v.end()); for (int i = 0; i < n; i += 2) v[i] ^= x; } sort(v.begin(), v.end()); printf( %d %d n , v[n - 1], v[0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 3e5 + 5; long long n, q, a[maxn], c[maxn]; long long read() { long long res = 0, f = 1; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (!isdigit(ch)); do { res = res * 10 + ch - 0 ; ch = getchar(); } while (isdigit(ch)); return res * f; } long long check(long long x) { if (!x) return 0; return x > 0 ? 1 : -1; } struct SegmentTree { long long mxlen[maxn << 2], lmost[maxn << 2], ltype[maxn << 2], rmost[maxn << 2], rtype[maxn << 2], len[maxn << 2]; void pushup(long long rt, long long l, long long r) { long long ls = rt << 1, rs = rt << 1 | 1, mx = max(mxlen[ls], mxlen[rs]), mid = (l + r) >> 1; ltype[rt] = ltype[ls]; rtype[rt] = rtype[rs]; mx = max(mx, lmost[ls]); mx = max(mx, rmost[rs]); if (rtype[ls] && ltype[rs] && rtype[ls] >= ltype[rs]) { mx = max(mx, rmost[ls] + lmost[rs]); if (lmost[ls] == len[ls]) lmost[rt] = lmost[ls] + lmost[rs]; else lmost[rt] = lmost[ls]; if (rmost[rs] == len[rs]) rmost[rt] = rmost[ls] + rmost[rs]; else rmost[rt] = rmost[rs]; } else lmost[rt] = lmost[ls], rmost[rt] = rmost[rs]; mxlen[rt] = mx; } void build(long long rt, long long l, long long r) { len[rt] = r - l + 1; if (l == r) { ltype[rt] = rtype[rt] = lmost[rt] = rmost[rt] = 0; if (a[l]) mxlen[rt] = 1; if (a[l] > 0) { ltype[rt] = 1; lmost[rt] = 1; rtype[rt] = 1; rmost[rt] = 1; } else if (a[l] < 0) { ltype[rt] = -1; lmost[rt] = 1; rtype[rt] = -1; rmost[rt] = 1; } return; } long long mid = (l + r) >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); pushup(rt, l, r); } void update(long long rt, long long l, long long r, long long x, long long val) { if (l == r) { a[l] += val; ltype[rt] = rtype[rt] = lmost[rt] = rmost[rt] = 0; if (a[l]) mxlen[rt] = 1; if (a[l] > 0) { ltype[rt] = 1; lmost[rt] = 1; rtype[rt] = 1; rmost[rt] = 1; } else if (a[l] < 0) { ltype[rt] = -1; lmost[rt] = 1; rtype[rt] = -1; rmost[rt] = 1; } return; } long long mid = (l + r) >> 1; if (x <= mid) update(rt << 1, l, mid, x, val); else update(rt << 1 | 1, mid + 1, r, x, val); pushup(rt, l, r); } } T; signed main() { n = read(); for (long long i = (1); i <= (n); ++i) c[i] = read(); if (n == 1) { q = read(); while (q--) { long long l = read(), r = read(), x = read(); puts( 1 ); } return 0; } for (long long i = (1); i <= (n - 1); ++i) a[i] = c[i + 1] - c[i]; T.build(1, 1, n - 1); q = read(); while (q--) { long long l = read(), r = read(), x = read(); if (l - 1 >= 1) T.update(1, 1, n - 1, l - 1, x); if (r + 1 <= n) T.update(1, 1, n - 1, r, -x); printf( %d n , T.mxlen[1] + 1); } }
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../framework_defines.vh"
`include "../afu_defines.vh"
module fpga_setup (
input wire clk,
input wire rst_n,
output reg ctx_status_valid,
// server_io <--> cmd server: RX_RD
input wire io_rx_csr_valid,
input wire [13:0] io_rx_csr_addr,
input wire [31:0] io_rx_csr_data,
// TX WR
input wire setup_tx_wr_ready,
output reg setup_tx_wr_valid,
output reg [`FPGA_SETUP_TAG-1:0] setup_tx_wr_tag,
output reg [31:0] setup_tx_wr_addr,
output reg [511:0] setup_tx_data,
// setup pagetable
input wire [1:0] pt_status,
output wire pt_update,
output wire [31:0] pt_base_addr,
output wire spl_reset_t
);
reg [31:0] pt_update_cycles = 0;
reg afu_dsm_updated = 0;
wire csr_afu_dsm_base_valid;
wire [31:0] csr_afu_dsm_base;
reg spl_dsm_updated = 0;
wire csr_spl_dsm_base_valid;
wire [31:0] csr_spl_dsm_base;
reg vir_ctx_updated = 0;
wire [31:0] csr_vir_ctx_base;
wire csr_vir_ctx_valid;
reg pt_status_updated = 0;
reg afu_config_updated = 0;
wire spl_dsm_update;
wire afu_dsm_update;
wire vir_ctx_update;
wire pt_status_update;
wire afu_config_update;
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ///////////////////////////
////////////////////////////////////////// CSR File ////////////////////////
///////////////////////////////////////////// ///////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
csr_file csr_file(
.clk (clk),
.reset_n (rst_n),
.spl_reset (spl_reset_t),
// server_io --> csr_file
.io_rx_csr_valid (io_rx_csr_valid),
.io_rx_csr_addr (io_rx_csr_addr),
.io_rx_csr_data (io_rx_csr_data),
// csr_file --> dsm_module, spl_id, afu_id
.csr_spl_dsm_base (csr_spl_dsm_base),
.csr_spl_dsm_base_valid (csr_spl_dsm_base_valid),
.csr_spl_dsm_base_done (spl_dsm_updated),
.csr_afu_dsm_base (csr_afu_dsm_base),
.csr_afu_dsm_base_valid (csr_afu_dsm_base_valid),
.csr_afu_dsm_base_done (afu_dsm_updated),
// csr_file --> ctx_tracker, FPGA virtual memory space
.csr_ctx_base_valid (csr_vir_ctx_valid),
.csr_ctx_base (csr_vir_ctx_base),
.csr_ctx_base_done (vir_ctx_updated)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ///////////////////////////
////////////////////////////////////////// Setup FSM ////////////////////////
///////////////////////////////////////////// ///////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
assign spl_dsm_update = csr_spl_dsm_base_valid & ~spl_dsm_updated;
assign afu_dsm_update = csr_afu_dsm_base_valid & ~afu_dsm_updated;
assign vir_ctx_update = csr_vir_ctx_valid & (|pt_status) & ~vir_ctx_updated;
assign pt_status_update = csr_vir_ctx_valid & pt_status[0] & ~pt_status_updated;
assign afu_config_update = afu_dsm_updated & ~afu_config_updated;
always @(posedge clk) begin
if (~rst_n | spl_reset_t) begin
setup_tx_wr_addr <= 0;
setup_tx_wr_valid <= 1'b0;
setup_tx_wr_tag <= 'h0;
setup_tx_data <= 0;
spl_dsm_updated <= 1'b0;
afu_dsm_updated <= 1'b0;
vir_ctx_updated <= 1'b0;
pt_status_updated <= 1'b0;
afu_config_updated <= 1'b0;
ctx_status_valid <= 0;
end
else if( setup_tx_wr_ready ) begin
casex ({spl_dsm_update, afu_dsm_update, afu_config_update, vir_ctx_update, pt_status_update})
5'b1????: begin //
setup_tx_wr_addr <= csr_spl_dsm_base;
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h1;
setup_tx_data <= {480'b0, `SPL_ID};
spl_dsm_updated <= 1'b1;
end
5'b01???: begin //
setup_tx_wr_addr <= csr_afu_dsm_base;
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h2;
setup_tx_data <= {448'b0, `AFU_ID};
afu_dsm_updated <= 1'b1;
end
5'b001??: begin
setup_tx_wr_addr <= (csr_afu_dsm_base + `ALLOC_OPERATORS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h3;
setup_tx_data <= {256'b0,
{16'b0,`FTHREAD_8_PLACED_AFU},
{16'b0,`FTHREAD_7_PLACED_AFU},
{16'b0,`FTHREAD_6_PLACED_AFU},
{16'b0,`FTHREAD_5_PLACED_AFU},
{16'b0,`FTHREAD_4_PLACED_AFU},
{16'b0,`FTHREAD_3_PLACED_AFU},
{16'b0,`FTHREAD_2_PLACED_AFU},
{16'b0,`FTHREAD_1_PLACED_AFU} };
afu_config_updated <= 1'b1;
end
5'b0001?: begin
setup_tx_wr_addr <= (csr_spl_dsm_base + `CTX_STATUS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h4;
setup_tx_data <= {384'b0, 127'b0, pt_status[1]};
vir_ctx_updated <= 1'b1;
end
5'b00001: begin
setup_tx_wr_addr <= (csr_afu_dsm_base + `PT_STATUS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h5;
setup_tx_data <= {480'b0, pt_update_cycles};
pt_status_updated <= 1'b1;
ctx_status_valid <= pt_status[0];
end
5'b00000: begin
setup_tx_wr_addr <= 0;
setup_tx_wr_valid <= 1'b0;
setup_tx_wr_tag <= 'h0;
setup_tx_data <= 0;
end
endcase
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
assign pt_update = csr_vir_ctx_valid;
assign pt_base_addr = csr_vir_ctx_base;
//
always @(posedge clk) begin
if (~rst_n | spl_reset_t) begin
pt_update_cycles <= 0;
end
else begin
if(pt_update & ~(|pt_status) ) begin
pt_update_cycles <= pt_update_cycles + 1'b1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: seven_seg_decoder
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Produces cathode signals for displaying digits on the SSD.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module seven_seg_decoder(
num_in,
control,
seg_out,
display_sel
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] num_in;
input [1:0] control;
output [6:0] seg_out;
input display_sel;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
wire [6:0] seg_out_bcd;
wire [6:0] seg_out_hex;
wire [6:0] seg_out_buf;
// ==============================================================================
// Implementation
// ==============================================================================
// If displaying hex, then make digit 4 on the SSD be an "H"
assign seg_out = (control == 2'b11 & display_sel == 1'b0) ? 7'b0001001 : seg_out_buf;
// Select either the HEX data or Dec. data to display on the SSD.
assign seg_out_buf = (display_sel == 1'b1) ? seg_out_bcd : seg_out_hex;
// Decimal decoder
assign seg_out_bcd = (num_in == 4'b0000) ? 7'b1000000 : //0
(num_in == 4'b0001) ? 7'b1111001 : //1
(num_in == 4'b0010) ? 7'b0100100 : //2
(num_in == 4'b0011) ? 7'b0110000 : //3
(num_in == 4'b0100) ? 7'b0011001 : //4
(num_in == 4'b0101) ? 7'b0010010 : //5
(num_in == 4'b0110) ? 7'b0000010 : //6
(num_in == 4'b0111) ? 7'b1111000 : //7
(num_in == 4'b1000) ? 7'b0000000 : //8
(num_in == 4'b1001) ? 7'b0010000 : //9
(num_in == 4'b1010) ? 7'b1111111 : //nothing when positive
(num_in == 4'b1011) ? 7'b1000110 : //C for temperature reading
7'b0111111; //minus sign
// Hex decoder
assign seg_out_hex = (num_in == 4'b0000) ? 7'b1000000 : //0
(num_in == 4'b0001) ? 7'b1111001 : //1
(num_in == 4'b0010) ? 7'b0100100 : //2
(num_in == 4'b0011) ? 7'b0110000 : //3
(num_in == 4'b0100) ? 7'b0011001 : //4
(num_in == 4'b0101) ? 7'b0010010 : //5
(num_in == 4'b0110) ? 7'b0000010 : //6
(num_in == 4'b0111) ? 7'b1111000 : //7
(num_in == 4'b1000) ? 7'b0000000 : //8
(num_in == 4'b1001) ? 7'b0010000 : //9
(num_in == 4'b1010) ? 7'b0001000 : //A
(num_in == 4'b1011) ? 7'b0000011 : //B
(num_in == 4'b1100) ? 7'b1000110 : //C
(num_in == 4'b1101) ? 7'b0100001 : //D
(num_in == 4'b1110) ? 7'b0000110 : //E
7'b0001110; //F
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int n, m; int clauses[123123][2]; vector<int> uses[123123]; bool vis[123123]; vector<int> chain[123123]; int counter; vector<pair<long long, long long>> dips; long long ans; int rightc(int cnr) { int xnr = abs(clauses[cnr][1]); if (uses[xnr].size() == 2) { return uses[xnr][0] == cnr ? uses[xnr][1] : uses[xnr][0]; } else { return 0; } } void load() { cin >> n >> m; int k; for (int i = 1; i <= n; ++i) { cin >> k; for (int j = 0; j < k; ++j) { cin >> clauses[i][j]; uses[abs(clauses[i][j])].push_back(i); } } } void dfs(int cnr, int from) { if (vis[cnr]) { return; } vis[cnr] = 1; if (abs(clauses[cnr][1]) == from) { swap(clauses[cnr][0], clauses[cnr][1]); } chain[counter].push_back(cnr); dfs(rightc(cnr), abs(clauses[cnr][1])); } void dfs2(int cnr, int from, int f) { if (vis[cnr]) { return; } vis[cnr] = 1; if (!clauses[cnr][1]) { if (!f) { swap(clauses[cnr][0], clauses[cnr][1]); } } else { if (abs(clauses[cnr][1]) == from) { swap(clauses[cnr][0], clauses[cnr][1]); } } chain[counter].push_back(cnr); dfs2(rightc(cnr), abs(clauses[cnr][1]), 1); } void buildChains() { vis[0] = 1; for (int i = 1; i <= m; ++i) if (uses[i].size() == 1 && !vis[uses[i][0]]) { dfs(uses[i][0], i); ++counter; } for (int i = 1; i <= m; ++i) if (uses[i].size() == 2) { if (!vis[uses[i][0]] && !clauses[uses[i][0]][1]) { dfs2(uses[i][0], i, 0); ++counter; } if (!vis[uses[i][1]] && !clauses[uses[i][1]][1]) { dfs2(uses[i][1], i, 0); ++counter; } } for (int i = 1; i <= n; ++i) if (!vis[i]) { dfs(i, abs(clauses[i][0])); ++counter; } } long long dp[123123][2][2][2]; int val(int i, int j, int nr) { int v1 = i; if (clauses[nr][0] < 0) { v1 = 1 - v1; } if (clauses[nr][0] == 0) { v1 = 0; } int v2 = j; if (clauses[nr][1] < 0) { v2 = 1 - v2; } if (clauses[nr][1] == 0) { v2 = 0; } return (v1 | v2); } void cleaar(int si) { for (int i = 0; i < si; ++i) for (int j = 0; j < 2; ++j) for (int l = 0; l < 2; ++l) for (int k = 0; k < 2; ++k) dp[i][j][l][k] = 0; } void consider(int nr) { if (chain[nr].size() == 1 && abs(clauses[chain[nr][0]][0]) == abs(clauses[chain[nr][0]][1])) { if (clauses[chain[nr][0]][0] == clauses[chain[nr][0]][1]) { dips.push_back(make_pair(1, 1)); } else { dips.push_back(make_pair(0, 2)); } return; } cleaar(chain[nr].size()); int fi = chain[nr][0]; for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) dp[0][i][j][val(i, j, fi)] = 1; for (int i = 0; i < chain[nr].size() - 1; ++i) for (int j = 0; j < 2; ++j) for (int l = 0; l < 2; ++l) for (int k = 0; k < 2; ++k) { dp[i + 1][j][0][val(l, 0, chain[nr][i + 1]) ^ k] += dp[i][j][l][k]; dp[i + 1][j][0][val(l, 0, chain[nr][i + 1]) ^ k] %= mod; dp[i + 1][j][1][val(l, 1, chain[nr][i + 1]) ^ k] += dp[i][j][l][k]; dp[i + 1][j][1][val(l, 1, chain[nr][i + 1]) ^ k] %= mod; } int si = chain[nr].size(); if (!clauses[chain[nr][0]][0] && !clauses[chain[nr][si - 1]][1]) { dips.push_back(make_pair(dp[si - 1][0][0][0], dp[si - 1][0][0][1])); return; } if (!clauses[chain[nr][si - 1]][1]) { long long r0 = (dp[si - 1][0][0][0] + dp[si - 1][1][0][0]) % mod; long long r1 = (dp[si - 1][0][0][1] + dp[si - 1][1][0][1]) % mod; dips.push_back(make_pair(r0, r1)); return; } if (abs(clauses[chain[nr][0]][0]) != abs(clauses[chain[nr][si - 1]][1])) { long long r0 = (dp[si - 1][0][0][0] + dp[si - 1][1][1][0] + dp[si - 1][0][1][0] + dp[si - 1][1][0][0]) % mod; long long r1 = (dp[si - 1][0][0][1] + dp[si - 1][1][1][1] + dp[si - 1][0][1][1] + dp[si - 1][1][0][1]) % mod; dips.push_back(make_pair(r0, r1)); return; } long long r0 = (dp[si - 1][0][0][0] + dp[si - 1][1][1][0]) % mod; long long r1 = (dp[si - 1][0][0][1] + dp[si - 1][1][1][1]) % mod; dips.push_back(make_pair(r0, r1)); } void makeAns() { long long a = dips[0].first; long long b = dips[0].second; for (int i = 1; i < counter; ++i) { long long c = (a * dips[i].first + b * dips[i].second) % mod; long long d = (a * dips[i].second + b * dips[i].first) % mod; a = c; b = d; } ans = b; for (int i = 1; i <= m; ++i) if (uses[i].empty()) { ans *= 2; ans %= mod; } } void debug() { return; for (int i = 0; i < counter; ++i) { cerr << i << : ; for (int ind : chain[i]) { cerr << ( << clauses[ind][0] << , << clauses[ind][1] << ) ; } cerr << endl; } for (auto tmp : dips) { cerr << tmp.first << << tmp.second << endl; } } int main() { ios_base::sync_with_stdio(0); load(); buildChains(); for (int i = 0; i < counter; ++i) { consider(i); } debug(); makeAns(); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k, lst, a[22], b[1 << 18], o[1 << 18]; long long f[1 << 18][18], g[1 << 18]; char s[22][22]; void rec(int sum, int x, int mask) { if (sum == 0) { for (i = 0; i < (1 << n); i++) if (b[i] > lst) for (j = 0; j < n; j++) f[i][j] = 0; for (i = 0; i < (1 << n) - 1; i++) if (b[i] >= lst) for (j = 0; j < n; j++) if (f[i][j]) { int prv = (1 << n) - 1 - i; if ((mask >> (n - b[i] - 1)) & 1) { for (int x = (prv & (prv - 1)); prv > 0; x &= (x - 1)) { k = o[prv ^ x]; if (s[j][k] == 1 ) f[i ^ (1 << k)][k] += f[i][j]; prv = x; } } else for (int x = (prv & (prv - 1)); prv > 0; x &= (x - 1)) { k = o[prv ^ x]; f[i ^ (1 << k)][k] += f[i][j]; prv = x; } } for (j = 0; j < n; j++) g[mask] += f[i][j]; return; } for (; x > 0; x--) { rec(sum - x, min(sum - x, x), (mask << x) + (1 << (x - 1)) - 1); lst = n - (sum - x + 1); } } int main() { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , s[i]); f[1 << i][i] = 1; o[1 << i] = i; } lst = 1; for (i = 0; i < (1 << n); i++) b[i] = b[i / 2] + (i & 1); rec(n, n, 0); for (i = 0; i < (1 << (n - 1)); i++) { for (m = 0, j = -1; j < n - 1; j = k) { for (k = j + 1; k < n - 1 && ((i >> k) & 1); k++) ; a[m++] = k - j; } sort(a, a + m); reverse(a, a + m); for (k = j = 0; j < m; j++) k = (k << a[j]) + (1 << (a[j] - 1)) - 1; g[i] = g[k]; } for (j = n - 1; j >= 0; j--) for (i = (1 << (n - 1)) - 1; i > 0; i--) if ((i >> j) & 1) g[i ^ (1 << j)] -= g[i]; for (i = 0; i < (1 << (n - 1)); i++) printf( %I64d , g[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100; int cost[N][2], timee, tmm, num, clr, n; char ha, arr[25]; string tm1, tm2; int main() { scanf( %s , &arr); tm1 = arr; scanf( %s%d , &arr, &n); tm2 = arr; while (n--) { scanf( %d %c%d %c , &timee, &tmm, &num, &clr); if (clr == y ) { if (tmm == h ) { cost[num][0]++; } else { cost[num][1]++; } } else { if (tmm == h ) { cost[num][0] += 2; } else { cost[num][1] += 2; } } if (cost[num][0] > 1) { cout << tm1 << << num << << timee << n ; cost[num][0] = -1e9; } if (cost[num][1] > 1) { cout << tm2 << << num << << timee << n ; cost[num][1] = -1e9; } } return 0; }
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Interface ////
//// This is the external bus interface, that is WISHBONE ////
//// SoC compliant. ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_wb.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_wb.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.4 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.2 2001/08/10 08:48:33 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:52 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:11:47 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_wb( // WISHBONE Interface
wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o,
wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i,
// Memory Arbiter Interface
ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack,
// Register File interface
rf_re, rf_we, rf_din, rf_dout);
input wb_clk, phy_clk;
input rst;
input [`USBF_UFC_HADR:0] wb_addr_i;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output wb_ack_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
// Memory Arbiter Interface
output [`USBF_UFC_HADR:0] ma_adr;
output [31:0] ma_dout;
input [31:0] ma_din;
output ma_we;
output ma_req;
input ma_ack;
// Register File interface
output rf_re;
output rf_we;
input [31:0] rf_din;
output [31:0] rf_dout;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [5:0] // synopsys enum state
IDLE = 6'b00_0001,
MA_WR = 6'b00_0010,
MA_RD = 6'b00_0100,
W0 = 6'b00_1000,
W1 = 6'b01_0000,
W2 = 6'b10_0000;
reg [5:0] state, next_state;
reg wb_req_s1;
reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2;
reg ma_we;
reg rf_re, rf_we_d;
reg ma_req;
reg wb_ack_o;
reg [31:0] wb_data_o;
///////////////////////////////////////////////////////////////////
//
// Interface Logic
//
assign ma_adr = wb_addr_i;
assign ma_dout = wb_data_i;
assign rf_dout = wb_data_i;
always @(posedge wb_clk)
if( `USBF_RF_SEL ) wb_data_o <= rf_din;
else wb_data_o <= ma_din;
// Sync WISHBONE Request
always @(posedge phy_clk)
wb_req_s1 <= wb_stb_i & wb_cyc_i;
// Sync WISHBONE Ack
always @(posedge wb_clk)
wb_ack_s1 <= wb_ack_d;
always @(posedge wb_clk)
wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
always @(posedge wb_clk)
wb_ack_s1a <= wb_ack_s1;
always @(posedge wb_clk)
wb_ack_s2 <= wb_ack_s1a;
assign rf_we = rf_we_d;
///////////////////////////////////////////////////////////////////
//
// Interface State Machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) state <= IDLE;
//to the prefered high reset
if(rst) state <= IDLE;
else state <= next_state;
always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i)
begin
next_state = state;
ma_req = 1'b0;
ma_we = 1'b0;
wb_ack_d = 1'b0;
rf_re = 1'b0;
rf_we_d = 1'b0;
case(state) // synopsys parallel_case
IDLE:
begin
if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i)
begin
ma_req = 1'b1;
ma_we = 1'b1;
next_state = MA_WR;
end
if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i)
begin
ma_req = 1'b1;
next_state = MA_RD;
end
if(wb_req_s1 && `USBF_RF_SEL && wb_we_i)
begin
rf_we_d = 1'b1;
next_state = W0;
end
if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i)
begin
rf_re = 1'b1;
next_state = W0;
end
end
MA_WR:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
ma_we = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
MA_RD:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
W0:
begin
wb_ack_d = 1'b1;
next_state = W1;
end
W1:
begin
next_state = W2;
end
W2:
begin
next_state = IDLE;
end
endcase
end
endmodule
|
module pulses(
/* This module sets up the output logic, including the pulse and block switches, the attenuator(s),
and the scope trigger. It needs to have two modes:
A CW mode, which holds both switches open, and outputs a trigger for the scope and the SynthHD.
This mode is chosen by setting the 'mode' input to 0.
Inputs are 'period', 'pre_att', and 'post_att'.
A pulsed mode, which opens the pulse switch to chop the pulses up, closes the block switch for
only the period after each pi pulse where we expect the echo to be (if blocking is on).
This mode is chosen by setting the 'mode' input to a nonzero value, denoting the number of pi pulses.
If 'mode' is 1, a Hahn echo is taken, otherwise it's CPMG.
Inputs are 'pum
*/
input clk_pll, // The PLL clock
input clk, // The 12 MHz clock
// input reset, // Used only in simulation
input [23:0] per, // TODO: restore full 32-bit nature
input [15:0] p1wid,
input [15:0] del,
input [15:0] p2wid,
// input [6:0] pr_att,
// input [6:0] po_att,
input cp,
// input [7:0] p_bl,
// input [15:0] p_bl_off,
input bl,
input rxd,
// input [31:0] period, // Duty cycle (LV)
// input [31:0] p1width, // Width of the first pulse (LV)
// input [31:0] delay, // Delay between main pulses (LV)
// input [31:0] p2width, // Width of the second pulse (LV)
// // input [6:0] pre_att, // Attenuation for pump pulse (LV)
// // input [6:0] post_att, // Attenuation for second attenuator (LV)
// input cpmg, // Set mode to CW (0), Hahn echo (1) (LV)
// input [7:0] pulse_block, // Time after the second pulse to keep the block switch closed (LV)
// input [15:0] pulse_block_off, // Width of the signal window when we open the block switch (LV)
// input block, // Blocking on (1) or off (0) (LV)
output sync_on, // Wire for scope trigger pulse
output pulse_on, // Wire for switch pulse
// output [6:0] Att1, // Wires for main attenuator
// output [6:0] Att3, // Wires for second attenuator
output inhib // Wire for blocking switch pulse
);
reg [31:0] counter = 0; // 32-bit for times up to 21 seconds
reg sync;
reg pulse;
// reg [6:0] A1;
// reg [6:0] A3;
reg inh;
reg rec = 0;
reg cw = 0;
// Running at a 101.5-MHz clock, our time step is ~10 (9.95) ns.
// All these numbers are thus multiplied by 9.95 ns to get times.
// 24-bit allows periods up to 170 ms
parameter stperiod = 100500 >> 8; // 1 is a 0.652 ms period
// parameter stp1width = 30; // 298.5 ns
// parameter stp2width = 30;
// parameter stdelay = 200; // 1.99 us delay
// // parameter stblock = 100; // 500 ns block open
// parameter stcpmg = 1; // Do Hahn echo by default
// reg [31:0] period = stperiod;
// reg [15:0] p1width = stp1width;
// reg [15:0] delay = stdelay;
// reg [15:0] p2width = stp2width;
// reg [7:0] pulse_block = 8'd50;
// // reg [15:0] pulse_block_off = stblock;
// reg cpmg = stcpmg;
// reg block = 1;
// reg rx_done = 0;
// reg [15:0] p2start = stp1width+stdelay;
// reg [15:0] sync_down = stp1width+stdelay+stp2width;
// reg [15:0] block_off = stp1width+2*stdelay+stp2width-8'd50;
// reg [15:0] block_on = stp1width+2*stdelay+stp2width-8'd50+stblock;
reg [23:0] period = stperiod;
reg [15:0] p1width;
reg [15:0] delay;
reg [15:0] p2width;
reg cpmg;
reg block;
reg [7:0] pulse_block = 8'd50;
reg rx_done;
reg [15:0] p2start;
reg [23:0] sync_down;
reg [15:0] block_off;
// reg nutation_pulse = 0;
// reg [31:0] nutation_pulse_width = 32'd50;
// reg [31:0] nutation_pulse_delay = 32'd300;
// reg [31:0] nutation_pulse_start;
// reg [31:0] nutation_pulse_stop;
// reg [1:0] xfer_bits = 0;
assign sync_on = sync; // The scope trigger pulse
assign pulse_on = pulse; // The switch pulse
// assign Att1 = A1; // The main attenuator control
// assign Att3 = A3; // The second attenuator control
assign inhib = inh; // The blocking switch pulse
// assign inhib = ccount[1];
// parameter FIRST_PULSE_ON = 4'd0;
// parameter FIRST_DELAY = 4'd1;
// parameter SECOND_PULSE_ON = 4'd2;
// parameter POST_PI_PULSE = 4'd3;
// parameter FIRST_BLOCK_OFF = 4'd4;
// parameter FIRST_BLOCK_ON = 4'd5;
// parameter CPMG_PULSE_ON = 4'd6;
// parameter POST_CPMG_PULSE = 4'd7;
// parameter CPMG_BLOCK_OFF = 4'd8;
// parameter CPMG_BLOCK_ON = 4'd9;
// parameter NUTATION_PULSE_ON = 4'd10;
always @(posedge clk) begin
// { rx_done, xfer_bits } <= { xfer_bits, rxd };
// if (rx_done) begin
period <= per;
p1width <= p1wid;
p2width <= p2wid;
delay <= del;
cpmg <= cp;
block <= bl;
// end
// if (reset) begin
// counter <= 0;
// end
p2start <= p1width + delay;
sync_down <= (cpmg > 0) ? p2start + p2width : period << 7;
block_off <= p2start + p2width + delay - pulse_block;
cw <= (cpmg > 0) ? 0 : 1;
end
/* The main loops runs on the 100.5 MHz PLL clock.
*/
always @(posedge clk_pll) begin
// if (!reset) begin
// if (cpmg > 0) begin
// block_on <= block_off + pulse_block_off;
// p2start <= p1width + delay;
// sync_down <= p2start + p2width;
// block_off <= sync_down + delay - pulse_block;
case (counter)
0: begin
pulse <= 1;
inh <= block;
sync <= 1;
end
p1width: begin
pulse <= cw;
end
p2start: begin
pulse <= 1;
end
sync_down: begin
pulse <= cw;
sync <= 0;
end
block_off: begin
inh <= 0;
end
endcase // case (counter)
// pulse <= (counter < p1width) ? 1 : // Switch pulse goes up at 0 if the pump is on
// ((counter < p2start) ? cw : // then down after p1width
// ((counter < sync_down) ? 1 : cw));
// // inh <= ((counter < block_off) || (counter > block_on)) ? block : 0; // Turn the blocking switch on except for a window after the second pulse.
// inh <= (counter < (block_off)) ? block : 0; // Turn the blocking switch on except for a window after the second pulse.
// sync <= (counter < sync_down) ? 1 : 0;
// end // if (cpmg > 0)
// else begin
// pulse <= 1;
// inh <= 0;
// sync <= (counter < (period >> 1)) ? 1 : 0;
// end // else: !if(cpmg > 0)
// sync <= (counter < sync_down) ? 1 : 0;
// counter <= ((counter < period) && !reset) ? counter + 1 : 0; // Increment the counter until it reaches the period
counter <= (counter < (period << 8)) ? counter + 1 : 0; // Increment the counter until it reaches the period
// end // if (!reset)
// else begin
// counter <= 0;
// end
end // always @ (posedge clk_pll)
endmodule // pulses
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1001000; const int INF = 1e9; int n, L, U; int head[maxn], nxt[maxn << 1], rdc[maxn << 1], w[maxn << 1], tnt; int prt, rt, asiz; int siz[maxn], mdep[maxn]; int fdep, gdep; int f[maxn], g[maxn], fp[maxn], gp[maxn], dta; int q[maxn], qt, qe; int ansu, ansv; vector<int> v[maxn], t[maxn]; bool vis[maxn]; inline int read() { int res = 0; char ch = getchar(), ch1 = ch; while (!isdigit(ch)) ch1 = ch, ch = getchar(); while (isdigit(ch)) res = (res << 3) + (res << 1) + ch - 0 , ch = getchar(); return ch1 == - ? -res : res; } bool cmp(int x, int y) { return mdep[rdc[x]] < mdep[rdc[y]]; } void add(int x, int y, int z) { nxt[++tnt] = head[x]; head[x] = tnt; rdc[tnt] = y; w[tnt] = z; } void findrt(int p, int f) { int res = 0; siz[p] = 1; for (register int i = head[p]; i; i = nxt[i]) if (rdc[i] != f && !vis[rdc[i]]) { findrt(rdc[i], p); res = max(res, siz[rdc[i]]); siz[p] += siz[rdc[i]]; } res = max(res, asiz - siz[p]); if (res <= (asiz >> 1)) rt = p; } void builddfs(int p, int f) { siz[p] = 1; for (register int i = head[p]; i; i = nxt[i]) if (rdc[i] != f && !vis[rdc[i]]) { mdep[rdc[i]] = mdep[p] + 1; builddfs(rdc[i], p); siz[p] += siz[rdc[i]]; } for (register int i = head[p]; i; i = nxt[i]) if (rdc[i] != f && !vis[rdc[i]]) mdep[p] = max(mdep[p], mdep[rdc[i]]); } void build(int p) { vis[p] = true; mdep[p] = 0; for (register int i = head[p]; i; i = nxt[i]) { if (vis[rdc[i]]) continue; mdep[rdc[i]] = 1; builddfs(rdc[i], p); mdep[p] = max(mdep[p], mdep[rdc[i]]); v[p].push_back(i); } sort(v[p].begin(), v[p].end(), cmp); for (register int i = head[p]; i; i = nxt[i]) { if (vis[rdc[i]]) continue; asiz = siz[rdc[i]]; findrt(rdc[i], p); t[p].push_back(rt); build(rt); } vis[p] = false; } void dfs(int p, int f, int dep, int pv) { if (g[dep] < pv) { g[dep] = pv; gp[dep] = p; } for (register int i = head[p]; i; i = nxt[i]) if (rdc[i] != f && !vis[rdc[i]]) dfs(rdc[i], p, dep + 1, pv + (w[i] >= dta ? 1 : -1)); gdep = max(gdep, dep); } bool check(int p) { if ((mdep[p] << 1) < L) return false; bool flag = false; vis[p] = true; fp[0] = gp[0] = p; for (register int i = 0; i < v[p].size() && !flag; ++i) { dfs(rdc[v[p][i]], p, 1, (w[v[p][i]] >= dta ? 1 : -1)); qt = 1; qe = 0; for (register int j = 0, k = min(fdep, U); j <= gdep; ++j) { while (qt <= qe && q[qt] + j > U) ++qt; while (j + k >= L && k >= 0) { while (qt <= qe && f[q[qe]] <= f[k]) --qe; q[++qe] = k; --k; } if (qt <= qe && g[j] + f[q[qt]] >= 0) { flag = true; ansu = gp[j]; ansv = fp[q[qt]]; break; } } fdep = gdep; while (gdep) { if (f[gdep] < g[gdep]) { f[gdep] = g[gdep]; fp[gdep] = gp[gdep]; } g[gdep] = -INF; --gdep; } } while (fdep) { f[fdep] = -INF; --fdep; } if (flag) { vis[p] = false; return true; } for (register int i = 0; i < t[p].size(); ++i) if (check(t[p][i])) { vis[p] = false; return true; } vis[p] = false; return false; } int main() { n = read(); L = read(); U = read(); for (int i = 1, x, y, z; i < n; ++i) { x = read(); y = read(); z = read(); add(x, y, z); add(y, x, z); } asiz = n; findrt(1, 0); build(prt = rt); for (register int i = 0; i <= n; ++i) f[i] = g[i] = -INF; f[0] = g[0] = 0; int l = -1, r = 1e9; while (l < r) { dta = (l + r + 1) >> 1; if (check(prt)) l = dta; else r = dta - 1; } dta = l; check(l); printf( %d %d n , ansu, ansv); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, cnt; vector<int> e[N]; vector<pair<int, int> > ans; void init() { scanf( %d , &n); for (int i = 1, x, y; i < n; ++i) { scanf( %d %d , &x, &y); e[x].push_back(y); e[y].push_back(x); } } void dfs(int x, int father, int last_idx) { int pre = last_idx; for (int i = 0; i < e[x].size(); ++i) if (e[x][i] != father) { printf( 2 %d %d n , x, e[x][i]); cnt++; if (pre != -1) ans.push_back(make_pair(pre, cnt)); pre = cnt; dfs(e[x][i], x, cnt); } } void solve() { printf( %d n , n - 1); cnt = 0; dfs(1, -1, -1); for (int i = 0; i < ans.size(); ++i) printf( %d %d n , ans[i].first, ans[i].second); } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) using namespace std; int a, b, c, d, n, m, k; long long pc[1000001]; long long dp[7][333335]; int f[6]; const int N = 333333; const long long infll = (long long)1000000000 * 1000000000; inline void upd(long long& a, long long b) { if (a < b) a = b; } long long solve(int n) { long long ans = pc[n]; for (int _n((n)-1), i(0); i <= _n; i++) { int rem = n - i; if (rem % 3) continue; ans = max(ans, pc[i] + dp[5][rem / 3]); } return ans; } int main() { scanf( %d , &k); --k; for (int _n((6) - 1), i(0); i <= _n; i++) scanf( %d , &f[i]); pc[0] = 0; for (int _n((999999)), i(1); i <= _n; i++) { int t = i; long long a = 0; for (int _n((6) - 1), j(0); j <= _n; j++) { int dig = t % 10; if (dig == 3 || dig == 6 || dig == 9) { a += (long long)f[j] * (dig / 3); } t /= 10; } pc[i] = a; } for (int _n((7) - 1), i(0); i <= _n; i++) for (int _n((N + 2) - 1), j(0); j <= _n; j++) dp[i][j] = -8 * infll; for (int _n((N + 1) - 1), i(0); i <= _n; i++) { if (i > 3 * k) break; dp[0][i] = (long long)f[0] * i; } auto ev1 = [&](int i, int s) { return (long long)i * (f[1] - 10LL * f[0]) + (long long)s * f[0]; }; for (int _n((N + 1) - 1), i(0); i <= _n; i++) { if (i > 33LL * k) break; int l = 0; if (i > 3 * k) { int rem = i - 3 * k; l = rem / 10; if (rem % 10) ++l; } int r = min(3 * k, i / 10); if (l > r) continue; dp[1][i] = max(ev1(l, i), ev1(r, i)); } for (int _n(5), d(2); d <= _n; d++) { long long o = 0; for (int _n((d + 1) - 1), z(0); z <= _n; z++) o = o * 10 + 3; o *= k; o = min<long long>(o, N); int t = 1; for (int _n((d)-1), j(0); j <= _n; j++) t *= 10; for (int _n((o + 1) - 1), i(0); i <= _n; i++) { int r = min(3 * k, i / t); long long cd = 0; for (int _n((r + 1) - 1), j(0); j <= _n; j++) { upd(cd, dp[d - 1][i - j * t] + (long long)f[d] * j); } dp[d][i] = cd; } } scanf( %d , &m); for (int _n((m)), hod(1); hod <= _n; hod++) { scanf( %d , &n); long long ans = solve(n); printf( %I64d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; pair<int, int> A[N]; int factorial[N]; int twos[N]; int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = (int)0; i < (int)2 * n; i++) { cin >> A[i].first; A[i].second = i % n; } sort(A, A + 2 * n); int MOD; cin >> MOD; factorial[0] = 1; twos[0] = 0; for (int i = (int)1; i < (int)2 * n + 1; i++) { if (i % 2 == 0) twos[i] = 1 + twos[i / 2]; else twos[i] = 0; int ti = i; while (ti % 2 == 0) ti /= 2; factorial[i] = (ti * (long long int)factorial[i - 1]) % MOD; } for (int i = (int)0; i < (int)2 * n; i++) twos[i + 1] += twos[i]; n *= 2; int ans = 1; for (int i = 0; i < n;) { int endi = i; while (endi < n and A[endi].first == A[i].first) endi++; int numduplicates = 0; for (int j = (int)i; j < (int)endi; j++) if (j + 1 < endi and A[j].second == A[j + 1].second) numduplicates++; int len = endi - i; ans = (ans * (long long int)factorial[len]) % MOD; int ntwos = twos[len] - numduplicates; for (int x = (int)0; x < (int)ntwos; x++) { ans = (ans * 2) % MOD; } i = endi; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int maxn = 2e5 + 50; const long long inf = 1e17; int t; void get() { fflush(stdout); scanf( %d , &t); for (int i = 1; i <= t; i++) scanf( %*s ); } int main() { do { puts( next 0 1 ), get(); puts( next 0 ), get(); } while (t == 3); do { puts( next 0 1 2 3 4 5 6 7 8 9 ), get(); } while (t == 2); puts( done ); return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module hb_interp_tb( ) ;
// Parameters for instantiation
parameter clocks = 8'd2 ; // Number of clocks per output
parameter decim = 1 ; // Sets the filter to decimate
parameter rate = 2 ; // Sets the decimation rate
reg clock ;
reg reset ;
reg enable ;
wire strobe_in ;
reg signed [17:0] data_in ;
wire strobe_out ;
wire signed [17:0] data_out ;
initial
begin
$dumpfile("hb_interp_tb.vcd");
$dumpvars(0,hb_interp_tb);
end
// Setup the clock
initial clock = 1'b0 ;
always #5 clock <= ~clock ;
// Come out of reset after a while
initial reset = 1'b1 ;
initial #1000 reset = 1'b0 ;
always @(posedge clock)
enable <= ~reset;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
cic_strober #(.WIDTH(8))
out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks),
.strobe_fast(1),.strobe_slow(strobe_out) );
cic_strober #(.WIDTH(8))
in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2),
.strobe_fast(strobe_out),.strobe_slow(strobe_in) );
hb_interp #() uut
(.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in),
.stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) );
integer i, ri, ro, infile, outfile ;
always @(posedge clock)
begin
if(strobe_out)
$display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat","r") ;
outfile = $fopen("output.dat","r") ;
$timeformat(-9, 2, " ns", 10) ;
end
reg endofsim ;
reg signed [17:0] compare ;
integer noe ;
initial noe = 0 ;
initial begin
// Initialize inputs
data_in <= 18'd0 ;
// Wait for reset to go away
@(negedge reset) #0 ;
// While we're still simulating ...
while( !endofsim ) begin
// Write the input from the file or 0 if EOF...
@( negedge clock ) begin
if(strobe_in)
if( !$feof(infile) )
ri <= #1 $fscanf( infile, "%d", data_in ) ;
else
data_in <= 18'd0 ;
end
end
// Print out the number of errors that occured
if( noe )
$display( "FAILED: %d errors during simulation", noe ) ;
else
$display( "PASSED: Simulation successful" ) ;
$finish ;
end
// Output comparison of simulated values versus known good values
always @ (posedge clock) begin
if( reset )
endofsim <= 1'b0 ;
else begin
if( !$feof(outfile) ) begin
if( strobe_out ) begin
ro = $fscanf( outfile, "%d\n", compare ) ;
if( compare != data_out ) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1 ;
end
end
end else begin
// Signal end of simulation when no more outputs
if($feof(infile))
endofsim <= 1'b1 ;
end
end
end
endmodule // small_hb_int_tb
|
#include <bits/stdc++.h> using namespace std; int row[1010]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); memset(row, 0x3f3f3f3f, sizeof row); long long ans = 0; for (int i = (0); i < (n); ++i) { int r, c; scanf( %d %d , &r, &c); row[r] = min(c, row[r]); } for (int i = 1; i <= m; ++i) ans += ((row[i] == 0x3f3f3f3f) ? 0 : row[i]); printf( %lld n , min(ans, (long long)k)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_2_V
`define SKY130_FD_SC_MS__O211A_2_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_2_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int sum = 0; char c = getchar(); bool f = 0; while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } if (f) return -sum; return sum; } const int N = 200005; const int orz = 2000000; const int otz = 1000000005; int n, K, d, a[N], b[N], c[N]; namespace Seg { int lazy[N * 4], t[N * 4], v, rch; inline void push(int p) { if (!lazy[p]) return; int x = lazy[p], l = p << 1, r = (l | 1); t[l] += x; t[r] += x; lazy[l] += x; lazy[r] += x; lazy[p] = 0; } inline void ch(int p, int l, int r, int L, int R) { if (l == L && r == R) { lazy[p] += v; t[p] += v; return; } int mid = (l + r) >> 1; push(p); if (R <= mid) ch(p << 1, l, mid, L, R); else if (L > mid) ch(p << 1 | 1, mid + 1, r, L, R); else ch(p << 1, l, mid, L, mid), ch(p << 1 | 1, mid + 1, r, mid + 1, R); t[p] = min(t[p << 1], t[p << 1 | 1]); } inline void ask(int p, int l, int r) { if (l == r) { rch = l; return; } int mid = (l + r) >> 1; push(p); if (t[p << 1] < K) ask(p << 1, l, mid); else ask(p << 1 | 1, mid + 1, r); } } // namespace Seg using namespace Seg; int s1[N], s2[N], t1, t2; map<int, int> H; int main() { int i, r, st = 1, ed = 1, ans = 1, ino = 0; n = read(); K = read(); d = read(); for (i = 1; i <= n; i++) a[i] = read() + otz; if (!d) { for (i = 1; i <= n; i = r) { r = i; while (r <= n && a[r] == a[i]) r++; if (r - i > ans) ans = r - i, st = i, ed = r - 1; } printf( %d %d , st, ed); return 0; } for (i = 1; i <= n; i++) b[i] = a[i] % d, c[i] = a[i] / d; a[0] = a[1]; b[0] = b[1]; v = orz; ch(1, 1, n, 1, n); for (i = 1; i <= n; i++) { if (b[i] != b[i - 1]) v = orz, ch(1, 1, n, ino + 1, i - 1), ino = i - 1; if (H[a[i]] > ino) v = orz, ch(1, 1, n, ino + 1, H[a[i]]), ino = H[a[i]]; while (t1 && a[i] > a[s1[t1]]) v = c[i] - c[s1[t1]], ch(1, 1, n, s1[t1 - 1] + 1, s1[t1]), t1--; while (t2 && a[i] < a[s2[t2]]) v = c[s2[t2]] - c[i], ch(1, 1, n, s2[t2 - 1] + 1, s2[t2]), t2--; H[a[i]] = i; s1[++t1] = i; s2[++t2] = i; v = -1; ch(1, 1, n, 1, i); v = -orz; ch(1, 1, n, i, i); ask(1, 1, n); if (i - rch + 1 > ans) ans = i - rch + 1, st = rch, ed = i; } printf( %d %d , st, ed); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solve() { map<int, int> cnt; int n; cin >> n; for (int i = 0; i < n; ++i) { int x; cin >> x; cnt[x]++; } int a = -1; for (int i = 0; i <= 101; ++i) { if (cnt[i] == 0) { cout << i + (a == -1 ? i : a) << n ; return; } else if (cnt[i] == 1 and a == -1) { a = i; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T = 1, tc = 1; cin >> T; while (T--) { solve(); } return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// ,
//
// Create Date: 16:54:00 06/03/2014
// Design Name: tb_signal_gen
// Module Name: tb_signal_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Testbenc for "Testbench signal generation" for gates test
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_signal_gen;
// Praramers
parameter INPUT_PORTS = 3;
// Inputs
reg clk;
reg rst;
reg req;
// Outputs
wire [INPUT_PORTS-1:0] stm_value;
wire gnt;
// Instantiate the Unit Under Test (UUT)
signal_gen
#(.INPUT_PORTS(INPUT_PORTS))
uut (
.clk(clk),
.rst(rst),
.req(req),
.stm_value(stm_value),
.gnt(gnt)
);
parameter PERIOD = 10;
always begin
clk = 1'b0;
#(PERIOD/2)
clk = 1'b1;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
rst = 1;
req = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
req = 0;
// Add stimulus here
#100;
req = 1;
$display($time, " << Starting the Simulation >>");
#100;
req = 0;
$monitor(" %0d %b", $time, gnt);
wait(gnt)
begin
$display($time, " << Finishing the Simulation >>");
$stop;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_0 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
/*
File: ewrapper_io_tx_slow.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_tx_slow (/*AUTOARG*/
// Outputs
DATA_OUT_TO_PINS_P, DATA_OUT_TO_PINS_N, LCLK_OUT_TO_PINS_P,
LCLK_OUT_TO_PINS_N,
// Inputs
CLK_IN, CLK_IN_90, CLK_DIV_IN, CLK_RESET, IO_RESET,
DATA_OUT_FROM_DEVICE
);
//###########
//# INPUTS
//###########
input CLK_IN; // Fast clock input from PLL/MMCM
input CLK_IN_90; // Fast clock input with 90deg phase shift
input CLK_DIV_IN; // Slow clock input from PLL/MMCM
input CLK_RESET;
input IO_RESET;
input [71:0] DATA_OUT_FROM_DEVICE;
//#############
//# OUTPUTS
//#############
output [8:0] DATA_OUT_TO_PINS_P;
output [8:0] DATA_OUT_TO_PINS_N;
output LCLK_OUT_TO_PINS_P;
output LCLK_OUT_TO_PINS_N;
//############
//# REGS
//############
reg [1:0] clk_cnt;
reg tx_coreclock_del_45;
reg tx_coreclock_del_135;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [71:0] tx_in_sync;
//############
//# WIRES
//############
wire txo_lclk;
wire txo_lclk90;
wire tx_coreclock;
wire reset;
wire tx_pedge_first;
wire [8:0] clk_even;
wire [8:0] clk0_even;
wire [8:0] clk1_even;
wire [8:0] clk2_even;
wire [8:0] clk3_even;
wire [8:0] clk_odd;
wire [8:0] clk0_odd;
wire [8:0] clk1_odd;
wire [8:0] clk2_odd;
wire [8:0] clk3_odd;
wire cycle_sel_0;
wire cycle_sel_1;
wire cycle_sel_2;
wire cycle_sel_3;
wire [71:0] tx_in;
wire [8:0] tx_out;
wire tx_lclk_out;
wire [8:0] DATA_OUT_TO_PINS_P;
wire [8:0] DATA_OUT_TO_PINS_N;
wire LCLK_OUT_TO_PINS_P;
wire LCLK_OUT_TO_PINS_N;
wire [8:0] oddr_data_d1;
wire [8:0] oddr_data_d2;
wire oddr_clk_d1;
wire oddr_clk_d2;
/*AUTOINPUT*/
/*AUTOWIRE*/
`ifdef EP64
assign oddr_data_d1[8:0] = ~clk_even_reg[8:0];
assign oddr_data_d2[8:0] = ~clk_odd_reg[8:0];
assign oddr_clk_d1 = 1'b0;
assign oddr_clk_d2 = 1'b1;
`else
assign oddr_data_d1[8:0] = clk_even_reg[8:0];
assign oddr_data_d2[8:0] = clk_odd_reg[8:0];
assign oddr_clk_d1 = 1'b1;
assign oddr_clk_d2 = 1'b0;
`endif
assign reset = CLK_RESET;
assign tx_in[71:0] = DATA_OUT_FROM_DEVICE[71:0];
assign txo_lclk = CLK_IN;
assign txo_lclk90 = CLK_IN_90;
assign tx_coreclock = CLK_DIV_IN;
//#################################################
//# Synchronize incoming data to fast clock domain
//#################################################
always @ (posedge txo_lclk or posedge reset)
if(reset)
tx_in_sync[71:0] <= {(72){1'b0}};
else if(tx_pedge_first)
tx_in_sync[71:0] <= tx_in[71:0];
//################################
//# Output Buffers Instantiation
//################################
genvar pin_count;
generate
for (pin_count = 0; pin_count < 9; pin_count = pin_count + 1) begin: pins
OBUFDS #(.IOSTANDARD (`IOSTND)) obufds_inst
(.O (DATA_OUT_TO_PINS_P[pin_count]),
.OB (DATA_OUT_TO_PINS_N[pin_count]),
.I (tx_out[pin_count]));
end
endgenerate
OBUFDS #(.IOSTANDARD (`IOSTND)) obufds_lclk_inst
(.O (LCLK_OUT_TO_PINS_P),
.OB (LCLK_OUT_TO_PINS_N),
.I (tx_lclk_out));
//#############################
//# ODDR instantiation
//#############################
genvar oddr_cnt;
generate
for (oddr_cnt = 0; oddr_cnt < 9; oddr_cnt = oddr_cnt + 1) begin: oddrs
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_inst (
.Q (tx_out[oddr_cnt]),
.C (txo_lclk),
.CE (1'b1),
.D1 (oddr_data_d1[oddr_cnt]),
.D2 (oddr_data_d2[oddr_cnt]),
.R (reset),
.S (1'b0));
end
endgenerate
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst (
.Q (tx_lclk_out),
.C (txo_lclk90),
.CE (1'b1),
.D1 (oddr_clk_d1),
.D2 (oddr_clk_d2),
.R (reset),
.S (1'b0));
//########################
//# Data Serialization
//########################
always @ (posedge txo_lclk or posedge reset)
if(reset)
begin
clk_even_reg[8:0] <= {(9){1'b0}};
clk_odd_reg[8:0] <= {(9){1'b0}};
end
else
begin
clk_even_reg[8:0] <= clk_even[8:0];
clk_odd_reg[8:0] <= clk_odd[8:0];
end
mux4 #(18) mux4(// Outputs
.out ({clk_even[8:0],clk_odd[8:0]}),
// Inputs
.in0 ({clk0_even[8:0],clk0_odd[8:0]}), .sel0 (cycle_sel_0),
.in1 ({clk1_even[8:0],clk1_odd[8:0]}), .sel1 (cycle_sel_1),
.in2 ({clk2_even[8:0],clk2_odd[8:0]}), .sel2 (cycle_sel_2),
.in3 ({clk3_even[8:0],clk3_odd[8:0]}), .sel3 (cycle_sel_3));
//#################################
//# Serialization Cycle Counter
//#################################
assign cycle_sel_0 = (clk_cnt[1:0] == 2'b00);
assign cycle_sel_1 = (clk_cnt[1:0] == 2'b01);
assign cycle_sel_2 = (clk_cnt[1:0] == 2'b10);
assign cycle_sel_3 = (clk_cnt[1:0] == 2'b11);
always @ (posedge txo_lclk or posedge reset)
if(reset)
clk_cnt[1:0] <= 2'b00;
else if(tx_pedge_first)
clk_cnt[1:0] <= 2'b00;
else
clk_cnt[1:0] <= clk_cnt[1:0] + 2'b01;
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge txo_lclk)
tx_coreclock_del_45 <= tx_coreclock;
always @ (negedge txo_lclk)
tx_coreclock_del_135 <= tx_coreclock_del_45;
assign tx_pedge_first = tx_coreclock_del_45 & ~tx_coreclock_del_135;
//##################################
//# Data Alignment Channel-to-Byte
//##################################
assign clk0_even[8:0] ={tx_in_sync[71],tx_in_sync[63],tx_in_sync[55],
tx_in_sync[47],tx_in_sync[39],tx_in_sync[31],
tx_in_sync[23],tx_in_sync[15],tx_in_sync[7]};
assign clk0_odd[8:0] ={tx_in_sync[70],tx_in_sync[62],tx_in_sync[54],
tx_in_sync[46],tx_in_sync[38],tx_in_sync[30],
tx_in_sync[22],tx_in_sync[14],tx_in_sync[6]};
assign clk1_even[8:0] ={tx_in_sync[69],tx_in_sync[61],tx_in_sync[53],
tx_in_sync[45],tx_in_sync[37],tx_in_sync[29],
tx_in_sync[21],tx_in_sync[13],tx_in_sync[5]};
assign clk1_odd[8:0] ={tx_in_sync[68],tx_in_sync[60],tx_in_sync[52],
tx_in_sync[44],tx_in_sync[36],tx_in_sync[28],
tx_in_sync[20],tx_in_sync[12],tx_in_sync[4]};
assign clk2_even[8:0] ={tx_in_sync[67],tx_in_sync[59],tx_in_sync[51],
tx_in_sync[43],tx_in_sync[35],tx_in_sync[27],
tx_in_sync[19],tx_in_sync[11],tx_in_sync[3]};
assign clk2_odd[8:0] ={tx_in_sync[66],tx_in_sync[58],tx_in_sync[50],
tx_in_sync[42],tx_in_sync[34],tx_in_sync[26],
tx_in_sync[18],tx_in_sync[10],tx_in_sync[2]};
assign clk3_even[8:0] ={tx_in_sync[65],tx_in_sync[57],tx_in_sync[49],
tx_in_sync[41],tx_in_sync[33],tx_in_sync[25],
tx_in_sync[17],tx_in_sync[9], tx_in_sync[1]};
assign clk3_odd[8:0] ={tx_in_sync[64],tx_in_sync[56],tx_in_sync[48],
tx_in_sync[40],tx_in_sync[32],tx_in_sync[24],
tx_in_sync[16],tx_in_sync[8], tx_in_sync[0]};
endmodule // ewrapper_io_tx_slow
|
module reset_test_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
reg [1:0] i;
wire [0:0] rval;
assign rval = {reset, 1'b0 };
always @(posedge clk)
begin
case (|(reset))
1'b 1:
begin
case (({(0)*(rval)})+(0))
0:
dout[31:0] <= 57005;
1:
dout[31:1] <= 57005;
2:
dout[31:2] <= 57005;
3:
dout[31:3] <= 57005;
4:
dout[31:4] <= 57005;
5:
dout[31:5] <= 57005;
6:
dout[31:6] <= 57005;
7:
dout[31:7] <= 57005;
8:
dout[31:8] <= 57005;
9:
dout[31:9] <= 57005;
10:
dout[31:10] <= 57005;
11:
dout[31:11] <= 57005;
12:
dout[31:12] <= 57005;
13:
dout[31:13] <= 57005;
14:
dout[31:14] <= 57005;
15:
dout[31:15] <= 57005;
16:
dout[31:16] <= 57005;
17:
dout[31:17] <= 57005;
18:
dout[31:18] <= 57005;
19:
dout[31:19] <= 57005;
20:
dout[31:20] <= 57005;
21:
dout[31:21] <= 57005;
22:
dout[31:22] <= 57005;
23:
dout[31:23] <= 57005;
24:
dout[31:24] <= 57005;
25:
dout[31:25] <= 57005;
26:
dout[31:26] <= 57005;
27:
dout[31:27] <= 57005;
28:
dout[31:28] <= 57005;
29:
dout[31:29] <= 57005;
30:
dout[31:30] <= 57005;
31:
dout[31:31] <= 57005;
endcase
i = 1;
end
endcase
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
end
endmodule
|
//
// my_fpga.v
//
module my_fpga (
input clk, n_rst,
input up, dn,
output [31:0] cnt,
output [3:0] cnt_1k,
input in1, in2,
output out1, out2);
reg rst;
reg [1:0] rst_sr;
reg [31:0] count;
reg [16:0] div_count;
reg [3:0] count_1k;
or_gate g1(in1, in2, out1);
and_gate g2(in1, in2, out2);
assign cnt = count;
assign cnt_1k = count_1k;
always @(posedge clk, posedge rst) begin
if (rst)
count <= 0;
else begin
if (up)
count <= count + 1;
else if (dn)
count <= count - 1;
end
end
always @(posedge clk, posedge rst) begin
if (rst) begin
div_count <= 0;
count_1k <= 0;
end
else begin
if (div_count == 99999) begin
div_count <= 0;
if (up)
count_1k <= count_1k + 1;
else if (dn)
count_1k <= count_1k - 1;
end
else
div_count <= div_count + 1;
end
end
always @(posedge clk, negedge n_rst) begin
if (n_rst == 0) begin
rst_sr <= 2'b11;
rst <= 1;
end
else begin
rst <= rst_sr[1];
rst_sr[1] <= rst_sr[0];
rst_sr[0] <= ~ n_rst;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_4_V
`define SKY130_FD_SC_MS__A41O_4_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41o_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41o_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_4_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > v; long long x; long long k; int broj; int main(void) { cin >> x; k = 0; long long i = 1; for (long long i = 1; i <= sqrt(x); ++i) { if (k + i * i > (1000000000000000000)) goto van; k = k + i * i; if (x - k < 0) goto van; if ((2 * (x - k)) % (i * (i + 1)) == 0) { v.push_back( pair<long long, long long>(i, i + (2 * (x - k)) / (i * (i + 1)))); } } van:; for (int i = 0; i < v.size(); ++i) { broj++; } for (int i = v.size() - 1; i >= 0; --i) { if (v[i].second == v[i].first) continue; broj++; } cout << broj << endl; for (int i = 0; i < v.size(); ++i) { broj++; cout << v[i].first << << v[i].second << endl; } for (int i = v.size() - 1; i >= 0; --i) { if (v[i].second == v[i].first) continue; broj++; cout << v[i].second << << v[i].first << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; constexpr int INF = 1e9 + 1; constexpr long long LLINF = 1e18 + 1; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } void solve() { int n, t; cin >> n; vector<int> arr(101); for (__typeof(n) i = 0; i < n; i++) { cin >> t; arr[t] = 1; } int col = 0; for (int i = 1; i <= 100; i++) if (arr[i]) { for (int j = i; j <= 100; j += i) { arr[j] = 0; } col++; } printf( %d n , col); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int t = 1; while (t--) solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V
|
module ereset (/*AUTOARG*/
// Outputs
etx_reset, erx_reset, sys_reset,etx90_reset,erx_ioreset,
// Inputs
reset, sys_clk, tx_lclk_div4, rx_lclk_div4,tx_lclk90,rx_lclk
);
// reset inputs
input reset; // POR | ~elink_en (with appropriate delays..)
//synchronization clocks
input sys_clk; // system clock
input tx_lclk_div4; // slow clock for TX
input rx_lclk_div4; // slow clock for RX
input tx_lclk90;
input rx_lclk;
//synchronous reset outputs
output etx_reset; // reset for TX slow logic
output erx_reset; // reset for RX slow logic
output sys_reset; // reset for system FIFOs
output etx90_reset;
output erx_ioreset;
reg erx_ioresetb;
reg erx_resetb;
reg etx_resetb;
reg sys_resetb;
reg etx90_resetb;
/*
//erx reset synchronizer
synchronizer sync_erx (.out (erx_resetb),
.in (1'b1),
.clk (rx_lclk_div4),
.reset (reset)
);
//etx reset synchronizer
synchronizer sync_etx (.out (etx_resetb),
.in (1'b1),
.clk (tx_lclk_div4),
.reset (reset)
);
//system reset synchronizer
synchronizer sync_sys (.out (sys_resetb),
.in (1'b1),
.clk (sys_clk),
.reset (reset)
);
*/
always @ (posedge rx_lclk_div4)
erx_resetb <= reset;
always @ (posedge tx_lclk_div4)
etx_resetb <= reset;
always @ (posedge sys_clk)
sys_resetb <= reset;
always @ (posedge tx_lclk90)
etx90_resetb <= reset;
always @ (posedge rx_lclk)
erx_ioresetb <= reset;
assign erx_ioreset =erx_ioresetb;
assign etx_reset =etx_resetb;
assign erx_reset =erx_resetb;
assign sys_reset =sys_resetb;
assign etx90_reset =etx90_resetb;
endmodule // ereset
// Local Variables:
// verilog-library-directories:("." "../../common/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 13:37:41 09/20/2011
// Module Name: uart_light_tx
//////////////////////////////////////////////////////////////////////////////////
module uart_light_tx
#(
parameter WORD_SIZE = 8,
parameter FIFO_ADDR_BITS = 5
)(
input wire reset,
input wire clk_peri,
input wire clk_tx,
input wire word_ready,
input wire [WORD_SIZE-1:0] word_tx,
output wire tx,
output wire fifo_tx_full,
output wire fifo_tx_empty,
output wire fifo_tx_read
);
wire frame_done,transmit,clear,fifo_read_enable,fifo_full,fifo_empty,fifo_write_enable;
assign fifo_tx_read = fifo_read_enable;
uart_light_tx_ctrl
tx_ctrl0
(
.reset(reset),
.clk_tx(clk_tx),
.word_ready(word_ready),
.fifo_tx_full(fifo_tx_full),
.fifo_tx_empty(fifo_tx_empty),
.frame_done(frame_done),
.transmit(transmit),
.clear(clear),
.fifo_read_enable(fifo_read_enable),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty),
.fifo_write_enable(fifo_write_enable)
);
uart_light_tx_dp
#(
.FIFO_ADDR_BITS(FIFO_ADDR_BITS)
)
tx_dp0
(
.reset(reset),
.clk_peri(clk_peri),
.clk_tx(clk_tx),
.tx(tx),
.word_tx(word_tx),
.transmit(transmit),
.clear(clear),
.fifo_read_enable(fifo_read_enable),
.frame_done(frame_done),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty),
.fifo_write_enable(fifo_write_enable)
);
endmodule
|
#include <bits/stdc++.h> const int N = 1e3 + 5; using namespace std; int main() { ios::sync_with_stdio(false); int arr[N][N], str, sve, k, n[N], m[N], i, j, x, y; char ch; cin >> str >> sve >> k; for (i = 1; i <= str; i++) for (j = 1; j <= sve; j++) cin >> arr[i][j]; for (i = 1; i <= N; i++) n[i] = m[i] = i; while (k--) { cin >> ch >> x >> y; if (ch == r ) swap(n[x], n[y]); else if (ch == c ) swap(m[x], m[y]); else cout << arr[n[x]][m[y]] << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLXTP_BLACKBOX_V
/**
* srdlxtp: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 06:19:33 AM
// Design Name:
// Module Name: Barrel_Shifter_M
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Barrel_Shifter_M
#(parameter SW=26)
(
input wire clk,
input wire rst,
input wire load_i,
input wire Shift_Value_i,
input wire [SW-1:0] Shift_Data_i,
/////////////////////////////////////////////7
output wire [SW-1:0] N_mant_o
);
wire [SW-1:0] Data_Reg;
////////////////////////////////////////////////////7
shift_mux_array #(.SWR(SW), .LEVEL(0)) shift_mux_array(
.Data_i(Shift_Data_i),
.select_i(Shift_Value_i),
.bit_shift_i(1'b1),
.Data_o(Data_Reg)
);
RegisterMult #(.W(SW)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:35:35 07/12/2015
// Design Name:
// Module Name: Distributed_RAM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Distributed_RAM(
Clock_in,
Write_Enable_in,
Address_in,
Data_in,
Data_out
);
parameter AddressWidth = 8;
parameter DataWidth = 8;
parameter Depth = 256;
input Clock_in;
input Write_Enable_in;
input [AddressWidth-1:0]Address_in;
input [DataWidth-1:0]Data_in;
output [DataWidth-1:0]Data_out;
(* ram_style = "distributed" *)
reg [DataWidth-1:0] RAM [Depth-1:0];
integer i;
initial begin
for (i = 0; i < Depth; i = i + 1) begin
RAM[i] = {DataWidth{1'b0}};
end
end
always @ (posedge Clock_in) begin
if (Write_Enable_in) begin
RAM[Address_in]<=Data_in;
end
end
assign Data_out = RAM[Address_in];
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, ta; int b, tb; int h, m; bool read() { if (!(cin >> a >> ta)) return false; assert(cin >> b >> tb); assert(scanf( %d:%d , &h, &m) == 2); return true; } void solve() { int x1 = h * 60 + m; int y1 = x1 + ta; int ans = 0; for (int x2 = 5 * 60 + 0; x2 < 24 * 60; x2 += b) { int y2 = x2 + tb; int x = max(x1, x2), y = min(y1, y2); if (x < y) ans++; } cout << ans << endl; } int main() { read(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, num = 1, mul; cin >> n; string s = codeforces ; int ln = s.length(), a[12] = {0}; for (long long int i = 2; i <= 100; i++) { long long int curr = pow(i, 10ll); if (curr >= n) { for (int j = 0; j < 10; j++) { a[j] = i - 1; num *= (i - 1); } mul = i; break; } } int pos = 0; while (num < n) { num /= (mul - 1); num *= mul; a[pos] = mul; pos++; } for (int i = 0; i < 10; i++) { for (int j = 0; j < a[i]; j++) cout << s[i]; } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug511
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [7:0] au;
wire [7:0] as;
Test1 test1 (.au);
Test2 test2 (.as);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] result=%x %x\n", $time, au, as);
`endif
if (au != 'h12) $stop;
if (as != 'h02) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test1 (output [7:0] au);
wire [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign au=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
module Test2 (output [7:0] as);
wire signed [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign as=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3010, Mo = 1000000007; int tt, n, D; int f[N][N], rev[N * 2], head[N], to[N], nxt[N]; inline int gi() { int x = 0, o = 1; char ch = getchar(); while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } inline void dfs(int x) { for (int i = 1; i <= n; i++) f[x][i] = 1; for (int i = head[x]; i; i = nxt[i]) { int y = to[i]; dfs(y); for (int j = 1; j <= n; j++) f[x][j] = 1LL * f[x][j] * f[y][j] % Mo; } for (int i = 2; i <= n; i++) f[x][i] = (f[x][i - 1] + f[x][i]) % Mo; } inline int Pow(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = 1LL * ret * x % Mo; x = 1LL * x * x % Mo, y >>= 1; } return ret; } int main() { cin >> n >> D; for (int i = 2, x; i <= n; i++) to[++tt] = i, nxt[tt] = head[x = gi()], head[x] = tt; dfs(1); if (D <= n) return cout << f[1][D], 0; int ans = 0; for (int i = -n; i <= n; i++) rev[i + n] = Pow(i, Mo - 2); for (int i = 0; i <= n; i++) { int sum = f[1][i]; for (int j = 0; j <= n; j++) if (i != j) sum = 1LL * sum * (D - j) % Mo * rev[i - j + n] % Mo; (ans += sum) %= Mo; } cout << (ans + Mo) % Mo; return 0; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_logic_op.v
// Title : Logic operations (and / or / not etc)
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_logic_op (
// ----- Inputs -------
logic_op_x,
operand_0_x,
operand_1_x,
// ----- Outputs -------
logic_result_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [`LM32_LOGIC_OP_RNG] logic_op_x;
input [`LM32_WORD_RNG] operand_0_x;
input [`LM32_WORD_RNG] operand_1_x;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] logic_result_x;
reg [`LM32_WORD_RNG] logic_result_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
integer logic_idx;
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
always @(*)
begin
for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
end
endmodule
|
#include <bits/stdc++.h> int n, k, s, e, m, ans, temp, tp, tv; bool m11, m22, first, b[100005], move; char a[100005]; int dist() { if (m - s < e - m) return e - m; else return m - s; } int main() { scanf( %d %d , &n, &k); scanf( %s , a); for (e = 0; e < n; e++) { if (a[e] == 0 ) temp++; if (a[e] == 0 && !first) s = e, first = true; if (temp >= k + 1) break; } m = s; ans = dist(); while (e < n) { tv = dist(); tp = m; move = false; if (ans > dist()) { ans = dist(); } while (m <= e) { m++; if (a[m] == 0 ) { if (tv > dist()) { tv = dist(); tp = m; if (ans > dist()) { ans = dist(); } } else { m = tp; break; } } } while (e < n) { e++; if (e < n && a[e] == 0 ) { while (true) { s++; if (a[s] == 0 ) { if (m < s) { m = s; } move = true; break; } } } if (move) break; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> int main() { int n, b = 1, i = 1; scanf( %d , &n); for (i = 1; i < n; i++) { b = b + i; if (b > n) b = b % n; printf( %d n , b); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, const U &b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, const U &b) { if (a < b) a = b; } int a[2020]; struct Dinic { int V, E, src, tar; int head[2020], work[2020], dis[2020]; int to[8080], nxt[8080]; long long cap[8080]; int q[2020], qf, qb; void init(int n, int s, int t) { V = n + 1; E = 0; src = s; tar = t; for (int i = 0; i <= V; i++) head[i] = -1; } void add(int u, int v, long long c) { to[E] = v; cap[E] = c; nxt[E] = head[u]; head[u] = E++; to[E] = u; cap[E] = 0; nxt[E] = head[v]; head[v] = E++; } bool bfs() { for (int i = 0; i <= V; i++) dis[i] = -1; qf = qb = 0; q[qb++] = src; dis[src] = 0; while (qf < qb && dis[tar] == -1) { int u = q[qf++]; for (int i = head[u]; i >= 0; i = nxt[i]) { int v = to[i]; if (dis[v] == -1 && cap[i] > 0) { dis[v] = dis[u] + 1; q[qb++] = v; } } } return dis[tar] >= 0; } long long dfs(int u, long long &bot) { int v; long long bot1, delta; if (u == tar) return bot; for (int &i = work[u]; i >= 0; i = nxt[i]) { int v = to[i]; if (dis[v] != dis[u] + 1 || cap[i] == 0) continue; bot1 = min(bot, cap[i]); if (delta = dfs(v, bot1)) { cap[i] -= delta; cap[i ^ 1] += delta; bot = bot1; return delta; } } return 0; } long long dinic() { long long ans = 0, delta, bot; while (bfs()) { memcpy(work, head, sizeof(int) * V); delta = 0x3f3f3f3f3f3f3f3fLL; while (delta = dfs(src, bot = 0x3f3f3f3f3f3f3f3fLL)) ans += delta; } return ans; } } dinic; int main() { int n, m; scanf( %d %d , &n, &m); int src = n + m + 1, tar = src + 1; dinic.init(tar, src, tar); for (int i = 1; i <= n; i++) { scanf( %d , a + i); dinic.add(src, i, a[i]); } long long ans = 0; for (int i = n + 1, u, v, w; i <= n + m; i++) { scanf( %d %d %d , &u, &v, &w); dinic.add(u, i, 0x3f3f3f3f3f3f3f3fLL); dinic.add(v, i, 0x3f3f3f3f3f3f3f3fLL); dinic.add(i, tar, w); ans += w; } printf( %I64d n , ans - dinic.dinic()); }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int dp[100005], x[105], s[105]; bool vis[100005]; int main() { int n, m, minv = INF; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d%d , &x[i], &s[i]); minv = min(minv, x[i]); for (int j = max(x[i] - s[i], 1); j <= min(x[i] + s[i], m); ++j) { vis[j] = true; } } memset(dp, INF, sizeof(dp)); dp[0] = 0; for (int i = 1; i <= m; ++i) { if (vis[i]) dp[i] = min(dp[i - 1], dp[i]); else { if (i >= minv) dp[i] = min(dp[i], dp[i - 1] + 1); for (int j = 0; j < n; ++j) { if (x[j] > i) { int tem = x[j] - s[j] - i; dp[min(m, x[j] + s[j] + tem)] = min(dp[min(x[j] + s[j] + tem, m)], dp[i - 1] + tem); } } } } printf( %d n , dp[m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; char s[N]; int main() { vector<int> v1, v2; scanf( %s , s); int len = strlen(s); for (int i = 0; i < len; i++) { if (s[i] == l ) { v1.push_back(i + 1); } else v2.push_back(i + 1); } for (int x : v2) printf( %d n , x); for (int i = (int)v1.size() - 1; i >= 0; i--) printf( %d n , v1[i]); return 0; }
|
// Streams the contents of memory to an LCD through a FIFO.
module Frame_buffer
#(parameter ADDRESS=0, LENGTH=0)
(
input wire clock,
input wire reset_n,
// Memory interface:
output reg [28:0] address,
output wire [7:0] burstcount,
input wire waitrequest,
input wire [63:0] readdata,
input wire readdatavalid,
output reg read,
// LCD interface:
input wire lcd_tick,
input wire lcd_next_frame,
output wire [7:0] lcd_red,
output wire [7:0] lcd_green,
output wire [7:0] lcd_blue,
input wire lcd_data_enable,
output reg lcd_data_enable_delayed,
// Front buffer handling.
input wire rast_front_buffer,
output reg fb_front_buffer,
// These get displayed on the LCD.
output wire [31:0] debug_value0,
output wire [31:0] debug_value1,
output wire [31:0] debug_value2
);
// Convert to 64-bit-based addresses.
/* verilator lint_off WIDTH */
localparam [28:0] FIRST_ADDRESS0_64BIT = ADDRESS/8;
localparam [28:0] LAST_ADDRESS0_64BIT = FIRST_ADDRESS0_64BIT + LENGTH/8 - 1;
localparam [28:0] FIRST_ADDRESS1_64BIT = ADDRESS/8 + LENGTH/8;
localparam [28:0] LAST_ADDRESS1_64BIT = FIRST_ADDRESS1_64BIT + LENGTH/8 - 1;
/* verilator lint_on WIDTH */
// State machine for transferring data from SDRAM to FIFO.
localparam M2F_STATE_START_FRAME = 4'h0;
localparam M2F_STATE_IDLE = 4'h1;
localparam M2F_STATE_READ = 4'h2;
localparam M2F_STATE_FLUSH_SDRAM = 4'h5;
localparam M2F_STATE_FLUSH_FIFO = 4'h6;
reg [3:0] m2f_state /* verilator public */;
// State machine for transferring data from FIFO to LCD.
localparam F2L_STATE_IDLE = 2'h0;
localparam F2L_STATE_WAIT = 2'h1;
localparam F2L_STATE_READ = 2'h2;
reg [1:0] f2l_state;
// Registers and assignments.
assign burstcount = 8'h01;
assign debug_value0 = {
3'b0, waitrequest,
3'b0, readdatavalid,
3'b0, read,
4'b0,
4'b0,
3'b0, fifo_write_wait,
3'b0, fifo_read_wait,
m2f_state
};
assign debug_value1 = { 6'b0, word_count_latched };
assign debug_value2 = { 6'b0, pixel_count_latched };
// FIFO from memory to scanned out pixels.
localparam FIFO_DEPTH = 256;
localparam FIFO_DEPTH_LOG2 = 8;
localparam BURST_LENGTH = 32;
reg fifo_sclr;
wire fifo_write_wait;
wire fifo_read_wait;
wire fifo_write /* verilator public */;
reg fifo_read /* verilator public */;
wire [63:0] fifo_read_data /* verilator public */;
wire [FIFO_DEPTH_LOG2 - 1:0] fifo_usedw /* verilator public */;
assign fifo_write = readdatavalid;
/* verilator lint_off PINMISSING */
scfifo #(.add_ram_output_register("OFF"),
.intended_device_family("CYCLONEV"),
.lpm_numwords(FIFO_DEPTH),
.lpm_showahead("OFF"),
.lpm_type("scfifo"),
.lpm_width(64),
.lpm_widthu(FIFO_DEPTH_LOG2),
.overflow_checking("ON"),
.underflow_checking("ON"),
.use_eab("ON")) frame_buffer_fifo(
.aclr(!reset_n),
.sclr(fifo_sclr),
.clock(clock),
.data(readdata),
.empty(fifo_read_wait),
.full(fifo_write_wait),
.usedw(fifo_usedw),
.q(fifo_read_data),
.rdreq(fifo_read),
.wrreq(fifo_write));
/* verilator lint_on PINMISSING */
// The next address to read after this one.
reg [28:0] next_address;
// For debugging.
reg [25:0] word_count;
reg [25:0] word_count_latched;
// Keep track of bursts.
reg [5:0] words_requested /* verilator public */;
reg [5:0] words_read /* verilator public */;
// State machine.
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
m2f_state <= M2F_STATE_START_FRAME;
address <= 29'h0;
next_address <= 29'h0;
read <= 1'b0;
fb_front_buffer <= 1'b0;
word_count <= 26'b0;
word_count_latched <= 26'b0;
words_requested <= 6'b0;
words_read <= 6'b0;
fifo_sclr <= 1'b0;
end else begin
case (m2f_state)
// Initial state.
M2F_STATE_START_FRAME: begin
fb_front_buffer <= rast_front_buffer;
// Start at beginning of front buffer frame memory.
if (rast_front_buffer) begin
next_address <= FIRST_ADDRESS1_64BIT;
end else begin
next_address <= FIRST_ADDRESS0_64BIT;
end
fifo_sclr <= 1'b0;
m2f_state <= M2F_STATE_IDLE;
end
// Wait for FIFO to have space (one burst and then some).
M2F_STATE_IDLE: begin
// If we should start the next frame, abort and
// flush the queue.
if (lcd_next_frame) begin
m2f_state <= M2F_STATE_FLUSH_SDRAM;
end else if ({ 1'b0, fifo_usedw } < FIFO_DEPTH - BURST_LENGTH - 8) begin
// Start burst reading.
words_requested <= 6'b0;
words_read <= 6'b0;
m2f_state <= M2F_STATE_READ;
end
end
// Initiate BURST_LENGTH reads and wait for them to complete.
M2F_STATE_READ: begin
// If we should start the next frame, abort and
// flush the queue.
if (lcd_next_frame) begin
read <= 1'b0;
m2f_state <= M2F_STATE_FLUSH_SDRAM;
end else if (read && waitrequest) begin
// If we initiated a read already, and the memory
// controller is busy, we have to wait.
end else begin
// Keep reading a whole burst length.
if (words_requested < BURST_LENGTH) begin
// Initiate a read.
read <= 1'b1;
address <= next_address;
words_requested <= words_requested + 1'b1;
// Compute the next address after this read.
if (next_address == LAST_ADDRESS0_64BIT ||
next_address == LAST_ADDRESS1_64BIT) begin
// We're done with this frame.
if (fb_front_buffer) begin
next_address <= FIRST_ADDRESS1_64BIT;
end else begin
next_address <= FIRST_ADDRESS0_64BIT;
end
end else begin
next_address <= next_address + 1'b1;
end
end else begin
// Not reading this clock cycle.
read <= 1'b0;
end
end
// If a word has returned from memory, keep track of it.
// We don't want to exit this state (and risk re-entering
// it) until all words have come back.
if (readdatavalid) begin
if (!lcd_next_frame && words_read == BURST_LENGTH - 1) begin
// Got all the words from this burst.
m2f_state <= M2F_STATE_IDLE;
end
words_read <= words_read + 1'b1;
end
end
// Flush the SDRAM queue.
M2F_STATE_FLUSH_SDRAM: begin
// We've perhaps queued up a bunch of reads,
// because reads can be pipelined. We need for
// all those reads to finish before we can
// flush the FIFO.
if (readdatavalid) begin
// We've read another word.
words_read <= words_read + 1'b1;
end
if (words_requested == words_read) begin
// Done flushing the SDRAM. Now we can flush the FIFO.
m2f_state <= M2F_STATE_FLUSH_FIFO;
end
end
// Flush the FIFO.
M2F_STATE_FLUSH_FIFO: begin
fifo_sclr <= 1'b1;
m2f_state <= M2F_STATE_START_FRAME;
end
default: begin
// Bug. Just restart.
m2f_state <= M2F_STATE_START_FRAME;
end
endcase
if (readdatavalid) begin
word_count <= word_count + 1'b1;
end
if (lcd_next_frame) begin
if (word_count >= 128) begin
word_count_latched <= word_count;
end
word_count <= 26'b0;
end
end
end
// Get pixel data out of the FIFO.
/* verilator lint_off UNUSED */
reg [63:0] pixel_data;
/* verilator lint_on UNUSED */
reg need_shifting;
assign lcd_red = pixel_data[7:0];
assign lcd_green = pixel_data[15:8];
assign lcd_blue = pixel_data[23:16];
reg [25:0] pixel_count;
reg [25:0] pixel_count_latched;
// For delaying the data enable signal.
reg lcd_data_enable_d1;
reg lcd_data_enable_d2;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
f2l_state <= F2L_STATE_IDLE;
fifo_read <= 1'b0;
need_shifting <= 1'b0;
pixel_count <= 26'b0;
pixel_count_latched <= 26'b0;
lcd_data_enable_d1 <= 1'b0;
lcd_data_enable_d2 <= 1'b0;
end else begin
// If we're clearing the FIFO, clear everything else too.
if (fifo_sclr) begin
f2l_state <= F2L_STATE_IDLE;
fifo_read <= 1'b0;
need_shifting <= 1'b0;
// Debug output.
if (pixel_count >= 128) begin
pixel_count_latched <= pixel_count;
end
pixel_count <= 26'b0;
end else begin
// Delay data enable by three clocks, since that's how long it
// takes for us to realize we need to pull from the FIFO and wait
// for the FIFO data.
lcd_data_enable_d1 <= lcd_data_enable;
lcd_data_enable_d2 <= lcd_data_enable_d1;
lcd_data_enable_delayed <= lcd_data_enable_d2;
case (f2l_state)
F2L_STATE_IDLE: begin
// See if we should pre-fetch the head of the FIFO.
if (!lcd_tick && !need_shifting && lcd_data_enable) begin
// Start a FIFO read. Data will be available in
// two clocks.
fifo_read <= 1'b1;
f2l_state <= F2L_STATE_WAIT;
end else begin
// See if we need to shift the pixel from
// the high 32 bits to the low ones.
if (lcd_tick && lcd_data_enable && need_shifting) begin
// Next pixel.
pixel_data[31:0] <= pixel_data[63:32];
need_shifting <= 1'b0;
end
end
end
F2L_STATE_WAIT: begin
// We can check this one clock after we request a read.
if (fifo_read_wait) begin
// We missed it. Nothing we can do here will
// fix it, so draw some magenta so that it's
// obvious something went wrong.
pixel_data <= 64'h00ff00ff_00ff00ff;
f2l_state <= F2L_STATE_IDLE;
end else begin
// Must wait one more clock to get the data.
f2l_state <= F2L_STATE_READ;
end
// Either way stop reading.
fifo_read <= 1'b0;
end
F2L_STATE_READ: begin
// Grab the data from the FIFO.
pixel_data <= fifo_read_data;
// We got a 64-bit number, but our pixels are
// 32 bits. Record that fact that we still need
// to shift the high 32 bits into the lower ones.
need_shifting <= 1'b1;
// Either way go back to waiting.
f2l_state <= F2L_STATE_IDLE;
end
default: begin
// Bug.
f2l_state <= F2L_STATE_IDLE;
end
endcase
// Debug output.
if (fifo_read) begin
pixel_count <= pixel_count + 1'b1;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double R, r, k; int tt; scanf( %d , &tt); while (tt--) { scanf( %lf%lf%lf , &R, &r, &k); double a = (R + r) / (4 * R * r), b = k * (R - r) / (2 * R * r); double t = (R - r) / (4 * R * r); double s = t / (a * a + b * b - t * t); printf( %.9lf n , s); } return 0; }
|
#include <bits/stdc++.h> const int maxn = 1e6 + 9, mod = 998244353, inf = 0x3f3f3f3f; int Read() { int x(0), f(1); char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3ll) + (x << 1ll) + c - 0 ; c = getchar(); } return x * f; } void Chkmin(int &x, int y) { if (y < x) x = y; } void Chkmax(int &x, int y) { if (y > x) x = y; } int add(int x, int y) { return x += y, x >= mod ? x - mod : x; } int dec(int x, int y) { return x -= y, x < 0 ? x + mod : x; } int mul(int x, int y) { return 1ll * x * y % mod; } int Pow(int base, int b) { int ret(1); while (b) { if (b & 1) ret = mul(ret, base); base = mul(base, base); b >>= 1; } return ret; } int Gcd(int a, int b) { return b ? Gcd(b, a % b) : a; } struct point { int x, y; } a[maxn]; int n, K; double d[maxn]; std::multiset<double> Set; std::map<std::pair<int, int>, std::vector<int> > mp; std::map<std::pair<int, int>, std::vector<int> >::iterator it1; double Dist(double x, double y) { return std::sqrt(x * x + y * y); } bool cmp(int x, int y) { return d[x] > d[y]; } int main() { n = Read(); K = Read(); for (int i = 1; i <= n; ++i) { int x(Read()), y(Read()); if (!x && !y) continue; a[i] = (point){x, y}; d[i] = Dist(x, y); int z(Gcd(std::abs(x), std::abs(y))); int xx(x / z), yy(y / z); mp[std::pair<int, int>(xx, yy)]; it1 = mp.find(std::pair<int, int>(xx, yy)); assert(it1 != mp.end()); it1->second.push_back(i); } for (it1 = mp.begin(); it1 != mp.end(); ++it1) { std::vector<int> A(it1->second); std::sort(A.begin(), A.end(), cmp); int m(A.size()); int ret(0); double pre(0); int j(1); for (int i = 1; i <= m; ++i) if (K - 2 * i + 1 >= 0) { int x(A[i - 1]); Set.insert(d[x] * (1.0 * (K - 2 * i + 1))); j = i + 1; } else { int x(A[m - 1 - (i - j)]); double tmp(-2.0 * pre); tmp += d[x] * (1.0 * (K - 2 * j + 1)); Set.insert(tmp); pre += d[x]; } } int flag(0); double ret(0); while (K--) { if (!Set.size()) { continue; } if (*Set.rbegin() <= 0 && !flag) { flag = 1; continue; } ret += *Set.rbegin(); Set.erase(Set.find(*Set.rbegin())); } printf( %.10lf n , ret); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_8_b2s_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data as it is ready and it has to be
// accepted. The read data FIFO in the axi_protocol_converter_v2_1_8_b2s_r_channel module will buffer
// the data before being sent to AXI. The address channel module will
// send the transaction information for every command that is sent to the
// MC. The transaction information will be buffered in a transaction FIFO.
// Based on the transaction FIFO information data will be ignored in
// BL8 mode and the last signal to the AXI will be asserted.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] s_rid ,
output wire [C_DATA_WIDTH-1:0] s_rdata ,
output wire [1:0] s_rresp ,
output wire s_rlast ,
output wire s_rvalid ,
input wire s_rready ,
input wire [C_DATA_WIDTH-1:0] m_rdata ,
input wire [1:0] m_rresp ,
input wire m_rvalid ,
output wire m_rready ,
// Connections to/from axi_protocol_converter_v2_1_8_b2s_ar_channel module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_8_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_8_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 00:48:48
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Referenced from fpga4fun
//
//////////////////////////////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = ;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = ;
parameter Oversampling = 16;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
////////////////////////////////////////////////////////
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000010; struct node { int v, id; } MAX[MAXN], MMAX[MAXN]; int n, f[MAXN]; int main() { scanf( %d , &n); n++; MAX[1].v = MMAX[1].v = 0; MAX[1].id = MMAX[1].id = 1; for (register int i = 2; i <= n; i++) { scanf( %d , &f[i]); MAX[i].v = 0; MMAX[i].v = 0; MAX[i].id = MMAX[i].id = i; int now = i; while (now) { if (MAX[f[now]].id == now) { if (max(MAX[now].v, MMAX[now].v + 1) > MAX[f[now]].v) { MAX[f[now]].v = max(MAX[now].v, MMAX[now].v + 1); } else { break; } } else if (MMAX[f[now]].id == now) { if (max(MAX[now].v, MMAX[now].v + 1) > MAX[f[now]].v) { swap(MAX[f[now]], MMAX[f[now]]); MAX[f[now]].v = max(MAX[now].v, MMAX[now].v + 1); } else if (max(MAX[now].v, MMAX[now].v + 1) > MMAX[f[now]].v) { MMAX[f[now]].v = max(MAX[now].v, MMAX[now].v + 1); } else { break; } } else { if (max(MAX[now].v, MMAX[now].v + 1) > MAX[f[now]].v) { swap(MAX[f[now]], MMAX[f[now]]); MAX[f[now]].v = max(MAX[now].v, MMAX[now].v + 1); MAX[f[now]].id = now; } else if (max(MAX[now].v, MMAX[now].v + 1) > MMAX[f[now]].v) { MMAX[f[now]].v = max(MAX[now].v, MMAX[now].v + 1); MMAX[f[now]].id = now; } else { break; } } now = f[now]; } printf( %d , MAX[1].v); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[100] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5, 1, 15, 2, 13, 2, 2, 1, 13, 1, 2, 4, 267, 1, 4, 1, 5, 1, 4, 1, 50, 1, 2, 3, 4, 1, 6, 1, 52, 15, 2, 1, 15, 1, 2, 1, 12, 1, 10, 1, 4, 2}; long long b; cin >> b; cout << a[b] << endl; }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for phase_accumulator
*/
module test_phase_accumulator;
// Parameters
parameter WIDTH = 32;
parameter INITIAL_PHASE = 0;
parameter INITIAL_PHASE_STEP = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_phase_tdata = 0;
reg input_phase_tvalid = 0;
reg [WIDTH-1:0] input_phase_step_tdata = 0;
reg input_phase_step_tvalid = 0;
reg output_phase_tready = 0;
// Outputs
wire input_phase_tready;
wire input_phase_step_tready;
wire [WIDTH-1:0] output_phase_tdata;
wire output_phase_tvalid;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_phase_tdata,
input_phase_tvalid,
input_phase_step_tdata,
input_phase_step_tvalid,
output_phase_tready);
$to_myhdl(input_phase_tready,
input_phase_step_tready,
output_phase_tdata,
output_phase_tvalid);
// dump file
$dumpfile("test_phase_accumulator.lxt");
$dumpvars(0, test_phase_accumulator);
end
phase_accumulator #(
.WIDTH(WIDTH),
.INITIAL_PHASE(INITIAL_PHASE),
.INITIAL_PHASE_STEP(INITIAL_PHASE_STEP)
)
UUT (
.clk(clk),
.rst(rst),
.input_phase_tdata(input_phase_tdata),
.input_phase_tvalid(input_phase_tvalid),
.input_phase_tready(input_phase_tready),
.input_phase_step_tdata(input_phase_step_tdata),
.input_phase_step_tvalid(input_phase_step_tvalid),
.input_phase_step_tready(input_phase_step_tready),
.output_phase_tdata(output_phase_tdata),
.output_phase_tvalid(output_phase_tvalid),
.output_phase_tready(output_phase_tready)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MM_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_MM_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_MM
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 2)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_MM = {digit1,digit0};
endmodule
|
/*
* DUT VGA LCD FML
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
//`timescale 1ns/10ps
`timescale 1ns/1ps
module tb_vga_lcd_fml;
// Registers and nets
reg clk_100;
reg rst;
reg shift_reg1; // if set: 320x200
reg graphics_alpha; // if not set: 640x400 text mode
// VGA LCD FML master interface
wire [20-1:0] fml_adr;
wire fml_stb;
reg fml_we;
reg fml_ack;
wire [1:0] fml_sel;
wire [15:0] fml_do;
reg [15:0] fml_di;
// VGA LCD Direct Cache Bus
wire dcb_stb;
wire [20-1:0] dcb_adr;
reg [15:0] dcb_dat;
reg dcb_hit;
// attribute_ctrl
reg [3:0] pal_addr;
reg pal_we;
wire [7:0] pal_read;
reg [7:0] pal_write;
// dac_regs
reg dac_we;
reg [1:0] dac_read_data_cycle;
reg [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
reg [1:0] dac_write_data_cycle;
reg [7:0] dac_write_data_register;
reg [3:0] dac_write_data;
// VGA pad signals
wire [3:0] vga_red_o;
wire [3:0] vga_green_o;
wire [3:0] vga_blue_o;
wire horiz_sync;
wire vert_sync;
// Base address of video memory
reg [15:0] start_addr;
// CRTC
reg [5:0] cur_start;
reg [5:0] cur_end;
reg [4:0] vcursor;
reg [6:0] hcursor;
reg [6:0] horiz_total;
reg [6:0] end_horiz;
reg [6:0] st_hor_retr;
reg [4:0] end_hor_retr;
reg [9:0] vert_total;
reg [9:0] end_vert;
reg [9:0] st_ver_retr;
reg [3:0] end_ver_retr;
reg x_dotclockdiv2;
// retrace signals
wire v_retrace;
wire vh_retrace;
wire vga_clk;
/* Process FML requests */
reg [2:0] fml_wcount;
reg [2:0] fml_rcount;
reg [3:0] fml_pipe;
initial begin
fml_ack = 1'b0;
fml_wcount = 0;
fml_rcount = 0;
end
always @(posedge clk_100)
fml_pipe <= rst ? 4'b0 : { fml_pipe[2:0], fml_stb };
always @(posedge clk_100) begin
if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
fml_ack <= 1'b1;
if(fml_we) begin
//$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
fml_wcount <= 7;
end else begin
fml_di = 16'hbeef;
//$display("%t FML R addr %x data %x", $time, fml_adr, fml_di);
fml_rcount <= 7;
end
end else
fml_ack <= 1'b0;
if(fml_wcount != 0) begin
//#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
fml_wcount <= fml_wcount - 1;
end
if(fml_rcount != 0) begin
//fml_di = #1 {13'h1eba, fml_rcount};
fml_di = {13'h1eba, fml_rcount};
//$display("%t FML R continuing %x / %d", $time, fml_di, fml_rcount);
fml_rcount <= fml_rcount - 1;
end
end
/* Process DCB requests */
//reg [15:0] dcb_dat;
reg [2:0] dcb_rcount;
reg [3:0] dcb_pipe;
initial begin
dcb_hit = 1'b0;
dcb_rcount = 0;
end
always @(posedge clk_100)
dcb_pipe <= rst ? 4'b0 : { dcb_pipe[2:0], dcb_stb };
always @(posedge clk_100) begin
//if (dcb_stb)
//$display("%t DCB R addr %x", $time, dcb_adr);
if (dcb_stb & (dcb_rcount == 0))
begin
dcb_hit <= 1'b1;
//dcb_hit <= 1'b0;
dcb_dat = 16'hbeef;
//$display("%t DCB R addr %x data %x", $time, dcb_adr, dcb_dat);
dcb_rcount <= 7;
end else
dcb_hit <= 1'b0;
if(dcb_stb & (dcb_rcount != 0)) begin
//dcb_dat = #1 {13'h1eba, dcb_rcount};
dcb_dat = {13'h1eba, dcb_rcount};
//$display("%t DCB R continuing %x / %d", $time, dcb_dat, dcb_rcount);
dcb_rcount <= dcb_rcount - 1;
end
end
// Module instantiations
vga_lcd_fml #(
.fml_depth (20) // 8086 can only address 1 MB
) dut (
.clk(clk_100), // 100 Mhz clock
.rst(rst),
.shift_reg1(shift_reg1), // if set: 320x200
.graphics_alpha(graphics_alpha), // if not set: 640x400 text mode
// VGA LCD FML master interface
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_do(fml_do),
.fml_di(fml_di),
// VGA LCD Direct Cache Bus
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
// attribute_ctrl
.pal_addr(pal_addr),
.pal_we(pal_we),
.pal_read(pal_read),
.pal_write(pal_write),
// dac_regs
.dac_we(dac_we),
.dac_read_data_cycle(dac_read_data_cycle),
.dac_read_data_register(dac_read_data_register),
.dac_read_data(dac_read_data),
.dac_write_data_cycle(dac_write_data_cycle),
.dac_write_data_register(dac_write_data_register),
.dac_write_data(dac_write_data),
// VGA pad signals
.vga_red_o(vga_red_o),
.vga_green_o(vga_green_o),
.vga_blue_o(vga_blue_o),
.horiz_sync(horiz_sync),
.vert_sync(vert_sync),
// Base address of video memory
.start_addr(start_addr),
// CRTC
.cur_start(cur_start),
.cur_end(cur_end),
.vcursor(vcursor),
.hcursor(hcursor),
.horiz_total(horiz_total),
.end_horiz(end_horiz),
.st_hor_retr(st_hor_retr),
.end_hor_retr(end_hor_retr),
.vert_total(vert_total),
.end_vert(end_vert),
.st_ver_retr(st_ver_retr),
.end_ver_retr(end_ver_retr),
.x_dotclockdiv2(x_dotclockdiv2),
// retrace signals
.v_retrace(v_retrace),
.vh_retrace(vh_retrace),
.vga_clk(vga_clk)
);
// Continuous assignments
// Behaviour
// Clock generation
//always #10 clk_100 <= !clk_100;
initial clk_100 = 1'b0;
always #5 clk_100 = ~clk_100;
task waitclock;
begin
@(posedge clk_100);
#1;
end
endtask
always begin
// Initialize to a known state
rst = 1'b1; // reset is active
waitclock;
rst = 1'b0;
waitclock;
/*
// Set Text Mode
shift_reg1 = 1'b0; // if set: 320x200
graphics_alpha = 1'b0; // if not set: 640x400 text mode
*/
// Set Linear Mode
shift_reg1 = 1'b1; // if set: 320x200
graphics_alpha = 1'b1; // if not set: 640x400 text mode
// Base address of video memory
start_addr = 16'h1000;
// CRTC configuration signals
cur_start = 5'd0; // reg [5:0] cur_start,
cur_end = 5'd0; // reg [5:0] cur_end,
vcursor = 4'd0; // reg [4:0] vcursor,
hcursor = 6'd0; // reg [6:0] hcursor,
horiz_total = 7'd79; // reg [6:0] horiz_total,
//horiz_total = 7'd639; // reg [6:0] horiz_total,
end_horiz = 7'd750; // reg [6:0] end_horiz,
st_hor_retr = 7'd760; // reg [6:0] st_hor_retr,
st_hor_retr = 7'd656; // reg [6:0] st_hor_retr,
//end_hor_retr = 5'd10; // reg [4:0] end_hor_retr,
end_hor_retr = 5'd750; // reg [4:0] end_hor_retr,
end_hor_retr = 5'd752; // reg [4:0] end_hor_retr,
vert_total = 10'd399; // reg [9:0] vert_total,
end_vert = 10'd550; // reg [9:0] end_vert,
st_ver_retr = 10'd560; // reg [9:0] st_ver_retr,
//end_ver_retr = 4'd10; // reg [3:0] end_ver_retr,
end_ver_retr = 4'd750; // reg [3:0] end_ver_retr,
x_dotclockdiv2 = 1'b0; // reg x_dotclockdiv2
repeat (20000) begin
waitclock;
end
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, e; cin >> n >> d >> e; long long a = n, b = n, i; e = 5 * e; for (i = 0; e * i <= n; i++) { a = min(a, (n - (e * i)) % d); } for (i = 0; d * i <= n; i++) { b = min(b, (n - (d * i)) % e); } cout << min(a, b); }
|
#include <bits/stdc++.h> using namespace std; long mod(long int a) { return (a > 0 ? a : (-a)); } long min(long int a, long int b) { return (a) > (b) ? (b) : (a); } long max(long int a, long int b) { return (a) < (b) ? (b) : (a); } bool sortbyff(const pair<int, int> &a, const pair<int, int> &b) { return (a.first < b.first); } long num[1000001], t[5001][2]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long n, m, k, i, j, l, r, a = -1, b = -1, c, d, s, u, w, x = 0, y, z, sum = 0, p = 0, ans = 0, M = 10000000; cin >> n; cout << n << ; for (i = 1; i < n; i++) { cout << i << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[2000010], t[2000010]; int main(void) { int n; scanf( %d , &n); scanf( %s , s); scanf( %s , t); int count_s, count_t, count_com; count_s = count_t = count_com = 0; for (int i = 0; i < 2 * n; ++i) { if (s[i] == 1 && t[i] == 1 ) { ++count_com; } if (s[i] == 1 && t[i] != 1 ) { ++count_s; } if (s[i] != 1 && t[i] == 1 ) { ++count_t; } } if (count_com % 2 == 0) { if (count_s > count_t) { puts( First ); } else if (count_s >= count_t - 1) { puts( Draw ); } else { puts( Second ); } } else { if (count_s >= count_t) { puts( First ); } else if (count_s >= count_t - 2) { puts( Draw ); } else { puts( Second ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX4_PP_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { vector<pair<int, int> > v; int n, i, c = 1, ans = 0; vector<pair<int, int> >::iterator it; cin >> n; for (i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back(make_pair(y, x)); } sort(v.begin(), v.end()); for (i = n - 1; i >= 0; i--) { if (c == 0) { break; } c = c - 1 + v[i].first; ans = ans + v[i].second; } cout << ans << endl; }
|
`timescale 1ns/10ps
module RegBankP2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out_0;
wire [7:0] out_1;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankP2_LD0,8'hBA};
inst_en = 1;
#4 inst = {`RegBankP2_LD1,8'hFE};
inst_en = 1;
#4 inst = {`RegBankP2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankP2_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankP2_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankP2_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankP2_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankP2_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankP2
rbp2 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out_0(out_0),
.out_1(out_1));
endmodule // RegBankP2Sim
|
#include <bits/stdc++.h> int main() { int a, b, c, d, p1, p2, p3, p4; scanf( %d %d %d %d , &a, &b, &c, &d); p1 = ((3 * a / 10)); p2 = (a - (a * c / 250)); if (p1 > p2) { p1 = p1; } else if (p2 > p1) { p1 = p2; } else if (p2 == p1) { p1 = p1; } p3 = ((3 * b / 10)); p4 = (b - (b * d / 250)); if (p3 > p4) { p3 = p3; } else if (p4 > p3) { p3 = p4; } else if (p3 == p4) { p3 = p3; } if (p1 > p3) { printf( Misha n ); } else if (p3 > p1) { printf( Vasya n ); } else if (p1 == p3) { printf( Tie n ); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int maxn = 100001, inf = 2147483647; const long long mod = 1 ? 998244353 : 1000000007, linf = 9223372036854775807; const double pi = acos(-1); inline long long mi(long long a, long long b, long long mm = mod) { a %= mm; long long u = 1; while (b) { if (b & 1) u = u * a % mm; a = a * a % mm, b >>= 1; } return u; } inline long long gcd(long long a, long long b) { long long c = a % b; while (c) a = b, b = c, c = a % b; return b; } inline void mem(int* a, int p = 0, int len = maxn) { for (int i = 0; i < len; i++) a[i] = p; } struct p { } e; int t, n, a[maxn], b[maxn], x; signed main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> t; while (t--) { cin >> n; map<int, int> ma; x = 0; for (int i = 0; i < n; i++) cin >> b[i], ma[b[i]]++, x = max(x, ma[b[i]]); if (x > 1) cout << YES n ; else cout << NO n ; } }
|
#include <bits/stdc++.h> using namespace std; double distance(double x1, double y1, double x2, double y2) { return sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); } int main() { double ax, ay, bx, by, tx, ty; scanf( %lf%lf%lf%lf%lf%lf , &ax, &ay, &bx, &by, &tx, &ty); int n; scanf( %d , &n); double cdist[n], D = 0; pair<double, double> p[n]; for (int i = 0; i < n; ++i) { scanf( %lf%lf , &p[i].first, &p[i].second); cdist[i] = distance(tx, ty, p[i].first, p[i].second); D += 2 * cdist[i]; } set<pair<double, int> > A, B; double distA[n], distB[n]; for (int i = 0; i < n; ++i) { double x = -cdist[i] + distance(ax, ay, p[i].first, p[i].second); distA[i] = x; A.insert({x, i}); x = -cdist[i] + distance(bx, by, p[i].first, p[i].second); distB[i] = x; B.insert({x, i}); } double temp1 = D + A.begin()->first; double temp2 = D + B.begin()->first; double temp3 = D + A.begin()->first; int idx = A.begin()->second; B.erase({distB[idx], idx}); if (not B.empty()) temp3 += B.begin()->first; B.insert({distB[idx], idx}); double temp4 = D + B.begin()->first; idx = B.begin()->second; A.erase({distA[idx], idx}); if (not A.empty()) temp4 += A.begin()->first; double ans = min(min(temp1, temp2), min(temp3, temp4)); printf( %lf n , ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
reg GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
reg GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
module \$_DFF_N_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 7) begin
wire T0, T1;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
end else
if (WIDTH == 8) begin
wire T0, T1, T2, T3, T4, T5;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2016 01:33:37 PM
// Design Name:
// Module Name: fslcd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsmotor #
(
parameter integer C_MICROSTEP_WIDTH = 3,
parameter integer C_INVERT_DIR = 0
) (
output wire s0_zpd,
input wire s0_xen,
input wire s0_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s0_ms,
input wire s0_drive,
input wire s0_dir,
output wire s1_zpd,
input wire s1_xen,
input wire s1_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s1_ms,
input wire s1_drive,
input wire s1_dir,
output wire s2_zpd,
input wire s2_xen,
input wire s2_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s2_ms,
input wire s2_drive,
input wire s2_dir,
output wire s3_zpd,
input wire s3_xen,
input wire s3_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s3_ms,
input wire s3_drive,
input wire s3_dir,
output wire s4_zpd,
input wire s4_xen,
input wire s4_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s4_ms,
input wire s4_drive,
input wire s4_dir,
output wire s5_zpd,
input wire s5_xen,
input wire s5_xrst,
input wire [C_MICROSTEP_WIDTH-1:0] s5_ms,
input wire s5_drive,
input wire s5_dir,
output wire [C_MICROSTEP_WIDTH-1:0] pm_ms,
input wire pm0_zpd,
output wire pm0_xen,
output wire pm0_xrst,
output wire pm0_drive,
output wire pm0_dir,
input wire pm1_zpd,
output wire pm1_xen,
output wire pm1_xrst,
output wire pm1_drive,
output wire pm1_dir,
output wire [C_MICROSTEP_WIDTH-1:0] am_ms,
output wire am0_xen,
output wire am0_xrst,
output wire am0_drive,
output wire am0_dir,
output wire am1_xen,
output wire am1_xrst,
output wire am1_drive,
output wire am1_dir,
output wire [C_MICROSTEP_WIDTH-1:0] rm_ms,
input wire rm0_zpd,
output wire rm0_xen,
output wire rm0_xrst,
output wire rm0_drive,
output wire rm0_dir,
input wire rm1_zpd,
output wire rm1_xen,
output wire rm1_xrst,
output wire rm1_drive,
output wire rm1_dir
);
assign s0_zpd = pm0_zpd;
assign s1_zpd = pm1_zpd;
assign s4_zpd = rm0_zpd;
assign s5_zpd = rm1_zpd;
assign pm_ms = s0_ms;
assign pm0_xen = s0_xen;
assign pm0_xrst = s0_xrst;
assign pm0_drive = s0_drive;
if (C_INVERT_DIR == 0) begin
assign pm0_dir = s0_dir;
end
else begin
assign pm0_dir = ~s0_dir;
end
assign pm1_xen = s1_xen;
assign pm1_xrst = s1_xrst;
assign pm1_drive = s1_drive;
if (C_INVERT_DIR == 0) begin
assign pm1_dir = s1_dir;
end
else begin
assign pm1_dir = ~s1_dir;
end
assign am_ms = s2_ms;
assign am0_xen = s2_xen;
assign am0_xrst = s2_xrst;
assign am0_drive = s2_drive;
if (C_INVERT_DIR == 0) begin
assign am0_dir = s2_dir;
end
else begin
assign am0_dir = ~s2_dir;
end
assign am1_xen = s3_xen;
assign am1_xrst = s3_xrst;
assign am1_drive = s3_drive;
if (C_INVERT_DIR == 0) begin
assign am1_dir = s3_dir;
end
else begin
assign am1_dir = ~s3_dir;
end
assign rm_ms = s4_ms;
assign rm0_xen = s4_xen;
assign rm0_xrst = s4_xrst;
assign rm0_drive = s4_drive;
if (C_INVERT_DIR == 0) begin
assign rm0_dir = s4_dir;
end
else begin
assign rm0_dir = ~s4_dir;
end
assign rm1_xen = s5_xen;
assign rm1_xrst = s5_xrst;
assign rm1_drive = s5_drive;
if (C_INVERT_DIR == 0) begin
assign rm1_dir = s5_dir;
end
else begin
assign rm1_dir = ~s5_dir;
end
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input sgmii_refclk_p,
input sgmii_refclk_n,
input [3:0] sgmii_rxn,
input [3:0] sgmii_rxp,
output [3:0] sgmii_txn,
output [3:0] sgmii_txp,
output mdio_mdc,
inout mdio_mdio,
output [1:0] pl_led,
output [1:0] pl_pmod,
input pl_btn
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire bd_aresetn ;
//wire sgmii_refclk_se;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_3[23];
assign pl_pmod[1] = bd_aresetn;
// sgmii ref clk
/*
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFDS_i_sgmii_refclk (
.O (sgmii_refclk_se), // Buffer output
.I (sgmii_refclk_p), // Diff_p buffer input (connect directly to top-level port)
.IB (sgmii_refclk_n) // Diff_n buffer input (connect directly to top-level port)
);
*/
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.mdio_mdc (mdio_mdc ),
.mdio_mdio_io (mdio_mdio ),
.ref_clk_125_n (sgmii_refclk_n ),
.ref_clk_125_p (sgmii_refclk_p ),
.sgmii_0_rxn (sgmii_rxn[0] ),
.sgmii_0_rxp (sgmii_rxp[0] ),
.sgmii_0_txn (sgmii_txn[0] ),
.sgmii_0_txp (sgmii_txp[0] ),
.sgmii_1_rxn (sgmii_rxn[1] ),
.sgmii_1_rxp (sgmii_rxp[1] ),
.sgmii_1_txn (sgmii_txn[1] ),
.sgmii_1_txp (sgmii_txp[1] ),
.sgmii_2_rxn (sgmii_rxn[2] ),
.sgmii_2_rxp (sgmii_rxp[2] ),
.sgmii_2_txn (sgmii_txn[2] ),
.sgmii_2_txp (sgmii_txp[2] ),
.sgmii_3_rxn (sgmii_rxn[3] ),
.sgmii_3_rxp (sgmii_rxp[3] ),
.sgmii_3_txn (sgmii_txn[3] ),
.sgmii_3_txp (sgmii_txp[3] ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.bd_aresetn ( bd_aresetn ),
.ext_rst ( pl_btn )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const int N = 510000, M = N << 1; int n, hd[N], to[M], nxt[M], noedg = 1, size[N]; long long buc[N], f[N], ans = inf; vector<int> app[N]; template <class T> inline void read(T &x) { x = 0; char ch = getchar(), w = 0; while (!isdigit(ch)) w = (ch == - ), ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x = w ? -x : x; return; } inline void addEdg(int x, int y) { nxt[++noedg] = hd[x], hd[x] = noedg, to[noedg] = y; nxt[++noedg] = hd[y], hd[y] = noedg, to[noedg] = x; return; } inline long long sq(long long x) { return x * x; } void dfs(int now, int fa) { size[now] = 1, f[now] = inf; for (register int i = hd[now], v; i; i = nxt[i]) { if ((v = to[i]) == fa) continue; dfs(v, now), size[now] += size[v]; } buc[0] = 0, app[now].push_back(0); for (register int i = hd[now], v; i; i = nxt[i]) { if ((v = to[i]) == fa) continue; for (register int j = 0, sz = app[now].size(); j < sz; ++j) ans = min(ans, buc[app[now][j]] + f[v] + sq(n - app[now][j] - size[v])); if (buc[size[v]] == inf) app[now].push_back(size[v]); buc[size[v]] = min(buc[size[v]], f[v]); f[now] = min(f[now], f[v] + sq(size[now] - size[v])); } for (register int i = 0, sz = app[now].size(); i < sz; ++i) buc[app[now][i]] = inf; if (f[now] == inf) f[now] = 1; return; } int main() { int x, y; read(n); for (register int i = 1; i < n; ++i) read(x), read(y), addEdg(x, y), buc[i] = inf; dfs(1, 0); cout << ((long long)n * (2 * n - 1) - ans) / 2; return 0; int qwq; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
`define MSU
`ifndef MSU
assign reg_data_out = 0;
assign status_out = 0;
assign volume_out = 0;
assign volume_latch_out = 0;
assign addr_out = 0;
assign track_out = 0;
assign DBG_msu_reg_oe_rising = 0;
assign DBG_msu_reg_oe_falling = 0;
assign DBG_msu_reg_we_rising = 0;
assign DBG_msu_address = 0;
assign DBG_msu_address_ext_write_rising = 0;
`else
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_PP_BLACKBOX_V
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_mac_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.ptp_ts(rx_ptp_ts),
.rx_start_packet(rx_start_packet),
.rx_error_count(rx_error_count),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_mac_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_mac_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
`resetall
|
#include <iostream> #include <vector> #include <algorithm> #include <string> #include <map> #include <unordered_set> #include <unordered_map> #include <cmath> #include <random> #include <chrono> #include <set> #include <queue> #include <stack> #include <deque> #include <cstring> const long long big = 998244353; using namespace std; long long power(long long a, long long n) { if (n == 0) return 1; if (n % 2 == 1) return (power(a, n - 1) * a) % big; else { long long b = power(a, n / 2); return (b * b) % big; } } int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int t2[1000000]; void build_min(int a[], int v, int tl, int tr) { if (tl >= tr) t2[v] = a[tl]; else { int tm = (tl + tr) / 2; build_min(a, v * 2, tl, tm); build_min(a, v * 2 + 1, tm + 1, tr); t2[v] = min(t2[v * 2], t2[v * 2 + 1]); } } int sum_min (int v, int tl, int tr, int l, int r) { if (l > r) return 1000000; if (l == tl && r == tr) return t2[v]; int tm = (tl + tr) / 2; return min(sum_min (v*2, tl, tm, l, min(r,tm)) , sum_min (v*2+1, tm+1, tr, max(l,tm+1), r)); } int t[1000000]; void build_max(int a[], int v, int tl, int tr) { if (tl >= tr) t[v] = a[tl]; else { int tm = (tl + tr) / 2; build_max(a, v * 2, tl, tm); build_max(a, v * 2 + 1, tm + 1, tr); t[v] = max(t[v * 2], t[v * 2 + 1]); } } void update(int v, int tl, int tr, int l, int r, int add) { if (l > r) return; if (l == tl && tr == r) t[v] += add; else { int tm = (tl + tr) / 2; update(v * 2, tl, tm, l, min(r, tm), add); update(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, add); } } int get(int v, int tl, int tr, int pos) { if (tl == tr) return t[v]; int tm = (tl + tr) / 2; if (pos <= tm) return t[v] + get(v * 2, tl, tm, pos); else return t[v] + get(v * 2 + 1, tm + 1, tr, pos); } int sum_max (int v, int tl, int tr, int l, int r) { if (l > r) return -1000000; if (l == tl && r == tr) return t[v]; int tm = (tl + tr) / 2; return max(sum_max (v*2, tl, tm, l, min(r,tm)) , sum_max (v*2+1, tm+1, tr, max(l,tm+1), r)); } class Cmp { public: bool operator()(vector<long long>& a, vector<long long>& b) { return a.size() > b.size(); } }; void solve() { long long n, k; cin >> n >> k; vector<long long> sa(n); for (int i = 0; i < n; ++i) { cin >> sa[i]; } vector<long long> tmp(n); for (int i = 0; i < n; ++i) { tmp[sa[i]] = i; } long long cur = 0; vector<long long> s(n); s[sa[0]] = 0; for (int i = 1; i < n; ++i) { long long j = sa[i - 1]; long long l = sa[i]; if (l == n - 1 || (j < n - 1 && tmp[j + 1] > tmp[l + 1])) cur++; s[sa[i]] = cur; } long long dif = k; for (long long i: s) { // cout << i << ; if (k - i - 1 < dif) { dif = k - i - 1; } } if (dif < 0) { cout << 0; return; } else if (dif == 0) { cout << 1; return; } else { long long ans = 1; for (int i = 1; i <= dif; ++i) { ans *= (n + i); ans %= big; ans *= power(i, big - 2); ans %= big; } cout << ans; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; // cin >> t; //cout.precision(20); while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; double R, r; struct Punct { double x, y; }; Punct A, B; inline double Dist(Punct A, Punct B) { return sqrt((A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y)); } int main() { double d; cin >> A.x >> A.y >> R; cin >> B.x >> B.y >> r; d = Dist(A, B); if (R >= r) { if (d + r <= R) { d = R - d - r; d /= 2.0; } else { if (d <= R + r) d = 0.0; else { d = d - R - r; d /= 2.0; } } } else { if (d + R <= r) { d = r - d - R; d /= 2.0; } else { if (d <= R + r) d = 0.0; else { d = d - R - r; d /= 2.0; } } } printf( %.6lf n , d); return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
module sia_txq_tb();
reg story_to, fault_to;
reg clk_i, reset_i;
reg [11:0] dat_i;
reg we_i;
wire txd_o, txc_o, not_full_o, empty_o, idle_o;
sia_txq #(
.SHIFT_REG_WIDTH(12),
.BAUD_RATE_WIDTH(32),
.DEPTH_BITS(2)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.we_i(we_i),
.bits_i(5'd10), // 8N1
.baud_i(32'd49), // 1Mbps when clocked at 50MHz.
.txcmod_i(3'b100),
.txd_o(txd_o),
.txc_o(txc_o),
.not_full_o(not_full_o),
.empty_o(empty_o),
.idle_o(idle_o)
);
always begin
#10 clk_i <= ~clk_i;
end
`STANDARD_FAULT
`DEFASSERT0(txd, o)
`DEFASSERT0(idle, o)
`DEFASSERT0(empty, o)
`DEFASSERT0(not_full, o)
initial begin
$dumpfile("sia_txq.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, we_i} <= 0;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
// Write a single value to the queue.
// Transmission should start soon thereafter.
dat_i <= 12'b111_11101101_0;
we_i <= 1;
wait(~clk_i); wait(clk_i); #1;
we_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1); // EMPTY reports FIFO status, not engine status.
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
#1000; // No TXC to wait on, so fake it 'til you make it.
assert_txd(1);
assert_idle(1);
assert_empty(1);
assert_not_full(1);
wait(~clk_i); wait(clk_i); #1;
// Keep writing until we fill the queue. For this test's
// configuration, that should amount to FIVE values.
// The first four are provided by the FIFO, and the third
// is whatever the engine has consumed and is currently
// sending.
dat_i <= 12'b111_11101101_0;
we_i <= 1;
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(0)
assert_empty(0);
assert_not_full(1);
fault_to <= 1;
wait(~clk_i); wait(clk_i); #1; // TXE activated; refills FIFO(0)
assert_empty(0);
assert_not_full(1);
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(1)
assert_empty(0);
assert_not_full(1);
fault_to <= 1;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(2)
assert_empty(0);
assert_not_full(1);
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(3); now full.
assert_empty(0);
assert_not_full(0);
fault_to <= 1'bX;
we_i <= 0;
#10000; // Wait for all five characters to be sent.
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(1);
assert_not_full(1);
#100;
$display("@I Done.");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long const N = 35; long long dp[N][2][2]; long long get(long long l, long long r) { if (l < 0 || r < 0) return 0; memset(dp, 0, sizeof dp); dp[35][1][1] = 1; for (long long i = 34; i >= 0; i--) { for (long long j = 0; j <= 1; j++) { for (long long k = 0; k <= 1; k++) { long long x = (j && !((l >> i) & 1ll)), y = (k && !((r >> i) & 1ll)); dp[i][x][y] += dp[i + 1][j][k]; if (!j || ((l >> i) & 1ll)) dp[i][j][y] += dp[i + 1][j][k]; if (!k || ((r >> i) & 1ll)) dp[i][x][k] += dp[i + 1][j][k]; } } } return dp[0][0][0] + dp[0][1][0] + dp[0][1][1] + dp[0][0][1]; } signed main() { long long T, l, r; scanf( %lld , &T); while (T--) { scanf( %lld%lld , &l, &r); long long ans = get(r, r) - get(l - 1, r) * 2 + get(l - 1, l - 1); printf( %lld n , ans); } return 0; }
|
Require Driver.
Cd "extracted".
Set Extraction AccessOpaque.
Extraction Blacklist String List.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
Extract Inductive nat => int [ "0" "Pervasives.succ" ]
"(fun fO fS n -> if n=0 then fO () else fS (n-1))".
(** Efficient (but uncertified) versions for usual [nat] functions *)
Extract Constant plus => "(+)".
Extract Constant pred => "fun n -> max 0 (n-1)".
Extract Constant minus => "fun n m -> max 0 (n-m)".
Extract Constant mult => "( * )".
Extract Inlined Constant max => max.
Extract Inlined Constant min => min.
(*Extract Inlined Constant nat_beq => "(=)".*)
Extract Inlined Constant EqNat.beq_nat => "(=)".
Extract Inlined Constant EqNat.eq_nat_decide => "(=)".
Extract Inlined Constant Peano_dec.eq_nat_dec => "(=)".
Extract Constant Compare_dec.nat_compare =>
"fun n m -> if n=m then Eq else if n<m then Lt else Gt".
Extract Inlined Constant Compare_dec.leb => "(<=)".
Extract Inlined Constant Compare_dec.le_lt_dec => "(<=)".
Extract Constant Compare_dec.lt_eq_lt_dec =>
"fun n m -> if n>m then None else Some (n<m)".
Extract Constant Even.even_odd_dec => "fun n -> n mod 2 = 0".
Extract Constant Div2.div2 => "fun n -> n/2".
Separate Extraction Driver.
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; int n, m; long long t[MAX << 2], tag[MAX << 2]; int sz = 1; inline void Period(int k, int l, int r, int a, int b, long long x) { if (a > r || b < l) return; if (a >= l && b <= r) { tag[k] = t[k] = x; return; } Period(k << 1, l, r, a, (a + b) >> 1, x); Period((k << 1) + 1, l, r, ((a + b) >> 1) + 1, b, x); t[k] = max(t[k << 1], t[(k << 1) + 1]); } inline long long Query(int k, int l, int r, int a, int b) { if (tag[k]) { t[k] = tag[k]; tag[k << 1] = max(tag[k << 1], tag[k]); tag[(k << 1) + 1] = max(tag[(k << 1) + 1], tag[k]); tag[k] = 0; } if (a > r || b < l) return 0; if (a >= l && b <= r) return t[k]; return max(Query(k << 1, l, r, a, (a + b) >> 1), Query((k << 1) + 1, l, r, ((a + b) >> 1) + 1, b)); } int main() { ios::sync_with_stdio(false); cin >> n; while (sz < n) sz <<= 1; for (int i = 1; i <= n; i++) { long long x; cin >> x; Period(1, i, i, 1, sz, x); } cin >> m; while (m--) { int x; long long h; cin >> x >> h; long long res = Query(1, 1, x, 1, sz); cout << res << endl; Period(1, 1, x, 1, sz, res + h); } return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); bool isPrime(int n) { if (n == 1) return false; for (int i = 2; i * i <= n; ++i) { if (n % i == 0) return false; } return true; } void solve() { int n, sum = 0; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; sum += a[i]; } if (!isPrime(sum)) { cout << n << n ; for (int i = 1; i <= n; ++i) { cout << i << ; } cout << n ; } else { cout << n - 1 << n ; int oddpos = -1; for (int i = 0; i < n; ++i) { if (a[i] % 2 != 0) { oddpos = i; break; } } for (int i = 0; i < n; ++i) { if (i != oddpos) cout << i + 1 << ; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { solve(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V
|
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_RS232 *
* Description: *
* This module reads and writes data to the RS232 connector on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
*****************************************************************************/
/* Settings */
`define USE_DATA_WIDTH_8 1
/* End settings */
module Altera_UP_Avalon_RS232 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BAUD_COUNTER_WIDTH = 9;
parameter BAUD_TICK_INCREMENT = 9'd1;
parameter BAUD_TICK_COUNT = 9'd433;
parameter HALF_BAUD_TICK_COUNT = 9'd216;
parameter TOTAL_DATA_WIDTH = 10;
parameter DATA_WIDTH = 8;
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [3:0] byteenable;
input read;
input write;
input [31:0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31:0] readdata;
output UART_TXD;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [7:0] read_available;
`ifdef USE_PARITY
wire [DATA_WIDTH:0] read_data;
`else
wire [(DATA_WIDTH - 1):0] read_data;
`endif
wire parity_error;
wire write_data_parity;
wire [7:0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DATA_WIDTH - 1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
6'h00,
parity_error,
`ifdef USE_DATA_WIDTH_7
2'h0,
`endif
`ifdef USE_DATA_WIDTH_8
1'b0,
`endif
read_data[(DATA_WIDTH - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (|read_available);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_to_uart <= 1'b0;
else
data_to_uart <= writedata[(DATA_WIDTH - 1):0];
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
`ifdef USE_PARITY
assign parity_error = (read_available != 8'h00) ?
((^(read_data[DATA_WIDTH:0])) ^ ODD_PARITY) :
1'b0;
`else
assign parity_error = 1'b0;
`endif
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_RS232_In_Deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_In_Deserializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_In_Deserializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_In_Deserializer.DATA_WIDTH = DATA_WIDTH;
`endif
Altera_UP_RS232_Out_Serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
`ifdef USE_PARITY
.transmit_data ({write_data_parity, data_to_uart}),
`else
.transmit_data (data_to_uart),
`endif
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_Out_Serializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_Out_Serializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_Out_Serializer.DATA_WIDTH = DATA_WIDTH;
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
|
// Check the various variable array selects (small to large).
module top;
reg passed;
wire [1:0] a [1:4];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [1:4];
wire [1:0] c [-3:0];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [-3:0];
wire [1:0] res_a0 = a[s0];
wire [1:0] res_a1 = a[s1];
wire [1:0] res_a2 = a[s2];
wire [1:0] res_c3 = c[s3];
wire [1:0] res_c4 = c[s4];
reg res_a [1:4];
reg res_c [-3:0];
assign a[1] = 2'd0;
assign a[2] = 2'b1;
assign a[3] = 2'd2;
assign a[4] = 2'd3;
assign c[-3] = 2'd0;
assign c[-2] = 2'b1;
assign c[-1] = 2'd2;
assign c[0] = 2'd3;
initial begin
#1;
passed = 1'b1;
ar[1] = 2'd0;
ar[2] = 2'b1;
ar[3] = 2'd2;
ar[4] = 2'd3;
cr[-3] = 2'd0;
cr[-2] = 2'b1;
cr[-1] = 2'd2;
cr[0] = 2'd3;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 2'bxx) begin
$display("Failed a[s0], expected 2'bxx, got %b", a[s0]);
passed = 1'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 2'bxx) begin
$display("Failed a[s1], expected 2'bxx, got %b", a[s1]);
passed = 1'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 2'bxx) begin
$display("Failed a[s2], expected 2'bxx, got %b", a[s2]);
passed = 1'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 2'b11) begin
$display("Failed c[s3], expected 2'b11, got %b", c[s3]);
passed = 1'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 2'b11) begin
$display("Failed c[s4], expected 2'b11, got %b", c[s4]);
passed = 1'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 2'bxx) begin
$display("Failed ar[s0], expected 2'bxx, got %b", ar[s0]);
passed = 1'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 2'bxx) begin
$display("Failed ar[s1], expected 2'bxx, got %b", ar[s1]);
passed = 1'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 2'bxx) begin
$display("Failed ar[s2], expected 2'bxx, got %b", ar[s2]);
passed = 1'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 2'b11) begin
$display("Failed cr[s3], expected 2'b11, got %b", cr[s3]);
passed = 1'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 2'b11) begin
$display("Failed cr[s4], expected 2'b11, got %b", cr[s4]);
passed = 1'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 2'bxx) begin
$display("Failed res_a0, expected 2'bxx, got %b", res_a0);
passed = 1'b0;
end
if (res_a1 !== 2'bxx) begin
$display("Failed res_a1, expected 2'bxx, got %b", res_a1);
passed = 1'b0;
end
if (res_a2 !== 2'bxx) begin
$display("Failed res_a2, expected 2'bxx, got %b", res_a2);
passed = 1'b0;
end
if (res_c3 !== 2'b11) begin
$display("Failed res_c3, expected 2'b11, got %b", res_c3);
passed = 1'b0;
end
if (res_c4 !== 2'b11) begin
$display("Failed res_c4, expected 2'b11, got %b", res_c4);
passed = 1'b0;
end
// Check procedural L-value variable bit selects.
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s0] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s1] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s2] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s3] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s3], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s4] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s4], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; char s[200]; char p[200]; char ans[200]; bool used[200][30]; bool brute(int pos) { if (pos == n) { puts(ans); exit(0); } if (ans[pos] != 0) { if (pos >= strlen(s) - 1) { if (p[pos - strlen(s) + 1] == 0 ) { bool ok = true; for (int j = strlen(s) - 1; j >= 0; j--) { if (ans[pos - j] != s[strlen(s) - 1 - j]) { ok = false; break; } } if (ok) return false; } } return brute(pos + 1); } memset(used[pos], 0, sizeof used[pos]); int cnt = k; bool need_check = false; if (pos >= strlen(s) - 1) { need_check = true; for (int i = strlen(s) - 1; i > 0; i--) { if (ans[pos - i] != s[strlen(s) - 1 - i]) { need_check = false; break; } } } for (int t = 0; t < k; t++) { ans[pos] = (char)( a + t); if (!need_check) { if (brute(pos + 1)) return true; } else { if (t != s[strlen(s) - 1] - a ) { if (brute(pos + 1)) return true; } } } ans[pos] = 0; return false; } int main() { scanf( %d %d n , &n, &k); gets(s); gets(p); memset(ans, 0, sizeof ans); for (int i = 0; i < strlen(p); i++) { if (p[i] == 1 ) { for (int j = 0; j < strlen(s); j++) { if (ans[i + j] == 0 || ans[i + j] == s[j]) { ans[i + j] = s[j]; } else { puts( No solution ); return 0; } } } } for (int i = 0; i < strlen(p); i++) { if (p[i] == 0 ) { bool ok = true; for (int j = 0; j < strlen(s); j++) { if (ans[i + j] != s[j]) { ok = false; break; } } if (ok) { puts( No solution ); return 0; } } } for (int i = 0; i < k; i++) { bool ok = true; for (int j = 0; j < strlen(s); j++) { if (s[j] - a == i) { ok = false; break; } } if (ok) { for (int j = 0; j < n; j++) { if (ans[j] == 0) ans[j] = (char)( a + i); } puts(ans); return 0; } } brute(0); puts( No solution ); }
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
`define DRIVE(sig) \
/* Just throw a bunch of bits at the input */ \
/* verilator lint_off WIDTH */ \
sig``_in <= {8{crc}}; \
/* verilator lint_on WIDTH */
`define CHECK(sig) \
if (cyc > 0 && sig``_in != sig``_out) begin \
$display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \
sig``_in, sig``_out); \
$stop; \
end
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam last_cyc =
`ifdef TEST_BENCHMARK
`TEST_BENCHMARK;
`else
10;
`endif
genvar x;
generate
for (x = 0; x < 2; x = x + 1) begin: gen_loop
integer cyc = 0;
reg [63:0] crc = 64'h5aef0c8d_d70a4497;
logic [31:0] accum_in;
logic [31:0] accum_out;
logic accum_bypass;
logic [31:0] accum_bypass_out;
logic [31:0] accum_out_expect;
logic [31:0] accum_bypass_out_expect;
logic s1_in;
logic s1_out;
logic [1:0] s2_in;
logic [1:0] s2_out;
logic [7:0] s8_in;
logic [7:0] s8_out;
logic [32:0] s33_in;
logic [32:0] s33_out;
logic [63:0] s64_in;
logic [63:0] s64_out;
logic [64:0] s65_in;
logic [64:0] s65_out;
logic [128:0] s129_in;
logic [128:0] s129_out;
logic [3:0] [31:0] s4x32_in;
logic [3:0] [31:0] s4x32_out;
secret
secret (
.accum_in,
.accum_out,
.accum_bypass,
.accum_bypass_out,
.s1_in,
.s1_out,
.s2_in,
.s2_out,
.s8_in,
.s8_out,
.s33_in,
.s33_out,
.s64_in,
.s64_out,
.s65_in,
.s65_out,
.s129_in,
.s129_out,
.s4x32_in,
.s4x32_out,
.clk);
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d",
$time, x, cyc, accum_in, accum_out, accum_bypass_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
accum_in <= accum_in + 5;
// 7 is the secret_value inside the secret module
accum_out_expect <= accum_in + accum_out_expect + 7;
`DRIVE(s1)
`DRIVE(s2)
`DRIVE(s8)
`DRIVE(s33)
`DRIVE(s64)
`DRIVE(s65)
`DRIVE(s129)
`DRIVE(s4x32)
if (cyc == 0) begin
accum_in <= x*100;
accum_bypass <= '0;
end else if (cyc > 0) begin
if (accum_out_expect != accum_out) begin
$display("%%Error: (%m) accum_out expected %0d got %0d",
accum_out_expect, accum_out);
$stop;
end
if (accum_bypass_out_expect != accum_bypass_out) begin
$display("%%Error: (%m) accum_bypass_out expected %0d got %0d",
accum_bypass_out_expect, accum_bypass_out);
$stop;
end
end
if (cyc == 5) accum_bypass <= '1;
if (x == 0 && cyc == last_cyc) begin
$display("final cycle = %0d", cyc);
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(*) begin
// XSim (and maybe all event simulators?) sees the moment where
// s1_in has not yet propagated to s1_out, however, they do always
// both change at the same time
/* verilator lint_off STMTDLY */
#1;
/* verilator lint_on STMTDLY */
`CHECK(s1)
`CHECK(s2)
`CHECK(s8)
`CHECK(s33)
`CHECK(s64)
`CHECK(s65)
`CHECK(s129)
`CHECK(s4x32)
end
assign accum_bypass_out_expect = accum_bypass ? accum_in :
accum_out_expect;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3100; const int inf = 1e9 + 100; struct node { int a, b; } l[maxn]; int s[maxn * 2 + 10], dp[maxn][maxn * 2 + 10], to[maxn]; int cmp(node a, node b) { if (a.b != b.b) return a.b < b.b; else { return a.a > b.a; } } int main() { int num, T, top, n; scanf( %d , &T); while (T--) { scanf( %d , &n); top = 0; for (int i = 1; i <= n; i++) { scanf( %d%d , &l[i].a, &l[i].b); s[++top] = l[i].a; s[++top] = l[i].b; } sort(s + 1, s + top + 1); num = unique(s + 1, s + top + 1) - s - 1; sort(l + 1, l + n + 1, cmp); for (int i = 1; i <= n; i++) { l[i].a = lower_bound(s + 1, s + num + 1, l[i].a) - s; l[i].b = lower_bound(s + 1, s + num + 1, l[i].b) - s; } for (int i = 1; i <= n; i++) { to[i] = 0; for (int j = i - 1; j >= 1; j--) { if (l[j].b < l[i].a) { to[i] = j; break; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= num; j++) { dp[i][j] = 0; } } for (int i = 1; i <= n; i++) { for (int j = l[i].b; j >= 1; j--) { dp[i][j] = dp[i - 1][j]; if (l[i].a >= j) { dp[i][j] = max(dp[i][j], dp[to[i]][j] + dp[i - 1][l[i].a] + 1); } } } printf( %d n , dp[n][1]); } return 0; }
|
module ovm;
class simple_item extends ovm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// OVM automation macros for general objects
`ovm_object_utils_begin(simple_item)
a = b;
c = d;
`ovm_field_int(addr, OVM_ALL_ON)
`ovm_field_int(data, OVM_ALL_ON)
`ovm_field_int(delay, OVM_ALL_ON)
`ovm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends ovm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`ovm_object_utils(mydata)
`ovm_object_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
`ovm_object_param_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
endclass
class my_trans extends ovm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`ovm_object_utils_begin(my_trans)
`ovm_field_array_int ( data, OVM_ALL_ON)
`ovm_object_utils_end
function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // ovm
module tt;
initial begin
while (1) begin
`ovm_do_with(aa, {bb == 0;})
`ovm_do(cc)
`ovm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.