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#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 5; const int M = 1e6; const long long INF = (long long)(1e18); const int inf = 1e9; const long long MOD = 1000000007LL; long long n, m; long long a[MAX_N]; long long ans[MAX_N]; long long suff[MAX_N]; void solve() {} int main(... |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 10:22:00 11/21/2016
// Module Name: FORWARDING_UNIT
// Project Name:... |
#include <bits/stdc++.h> using namespace std; const int N = 100100; const long long MOD = 100030001, H = 47; map<int, long long> d[N]; vector<int> adj[N]; set<pair<long long, int> > s; vector<pair<int, pair<long long, int> > > nei[N]; long long r[N], l[N], num[N], ch[N], h[3 * N], n, sz, ans, o = 10, c ... |
#include <bits/stdc++.h> using namespace std; const long long int INF = 2e18; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) { if (n % i == 0 || n % (i + 2) == 0) ... |
#include <bits/stdc++.h> using namespace std; struct fast_ios { fast_ios() { cin.tie(nullptr), ios::sync_with_stdio(false), cout << fixed << setprecision(20); }; } fast_ios_; string solve(string S) { const int N = S.length(); int L = N; while (L % 2 == 0) L /= 2; while (L... |
module S3A3(C50, C1, Anodo1, D1);
input C50;
output reg C1=0;
output Anodo1=1;
output reg [6:0] D1=0;
reg [24:0] Ct1 = 0;
reg [3:0] unidades=0;
parameter [6:0] cero = 7'b0000001;
parameter [6:0] uno = 7'b0000001;
parameter [6:0] dos = 7'b0000001;
parameter [6:0] tres = 7'b0000001;
parameter [6:0] cuatro... |
// file: Master_Clock_Divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaim... |
#include <bits/stdc++.h> using namespace std; char symmetric[11] = { A , H , I , M , O , T , U , V , W , X , Y }; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if... |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ S... |
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } vector<int> v... |
#include <bits/stdc++.h> using namespace std; const long long maxn = 3e5 + 5; long long n, q, a[maxn], c[maxn]; long long read() { long long res = 0, f = 1; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (!isdigit(ch)); do { res = res * 10 + ch - 0 ; ch... |
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed t... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: seven_seg_decoder
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14... |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int n, m; int clauses[123123][2]; vector<int> uses[123123]; bool vis[123123]; vector<int> chain[123123]; int counter; vector<pair<long long, long long>> dips; long long ans; int rightc(int cnr) { int xnr = abs(clauses[cn... |
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k, lst, a[22], b[1 << 18], o[1 << 18]; long long f[1 << 18][18], g[1 << 18]; char s[22][22]; void rec(int sum, int x, int mask) { if (sum == 0) { for (i = 0; i < (1 << n); i++) if (b[i] > lst) for (j = 0; j < n; j++) f[i... |
#include <bits/stdc++.h> using namespace std; const int N = 100; int cost[N][2], timee, tmm, num, clr, n; char ha, arr[25]; string tm1, tm2; int main() { scanf( %s , &arr); tm1 = arr; scanf( %s%d , &arr, &n); tm2 = arr; while (n--) { scanf( %d %c%d %c , &timee, &tmm, &num, &clr);... |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
... |
module pulses(
/* This module sets up the output logic, including the pulse and block switches, the attenuator(s),
and the scope trigger. It needs to have two modes:
A CW mode, which holds both switches open, and outputs a trigger for the scope and the SynthHD.
This mode is ... |
#include <bits/stdc++.h> using namespace std; const int maxn = 1001000; const int INF = 1e9; int n, L, U; int head[maxn], nxt[maxn << 1], rdc[maxn << 1], w[maxn << 1], tnt; int prt, rt, asiz; int siz[maxn], mdep[maxn]; int fdep, gdep; int f[maxn], g[maxn], fp[maxn], gp[maxn], dta; int q[maxn], qt, q... |
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, cnt; vector<int> e[N]; vector<pair<int, int> > ans; void init() { scanf( %d , &n); for (int i = 1, x, y; i < n; ++i) { scanf( %d %d , &x, &y); e[x].push_back(y); e[y].push_back(x); } } void dfs(int x... |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) using namespace std; int a, b, c, d, n, m, k; long long pc[1000001]; long long dp[7][333335]; int f[6]; const int N = 333333; const long long infll = (long long)1000000000 * 1000000000... |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; pair<int, int> A[N]; int factorial[N]; int twos[N]; int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = (int)0; i < (int)2 * n; i++) { cin >> A[i].first; A[i].second = i % n; } sort(... |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int maxn = 2e5 + 50; const long long inf = 1e17; int t; void get() { fflush(stdout); scanf( %d , &t); for (int i = 1; i <= t; i++) scanf( %*s ); } int main() { do { puts( next 0 1 ), get(); put... |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is dis... |
#include <bits/stdc++.h> using namespace std; int row[1010]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); memset(row, 0x3f3f3f3f, sizeof row); long long ans = 0; for (int i = (0); i < (n); ++i) { int r, c; scanf( %d %d , &r, &c); row[r] = min(c, row[r]); } ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; inline int read() { int sum = 0; char c = getchar(); bool f = 0; while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } if (f) r... |
#include <bits/stdc++.h> using namespace std; template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; ... |
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// ,
//
// Create Date: 16:54:00 06/03/2014
// Design Name: tb_signal_gen
// Module Name: tb_signal_gen
// Project Name: Streaming Media on Null Convention Logic
/... |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*
File: ewrapper_io_tx_slow.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free ... |
module reset_test_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
reg [1:0] i;
wire [0:0] rval;
assign rval = {reset, 1'b0 };
always @(posedge clk)
begin
case (|(reset))
1'b 1:
... |
//
// my_fpga.v
//
module my_fpga (
input clk, n_rst,
input up, dn,
output [31:0] cnt,
output [3:0] cnt_1k,
input in1, in2,
output out1, out2);
reg rst;
reg [1:0] rst_sr;
reg [31:0] count;
reg [16:0] div_count;
reg [3:0] count_1k;
or_gate g1(in1, in2, out1);
... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > v; long long x; long long k; int broj; int main(void) { cin >> x; k = 0; long long i = 1; for (long long i = 1; i <= sqrt(x); ++i) { if (k + i * i > (1000000000000000000)) goto van; k = k + i * i; ... |
#include <bits/stdc++.h> using namespace std; constexpr int INF = 1e9 + 1; constexpr long long LLINF = 1e18 + 1; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } void solve() { int n, t; cin >> n; vect... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
module ereset (/*AUTOARG*/
// Outputs
etx_reset, erx_reset, sys_reset,etx90_reset,erx_ioreset,
// Inputs
reset, sys_clk, tx_lclk_div4, rx_lclk_div4,tx_lclk90,rx_lclk
);
// reset inputs
input reset; // POR | ~elink_en (with appropriate delays..)
//synchronization clocks
input ... |
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the follo... |
#include <bits/stdc++.h> const int N = 1e3 + 5; using namespace std; int main() { ios::sync_with_stdio(false); int arr[N][N], str, sve, k, n[N], m[N], i, j, x, y; char ch; cin >> str >> sve >> k; for (i = 1; i <= str; i++) for (j = 1; j <= sve; j++) cin >> arr[i][j]; for (i = 1; i <=... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 06:19:33 AM
// Design Name:
// Module Name: Barrel_Shifter_M
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:35:35 07/12/2015
// Design Name:
// Module Name: Distributed_RAM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//... |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time bas... |
#include <bits/stdc++.h> using namespace std; int a, ta; int b, tb; int h, m; bool read() { if (!(cin >> a >> ta)) return false; assert(cin >> b >> tb); assert(scanf( %d:%d , &h, &m) == 2); return true; } void solve() { int x1 = h * 60 + m; int y1 = x1 + ta; int ans = 0; fo... |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, num = 1, mul; cin >> n; string s = codeforces ; int ln = s.length(), a[12] = {0}; for (long long int i = 2; i <= 100; i++) { long long int curr = pow(i, 10ll); if (curr >= n) { for (int j = 0; j < 10... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug511
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [7:0] au;
wire [7:0] a... |
#include <bits/stdc++.h> using namespace std; const int N = 3010, Mo = 1000000007; int tt, n, D; int f[N][N], rev[N * 2], head[N], to[N], nxt[N]; inline int gi() { int x = 0, o = 1; char ch = getchar(); while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) o = -1, ch = get... |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// -------... |
#include <bits/stdc++.h> int n, k, s, e, m, ans, temp, tp, tv; bool m11, m22, first, b[100005], move; char a[100005]; int dist() { if (m - s < e - m) return e - m; else return m - s; } int main() { scanf( %d %d , &n, &k); scanf( %s , a); for (e = 0; e < n; e++) { if (a[... |
#include <bits/stdc++.h> int main() { int n, b = 1, i = 1; scanf( %d , &n); for (i = 1; i < n; i++) { b = b + i; if (b > n) b = b % n; printf( %d n , b); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, const U &b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, const U &b) { if (a < b) a = b; } int a[2020]; struct Dinic { int V, E, src, tar; int head[2... |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int dp[100005], x[105], s[105]; bool vis[100005]; int main() { int n, m, minv = INF; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d%d , &x[i], &s[i]); minv = min(minv, x[i]); for (int j = ma... |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; char s[N]; int main() { vector<int> v1, v2; scanf( %s , s); int len = strlen(s); for (int i = 0; i < len; i++) { if (s[i] == l ) { v1.push_back(i + 1); } else v2.push_back(i + 1); } for (in... |
// Streams the contents of memory to an LCD through a FIFO.
module Frame_buffer
#(parameter ADDRESS=0, LENGTH=0)
(
input wire clock,
input wire reset_n,
// Memory interface:
output reg [28:0] address,
output wire [7:0] burstcount,
input wire waitrequest,
input wire [63:0] readdata,
... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; int main() { double R, r, k; int tt; scanf( %d , &tt); while (tt--) { scanf( %lf%lf%lf , &R, &r, &k); double a = (R + r) / (4 * R * r), b = k * (R - r) / (2 * R * r); double t = (R - r) / (4 * R * r); double s = t / (a * a + b * b... |
#include <bits/stdc++.h> const int maxn = 1e6 + 9, mod = 998244353, inf = 0x3f3f3f3f; int Read() { int x(0), f(1); char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3ll) + (x << 1ll) + c - 0 ; ... |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_8_b2s_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data a... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 00:48:48
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000010; struct node { int v, id; } MAX[MAXN], MMAX[MAXN]; int n, f[MAXN]; int main() { scanf( %d , &n); n++; MAX[1].v = MMAX[1].v = 0; MAX[1].id = MMAX[1].id = 1; for (register int i = 2; i <= n; i++) { scanf( %d ,... |
#include <bits/stdc++.h> using namespace std; int main() { int a[100] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5,... |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MM_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Descri... |
/*
* DUT VGA LCD FML
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundat... |
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, e; cin >> n >> d >> e; long long a = n, b = n, i; e = 5 * e; for (i = 0; e * i <= n; i++) { a = min(a, (n - (e * i)) % d); } for (i = 0; d * i <= n; i++) { b = min(b, (n - (d * i)) % e); } cout... |
#include <bits/stdc++.h> using namespace std; long mod(long int a) { return (a > 0 ? a : (-a)); } long min(long int a, long int b) { return (a) > (b) ? (b) : (a); } long max(long int a, long int b) { return (a) < (b) ? (b) : (a); } bool sortbyff(const pair<int, int> &a, const pair<int, int> &b) { return (... |
#include <bits/stdc++.h> using namespace std; char s[2000010], t[2000010]; int main(void) { int n; scanf( %d , &n); scanf( %s , s); scanf( %s , t); int count_s, count_t, count_com; count_s = count_t = count_com = 0; for (int i = 0; i < 2 * n; ++i) { if (s[i] == 1 && t[i] == 1 ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; int main() { vector<pair<int, int> > v; int n, i, c = 1, ans = 0; vector<pair<int, int> >::iterator it; cin >> n; for (i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back(make_pair(y, x)); } sort(v.begin(), v.end()); ... |
`timescale 1ns/10ps
module RegBankP2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out_0;
wire [7:0] out_1;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever ... |
#include <bits/stdc++.h> int main() { int a, b, c, d, p1, p2, p3, p4; scanf( %d %d %d %d , &a, &b, &c, &d); p1 = ((3 * a / 10)); p2 = (a - (a * c / 250)); if (p1 > p2) { p1 = p1; } else if (p2 > p1) { p1 = p2; } else if (p2 == p1) { p1 = p1; } p3 = ((3 * b / 10));... |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int maxn = 100001, inf = 2147483647; const long long mod = 1 ? 998244353 : 1000000007, linf = 9223372036854775807; const double pi = acos(-1); inline long long mi(long long a, long long b, long long mm = mod) { a %= mm; long... |
#include <bits/stdc++.h> using namespace std; double distance(double x1, double y1, double x2, double y2) { return sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); } int main() { double ax, ay, bx, by, tx, ty; scanf( %lf%lf%lf%lf%lf%lf , &ax, &ay, &bx, &by, &tx, &ty); int n; scanf( %d , ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
lo... |
module \$_DFF_N_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMA... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2016 01:33:37 PM
// Design Name:
// Module Name: fslcd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Re... |
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
in... |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const int N = 510000, M = N << 1; int n, hd[N], to[M], nxt[M], noedg = 1, size[N]; long long buc[N], f[N], ans = inf; vector<int> app[N]; template <class T> inline void read(T &x) { x = 0; char ch = getchar(), w = 0; w... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// R... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
#include <iostream> #include <vector> #include <algorithm> #include <string> #include <map> #include <unordered_set> #include <unordered_map> #include <cmath> #include <random> #include <chrono> #include <set> #include <queue> #include <stack> #include <deque> #include <cstring> const long... |
#include <bits/stdc++.h> using namespace std; double R, r; struct Punct { double x, y; }; Punct A, B; inline double Dist(Punct A, Punct B) { return sqrt((A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y)); } int main() { double d; cin >> A.x >> A.y >> R; cin >> B.x >> B.y >> r; ... |
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
module sia_txq_tb();
reg story_to, fault_to;
reg clk_i, reset_i;
reg [11:0] dat_i;
reg we_i;
wire txd_o, txc_o, not_full_o, empty_o, idle_o;
sia_txq #(
.SHIFT_REG_WIDTH(12),
.BAUD_RATE_WIDTH(32),
.DEPTH_BITS(2)
) x(
.clk_i(clk_i),
... |
#include <bits/stdc++.h> using namespace std; long long const N = 35; long long dp[N][2][2]; long long get(long long l, long long r) { if (l < 0 || r < 0) return 0; memset(dp, 0, sizeof dp); dp[35][1][1] = 1; for (long long i = 34; i >= 0; i--) { for (long long j = 0; j <= 1; j++) { ... |
Require Driver.
Cd "extracted".
Set Extraction AccessOpaque.
Extraction Blacklist String List.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )... |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; int n, m; long long t[MAX << 2], tag[MAX << 2]; int sz = 1; inline void Period(int k, int l, int r, int a, int b, long long x) { if (a > r || b < l) return; if (a >= l && b <= r) { tag[k] = t[k] = x; return; } ... |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); bool isPrime(int n) { if (n == 1) return false; for (int i = 2; i * i <= n; ++i) { if (n % i == 0) return false; } return true; } void solve() { int n, sum = 0; cin ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_RS232 *
* Description: *
* ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// Check the various variable array selects (small to large).
module top;
reg passed;
wire [1:0] a [1:4];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [1:4];
wire [1:0] c [-3:0];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [-3:0];
wire [1:0] res_a0 = a[s0];
wir... |
#include <bits/stdc++.h> using namespace std; int n, k; char s[200]; char p[200]; char ans[200]; bool used[200][30]; bool brute(int pos) { if (pos == n) { puts(ans); exit(0); } if (ans[pos] != 0) { if (pos >= strlen(s) - 1) { if (p[pos - strlen(s) + 1] == 0 ) { ... |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
`define DRIVE(sig) \
/* Just throw a bunch of bits at the input */ \
/* verilator lint_off WIDTH */ \
sig``_in <= {8{crc}}; \
/* verilator lint_on WIDTH */
`define ... |
#include <bits/stdc++.h> using namespace std; const int maxn = 3100; const int inf = 1e9 + 100; struct node { int a, b; } l[maxn]; int s[maxn * 2 + 10], dp[maxn][maxn * 2 + 10], to[maxn]; int cmp(node a, node b) { if (a.b != b.b) return a.b < b.b; else { return a.a > b.a; } }... |
module ovm;
class simple_item extends ovm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// OVM automation macros for general objects
`ovm_object_utils_begin(simple_item)
a = b;
... |
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