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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_data_receive(
input posedge_clk,
input rx_resetn,
input ready_control_p_r,
input ready_data_p_r,
input ready_control,
input ready_data,
input parity_rec_c,
input parity_rec_d,
input parity_rec_c_gen,
input parity_rec_d_gen,
input [2:0] control_p_r,
input [2:0] control_l_r,
input [8:0] dta_timec_p,
output reg [1:0] state_data_process,
output reg last_is_control,
output reg last_is_data,
output reg last_is_timec,
output reg rx_error_c,
output reg rx_error_d,
output reg rx_got_fct,
output reg [8:0] rx_data_flag/* synthesis dont_replicate */,
output reg [7:0] timecode/* synthesis dont_replicate */
);
reg [1:0] next_state_data_process/* synthesis dont_replicate */;
always@(*)
begin
next_state_data_process = state_data_process;
case(state_data_process)
2'd0:
begin
if(ready_control_p_r || ready_data_p_r)
begin
next_state_data_process = 2'd1;
end
else
begin
next_state_data_process = 2'd0;
end
end
2'd1:
begin
if(ready_control || ready_data)
begin
next_state_data_process = 2'd0;
end
else
begin
next_state_data_process = 2'd1;
end
end
default:
begin
next_state_data_process = 2'd0;
end
endcase
end
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
rx_data_flag <= 9'd0;
timecode <= 8'd0;
state_data_process <= 2'd0;
rx_error_c <= 1'b0;
rx_error_d <= 1'b0;
rx_got_fct <= 1'b0;
end
else
begin
state_data_process <= next_state_data_process;
case(state_data_process)
2'd0:
begin
rx_error_c <= rx_error_c;
rx_error_d <= rx_error_d;
if(ready_control_p_r)
begin
if(control_l_r[2:0] != 3'd7 && control_p_r[2:0] == 3'd4)
begin
rx_got_fct <= 1'b1;
end
else
begin
rx_got_fct <= 1'b0;
end
if(control_p_r[2:0] == 3'd6)
begin
rx_data_flag <= 9'b100000001;
end
else if(control_p_r[2:0] == 3'd5)
begin
rx_data_flag <= 9'b100000000;
end
else
begin
rx_data_flag <= rx_data_flag;
end
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
end
else if(ready_data_p_r)
begin
rx_got_fct <= 1'b0;
if(control_p_r[2:0] == 3'd7)
begin
timecode <= {dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
end
else
begin
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
end
end
else
begin
rx_got_fct <= 1'b0;
timecode <= timecode;
end
end
2'd1:
begin
if(ready_control_p_r)
begin
if(parity_rec_c_gen != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
else
rx_error_c <= rx_error_c;
rx_got_fct <= rx_got_fct;
end
else if(ready_data_p_r)
begin
if(parity_rec_d_gen != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
else
rx_error_d <= rx_error_d;
rx_got_fct <= 1'b0;
end
else
begin
rx_error_c <= rx_error_c;
rx_error_d <= rx_error_d;
rx_got_fct <= 1'b0;
end
rx_data_flag <= rx_data_flag;
timecode <= timecode;
end
default:
begin
rx_data_flag <= rx_data_flag;
timecode <= timecode;
rx_got_fct <= rx_got_fct;
end
endcase
end
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Arguments id {A} x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Local Open Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Arguments prod_curry {A B C} f p.
Arguments prod_uncurry {A B C} f x y.
|
// megafunction wizard: %LPM_CONSTANT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_constant
// ============================================================
// File Name: lpm_constant3.v
// Megafunction Name(s):
// lpm_constant
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_constant3 (
result);
output [11:0] result;
wire [11:0] sub_wire0;
wire [11:0] result = sub_wire0[11:0];
lpm_constant lpm_constant_component (
.result (sub_wire0));
defparam
lpm_constant_component.lpm_cvalue = 4095,
lpm_constant_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=Zsql",
lpm_constant_component.lpm_type = "LPM_CONSTANT",
lpm_constant_component.lpm_width = 12;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "Zsql"
// Retrieval info: PRIVATE: Radix NUMERIC "16"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Value NUMERIC "4095"
// Retrieval info: PRIVATE: nBit NUMERIC "12"
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "4095"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=Zsql"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: USED_PORT: result 0 0 12 0 OUTPUT NODEFVAL result[11..0]
// Retrieval info: CONNECT: result 0 0 12 0 @result 0 0 12 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
// Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and
// SINGLE_ENDED added. PK. 6/20/08
// Rev 1.2 - Loacalparam CLK_GENERATOR added and logic for clocks generation
// using PLL or DCM added as generic code. PK. 10/14/08
// Rev 1.3 - Added parameter NOCLK200 with default value '0'. Used for
// controlling the instantiation of IBUFG for clk200. jul/03/09
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_infrastructure #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter CLK_PERIOD = 3000,
parameter CLK_TYPE = "DIFFERENTIAL",
parameter DLL_FREQ_MODE = "HIGH",
parameter NOCLK200 = 0,
parameter RST_ACT_LOW = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input clk200_p,
input clk200_n,
input idly_clk_200,
output clk0,
output clk90,
output clk200,
output clkdiv0,
input sys_rst_n,
input idelay_ctrl_rdy,
output rst0,
output rst90,
output rst200,
output rstdiv0
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = CLK_PERIOD/1000;
// By default this Parameter (CLK_GENERATOR) value is "PLL". If this
// Parameter is set to "PLL", PLL is used to generate the design clocks.
// If this Parameter is set to "DCM",
// DCM is used to generate the design clocks.
localparam CLK_GENERATOR = "PLL";
wire clk0_bufg;
wire clk0_bufg_in;
wire clk90_bufg;
wire clk90_bufg_in;
wire clk200_bufg;
wire clkdiv0_bufg;
wire clkdiv0_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
wire sys_clk_ibufg;
wire sys_rst;
assign sys_clk_ibufg = sys_clk; // ssiegel - place memory clock from IBUFG on sys_clk_ibufg
assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
assign clk0 = clk0_bufg;
assign clk90 = clk90_bufg;
assign clk200_bufg = idly_clk_200; // added ssiegel
assign clk200 = clk200_bufg;
assign clkdiv0 = clkdiv0_bufg;
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
generate
if (CLK_GENERATOR == "PLL") begin : gen_pll_adv
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (10.000),
.CLKOUT0_DIVIDE (CLK_PERIOD_INT),
.CLKOUT1_DIVIDE (CLK_PERIOD_INT),
.CLKOUT2_DIVIDE (CLK_PERIOD_INT*2),
.CLKOUT3_DIVIDE (1),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (90.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (CLK_PERIOD_INT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk0_bufg_in),
.CLKOUT1 (clk90_bufg_in),
.CLKOUT2 (clkdiv0_bufg_in),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
end else if (CLK_GENERATOR == "DCM") begin: gen_dcm_base
DCM_BASE #
(
.CLKIN_PERIOD (CLK_PERIOD_NS),
.CLKDV_DIVIDE (2.0),
.DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
.DUTY_CYCLE_CORRECTION ("TRUE"),
.FACTORY_JF (16'hF0F0)
)
u_dcm_base
(
.CLK0 (clk0_bufg_in),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (clk90_bufg_in),
.CLKDV (clkdiv0_bufg_in),
.CLKFX (),
.CLKFX180 (),
.LOCKED (locked),
.CLKFB (clk0_bufg),
.CLKIN (sys_clk_ibufg),
.RST (sys_rst)
);
end
endgenerate
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFG U_BUFG_CLK90
(
.O (clk90_bufg),
.I (clk90_bufg_in)
);
BUFG U_BUFG_CLKDIV0
(
.O (clkdiv0_bufg),
.I (clkdiv0_bufg_in)
);
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL/ DCM hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL/DCM deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. In the case of all resets except rst200, also assert reset if the
// IDELAY master controller is not yet ready
// 3. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
//***************************************************************************
assign rst_tmp = sys_rst | ~locked | ~idelay_ctrl_rdy;
// synthesis attribute max_fanout of rst0_sync_r is 10
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
// synthesis attribute max_fanout of rstdiv0_sync_r is 10
always @(posedge clkdiv0_bufg or posedge rst_tmp)
if (rst_tmp)
rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
else
// logical left shift by one (pads with 0)
rstdiv0_sync_r <= rstdiv0_sync_r << 1;
// synthesis attribute max_fanout of rst90_sync_r is 10
always @(posedge clk90_bufg or posedge rst_tmp)
if (rst_tmp)
rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst90_sync_r <= rst90_sync_r << 1;
// make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
// synthesis attribute max_fanout of rst200_sync_r is 10
always @(posedge clk200_bufg or negedge locked)
if (!locked)
rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst200_sync_r <= rst200_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
assign rst90 = rst90_sync_r[RST_SYNC_NUM-1];
assign rst200 = rst200_sync_r[RST_SYNC_NUM-1];
assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int a[200000]; long long int left1[200000][2]; long long int right1[200000][2]; long long int ans[200000]; int main() { long long int n; cin >> n; left1[1][0] = 0; right1[n][0] = 0; for (long long int i = 1; i <= n; i++) cin >> a[i]; left1[1][1] = a[1]; right1[n][1] = a[n]; for (long long int i = 2; i <= n; i++) { left1[i][1] = max(a[i], left1[i - 1][1] + 1); left1[i][0] = left1[i - 1][0] + (left1[i][1] - a[i]); } for (long long int i = n - 1; i >= 0; i--) { right1[i][1] = max(a[i], right1[i + 1][1] + 1); right1[i][0] = right1[i + 1][0] + right1[i][1] - a[i]; } for (long long int i = 1; i <= n; i++) ans[i] = left1[i - 1][0] + right1[i + 1][0] + max(left1[i][1], right1[i][1]) - a[i]; long long int j = 1e18; for (long long int i = 1; i <= n; i++) { j = min(ans[i], j); } cout << j; }
|
// file: zynq_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module zynq_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_zynq_1_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_zynq_1_clk_wiz_0_0;
wire clkfbout_buf_zynq_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_zynq_1_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_zynq_1_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_zynq_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_zynq_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_zynq_1_clk_wiz_0_0),
.I (clkfbout_zynq_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_zynq_1_clk_wiz_0_0));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, d0, d1
);
input clk;
input [7:0] d0, d1;
logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed },
'{ '1, '1, 8'h11, 8'h22 }};
logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed },
'{ '1, '1, 8'h11, 8'h22 }};
logic [7:0] data [1:0][3:0];
logic [7:0] datl [0:1][0:3];
initial begin
data = '{ '{ d0, d1, 8'hfe, 8'hed },
'{ d1, d1, 8'h11, 8'h22 }};
data[0] = '{ d0, d1, 8'h19, 8'h39 };
datl = '{ '{ d0, d1, 8'hfe, 8'hed },
'{ d1, d1, 8'h11, 8'h22 }};
datl[0] = '{ d0, d1, 8'h19, 8'h39 };
`ifdef TEST_VERBOSE
$display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]);
$display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]);
$display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]);
$display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]);
`endif
if (inia[0][0] !== 8'h22) $stop;
if (inia[0][1] !== 8'h11) $stop;
if (inia[1][0] !== 8'hed) $stop;
if (inia[1][1] !== 8'hfe) $stop;
if (inil[0][2] !== 8'hfe) $stop;
if (inil[0][3] !== 8'hed) $stop;
if (inil[1][2] !== 8'h11) $stop;
if (inil[1][3] !== 8'h22) $stop;
if (data[0][0] !== 8'h39) $stop;
if (data[0][1] !== 8'h19) $stop;
if (data[1][0] !== 8'hed) $stop;
if (data[1][1] !== 8'hfe) $stop;
if (datl[0][2] !== 8'h19) $stop;
if (datl[0][3] !== 8'h39) $stop;
if (datl[1][2] !== 8'h11) $stop;
if (datl[1][3] !== 8'h22) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__decap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int __gcd(int x, int y) { if (!y) return x; return __gcd(y, x % y); } const long long linf = 1e18 + 5; int mod = (int)1e9; const int logN = 18; const int inf = 1e9 + 9; const int N = 1e5 + 5; int ff, h[N], n, a[N], x, y, z, p; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); h[a[i]]++; } int ff = 0; for (int i = 1; i <= 100000; i++) if (h[i] & 1) ff = 1; if (ff) { cout << Conan ; } else cout << Agasa ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000 * 1000 + 20; const int N5 = 300 * 1000 + 10; const int N3 = 3000 + 20; const long long mod = 1000 * 1000 * 1000 + 9; const long long inf = LLONG_MAX / 2; long long dp[2][N], par[N], rnk[N]; long long __pow(long long x, int y) { if (y == 0) return 1; return __pow(x * x % mod, y / 2) % mod * (y & 1 ? x : 1) % mod; } int find_root(int v) { if (par[v] == v) { return v; } return par[v] = find_root(par[v]); } void _merge(int a, int b) { int r_a = find_root(a); int r_b = find_root(b); if (rnk[r_a] > rnk[r_b]) { swap(r_a, r_b); } par[r_a] = r_b; if (rnk[r_a] == rnk[r_b]) { rnk[r_b]++; } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; int t = 0; for (int i = 1; i <= n; i++) par[i] = i; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; if (find_root(x) != find_root(y)) { t++; _merge(x, y); } cout << ((__pow(2, i - t) + mod) - 1) % mod << n ; } }
|
// a memory module
// note that addr is a byte address. To simplify our implementation
// we use addr>>2 to index the memory array.
module mem(addr,datain,dataout, MemWrite, MemRead);
// currently the memory has 128 32-bit words
parameter mem_capacity = 4096;
input [31:0] addr, datain;
output [31:0] dataout;
reg [31:0] dataout;
// controls when writing and when readiing
input MemWrite, MemRead;
// memory cells are defined here
// reg [31:0] memory [mem_capacity-1:0];
reg [31:0] memory [mem_capacity-1:0];
integer i;
// reset it at the beginning
initial begin
for (i=0; i<mem_capacity-1; i=i+1)
memory[i] = 0;
// read initial data into the memory
// pls refer to http://www.asic-world.com/verilog/memory_fsm1.html
$readmemh("mem.dat", memory);
end
// whenever the any of sigals (addr or datain or memwrite or memread) changes
always @(addr or datain or MemWrite or MemRead)
begin
if (MemRead)
dataout = memory[addr>>2];
if (MemWrite)
memory[addr>>2] = datain;
end
endmodule
module MemTestbench;
reg [31:0] addr, datain;
reg MemWrite, MemRead;
wire [31:0] dataout;
mem UUT(addr, datain, dataout, MemWrite, MemRead);
initial begin
addr = 0;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0000_0100;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0001_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0010_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0011_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0100_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0101_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0110_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_0111_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_1000_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_1001_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_1010_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_0000_1011_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0000_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0001_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0010_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0011_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0100_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0101_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0110_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_0111_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_1000_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0000_1000_1001_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 32'b0000_0000_0000_0000_0001_0000_0000_0000;
MemWrite = 0;
MemRead = 1;
#20 addr = 5;
datain = 6;
MemWrite = 1;
MemRead = 0;
#20 addr = 1;
datain = 10;
MemWrite = 1;
MemRead = 0;
#20 addr = 8;
datain = 11;
MemWrite = 1;
MemRead = 0;
#20 addr = 5;
datain = 10;
MemWrite = 0;
MemRead = 1;
#20 addr = 1;
datain = 13;
MemWrite = 0;
MemRead = 1;
#20 addr = 8;
datain = 13;
MemWrite = 0;
MemRead = 1;
end
initial
#600 $stop;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_outputcontrol.v,v $
// Revision 1.2 2005/12/13 12:54:49 maverickist
// first simulation passed
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= 1'b0;
MdoEn_d <= 1'b0;
MdoEn <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
MdoEn_d <= MdoEn_2d;
MdoEn <= MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= 1'b0;
Mdo_d <= 1'b0;
Mdo <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= ~SerialEn & BitCounter<32;
Mdo_d <= ShiftedBit | Mdo_2d;
Mdo <= Mdo_d;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300002; int n, m, l[MAXN * 4], r[MAXN * 4], d[MAXN * 4], id[MAXN]; string s; void input() { scanf( %d%d , &n, &m); cin.ignore(1); getline(cin, s); s = 0 + s; } void init(int x, int left, int right) { l[x] = left; r[x] = right; if (left == right) { d[x] = 0; id[left] = x; return; } int mid = (left + right) / 2; init(x * 2, left, mid); init(x * 2 + 1, mid + 1, right); d[x] = d[x * 2] + d[x * 2 + 1]; if (s[mid] == . && s[mid + 1] == . ) d[x]++; } void update(int a) { int x = id[a]; x /= 2; while (x > 0) { d[x] = d[x * 2] + d[x * 2 + 1]; if (s[r[x * 2]] == . && s[l[x * 2 + 1]] == . ) d[x]++; x /= 2; } } int main() { input(); init(1, 1, n); int a; char b; for (int q = 1; q <= m; q++) { scanf( %d %c , &a, &b); if ((s[a] == . && b == . ) || (s[a] != . && b != . )) { printf( %d n , d[1]); continue; } s[a] = b; update(a); printf( %d n , d[1]); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: cont_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module cont_test #(parameter W=4)(
//INPUTS
input wire clk,
input wire rst,
input wire load,
input wire enable,
input wire [W-1:0] d,
//OUTPUTS
output wire max_tick,
output wire min_tick,
output wire [W-1:0] q
);
reg [W-1:0] count;
always @(posedge clk, posedge rst)
begin
if (rst)
count <= 0;
else if (enable)
begin
if (load)
begin
count <= d;
end
else
count <= count + 1'b1;
end
end
assign q = count;
assign max_tick = (count == 2**W-1) ? 1'b1 : 1'b0;
assign min_tick = (count == 0) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int nmax = 1e5 + 42; int n; long long k; int arr[nmax]; void compress() { set<int> seen = {}; for (int i = 1; i <= n; i++) seen.insert(arr[i]); map<int, int> c = {}; int val = 0; for (auto k : seen) { val++; c[k] = val; } for (int i = 1; i <= n; i++) arr[i] = c[arr[i]]; } int fenwick[nmax][2]; int sum(int pos, int index) { int ret = 0; while (pos) { ret = ret + fenwick[pos][index]; pos = pos - (pos & (-pos)); } return ret; } int query(int l, int r, int index) { return sum(r, index) - sum(l - 1, index); } void update(int pos, int add, int index) { while (pos <= n) { fenwick[pos][index] += add; pos = pos + (pos & (-pos)); } } int main() { scanf( %i%lld , &n, &k); for (int i = 1; i <= n; i++) scanf( %i , &arr[i]); compress(); int r = n + 1; long long now = 0; while (r > 1 && now <= k) { r--; now = now + query(1, arr[r] - 1, 1); if (now > k) { now = now - query(1, arr[r] - 1, 1); r++; break; } update(arr[r], 1, 1); } long long ans = 0; for (int l = 1; l < n; l++) { now = now + query(arr[l] + 1, n, 0) + query(1, arr[l] - 1, 1); update(arr[l], 1, 0); while (l >= r || (now > k && r <= n)) { now = now - query(arr[r] + 1, n, 0) - query(1, arr[r] - 1, 1); update(arr[r], -1, 1); r++; } ans = ans + (n - r + 1); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) const int N = 4040; using namespace std; int n, m; int l[N], s[N]; int cost[N]; int inf = -1e9; int d[N][N]; int f[N][N]; vector<int> v[N]; vector<int> pos[N]; vector<int> fut[N][14]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> l[i]; for (int i = 1; i <= n; i++) cin >> s[i]; reverse(l + 1, l + n + 1); reverse(s + 1, s + n + 1); for (int i = 1; i <= n + m; i++) cin >> cost[i]; for (int i = 1; i <= n; i++) v[l[i]].push_back(i); for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) d[i][j] = inf; for (int i = 1; i <= n + m; i++) { for (int j = 0; j < 13; j++) { fut[i][j].resize((1 << 13 - j)); while (fut[i][j].size() >= N - 4) fut[i][j].pop_back(); for (auto &x : fut[i][j]) x = inf; } } for (int i = 0; i < N; i++) { for (int j = 1; j <= n + m; j++) { f[i][j] = cost[j]; for (int h = 0; h < 13; h++) { if (i & (1 << h)) f[i][j] += cost[j + h + 1]; else break; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= l[i]; j++) { int dif = min(12, l[i] - j); for (int p = 0; p < fut[j][dif].size(); p++) { d[p + 1][i] = max(d[p + 1][i], fut[j][dif][p] + f[p][l[i]] - s[i]); } } d[1][i] = max(d[1][i], cost[l[i]] - s[i]); for (int j = 0; j < N; j++) { int nj = j, x = l[i]; for (int h = 0; h < 13; h++) { fut[x][h][nj] = max(fut[x][h][nj], d[j][i]); nj >>= 1; } } } int res = 0; for (int i = 0; i < N; i++) { for (int j = 1; j <= n; j++) { res = max(res, d[i][j]); } } cout << res << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y) { int temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else return x * temp * temp; } long long int fun(long long int n) { if (n == 0) return 0; else { return n % 10 + fun(n / 10); } } int main() { long long int t; cin >> t; for (int _ = 0; _ < t; _++) { long long int n, k, a, b; cin >> k >> n >> a >> b; if (k - (n * b) <= 0) cout << -1 n ; else { long long int ans = 0; if ((k - (n * b)) % (a - b) == 0) { ans = ((k - (n * b)) / (a - b)) - 1; } else { ans = (k - (n * b)) / (a - b); } ans = min(n, ans); cout << ans << n ; } } }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fetchtexel #(
parameter depth = 2,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-5-1:0] fetch_adr,
output pipe_stb_o,
input pipe_ack_i,
output [255:0] fetch_dat,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di
);
/* Generate FML requests */
wire fetch_en;
always @(posedge sys_clk) begin
if(sys_rst)
fml_stb <= 1'b0;
else begin
if(fml_ack)
fml_stb <= 1'b0;
if(pipe_ack_o) begin
fml_stb <= pipe_stb_i;
fml_adr <= {fetch_adr, 5'd0};
end
end
end
assign pipe_ack_o = fetch_en & (~fml_stb | fml_ack);
/* Gather received data */
wire fifo_we;
tmu2_fifo64to256 #(
.depth(depth)
) fifo64to256 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.w8avail(fetch_en),
.we(fifo_we),
.wd(fml_di),
.ravail(pipe_stb_o),
.re(pipe_ack_i),
.rd(fetch_dat)
);
reg [1:0] bcount;
assign fifo_we = fml_ack | (|bcount);
always @(posedge sys_clk) begin
if(sys_rst)
bcount <= 2'd0;
else if(fml_ack)
bcount <= 2'd3;
else if(|bcount)
bcount <= bcount - 2'd1;
end
assign busy = pipe_stb_o | fml_stb | fifo_we;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_6to1_sel3_7_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
dout_WIDTH = 32
)(
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [6 : 0] din5,
input [6 : 0] din6,
input [2 : 0] din7,
output [6 : 0] dout);
// puts internal signals
wire [2 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
wire [6 : 0] mux_1_2;
// level 2 signals
wire [6 : 0] mux_2_0;
wire [6 : 0] mux_2_1;
// level 3 signals
wire [6 : 0] mux_3_0;
assign sel = din7;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = (sel[0] == 0)? din5 : din6;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = mux_1_2;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1); const int _ML = 500; const char _inpf[] = ; const char _outf[] = ; template <typename T, typename U> inline ostream &operator<<(ostream &_out, const pair<T, U> &_p) { _out << _p.x << << _p.y; return _out; } template <typename T, typename U> inline istream &operator>>(istream &_in, pair<T, U> &_p) { _in >> _p.x >> _p.y; return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const vector<T> &_v) { if (_v.empty()) return _out; _out << _v.front(); for (auto _it = ++_v.begin(); _it != _v.end(); ++_it) _out << << *_it; return _out; } template <typename T> inline istream &operator>>(istream &_in, vector<T> &_v) { for (auto &_i : _v) _in >> _i; return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const set<T> &_s) { if (_s.empty()) return _out; _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) _out << << *_it; return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const multiset<T> &_s) { if (_s.empty()) return _out; _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) _out << << *_it; return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_set<T> &_s) { if (_s.empty()) return _out; _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) _out << << *_it; return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_multiset<T> &_s) { if (_s.empty()) return _out; _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) _out << << *_it; return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const map<T, U> &_m) { if (_m.empty()) return _out; _out << ( << _m.begin()->x << : << _m.begin()->y << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) _out << , ( << _it->x << : << _it->y << ) ; return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const unordered_map<T, U> &_m) { if (_m.empty()) return _out; _out << ( << _m.begin()->x << : << _m.begin()->y << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) _out << , ( << _it->x << : << _it->y << ) ; return _out; } inline void mainFunction(void) { int n, m, k; cin >> n >> m >> k; vector<string> v(n + 2, string(m + 2, * )); int x = 228, y = 1488 + m + i + s + h + k + a + = + g + a + y ; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> v[i][j]; if (v[i][j] == X ) { v[i][j] = . ; x = i; y = j; } } } const int dx[] = {1, 0, 0, -1}; const int dy[] = {0, -1, 1, 0}; const int N = 1000 * 1000 + 228; vector<vector<int>> d(n + 2, vector<int>(m + 2, N)); static int qx[N]; static int qy[N]; int ql = 0; int qr = 1; qx[0] = x; qy[0] = y; d[x][y] = 0; while (ql != qr) { int xx = qx[ql]; int yy = qy[ql]; ++ql; for (int j = 0; j < 4; ++j) { if (v[xx + dx[j]][yy + dy[j]] == . && d[xx + dx[j]][yy + dy[j]] == N) { d[xx + dx[j]][yy + dy[j]] = d[xx][yy] + 1; qx[qr] = xx + dx[j]; qy[qr] = yy + dy[j]; ++qr; } } } const char c[] = { D , L , R , U }; static char p[228]; p[ U ] = D ; p[ D ] = U ; p[ R ] = L ; p[ L ] = R ; string s; for (int i = 0; i < k; ++i) { int j; for (j = 0; j < 4; ++j) { if (v[x + dx[j]][y + dy[j]] == . && d[x + dx[j]][y + dy[j]] <= k - i - 1) { break; } } if (j == 4) { cout << IMPOSSIBLE << n ; return; } s += c[j]; x += dx[j]; y += dy[j]; } cout << s << n ; } int main() { if (_inpf[0] != 0 ) assert(freopen(_inpf, r , stdin) != nullptr); if (_outf[0] != 0 ) assert(freopen(_outf, w , stdout) != nullptr); cin.tie(nullptr); ios_base::sync_with_stdio(false); cout << setprecision(20); mainFunction(); }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; if (n == 0 || n == 1) { cout << 0 << endl; return; } long long a[n]; vector<int> pos; long long even = n / 2, odds = n - even; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] != 0) { if (a[i] & 1) odds--; else even--; pos.push_back(i); } } if (pos.size() == 0) { cout << 1 << endl; return; } vector<pair<int, int>> good; int bad = 0; for (int i = 1; i < pos.size(); ++i) { if (pos[i] - pos[i - 1] != 1) { if (a[pos[i]] % 2 == a[pos[i - 1]] % 2) { good.push_back({pos[i], pos[i - 1]}); } } if (a[pos[i]] % 2 != a[pos[i - 1]] % 2) bad++; } sort(good.begin(), good.end(), [&](pair<int, int> a, pair<int, int> b) { return a.first - a.second < b.first - b.second; }); long long ans = bad; for (auto i : good) { int k = i.first - i.second - 1; if (a[i.first] & 1 && odds >= k) odds -= k; else if (!(a[i.first] & 1) && even >= k) even -= k; else ans += 2; } if (a[0] == 0) { int cnt = 0; while (a[cnt] == 0) cnt++; if (a[cnt] & 1 && odds >= cnt) odds -= cnt; else if (!(a[cnt] & 1) && even >= cnt) even -= cnt; else ans++; } if (a[n - 1] == 0) { int cnt = 0, i = n - 1; while (a[i] == 0) cnt++, --i; if (!(a[i] & 1 && odds >= cnt || !(a[i] & 1) && even >= cnt)) ans++; } cout << ans << endl; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); }
|
#include <bits/stdc++.h> const double pi = 3.141592653589793238462; const double eps = 1e-10; using namespace std; const int maxn = 100010; int c[maxn]; multiset<int> a; multiset<int> b; multiset<int>::iterator setfloor(int val) { multiset<int>::iterator it = b.upper_bound(val); if (it == b.begin()) it = b.end(); it--; return it; } int main() { int i, j, k, n, m, tc, cnt; ios_base::sync_with_stdio(false); cin >> n >> m; for (i = 0; i < n; i++) { cin >> j; a.insert(j); } for (i = 0; i < n; i++) { cin >> j; b.insert(j); } multiset<int>::iterator ita = --a.end(); multiset<int>::iterator itb, tmp1, tmp2; cnt = 0; int prev; for (i = 0; i < n; i++) { itb = setfloor(m - 1 - *ita); if (itb != b.end() && *itb <= m - 1 - *ita) { c[cnt++] = (*ita + *itb) % m; tmp1 = ita; ita--; a.erase(tmp1); b.erase(itb); } else ita--; } ita = a.end(); itb = b.end(); while (cnt < n) { ita--; itb--; c[cnt++] = (*ita + *itb) % m; } sort(c, c + cnt); for (i = cnt - 1; i >= 0; i--) cout << c[i] << ; cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_TB_V
`define SKY130_FD_SC_HD__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V
|
module jmsflipfloptb;
wire q, qbar;
reg clk,rst;
reg d;
wire qn_1,qn_1bar; // to monitor current q and previous q values
jmsflipflop jmsff(q,qbar,clk,rst,d);
jdflipflop jdff(qn_1,qn_1bar,clk,1'b0,q);
always #5 clk = ~clk;
initial
begin
d = 0; // JUST keep it initialized
clk = 1'b0;
rst = 1; # 20;
$display("INITIALIZING");
$display("RSLT\td\tqn_1\tq");
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
rst = 0; # 20;
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
$display("\nTESTING");
$display("RSLT\td\tqn_1\tq");
d = 0; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
else
$display ("FAIL\t%d\t%d\t%d",d,qn_1,q);
d = 1; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
else
$display ("FAIL\t%d\t%d\t%d",d,qn_1,q);
# 5; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
else
$display ("FAIL\t%d\t%d\t%d",d,qn_1,q);
d = 0; # 5; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
else
$display ("FAIL\t%d\t%d\t%d",d,qn_1,q);
d = 1; # 5; // JUST wait
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",d,qn_1,q);
else
$display ("FAIL\t%d\t%d\t%d",d,qn_1,q);
$finish;
end
endmodule
|
/*************** Code Submitted by Saumya Singh Netaji Subhas University of Technology CF : @saumya_singh203 ****************/ #include <bits/stdc++.h> using namespace std; #define int long long signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long t = 1; cin >> t; while (t--) { int n, m, x, add, r, c; cin >> n >> m >> x; c = (x - 1) / n; r = (x - 1) % n; cout << (r)*m + (c + 1) << endl; } }
|
#include <bits/stdc++.h> const int inf = 1039074182; using namespace std; int n, r, c; string word[1000005]; int len[1000005]; int nxt[1000005]; pair<int, int> st[1000005][22]; int sum[1000005]; int calc(int start) { int res = 0; for (int i = 0; i < 22; i++) { if ((1 << i) & r) { res += st[start][i].second; start = st[start][i].first; } } return res; } void print(int start) { for (int i = 0; i < r; i++) { if (start == n) break; for (int j = start; j < nxt[start]; j++) { cout << word[j]; if (j != nxt[start] - 1) cout << ; } cout << endl; start = nxt[start]; } } int main() { ios_base::sync_with_stdio(false); cin >> n >> r >> c; for (int i = 0; i < n; i++) { cin >> word[i]; len[i] = word[i].size(); } sum[0] = len[0] + 1; for (int i = 1; i < n; i++) { sum[i] = sum[i - 1] + len[i] + 1; } for (int i = 0, j = 0; i < n; i++) { while (j < n && sum[j] - (i ? sum[i - 1] : 0) - 1 <= c) j++; nxt[i] = j; } for (int i = 0; i < n; i++) { st[i][0] = make_pair(nxt[i], nxt[i] - i); } for (int i = 0; i < 22; i++) { st[n][i] = make_pair(n, 0); } for (int k = 1; k < 22; k++) { for (int i = 0; i < n; i++) { st[i][k].first = st[st[i][k - 1].first][k - 1].first; st[i][k].second = st[i][k - 1].second + st[st[i][k - 1].first][k - 1].second; } } int res = -1, maxk = -1; int temp; for (int i = 0; i < n; i++) { temp = calc(i); if (temp > res) { res = temp; maxk = i; } } print(maxk); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Rose-Hulman Institute of Technology
// Tom D'Agostino
// ECE398 CAN Controller Design
//
// Create Date: 21:29:50 04/13/2015
// Module Name: BaudGen
// Project Name: CANBUS
// Target Devices: Nexys 3 running a Xilinx Spartan6 XC6LX16-CS324
// Description: One-shot for the CRC
//////////////////////////////////////////////////////////////////////////////////
module OneShot(
input pulse,
input clk,
input rst,
output reg out
);
initial out = 0;
parameter waiting_l = 2'b00, on = 2'b01, waiting_h = 2'b10;
reg[1:0] next_state, current_state;
always @ (posedge clk or posedge rst) begin
if(rst) begin
current_state <= waiting_l;
end
else begin
current_state <= next_state;
end
end
always @ (current_state or pulse) begin
if(current_state == on) begin
next_state <= waiting_h;
end
else if(current_state == waiting_h) begin
if(pulse) begin
next_state <= waiting_h;
end
else begin
next_state <= waiting_l;
end
end
else if(pulse) begin
next_state<= on;
end
else begin
next_state<= waiting_l;
end
end
always @(current_state or rst) begin
if(rst)
out <= 1'b0;
else if(current_state == on)
out <= 1'b1;
else
out <= 1'b0;
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module ram #(
parameter DATA = 1008,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
initial begin : init
integer i;
for(i = 0; i < (2**ADDR); i = i + 1)
mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; t = 1; while (t--) { long long int n, m; cin >> n >> m; long long int arr[n]; string arr2[m]; for (long long int i = 0; i < n; i++) { cin >> arr[i]; } map<string, int> mp; for (long long int i = 0; i < m; i++) { cin >> arr2[i]; if (mp.find(arr2[i]) != mp.end()) { std::map<string, int>::iterator it = mp.find(arr2[i]); it->second++; } else { mp.insert({arr2[i], 1}); } } sort(arr, arr + n); vector<long long int> freq; for (auto &it : mp) { freq.push_back(it.second); } sort(freq.begin(), freq.end(), greater<long long int>()); long long int ans = 0; long long int ans2 = 0; for (long long int i = 0; i < freq.size(); i++) { ans += freq[i] * arr[i]; ans2 += freq[i] * arr[n - i - 1]; } cout << ans << << ans2 << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<pair<int, int>> ans; for (int c = 1; c < k; c++) { int r = 0; int C = c; while (ans.size() < n) { ans.emplace_back(r + 1, C + 1); if (C == k - 1) break; r++, C++; } r = k - 1; C = k - c - 1; while (ans.size() < n) { ans.emplace_back(r + 1, C + 1); if (C == 0) break; r--, C--; } } if (ans.size() != n) { cout << NO << endl; return (0); } cout << YES << endl; for (auto pp : ans) cout << pp.first << << pp.second << n ; return (0); }
|
//=================================================================
// Copyright(c) Alorium Technology Group Inc., 2016
// ALL RIGHTS RESERVED
// $Id: $
//=================================================================
//
// File name: : xlr8_top.v
// Author : Matt Weber
// Contact :
// Description : Simulation model of components on the XLR8
// board that we'd like to simulate, most importantly
// the XLR8 chip, but also various pullups and
// enables
//
//=================================================================
///////////////////////////////////////////////////////////////////
module xlr8_board #(parameter DESIGN_CONFIG = {28'd0, // 31:4: reserved
1'b1, // [3] : 1 = 16K Instruction, 0 = 8K instruction
2'd0, // [2:1]: clock speed[1:0]
1'b1}, // [0] = CFM FACTORY (1), CFM APPLICATION (0)
parameter APP_XB0_ENABLE = 32'hffff_ffff // for APPLICATION design, each bit [i] enables XB[i]
)
(
//Clock and Reset
input Clock, // 16MHz
input RESET_N,
//Arduino I/Os
inout wire SCL,
inout wire SDA,
inout [13:0] Digital, // Name to match names in original testbench
inout [5:0] Ana_Dig // Name to match names in original testbench
);
wire PIN13LED;
// We can disconnect Ana_Dig from ADC inputs if necessary (don't know if it is) by driving
// OE low. Else leave OE as high-Z (don't drive it high).
wire [5:0] DIG_IO;
wire [5:0] DIG_IO_OE;
wire ANA_UP; // Choose ADC ref between AREF pin and regulated 3.3V
wire I2C_ENABLE; // More importantly; disable pullups when doing analog read on A4/A5
// JTAG connector reused as digial IO. On that connector, pin 4 is power, pins 2&10 are ground
// and pin 8 selects between gpio (low) and jtag (high) modes and has a pulldown.
wire JT9; // external pullup. JTAG function is TDI
wire JT7; // no JTAG function
wire JT6; // no JTAG function
wire JT5; // external pullup. JTAG function is TMS
wire JT3; // JTAG function TDO
wire JT1; // external pulldown, JTAG function is TCK
// Interface to EEPROM or other device in SOIC-8 spot on the board
wire SOIC7; // WP in the case of an 24AA128SM EEPROM
wire SOIC6; // SCL in the case of an 24AA128SM EEPROM
wire SOIC5; // SDA in the case of an 24AA128SM EEPROM
wire SOIC3; // A2 in the case of an 24AA128SM EEPROM
wire SOIC2; // A1 in the case of an 24AA128SM EEPROM
wire SOIC1; // A0 in the case of an 24AA128SM EEPROM
/* xlr8_top AUTO_TEMPLATE (.D\([0-9]*\) (Digital[\1]),
.TX (Digital[1]),
.RX (Digital[0]),
.A\([0-9]*\) (DIG_IO[\1]),
);*/
xlr8_top xlr8_top_inst (
/*AUTOINST*/
// Outputs
.PIN13LED (PIN13LED),
.ANA_UP (ANA_UP),
.I2C_ENABLE (I2C_ENABLE),
// Inouts
.SCL (SCL),
.SDA (SDA),
.D13 (Digital[13]), // Templated
.D12 (Digital[12]), // Templated
.D11 (Digital[11]), // Templated
.D10 (Digital[10]), // Templated
.D9 (Digital[9]), // Templated
.D8 (Digital[8]), // Templated
.D7 (Digital[7]), // Templated
.D6 (Digital[6]), // Templated
.D5 (Digital[5]), // Templated
.D4 (Digital[4]), // Templated
.D3 (Digital[3]), // Templated
.D2 (Digital[2]), // Templated
.TX (Digital[1]), // Templated
.RX (Digital[0]), // Templated
.A5 (DIG_IO[5]), // Templated
.A4 (DIG_IO[4]), // Templated
.A3 (DIG_IO[3]), // Templated
.A2 (DIG_IO[2]), // Templated
.A1 (DIG_IO[1]), // Templated
.A0 (DIG_IO[0]), // Templated
.DIG_IO_OE (DIG_IO_OE[5:0]),
.SOIC7 (SOIC7),
.SOIC6 (SOIC6),
.SOIC5 (SOIC5),
.SOIC3 (SOIC3),
.SOIC2 (SOIC2),
.SOIC1 (SOIC1),
.JT9 (JT9),
.JT7 (JT7),
.JT6 (JT6),
.JT5 (JT5),
.JT3 (JT3),
.JT1 (JT1),
// Inputs
.Clock (Clock),
.RESET_N (RESET_N));
// The digital I/Os will likely always have pullups, either
// on the board (current plan) or in the chip (green board
// prototypes).
pullup(Digital[13]);
pullup(Digital[12]);
pullup(Digital[11]);
pullup(Digital[10]);
pullup(Digital[9]);
pullup(Digital[8]);
pullup(Digital[7]);
pullup(Digital[6]);
pullup(Digital[5]);
pullup(Digital[4]);
pullup(Digital[3]);
pullup(Digital[2]);
pullup(Digital[1]);
pullup(Digital[0]);
// The SDA/SCL pullups can be enabled/disabled
// when I2C_ENABLE is high, we should get pullups,
// when it is low, we should just set high-Z on
// SDA/SCL
rnmos Q19a (SDA,1'b1,I2C_ENABLE); // (r)esistive version of nmos
rnmos Q19b (SCL,1'b1,I2C_ENABLE); // should reduce 1'b1 to pull strength
// DIG_IO_OE are used to disconnect the digital I/O
// side of A5..A0 from the analog input side
// When DIG_IO_OE is 0 they are disconnected, when
// it is high-Z they are connected, when it is a
// 1 they are also connected, but bad, or at least
// unintended things, could happen in the circuits
// because the pullups are to 5V
pullup(DIG_IO_OE[5]);
pullup(DIG_IO_OE[4]);
pullup(DIG_IO_OE[3]);
pullup(DIG_IO_OE[2]);
pullup(DIG_IO_OE[1]);
pullup(DIG_IO_OE[0]);
tranif1(Ana_Dig[0],DIG_IO[0],DIG_IO_OE[0]);
tranif1(Ana_Dig[1],DIG_IO[1],DIG_IO_OE[1]);
tranif1(Ana_Dig[2],DIG_IO[2],DIG_IO_OE[2]);
tranif1(Ana_Dig[3],DIG_IO[3],DIG_IO_OE[3]);
tranif1(Ana_Dig[4],DIG_IO[4],DIG_IO_OE[4]);
tranif1(Ana_Dig[5],DIG_IO[5],DIG_IO_OE[5]);
endmodule: xlr8_board
// Local Variables:
// verilog-library-flags:("-y ../../../rtl/")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, i; scanf( %d %d , &n, &t); if (n == 1 && t == 10) { printf( -1 n ); } else { if (t == 10) { t = 1; } printf( %d , t); for (i = 0; i < n - 1; i++) { printf( 0 ); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; int n, k; bool check(long long m) { long long sum = 0; for (int i = n / 2; i < n; i++) { sum += max(m - v[i], 0ll); } if (sum <= k) { return true; } return false; } int main() { cin >> n >> k; v.resize(n); for (int i = 0; i < n; i++) { cin >> v[i]; } sort(v.begin(), v.end()); long long l = v[n / 2]; long long r = 1e10; while (l + 1 < r) { long long m = (l + r) / 2; if (check(m)) { l = m; } else { r = m; } } cout << l; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000LL * 1000000LL * 1000000LL; int n, k; int tyl, l, sum; int T[1000][1000]; int main() { scanf( %d %d , &n, &k); tyl = n * n; for (int i = 1; i <= n; i++) { for (int j = n; j >= k; j--) { T[i][j] = tyl; tyl--; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (j == k) { sum += T[i][j]; } if (T[i][j] == 0) { l++; T[i][j] = l; } } } printf( %d n , sum); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { printf( %d , T[i][j]); } printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 9; const int MOD = 1e9 + 7; const int MAXN = 300005; long long N, k, m; long long cook[MAXN], t[MAXN], l[MAXN]; vector<int> ch[MAXN]; int good, bad; template <class T, class Operation = plus<T>> struct SegmentTree { int n; vector<T> st; Operation op; const T identity; T query(int L, int R) { T resl = identity, resr = identity; for (L += n, R += n; L < R; L >>= 1, R >>= 1) { if (L & 1) resl = op(resl, st[L++]); if (R & 1) resr = op(st[--R], resr); } return op(resl, resr); } void update(int p, T val) { for (st[p += n] = val; p > 1; p >>= 1) st[p >> 1] = op(st[p], st[p ^ 1]); } SegmentTree(const vector<T> &A, const T &identity = 0, const Operation &op = Operation()) : n((int)A.size()), st(n << 1), op(op), identity(identity) { copy(A.begin(), A.end(), st.begin() + n); for (int i = n - 1; i > 0; --i) st[i] = this->op(st[i << 1], st[i << 1 | 1]); } }; struct Op { pair<long long, long long> operator()(const pair<long long, long long> &a, const pair<long long, long long> &b) { return pair<long long, long long>(a.first + b.first, a.second + b.second); } }; SegmentTree<pair<long long, long long>, Op> st( vector<pair<long long, long long>>(1000006), pair<long long, long long>(0, 0)); long long calc(int u) { pair<long long, long long> val = st.query(t[u], t[u] + 1); st.update(t[u], st.op(val, pair<long long, long long>(cook[u], cook[u] * t[u]))); long long maxi1 = 0, maxi2 = 0; for (int i = 0; i < (int)ch[u].size(); i++) { if (k - l[ch[u][i]] >= 0) { k -= l[ch[u][i]]; long long chdp = calc(ch[u][i]); if (chdp > maxi1) { maxi2 = maxi1; maxi1 = chdp; } else if (chdp > maxi2) { maxi2 = chdp; } k += l[ch[u][i]]; } } int lo = 0, hi = min(k + 2, (long long)1000004); while (lo + 1 < hi) { int med = lo + (hi - lo) / 2; pair<long long, long long> sum = st.query(0, med); if (sum.second > k) { hi = med; } else { lo = med; } } pair<long long, long long> sum = st.query(0, lo); long long f = sum.first; if (lo > 0) f += min((k - sum.second) / lo, st.st[st.n + lo].first); st.update(t[u], val); if (u == 0) { return max(f, maxi1); } else { return max(f, maxi2); } } int main() { cin >> N >> k; for (int i = 0; i < N; i++) { cin >> cook[i]; } for (int i = 0; i < N; i++) { cin >> t[i]; } for (int i = 1; i < N; i++) { cin >> m >> l[i]; l[i] *= 2; ch[m - 1].push_back(i); } cout << calc(0) << endl; }
|
#include <bits/stdc++.h> using namespace std; int tree[4 * 200005]; void update(int n, int st, int en, int index, int val) { if (st == en) { tree[n] = val; return; } int mid = (st + en) / 2, lc = 2 * n, rc = lc + 1; if (index <= mid) update(lc, st, mid, index, val); else update(rc, mid + 1, en, index, val); tree[n] = max(tree[lc], tree[rc]); } int query(int n, int st, int en, int l, int r) { if (r < st || en < l) return 0; if (l <= st && en <= r) return tree[n]; int mid = (st + en) / 2, lc = 2 * n, rc = lc + 1; return max(query(lc, st, mid, l, r), query(rc, mid + 1, en, l, r)); } vector<int> pos[200005 + 5]; int main() { int n, inp; scanf( %d , &n); int mx = 0; for (int i = 1; i < n + 1; i++) { scanf( %d , &inp); pos[inp].push_back(i); } for (int num = 1; num < 200005; num++) { reverse(pos[num].begin(), pos[num].end()); for (auto position : pos[num]) { if (position < num) continue; int highestDeletePossible = position - num; int maxAns = query(1, 0, 200005, 0, highestDeletePossible) + 1; update(1, 0, 200005, highestDeletePossible, maxAns); } } cout << query(1, 0, 200005, 0, 200005) << n ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback () ////
//// - Julius Baxter () ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom
#(parameter addr_width = 5,
parameter b3_burst = 0)
(
input wb_clk,
input wb_rst,
input [(addr_width+2)-1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o);
reg [addr_width-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
`ifdef (b3_burst)
case (adr)
`else
case(wb_adr_i)
`endif
/* // Zero r0 and endless loop
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h00000000;
4 : wb_dat_o <= 32'h15000000;
*/
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
default:
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if(b3_burst) begin : gen_b3_burst
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(addr_width+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q; struct matrix { int val; } matr[109][109]; matrix* mat[109][109]; int main() { scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { matr[i][j].val = 0; mat[i][j] = &matr[i][j]; } int t1, t2, t3, t4, t5; matrix* tmp; for (int i = 0; i < q; i++) { scanf( %d , &t1); if (t1 == 1) { scanf( %d , &t2); tmp = mat[t2][1]; for (int j = 1; j < m; j++) { mat[t2][j] = mat[t2][j + 1]; } mat[t2][m] = tmp; } else if (t1 == 2) { scanf( %d , &t2); tmp = mat[1][t2]; for (int i = 1; i < n; i++) { mat[i][t2] = mat[i + 1][t2]; } mat[n][t2] = tmp; } else if (t1 == 3) { scanf( %d %d %d , &t3, &t4, &t5); mat[t3][t4]->val = t5; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { printf( %d , matr[i][j].val); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( -funroll-loops ) #pragma GCC target( avx,sse4 ) using namespace std; const int P = 1e9 + 7, i2 = P / 2 + 1, i6 = P / 6 + 1, N = 1e6 + 5; long long n, m; int r, f1[N], f2[N], f3[N]; int main() { scanf( %lld , &n); long long g1 = (n + 1) % P, g3 = (long long)g1 * g1 % P * g1 % P; while ((long long)m * m <= n) m++; m--; for (register int i = 1, _lim_ = m; i <= _lim_; i++) { long long v1 = (long long)i * i % P, v2 = (long long)v1 * v1 % P, v3 = (long long)v1 * v2 % P; f1[i] = (f1[i - 1] + v1) % P; f2[i] = (f2[i - 1] + v2) % P; f3[i] = (f3[i - 1] + v3) % P; } for (register int x = 0, _lim_ = m; x <= _lim_; x++) { long long s = 0, v1 = (long long)x * x % P, v2 = (long long)v1 * v1 % P, v3 = (long long)v1 * v2 % P; while ((long long)x * x + (long long)m * m > n) m--; s = ((g3 + g1 * (3 * v1 - 3 * v2 - 1) + v1 - v2 * 3 + v3 * 2) % P * (m + 1) % P + (3 * g1 + 1 - (3 * g1 + 3) * v1 * 2 + v2 * 6) % P * f1[m] % P + 3 * (v1 * 2 - g1 - 1) * f2[m] + 2 * f3[m]) % P; s = (s * 2 - g3 + g1 - v1 * (3 * g1 + 1) + v2 * (3 * g1 + 3) - v3 * 2) % P; r = (r + s * (1 << (x > 0))) % P; } r = (long long)r * i6 % P; if (r < 0) r += P; printf( %d n , r); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 02:44:49 PM
// Design Name:
// Module Name: stego_decode
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module stego_decode(clk, rst, start, data_in, message, rdy);
output rdy, message;
input clk, rst, start;
input [7:0] data_in;
wire rdy;
wire message;
wire [11:0] dct;
// asserted when dct is ready
wire rdy_i;
// dct out signal delayed by one
reg rdy_i_d1;
// dct out signal delyed by two
reg rdy_i_d2;
// dct out signal delayed by three
reg rdy_i_d3;
reg signed [8:0] Q_1 = {9'd228};
reg signed [11:0] dct_signed;
reg signed [20:0] dct_q_i_0;
reg signed [20:0] dct_q_i_1;
reg signed [8:0] dct_q_i_2;
reg signed [8:0] dct_q_i_3;
// qunatized dct coifficient
reg signed [8:0] dct_q;
reg signed data_out;
reg data_out_rdy;
// counter of input blocks
reg [5:0] cnt;
reg [18:0] lfsr_1;
reg [21:0] lfsr_2;
reg [22:0] lfsr_3;
wire lfsr_out;
always @(posedge clk) begin
if (rst) begin
rdy_i_d1 <= 0;
rdy_i_d2 <= 0;
rdy_i_d3 <= 0;
end
else begin
rdy_i_d1 <= rdy_i;
rdy_i_d2 <= rdy_i_d1;
rdy_i_d3 <= rdy_i_d2;
end
end
always @(*) begin
dct_q_i_0 = dct_signed*Q_1;
dct_q_i_1 = dct_q_i_0[20] == 1 ? ~dct_q_i_0+1 : dct_q_i_0;
dct_q_i_2 = dct_q_i_1[11] == 1 ? dct_q_i_1[20:12]+12'd1 : dct_q_i_1[20:12];
dct_q_i_3 = dct_q_i_0[20] == 1 ? ~dct_q_i_2+1 : dct_q_i_2;
end
always @(posedge clk) begin
if (rst) begin
dct_signed <= 0;
end
else begin
if (rdy_i) begin
dct_signed <= dct;
end
end
end
always @(posedge clk) begin
if (rst) begin
dct_q <= 0;
end
else begin
if (rdy_i_d1) begin
dct_q <= dct_q_i_3;
end
end
end
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
end
else begin
if (rdy_i_d2) begin
cnt <= cnt + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
data_out <= 0;
data_out_rdy <= 0;
end
else begin
if (rdy_i_d2) begin
if (cnt == 6'd42) begin
data_out_rdy <= 1;
end
else begin
data_out_rdy <= 0;
end
data_out <= (cnt == 6'd42 ? dct_q[0]^lfsr_out : 1'b0);
end
end
end
assign message = data_out;
assign rdy = data_out_rdy;
assign lfsr_out = lfsr_1[18] ^ lfsr_2[21] ^ lfsr_3[22];
always @(posedge clk) begin
if (rst) begin
lfsr_1 <= 19'd1876;
lfsr_2 <= 22'd20007;
lfsr_3 <= 23'd14376;
end
else begin
if (rdy) begin
lfsr_1 <= {lfsr_1[17:0], lfsr_1[18]^lfsr_1[17]^lfsr_1[16]^lfsr_1[13]};
lfsr_2 <= {lfsr_2[20:0], lfsr_2[21]^lfsr_2[20]};
lfsr_3 <= {lfsr_3[21:0], lfsr_3[22]^lfsr_3[21]^lfsr_3[20]^lfsr_3[7]};
end
end
end
MDCT dct_5 (.clk(clk), .rst(rst), .dcti(data_in), .idv(start), .odv(rdy_i), .dcto(dct));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha9d3a7a69d2bea75
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [2:0] in;
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|
module LCDDisplay(clk_i, func_i, data_i, en_o, func_o, data_o);
input clk_i;
input [2:0] func_i;
input [127:0] data_i; // array of 16 chars
reg [7:0] data_c [0:31];
// consult LCD's datasheet about the output format
output reg en_o;
output [1:0] func_o;
output [7:0] data_o;
reg [1:0] func_o_0;
reg [1:0] func_o_1;
assign func_o = func_o_0 | func_o_1;
reg [7:0] data_o_0;
reg [7:0] data_o_1;
assign data_o = data_o_0 | data_o_1;
`define IDLE 1'b0
`define BUSY 1'b1
`define SPACE 8'b00100000
integer i;
reg state;
reg [1:0] lcd_clr_state;
integer lcd_clr_cyc;
reg [2:0] lcd_wrt_state;
integer lcd_wrt_cyc;
reg [6:0] ddram_addr;
integer cursor_pos;
initial begin
state = `BUSY;
for (i = 0; i < 31; i = i + 1) begin
data_c[i] = `SPACE;
end
en_o = 0;
func_o_0 = 2'b00;
func_o_1 = 2'b00;
data_o_0 = 8'b0;
data_o_1 = 8'b0;
lcd_clr_state = 2'b00;
lcd_wrt_state = 3'b000;
state = `IDLE;
end
`define NOP 3'b000
`define K0 3'b100
`define K1 3'b101
`define K2 3'b110
`define K3 3'b111
`define EN_PULSE_WIDTH 20
always@(negedge clk_i) begin
if (state == `IDLE) begin
case (func_i)
`K0: begin
for (i = 0; i < 31; i = i + 1) begin
data_c[i] <= `SPACE;
end
lcd_clr_state <= 2'b01;
state <= `BUSY;
end
`K2: begin
for (i = 0; i < 16; i = i + 1) begin
data_c[i + 16] <= data_c[i];
end
data_c[0] <= data_i[7:0];
data_c[1] <= data_i[15:8];
data_c[2] <= data_i[23:16];
data_c[3] <= data_i[31:24];
data_c[4] <= data_i[39:32];
data_c[5] <= data_i[47:40];
data_c[6] <= data_i[55:48];
data_c[7] <= data_i[63:56];
data_c[8] <= data_i[71:64];
data_c[9] <= data_i[79:72];
data_c[10] <= data_i[87:80];
data_c[11] <= data_i[95:88];
data_c[12] <= data_i[103:96];
data_c[13] <= data_i[111:104];
data_c[14] <= data_i[119:112];
data_c[15] <= data_i[127:120];
cursor_pos <= 0;
ddram_addr <= 7'b0000000;
lcd_wrt_state <= 3'b001;
state <= `BUSY;
end
endcase
end else begin
// BUSY state
case (lcd_clr_state)
2'b00: begin
// DO NOTHING
end
2'b01: begin
en_o <= 1;
func_o_0 <= 2'b00;
data_o_0 <= 8'b00000001;
lcd_clr_state <= 2'b10;
lcd_clr_cyc <= 0;
end
2'b10: begin
if (lcd_clr_cyc != 8000) begin
if (lcd_clr_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_clr_cyc <= lcd_clr_cyc + 1;
end else begin
data_o_0 <= 8'b0;
func_o_0 <= 2'b00;
lcd_clr_state <= 2'b00;
state <= `IDLE;
end
end
endcase
case (lcd_wrt_state)
3'b000: begin
// DO NOTHING
end
3'b001: begin
if (ddram_addr == 7'h50) begin
data_o_1 <= 8'b0;
func_o_1 <= 2'b00;
lcd_wrt_state <= 3'b000;
state <= `IDLE;
end else begin
en_o <= 1;
func_o_1 <= 2'b00;
data_o_1 <= {1'b1, ddram_addr};
if (ddram_addr == 7'h0F) begin
ddram_addr <= 7'h40;
end else begin
ddram_addr <= ddram_addr + 7'b1;
end
lcd_wrt_state <= 3'b010;
lcd_wrt_cyc <= 0;
end
end
3'b010: begin
if (lcd_wrt_cyc != 250) begin
if (lcd_wrt_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_wrt_cyc <= lcd_wrt_cyc + 1;
end else begin
lcd_wrt_state <= 3'b011;
end
end
3'b011: begin
en_o <= 1;
func_o_1 <= 2'b10;
data_o_1 <= data_c[cursor_pos];
cursor_pos <= cursor_pos + 1;
lcd_wrt_state <= 3'b100;
lcd_wrt_cyc <= 0;
end
3'b100: begin
if (lcd_wrt_cyc != 250) begin
if (lcd_wrt_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_wrt_cyc <= lcd_wrt_cyc + 1;
end else begin
lcd_wrt_state <= 3'b001;
end
end
endcase
end
end
endmodule
|
//----------------------------------------------------------------------------
//-- Limitaciones en la sintesis de puertas triestado
//-- Error 1: Conexion de un registro de 2 bits a traves de una
//-- puerta triestado
//----------------------------------------------------------------------------
//-- (C) BQ. November 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
/*
Al sintetizarlo con make sint3, se obtiene un error:
...
2.12.2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
Mapping error1.$ternary$error1.v:29$2 ($tribuf) with simplemap.
terminate called after throwing an instance of 'std::out_of_range'
what(): vector::_M_range_check: __n (which is 1) >= this->size() (which is 1)
Aborted (core dumped)
Makefile:143: recipe for target 'error1.bin' failed
make: *** [error1.bin] Error 134
*/
`default_nettype none
module error1 (
input wire clk, //-- Entrada de reloj
output wire [1:0] leds); //-- Leds a controlar
wire ena = 1'b1;
//-- Registro de 2 bits
reg [1:0] reg1;
//-- Cargar el registro con valor inicial
always @(posedge clk)
reg1 <= 2'b11;
//-- Conectar el registro a 2 leds
assign leds = (ena) ? reg1 : 2'bzz;
endmodule
|
//****************************************************************************/
// AMBA Components
// RTL IMPLEMENTATION, Synchronous Version
//
// Copyright (C) yyyy Ronan Barzic -
// Date : Mon Nov 9 09:47:28 2015
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : ahb_to_ssram.v
//
// Description : A simple AHB to Synchronous SRAM interface
// AHB interface is modeled according to cmsdk_ahb_ram_beh.v
//
//
//****************************************************************************/
module ahb_to_ssram (/*AUTOARG*/
// Outputs
HREADYOUT, HRDATA, HRESP, ahb_sram_addr, ahb_sram_en, ahb_sram_enb,
ahb_sram_wb, ahb_sram_we, ahb_sram_din,
// Inputs
HCLK, HRESETn, HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY,
sram_ahb_dout
);
parameter AW = 12;
`include "ahb_params.v"
localparam AHB_ADDRESS_PHASE = 1;
localparam AHB_DATA_PHASE = 2;
localparam AHB_IDLE_PHASE = 0;
// AHB interface
input wire HCLK; // Clock
input wire HRESETn; // Reset
input wire HSEL; // Device select
input wire [AW-1:0] HADDR; // Address
input wire [1:0] HTRANS; // Transfer control
input wire [2:0] HSIZE; // Transfer size
input wire HWRITE; // Write control
input wire [31:0] HWDATA; // Write data
input wire HREADY; // Transfer phase done
output reg HREADYOUT; // Device ready
output wire [31:0] HRDATA; // Read data output
output wire HRESP; // Device response (always OKAY)
// Synchronous SRAM connections
output [AW-1:0] ahb_sram_addr;
output ahb_sram_en;
output [3:0] ahb_sram_enb;
output [3:0] ahb_sram_wb;
output ahb_sram_we;
input [31:0] sram_ahb_dout;
output [31:0] ahb_sram_din;
reg [3:0] byte_sel_a;
reg [3:0] byte_sel_r;
reg data_phase_r;
reg write_en_r;
reg [AW-1:0] haddr_r;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
//assign seq_cycle = (HTRANS[1:0] == AMBA_AHB_HTRANS_SEQ[1:0]);
//assign nonseq_cycle = (HTRANS[1:0] ==AMBA_AHB_HTRANS_NONSEQ);
//
//
//assign busy_cycle = (HTRANS==AMBA_AHB_HTRANS_BUSY);
//assign idle_cycle = (HTRANS==AMBA_AHB_HTRANS_IDLE);
reg seq_cycle;
reg nonseq_cycle;
reg busy_cycle;
reg idle_cycle;
always @* begin
seq_cycle = 0;
nonseq_cycle = 0;
busy_cycle = 0;
idle_cycle = 0;
case(HTRANS[1:0])
AMBA_AHB_HTRANS_SEQ : begin
seq_cycle = 1'b1;
end
AMBA_AHB_HTRANS_NON_SEQ : begin
nonseq_cycle = 1'b1;
end
AMBA_AHB_HTRANS_BUSY : begin
busy_cycle = 1'b1;
end
AMBA_AHB_HTRANS_IDLE : begin
idle_cycle = 1'b1;
end
endcase
end
assign active_cycle = seq_cycle || nonseq_cycle;
assign read_valid = active_cycle & HSEL & HREADY & (~HWRITE);
assign write_valid = active_cycle & HSEL & HREADY & HWRITE;
assign rw_cycle = read_valid | write_valid;
always @(/*AUTOSENSE*/HADDR or HSIZE or rw_cycle) begin
/*AUTO_CONSTANT ( AMBA_AHB_HSIZE_16BITS AMBA_AHB_HSIZE_32BITS AMBA_AHB_HSIZE_8BITS) */
byte_sel_a = 4'b1111;
if (rw_cycle) begin
case(HSIZE[2:0])
AMBA_AHB_HSIZE_8BITS : begin
case(HADDR[1:0])
0 : begin
byte_sel_a = 4'b0001;
end
1 : begin
byte_sel_a = 4'b0010;
end
2 : begin
byte_sel_a = 4'b0100;
end
3 : begin
byte_sel_a = 4'b1000;
end
default: begin
end
endcase
end
AMBA_AHB_HSIZE_16BITS : begin
byte_sel_a = HADDR[1] ? 4'b1100 : 4'b0011;
end
AMBA_AHB_HSIZE_32BITS : begin
byte_sel_a = 4'b1111;
end
default: begin
byte_sel_a = 4'b1111;
end
endcase
end
end
always @(posedge HCLK or negedge HRESETn) begin
if(HRESETn == 1'b0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
byte_sel_r <= 4'h0;
haddr_r <= {AW{1'b0}};
write_en_r <= 1'h0;
// End of automatics
end
else begin
if(HREADY && HREADYOUT) begin
byte_sel_r <= byte_sel_a;
write_en_r <= write_valid;
haddr_r <= HADDR; // Could be optimize (?)
end
end
end
always @(posedge HCLK or negedge HRESETn) begin
if(HRESETn == 1'b0) begin
HREADYOUT <= 1'b1;
/*AUTORESET*/
end
else begin
HREADYOUT <= !(write_en_r & read_valid);
end
end
assign ahb_sram_addr = write_en_r ? haddr_r : HADDR;
assign ahb_sram_en = read_valid | write_en_r;
assign ahb_sram_we = write_en_r;
// Write cycle followed by a read cycle -> we must wait
assign ahb_sram_wb = byte_sel_r & {4{write_en_r}};
assign ahb_sram_enb = byte_sel_r & {4{ahb_sram_en}};
assign ahb_sram_din = HWDATA;
assign HRDATA = sram_ahb_dout;
assign HRESP = 1'b0;
endmodule // ahb_to_ssram
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T abs(T &a) { return a > 0 ? a : -a; } template <class T> inline T min(T &a, T &b) { return a < b ? a : b; } template <class T> inline T max(T &a, T &b) { return a > b ? a : b; } inline void read(int &x) { char ch; while ((ch = getchar()) && !(ch >= 0 && ch <= 9 )) ; x = ch - 0 ; while ((ch = getchar()) && (ch >= 0 && ch <= 9 )) x = x * 10 + ch - 0 ; } const int N = 2000002; int n, m, w[N], ans[N], dy[N], T = 1, t[N << 2]; void add(int x, int c) { for (t[x += T] += c, x >>= 1; x; x >>= 1) t[x] = t[x << 1] + t[(x << 1) + 1]; } int find(int k, int l, int r) { int x = 1; while (l < r) { int mid = l + r >> 1; if (t[x << 1] >= k) x = x << 1, r = mid; else k -= t[x << 1], x = x << 1 | 1, l = mid + 1; } return l; } int main() { read(n); read(m); int Len = n + m, gs = 0; while (T < Len) T <<= 1, gs++; T--; for (int i = m + 1; i <= n + m; i++) w[i] = i - m, add(i, 1); int x, y; for (int i = m; i >= 1; i--) { read(x); read(y); int p = find(y, 1, T + 1); w[i] = w[p]; add(i, 1); add(p, -1); if (ans[w[i]] && ans[w[i]] != x) { puts( -1 ); return 0; } ans[w[i]] = x; if (dy[x] && dy[x] != w[i]) { puts( -1 ); return 0; } dy[x] = w[i]; } int j = 1; for (int i = 1; i <= n; i++) { if (ans[i]) printf( %d , ans[i]); else { for (; dy[j]; j++) ; printf( %d , j++); } } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; const int inf = (int)1e9; const int mod = inf + 7; const double eps = 1e-9; const double pi = acos(-1.0); int n; string second; int a[100]; vector<int> g[202]; int dp[77][77][77][4]; int calc(vector<int> &a, int n, vector<int> &b, int m, vector<int> &c, int k) { n = a.size() - n; m = (int)b.size() - m; k = (int)c.size() - k; int x = a[n]; int cnt = 0; for (int i = m; i < b.size(); i++) if (b[i] < x) cnt++; for (int i = k; i < c.size(); i++) if (c[i] < x) cnt++; return cnt; } int get(int a, int b, int c, int ty) { if (a + b + c == 0) return 0; int &res = dp[a][b][c][ty]; if (res != -1) return res; res = inf; if (a > 0) { if (ty != 1) res = min(res, get(a - 1, b, c, 0) + calc(g[0], a, g[1], b, g[2], c)); } if (b > 0) { res = min(res, get(a, b - 1, c, 1) + calc(g[1], b, g[0], a, g[2], c)); } if (c > 0) { res = min(res, get(a, b, c - 1, 2) + calc(g[2], c, g[1], b, g[0], a)); } return res; } int main() { cin >> n >> second; for (int i = 0; i < n; i++) { if (second[i] == V ) a[i] = 1; else if (second[i] == K ) a[i] = 0; else a[i] = 2; g[a[i]].push_back(i); } memset(dp, -1, sizeof dp); cout << get(g[0].size(), g[1].size(), g[2].size(), 3) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Amulet { char p[2][2]; void Read() { cin >> p[0][0] >> p[0][1] >> p[1][0] >> p[1][1]; } Amulet Rotate() const { Amulet ret(*this); ret.p[0][0] = this->p[0][1]; ret.p[0][1] = this->p[1][1]; ret.p[1][0] = this->p[0][0]; ret.p[1][1] = this->p[1][0]; return ret; } }; bool Equiv(Amulet const& a1, Amulet const& a2) { return a1.p[0][0] == a2.p[0][0] && a1.p[0][1] == a2.p[0][1] && a1.p[1][0] == a2.p[1][0] && a1.p[1][1] == a2.p[1][1]; } bool operator==(Amulet const& a1, Amulet const& a2) { Amulet tmp(a1); for (int i = 0; i < 4; ++i) { if (Equiv(tmp, a2)) return true; tmp = tmp.Rotate(); } return false; } int main() { vector<Amulet> v; int n; cin >> n; for (int i = 0; i < n; ++i) { Amulet a; a.Read(); vector<Amulet>::iterator it = find(v.begin(), v.end(), a); if (it == v.end()) { v.push_back(a); } char dummy; cin >> dummy >> dummy; } cout << v.size() << endl; }
|
module BigSDRAMFPGA(clock,reset,leds,ddr_clk,ddr_clkn,ddr_cke,ddr_csn,ddr_rasn,ddr_casn,ddr_wen,ddr_ba,ddr_addr,ddr_dm,ddr_dq,ddr_dqs);
input wire clock;
input wire reset;
output wire [7:0] leds;
output wire ddr_clk;
output wire ddr_clkn;
output wire ddr_cke;
output wire ddr_csn;
output wire ddr_rasn;
output wire ddr_casn;
output wire ddr_wen;
output wire [1:0] ddr_ba;
output wire [12:0] ddr_addr;
output wire [1:0] ddr_dm;
inout wire [15:0] ddr_dq;
inout wire [1:0] ddr_dqs;
wire cm1_locked;
wire cm1_clock0;
wire cm1_clock180;
wire cm1_clock270;
wire cm1_clock2x0;
wire cm2_locked;
wire cm2_clock0;
wire cm2_clock90;
wire cm2_clock180;
wire cm2_clock270;
assign ddr_clk = cm2_clock0;
assign ddr_clkn = cm2_clock180;
ClockManager #(.ExternalFeedBack(0))
cm1 (.clock(clock),
.reset(reset),
.locked(cm1_locked),
.clock0(cm1_clock0),
.clock180(cm1_clock180),
.clock270(cm1_clock270),
.clock2x(cm1_clock2x0));
ClockManager #(.ExternalFeedBack(0))
cm2 (.clock(cm1_clock2x0),
.reset(reset & cm1_locked),
.locked(cm2_locked),
.clock0(cm2_clock0),
.clock90(cm2_clock90),
.clock180(cm2_clock180),
.clock270(cm2_clock270));
BigSDRAM
bigsdram (.clock0(cm1_clock0),
.clock180(cm1_clock180),
.clock270(cm1_clock270),
.reset(reset & cm1_locked & cm2_locked),
.leds(leds),
.ddr_clock0(cm2_clock0),
.ddr_clock90(cm2_clock90),
.ddr_clock270(cm2_clock270),
.ddr_cke(ddr_cke),
.ddr_csn(ddr_csn),
.ddr_rasn(ddr_rasn),
.ddr_casn(ddr_casn),
.ddr_wen(ddr_wen),
.ddr_ba(ddr_ba),
.ddr_addr(ddr_addr),
.ddr_dm(ddr_dm),
.ddr_dq(ddr_dq),
.ddr_dqs(ddr_dqs));
endmodule // BigSDRAMFPGA
|
#include <bits/stdc++.h> using namespace std; struct Query { int prefixe, nombre; int id; bool operator<(const Query& autre) const { return prefixe < autre.prefixe; } }; const int MAXP = 20; const int MAXN = 100 * 1000 + 10; const int MOD = 1000 * 1000 * 1000 + 7; bool prise[MAXP]; int puissance[MAXN]; int iConcerne[MAXP]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); puissance[0] = 1; for (int i = 1; i < MAXN; i++) { puissance[i] = (puissance[i - 1] * 2) % MOD; } int nbNombres, nbQuestions; cin >> nbNombres >> nbQuestions; int nombres[nbNombres]; for (int i = 0; i < nbNombres; i++) { cin >> nombres[i]; } Query questions[nbQuestions]; int solution[nbQuestions]; for (int i = 0; i < nbQuestions; i++) { cin >> questions[i].prefixe >> questions[i].nombre; questions[i].prefixe--; questions[i].id = i; } sort(questions, questions + nbQuestions); int inQuestion = 0; int nbPris = 0; for (int iN = 0; iN < nbNombres; iN++) { for (int i = 0; i < nbPris; i++) { if (nombres[iN] & (1 << iConcerne[i])) nombres[iN] ^= nombres[i]; } for (int i = 0; i < MAXP; i++) { if (!prise[i] && (nombres[iN] & (1 << i))) { swap(nombres[iN], nombres[nbPris]); iConcerne[nbPris] = i; nbPris++; prise[i] = true; break; } } while (inQuestion < nbQuestions && questions[inQuestion].prefixe == iN) { for (int i = 0; i < nbPris; i++) { if (questions[inQuestion].nombre & (1 << iConcerne[i])) questions[inQuestion].nombre ^= nombres[i]; } if (questions[inQuestion].nombre == 0) { solution[questions[inQuestion].id] = puissance[iN + 1 - nbPris]; } else { solution[questions[inQuestion].id] = 0; } inQuestion++; } } for (int i = 0; i < nbQuestions; i++) { cout << solution[i] << endl; } }
|
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-10; const int MODULO = 1000000007; typedef struct { int i, m, v; } P; vector<P> mv; bool mLt(const P& x, const P& y) { return (x.m != y.m) ? less<int>()(x.m, y.m) : less<int>()(x.v, y.v); } int n, k, h; bool C(double t) { int i = 1; for (__typeof__((mv).begin()) it = (mv).begin(); it != (mv).end(); ++it) { if ((double)i * h <= (*it).v * t) i++; if (i > k) break; } return i > k; } int main() { cin >> n >> k >> h; mv.resize(n); for (int i = 0; i < n; i++) mv[i].i = i + 1; for (int i = 0; i < n; i++) cin >> mv[i].m; for (int i = 0; i < n; i++) cin >> mv[i].v; sort(mv.begin(), mv.end(), mLt); double l = 0, r = 1e10; double t; for (int i = 0; i < 100; i++) { t = (l + r) / 2; if (C(t)) r = t; else l = t; } int cnt = 1; for (__typeof__((mv).begin()) it = (mv).begin(); it != (mv).end(); ++it) { if ((double)cnt * h <= (*it).v * t * (1 + EPS)) { printf( %d , (*it).i); cnt++; } if (cnt > k) break; } puts( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_SYMBOL_V
|
#include <bits/stdc++.h> int main() { int n, i, j; scanf( %d , &n); long long int a[n][2], x, y, max1, max2, min1, min2; for (i = 0; i < n; i++) for (j = 0; j < 2; j++) scanf( %I64d , &a[i][j]); min1 = max1 = a[0][0]; min2 = max2 = a[0][1]; for (i = 0; i < n; i++) { if (min1 > a[i][0]) min1 = a[i][0]; if (max1 < a[i][0]) max1 = a[i][0]; if (min2 > a[i][1]) min2 = a[i][1]; if (max2 < a[i][1]) max2 = a[i][1]; } x = max1 - min1; y = max2 - min2; if (x > y) printf( %I64d , x * x); else printf( %I64d , y * y); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> invi(long long n) { int x; vector<long long> a; for (long long i = 0; i < n; i++) { cin >> x; a.push_back(x); } return a; } void solve(); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) solve(); } void solve() { long long n, k; cin >> n >> k; vector<long long> jobcho = invi(n); vector<long long> time = invi(n); vector<long long> ind; vector<long long> task; for (long long i = 0; i < k; i++) { task.push_back(0); ind.push_back(n + 1); } for (long long i = 0; i < n; i++) { if (task[jobcho[i] - 1] < time[i]) { task[jobcho[i] - 1] = time[i]; ind[jobcho[i] - 1] = i; } } for (long long i = 0; i < k; i++) { if (ind[i] < (n + 1)) time[ind[i]] = 1e10; } long long jbleft = 0; for (long long i = 0; i < k; i++) { if (task[i] == 0) { jbleft++; } } sort(time.begin(), time.end()); long long sum = 0; for (long long i = 0; i < jbleft; i++) { sum += time[i]; } cout << sum << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; priority_queue<pair<int, int> > p; int n; const int maxn = 1 << 19; int vis[maxn]; long long dp[maxn][19]; int a[maxn], pos, L, sum; long long ans; int main() { scanf( %d , &n); memset(dp, -1, sizeof(dp)); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] == -1) pos = i; if (!pos) a[i] = 0; } a[pos] = 0; int tmp = n; for (L = 0; 1 << L <= n; L++) ; for (int j = 1; j <= L; j++) { long long Mi = inf; if (j == 1) Mi = 0; for (int i = n; i > n - j + 1; i--) if (dp[i][j - 1] != -1) Mi = min(Mi, dp[i][j - 1]); for (int i = n - j + 1; i >= n - sum; i--) { dp[i][j] = Mi + a[i]; if (dp[i][j - 1] != -1) Mi = min(Mi, dp[i][j - 1]); } sum += tmp / 2; tmp /= 2; } long long ans = inf; for (int i = 1; i <= n; i++) if (dp[i][L] != -1) ans = min(ans, dp[i][L]); cout << ans << n ; }
|
#include <bits/stdc++.h> int main() { long n; long m; std::cin >> n >> m; long a = 0, b = 0, c = 0, d = 0; while (!(n % 2)) { n = n / 2; a++; } while (!(n % 3)) { n = n / 3; b++; } while (!(m % 2)) { m = m / 2; c++; } while (!(m % 3)) { m = m / 3; d++; } if ((n != m) || (a > c) || (b > d)) { std::cout << -1; } else { std::cout << (c + d) - (a + b); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int const N = 400010; int const M = 1001000; int n, m; struct edges { int u, next; } e[M]; int p[N], idx; void addedge(int u, int v) { e[idx].u = v, e[idx].next = p[u], p[u] = idx++; } void init() { idx = 0; memset(p, (0xff), sizeof p); } int key[N]; int sz[N]; int dep[N]; void dfs(int u, int d, int pre = -1) { sz[u] = 1; dep[u] = d; for (int i = p[u]; ~i; i = e[i].next) { int v = e[i].u; if (v != pre) { dfs(v, d + 1, u); sz[u] += sz[v]; } } for (int i = p[u]; ~i; i = e[i].next) { int v = e[i].u; if (v != pre) { if (sz[v] + sz[v] > n) key[u] = v; } } if (pre != -1 && sz[u] + sz[u] < n) key[u] = pre; } int dp[N]; int dpu[N]; void dfs1(int u, int pre = -1) { for (int i = p[u]; ~i; i = e[i].next) { int v = e[i].u; if (v != pre) { dfs1(v, u); dp[u] = max(dp[u], dp[v]); } } if (sz[u] + sz[u] <= n) dp[u] = sz[u]; } void dfs2(int u, int pre = -1) { int m1 = dpu[u], m2 = 0; for (int i = p[u]; ~i; i = e[i].next) { int v = e[i].u; if (v != pre) { dp[u] = max(dp[u], dp[v]); if (dp[v] >= m1) { m2 = m1; m1 = dp[v]; } else if (dp[v] >= m2) { m2 = dp[v]; } } } for (int i = p[u]; ~i; i = e[i].next) { int v = e[i].u; if (v != pre) { int rem = n - sz[v]; if (rem + rem <= n) dpu[v] = rem; else { if (dp[v] == m1) dpu[v] = max(dpu[v], m2); else dpu[v] = max(dpu[v], m1); } dfs2(v, u); } } } int main() { scanf( %d , &n); init(); for (int i = 0; i < (n - 1); ++i) { int a, b; scanf( %d%d , &a, &b); addedge(a, b); addedge(b, a); } dfs(1, 0); dfs1(1); dfs2(1); for (int i = 1; i <= (n); ++i) { if (key[i] == 0) printf( 1 ); else { bool ok = 0; int u = key[i]; if (dep[u] > dep[i]) { int rem = sz[u] - dp[u]; if (rem + rem <= n) ok = 1; } else { int t = dpu[i]; int rem = n - sz[i]; if ((rem - t) * 2 <= n) ok = 1; } if (ok) printf( 1 ); else printf( 0 ); } } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, m, i, ans, a; int main() { cin >> t; while (t--) { cin >> n >> m; ans = 0; for (i = 1; i <= n; i++) { cin >> a; ans += a; } if (ans == m) cout << YES << endl; else cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long mul(long long a, long long b, long long p) { long long s = 0; while (b) { if (b & 1) s = (s + a) % p; a = (a + a) % p; b >>= 1; } return s; } long long ksm(long long a, long long b, long long p) { long long s = 1; while (b) { if (b & 1) s = mul(s, a, p); a = mul(a, a, p); b >>= 1; } return s; } int main() { long long n; cin >> n; while (n--) { long long a; cin >> a; long long n = to_string(a).length(); for (long long m = 0;; m++) { long long b = ((1 << n + m) - a % (1 << n + m)) % (1 << n + m); if ((a + b) % 5 == 0) b += 1 << n + m; if (b < pow(10, m)) { long long x = (a + b) >> n + m, d = -1; for (long long i = 0; i < 5; i++) if ((1 << i) % 5 == x % 5) { d = i; break; } for (long long i = 2, p = 5; i <= n + m; i++) { long long phi = p / 5 * 4; p *= 5; for (long long k = 0; k < 5; k++) if (ksm(2, d + k * phi, p) == x % p) { d += k * phi; break; } } cout << d + n + m << n ; break; } a *= 10; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; cin >> n >> m >> a >> b; if (m * a <= b) cout << n * a << n ; else cout << (n / m) * b + min((n % m) * a, b) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000 + 5; struct stu { int id, sc; } a[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int i, j; for (i = 1; i <= n; i++) { a[i].id = i; a[i].sc = 0; int x; for (j = 0; j < 4; j++) { cin >> x; a[i].sc += x; } } for (i = 1; i < n; i++) { for (j = i + 1; j <= n; j++) { if (a[i].sc < a[j].sc || (a[i].sc == a[j].sc && a[i].id > a[j].id)) { swap(a[i], a[j]); } } if (a[i].id == 1) break; } cout << i << endl; return 0; }
|
// wasca_mm_interconnect_0_avalon_st_adapter_008.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_008 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_008_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/19/2016 12:22:57 AM
// Design Name:
// Module Name: swAlloc
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef BLESS
// To enable parallel port allocator, set PARALLEL_PA in global.vh
module swAlloc (
numFlit_in,
ppv_0,
ppv_1,
ppv_2,
ppv_3,
allocPV_0,
allocPV_1,
allocPV_2,
allocPV_3
);
input [`PC_INDEX_WIDTH-1:0] numFlit_in;
input [`NUM_PORT-2:0] ppv_0, ppv_1, ppv_2, ppv_3;
output [`NUM_PORT-2:0] allocPV_0, allocPV_1, allocPV_2, allocPV_3;
generate
if (`PARALLEL_PA == 1'b0) begin : seqAlloc
wire [`NUM_PORT-2:0] w_availPort [1:3];
wire [`PC_INDEX_WIDTH-1:0] w_numFlit [1:3];
seqPortAlloc rank0PortAlloc(
.numFlit_in (numFlit_in),
.availPortVector_in (4'b1111),
.ppv (ppv_0),
.allocatedPortVector (allocPV_0),
.availPortVector_out (w_availPort[1]),
.numFlit_out (w_numFlit[1])
);
seqPortAlloc rank1PortAlloc(
.numFlit_in (w_numFlit[1]),
.availPortVector_in (w_availPort[1]),
.ppv (ppv_1),
.allocatedPortVector (allocPV_1),
.availPortVector_out (w_availPort[2]),
.numFlit_out (w_numFlit[2])
);
seqPortAlloc rank02ortAlloc(
.numFlit_in (w_numFlit[2]),
.availPortVector_in (w_availPort[2]),
.ppv (ppv_2),
.allocatedPortVector (allocPV_2),
.availPortVector_out (w_availPort[3]),
.numFlit_out (w_numFlit[3])
);
seqPortAlloc rank3PortAlloc(
.numFlit_in (w_numFlit[3]),
.availPortVector_in (w_availPort[3]),
.ppv (ppv_3),
.allocatedPortVector (allocPV_3),
.availPortVector_out (),
.numFlit_out ()
);
end
else begin : paraAlloc
// not implemetned;
// refer to IPDPS'16 DeC paper
end
endgenerate
endmodule
`endif // BLESS
`ifdef CARPOOL
// To enable parallel port allocator, set PARALLEL_PA in global.vh
module swAlloc (
mc_0,
mc_1,
mc_2,
mc_3,
numFlit_in,
ppv_0,
ppv_1,
ppv_2,
ppv_3,
allocPV_0,
allocPV_1,
allocPV_2,
allocPV_3
);
input mc_0, mc_1, mc_2, mc_3;
input [`PC_INDEX_WIDTH-1:0] numFlit_in;
input [`NUM_PORT-2:0] ppv_0, ppv_1, ppv_2, ppv_3;
output [`NUM_PORT-2:0] allocPV_0, allocPV_1, allocPV_2, allocPV_3;
generate
if (`PARALLEL_PA == 1'b0) begin : seqAlloc
wire [`NUM_PORT-2:0] w_availPort [1:3];
wire [`PC_INDEX_WIDTH-1:0] w_numFlit [1:3];
seqPortAlloc rank0PortAlloc(
.mc (mc_0),
.numFlit_in (numFlit_in),
.availPortVector_in (4'b1111),
.ppv (ppv_0),
.allocatedPortVector (allocPV_0),
.availPortVector_out (w_availPort[1]),
.numFlit_out (w_numFlit[1])
);
seqPortAlloc rank1PortAlloc(
.mc (mc_1),
.numFlit_in (w_numFlit[1]),
.availPortVector_in (w_availPort[1]),
.ppv (ppv_1),
.allocatedPortVector (allocPV_1),
.availPortVector_out (w_availPort[2]),
.numFlit_out (w_numFlit[2])
);
seqPortAlloc rank02ortAlloc(
.mc (mc_2),
.numFlit_in (w_numFlit[2]),
.availPortVector_in (w_availPort[2]),
.ppv (ppv_2),
.allocatedPortVector (allocPV_2),
.availPortVector_out (w_availPort[3]),
.numFlit_out (w_numFlit[3])
);
seqPortAlloc rank3PortAlloc(
.mc (mc_3),
.numFlit_in (w_numFlit[3]),
.availPortVector_in (w_availPort[3]),
.ppv (ppv_3),
.allocatedPortVector (allocPV_3),
.availPortVector_out (),
.numFlit_out ()
);
end
else begin : paraAlloc
wire [`NUM_PORT-2:0] apv_p_0, apv_p_1, apv_p_2, apv_p_3, ppv_p_0, ppv_p_1, ppv_p_2, ppv_p_3;
paraPortAlloc_st1 paraPA_st1_ch0(
.mc (mc_0),
.treat_as_uc (1'b0),
.numFlit_in (numFlit_in),
.ppv (ppv_0),
.ppv_others ({ppv_1, ppv_2, ppv_3}),
.apv_p (apv_p_0),
.ppv_p (ppv_p_0)
);
paraPortAlloc_st1 paraPA_st1_ch1(
.mc (mc_1),
.treat_as_uc (mc_0),
.numFlit_in (numFlit_in),
.ppv (ppv_1),
.ppv_others ({ppv_0, ppv_2, ppv_3}),
.apv_p (apv_p_1),
.ppv_p (ppv_p_1)
);
paraPortAlloc_st1 paraPA_st1_ch2(
.mc (mc_2),
.treat_as_uc (mc_0|mc_1),
.numFlit_in (numFlit_in),
.ppv (ppv_2),
.ppv_others ({ppv_0, ppv_1, ppv_3}),
.apv_p (apv_p_2),
.ppv_p (ppv_p_2)
);
paraPortAlloc_st1 paraPA_st1_ch3(
.mc (mc_3),
.treat_as_uc (mc_0|mc_1|mc_2),
.numFlit_in (numFlit_in),
.ppv (ppv_3),
.ppv_others ({ppv_0, ppv_1, ppv_2}),
.apv_p (apv_p_3),
.ppv_p (ppv_p_3)
);
paraPortAlloc_st2 # (.CH_INDEX (2'd0)) paraPA_st2_ch0(
.apv_p_0 (apv_p_0),
.apv_p_1 (apv_p_1),
.apv_p_2 (apv_p_2),
.apv_p_3 (apv_p_3),
.ppv_p_0 (ppv_p_0),
.ppv_p_1 (ppv_p_1),
.ppv_p_2 (ppv_p_2),
.ppv_p_3 (ppv_p_3),
.apv (allocPV_0)
);
paraPortAlloc_st2 # (.CH_INDEX (2'd1)) paraPA_st2_ch1(
.apv_p_0 (apv_p_0),
.apv_p_1 (apv_p_1),
.apv_p_2 (apv_p_2),
.apv_p_3 (apv_p_3),
.ppv_p_0 (ppv_p_0),
.ppv_p_1 (ppv_p_1),
.ppv_p_2 (ppv_p_2),
.ppv_p_3 (ppv_p_3),
.apv (allocPV_1)
);
paraPortAlloc_st2 # (.CH_INDEX (2'd2)) paraPA_st2_ch2(
.apv_p_0 (apv_p_0),
.apv_p_1 (apv_p_1),
.apv_p_2 (apv_p_2),
.apv_p_3 (apv_p_3),
.ppv_p_0 (ppv_p_0),
.ppv_p_1 (ppv_p_1),
.ppv_p_2 (ppv_p_2),
.ppv_p_3 (ppv_p_3),
.apv (allocPV_2)
);
paraPortAlloc_st2 # (.CH_INDEX (2'd3)) paraPA_st2_ch3(
.apv_p_0 (apv_p_0),
.apv_p_1 (apv_p_1),
.apv_p_2 (apv_p_2),
.apv_p_3 (apv_p_3),
.ppv_p_0 (ppv_p_0),
.ppv_p_1 (ppv_p_1),
.ppv_p_2 (ppv_p_2),
.ppv_p_3 (ppv_p_3),
.apv (allocPV_3)
);
end
endgenerate
endmodule
`endif // CARPOOL
|
module FreqCounter(rst_n, clk, refer, ready, sck, cs, miso);
input rst_n, clk, refer, sck, cs;
output miso;
output ready;
wire [31:0] sum;
wire [31:0] latchedSum;
Counter counter(rst_n, clk, refer, sum);
D_FF dff(rst_n, refer, cs, sum, latchedSum);
SpiSlave spi(rst_n, latchedSum, sck, cs, miso);
assign ready = refer;
endmodule
// Counter
module Counter(rst_n, clk, clr, sum);
input rst_n, clk, clr;
output reg [31:0] sum;
reg lastClr;
always @(negedge rst_n or posedge clk)
begin
if (~rst_n)
begin
sum <= 32'b0;
lastClr <= 1'b0;
end
else
if (clr && lastClr == ~clr)
begin // posedge clr
sum <= 32'b0;
lastClr <= clr;
end
else
begin
sum <= sum + 32'b1;
lastClr <= clr;
end
end
endmodule
// DFF
module D_FF(rst_n, trig, en, d, q);
input rst_n, trig, en;
input [31:0] d;
output reg [31:0] q;
always @(negedge rst_n or posedge trig)
begin
if (~rst_n)
q <= 32'b0;
else
begin
if (en)
q <= d;
else
q <= q;
end
end
endmodule
// SPI Slave
// MSB first, CPOL = 1, CPHA = 1
module SpiSlave(rst_n, sum, sck, cs, miso);
input rst_n, sck, cs;
input [31:0] sum;
output reg miso;
reg [4:0] i;
always @(negedge rst_n or posedge cs or negedge sck)
begin
if (~rst_n)
begin
miso <= 1'b0;
i <= 5'b11111;
end
else if (cs)
begin
miso <= 1'b0;
i <= 5'b11111;
end
else // if (~cs)
begin
miso <= sum[i];
i <= i - 5'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_LP_V
`define SKY130_FD_SC_LP__O21BA_LP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_lp (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_lp (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_LP_V
|
//-----------------------------------------------------------------------------
// File : wb_master.v
// Creation date : 27.07.2017
// Creation time : 14:33:17
// Description : A bridge between a CPU and wishbone bus.
// Created by : TermosPullo
// Tool : Kactus2 3.4.110 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:communication.bridge:wb_master_cpu_slave:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.bridge/wb_master_cpu_slave/1.0/wb_master_cpu_slave.1.0.xml
//-----------------------------------------------------------------------------
module wb_master #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of both input and output data.
parameter BASE_ADDRESS = 'h0F00, // The location of the bus in the system memory.
parameter RANGE = 'h0200 // Number of addresses accesible by the component.
) (
// Interface: contoller
// Is used by a controller to initiate transfers through the bridge.
input [ADDR_WIDTH-1:0] mem_address_in, // Target address of a peripheral operation.
input [DATA_WIDTH-1:0] mem_data_in, // Data from controller.
input mem_master_rdy, // Data is provided and transfer can be executed.
input mem_we_in, // Controllers writes = 1, Controller reads = 0.
output reg [DATA_WIDTH-1:0] mem_data_out, // Data to controller.
output reg mem_slave_rdy, // Bridge has executed the transfer.
// Interface: wb_master
// Connects to wishbone slave or mirrored master accessible through this bridge.
input wb_ack_i, // Slave asserts acknowledge.
input [DATA_WIDTH-1:0] wb_dat_i, // Data from slave to master.
input wb_err_i, // Indicates abnormal cycle termination.
output reg [ADDR_WIDTH-1:0] wb_adr_o, // The address of the data.
output reg wb_cyc_o, // Asserted by master for transfer.
output reg [DATA_WIDTH-1:0] wb_dat_o, // Data from master to slave.
output reg wb_stb_o, // Asserted by master for transfer.
output reg wb_we_o, // Write = 1, Read = 0.
// Interface: wb_system
// Grouping for wishbone system signals. The clock and reset are used for all logic
// in this module.
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The current state.
reg [2:0] state;
// The available states.
parameter [2:0]
S_CMD = 3'd0, // Waiting command from the master
S_WRITE_INIT = 3'd1, // Initiating a write to slave.
S_WAIT_WRITE_ACK = 3'd2, // Waiting ack for write from slave.
S_READ_INIT = 3'd3, // Initiating a read to slave.
S_WAIT_READ_ACK = 3'd4, // Waiting ack for write from slave.
S_DEASSERT = 3'd5;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
// Initally waiting for start signal.
state <= S_CMD;
// Everything else is zero.
wb_dat_o <= 0;
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_we_o <= 0;
wb_adr_o <= 0;
mem_data_out <= 0;
mem_slave_rdy <= 0;
end
else begin
case(state)
S_CMD: begin
// Wait for the master.
if (mem_master_rdy == 1'b1) begin
// Branch based on if it is read or write.
if (mem_we_in == 1'b1) begin
state <= S_WRITE_INIT;
end
else begin
state <= S_READ_INIT;
end
end
end
S_WRITE_INIT: begin
// Assert signals indicating we are ready to transfer.
wb_cyc_o <= 1;
wb_stb_o <= 1;
// We are writing to slave.
wb_we_o <= 1;
// Take data directly from the master.
wb_dat_o <= mem_data_in;
wb_adr_o <= mem_address_in;
// Next we shall wait for acknowledgement.
state <= S_WAIT_WRITE_ACK;
end
S_WAIT_WRITE_ACK: begin
if (wb_err_i == 1'b1 || wb_ack_i == 1'b1) begin
// Deassert initiator signals.
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_we_o <= 0;
// Pass the result to the master.
mem_slave_rdy <= 1;
// Look for the next operation.
state <= S_DEASSERT;
end
end
S_READ_INIT: begin
// Assert signals indicating we are ready to transfer.
wb_cyc_o <= 1;
wb_stb_o <= 1;
// We are reading from slave.
wb_we_o <= 0;
// Take address directly from the master.
wb_adr_o <= mem_address_in;
// Next we shall wait for acknowledgement.
state <= S_WAIT_READ_ACK;
end
S_WAIT_READ_ACK: begin
if (wb_err_i == 1'b1 || wb_ack_i == 1'b1) begin
// Deassert initiator signals.
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_we_o <= 0;
// Pass the result to the master.
mem_slave_rdy <= 1;
if (wb_err_i == 1'b1) begin
mem_data_out <= 0;
end
else begin
mem_data_out <= wb_dat_i;
end
// Look for the next operation.
state <= S_DEASSERT;
end
end
S_DEASSERT: begin
state <= S_CMD;
mem_slave_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> const int MAXN = 1000; int ba[MAXN], bb[MAXN]; int a, b, da, db, t, x, l1, l2; int main() { scanf( %d %d %d %d %d %d , &x, &t, &a, &b, &da, &db); int tm = 0; while (a >= 0) { ba[l1++] = a; a -= da; tm++; if (tm >= t) break; } tm = 0; while (b >= 0) { bb[l2++] = b; b -= db; tm++; if (tm >= t) break; } for (int i = 0; i < l1; i++) if (ba[i] == x) { printf( YES n ); return 0; } if (x == 0) { printf( YES n ); return 0; } for (int i = 0; i < l2; i++) if (bb[i] == x) { printf( YES n ); return 0; } for (int i = 0; i < l1; i++) for (int j = 0; j < l2; j++) if (ba[i] + bb[j] == x) { printf( YES n ); return 0; } printf( NO n ); return 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; int n; int xi[maxn], yi[maxn]; int ans1 = 0, ans2 = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &xi[i]), ans1 += xi[i]; for (int i = 1; i <= n; i++) scanf( %d , &yi[i]), ans2 += yi[i]; if (ans1 < ans2) printf( No n ); else printf( Yes n ); return 0; }
|
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: WSIZ Copernicus
// Engineer: Darek B.
//
// Create Date: 18.05.2017 17:42:28
// Design Name:
// Module Name: wyswietlacz_4x7seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
/*
MULTIPLEXOWANY, CZTEROSEGMENTOWY WYWIETLACZ 7SEG Z KROPK¥
*/
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wyswietlacz_4x7seg(
input wire clk, // zegar (nie mniej, ni¿ 250Hz)
input wire [4:0] L_1, // liczba segement 1 (6 bit = kropka)
input wire [4:0] L_2, // liczba segement 2 (6 bit = kropka)
input wire [4:0] L_3, // liczba segement 3 (6 bit = kropka)
input wire [4:0] L_4, // liczba segement 4 (6 bit = kropka)
output reg [3:0] segment_out, // wskanik wywietlanej liczby (0-wywietlany, 1-zgaszony)
output reg seg_um, // góra, rodek
output reg seg_ul, // góra, lewo
output reg seg_ur, // góra, prawo
output reg seg_mm, // rodek, rodek
output reg seg_dl, // dó³, lewo
output reg seg_dr, // dó³, prawo
output reg seg_dm, // dól, rodek
output reg seg_dot // kropka
);
function [7:0]liczbaNAsygnaly;
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000; // nic nie wieci
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111}; // 0
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010}; // 1
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101}; // 2
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011}; // 3
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010}; // 4
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011}; // 5
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111}; // 6
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010}; // 7
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111}; // 8
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011}; // 9
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000}; // -
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000}; // um
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000}; // ur
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000}; // mm
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000}; // ul
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000}; // nic
endcase
end
endfunction
always @(negedge clk)
begin
case (segment_out)
default: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end // inicjalizacja - pierwszy segment zapalony
4'b1110: begin segment_out <= ~4'b0010; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_2); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b1101: begin segment_out <= ~4'b0100; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_3); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b1011: begin segment_out <= ~4'b1000; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_4); end // z ka¿dym pe³nym cyklem zmieniamy wywietlany segment
4'b0111: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end // ustawiamy wyswietlany segment na pierwszy
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_TB_V
`define SKY130_FD_SC_MS__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
/**
* lpflow_inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; char getc() { char c = getchar(); while ((c < A || c > Z ) && (c < a || c > z ) && (c < 0 || c > 9 )) c = getchar(); return c; } int gcd(int n, int m) { return m == 0 ? n : gcd(m, n % m); } int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } int n, m, k, a[5010], q[5010], head, tail; long long f[5010][5010]; int main() { n = read(), k = read(), m = read(); for (int i = 1; i <= n; i++) a[i] = read(); memset(f, 200, sizeof(f)); f[0][0] = 0; for (int j = 1; j <= m; j++) { head = 1, tail = 1; q[1] = 0; for (int i = 1; i <= n; i++) { while (head < tail && q[head] < i - k) head++; f[i][j] = f[q[head]][j - 1] + a[i]; while (head <= tail && f[q[tail]][j - 1] <= f[i][j - 1]) tail--; q[++tail] = i; } } for (int i = n - 1; i >= max(0, n - k + 1); i--) f[n][m] = max(f[n][m], f[i][m]); if (f[n][m] < 0) cout << -1; else cout << f[n][m]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFXTP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_BLACKBOX_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPowerOfTwo(long long n) { if (n == 0) return false; return (ceil(log2(n)) == floor(log2(n))); } long long power(long long x, unsigned long long y) { if (y == 0) return 1; else if (y % 2 == 0) return power(x, y / 2) * power(x, y / 2); else return x * power(x, y / 2) * power(x, y / 2); } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } signed main() { long long n; cin >> n; priority_queue<long long> a, b, c, d; for (long long i = 0; i < n; i++) { string s; long long x; cin >> s >> x; if (s == 11 ) a.push(x); if (s == 10 ) b.push(x); if (s == 01 ) c.push(x); if (s == 00 ) d.push(x); } long long ans = 0; long long x = 0, y = 0, z = 0; ; while (!a.empty()) { ans += a.top(); x++; y++; a.pop(); z++; } while (!b.empty() && !c.empty()) { ans += b.top(); ans += c.top(); x++; y++; z += 2; b.pop(); c.pop(); } long long p = 2 * x - z; if (b.empty() == true) { while (!c.empty()) { d.push(c.top()); c.pop(); } } else { while (!b.empty()) { d.push(b.top()); b.pop(); } } while (p > 0 && !d.empty()) { p--; ans += d.top(); d.pop(); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int pc[1 << 10]; for (size_t i = 0; i < (1 << 10); i++) { int buf = 0; for (int j = 0; j < 10; j++) { if ((1 << j) & i) buf++; } pc[i] = buf; } int n, m; cin >> n >> m; map<int, pair<unsigned long long, unsigned long long>> ans; vector<int> v1(n); vector<int> v2(m); for (size_t i = 0; i < n; i++) { cin >> v1[i]; v1[i] *= 2; } for (size_t i = 0; i < m; i++) { cin >> v2[i]; v2[i] *= 2; } for (size_t i = 0; i < n; i++) { for (size_t j = 0; j < m; j++) { int buf = (v1[i] + v2[j]) / 2; ans[buf].first |= (1ULL << i); ans[buf].second |= (1ULL << j); } } int ansv = 0; for (auto i = ans.begin(); i != ans.end(); i++) { for (auto j = i; j != ans.end(); j++) { long long a1 = i->second.first; long long a2 = j->second.first; long long b1 = i->second.second; long long b2 = j->second.second; long long buf1 = a1 | a2; long long buf2 = b1 | b2; int buf = 0; while (buf1) { int buff = buf1 & 1023; buf1 >>= 10; buf += pc[buff]; } while (buf2) { int buff = buf2 & 1023; buf2 >>= 10; buf += pc[buff]; } ansv = max(ansv, buf); } } cout << ansv; }
|
#include <bits/stdc++.h> using namespace std; long long calc_2(int s) { if (s < 0) return 0; return 1LL * (s + 1) * (s + 2) / 2; } long long calc_3(int s) { if (s < 0) return 0; long long ans = 0; for (int i = 0; i <= s; i++) ans += calc_2(s - i); return ans; } int val[5]; int main() { int a, b, c, L; scanf( %d%d%d%d , &a, &b, &c, &L); val[1] = a - b - c, val[2] = b - a - c, val[3] = c - a - b; long long ans = calc_3(L); for (int i = 1; i <= 3; i++) { for (int z = 0; z <= L; z++) { int ed = min(L - z, val[i] + z); ans -= calc_2(ed); } } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_2_V
`define SKY130_FD_SC_HDLL__A2BB2O_2_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_2_V
|
#include <bits/stdc++.h> using namespace std; namespace { using namespace std; template <typename flow_t = long long> struct PushRelabel { struct Edge { int to, rev; flow_t f, c; }; vector<vector<Edge>> g; vector<flow_t> ec; vector<Edge*> cur; vector<vector<int>> hs; vector<int> H; PushRelabel(int n) : g(n), ec(n), cur(n), hs(2 * n), H(n) {} void add_edge(int s, int t, flow_t cap, flow_t rcap = 0) { if (s == t) return; Edge a = {t, (int)g[t].size(), 0, cap}; Edge b = {s, (int)g[s].size(), 0, rcap}; g[s].push_back(a); g[t].push_back(b); } void add_flow(Edge& e, flow_t f) { Edge& back = g[e.to][e.rev]; if (!ec[e.to] && f) hs[H[e.to]].push_back(e.to); e.f += f; e.c -= f; ec[e.to] += f; back.f -= f; back.c += f; ec[back.to] -= f; } flow_t max_flow(int s, int t) { const int n = g.size(); ec.assign(n, 0); cur.assign(n, nullptr); hs.assign(2 * n, {}); H.assign(n, 0); int v = g.size(); H[s] = v; ec[t] = 1; vector<int> co(2 * v); co[0] = v - 1; for (int i = 0; i < v; ++i) cur[i] = g[i].data(); for (auto& e : g[s]) add_flow(e, e.c); if (hs[0].size()) for (int hi = 0; hi >= 0;) { int u = hs[hi].back(); hs[hi].pop_back(); while (ec[u] > 0) if (cur[u] == g[u].data() + g[u].size()) { H[u] = 1e9; for (auto& e : g[u]) if (e.c && H[u] > H[e.to] + 1) H[u] = H[e.to] + 1, cur[u] = &e; if (++co[H[u]], !--co[hi] && hi < v) for (int i = 0; i < v; ++i) if (hi < H[i] && H[i] < v) { --co[H[i]]; H[i] = v + 1; } hi = H[u]; } else if (cur[u]->c && H[u] == H[cur[u]->to] + 1) add_flow(*cur[u], min(ec[u], cur[u]->c)); else ++cur[u]; while (hi >= 0 && hs[hi].empty()) --hi; } return -ec[s]; } }; template <typename flow_t = long long> struct MaxFlow { static constexpr flow_t INF = numeric_limits<flow_t>::max(); PushRelabel<flow_t> flow; MaxFlow(const int n) : flow(n) {} inline void add_arc(const int u, const int v, const flow_t capacity) { flow.add_edge(u, v, capacity); } inline void add_edge(const int u, const int v, const flow_t capacity) { flow.add_edge(u, v, capacity, capacity); } inline void add_infinite_arc(const int u, const int v) { flow.add_edge(u, v, INF); } inline void add_infinite_edge(const int u, const int v) { flow.add_edge(u, v, INF, INF); } flow_t solve(const int s, const int t) { return flow.max_flow(s, t); } }; template <typename flow_t> class MaxFlowLR { private: static constexpr flow_t INF = numeric_limits<flow_t>::max(); int n; vector<flow_t> from_source, to_sink, outgoing_capacity; vector<tuple<int, int, flow_t>> demands; flow_t total_demand; bool invalid; PushRelabel<flow_t> flow; public: MaxFlowLR(const int n) : n(n), from_source(n), to_sink(n), outgoing_capacity(n), total_demand(0), invalid(false), flow(n + 2) {} void add_arc(const int u, const int v, const flow_t demand, const flow_t capacity) { if (demand > capacity) { invalid = true; return; } if (u != v) { from_source[v] += demand; to_sink[u] += demand; flow.add_edge(u, v, capacity - demand); demands.push_back({u, v, demand}); total_demand += demand; outgoing_capacity[u] += capacity; } } flow_t solve(const int s, const int t) { if (invalid) { return -1; } const int source = n; const int sink = n + 1; for (int v = 0; v < n; ++v) { if (from_source[v] != 0) { flow.add_edge(source, v, from_source[v]); } if (to_sink[v] != 0) { flow.add_edge(v, sink, to_sink[v]); } } flow.add_edge(t, s, INF); const flow_t flow_aux = flow.max_flow(source, sink); if (s != t) { flow.g[s].pop_back(); flow.g[t].pop_back(); } for (int v = n - 1; v >= 0; --v) { if (to_sink[v] != 0) { flow.g[sink].pop_back(); flow.g[v].pop_back(); } if (from_source[v] != 0) { flow.g[source].pop_back(); flow.g[v].pop_back(); } } if (flow_aux != total_demand) return -1; const flow_t flow_new = flow.max_flow(s, t); flow_t total_flow = outgoing_capacity[s]; for (const auto& e : flow.g[s]) total_flow -= e.c; return total_flow; } vector<map<int, flow_t>> retrieve() { vector<map<int, flow_t>> ans(n); for (int u = 0; u < n; ++u) for (const auto& e : flow.g[u]) if (e.f > 0) ans[u][e.to] += e.f, ans[e.to][u] -= e.f; for (auto t : demands) if (get<2>(t) > 0) ans[get<0>(t)][get<1>(t)] += get<2>(t), ans[get<1>(t)][get<0>(t)] -= get<2>(t); return ans; } }; } // namespace inline int divceil(const int x, const int y) { const int q = x / y; return q * y == x ? q : q + 1; } inline long long divceil(const long long x, const long long y) { const long long q = x / y; return q * y == x ? q : q + 1; } map<int, int> coordinate_compression(vector<int> v) { sort(v.begin(), v.end()); const int n = unique(v.begin(), v.end()) - v.begin(); map<int, int> compr; for (int i = 0; i < n; ++i) compr[v[i]] = i; return compr; } map<long long, int> coordinate_compression(vector<long long> v) { sort(v.begin(), v.end()); const int n = unique(v.begin(), v.end()) - v.begin(); map<long long, int> compr; for (int i = 0; i < n; ++i) compr[v[i]] = i; return compr; } int main() { int n, m; scanf( %d%d , &n, &m); int r, b; scanf( %d%d , &r, &b); bool flip = false; if (r >= b) { flip = true; swap(r, b); } vector<std::pair<int, int>> original_points; vector<int> allx, ally; for (int i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); original_points.emplace_back(x, y); allx.push_back(x); ally.push_back(y); } map<int, int> comprx = coordinate_compression(allx), compry = coordinate_compression(ally); const int xlines = comprx.rbegin()->second + 1; const int ylines = compry.rbegin()->second + 1; vector<int> xdeg(xlines), ydeg(ylines); vector<int> xcons(xlines), ycons(ylines); vector<std::pair<int, int>> points; for (const std::pair<int, int> p : original_points) { const int xx = comprx[p.first]; const int yy = compry[p.second]; points.emplace_back(xx, yy); ++xdeg[xx]; ++ydeg[yy]; ++xcons[xx]; ++ycons[yy]; } while (m--) { int t, l, d; scanf( %d%d%d , &t, &l, &d); if (t == 1) { const auto it = comprx.find(l); if (it != comprx.end()) xcons[it->second] = min(xcons[it->second], d); } else { const auto it = compry.find(l); if (it != compry.end()) ycons[it->second] = min(ycons[it->second], d); } } MaxFlowLR<long long> dinic(2 + xlines + ylines); const int source = 0; const int sink = 1; const auto get_xvert = [&](const int i) { return 2 + i; }; const auto get_yvert = [&](const int i) { return 2 + xlines + i; }; for (int i = 0; i < xlines; ++i) { const int L = divceil(xdeg[i] - xcons[i], 2); const int R = (xdeg[i] + xcons[i]) / 2; dinic.add_arc(source, get_xvert(i), L, R); } for (int i = 0; i < ylines; ++i) { const int L = divceil(ydeg[i] - ycons[i], 2); const int R = (ydeg[i] + ycons[i]) / 2; dinic.add_arc(get_yvert(i), sink, L, R); } for (const std::pair<int, int> p : points) dinic.add_arc(get_xvert(p.first), get_yvert(p.second), 0, 1); long long flow_value = dinic.solve(source, sink); if (flow_value == -1) { puts( -1 ); return 0; } long long ans = flow_value * r + (n - flow_value) * b; cout << ans << endl; map<std::pair<int, int>, int> red; auto flow = dinic.retrieve(); for (int i = 0; i < xlines; ++i) { const int x = get_xvert(i); for (const auto p : flow[x]) { const int j = p.first - 2 - xlines; const int f = p.second; if (j >= 0) red[std::pair<int, int>(i, j)] += f; } } for (const std::pair<int, int> p : points) { int& v = red[p]; if (v) { v--; putchar(flip ? b : r ); } else { putchar(flip ? r : b ); } } cout << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
reg [15:0] v1;
reg [15:0] v2;
reg [15:0] v3;
integer nosplit;
always @ (posedge clk) begin
// write needed so that V3Dead doesn't kill v0..v3
$write(" values %x %x %x\n", v1, v2, v3);
// Locally-set 'nosplit' will prevent the if from splitting
// in splitAlwaysAll(). This whole always block should still be
// intact when we call splitReorderAll() which is the subject
// of this test.
nosplit = cyc;
if (nosplit > 2) begin
/* S1 */ v1 <= 16'h0;
/* S2 */ v1 <= m_din;
/* S3 */ if (m_din == 16'h0) begin
/* X1 */ v2 <= v1;
/* X2 */ v3 <= v2;
end
end
// We expect to swap S2 and S3, and to swap X1 and X2.
// We can check that this worked by the absense of dly vars
// in the generated output; if the reorder fails (or is disabled)
// we should see dly vars for v1 and v2.
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> a(n); for (auto &i : a) cin >> i; if (n == 1) { cout << 0 << n ; return 0; } int ans = INT_MAX, base; for (int i = 1; i <= 1000; i++) { int first = i, curr = 0; for (int j = 0; j < n; j++) if (a[j] != first + j * k) curr++; if (curr < ans) base = i, ans = curr; } cout << ans << n ; for (int j = 0; j < n; j++) { int now = base + j * k; if (a[j] < now) cout << + << j + 1 << << now - a[j] << n ; else if (a[j] > now) cout << - << j + 1 << << a[j] - now << n ; } }
|
#include <bits/stdc++.h> using namespace std; char s[50], c[50]; int t1 = 0, t2 = 0; int main() { cin >> s >> c; for (int i = 0; i < strlen(s); i += 2) { if ((s[i] == 8 && c[i] == [ ) || (s[i] == [ && c[i] == ( ) || (s[i] == ( && c[i] == 8 )) t1++; else if (s[i] != c[i]) t2++; } if (t1 > t2) cout << TEAM 1 WINS ; else if (t2 > t1) cout << TEAM 2 WINS ; else cout << TIE ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_1_V
`define SKY130_FD_SC_LS__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3 (
VPWR,
VGND,
X ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_FUNCTIONAL_PP_V
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of K580WT57 DMA controller
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wt57.v
//
// Warning: This realization is not fully operational.
module k580wt57(
input clk,
input ce,
input reset,
input[3:0] iaddr,
input[7:0] idata,
input[3:0] drq,
input iwe_n,
input ird_n,
input hlda,
output hrq,
output reg[3:0] dack,
output[7:0] odata,
output[15:0] oaddr,
output owe_n,
output ord_n,
output oiowe_n,
output oiord_n );
parameter ST_IDLE = 3'b000;
parameter ST_WAIT = 3'b001;
parameter ST_T1 = 3'b010;
parameter ST_T2 = 3'b011;
parameter ST_T3 = 3'b100;
parameter ST_T4 = 3'b101;
parameter ST_T5 = 3'b110;
parameter ST_T6 = 3'b111;
reg[2:0] state;
reg[1:0] channel;
reg[7:0] mode;
reg[4:0] chstate;
reg[15:0] chaddr[3:0];
reg[15:0] chtcnt[3:0];
reg ff,exiwe_n;
assign hrq = state!=ST_IDLE;
assign odata = {3'b0,chstate};
assign oaddr = chaddr[channel];
assign owe_n = chtcnt[channel][14]==0 || state!=ST_T2;
assign ord_n = chtcnt[channel][15]==0 || (state!=ST_T1 && state!=ST_T2);
assign oiowe_n = chtcnt[channel][15]==0 || state!=ST_T2;
assign oiord_n = chtcnt[channel][14]==0 || (state!=ST_T1 && state!=ST_T2);
wire[3:0] mdrq = drq & mode[3:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; ff <= 0; mode <= 0; exiwe_n <= 1'b1;
chstate <= 0; dack <= 0;
end else begin
exiwe_n <= iwe_n;
if (iwe_n && ~exiwe_n) begin
ff <= ~(ff|iaddr[3]);
if (ff) begin
if(iaddr==4'b0000) chaddr[0][15:8] <= idata;
if(iaddr==4'b0001) chtcnt[0][15:8] <= idata;
if(iaddr==4'b0010) chaddr[1][15:8] <= idata;
if(iaddr==4'b0011) chtcnt[1][15:8] <= idata;
if(iaddr==4'b0100) chaddr[2][15:8] <= idata;
if(iaddr==4'b0101) chtcnt[2][15:8] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][15:8] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][15:8] <= idata;
end else begin
if(iaddr==4'b0000) chaddr[0][7:0] <= idata;
if(iaddr==4'b0001) chtcnt[0][7:0] <= idata;
if(iaddr==4'b0010) chaddr[1][7:0] <= idata;
if(iaddr==4'b0011) chtcnt[1][7:0] <= idata;
if(iaddr==4'b0100) chaddr[2][7:0] <= idata;
if(iaddr==4'b0101) chtcnt[2][7:0] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][7:0] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][7:0] <= idata;
end
if (iaddr[3]) mode <= idata;
end
if (ce) begin
case (state)
ST_IDLE: begin
if (|mdrq) state <= ST_WAIT;
end
ST_WAIT: begin
if (hlda) state <= ST_T1;
casex (mdrq[3:1])
3'b1xx: channel <= 2'b11;
3'b01x: channel <= 2'b10;
3'b001: channel <= 2'b01;
3'b000: channel <= 2'b00;
endcase
end
ST_T1: begin
state <= ST_T2;
dack[channel] <= 1'b1;
end
ST_T2: begin
if (mdrq[channel]==0) begin
dack[channel] <= 0;
if (chtcnt[channel][13:0]==0) begin
chstate[channel] <= 1'b1;
if (mode[7]==1'b1 && channel==2'b10) begin
chaddr[channel] <= chaddr[2'b11];
chtcnt[channel][13:0] <= chtcnt[2'b11][13:0];
end
end else begin
chaddr[channel] <= chaddr[channel]+1'b1;
chtcnt[channel][13:0] <= chtcnt[channel][13:0]+14'h3FFF;
end
state <= ST_T3;
end
end
ST_T3: begin
state <= |mdrq ? ST_WAIT : ST_IDLE;
end
endcase
end
end
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module trigger_context_pkt
#(parameter BASE=0)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input packet_consumed, output reg trigger);
wire [23:0] cycles;
wire [15:0] packets;
wire [6:0] dummy1;
wire [14:0] dummy2;
wire enable_cycle, enable_consumed;
reg [30:0] cycle_count, packet_count;
setting_reg #(.my_addr(BASE+4), .at_reset(0)) sr_cycles
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_cycle,dummy1,cycles}),.changed());
setting_reg #(.my_addr(BASE+5), .at_reset(0)) sr_packets
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_consumed,dummy2,packets}),.changed());
always @(posedge clk)
if(reset | clear)
cycle_count <= 0;
else
if(trigger)
cycle_count <= 0;
else if(enable_cycle)
cycle_count <= cycle_count + 1;
always @(posedge clk)
if(reset | clear)
packet_count <= 0;
else
if(trigger)
packet_count <= 0;
else if(packet_consumed & enable_consumed)
packet_count <= packet_count + 1;
always @(posedge clk)
if(reset | clear)
trigger <= 0;
else
if((cycle_count > cycles)|(packet_count > packets))
trigger <= 1;
else
trigger <= 0;
endmodule // trigger_context_pkt
|
#include <bits/stdc++.h> using namespace std; long long n; long long k; long long a[200005]; long long s1; long long s2; long long inv[200005]; long long p; long long ans; long long quick_pow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res = res * x % 1000000007; x = x * x % 1000000007; n >>= 1; } return res; } int main() { scanf( %lld %lld , &n, &k); inv[1] = inv[0] = 1LL; for (long long i = 2; i <= n; i++) inv[i] = (1000000007 - 1000000007 / i) * inv[1000000007 % i] % 1000000007; for (long long i = 1; i <= n; ++i) inv[i] = inv[i - 1] * inv[i] % 1000000007; for (long long i = 1; i <= n; ++i) scanf( %lld , a + i); for (long long i = 0; i <= k; ++i) { long long fg = 1; if (i & 1) fg = -1; (s1 += fg * inv[i] * inv[k - i] % 1000000007 * quick_pow(k - i, n) % 1000000007) %= 1000000007; (s2 += fg * inv[i] * inv[k - i] % 1000000007 * quick_pow(k - i, n - 1) % 1000000007) %= 1000000007; } p = (s1 + s2 * (n - 1) % 1000000007) % 1000000007; p = (p + 1000000007) % 1000000007; for (long long i = 1; i <= n; ++i) ans = (ans + a[i] * p % 1000000007) % 1000000007; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int z; struct pi { bool operator()(const pair<int, int>& p, const pair<int, int>& q) { if (0) { } else if (abs(p.first - z) < abs(q.first - z)) { return 1; } else if (abs(p.first - z) > abs(q.first - z)) { return 0; } else { if (0) { } else if (p.first < q.first) { return 0; } else if (p.first > q.first) { return 1; } else { if (0) { } else if (p.first > z) { if (p.second < q.second) { return 1; } else { return 0; } } else if (p.first < z) { if (p.second < q.second) { return 0; } else { return 1; } } else { return 0; } } } } }; int main() { int i; int n, k; while (cin >> n >> k) { string s[10]; cin >> s[0]; for (i = 1; i < 10; ++i) s[i] = s[0]; pair<int, int> a[10][10100]; for (i = 0; i < n; ++i) a[0][i] = make_pair(s[0][i] - 0 , i); for (i = 1; i < 10; ++i) copy(a[0], a[0] + n, a[i]); int mn = 1 << 30, mnz; for (z = 0; z < 10; ++z) { sort(a[z], a[z] + n, pi()); int sm = 0; for (i = 0; i < k; ++i) { sm += abs(a[z][i].first - z); s[z][a[z][i].second] = 0 + z; } if (0) { } else if (mn > sm) { mn = sm; mnz = z; } else if (mn < sm) { } else { if (s[mnz] > s[z]) mnz = z; } } cout << mn << endl; cout << s[mnz] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { string s, t; cin >> s >> t; std::map<char, bool> ms, mt; for (int i = 0; i < s.size(); i++) { ms[s[i]] = true; mt[t[i]] = true; } for (char x = a ; x <= z ; x++) if (ms[x] && mt[x]) { cout << YES ; goto flag; } cout << NO ; flag: cout << endl; ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:55:37 06/19/2014
// Design Name:
// Module Name: CAR_CTR
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CAR_CTR(
output reg md1,
output reg md2,
output reg md3,
output reg md4,
input infL,
input infR,
input clk,
input reset_n
);
parameter FWD = 2'b00;
parameter STOP = 2'b01;
parameter RIGHT = 2'b10;
parameter LEFT = 2'b11;
parameter HIGH = 1'b1;
parameter LOW = 1'b0;
always @(*) begin
if (infL == LOW && infR == LOW) begin
// fwd
md1 = HIGH;
md2 = LOW;
md3 = HIGH;
md4 = LOW;
end else if (infL == HIGH && infR == LOW) begin
// right acc
md1 = LOW;
md2 = LOW;
md3 = HIGH;
md4 = LOW;
end else if (infL == LOW && infR == HIGH) begin
// left acc
md1 = HIGH;
md2 = LOW;
md3 = LOW;
md4 = LOW;
end else begin
// stop
md1 = LOW;
md2 = LOW;
md3 = LOW;
md4 = LOW;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreAHBLite default slave state machine logic for
// matrix (2 masters by 16 slaves)
//
// Revision Information:
// Date Description
// ---- -----------------------------------------
// 10Feb10 Production Release Version 3.1
//
// SVN Revision Information:
// SVN $Revision: 11955 $
// SVN $Date: 2010-01-30 15:35:13 -0800 (Sat, 30 Jan 2010) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4" (tabs used throughout file)
//
// *********************************************************************/
`timescale 1ns/1ps
module COREAHBLITE_DEFAULTSLAVESM
(
input HCLK,
input HRESETN,
input DEFSLAVEDATASEL,
output reg DEFSLAVEDATAREADY,
output reg HRESP_DEFAULT
);
localparam IDLE = 1'b0;
localparam HRESPEXTEND = 1'b1;
reg defSlaveSMNextState;
reg defSlaveSMCurrentState;
always @ ( * )
begin
DEFSLAVEDATAREADY = 1'b1;
HRESP_DEFAULT = 1'b0;
case ( defSlaveSMCurrentState )
IDLE:
begin
if ( DEFSLAVEDATASEL )
begin
DEFSLAVEDATAREADY = 1'b0;
HRESP_DEFAULT = 1'b1;
defSlaveSMNextState = HRESPEXTEND;
end
else
defSlaveSMNextState = IDLE;
end
HRESPEXTEND:
begin
HRESP_DEFAULT = 1'b1;
defSlaveSMNextState = IDLE;
end
default:
defSlaveSMNextState = IDLE;
endcase
end
always @ ( posedge HCLK or negedge HRESETN )
begin
if ( !HRESETN )
defSlaveSMCurrentState <= IDLE;
else
defSlaveSMCurrentState <= defSlaveSMNextState;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 2; int n; int a[N]; map<int, int> m; map<pair<int, int>, bool> checked; int main() { cin >> n; int zero = 0; for (int i = 0; i < n; ++i) { scanf( %d , a + i); if (!a[i]) zero++; ; m[a[i]]++; } sort(a, a + n); int ans = -1; int help1, help2, help3; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) if (i != j) { if (!a[i] and (!a[j])) continue; if (checked[make_pair(a[i], a[j])]) continue; checked[make_pair(a[i], a[j])] = true; map<int, int> m1; help3 = 2; m1[a[i]]++, m1[a[j]]++; help1 = a[i]; help2 = a[j]; while (m1[help1 + help2] < m[help1 + help2]) { m1[help1 + help2]++; help3++; help2 += help1; help1 = help2 - help1; } ans = max(ans, help3); } ans = max(ans, zero); cout << ans; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pci_exp_4_lane_64b_ep.v
// Version : 1.7
module v6_pcie_v1_7 (
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
pci_exp_txp,
pci_exp_txn,
// Rx
pci_exp_rxp,
pci_exp_rxn,
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
trn_clk,
trn_reset_n,
trn_lnk_up_n,
// Tx
trn_tbuf_av,
trn_tcfg_req_n,
trn_terr_drop_n,
trn_tdst_rdy_n,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_terrfwd_n,
trn_tcfg_gnt_n,
trn_tstr_n,
// Rx
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rerrfwd_n,
trn_rbar_hit_n,
trn_rdst_rdy_n,
trn_rnp_ok_n,
// Flow Control
trn_fc_cpld,
trn_fc_cplh,
trn_fc_npd,
trn_fc_nph,
trn_fc_pd,
trn_fc_ph,
trn_fc_sel,
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
cfg_do,
cfg_rd_wr_done_n,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_err_cor_n,
cfg_err_ur_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_locked_n,
cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_do,
cfg_interrupt_mmenable,
cfg_interrupt_msienable,
cfg_interrupt_msixenable,
cfg_interrupt_msixfm,
cfg_turnoff_ok_n,
cfg_to_turnoff_n,
cfg_trn_pending_n,
cfg_pm_wake_n,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
cfg_dcommand2,
cfg_pcie_link_state_n,
cfg_dsn,
cfg_pmcsr_pme_en,
cfg_pmcsr_pme_status,
cfg_pmcsr_powerstate,
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
pl_initial_link_width,
pl_lane_reversal_mode,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_link_upcfg_capable,
pl_ltssm_state,
pl_received_hot_rst,
pl_sel_link_rate,
pl_sel_link_width,
pl_directed_link_auton,
pl_directed_link_change,
pl_directed_link_speed,
pl_directed_link_width,
pl_upstream_prefer_deemph,
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
sys_clk,
sys_reset_n
); //synthesis syn_black_box
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(4 - 1):0] pci_exp_txp;
output [(4 - 1):0] pci_exp_txn;
// Rx
input [(4 - 1):0] pci_exp_rxp;
input [(4 - 1):0] pci_exp_rxn;
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
output trn_clk;
output trn_reset_n;
output trn_lnk_up_n;
// Tx
output [5:0] trn_tbuf_av;
output trn_tcfg_req_n;
output trn_terr_drop_n;
output trn_tdst_rdy_n;
input [63:0] trn_td;
input trn_trem_n;
input trn_tsof_n;
input trn_teof_n;
input trn_tsrc_rdy_n;
input trn_tsrc_dsc_n;
input trn_terrfwd_n;
input trn_tcfg_gnt_n;
input trn_tstr_n;
// Rx
output [63:0] trn_rd;
output trn_rrem_n;
output trn_rsof_n;
output trn_reof_n;
output trn_rsrc_rdy_n;
output trn_rsrc_dsc_n;
output trn_rerrfwd_n;
output [6:0] trn_rbar_hit_n;
input trn_rdst_rdy_n;
input trn_rnp_ok_n;
// Flow Control
output [11:0] trn_fc_cpld;
output [7:0] trn_fc_cplh;
output [11:0] trn_fc_npd;
output [7:0] trn_fc_nph;
output [11:0] trn_fc_pd;
output [7:0] trn_fc_ph;
input [2:0] trn_fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
output [31:0] cfg_do;
output cfg_rd_wr_done_n;
input [31:0] cfg_di;
input [3:0] cfg_byte_en_n;
input [9:0] cfg_dwaddr;
input cfg_wr_en_n;
input cfg_rd_en_n;
input cfg_err_cor_n;
input cfg_err_ur_n;
input cfg_err_ecrc_n;
input cfg_err_cpl_timeout_n;
input cfg_err_cpl_abort_n;
input cfg_err_cpl_unexpect_n;
input cfg_err_posted_n;
input cfg_err_locked_n;
input [47:0] cfg_err_tlp_cpl_header;
output cfg_err_cpl_rdy_n;
input cfg_interrupt_n;
output cfg_interrupt_rdy_n;
input cfg_interrupt_assert_n;
input [7:0] cfg_interrupt_di;
output [7:0] cfg_interrupt_do;
output [2:0] cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_turnoff_ok_n;
output cfg_to_turnoff_n;
input cfg_trn_pending_n;
input cfg_pm_wake_n;
output [7:0] cfg_bus_number;
output [4:0] cfg_device_number;
output [2:0] cfg_function_number;
output [15:0] cfg_status;
output [15:0] cfg_command;
output [15:0] cfg_dstatus;
output [15:0] cfg_dcommand;
output [15:0] cfg_lstatus;
output [15:0] cfg_lcommand;
output [15:0] cfg_dcommand2;
output [2:0] cfg_pcie_link_state_n;
input [63:0] cfg_dsn;
output cfg_pmcsr_pme_en;
output cfg_pmcsr_pme_status;
output [1:0] cfg_pmcsr_powerstate;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
output [2:0] pl_initial_link_width;
output [1:0] pl_lane_reversal_mode;
output pl_link_gen2_capable;
output pl_link_partner_gen2_supported;
output pl_link_upcfg_capable;
output [5:0] pl_ltssm_state;
output pl_received_hot_rst;
output pl_sel_link_rate;
output [1:0] pl_sel_link_width;
input pl_directed_link_auton;
input [1:0] pl_directed_link_change;
input pl_directed_link_speed;
input [1:0] pl_directed_link_width;
input pl_upstream_prefer_deemph;
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
input sys_clk;
input sys_reset_n;
endmodule // v6_pcie_v1_7
|
#include <bits/stdc++.h> using namespace std; int n, m, q; pair<int, int> t[300100]; pair<int, int> up[300100]; pair<int, int> down[300100]; pair<int, int> inter(pair<int, int> a, pair<int, int> b) { int f = max(a.first, b.first); int s = min(a.second, b.second); pair<int, int> res = {f, s}; return res; } long long int len(pair<int, int> a) { int res = a.second - a.first; if (res < 0) res = 0; return res; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> t[i].first >> t[i].second; down[0] = t[0]; up[n - 1] = t[n - 1]; for (int i = 0; i < n - 1; i++) down[i + 1] = inter(down[i], t[i + 1]); for (int i = n - 1; i > 0; i--) up[i - 1] = inter(up[i], t[i - 1]); long long int ma = -1; ma = max(ma, len(up[1])); ma = max(ma, len(down[n - 2])); for (int i = 1; i < n - 1; i++) { long long int a = len(inter(down[i - 1], up[i + 1])); ma = max(ma, a); } cout << ma; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
// CREATED "Wed Nov 06 13:56:51 2013"
module PPgen(
Single,
Yi,
Double,
Negate,
Yi_m1,
PPi
);
input wire Single;
input wire Yi;
input wire Double;
input wire Negate;
input wire Yi_m1;
output wire PPi;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
assign SYNTHESIZED_WIRE_1 = ~(Yi & Single);
assign SYNTHESIZED_WIRE_0 = ~(Yi_m1 & Double);
assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1);
assign PPi = SYNTHESIZED_WIRE_2 ^ Negate;
endmodule
|
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