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#include <bits/stdc++.h> using namespace std; long long n, k, q, a[200005], f[200005]; int main() { cin >> n >> k >> q; for (int i = 1; i <= n; i++) { long long l, r; cin >> l >> r; a[l]++; a[r + 1]--; } for (int i = 1; i <= 200000; i++) a[i] += a[i - 1]; for (int i = 1; i <= 200000; i++) { f[i] += f[i - 1]; if (a[i] >= k) { f[i]++; } } for (int i = 1; i <= q; i++) { long long l, r; cin >> l >> r; cout << f[r] - f[l - 1] << endl; } }
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#include <bits/stdc++.h> using namespace std; int a, b, c; int sisa(int x, int n) { if (x >= 0) return x % n; else if (abs(x) % n == 0) return 0; else return ((abs(x) / n) + 1) * n + x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> a >> b >> c; b += c; cout << (sisa(b, a) == 0 ? a : sisa(b, a)) << n ; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <class T> inline bool Min(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> inline bool Max(T &a, T b) { return a < b ? (a = b, true) : false; } inline int ni() { int a; scanf( %d , &a); return a; } inline ll nl() { ll a; scanf( %lld , &a); return a; } inline double nd() { double a; scanf( %lf , &a); return a; } inline void pi(int a) { printf( %d , a); } inline void pl(ll a) { printf( %lld , a); } inline void pd(double a) { printf( %.12lf , a); } const int N = 2e5 + 100; vector<int> gp[N]; bool is_university[N]; int n, k; int cnt[N]; ll ans = 0; void dfs(int v, int p) { cnt[v] = is_university[v]; for (int next : gp[v]) if (next != p) dfs(next, v), cnt[v] += cnt[next], ans += min(cnt[next], k + k - cnt[next]); } void solve() { n = ni(); k = ni(); for (int i = 0; i < (int)(k + k); ++i) is_university[ni()] = true; for (int i = 0; i < (int)(n - 1); ++i) { int a = ni(); int b = ni(); gp[a].push_back(b); gp[b].push_back(a); } dfs(1, 1); pl(ans); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_LP__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_FUNCTIONAL_V
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
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#include <bits/stdc++.h> template <class T> T abs(T x) { return x > 0 ? x : -x; } const int MAXINT = 1111 * 1111 * 1111; const long long MAXLINT = MAXINT * 1ll * MAXINT; const long double EPS = 1e-10; using namespace std; int n, m, x, y, z, p; int a, b; void reverse_left() { int aa = a, bb = b; a = m - b + 1; b = aa; swap(n, m); } void reverse_middle() { b = m - b + 1; } void reverse_right() { int aa = a, bb = b; b = n - a + 1; a = bb; swap(n, m); } void solve() { cin >> n >> m >> x >> y >> z >> p; int N = n, M = m; x %= 4; z %= 4; y %= 2; while (p--) { n = N; m = M; cin >> a >> b; for (int i = 0; i < x; i++) reverse_right(); for (int i = 0; i < y; i++) reverse_middle(); for (int i = 0; i < z; i++) reverse_left(); cout << a << << b << endl; } } int main() { solve(); }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const double eps = 1e-9; vector<long long> prnum; void sieve() { bool prime[1000001]; memset(prime, true, sizeof(prime)); for (int i = 2; i * i <= 1000000; i++) { if (prime[i] == true) { for (int j = 2 * i; j <= 1000000; j += i) { prime[j] = false; } } } for (int i = 2; i <= 1000000; i++) { if (prime[i]) prnum.push_back(i); } } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { long long n, k; cin >> n >> k; if (k >= n) { cout << 1 << n ; } else { long long ans = 1000000000; for (long long i = 1; i * i <= n; i++) { if (i > k) break; if (n % i == 0) { if ((n / i) <= k) { ans = min(ans, i); } else { ans = min(ans, n / i); } } } cout << ans << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans % m; } int bit[100005]; int n; int a[100005]; int lis[100005]; void update(int x, int val) { for (int i = x; i < 100005; i += (i & -i)) bit[i] = max(bit[i], val); } int read(int x) { int res = 0; for (int i = x; i; i -= (i & -i)) res = max(res, bit[i]); return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; int ans = 0; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { lis[i] = read(a[i] - 1) + 1; update(a[i], lis[i]); ans = max(ans, lis[i]); } cout << ans; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long a, b; cin >> a >> b; if (a == 0 || b == 0) { cout << 0 << endl; return; } cout << min((a + b) / 3, min(a, b)) << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); int tc = 1; cin >> tc; while (tc--) solve(); }
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#include <bits/stdc++.h> using namespace std; int n, m, k; int mid = 0; int num = 0; int e[21][21]; int flag[21]; void dfs(int x, int sum) { if (x > n) { num = num + 1; return; } dfs(x + 1, sum); for (int y = 1; y <= n; y++) { if (num > k) { break; } if (flag[y] == 0 && e[x][y] != 0 && sum + e[x][y] <= mid) { flag[y] = 1; dfs(x + 1, sum + e[x][y]); flag[y] = 0; } } return; } int main() { int u, v, w; cin >> n >> m >> k; int l = 0; int h = 1000 * n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { e[i][j] = 0; } } for (int i = 0; i < m; i++) { cin >> u >> v >> w; e[u][v] = w; } while (l < h) { mid = (l + h) / 2; num = 0; dfs(1, 0); if (num < k) { l = mid + 1; } else { h = mid; } } cout << l << endl; }
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#include <bits/stdc++.h> using namespace std; int M = 998244353; int pow(int a, int b) { if (b == 0) { return 1; } if (b % 2) { return ((long long)a * pow(a, b - 1)) % M; } else { int temp = pow(a, b / 2); return ((long long)temp * temp) % M; } } int inv[3010]; int w[55]; int a[55]; int dp1[55][55][55]; int dp2[55][55][55]; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < 3010; i++) { inv[i] = pow(i, M - 2); } for (int i = 0; i < n; i++) { cin >> a[i]; } int s = 0, s1 = 0, s2 = 0; for (int i = 0; i < n; i++) { cin >> w[i]; s += w[i]; if (a[i]) { s1 += w[i]; } } s2 = s - s1; for (int i = 0; i < n; i++) { dp1[i][0][0] = 1; } for (int l = 0; l < m; l++) { for (int i = 0; i < n; i++) { for (int j = 0; j < 55; j++) { for (int k = 0; k < 55; k++) { if (a[i]) { dp2[i][j][k] = (long long)dp1[i][j][k] * (s2 - l + j) % M * inv[s + 2 * j - l] % M; if (k && j) dp2[i][j][k] = (dp2[i][j][k] + (long long)dp1[i][j - 1][k - 1] * (w[i] + k - 1) % M * inv[s + 2 * j - l - 2] % M) % M; if (j) dp2[i][j][k] = (dp2[i][j][k] + (long long)dp1[i][j - 1][k] * (s1 + j - w[i] - k - 1) % M * inv[s + 2 * j - 2 - l] % M) % M; } else { dp2[i][j][k] = (long long)dp1[i][j][k] * (s2 - l + j - (w[i] - k)) % M * inv[s + 2 * j - l] % M; if (k) dp2[i][j][k] = (dp2[i][j][k] + (long long)dp1[i][j][k - 1] * (w[i] - (k - 1)) % M * inv[s + 2 * j - l] % M) % M; if (j) dp2[i][j][k] = (dp2[i][j][k] + (long long)dp1[i][j - 1][k] * (s1 + j - 1) % M * inv[s + 2 * j - 2 - l] % M) % M; } } } } for (int i = 0; i < 55; i++) { for (int j = 0; j < 55; j++) { for (int k = 0; k < 55; k++) { dp1[i][j][k] = dp2[i][j][k]; } } } } for (int i = 0; i < n; i++) { int ans = 0; for (int j = 0; j < 55; j++) { for (int k = 0; k < 55; k++) { if (a[i]) { int temp = (long long)(w[i] + k) * dp1[i][j][k] % M; ans = (ans + temp) % M; } else { int temp = (long long)(w[i] - k) * dp1[i][j][k] % M; ans = (ans + temp) % M; } } } cout << ans << endl; } }
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module jbasicgatestb;
wire yOR,yAND,yXOR,yNOR,yNAND,yXNOR;
reg a,b;
jbasicgates jbgs(yOR,yAND,yXOR,yNOR,yNAND,yXNOR,a,b);
initial
begin
$display("RSLT\ta\tb\tOR\tAND\tXOR\tNOR\tNAND\tXNOR");
a = 0; b = 0; #50; // Assign values and some delay
if ( (yOR == 0) && (yAND == 0) && (yXOR == 0) && (yNOR == 1) && (yNAND == 1) && (yXNOR == 1) ) // Test for inversion
$display("PASS\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
else
$display("FAIL\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
a = 0; b = 1; #50; // Assign values and some delay
if ( (yOR == 1) && (yAND == 0) && (yXOR == 1) && (yNOR == 0) && (yNAND == 1) && (yXNOR == 0) ) // Test for inversion
$display("PASS\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
else
$display("FAIL\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
a = 1; b = 0; #50; // Assign values and some delay
if ( (yOR == 1) && (yAND == 0) && (yXOR == 1) && (yNOR == 0) && (yNAND == 1) && (yXNOR == 0) ) // Test for inversion
$display("PASS\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
else
$display("FAIL\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
a = 1; b = 1; #50; // Assign values and some delay
if ( (yOR == 1) && (yAND == 1) && (yXOR == 0) && (yNOR == 0) && (yNAND == 0) && (yXNOR == 1) ) // Test for inversion
$display("PASS\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
else
$display("FAIL\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",a,b,yOR,yAND,yXOR,yNOR,yNAND,yXNOR);
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n, x = 4, y = 5; scanf( %d , &n); if (n == 1 || n == 2) { cout << 1; return 0; } while (y < n) { if (x & 1) x = 2 * y, y = x + 1; else x = 2 * y - 1, y = x + 1; } printf( %d , (x == n || y == n)); return 0; }
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`timescale 1ns/1ns
module testbench;
parameter t_c = 10;
reg clk;
reg rst;
reg pro_done=0;
wire done;
//wire start_ok;
initial begin
$fsdbDumpfile("wave_test.fsdb");
$fsdbDumpvars;
end
always begin //clk gen
clk = 1'b1; #(t_c/2);
clk = 1'b0; #(t_c/2);
end
initial begin //reset gen
rst = 1'b1;
#(2.5*t_c) rst = 1'b0;
// @(posedge pro_done);//wait process done
// $stop;
end
wire [31:0] dat_out;
wire ack_out;
reg cyc_i;
reg stb_i;
reg we;
wire [31:0] dat_i;
//reg [31:0] adr;
initial begin
cyc_i = 1'b0;
stb_i = 1'b0;
we = 0;
// adr = 32'd0;
end
reg [21:0] mem_adr_i;
reg [3:0] state;
reg teststart;
initial teststart = 0;
reg start;
//reg readstart;
initial begin
// readstart = 0;
start = 0;
#(4.5*t_c) teststart = 1'b1;
#(2*t_c) teststart = 0;
end
always @(posedge done) begin
pro_done<= 1;
end
sobel sobel_inf(
.rst_i(rst),
.clk_i(clk),
.cyc_i(cyc_i),
.stb_i(stb_i),
.adr_in(mem_adr_i),
.we(we),
.dat_in(dat_i),
// .readstart(readstart),
.start(start),
.dat_out(dat_out),
.ack_out(ack_out),
// .start_ok(start_ok),
.done(done));
always @ (posedge clk or posedge rst) begin
if (rst) begin
state <= 0;
mem_adr_i <= 0;
cyc_i <= 0;
stb_i <= 0;
end
else begin
case(state)
4'b0000: begin
state <= 4'b0000;
mem_adr_i <= 0;
cyc_i <= 0;
start <= 0;
we <= 1;
if (teststart == 1)
state <= 4'b0001;
end
4'b0001: begin
// mem_adr_i <= mem_adr_i + 4;
cyc_i <= 1;
stb_i <= 1;
state <= 4'b0010;
end
4'b0010:begin
if(ack_out) begin
stb_i <= 0;
state <= 4'b0011;
end
else
state <= 4'b0010;
end
4'b0011:begin
mem_adr_i <= mem_adr_i+4;
stb_i <= 1;
if(mem_adr_i >= 22'h4b000) begin
cyc_i <= 0;
stb_i <= 0;
state <= 4'b0100;
end
else
state <= 4'b0010;
end
4'b0100: begin
start <= 1;
mem_adr_i <= 0;
if(pro_done) begin
start <= 0;
we <= 0;
state <= 4'b0101;
end
else
state <= 4'b0100;
end
4'b0101:begin
cyc_i <= 1;
stb_i <= 1;
state <= 4'b0110;
end
4'b0110:begin
if(ack_out) begin
stb_i <= 0;
state <= 4'b0111;
end
else
state <= 4'b0110;
end
4'b0111:begin
mem_adr_i <= mem_adr_i+4;
stb_i <= 1;
if(mem_adr_i >= 22'h4ab00) begin
$stop;
end
else
state <=4'b0110;
end
endcase
end
end
DMAtest DMAtest1( .clk(clk),
.rst(rst),
.we(!we),
.ack_out(ack_out),
.readstart(cyc_i),
.done(pro_done),
.mem_adr_i(mem_adr_i),
.mem_dat_o(dat_i),
.mem_dat_i(dat_out)
);
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 200007; const int mod = 998244353; long long fast_pow(long long b, int k) { long long s = 1; while (k) { if (k & 1) (s *= b) %= mod; (b *= b) %= mod; k >>= 1; } return s; } long long fact[maxn]; int N; int A[maxn]; int sum[maxn], sum0[maxn]; int C[maxn]; void update(int x) { while (x <= N) C[x]++, x += x & (-x); return; } int query(int x) { int re = 0; while (x) re += C[x], x &= (x - 1); return re; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d , &A[i]); if (A[i] == -1) A[i] = 0; sum0[i] += sum0[i - 1] + (A[i] == 0); if (A[i] > N) { printf( 0 ); return 0; } sum[A[i]]++; } for (int i = 2; i <= N; i++) sum[i] += sum[i - 1]; fact[0] = 1; for (int i = 1; i <= N; i++) fact[i] = fact[i - 1] * i % mod; long long x, y; long long ans = 0; if (sum[0]) for (int i = 1; i <= N; i++) { if (A[i] == 0) continue; x = A[i] - sum[A[i]]; y = sum0[N] - sum0[i]; (ans += x * y % mod * fact[sum[0] - 1] % mod) %= mod; x = (N - A[i]) - (sum[N] - sum[A[i]]); y = sum0[i]; (ans += x * y % mod * fact[sum[0] - 1] % mod) %= mod; } x = 1ll * sum[0] * (sum[0] - 1) / 2 % mod; if (sum[0] > 1) y = fact[sum[0] - 2]; else y = 0; (ans += y * x % mod * x % mod) %= mod; y = 0; for (int i = 1; i <= N; i++) { if (A[i] == 0) continue; x = query(N) - query(A[i]); (y += x) %= mod; update(A[i]); } if (sum[0] > 0) x = fact[sum[0]]; else x = 1; (ans += y * x % mod) %= mod; (ans *= fast_pow(fact[sum[0]], mod - 2)) %= mod; printf( %lld , ans); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; inline int read() { int x = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c <= 9 && c >= 0 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return w == 1 ? x : -x; } int n, cnt, tot, l[800005], r[800005], a[800005 << 1], lx[800005], rx[800005], p[800005], t[800005], p2[800005], h[800005]; int main() { int T = read(); while (T--) { n = read(); cnt = 0; tot = 0; for (int i = 1; i <= n; i++) { l[i] = read(), r[i] = read(); a[++cnt] = l[i], a[++cnt] = r[i]; } sort(a + 1, a + cnt + 1); tot = unique(a + 1, a + cnt + 1) - a - 1; for (int i = 1; i <= n; i++) { lx[i] = lower_bound(a + 1, a + tot + 1, l[i]) - a; rx[i] = lower_bound(a + 1, a + tot + 1, r[i]) - a; lx[i] <<= 1; rx[i] <<= 1; } int tmp = 0; for (int i = 1; i <= tot * 2; i++) p2[i] = 0, h[i] = 0, p[i] = 0; for (int i = 1; i <= tot * 2; i++) t[i] = 0; for (int i = 1; i <= n; i++) t[lx[i]]++, t[rx[i] + 1]--; for (int i = 1; i <= tot * 2; i++) tmp += t[i], p[i] = tmp; for (int i = 1; i <= tot * 2; i++) if (p[i] != p[i - 1] && p[i] == 1) p2[i] = 1; for (int i = 1; i <= tot * 2; i++) h[i] = h[i - 1] + p2[i]; int ans = -1e9, ans1 = 0; for (int i = 1; i <= tot * 2 + 1; i++) if (p[i] != 0 && p[i - 1] == 0) ans1++; for (int i = 1; i <= n; i++) { int q = h[rx[i]] - h[lx[i] - 1]; q -= (p[rx[i]] == 1), q -= (p[lx[i]] == 1); ans = max(ans, q); } cout << ans1 + ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[10000006]; int main() { long long n, x, y; scanf( %lld%lld%lld , &n, &x, &y); for (int i = 0; i <= n; ++i) dp[i] = 1e18 + 100; dp[1] = x; for (int i = 2; i <= n; ++i) { if (i % 2 == 1) dp[i] = min(dp[i - 1] + x, min(dp[i / 2] + y + x, dp[i / 2 + 1] + y + x)); else dp[i] = min(dp[i - 1] + x, dp[i / 2] + y); } printf( %lld n , dp[n]); return 0; }
|
#include <bits/stdc++.h> int v[1000005]; int main() { int i, j, k; int n, m, a, b; int f[1010]; while (~scanf( %d , &n)) { memset(v, 0, sizeof(v)); a = b = 0; for (i = 0; i < n; i++) { scanf( %d , &f[i]); v[f[i]]++; if (v[f[i]] > b) { a = f[i]; b = v[f[i]]; } } printf( %d n , a); } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 21 11:24:56 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[31:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[31:0],probe16[0:0],probe17[0:0],probe18[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [31:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [31:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long modinverse(long long a, long long m) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m, t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long mod_pow(long long a, long long n, long long p) { long long ans = 1; while (n) { if (n & 1) ans = (ans * a) % p; a = (a * a) % p; n >>= 1; } return ans; } long long prime_mod_pow(long long a, long long n, long long p) { long long ans = 1; n %= p - 1; while (n) { if (n & 1) ans = (ans * a) % p; a = (a * a) % p; n >>= 1; } return ans; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long ext_gcd(long long l, long long r, long long &x, long long &y) { if (l == 0) { x = 0; y = 1; return r; } long long x1, y1, g; g = ext_gcd(r % l, l, x1, y1); x = y1 - (r / l) * x1; y = x1; return g; } const long long dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; long long ok(long long x, long long y, long long n, long long m) { return (x >= 0 and y >= 0 and x < n and y < m); } long long num_div; map<long long, long long> pr_factor; void factorise(long long n) { long long count = 0; while (!(n % 2)) { n >>= 1; count++; } if (count) num_div *= (count + 1); pr_factor[2] = count; for (long long i = 3; i <= sqrt(n); i += 2) { count = 0; while (n % i == 0) { count++; n /= i; } if (count) num_div *= (count + 1); pr_factor[i] = count; } if (n > 2) num_div *= 2; pr_factor[n] = 1; } bool type1(long long x1, long long x2, long long x3, long long y1, long long y2, long long y3, char c1, char c2, char c3) { if (x1 == x2 + x3 and y2 == y3 and x1 == y1 + y2) { cout << x1 << n ; for (long long i = 0; i < y1; i++) { for (long long j = 0; j < x1; j++) cout << c1; cout << n ; } for (long long i = 0; i < y2; i++) { for (long long j = 0; j < x2; j++) cout << c2; for (long long j = 0; j < x3; j++) cout << c3; cout << n ; } return true; } return false; } bool type2(long long x1, long long x2, long long x3, long long y1, long long y2, long long y3, char c1, char c2, char c3) { if (x1 == x2 and x2 == x3 and x1 == y1 + y2 + y3) { cout << x1 << n ; for (long long i = 0; i < y1; i++) { for (long long j = 0; j < x1; j++) cout << c1; cout << n ; } for (long long i = 0; i < y2; i++) { for (long long j = 0; j < x1; j++) cout << c2; cout << n ; } for (long long i = 0; i < y3; i++) { for (long long j = 0; j < x3; j++) cout << c3; cout << n ; } return true; } return false; } void solve() { long long x1, x2, x3, y1, y2, y3; cin >> x1 >> y1 >> x2 >> y2 >> x3 >> y3; vector<pair<long long, long long> > a; a.push_back(make_pair(x1, y1)); a.push_back(make_pair(y1, x1)); vector<pair<long long, long long> > b; b.push_back(make_pair(x2, y2)); b.push_back(make_pair(y2, x2)); vector<pair<long long, long long> > c; c.push_back(make_pair(x3, y3)); c.push_back(make_pair(y3, x3)); for (long long i = 0; i < a.size(); i++) { long long X1 = a[i].first, Y1 = a[i].second; for (long long j = 0; j < b.size(); j++) { long long X2 = b[j].first, Y2 = b[j].second; for (long long k = 0; k < c.size(); k++) { long long X3 = c[k].first, Y3 = c[k].second; if (type1(X1, X2, X3, Y1, Y2, Y3, A , B , C )) return; if (type1(X1, X3, X2, Y1, Y3, Y2, A , C , B )) return; if (type1(X2, X1, X3, Y2, Y1, Y3, B , A , C )) return; if (type1(X2, X3, X1, Y2, Y3, Y1, B , C , A )) return; if (type1(X3, X1, X2, Y3, Y1, Y2, C , A , B )) return; if (type1(X3, X2, X1, Y3, Y2, Y1, C , B , A )) return; if (type2(X1, X2, X3, Y1, Y2, Y3, A , B , C )) return; if (type2(X1, X3, X2, Y1, Y3, Y2, A , C , B )) return; if (type2(X2, X1, X3, Y2, Y1, Y3, B , A , C )) return; if (type2(X2, X3, X1, Y2, Y3, Y1, B , C , A )) return; if (type2(X3, X1, X2, Y3, Y1, Y2, C , A , B )) return; if (type2(X3, X2, X1, Y3, Y2, Y1, C , B , A )) return; } } } cout << -1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; long long tc = 1; while (t--) { solve(); tc++; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_1r1w_rf4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_1r1w_rf4
// Description: 1r1w regfile emulated using FF's.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_1r1w_rf4 (/*AUTOARG*/
// Outputs
dout,
// Inputs
rd_clk, wr_clk, rd_a, wr_a, din, wen_l
);
parameter REG_WIDTH = 64;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input rd_clk;
input wr_clk;
input [1:0] rd_a;
input [1:0] wr_a;
input [REG_WIDTH-1:0] din;
input wen_l;
output [REG_WIDTH-1:0] dout;
wire [1:0] wr_a_d1;
wire [REG_WIDTH-1:0] din_d1;
wire wen_l_d1;
wire [3:0] wr_a_dec_d1;
wire [3:0] wen_dec_d1;
wire [REG_WIDTH-1:0] line0;
wire [REG_WIDTH-1:0] line1;
wire [REG_WIDTH-1:0] line2;
wire [REG_WIDTH-1:0] line3;
wire [1:0] rd_a_d1;
reg [REG_WIDTH-1:0] dout;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Flop write address, write data and write enable
dff_ns #(2) wr_a_d1_ff (.din(wr_a),
.clk(wr_clk),
.q(wr_a_d1));
dff_ns #(REG_WIDTH) din_d1_ff (.din(din),
.clk(wr_clk),
.q(din_d1));
dff_ns #(1) wen_l_d1_ff (.din(wen_l),
.clk(wr_clk),
.q(wen_l_d1));
assign wr_a_dec_d1 = 1'b1 << wr_a_d1;
assign wen_dec_d1 = {4{~wen_l_d1}} & wr_a_dec_d1;
// FF's for storage
dffe_ns #(REG_WIDTH) line0_ff (.din(din_d1),.en(wen_dec_d1[0]),.clk(wr_clk),.q(line0));
dffe_ns #(REG_WIDTH) line1_ff (.din(din_d1),.en(wen_dec_d1[1]),.clk(wr_clk),.q(line1));
dffe_ns #(REG_WIDTH) line2_ff (.din(din_d1),.en(wen_dec_d1[2]),.clk(wr_clk),.q(line2));
dffe_ns #(REG_WIDTH) line3_ff (.din(din_d1),.en(wen_dec_d1[3]),.clk(wr_clk),.q(line3));
// Flop read address
dff_ns #(2) rd_a_d1_ff (.din(rd_a),
.clk(rd_clk),
.q(rd_a_d1));
// Mux out read data
always @(/*AUTOSENSE*/line0 or line1 or line2 or line3 or rd_a_d1) begin
case (rd_a_d1)
2'd0: dout = line0;
2'd1: dout = line1;
2'd2: dout = line2;
2'd3: dout = line3;
default: dout = {REG_WIDTH{1'bx}};
endcase // case(rd_a_d1)
end
endmodule // iobdg_1r1w_rf4
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Used by the SD card reader to receive data responses from the
* SPI flash interface and store them in RAM.
*
* @author Robert Fotino, 2016
*/
`include "../definitions.vh"
module spi_data_reader
(
input clk,
input calib_done,
input sclk_posedge,
input sclk_negedge,
input [6:0] block_addr,
input en,
input in,
output reg error,
output done,
// Signals for writing to RAM
output reg mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
// Initialize outputs
initial begin
error = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
end
// Our interface with RAM is write-only, so always give the
// write command (000)
assign mem_cmd_instr = 3'b000;
// We always want to write 128-byte blocks to RAM, so always
// use a burst length of 32 32-bit words
assign mem_cmd_bl = 6'b011111;
// We also always want to write 32-bit words, so don't mask
// any bytes
assign mem_wr_mask = 4'b0000;
// Keep track of which bit we are on, so that we always
// start at bit 7 for synchonous byte-oriented communication
reg [2:0] bit_counter = 7;
always @ (posedge clk) begin
if (sclk_negedge) begin
bit_counter <= bit_counter - 1;
end
end
// Keep track of the current byte. Once 8 bits have been read in,
// the valid flag goes high for one cycle
reg [7:0] cur_byte = 8'hFF;
reg cur_byte_valid = 0;
always @ (posedge clk) begin
cur_byte_valid <= 0;
if (sclk_posedge) begin
cur_byte[bit_counter] <= in;
if (0 == bit_counter) begin
cur_byte_valid <= 1;
end
end
end
// State machine logic
localparam STATE_IDLE = 0;
localparam STATE_TOKEN = 1;
localparam STATE_BLOCK = 2;
localparam STATE_CRC = 3;
localparam STATE_FLUSH = 4;
localparam STATE_ERROR = 5;
reg [2:0] state = STATE_IDLE;
reg [8:0] byte_counter = 0;
reg crc_counter = 0;
reg [6:0] block_addr_reg = 0;
assign done = (STATE_IDLE == state) && !en;
always @ (posedge clk) begin
// Default to disabled signals
mem_cmd_en <= 0;
mem_wr_en <= 0;
case (state)
// Wait here until we get the enabled signal
STATE_IDLE: begin
if (en) begin
state <= STATE_TOKEN;
byte_counter <= 0;
crc_counter <= 0;
block_addr_reg <= block_addr;
end
end
// Wait until we see 0xFE to start the data, or an error token
// (error tokens start with 0b000)
STATE_TOKEN: begin
if (cur_byte_valid) begin
if (8'hFE == cur_byte) begin
state <= STATE_BLOCK;
end else if (3'b000 == cur_byte[7:5]) begin
state <= STATE_ERROR;
end
end
end
// Consume the data block and store it in RAM
STATE_BLOCK: begin
if (cur_byte_valid) begin
mem_wr_data <= { mem_wr_data[23:0], cur_byte };
// Check if we have read a 4-byte chunk
if (3 == byte_counter[1:0]) begin
mem_wr_en <= 1;
end
// Check if we have read 128 bytes and are ready to write
// to RAM
if (127 == byte_counter[6:0]) begin
mem_cmd_en <= 1;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, block_addr_reg,
byte_counter[8:7], 7'b0 };
end
// Increment the byte counter, or move onto the next state if
// we've read all 512 bytes
if (511 == byte_counter) begin
state <= STATE_CRC;
end else begin
byte_counter <= byte_counter + 1;
end
end
end
// Consume the 2-byte CRC, but don't do any verification
STATE_CRC: begin
if (cur_byte_valid) begin
if (crc_counter) begin
state <= STATE_FLUSH;
end
crc_counter <= ~crc_counter;
end
end
// Wait until the write FIFO is empty
STATE_FLUSH: begin
if (mem_wr_empty) begin
state <= STATE_IDLE;
end
end
// An error occurred - no recovery mechanism right now.
STATE_ERROR: begin
error <= 1;
end
endcase
// If we have a memory write error or underrun, go to the error state
if (calib_done && (mem_wr_error || mem_wr_underrun)) begin
state <= STATE_ERROR;
end
end
endmodule
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 06/14/2014 at 20:26
// Component: CD32Shifter
module CD32Shifter (
output db9_6_out,
output db9_9_oe,
output db9_9_out,
input clock,
input db9_5_in,
input db9_6_in
);
//`#start body` -- edit after this line, do not edit this line
// Your code goes here
localparam OPERATION_SHIFT=3'b000;
localparam OPERATION_NOP=3'b001;
localparam OPERATION_LOAD=3'b010;
localparam OPERATION_LOADSHIFT=3'b011;
reg[2:0] operation;
localparam STATE_IDLE=2'b00;
localparam STATE_SHIFT1=2'b01;
localparam STATE_SHIFT2=2'b11;
reg[1:0] shiftstate;
wire mode;
assign mode=db9_5_in; // Shift register enable signal on DB9 pin 5.
wire shift;
assign shift=db9_6_in; // Shift register clock signal on DB9 pin 6.
wire firebutton; // Gets its value from the DataPath z1 signal (1 when A1=0).
// If the mode signal is high, then buttons 0 and 1 are passed through to DB9 pins 6 and 9, respectively
// If the mode signal is low, then the output of the shifter is passed to DB9 pin 9,
// while pin 6 becomes a clock signal.
wire shifted_data;
assign db9_9_out = shifted_data;
assign db9_6_out = mode ? firebutton : 1'b1;
// Need to use strong drive on pin 9 for speed, so for safety we avoid driving the
// pin high when not actively shifting.
assign db9_9_oe = ((shiftstate!=STATE_IDLE) | shifted_data==1'b0);
// FIXME - do we need more filtering on DB9_6_in?
always @(posedge clock)
begin
if(shiftstate==STATE_IDLE)
begin
shiftstate<=STATE_IDLE;
// Contintually load the current button status into the shift register while idle.
// This allows the first button's status to reach the s0 signal.
operation<=OPERATION_LOAD;
// Wait for mode signal to drop. When it does, start shifting.
if(mode==1'b0 && shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
end
else if(shiftstate==STATE_SHIFT1)
begin
operation<=OPERATION_NOP;
// Wait for posedge of the shift signal, shift data on transition.
if(shift==1'b1)
begin
shiftstate<=STATE_SHIFT2;
operation<=OPERATION_SHIFT;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else if(shiftstate==STATE_SHIFT2)
begin
operation<=OPERATION_NOP;
// Wait for negedge of the shift signal.
if(shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else
shiftstate<=STATE_IDLE;
end
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: SHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: NOP*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: LOAD*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: LOADSHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'hFF, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) CD32Shifter_DP(
/* input */ .reset(1'b0),
/* input */ .clk(clock),
/* input [02:00] */ .cs_addr(operation),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(firebutton), // We use A1 to bring the fire button's status into the component
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(shifted_data),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_SYMBOL_V
`define SKY130_FD_SC_LP__AND4_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_TB_V
`define SKY130_FD_SC_LS__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 16:48:52 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [3:0]probe5;
endmodule
|
module lab5(CLK, RESET, IOA, IOB, IOC, EN_L, PC, NextPC, Iin, DataA, DataB, DataC, DataD, Din, MW, IOD, IOE, IOF, IOG);
input CLK;
input RESET;
input [7:0] IOA;
input [7:0] IOB;
input [7:0] IOC;
input EN_L;
output [7:0] PC;
output [7:0] NextPC;
output [15:0] Iin;
output [7:0] DataA;
output [7:0] DataB;
output [7:0] DataC;
output [7:0] DataD;
output [7:0] Din;
output MW;
output [7:0] IOD;
output [7:0] IOE;
output [7:0] IOF;
output [7:0] IOG;
cpu proc(
.CLK(CLK),
.RESET(RESET),
.PC(PC),
.NextPC(NextPC),
.Iin(Iin),
.DataA(DataA),
.DataB(DataB),
.DataC(DataC),
.DataD(DataD),
.Din(Din),
.MW(MW),
.EN_L(EN_L)
);
// BELOW IS THE ONLY LINE YOU SHOULD HAVE TO MODIFY IN THIS FILE
lab5iram1B program2run(
.CLK(CLK),
.RESET(RESET),
.ADDR(PC),
.Q(Iin)
);
lab5dram memory(
.CLK(CLK),
.RESET(RESET),
.ADDR(DataD),
.DATA(DataB),
.MW(MW),
.Q(Din),
.IOA(IOA),
.IOB(IOB),
.IOC(IOC),
.IOD(IOD),
.IOE(IOE),
.IOF(IOF),
.IOG(IOG)
);
endmodule
|
// AJ, Beck, and Ray
// ALUnit testbench
// 5/4/15
`include "adder_subtractor.v"
`include "flag.v"
`include "mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "ALUnit.sv"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
module ALUnittest();
// localize variables
wire clk; // Clock
wire [2:0] control;
wire [31:0] busADD;
wire [31:0] busA, busB;
wire zero, overflow, carryout, negative;
// declare an instance of the module
ALUnit ALUnit (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
// Running the GUI part of simulation
ALUnittester tester (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
// file for gtkwave
initial
begin
$dumpfile("ALUnittest.vcd");
$dumpvars(1, ALUnit);
end
endmodule
module ALUnittester (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
output clk; // Clock
output [2:0] control;
input [31:0] busADD;
output reg [31:0] busA, busB;
input zero, overflow, carryout, negative;
parameter d = 20;
// generate a clock
always #(d/2) clk = ~clk;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zero \t overflow \t carryout \t negative \t ");
#d;
end
reg [31:0] i;
always @(posedge clk) // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zero, overflow, carryout, negative, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int ans = 1e9; for (int i = 0; i < n - 1; i++) if (s[i] == R && s[i + 1] == L ) ans = min(ans, (a[i + 1] - a[i]) / 2); if (ans == 1e9) cout << -1 << endl; else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); vector<vector<long long>> a(n); for (int i = 0; i < n; i++) { int m; long long p; scanf( %d , &m); scanf( %lld , &p); a[m].push_back(p); } vector<int> cnt(n); cnt[0] = a[0].size(); for (int i = 1; i < n; i++) { cnt[i] = cnt[i - 1] + a[i].size(); } long long res = 0; multiset<long long> s; int ch = 0; for (int i = n - 1; i > 0; i--) { for (long long j : a[i]) s.insert(j); int temp = 0; for (int j = 0; j < i - ch - cnt[i - 1]; j++) { long long p = *(s.begin()); s.erase(s.begin()); res += p; temp++; } ch += temp; } printf( %lld n , res); } }
|
// $Revision: $ $Date: $
//-----------------------------------------------------------------------------
// (c) Copyright 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------
/*
Module Description:
This is the top level of a bridge from AXI4-Streaming to Video Out
(Data, Hsync, Vsync, Data Enable)
------------------------------------------------------------------------------
*/
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module v_axi4s_vid_out_v3_0_axi4s_vid_out_top
#(
parameter C_S_AXIS_VIDEO_DATA_WIDTH = 8,
parameter C_S_AXIS_VIDEO_FORMAT = 2,
parameter VID_OUT_DATA_WIDTH = 24,
parameter C_S_AXIS_VIDEO_TDATA_WIDTH = 24,
parameter RAM_ADDR_BITS = 10, // default depth = 1024(10) min = 32 (5)
parameter HYSTERESIS_LEVEL = 12, // min 12
parameter FILL_GUARDBAND = 3,
parameter VTG_MASTER_SLAVE = 0 //timing mode, 1= VTG master,0 = VTG is slave
)
(
// AXI4-streaming interface
input wire aclk, // axi-4 S clock
input wire rst, // general reset
input wire aclken, // axi-4 clock enable
input wire aresetn, // axi-4 reset active low
input wire [C_S_AXIS_VIDEO_TDATA_WIDTH-1:0] s_axis_video_tdata , // axi-4 S data
input wire s_axis_video_tvalid, // axi-4 S valid
output wire s_axis_video_tready, // axi-4 S ready
input wire s_axis_video_tuser , // axi-4 S start of field
input wire s_axis_video_tlast , // axi-4 S end of line
input wire fid, // Field ID, sampled on SOF
// video output interface
input wire vid_io_out_clk , // clock for video output
input wire vid_io_out_ce, // video clock enable
output wire vid_active_video , // video data enable
output wire vid_vsync , // video vertical sync
output wire vid_hsync , // video horizontal sync
output wire vid_vblank , // video vertical blank
output wire vid_hblank , // video horizontal blank
output wire vid_field_id , // video field ID
output wire [VID_OUT_DATA_WIDTH-1:0] vid_data, // video data at DDR rate
// Register/VTG Interface
input wire vtg_vsync, // vsync from the video timing generator
input wire vtg_hsync,
input wire vtg_vblank,
input wire vtg_hblank,
input wire vtg_active_video,
input wire vtg_field_id,
output wire vtg_ce,
// output status bits
output wire locked,
output wire wr_error,
output wire empty
);
// Signal declarations
wire [VID_OUT_DATA_WIDTH -1:0] fifo_data;
wire fifo_eol;
wire fifo_sof;
wire fifo_fid;
wire [RAM_ADDR_BITS -1:0] fifo_level_rd;
wire fifo_empty;
wire fifo_rd_en;
// Module instances
v_axi4s_vid_out_v3_0_out_coupler #(
.DATA_WIDTH (VID_OUT_DATA_WIDTH),
.RAM_ADDR_BITS (RAM_ADDR_BITS),
.FILL_GUARDBAND (FILL_GUARDBAND)
)
out_coupler_i (
.video_out_clk (vid_io_out_clk),
.rst (rst),
.vid_ce (vid_io_out_ce),
.fifo_rst (fifo_rst),
.aclk (aclk),
.aclken (aclken),
.aresetn (aresetn),
.wr_data ({fid,s_axis_video_tuser,s_axis_video_tlast,
s_axis_video_tdata[VID_OUT_DATA_WIDTH-1:0]}),
.valid (s_axis_video_tvalid),
.ready (s_axis_video_tready),
.rd_data (fifo_data),
.eol (fifo_eol),
.sof (fifo_sof),
.fid (fifo_fid),
.rd_en (fifo_rd_en),
.level_wr (),
.level_rd (fifo_level_rd),
.wr_error (wr_error),
.rd_error (empty),
.empty (fifo_empty),
.locked (locked)
);
v_axi4s_vid_out_v3_0_out_sync #(
.RAM_ADDR_BITS (RAM_ADDR_BITS),
.HYSTERESIS_LEVEL (HYSTERESIS_LEVEL),
.VTG_MASTER_SLAVE (VTG_MASTER_SLAVE)
)
out_sync_i
(
.video_out_clk (vid_io_out_clk),
.rst (rst ),
.vid_ce (vid_io_out_ce),
.fifo_sof (fifo_sof),
.fifo_eol (fifo_eol),
.fifo_fid (fifo_fid),
.fifo_level (fifo_level_rd),
.empty (fifo_empty),
.rd_error (empty),
.wr_error (wr_error),
.read_en (fifo_rd_en),
.fifo_rst (fifo_rst),
.vsync (vtg_vsync ),
.hsync (vtg_hsync ),
.field_id (vtg_field_id),
.act_vid (vtg_active_video),
.clock_en (vtg_ce),
.locked (locked)
);
v_axi4s_vid_out_v3_0_vid_out_formatter #(
.DATA_WIDTH (VID_OUT_DATA_WIDTH)
)
vid_out_formatter_i
(
.video_out_clk (vid_io_out_clk),
.rst (fifo_rst),
.vid_ce (vid_io_out_ce),
.odf_data (fifo_data),
.odf_vsync (vtg_vsync ),
.odf_hsync (vtg_hsync ),
.odf_vblank (vtg_vblank),
.odf_hblank (vtg_hblank),
.odf_act_vid (vtg_active_video),
.odf_field_id (vtg_field_id),
.locked (locked),
.fifo_rd_en (fifo_rd_en),
.video_de (vid_active_video ),
.video_vsync (vid_vsync),
.video_hsync (vid_hsync),
.video_vblank (vid_vblank),
.video_hblank (vid_hblank),
.video_field_id (vid_field_id),
.video_data (vid_data )
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <typename T, typename TT> inline ostream &operator<<(ostream &os, const pair<T, TT> &t) { return os << t.first << << t.second; } template <typename T> inline ostream &operator<<(ostream &os, const vector<T> &t) { for (auto i : t) os << i << ; return os; } template <typename T> inline istream &operator>>(istream &is, vector<T> &v) { for (T &t : v) is >> t; return is; } template <typename T1, typename T2> inline istream &operator>>(istream &is, pair<T1, T2> &t) { is >> t.first >> t.second; return is; } const long long mod = 1e9 + 7; void solve() { int a, b, c, d; cin >> a >> b >> c >> d; vector<string> s(50, string(50, D )); for (int i = 0; i < 36; i++) { for (int j = 0; j < 50; j++) { s[i][j] = char( A + (i / 12)); } } a--, b--, c--, d--; for (int i = 1; i < 11; i += 2) { for (int j = 0; j < 50 and b; j += 2, b--) s[i][j] = B ; } for (int i = 13; i < 23; i += 2) { for (int j = 0; j < 50 and c; j += 2, c--) s[i][j] = C ; } for (int i = 25; i < 35; i += 2) { for (int j = 0; j < 50 and d; j += 2, d--) s[i][j] = D ; } for (int i = 37; i < 50; i += 2) { for (int j = 0; j < 50 and a; j += 2, a--) s[i][j] = A ; } cout << 50 << << 50 << n ; for (auto x : s) cout << x << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ; int T = 1; while (T--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; struct node { int x, index; } a[1010]; bool cmp(node x, node y) { if (x.x != y.x) return x.x > y.x; else return x.index > y.index; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].x); a[i].index = i; } sort(a + 1, a + n + 1, cmp); int SUM = 0; for (int i = 1; i <= n; i++) { SUM += ((i - 1) * a[i].x + 1); } printf( %d n , SUM); for (int i = 1; i <= n; i++) { printf( %d , a[i].index); } }
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#include <bits/stdc++.h> using namespace std; int n; int v[2][1000000 + 10]; void solve(int n, int p) { if (n == 0) { v[p][0] = 0; return; } if (!(n & (n + 1))) { for (int i = 0; i <= n; ++i) { v[p][i] = n - i; } } else { int two = 1; while (two * 2 < n + 1) two *= 2; solve(n - two, p ^ 1); for (int i = 0; i <= n - two; ++i) { v[p][i] = two + v[p ^ 1][i]; } int cur = two; for (int i = two; i <= n; ++i) { --cur; v[p][i] = cur; } for (int i = n - two + 1; i < two; ++i) { --cur; v[p][i] = cur; } } } int main() { cin >> n; long long s = 0; for (int i = 0; i <= n; ++i) s += i; cout << s + s << endl; solve(n, 0); for (int i = 0; i <= n; ++i) { printf( %d , v[0][i]); } return 0; }
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// wasca_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [21:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
wasca_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port), // custom_instruction_master.readra
.reset_req (1'b0) // (terminated)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int n, sum, m[17], r[17]; double ans; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> m[i]; for (int i = 1; i <= n; i++) cin >> r[i]; for (int i = 1; i <= 999999; i++) for (int j = 1; j <= n; j++) if (i % m[j] == r[j]) { sum++; break; } ans = 1.0 * sum / 999999; cout << ans; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; char s[111111]; int m, l, r, n, pos[111111], nxt[111111][28], pre[111111][28], pr[111111][28], nx[111111][28], cur[28], a[111111]; int prefix[111111]; int solve(int l, int r); int getsuf(int pos, int k) { if (~nx[pos][k]) return nx[pos][k]; return nx[pos][k] = solve(pos, nxt[pos][k] - 1); } int getpre(int pos, int k) { if (~pr[pos][k]) return pr[pos][k]; return pr[pos][k] = solve(pre[pos][k] + 1, pos); } int solve(int l, int r) { if (l > r) return 0; if (l == r) return 1; bool used[55]; memset(used, 0, sizeof(used)); int ans, res; for (int i = 0; i < 26; i++) { int s = nxt[l][i], e = pre[r][i]; if (s > e || !s || !e) continue; ans = prefix[e] ^ prefix[pre[s][i]]; if (s != l) ans ^= getsuf(l, i); if (e != r) ans ^= getpre(r, i); used[ans] = 1; } res = 0; while (used[res]) res++; return res; } int main() { scanf( %s , s); n = strlen(s); for (int i = 1; i <= n; i++) { a[i] = s[i - 1] - a ; } memset(nx, -1, sizeof(nx)); memset(pr, -1, sizeof(pr)); for (int i = n; i >= 1; i--) { cur[a[i]] = i; for (int j = 0; j < 26; j++) nxt[i][j] = cur[j]; } memset(cur, 0, sizeof(cur)); for (int i = 1; i <= n; i++) { cur[a[i]] = i; for (int j = 0; j < 26; j++) pre[i][j] = cur[j]; } for (int i = 1; i <= n; i++) { if (!pre[i][a[i]]) continue; prefix[i] = prefix[pre[i - 1][a[i]]] ^ solve(pre[i - 1][a[i]] + 1, i - 1); } scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &l, &r); if (!solve(l, r)) printf( Bob n ); else printf( Alice n ); } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// serialInterface.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Perform all serial to parallel, and parallel
//// to serial conversions. Perform device address matching
//// Handle arbitrary length I2C reads terminated by NAK
//// from host, and arbitrary length I2C writes terminated
//// by STOP from host
//// The second byte of a I2C write is always interpreted
//// as a register address, and becomes the base register address
//// for all read and write transactions.
//// I2C WRITE: devAddr, regAddr, data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// I2C READ: data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// Note that when regAddR reaches 255 it will automatically wrap round to 0
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module serialInterface (clearStartStopDet, clk, dataIn, dataOut, regAddr, rst, scl, sdaIn, sdaOut, startStopDetState, writeEn);
input clk;
input [7:0]dataIn;
input rst;
input scl;
input sdaIn;
input [1:0]startStopDetState;
output clearStartStopDet;
output [7:0]dataOut;
output [7:0]regAddr;
output sdaOut;
output writeEn;
reg clearStartStopDet, next_clearStartStopDet;
wire clk;
wire [7:0]dataIn;
reg [7:0]dataOut, next_dataOut;
reg [7:0]regAddr, next_regAddr;
wire rst;
wire scl;
wire sdaIn;
reg sdaOut, next_sdaOut;
wire [1:0]startStopDetState;
reg writeEn, next_writeEn;
// diagram signals declarations
reg [2:0]bitCnt, next_bitCnt;
reg [7:0]rxData, next_rxData;
reg [1:0]streamSt, next_streamSt;
reg [7:0]txData, next_txData;
// BINARY ENCODED state machine: SISt
// State codes definitions:
`define START 4'b0000
`define CHK_RD_WR 4'b0001
`define READ_RD_LOOP 4'b0010
`define READ_WT_HI 4'b0011
`define READ_CHK_LOOP_FIN 4'b0100
`define READ_WT_LO 4'b0101
`define READ_WT_ACK 4'b0110
`define WRITE_WT_LO 4'b0111
`define WRITE_WT_HI 4'b1000
`define WRITE_CHK_LOOP_FIN 4'b1001
`define WRITE_LOOP_WT_LO 4'b1010
`define WRITE_ST_LOOP 4'b1011
`define WRITE_WT_LO2 4'b1100
`define WRITE_WT_HI2 4'b1101
`define WRITE_CLR_WR 4'b1110
`define WRITE_CLR_ST_STOP 4'b1111
reg [3:0]CurrState_SISt, NextState_SISt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: SISt
// NextState logic (combinatorial)
always @ (startStopDetState or streamSt or scl or txData or bitCnt or rxData or sdaIn or regAddr or dataIn or sdaOut or writeEn or dataOut or clearStartStopDet or CurrState_SISt)
begin
NextState_SISt <= CurrState_SISt;
// Set default values for outputs and signals
next_streamSt <= streamSt;
next_txData <= txData;
next_rxData <= rxData;
next_sdaOut <= sdaOut;
next_writeEn <= writeEn;
next_dataOut <= dataOut;
next_bitCnt <= bitCnt;
next_clearStartStopDet <= clearStartStopDet;
next_regAddr <= regAddr;
case (CurrState_SISt) // synopsys parallel_case full_case
`START:
begin
next_streamSt <= `STREAM_IDLE;
next_txData <= 8'h00;
next_rxData <= 8'h00;
next_sdaOut <= 1'b1;
next_writeEn <= 1'b0;
next_dataOut <= 8'h00;
next_bitCnt <= 3'b000;
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
`CHK_RD_WR:
begin
if (streamSt == `STREAM_READ)
begin
NextState_SISt <= `READ_RD_LOOP;
next_txData <= dataIn;
next_regAddr <= regAddr + 1'b1;
next_bitCnt <= 3'b001;
end
else
begin
NextState_SISt <= `WRITE_WT_HI;
next_rxData <= 8'h00;
end
end
`READ_RD_LOOP:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_HI;
next_sdaOut <= txData [7];
next_txData <= {txData [6:0], 1'b0};
end
end
`READ_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `READ_CHK_LOOP_FIN;
end
end
`READ_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b000)
begin
NextState_SISt <= `READ_WT_LO;
end
else
begin
NextState_SISt <= `READ_RD_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`READ_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_ACK;
next_sdaOut <= 1'b1;
end
end
`READ_WT_ACK:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `CHK_RD_WR;
if (sdaIn == `I2C_NAK)
next_streamSt <= `STREAM_IDLE;
end
end
`WRITE_WT_LO:
begin
if ((scl == 1'b0) && (startStopDetState == `STOP_DET ||
(streamSt == `STREAM_IDLE && startStopDetState == `NULL_DET)))
begin
NextState_SISt <= `WRITE_CLR_ST_STOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
next_streamSt <= `STREAM_IDLE;
next_clearStartStopDet <= 1'b1;
end
else if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_ST_LOOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
end
end
`WRITE_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
next_bitCnt <= 3'b000;
end
end
`WRITE_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b111)
begin
NextState_SISt <= `WRITE_CLR_WR;
next_sdaOut <= `I2C_ACK;
case (streamSt)
`STREAM_IDLE: begin
if (rxData[7:1] == `I2C_ADDRESS &&
startStopDetState == `START_DET) begin
if (rxData[0] == 1'b1)
next_streamSt <= `STREAM_READ;
else
next_streamSt <= `STREAM_WRITE_ADDR;
end
else
next_sdaOut <= `I2C_NAK;
end
`STREAM_WRITE_ADDR: begin
next_streamSt <= `STREAM_WRITE_DATA;
next_regAddr <= rxData;
end
`STREAM_WRITE_DATA: begin
next_dataOut <= rxData;
next_writeEn <= 1'b1;
end
default:
next_streamSt <= streamSt;
endcase
end
else
begin
NextState_SISt <= `WRITE_ST_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`WRITE_LOOP_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_CHK_LOOP_FIN;
end
end
`WRITE_ST_LOOP:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_LOOP_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
end
end
`WRITE_WT_LO2:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `CHK_RD_WR;
next_sdaOut <= 1'b1;
end
end
`WRITE_WT_HI2:
begin
next_clearStartStopDet <= 1'b0;
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO2;
end
end
`WRITE_CLR_WR:
begin
if (writeEn == 1'b1)
next_regAddr <= regAddr + 1'b1;
next_writeEn <= 1'b0;
next_clearStartStopDet <= 1'b1;
NextState_SISt <= `WRITE_WT_HI2;
end
`WRITE_CLR_ST_STOP:
begin
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_SISt <= `START;
else
CurrState_SISt <= NextState_SISt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
sdaOut <= 1'b1;
writeEn <= 1'b0;
dataOut <= 8'h00;
clearStartStopDet <= 1'b0;
// regAddr <= // Initialization in the reset state or default value required!!
streamSt <= `STREAM_IDLE;
txData <= 8'h00;
rxData <= 8'h00;
bitCnt <= 3'b000;
end
else
begin
sdaOut <= next_sdaOut;
writeEn <= next_writeEn;
dataOut <= next_dataOut;
clearStartStopDet <= next_clearStartStopDet;
regAddr <= next_regAddr;
streamSt <= next_streamSt;
txData <= next_txData;
rxData <= next_rxData;
bitCnt <= next_bitCnt;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000005; int n, q[N], top1, top2; struct ky { int x, y; long long w, val; bool operator<(const ky& p) const { return x < p.x; } } a[N]; long long f[N], ans; inline double slope(const int x, const int y) { return a[x].x == a[y].x ? 1e18 : (double)(1.0 * (f[x] - f[y])) / (a[x].x - a[y].x); } inline long long cal(const int x, const int y) { return f[y] - (0ll + a[y].x) * a[x].y + a[x].val; } template <class I> inline void ckMax(I& p, I q) { p = (p > q ? p : q); } int main() { scanf( %d , &n); register int i; for (i = 1; i <= n; ++i) scanf( %d%d%lld , &a[i].x, &a[i].y, &a[i].w), a[i].val = (0ll + a[i].x) * a[i].y - a[i].w; std::sort(a + 1, a + 1 + n), f[1] = a[1].val, q[top1 = top2 = 1] = 0; for (i = 1; i <= n; ++i) { while (top1 < top2 && slope(q[top1], q[top1 + 1]) >= a[i].y) ++top1; f[i] = cal(i, q[top1]), ckMax(ans, f[i]); while (top1 < top2 && slope(q[top2 - 1], q[top2]) < slope(q[top2], i)) --top2; q[++top2] = i; } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> bool u[1000001]; int pr[500001]; int l; int n; long long a[8]; int f[7000]; int thr[10]; int b[8]; int inf = 10000; int g[8]; int cal(long long x) { int i; int ret = 0; for (i = 1; i <= l && pr[i] <= x / pr[i]; i++) { while (x % pr[i] == 0) { x = x / pr[i]; ret++; } } if (x > 1) ret++; return ret; } void dfs(int x, int y, long long z, int r, int cur) { int i; if (r == n) { if (f[x] > f[y] + cur + 1) f[x] = f[y] + cur + 1; } else { if (z % a[r] == 0 && b[r] == 2) dfs(x, y - thr[r], z / a[r], r + 1, cur - g[r]); dfs(x, y, z, r + 1, cur); } } int main() { int i, j; memset(u, true, sizeof(u)); l = 0; for (i = 2; i <= 1000000; i++) { if (u[i]) { l++; pr[l] = i; } for (j = 1; j <= l && i <= 1000000 / pr[j]; j++) { u[i * pr[j]] = false; if (i % pr[j] == 0) break; } } scanf( %d , &n); for (i = 0; i < n; i++) scanf( %I64d , &a[i]); for (i = 0; i < n; i++) g[i] = cal(a[i]); thr[0] = 1; for (i = 1; i <= n; i++) thr[i] = thr[i - 1] * 3; int mm = inf; f[0] = 0; for (i = 1; i < thr[n] - 1; i++) { int cur = i; bool flag = true; for (j = n - 1; j >= 0; j--) { b[j] = cur / thr[j]; cur = cur % thr[j]; if (b[j] == 0) flag = false; } f[i] = inf; for (j = 0; j < n; j++) if (b[j] == 1) { if (g[j] == 1) { if (f[i] > f[i - thr[j]] + 1) f[i] = f[i - thr[j]] + 1; } else { if (f[i] > g[j] + f[i - thr[j]] + 1) f[i] = g[j] + f[i - thr[j]] + 1; } dfs(i, i - thr[j], a[j], 0, g[j]); } if (flag) { for (j = 0; j < n; j++) if (b[j] == 1) break; if (i + thr[j] == thr[n] - 1) { if (f[i] < mm) mm = f[i]; } else { if (f[i] + 1 < mm) mm = f[i] + 1; } } } printf( %d n , mm); return 0; }
|
`default_nettype none
module pulse_gen(
input clk, // 12 MHz base clock
input clk_pll,
input RS232_Rx, // Receive pin for the FTDI chip
input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output P2
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
reg [31:0] period;
reg [15:0] p1width;
reg [15:0] delay;
reg [15:0] p2width;
reg [15:0] nut_del;
reg [7:0] nut_wid;
reg block;
reg [7:0] pulse_block;
reg [15:0] pulse_block_off;
reg [7:0] cpmg;
reg rx_done;
// reg [6:0] pre_att;
// reg [6:0] post_att;
// Generating the necessary pulses
pulses pulses(
.clk(clk),
.clk_pll(clk_pll),
.reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(P2)
// .test({FM, P3, P4})
);
// NOSIM2_START
parameter att_on_val = 7'b1111111;
parameter att_off_val = 7'b0000000;
parameter stperiod = 1;
parameter stp1width = 30; // 150 ns
parameter stp2width = 60;
parameter stdelay = 200; // 1 us delay
parameter stcpmg = 3; // Do CPMG with 3 pulses by default
parameter stblock = 50;
parameter stblockoff = 100;
parameter stnutwid = 100;
parameter stnutdel = 100;
// Initialize pulse values
always @(posedge clk) begin
if (resetn) begin
period = stperiod << 18;
p1width = stp1width;
delay = stdelay;
p2width = stp2width;
pulse_block = stblock;
pulse_block_off = stblockoff;
block = 1;
cpmg = stcpmg;
nut_wid = stnutwid;
nut_del = stnutdel;
end // if (reset)
end // always @ (posedge clk)
endmodule // pulse_gen_sim
|
#include <bits/stdc++.h> using namespace std; const int kMaxN = 100010; const int kMaxA = 1000000010; int a[kMaxN]; signed main() { cin.tie(0); ios::sync_with_stdio(false); long long n; cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long ans = 0; for (long long x = 1; (1LL << x) < 2 * kMaxA; x++) { long long val = (1 << x); for (long long i = 0; i < n; i++) { long long num = upper_bound(a + i + 1, a + n, val - a[i]) - lower_bound(a + i + 1, a + n, val - a[i]); ans += num; } } cout << ans << endl; return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
module interrupt_controller (
input wire clock,
input wire reset,
input wire m1_n,
input wire iorq_n,
output wire int_n,
input wire [4:0] int_req,
output reg [4:0] int_ack,
output wire [7:0] jump_addr,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire wr_n,
input wire rd_n,
input wire cs
);
//////////////////////////////////////
// Interrupt Registers
//
// IF - Interrupt Flag (FF0F)
// Bit 4: New Value on Selected Joypad Keyline(s) (rst 60)
// Bit 3: Serial I/O transfer end (rst 58)
// Bit 2: Timer Overflow (rst 50)
// Bit 1: LCD (see STAT) (rst 48)
// Bit 0: V-Blank (rst 40)
//
// IE - Interrupt Enable (FFFF)
// Bit 4: New Value on Selected Joypad Keyline(s)
// Bit 3: Serial I/O transfer end
// Bit 2: Timer Overflow
// Bit 1: LCDC (see STAT)
// Bit 0: V-Blank
//
// 0 <= disable
// 1 <= enable
//////////////////////////////////////
wire[7:0] IF;
reg[7:0] IE;
parameter POLL_STATE = 0;
parameter WAIT_STATE = 1;
parameter ACK_STATE = 2;
parameter CLEAR_STATE = 3;
parameter VBLANK_INT = 0;
parameter LCDC_INT = 1;
parameter TIMER_INT = 2;
parameter SERIAL_INT = 3;
parameter INPUT_INT = 4;
parameter VBLANK_JUMP = 8'hA0; // 8'h40;
parameter LCDC_JUMP = 8'hA2; // 8'h48;
parameter TIMER_JUMP = 8'hA4; // 8'h50;
parameter SERIAL_JUMP = 8'hA6; // 8'h58;
parameter INPUT_JUMP = 8'hA8; // 8'h60;
reg[1:0] state;
reg[2:0] interrupt;
reg[7:0] reg_out;
always @(posedge clock)
begin
if (reset)
begin
IE <= 8'h0;
state <= POLL_STATE;
end
else
begin
// Read / Write for registers
if (cs)
begin
if (!wr_n)
begin
case (A)
16'hFFFF: IE <= Di;
endcase
end
else if (!rd_n)
begin
case (A)
16'hFF0F: reg_out <= IF;
16'hFFFF: reg_out <= IE;
endcase
end
end
case (state)
POLL_STATE:
begin
if (IF[VBLANK_INT] && IE[VBLANK_INT])
begin
interrupt <= VBLANK_INT;
state <= WAIT_STATE;
end
else if (IF[LCDC_INT] && IE[LCDC_INT])
begin
interrupt <= LCDC_INT;
state <= WAIT_STATE;
end
else if (IF[TIMER_INT] && IE[TIMER_INT])
begin
interrupt <= TIMER_INT;
state <= WAIT_STATE;
end
else if (IF[SERIAL_INT] && IE[SERIAL_INT])
begin
interrupt <= SERIAL_INT;
state <= WAIT_STATE;
end
else if (IF[INPUT_INT] && IE[INPUT_INT])
begin
interrupt <= INPUT_INT;
state <= WAIT_STATE;
end
end
WAIT_STATE:
begin
if (!m1_n && !iorq_n)
state <= ACK_STATE;
end
ACK_STATE:
begin
int_ack[interrupt] <= 1'b1;
state <= CLEAR_STATE;
end
CLEAR_STATE:
begin
int_ack[interrupt] <= 1'b0;
if (m1_n || iorq_n)
state <= POLL_STATE;
end
endcase
end
end
assign IF = int_req; // this makes the value read only
assign Do = (cs) ? reg_out : 8'hFF;
assign int_n = (state == WAIT_STATE) ? 1'b0 : 1'b1; // active low
assign jump_addr =
(interrupt == VBLANK_INT) ? VBLANK_JUMP :
(interrupt == LCDC_INT) ? LCDC_JUMP :
(interrupt == TIMER_INT) ? TIMER_JUMP :
(interrupt == SERIAL_INT) ? SERIAL_JUMP :
(interrupt == INPUT_INT) ? INPUT_JUMP : 8'hZZ;
endmodule
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "lut/lut4.sim.v"
`include "dff/dff.sim.v"
`include "omux/omux.sim.v"
module PAIR (
I,
CLK,
O
);
input wire [3:0] I;
input wire CLK;
output wire O;
(* pack="LUT2FF" *)
wire lut_out;
LUT4 lut (.I(I), .O(lut_out));
wire ff_out;
DFF dff (.CLK(CLK), .D(lut_out), .Q(ff_out));
parameter FF_BYPASS = "F";
OMUX #(.MODE(FF_BYPASS)) mux(.L(lut_out), .F(ff_out), .O(O));
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: feature_map_ram_1024w.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module feature_map_ram_1024w (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter init_file = "";
input clock;
input [23:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "24576"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../../ECE289/16bit-Processor-on-chip-ram/Scalar_x_Matrix_Disp_Demo.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../../ECE289/16bit-Processor-on-chip-ram/Scalar_x_Matrix_Disp_Demo.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL feature_map_ram_1024w_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read(T& x) { x = 0; int f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= (ch == - ), ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x = f ? -x : x; } const int N = 3e5 + 10; int n, i, j, len, ans = -1, a[N]; int main() { read(n); for (i = 1; i <= n; ++i) read(a[i]); int mn = -1; for (i = 1, j = n, len = n - 1; i <= j; ++i, --j, --len) { if (mn == -1) mn = min(a[i], a[j]); else mn = min(mn, min(a[i], a[j])); int k = mn / len; if (k < 0) continue; if (ans == -1) ans = k; else ans = min(ans, k); } printf( %d n , ans); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fdest #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input fetch_en,
input pipe_stb_i,
output reg pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output pipe_stb_o,
input pipe_ack_i,
output reg [15:0] color_f,
output [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output reg [15:0] dcolor
);
/* Hit detection */
reg valid;
reg [fml_depth-1-1-4:0] tag;
reg [fml_depth-1-1:0] dadr_r;
reg hit;
reg tag_we;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid <= 1'b0;
hit <= 1'b0;
dadr_r <= {fml_depth-1{1'b0}};
end else begin
if(tag_we)
valid <= 1'b1;
if(flush)
valid <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
hit <= valid & (tag == dadr[fml_depth-1-1:4]);
dadr_r <= dadr;
end
end
end
always @(posedge sys_clk) begin
if(sys_rst)
tag <= {fml_depth-1-4{1'b0}};
else if(tag_we)
tag <= dadr_r[fml_depth-1-1:4];
end
/* Forward */
always @(posedge sys_clk) begin
if(sys_rst)
color_f <= 16'd0;
else if(pipe_stb_i & pipe_ack_o)
color_f <= color;
end
assign dadr_f = dadr_r;
/* Storage */
reg [63:0] storage[0:3];
// synthesis translate_off
initial begin
storage[0] = 64'd0;
storage[1] = 64'd0;
storage[2] = 64'd0;
storage[3] = 64'd0;
end
// synthesis translate_on
wire [63:0] storage_do = storage[dadr_r[3:2]];
always @(*) begin
case(dadr_r[1:0])
2'd0: dcolor = storage_do[63:48];
2'd1: dcolor = storage_do[47:32];
2'd2: dcolor = storage_do[31:16];
2'd3: dcolor = storage_do[15:0];
endcase
end
reg [1:0] storage_wa;
reg storage_we;
always @(posedge sys_clk) begin
if(storage_we)
storage[storage_wa] = fml_di;
end
/* Control & bus master */
assign fml_adr = {dadr_r[fml_depth-1-1:4], 5'd0};
reg wanted;
always @(posedge sys_clk) begin
if(sys_rst)
wanted <= 1'b0;
else if(pipe_ack_o)
wanted <= pipe_stb_i;
end
reg stb_after_fetch;
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter FETCH1 = 3'd1;
parameter FETCH2 = 3'd2;
parameter FETCH3 = 3'd3;
parameter FETCH4 = 3'd4;
parameter OUT = 3'd5;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
tag_we = 1'b0;
storage_we = 1'b0;
storage_wa = 2'bx;
fml_stb = 1'b0;
pipe_ack_o = 1'b0;
stb_after_fetch = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = pipe_ack_i | ~wanted;
if(wanted & ~hit & fetch_en) begin
pipe_ack_o = 1'b0;
next_state = FETCH1;
end
end
FETCH1: begin
fml_stb = 1'b1;
storage_we = 1'b1;
storage_wa = 2'd0;
if(fml_ack)
next_state = FETCH2;
end
FETCH2: begin
storage_we = 1'b1;
storage_wa = 2'd1;
next_state = FETCH3;
end
FETCH3: begin
storage_we = 1'b1;
storage_wa = 2'd2;
next_state = FETCH4;
end
FETCH4: begin
storage_we = 1'b1;
storage_wa = 2'd3;
tag_we = 1'b1;
next_state = OUT;
end
OUT: begin
stb_after_fetch = 1'b1;
pipe_ack_o = pipe_ack_i;
if(pipe_ack_i)
next_state = IDLE;
end
endcase
end
assign pipe_stb_o = stb_after_fetch | (wanted & (hit | ~fetch_en));
assign busy = wanted;
endmodule
|
#include <bits/stdc++.h> using namespace std; int di[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dj[] = {1, -1, 0, 0, 1, -1, 1, -1}; inline int calcMedian(vector<int> &vec) { if (((int)vec.size()) % 2 == 1) { return vec[((int)vec.size()) / 2]; } return (vec[((int)vec.size()) / 2 - 1] + vec[((int)vec.size()) / 2]) / 2; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long init = 0, ans = 0; int n, m; cin >> n >> m; vector<int> vec(m); vector<vector<int> > adj(n); for (int i = 0; i < m; ++i) { cin >> vec[i]; --vec[i]; if (i && vec[i] != vec[i - 1]) { ans = init += abs(vec[i] - vec[i - 1]); adj[vec[i]].push_back(vec[i - 1]); adj[vec[i - 1]].push_back(vec[i]); } } for (int i = 0; i < n; ++i) if (((int)adj[i].size())) { sort(adj[i].begin(), adj[i].end()); int median = calcMedian(adj[i]); long long tmp = 0; for (int j = 0; j < ((int)adj[i].size()); ++j) { tmp -= 0LL + abs(adj[i][j] - i); tmp += 0LL + abs(adj[i][j] - median); } if (init + tmp < ans) ans = init + tmp; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; struct node { int num, cnt; node *l, *r, *p, *path; }; typedef node *pnode; const int N = 100003; node tr[N + 1]; pnode tmp[100002]; const pnode pNull = tr + N; inline void upd(pnode v) { if (v == pNull) return; v->cnt = 1 + v->l->cnt + v->r->cnt; v->l->p = v; v->r->p = v; } pnode fnd(pnode v, int cnt) { if (v == pNull) return pNull; if (v->l->cnt >= cnt) return fnd(v->l, cnt); else if (v->l->cnt + 1 == cnt) return v; else return fnd(v->r, cnt - v->l->cnt - 1); } inline bool is_left_son(pnode v1, pnode v2) { return v1->l == v2; } void rotate(pnode v) { if (v->p == pNull) return; pnode f = v->p; if (is_left_son(f, v)) { pnode tmp = v->r; v->r = f; f->l = tmp; v->p = f->p; if (is_left_son(v->p, f)) v->p->l = v; else v->p->r = v; f->p = v; upd(f); upd(v); } else { pnode tmp = v->l; v->l = f; f->r = tmp; v->p = f->p; if (is_left_son(v->p, f)) v->p->l = v; else v->p->r = v; f->p = v; upd(f); upd(v); } v->path = f->path; } void splay(pnode v) { while (v->p != pNull) { if (v->p->p == pNull) { rotate(v); break; } if (is_left_son(v->p, v) == is_left_son(v->p->p, v->p)) { rotate(v->p); rotate(v); } else { rotate(v); rotate(v); } } } pnode merge(pnode l, pnode r) { if (l == pNull && r == pNull) return pNull; if (l == pNull) return r; if (r == pNull) return l; pnode q = fnd(r, 1); splay(q); q->l = l; upd(q); return q; } pnode getRoot(pnode v, int &cnt) { splay(v); cnt = v->l->cnt + 1; return v; } pnode expose(pnode v) { splay(v); if (v->r != pNull) { v->r->path = v; v->r->p = pNull; v->r = pNull; upd(v); } int tmp = 0; while (v->path != pNull) { pnode f = v->path; splay(f); if (f->r != pNull) { f->r->path = f; f->r->p = pNull; f->r = pNull; upd(f); } pnode old = f->path; v = merge(f, v); v->path = old; } return v; } pnode makeRoot(pnode v) { pnode root = expose(v); splay(v); return v; } int a, b, c, d, i, j, n, m, k; int mas[100004]; int main() { scanf( %d%d , &n, &m); for (int _n((n)-1), i(0); i <= _n; i++) { scanf( %d , &mas[i]); pnode q = &tr[k++]; q->l = q->r = q->p = pNull; q->cnt = 1; q->num = i; if (i + mas[i] < n) { q->path = &tr[i + mas[i]]; } else { q->path = &tr[n]; } } pnode q = &tr[k++]; q->l = q->r = q->p = q->path = pNull; q->cnt = 1; q->num = n; for (int _n((m)-1), i(0); i <= _n; i++) { scanf( %d , &a); if (a == 0) { scanf( %d%d , &a, &b); --a; pnode link = pNull; if (a + mas[a] < n) link = tr + a + mas[a]; else link = tr + n; pnode root = makeRoot(link); c = 0; pnode pa = expose(tr + a); expose(link); tr[a].path = pNull; mas[a] = b; if (a + mas[a] < n) link = tr + a + mas[a]; else link = tr + n; tr[a].path = link; } else { scanf( %d , &a); --a; makeRoot(tr + n); pnode root = expose(tr + a); pnode p = fnd(root, 2); printf( %d %d n , p->num + 1, root->cnt - 1); } } }
|
`include "constants.vh"
`include "rv32_opcodes.vh"
module singlecycproc
(
output wire [`ADDR_LEN-1:0] iraddr1,
output wire [`ADDR_LEN-1:0] iraddr2,
output wire [`ADDR_LEN-1:0] draddr1,
output wire [`ADDR_LEN-1:0] draddr2,
input wire [`DATA_LEN-1:0] irdata1,
input wire [`DATA_LEN-1:0] irdata2,
input wire [`DATA_LEN-1:0] drdata1,
input wire [`DATA_LEN-1:0] drdata2,
output wire [1:0] drsize1,
output wire [1:0] drsize2,
output wire [`ADDR_LEN-1:0] dwaddr1,
output wire [`ADDR_LEN-1:0] dwaddr2,
output wire [`DATA_LEN-1:0] dwdata1,
output wire [`DATA_LEN-1:0] dwdata2,
output wire dwe1,
output wire dwe2,
output wire [1:0] dwsize1,
output wire [1:0] dwsize2,
input clk,
input reset
);
wire [6:0] opcode;
wire [`IMM_TYPE_WIDTH-1:0] imm_type;
wire [`REG_SEL-1:0] rs1;
wire [`REG_SEL-1:0] rs2;
wire [`REG_SEL-1:0] rd;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel;
wire wr_reg;
wire ill_inst;
wire uses_rs1;
wire uses_rs2;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire [`RS_ENT_SEL-1:0] rs_ent;
wire [2:0] dmem_size;
wire [`MEM_TYPE_WIDTH-1:0] dmem_type;
wire [`MD_OP_WIDTH-1:0] md_req_op;
wire md_req_in_1_signed;
wire md_req_in_2_signed;
wire [`MD_OUT_SEL_WIDTH-1:0] md_req_out_sel;
wire [`DATA_LEN-1:0] imm;
wire [`DATA_LEN-1:0] rs1_data;
wire [`DATA_LEN-1:0] rs2_data;
reg [`DATA_LEN-1:0] wb_data;
wire [`DATA_LEN-1:0] alu_src_a;
wire [`DATA_LEN-1:0] alu_src_b;
wire [`DATA_LEN-1:0] alu_res;
wire [`DATA_LEN-1:0] mul_res;
wire [`DATA_LEN-1:0] load_dat;
wire [`DATA_LEN-1:0] imm_br;
wire [`DATA_LEN-1:0] imm_jal;
wire [`DATA_LEN-1:0] imm_jalr;
reg [`DATA_LEN-1:0] imm_j;
reg [`ADDR_LEN-1:0] pc;
reg [`ADDR_LEN-1:0] npc;
always @ (posedge clk) begin
if (reset) begin
pc <= 32'h0;
end
else begin
pc <= npc;
end
end
assign iraddr1 = pc;
assign opcode = irdata1[6:0];
/*
//512KB SRAM
memory_nolatch
simmem(
.clk(clk),
.iraddr1(iraddr1),
.iraddr2(iraddr2),
.draddr1(draddr1),
.draddr2(draddr2),
.irdata1(irdata1),
.irdata2(irdata2),
.drdata1(drdata1),
.drdata2(drdata2),
.drsize1(drsize1),
.drsize2(drsize2),
.dwaddr1(dwaddr1),
.dwaddr2(dwaddr2),
.dwdata1(dwdata1),
.dwdata2(dwdata2),
.dwe1(dwe1),
.dwe2(dwe2),
.dwsize1(dwsize1),
.dwsize2(dwsize2)
);
*/
decoder dcd(
.inst(irdata1),
.imm_type(imm_type),
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.src_a_sel(src_a_sel),
.src_b_sel(src_b_sel),
.wr_reg(wr_reg),
.uses_rs1(uses_rs1),
.uses_rs2(uses_rs2),
.illegal_instruction(ill_inst),
.alu_op(alu_op),
.rs_ent(rs_ent),
.dmem_size(dmem_size),
.dmem_type(dmem_type),
.md_req_op(md_req_op),
.md_req_in_1_signed(md_req_in_1_signed),
.md_req_in_2_signed(md_req_in_2_signed),
.md_req_out_sel(md_req_out_sel)
);
imm_gen ig(
.inst(irdata1),
.imm_type(imm_type),
.imm(imm)
);
ram_sync_nolatch_2r1w #(`REG_SEL, `DATA_LEN, `REG_NUM)
regfile(
.clk(clk),
.raddr1(rs1),
.raddr2(rs2),
.rdata1(rs1_data),
.rdata2(rs2_data),
.waddr(rd),
.wdata(wb_data),
.we(wr_reg && (rd != 0))
);
src_a_mux sam(
.src_a_sel(src_a_sel),
.pc(pc),
.rs1(rs1_data),
.alu_src_a(alu_src_a)
);
src_b_mux sbm(
.src_b_sel(src_b_sel),
.imm(imm),
.rs2(rs2_data),
.alu_src_b(alu_src_b)
);
//ALICE so cute!
alu alu_normal(
.op(alu_op),
.in1(alu_src_a),
.in2(alu_src_b),
.out(alu_res)
);
//MULTIPLIER
multiplier mpr(
.src1(rs1_data),
.src2(rs2_data),
.src1_signed(md_req_in_1_signed),
.src2_signed(md_req_in_2_signed),
.sel_lohi(md_req_out_sel[0]),
.result(mul_res)
);
//LOAD UNIT
assign draddr1 = alu_res;
assign load_dat = drdata1;
assign drsize1 = dmem_size[1:0];
//STORE UNIT
assign dwaddr1 = alu_res;
assign dwsize1 = dmem_size[1:0];
assign dwdata1 = rs2_data;
assign dwe1 = (rs_ent == `RS_ENT_ST) ? 1 : 0;
//BRANCH UNIT
assign imm_br = { {20{irdata1[31]}}, irdata1[7], irdata1[30:25], irdata1[11:8], 1'b0 };
assign imm_jal = { {12{irdata1[31]}}, irdata1[19:12], irdata1[20],
irdata1[30:25], irdata1[24:21], 1'b0 };
assign imm_jalr = { {21{irdata1[31]}}, irdata1[30:21], 1'b0 };
always @(*) begin
case(rs_ent)
`RS_ENT_LD: begin
wb_data = load_dat;
end
`RS_ENT_MUL: begin
wb_data = mul_res;
end
default: begin
wb_data = alu_res;
end
endcase
end // always @ begin
always @(*) begin
case (opcode)
`RV32_BRANCH: begin
npc = alu_res ? (pc + imm_br) : (pc + 4);
end
`RV32_JAL: begin
npc = pc + imm_jal;
end
`RV32_JALR: begin
npc = rs1_data + imm_jalr;
end
default: begin
npc = pc + 4;
end
endcase
end // always @ begin
endmodule // testbench
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while(t--){ int n; cin >> n; vector<int> arr(n,0); for(int i = 0; i < n; i++){ cin >> arr[i]; } vector<int> str; str.push_back(arr[0]); cout << str[0] << endl; for(int i = 1; i < n; i++){ vector<int> temp; if(arr[i] == 1){ for(int i = 0; i < str.size(); i++){ temp.push_back(str[i]); } // temp = str; temp.push_back(1); } else{ for(int j = str.size() - 1; j >= 0; j--){ if(str[j] == arr[i] - 1){ for(int k = 0; k < j; k++){ temp.push_back(str[k]); } temp.push_back(arr[i]); break; } } } str = {}; for(int i = 0; i < temp.size(); i++){ str.push_back(temp[i]); } for(int i = 0; i < str.size(); i++){ cout << str[i]; if(i != str.size() - 1) cout << . ; } cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; long long a1, a2, b1, b2, c1, c2, d1, d2; int main() { cin >> a1 >> a2 >> b1 >> b2 >> c1 >> c2; for (int q = 0; q < 4; q++) { if (q == 0) { d1 = b1 - (a1); d2 = b2 - (a2); } if (q == 1) { d1 = b1 - (-a1); d2 = b2 - (-a2); } if (q == 2) { d1 = b1 - (-a2); d2 = b2 - (a1); } if (q == 3) { d1 = b1 - (a2); d2 = b2 - (-a1); } long long k1 = d1 * c1 + d2 * c2; long long k2 = c1 * c1 + c2 * c2; long long k3 = c1 * d2 - c2 * d1; long long k4 = c1 * c1 + c2 * c2; if (k2 == 0) { if (d1 == 0 && d2 == 0) { cout << YES ; return 0; } } else if (k1 % k2 == 0 && k3 % k4 == 0) { cout << YES ; return 0; } } cout << NO ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_SS_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_SS_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_SS//Dígitos BCD ya concatenados hacia los registros(8 bits)
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 1)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_SS = {digit1,digit0};
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:led_controller:1.0
// IP Revision: 4
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "ip_design_led_controller_0_0,led_controller_v1_0,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ip_design_led_controller_0_0 (
LEDs_out,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready,
s00_axi_aclk,
s00_axi_aresetn
);
output wire [7 : 0] LEDs_out;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire s00_axi_rready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
input wire s00_axi_aresetn;
led_controller_v1_0 #(
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
) inst (
.LEDs_out(LEDs_out),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A31OI_BEHAVIORAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pint = pair<int, int>; using pll = pair<ll, ll>; int main() { cin.tie(0); ios::sync_with_stdio(false); ll n, m; cin >> n >> m; vector<ll> a(n); for (ll i = 0; i < (ll)n; i++) cin >> a[i]; sort(a.begin(), a.end()); reverse(a.begin(), a.end()); ll sum = 0; for (ll i = 0; i < (ll)n; i++) sum += a[i]; if (sum < m) { cout << -1 << endl; return 0; } ll l = 0, r = n; while (r - l > 1) { ll mid = (l + r) / 2; ll power = 0; ll cnt = 0, cost = 0; for (ll i = 0; i < (ll)n; i++) { if (a[i] < cost) break; power += a[i] - cost; cnt++; if (cnt == mid) { cnt = 0; cost++; } } if (power >= m) r = mid; else l = mid; } cout << r << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[11000][4]; int ans[110][110]; int main() { cin.sync_with_stdio(false); cin.tie(0); int n, m, q; cin >> n >> m >> q; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) ans[i][j] = 0; for (int i = 0; i < q; i++) { int x1; cin >> x1; if (x1 != 3) { int x2; cin >> x2; x2--; a[i][0] = x1; a[i][1] = x2; a[i][2] = 0; a[i][3] = 0; } else { int x2, x3, x4; cin >> x2 >> x3 >> x4; x2--; x3--; a[i][0] = x1; a[i][1] = x2; a[i][2] = x3; a[i][3] = x4; } } for (int i = q - 1; i >= 0; i--) { if (a[i][0] == 3) { ans[a[i][1]][a[i][2]] = a[i][3]; } if (a[i][0] == 1) { int x = ans[a[i][1]][m - 1]; for (int j = m - 1; j > 0; j--) { ans[a[i][1]][j] = ans[a[i][1]][j - 1]; } ans[a[i][1]][0] = x; } if (a[i][0] == 2) { int x = ans[n - 1][a[i][1]]; for (int j = n - 1; j > 0; j--) { ans[j][a[i][1]] = ans[j - 1][a[i][1]]; } ans[0][a[i][1]] = x; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << ans[i][j] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 100000 + 10; struct NODE { long long int index; long long int a; bool operator<(const NODE& x) const { return a < x.a; } } node[M]; struct SUR { long long int index; long long int a; bool operator<(const SUR& x) const { return index < x.index; } } sur[M]; int main() { long long int n, k; cin >> n >> k; long long int bk = k; long long int sum = 0; for (int i = 0; i < n; i++) { cin >> node[i].a; node[i].index = i + 1; sum += node[i].a; } sort(node, node + n); if (sum < bk) { cout << -1 << endl; } else { if (sum > bk) { long long int p1 = 0; vector<long long int> psum; vector<long long int> id; long long int pmin = 0; while (p1 < n) { long long int p2 = p1; while (p2 < n && node[p2].a == node[p1].a) { p2++; } p2--; long long int value = (node[p1].a - pmin) * (n - 1 - p1 + 1); psum.push_back(value); id.push_back(p1); pmin = node[p1].a; p2++; p1 = p2; } long long int tsum = 0; int index = -1; for (int i = 0; i < psum.size(); i++) { if (tsum + psum[i] <= k) { tsum += psum[i]; } else { index = i; break; } } long long int res = k - tsum; res = res % (n - id[index]); int istart = 0; for (int i = id[index]; i < n; i++) { sur[istart].a = node[i].a; sur[istart++].index = node[i].index; } sort(sur, sur + istart); long long int lastmin = (id[index] - 1 >= 0 ? node[id[index] - 1].a : 0); long long int div = (k - tsum) / (n - id[index]); for (int i = 0; i < istart; i++) { if (i < res) { sur[i].a = sur[i].a - 1 - lastmin - div; } else { sur[i].a = sur[i].a - lastmin - div; } } vector<int> ans; for (int i = 0; i < istart; i++) { if (sur[(i + res) % istart].a > 0) { ans.push_back(sur[(i + res) % istart].index); } } for (int i = 0; i < ans.size(); i++) { cout << ans[i]; if (i < ans.size() - 1) { cout << ; } else { cout << endl; } } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hdll__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long h, n; long long ret = 0LL; int a[60]; long long two(int x) { if (x == 0) return 1LL; long long half = two(x / 2); half *= half; return x % 2 ? half * 2 : half; } void solve() { int c = 0; --n; while (n) { a[c++] = n % 2; n >>= 1; } for (int i = c; i < h; ++i) a[i] = 0; int e = 0; for (int i = h - 1; i >= 0; --i) { if (a[i] != e) { ret += two(i + 1); } if (a[i] == e) { ret += 1; e = !e; } } cout << ret << endl; } int main() { cin >> h >> n; solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int X[4] = {0, 0, -1, 1}; const int Y[4] = {-1, 1, 0, 0}; int dp[1001][1001], Vis[1001][1001]; char c[1001][1001]; int vis[1001][1001], i, j, m, n, p, k, ans; bool check(int x, int y, int xx, int yy) { if (x < 0 || y < 0 || x > n || y >= m) return false; if (c[x][y] == D && c[xx][yy] == A ) return true; if (c[x][y] == I && c[xx][yy] == D ) return true; if (c[x][y] == M && c[xx][yy] == I ) return true; if (c[x][y] == A && c[xx][yy] == M ) return true; return false; } int dfs(int x, int y) { if (Vis[x][y]) return dp[x][y]; if (vis[x][y]) { printf( Poor Inna! n ); exit(0); } vis[x][y] = 1; int i; for (i = 0; i < 4; i++) if (check(x + X[i], y + Y[i], x, y)) dp[x][y] = max(dp[x][y], dfs(x + X[i], y + Y[i])); if (c[x][y] == A ) dp[x][y]++; vis[x][y] = 0; Vis[x][y] = 1; return dp[x][y]; } int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %s , &c[i]); for (i = 1; i <= n; i++) for (j = 0; j < m; j++) if (c[i][j] == D ) ans = max(ans, dfs(i, j)); if (!ans) printf( Poor Dima! n ); else printf( %d n , ans); }
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef unsigned long long ull; const int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; const int inf = 0x3f3f3f3f; const ll linf = 0x3f3f3f3f3f3f3f3f; const ll mod = 1e9 + 7; //const ll mod = 998244353; ll ksm(ll x,ll k) { ll ret=1; while(k) { if(k&1) ret=ret*x%mod; x=x*x%mod,k>>=1; } return ret; } ll prime[10000005],pcnt,phi[10000005]; bool mark[10000005]; inline void pre(ll n) { mark[1]=1; for(ll i=2;i<=n;i++) { if(!mark[i]) prime[++pcnt]=i/*,phi[i]=i-1*/; for(ll j=1;j<=pcnt;j++) { ll k=i*prime[j]; if(k>n) break; mark[k]=1; if(i%prime[j]==0) { // phi[k]=phi[i]*prime[j]; break; } // else phi[k]=phi[i]*(prime[j]-1); } } } struct data { int u,v,val; data(int _u=0,int _v=0,int _val=0):u(_u),v(_v),val(_val) {} bool operator < (const data &x) const { if(val==x.val) return u<x.u; return val<x.val; } }a[505*505]; int fa[505*505],c[505*505]; vector <int> u,v; int getfa(int x) { return x==fa[x] ? x:fa[x]=getfa(fa[x]); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int T=1; // cin>>T; while(T--) { int n; cin>>n; for(int i=1;i<=n*n;i++) fa[i]=i; int cnt=0; for(int i=1;i<=n;i++) { for(int j=1;j<=n;j++) { int x; cin>>x; if(i==j) c[i]=x; if(i>=j) continue; a[++cnt]=data(i,j,x); } } sort(a+1,a+cnt+1); int k=n; for(int i=1;i<=cnt;i++) { int fu=getfa(a[i].u),fv=getfa(a[i].v); if(fu==fv) continue; if(fu>n && c[fu]==a[i].val) { fa[fv]=fu,u.push_back(fv),v.push_back(fu); continue; } if(fv>n && c[fv]==a[i].val) { fa[fu]=fv,u.push_back(fu),v.push_back(fv); continue; } k++; fa[fu]=fa[fv]=k; c[k]=a[i].val; u.push_back(fu),v.push_back(k); u.push_back(fv),v.push_back(k); } cout<<k<< n ; for(int i=1;i<=k;i++) cout<<c[i]<< ; cout<< n ; cout<<k<< n ; for(int i=0;i<u.size();i++) cout<<u[i]<< <<v[i]<< n ; } }
|
#include <bits/stdc++.h> using namespace std; int i; long n, m; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; map<string, int> mp; string s; while (n--) { cin >> s; mp[s]++; if (mp[s] > 1) { cout << YES << endl; } else cout << NO << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> segs; int numNeg = 0; int curLen = 0; for (int i = 0; i < n; i++) { int a; scanf( %d , &a); if (a < 0) { if (numNeg == 2) { segs.push_back(curLen); curLen = 1; numNeg = 1; } else { numNeg += 1; curLen += 1; } } else { curLen += 1; } } if (curLen != 0) { segs.push_back(curLen); } printf( %d n , segs.size()); for (int s : segs) { printf( %d , s); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100100]; int num[100100]; int main() { set<int> s; int n; cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = n; i >= 1; i--) { s.insert(a[i]); num[i] = s.size(); } s.clear(); long long sum = 0; for (int i = 1; i <= n; i++) { if (s.find(a[i]) == s.end()) { s.insert(a[i]); sum += num[i + 1]; } } cout << sum << endl; }
|
// Driver for an LCD TFT display. Specifically, this was written to drive
// the AdaFruit YX700WV03, which is an 800x480 7" display. It's driven
// like a VGA monitor, but with digital color values, a data enable signal,
// and a clock.
module LCD_control(
input wire clock, // System clock.
input wire tick, // LCD clock (synchronous with system clock).
input wire reset_n, // Asynchronous reset, active low.
output reg [9:0] x, // On-screen X pixel location.
output reg [9:0] y, // On-screen Y pixel location.
output reg next_frame, // 1 when between frames (one clock).
output reg hs_n, // Horizontal sync, active low.
output reg vs_n, // Vertical sync, active low.
output reg data_enable // Whether we need a pixel right now.
);
// There are two internal registers, h and v. They are 0-based.
// The h value has these ranges:
//
// h hs_n
// [0, H_FRONT) 1 (front porch)
// [H_FRONT, H_FRONT + H_SYNC) 0 (sync pulse)
// [H_FRONT + H_SYNC, H_BLANK) 1 (back porch)
// [H_BLANK, H_TOTAL) 1 (pixels are visible)
//
// The v value has these ranges:
//
// v vs_n
// [0, V_FRONT) 1 (front porch)
// [V_FRONT, V_FRONT + V_SYNC) 0 (sync pulse)
// [V_FRONT + V_SYNC, V_BLANK) 1 (back porch)
// [V_BLANK, V_TOTAL) 1 (pixels are visible)
//
// next_frame is on the second pixel of the first row.
// Video parameters.
parameter H_FRONT = 24;
parameter H_SYNC = 72;
parameter H_BACK = 96;
parameter H_ACT = 800;
parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
parameter V_FRONT = 3;
parameter V_SYNC = 10;
parameter V_BACK = 7;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
reg [10:0] h;
reg [10:0] v;
wire h_visible = h >= H_BLANK;
/* verilator lint_off UNSIGNED */
wire v_visible = v >= V_BLANK;
/* verilator lint_on UNSIGNED */
/* verilator lint_off UNUSED */
wire [10:0] h_normalized = h - H_BLANK;
wire [10:0] v_normalized = v - V_BLANK;
/* verilator lint_on UNUSED */
// Latch the next_frame register. This will be true for one (tick) clock
// a few rows after the last visible pixel.
always @(posedge clock) begin
if (tick) begin
// Don't do it right away after the end of the previous frame,
// that might cause problems if some logic isn't quite done
// dealing with the color. Wait a few rows.
next_frame <= h == 0 && v == V_FRONT;
end
end
// Walk through screen.
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
h <= 0;
v <= 0;
hs_n <= 1;
vs_n <= 1;
x <= 0;
y <= 0;
data_enable <= 0;
end else if (tick) begin
// Advance pixel.
if (h < H_TOTAL - 1) begin
h <= h + 1'b1;
end else begin
// Next line.
h <= 0;
if (v < V_TOTAL - 1) begin
v <= v + 1'b1;
end else begin
v <= 0;
end
// Vertical sync.
if (v == V_FRONT - 1) begin
// Front porch end, sync pulse start.
vs_n <= 1'b0;
end
if (v == V_FRONT + V_SYNC - 1) begin
// Sync pulse end, back porch start.
vs_n <= 1'b1;
end
end
// Horizontal sync.
if (h == H_FRONT - 1) begin
// Front porch end, sync pulse start.
hs_n <= 1'b0;
end
if (h == H_FRONT + H_SYNC - 1) begin
// Sync pulse end, back porch start.
hs_n <= 1'b1;
end
// Latch output registers. These are delayed from the h and
// v values.
x <= h_visible ? h_normalized[9:0] : 10'h0;
y <= v_visible ? v_normalized[9:0] : 10'h0;
data_enable <= h_visible && v_visible;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 1005; const int oo = 1000000000; const long long Base = 1000000007; typedef int Tarr[MaxN]; long long x, y, a, b, n, m, xx, yy, r1, r2, r3, r4; void Ok(int Val) { int xx = Val * a, yy = Val * b; if (xx % 2 == 0) { r1 = max((long long)0, min(n - xx, x - xx / 2)); } else r1 = max((long long)0, min(n - xx, x - xx / 2 - 1)); if (yy % 2 == 0) { r2 = max((long long)0, min(m - yy, y - yy / 2)); } else r2 = max((long long)0, min(m - yy, y - yy / 2 - 1)); r3 = r1 + xx; r4 = r2 + yy; } int main() { cin >> n >> m >> x >> y >> a >> b; int aa = a, bb = b, tmp; do { tmp = aa % bb; aa = bb; bb = tmp; } while (bb != 0); a /= aa; b /= aa; Ok(min((n) / a, (m) / b)); cout << r1 << << r2 << << r3 << << r4; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:09:46 04/21/2015
// Design Name:
// Module Name: clockdivider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clockdivider(
input clk,
input rst,
input select,
output reg [31:0] OUT1,
output reg [31:0] OUT2,
output clkdivided1hz,
output clkdivided200hz,
output clkselect
);
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT1<=32'd0;
else
if (OUT1 == 32'd50000000)
OUT1<=32'd0;
else
OUT1 <= OUT1 + 1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
OUT2<=32'd0;
else
if (OUT2 == 32'd500000)
OUT2<=32'd0;
else
OUT2 <= OUT2 + 1;
end
assign clkdivided1hz = (OUT1 == 32'd50000000);
assign clkdivided200hz = (OUT2 == 32'd250000);
assign clkselect = clkdivided200hz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
|
//#############################################################################
//# Function: Low power clock gate circuit #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockgate (
input clk, // clock input
input te, // test enable enable
input en, // enable (from positive edge FF)
output eclk // enabled clock output
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic
asic_icg icg (.en(en),
.te(te),
.clk(clk),
.eclk(eclk));
end
else
begin : generic
wire en_sh;
wire en_sl;
//Stable low/valid rising edge enable
assign en_sl = en | te;
//Stable high enable signal
oh_lat0 lat0 (.out (en_sh),
.in (en_sl),
.clk (clk));
assign eclk = clk & en_sh;
end
endgenerate
endmodule // oh_clockgate
|
`include "../../elink/hdl/elink_constants.v"
module fifo_async
(/*AUTOARG*/
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104; //FIFO width
parameter DEPTH = 16; //FIFO depth
//##########
//# RESET/CLOCK
//##########
input wr_rst; //write reset
input rd_rst; //read reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
`ifdef TARGET_CLEAN
fifo_async_model fifo_model (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
`elsif TARGET_XILINX
generate
if((DW==104) & (DEPTH==16))
begin
fifo_async_104x16 fifo_async_104x16 (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if((DW==104) & (DEPTH==32))
begin
fifo_async_104x32 fifo_async_104x32 (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
endgenerate
`endif // !`elsif TARGET_XILINX
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../xilibs/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// Copyright (c) 2015 Kareem Matariyeh
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Creator: Kareem Matariyeh (asm2750)
//
// Create Date: 21:54:21 01/03/2015
// Design Name:
// Module Name: FIFO_WxD
// Project Name: neopixel (ws2812) transmitter
// Target Devices: Any device able to fit design at timing requirements
// Tool versions: Any tool able to synthesize design
// Description: A adjustable width x depth FIFO that has has two ports.
//
// Dependencies: None.
//
// Revision:
// Revision 1.00 - Design Implmented and working on Spartan 6 XC6SLX6
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FIFO_WxD #(
parameter U_FIFO_WIDTH = 24, // word width of FIFO
parameter U_FIFO_SQ_DEPTH = 10 // 2^n depth of the FIFO (3k byte - 1 FIFO by default)
)(
input wire rst,
input wire [U_FIFO_WIDTH - 1:0] dataIn,
input wire wr_en,
input wire rd_en,
output wire [U_FIFO_WIDTH - 1:0] dataOut,
output wire full_flg,
output wire empty_flg
);
// FIFO buffer instance
reg [U_FIFO_WIDTH - 1:0] fifo [(2^U_FIFO_SQ_DEPTH) - 1:0];
// pointer counters (set to 0 initially)
reg [U_FIFO_SQ_DEPTH - 1:0] wr_ptr = 0;
reg [U_FIFO_SQ_DEPTH - 1:0] rd_ptr = 0;
// write block
always@(posedge wr_en or negedge rst)
begin
if(!rst) // async reset
wr_ptr <= 0;
else if(!full_flg) // write data to the buffer and inc the write pointer
begin
fifo[wr_ptr] <= dataIn;
wr_ptr <= wr_ptr + 1'b1;
end
end // write block
// read block
always@(posedge rd_en or negedge rst)
begin
if(!rst)
rd_ptr <= 0;
else if(!empty_flg)
begin
rd_ptr <= rd_ptr + 1'b1;
end
end // read block
// assign the outputs continously (pointers determine flags and data)
assign empty_flg = (wr_ptr == rd_ptr)? 1'b1 : 1'b0;
assign full_flg = ((wr_ptr + {{U_FIFO_SQ_DEPTH-1{1'b0}}, 1'b1}) == rd_ptr)? 1'b1 : 1'b0; // because of the full flg decision the fifo depth is 2^n - 1
assign dataOut = (empty_flg)? {U_FIFO_WIDTH{1'b0}} : fifo[rd_ptr]; // 0 if empty
endmodule
|
#include<bits/stdc++.h> #define llong long long #define mkpr make_pair #define x first #define y second #define iter iterator #define riter reverse_iterator #define y1 Lorem_ipsum_ #define tm dolor_sit_amet_ using namespace std; inline int read() { int x = 0,f = 1; char ch = getchar(); for(;!isdigit(ch);ch=getchar()) {if(ch== - ) f = -1;} for(; isdigit(ch);ch=getchar()) {x = x*10+ch-48;} return x*f; } const int P = 1e9+7; const int mxN = 2e5; int n,m; llong fact[mxN+3],facti[mxN+3],inv[mxN+3]; llong quickpow(llong x,llong y) { llong cur = x,ret = 1ll; for(int i=0; y; i++) { if(y&(1ll<<i)) {y-=(1ll<<i); ret = ret*cur%P;} cur = cur*cur%P; } return ret; } llong comb(llong x,llong y) {return x<0ll||y<0ll||x<y?0ll:fact[x]*facti[y]%P*facti[x-y]%P;} llong combi(llong x,llong y) {return x<0ll||y<0ll||x<y?0ll:facti[x]*fact[y]%P*fact[x-y]%P;} void initfact(int n) { fact[0] = 1ll; for(int i=1; i<=n; i++) fact[i] = fact[i-1]*i%P; facti[n] = quickpow(fact[n],P-2); for(int i=n-1; i>=0; i--) facti[i] = facti[i+1]*(i+1ll)%P; } int main() { initfact(mxN); int T = read(); while(T--) { n = read(),m = read(); llong ans = 0ll; for(int i=0; i<=n; i++) { llong cur = comb(n-1ll*(i-1)*(m-1),i)*combi(n,i)%P; ans = (ans+cur)%P; } printf( %lld n ,ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long kkk, kk, otv = 0; string ss; long long i, a; cin >> a; for (i = 0; i < a; i++) { long long s1, s2, s3; cin >> s1 >> s2 >> s3; if ((s1 > s2 + s3 + 1) || (s2 > s1 + s3 + 1) || (s3 > s1 + s2 + 1)) cout << No << endl; else cout << Yes << endl; } }
|
#include <bits/stdc++.h> using namespace std; int expo(int x, int y) { int res = 1; while (y) { if (y % 2) res = (res * x % 1000000007) % 1000000007; x = (x * x) % 1000000007; y /= 2; } return res; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long nextPrime(long long N) { if (N <= 1) return 2; long long prime = N; bool found = false; while (!found) { prime++; if (isPrime(prime)) found = true; } return prime; } long long cl(long long n, long long d) { return (n + d - 1) / d; } long long binToDec(string s) { return bitset<64>(s).to_ullong(); } string decToBin(long long a) { return bitset<64>(a).to_string(); } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / (gcd(a, b)); } void print(pair<long long, long long> a) { cout << a.first << << a.second; cout << endl; ; } void print(long long a) { cout << a; cout << endl; } void print(std::vector<long long> a) { for (auto i : a) cout << i << ; cout << endl; ; } void print(string s) { cout << s; cout << endl; ; } void printr(std::vector<long long> a, long long start, long long end) { for (long long i = start; i < end; i++) cout << a[i] << ; cout << endl; ; } void print(long long a, long long b) { cout << a << << b; } void amax(long long &a, long long b) { a = max(a, b); } void amin(long long &a, long long b) { a = min(a, b); } long long madd(long long a, long long b) { return ((a % 1000000007) + (b % 1000000007)) % 1000000007; } long long mmul(long long a, long long b) { return ((a % 1000000007) * (b % 1000000007)) % 1000000007; } long long msub(long long a, long long b) { return ((a % 1000000007) - (b % 1000000007) + 1000000007) % 1000000007; } long long fpow(long long x, long long y, long long p = 1000000007) { x %= p; long long sum = 1; while (y) { if (y & 1) sum = sum * x; sum %= p; y = y >> 1; x = x * x; x %= p; } return sum; } bool isPerSquare(long double a) { if (a < 0) return false; long long sr = sqrt(a); return (sr * sr == a); } bool isPalindrome(string str) { long long low = 0, high = long long(str.size()) - 1; while (low < high) { if (str[low] != str[high]) return false; low++, high--; } return true; } void solve() { long long n; cin >> n; ; vector<set<long long>> vp(n + 1); for (__typeof(n + 1) i = (1) - ((1) > (n + 1)); i != (n + 1) - ((1) > (n + 1)); i += 1 - 2 * ((1) > (n + 1))) { long long x; cin >> x; ; set<long long> temp; for (__typeof(x) i = (0) - ((0) > (x)); i != (x) - ((0) > (x)); i += 1 - 2 * ((0) > (x))) { long long y; cin >> y; ; temp.insert(y); } vp[i] = temp; } vector<vector<long long>> dependent(n + 1); set<long long> books; for (long long i = 1; i <= n; i++) { for (auto j : vp[i]) { dependent[j].push_back(i); } } long long ans = 1; for (long long i = 1; i <= n; i++) { if (long long(vp[i].size()) == 0) { books.insert(i); } } long long rem = 0; while (long long(books.size())) { bool added = false, erased = false; std::vector<long long> add; auto i = *books.begin(); while (1) { if (!added && long long(dependent[i].size()) && dependent[i][0] < i) { added = true; ans++; } for (long long j = 0; j < long long(dependent[i].size()); j++) { vp[dependent[i][j]].erase(i); if (long long(vp[dependent[i][j]].size()) == 0) { books.insert(dependent[i][j]); } } dependent[i].clear(); rem++; books.erase(i); if (rem == n) { print(ans); return; } if (books.upper_bound(i) == books.end()) { break; } else { i = *books.upper_bound(i); } } } print(-1); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) solve(); }
|
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: clk_prescaler.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// REV: Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module clk_prescaler(
CLK, CLK_EN, div_1, div_2, div_3, MR, pre_0, pre_1, clk_1us);
input CLK;
input CLK_EN; // enables the divide chain
input div_1; // divider select bit 1
input div_2; // divider select bit 2
input div_3; // divider select bit 3
input MR;
input pre_0; // prescaler select bit 0
input pre_1; // prescaler select bit 1
output clk_1us; // OD, STD mode fsm clock
wire CLK;
wire MR;
wire pre_0;
wire pre_1;
wire div_1;
wire div_2;
wire div_3;
wire clk_prescaled; // prescaled clock output
reg clk_1us; // 1us timebase for 1-wire STD and OD trans
reg clk_div; // divided clk for hdrive
reg en_div; // enable use of divided clk for hdrive
reg clk_prescaled_reg;
reg [6:0] div_cnt;
reg [2:0] ClkPrescale;
parameter [2:0] s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100,
s5=3'b101, s6=3'b110;
//--------------------------------------------------------------------------
// Clock Prescaler
//--------------------------------------------------------------------------
wire rst_clk = MR || !CLK_EN;
always @(posedge rst_clk or posedge CLK)
if(rst_clk)
ClkPrescale <= s0;
else
case(ClkPrescale)
s0: ClkPrescale <= s1;
s1: ClkPrescale <= s2;
s2: if(pre_0 && !pre_1)
ClkPrescale <= s0;
else
ClkPrescale <= s3;
s3: ClkPrescale <= s4;
s4: if(!pre_0 && pre_1)
ClkPrescale <= s0;
else
ClkPrescale <= s5;
s5: ClkPrescale <= s6;
s6: ClkPrescale <= s0;
default: ClkPrescale<=s0;
endcase
reg en_clk;
//
// Create prescaled clock
//
always @(posedge MR or posedge CLK)
if (MR)
clk_prescaled_reg<=1;
else
clk_prescaled_reg <= (!ClkPrescale[0] && !ClkPrescale[1]
&& !ClkPrescale[2]);
//assign clk_prescaled = (!pre_0 && !pre_1 && CLK_EN)?CLK:clk_prescaled_reg;
always @(posedge MR or negedge CLK)
if (MR)
en_clk <= 1'b1;
else
en_clk <= CLK_EN && ((!pre_0 && !pre_1) || (ClkPrescale[2:0] == 3'b000));
assign clk_prescaled = en_clk & CLK;
//--------------------------------------------------------------------------
// Clock Divider
// using clk_prescaled as its input, this divide-by-2 chain does the
// other clock division
//--------------------------------------------------------------------------
always @(posedge MR or posedge CLK)
if (MR)
div_cnt <= 7'h00;
else if (en_clk)
div_cnt <= div_cnt + 1;
reg clk_1us_en;
always @(posedge MR or negedge CLK)
if (MR)
clk_1us_en <= 1'b1;
else
case ({div_3, div_2, div_1})
3'b000 : clk_1us_en <= CLK_EN;
3'b001 : clk_1us_en <= ~div_cnt[0];
3'b010 : clk_1us_en <= (div_cnt[1:0] == 2'h1);
3'b011 : clk_1us_en <= (div_cnt[2:0] == 3'h3);
3'b100 : clk_1us_en <= (div_cnt[3:0] == 4'h7);
3'b101 : clk_1us_en <= (div_cnt[4:0] == 5'h0f);
3'b110 : clk_1us_en <= (div_cnt[5:0] == 6'h1f);
3'b111 : clk_1us_en <= (div_cnt[6:0] == 7'h3f);
endcase
always @(clk_1us_en or en_clk or CLK)
clk_1us = clk_1us_en & en_clk & CLK;
endmodule // clk_prescaler
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
/************************************************************************************
*
* FIFO
*
************************************************************************************/
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
} fifov_flags_t;
module LAG_fifo_v (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
#include <bits/stdc++.h> using namespace std; int n; int vis[601], co[601], fa[601], d[601]; int zb(int o, int l, int r) { int ans1 = 0, ans2 = 0; int sz = 0; for (int i = l; i <= r; i++) if (!vis[i]) sz++; if (sz > 0) { printf( ? %d n , sz + 1); for (int i = l; i <= r; i++) if (!vis[i]) printf( %d , i); printf( %d n , o); fflush(stdout); scanf( %d , &ans1); } if (sz > 1) { printf( ? %d n , sz); for (int i = l, ok = 0; i <= r; i++) if (!vis[i]) printf(!ok ? ok = 1, %d : %d , i); printf( n ); fflush(stdout); scanf( %d , &ans2); } return ans1 - ans2; } int nx(int o) { if (!zb(o, 1, n)) return 0; int l = 1, r = n; while (l != r) { int mid = l + r >> 1; if (zb(o, l, mid)) r = mid; else l = mid + 1; } return l; } void dfs(int u) { for (;;) { int v = nx(u); if (!v) break; vis[v] = 1; co[v] = co[u] ^ 1; fa[v] = u; d[v] = d[u] + 1; dfs(v); } } int zb2(int o, int l, int r, int* wd) { int ans1 = 0, ans2 = 0; int sz = 0; for (int i = l; i <= r; i++) if (wd[i] != o) sz++; if (sz > 0) { printf( ? %d n , sz + 1); for (int i = l; i <= r; i++) if (wd[i] != o) printf( %d , wd[i]); printf( %d n , o); fflush(stdout); scanf( %d , &ans1); } if (sz > 1) { printf( ? %d n , sz); for (int i = l, ok = 0; i <= r; i++) if (wd[i] != o) printf(!ok ? ok = 1, %d : %d , wd[i]); printf( n ); fflush(stdout); scanf( %d , &ans2); } return ans1 - ans2; } int nx2(int o, int* wd) { if (!zb2(o, 1, wd[0], wd)) return 0; int l = 1, r = wd[0]; while (l != r) { int mid = l + r >> 1; if (zb2(o, l, mid, wd)) r = mid; else l = mid + 1; } return wd[l]; } int ld[601], rd[601]; int dd[601]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) if (!vis[i]) vis[i] = 1, co[i] = 0, dfs(i); for (int i = 1; i <= n; i++) if (co[i]) rd[++rd[0]] = i; else ld[++ld[0]] = i; for (int i = 1; i <= ld[0]; i++) { int u = ld[i], v; if (v = nx2(u, ld)) { for (; u != v;) { if (d[u] > d[v]) dd[++dd[0]] = u, u = fa[u]; else dd[++dd[0]] = v, v = fa[v]; } dd[++dd[0]] = u; printf( N %d n , dd[0]); for (int i = 1; i <= dd[0]; i++) printf( %d%c , dd[i], i == dd[0] ? n : ); return 0; } } for (int i = 1; i <= rd[0]; i++) { int u = rd[i], v; if (v = nx2(u, rd)) { for (; u != v;) { if (d[u] > d[v]) dd[++dd[0]] = u, u = fa[u]; else dd[++dd[0]] = v, v = fa[v]; } dd[++dd[0]] = u; printf( N %d n , dd[0]); for (int i = 1; i <= dd[0]; i++) printf( %d%c , dd[i], i == dd[0] ? n : ); return 0; } } printf( Y %d n , ld[0]); for (int i = 1; i <= ld[0]; i++) printf( %d%c , ld[i], i == ld[0] ? n : ); }
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
#include<iostream> #include<cstdlib> #include<cstdio> #include<cmath> #include<iomanip> #include<cstring> #include<algorithm> #include<ctime> using namespace std; const int MAXN=2010; int read() { int kkk=0,x=1; char c=getchar(); while((c< 0 || c> 9 ) && c!= - ) c=getchar(); if(c== - ) c=getchar(),x=-1; while(c>= 0 && c<= 9 ) kkk=kkk*10+(c- 0 ),c=getchar(); return kkk*x; } int n,X[MAXN],Y[MAXN],tag[MAXN],father[MAXN],id[MAXN],cur,ans[MAXN*MAXN][2],ANS,dl[MAXN],h,t,pd[MAXN]; double Theta[MAXN]; int find(int k){return father[k]==k?k:father[k]=find(father[k]);} void solve(int S) { h=t=0; dl[++t]=S; while(h!=t) { int u=dl[++h]; father[u]=S; if(tag[u]==S) break; dl[++t]=tag[u]; } if(t==1) pd[S]=1; } bool cmp(int x,int y){return Theta[x]<Theta[y];} int main() { n=read(); for(int i=1;i<=n;++i) X[i]=read(),Y[i]=read(),tag[i]=read(); for(int i=1;i<=n;++i) if(!father[i]) solve(i); for(int i=1;i<=n;++i) if(!pd[i]) { if(!cur) cur=i; else if(X[i]<X[cur] || (X[i]==X[cur] && Y[i]<Y[cur])) cur=i; } for(int i=1;i<=n;++i) Theta[i]=atan2(Y[i]-Y[cur],X[i]-X[cur]); for(int i=1;i<=n;++i) id[i]=i; sort(id+1,id+n+1,cmp); pd[cur]=1; for(int i=1,las=0;i<=n;++i) if(!pd[id[i]]) { if(las) { int alas=find(las),aid=find(id[i]); if(alas!=aid) { father[alas]=aid; ans[++ANS][0]=las; ans[ANS][1]=id[i]; swap(tag[las],tag[id[i]]); } } las=id[i]; } while(tag[cur]!=cur) { ans[++ANS][0]=cur; ans[ANS][1]=tag[cur]; swap(tag[cur],tag[tag[cur]]); } printf( %d n ,ANS); for(int i=1;i<=ANS;++i) printf( %d %d n ,ans[i][0],ans[i][1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a[200009], ans = 1, b[200009], sum = 1; bool vis[200009]; void dfs(long long x) { if (vis[x]) return; vis[x] = 1; dfs(a[x]); } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; dfs(1); for (int i = 1; i <= n; i++) { if (vis[i]) continue; sum++; dfs(i); } bool f = 0, g = 0; for (int i = 1; i <= n; i++) { ans += b[i]; } ans %= 2; if (sum != 1) ans += sum; cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_clk #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter CLKIN_DS_OR_SE_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
output loaden,
output [ 7:0] phase,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR / 2 : SERDES_FACTOR;
// internal signals
wire clk_in_s;
// defaults
assign loaden = 'd0;
assign phase = 'd0;
assign up_drp_rdata[31:16] = 'd0;
// instantiations
generate
if (CLKIN_DS_OR_SE_N == 1) begin
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
end else begin
IBUF IBUF_inst (
.O(clk_in_s),
.I(clk_in_p));
end
endgenerate
generate
if (MMCM_OR_BUFR_N == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK0_PHASE (0.0),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV),
.MMCM_CLK1_PHASE (0.0),
.MMCM_CLK2_DIV (MMCM_CLK0_DIV),
.MMCM_CLK2_PHASE (90.0))
i_mmcm_drp (
.clk (clk_in_s),
.clk2 (1'b0),
.clk_sel (1'b1),
.mmcm_rst (rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.mmcm_clk_2 (out_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata[15:0]),
.up_drp_rdata (up_drp_rdata[15:0]),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
endgenerate
generate
if (MMCM_OR_BUFR_N == 0) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE(BUFR_DIVIDE)) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
assign out_clk = clk;
assign up_drp_rdata[15:0] = 'd0;
assign up_drp_ready = 'd0;
assign up_drp_locked = 'd0;
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.14159265358979323846; long long MOD = 1e9 + 7; const char nl = n ; const long long inf = 1e15; long long power(long long x, long long y) { long long z = 1; while (y > 0) { if (y % 2) z = z * x; x = x * x; y /= 2; } return z; } long long gcd(long long a, long long b) { if (a < b) return gcd(b, a); if (b == 0) return a; return gcd(b, a % b); } long long sq(long long a) { long long ans = (1ll * a * a); return ans; } bool isprime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long digitsum(long long x) { long long ans = 0; while (x > 0) { ans += (x % 10); x /= 10; } return ans; } void solve() { long long m; long long n, d; cin >> n >> d >> m; long long a[n]; long long i, j; vector<long long> large; vector<long long> small; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] <= m) { small.push_back(a[i]); } else { large.push_back(a[i]); } } long long ans = 0; sort(large.begin(), large.end(), greater<int>()); sort(small.begin(), small.end(), greater<int>()); long long temp = 0; for (i = 0; i < small.size(); i++) { temp += small[i]; } ans = max(ans, temp); for (i = 1; i <= large.size(); i++) { temp = 0; if (n - 1 - (i - 1) * (d + 1) >= 0) { long long x = small.size(); for (j = 0; j < min(n - 1 - (i - 1) * (d + 1), x); j++) { temp += small[j]; } temp += large[0]; for (j = 1; j <= i - 1; j++) { temp += large[j]; } } ans = max(ans, temp); } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); long long TC = 1; while (TC--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T x, T y) { if (x < y) swap(x, y); while (y > 0) { T f = x % y; x = y; y = f; } return x; } const int maxn = 200005; int n; int a[maxn]; int dp[maxn]; vector<int> adj[maxn]; void dfs(int u, int p, set<int> gcd0, set<int> gcd1) { dp[u] = *gcd0.rbegin(); if (!gcd1.empty()) { dp[u] = max(dp[u], *gcd1.rbegin()); } for (int v : adj[u]) { if (v != p) { set<int> g0; set<int> g1 = gcd0; for (auto x : gcd0) g0.insert(gcd(x, a[v])); for (auto x : gcd1) g1.insert(gcd(x, a[v])); dfs(v, u, g0, g1); } } } int main(int argc, char *argv[]) { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); cin >> n; { for (int i = 1; i <= n; i++) cin >> a[i], dp[i] = i; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } set<int> gcd0; set<int> gcd1; gcd0.insert(a[1]); gcd1.insert(0); dfs(1, 0, gcd0, gcd1); for (int i = 1; i <= n; i++) { cout << dp[i] << (i == n ? n : ); } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int o_9357fc8171180e5951f52ff0433bc1c2 = 2e5 + 5; int o_c6e13f5716dd4a7981ad58d262f52b74[o_9357fc8171180e5951f52ff0433bc1c2]; int o_9c41a6fd007fd994071a60164bbac5df[o_9357fc8171180e5951f52ff0433bc1c2]; int o_0f2474e49c5126ff73eea4a0af8b5e21[o_9357fc8171180e5951f52ff0433bc1c2]; int o_222c8f12edb48077b7f80e418fc4ae9b; void o_cdc7abbebb884a9b7563651070ab3584( int o_ebaa526c4057d32c4c40ddc1b5853432) { int o_9249d541dcee6d0da9788c8a48341e3f = o_ebaa526c4057d32c4c40ddc1b5853432; while ((o_ebaa526c4057d32c4c40ddc1b5853432 <= o_222c8f12edb48077b7f80e418fc4ae9b) & !!(o_ebaa526c4057d32c4c40ddc1b5853432 <= o_222c8f12edb48077b7f80e418fc4ae9b)) { if ((o_c6e13f5716dd4a7981ad58d262f52b74 [o_0f2474e49c5126ff73eea4a0af8b5e21 [o_ebaa526c4057d32c4c40ddc1b5853432]] < o_c6e13f5716dd4a7981ad58d262f52b74 [o_9249d541dcee6d0da9788c8a48341e3f]) & !!(o_c6e13f5716dd4a7981ad58d262f52b74 [o_0f2474e49c5126ff73eea4a0af8b5e21 [o_ebaa526c4057d32c4c40ddc1b5853432]] < o_c6e13f5716dd4a7981ad58d262f52b74 [o_9249d541dcee6d0da9788c8a48341e3f])) o_0f2474e49c5126ff73eea4a0af8b5e21[o_ebaa526c4057d32c4c40ddc1b5853432] = o_9249d541dcee6d0da9788c8a48341e3f; ; o_ebaa526c4057d32c4c40ddc1b5853432 += o_ebaa526c4057d32c4c40ddc1b5853432 & -o_ebaa526c4057d32c4c40ddc1b5853432; }; }; int o_7b4c14178acfe31ed3721a6cd243d1af(int o_b2c3eb11e9cde933c1d1c4ee68797ae1) { int o_29e92c77d34560f5b43d1a63a2c86194 = (0x0000000000000000 + 0x0000000000000200 + 0x0000000000000800 - 0x0000000000000A00); while ((o_b2c3eb11e9cde933c1d1c4ee68797ae1 > (0x0000000000000000 + 0x0000000000000200 + 0x0000000000000800 - 0x0000000000000A00)) & !!(o_b2c3eb11e9cde933c1d1c4ee68797ae1 > (0x0000000000000000 + 0x0000000000000200 + 0x0000000000000800 - 0x0000000000000A00))) { o_29e92c77d34560f5b43d1a63a2c86194 = max(o_29e92c77d34560f5b43d1a63a2c86194, o_c6e13f5716dd4a7981ad58d262f52b74 [o_0f2474e49c5126ff73eea4a0af8b5e21 [o_b2c3eb11e9cde933c1d1c4ee68797ae1]]); o_b2c3eb11e9cde933c1d1c4ee68797ae1 -= o_b2c3eb11e9cde933c1d1c4ee68797ae1 & -o_b2c3eb11e9cde933c1d1c4ee68797ae1; }; return o_29e92c77d34560f5b43d1a63a2c86194; }; int main() { int o_25edde8d6f07981ced44026f92972458, o_afaa1445a88832680cab678cb0ecba8d; cin >> o_25edde8d6f07981ced44026f92972458 >> o_222c8f12edb48077b7f80e418fc4ae9b >> o_afaa1445a88832680cab678cb0ecba8d; for (int o_a857bef51fd39475b80be11d6b22f6db = (0x0000000000000002 + 0x0000000000000201 + 0x0000000000000801 - 0x0000000000000A03); (o_a857bef51fd39475b80be11d6b22f6db <= o_25edde8d6f07981ced44026f92972458) & !!(o_a857bef51fd39475b80be11d6b22f6db <= o_25edde8d6f07981ced44026f92972458); o_a857bef51fd39475b80be11d6b22f6db++) cin >> o_9c41a6fd007fd994071a60164bbac5df[o_a857bef51fd39475b80be11d6b22f6db]; int o_b5b891a52e873a8d3954f27b2e9eed11 = (0x0000000000000002 + 0x0000000000000201 + 0x0000000000000801 - 0x0000000000000A03), o_cf4ec3c7cd8a5ab051889a363b038203 = (0x0000000000000000 + 0x0000000000000200 + 0x0000000000000800 - 0x0000000000000A00), o_d07ee75e0b7097794bfa2922f8c57846, o_f83a4dfabf25c5eaaef2a7a8b261c1e3 = (0x0000000000000002 + 0x0000000000000201 + 0x0000000000000801 - 0x0000000000000A03); o_c6e13f5716dd4a7981ad58d262f52b74[o_9c41a6fd007fd994071a60164bbac5df[( 0x0000000000000002 + 0x0000000000000201 + 0x0000000000000801 - 0x0000000000000A03)]]++; o_cdc7abbebb884a9b7563651070ab3584(o_9c41a6fd007fd994071a60164bbac5df[( 0x0000000000000002 + 0x0000000000000201 + 0x0000000000000801 - 0x0000000000000A03)]); while ((o_b5b891a52e873a8d3954f27b2e9eed11 <= o_25edde8d6f07981ced44026f92972458) & !!(o_b5b891a52e873a8d3954f27b2e9eed11 <= o_25edde8d6f07981ced44026f92972458)) { o_d07ee75e0b7097794bfa2922f8c57846 = o_b5b891a52e873a8d3954f27b2e9eed11 - o_cf4ec3c7cd8a5ab051889a363b038203 - o_7b4c14178acfe31ed3721a6cd243d1af(o_222c8f12edb48077b7f80e418fc4ae9b); while ((o_cf4ec3c7cd8a5ab051889a363b038203 < o_b5b891a52e873a8d3954f27b2e9eed11) & !!(o_cf4ec3c7cd8a5ab051889a363b038203 < o_b5b891a52e873a8d3954f27b2e9eed11) && (o_d07ee75e0b7097794bfa2922f8c57846 > o_afaa1445a88832680cab678cb0ecba8d) & !!(o_d07ee75e0b7097794bfa2922f8c57846 > o_afaa1445a88832680cab678cb0ecba8d)) { o_cf4ec3c7cd8a5ab051889a363b038203++; o_c6e13f5716dd4a7981ad58d262f52b74 [o_9c41a6fd007fd994071a60164bbac5df [o_cf4ec3c7cd8a5ab051889a363b038203]]--; o_cdc7abbebb884a9b7563651070ab3584( o_9c41a6fd007fd994071a60164bbac5df [o_cf4ec3c7cd8a5ab051889a363b038203]); o_d07ee75e0b7097794bfa2922f8c57846 = o_b5b891a52e873a8d3954f27b2e9eed11 - o_cf4ec3c7cd8a5ab051889a363b038203 - o_7b4c14178acfe31ed3721a6cd243d1af( o_222c8f12edb48077b7f80e418fc4ae9b); }; o_f83a4dfabf25c5eaaef2a7a8b261c1e3 = max( o_f83a4dfabf25c5eaaef2a7a8b261c1e3, o_7b4c14178acfe31ed3721a6cd243d1af(o_222c8f12edb48077b7f80e418fc4ae9b)); o_b5b891a52e873a8d3954f27b2e9eed11++; if ((o_b5b891a52e873a8d3954f27b2e9eed11 > o_25edde8d6f07981ced44026f92972458) & !!(o_b5b891a52e873a8d3954f27b2e9eed11 > o_25edde8d6f07981ced44026f92972458)) break; ; o_c6e13f5716dd4a7981ad58d262f52b74 [o_9c41a6fd007fd994071a60164bbac5df [o_b5b891a52e873a8d3954f27b2e9eed11]]++; o_cdc7abbebb884a9b7563651070ab3584( o_9c41a6fd007fd994071a60164bbac5df[o_b5b891a52e873a8d3954f27b2e9eed11]); }; cout << o_f83a4dfabf25c5eaaef2a7a8b261c1e3; };
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, p; cin >> n >> k; int l = log2(n) + 1; for (long int i = 1; i <= 30; i++) { if (n - i * k > 0) { p = n - i * k; bitset<30> b(p); if (i > b.count() && p != 1 && p >= i) { cout << i; break; } else if (i == b.count()) { cout << i; break; } } else { cout << -1 ; break; } } }
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#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } int n, a, b, ans, ansa[1000000], ansb[1000000], cnta, cntb; bool flag[1000000]; bool check(int k) { int w = a; cnta = cntb = 0; for (int i = 1; i <= k; i++) if (w >= i) ansa[++cnta] = i, w -= i; else break; ansa[cnta + 1] = k + 1; for (int i = cnta; i >= 1; i--) { if (!w) break; while (w && ansa[i] + 1 < ansa[i + 1]) ansa[i]++, w--; } if (b >= 1ll * k * (k + 1) / 2 - (a - w)) return 1; else return 0; } int main() { a = read(), b = read(); n = sqrt((a + b) * 2ll) + 2; int l = 0, r = n; while (l <= r) { int mid = l + r >> 1; if (check(mid)) ans = mid, l = mid + 1; else r = mid - 1; } int w = a; cnta = cntb = 0; for (int i = 1; i <= ans; i++) if (w >= i) ansa[++cnta] = i, w -= i; else break; ansa[cnta + 1] = ans + 1; for (int i = cnta; i >= 1; i--) { if (!w) break; while (w && ansa[i] + 1 < ansa[i + 1]) ansa[i]++, w--; } printf( %d n , cnta); for (int i = 1; i <= cnta; i++) printf( %d , ansa[i]), flag[ansa[i]] = 1; cout << endl; printf( %d n , ans - cnta); for (int i = 1; i <= ans; i++) if (!flag[i]) printf( %d , i); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_TB_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_TB_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkdlyinv3sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_TB_V
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#include <bits/stdc++.h> long long mod = 1000000007; long long mod2 = 998244353; long long OO = 1e18; long long david_villa_pow(long long x, long long n) { if (n == 0) return 1; long long u = david_villa_pow(x, n / 2); u = ((u) * (u)); if (n % 2 == 1) u = ((u) * (x)); return u; } long long up(long long x, long long y) { if (x % y == 0) return x / y; return x / y + 1; } using namespace std; long long a[200200]; int main() { long long i, j; ; long long T; cin >> T; while (T--) { long long n, k, mn = OO; cin >> n >> k; for (i = 0; i < n; i++) { cin >> a[i]; mn = min(mn, a[i]); } long long indx = 0; for (i = 0; i < n; i++) { if (a[i] == mn) { indx = i; break; } } long long res = 0; for (i = 0; i < n; i++) { if (i != indx) { res += (k - a[i]) / mn; } } cout << res << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[100005]; int Gcd(int x, int y) { if (y == 0) return x; return Gcd(y, x % y); } int main(void) { int n, i, ans; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); ans = 0; for (i = 1; i <= n; i++) ans = Gcd(ans, a[i]); if (((a[n] / ans) - (n - 1)) % 2) printf( Bob n ); else printf( Alice n ); return 0; }
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#include <bits/stdc++.h> using namespace std; void debug(int n) { printf( %d n ); } bool cmp(pair<int, pair<int, int> > &a, pair<int, pair<int, int> > &b) { if (a.second.first == b.second.first) { return a.first < b.first; } return a.second.first < b.second.first; } int main() { int n, u, v, kase; scanf( %d , &kase); while (kase--) { scanf( %d , &n); vector<pair<int, pair<int, int> > > q; for (int i = 0; i < n; i++) { scanf( %d%d , &u, &v); q.push_back(make_pair(i, make_pair(u, v))); } sort(q.begin(), q.end(), cmp); vector<int> idx; int time = 0; for (int i = 0; i < n; i++) { time = max(time, q[i].second.first); if (time > q[i].second.second) { idx.push_back(0); } else { idx.push_back(time); time++; } } for (auto i : idx) printf( %d , i); printf( n ); } }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; vector<long long int> v; unordered_map<long long int, long long int> mapy; v.push_back(0); v.push_back(2); mapy[2] = 1; for (long long int i = 2; i <= 100000; i++) { v.push_back(((3 * (i * (i + 1))) / 2) - i); mapy[(((3 * (i * (i + 1))) / 2) - i)] = 1; } while (t--) { long long int n; cin >> n; ; long long int c = 0; while (n > 1) { auto f = lower_bound(v.begin(), v.end(), n); if (mapy[n] == 1) { c++; break; } long long int hj = f - v.begin(); hj--; n -= v[hj]; c++; } cout << c << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.length(); int open = 0; int closed = 0; int hash = 0; for (__typeof((l)) i = 0; i < (l); i++) { if (s[i] == ( ) open++; if (s[i] == ) ) closed++; if (s[i] == # ) hash++; if (open < (closed + hash)) { cout << -1 ; return 0; } } if (hash == 0) { if (open != closed) { cout << -1 ; } return 0; } int count = 0; int closed2 = 0; int open2 = 0; vector<int> ans; for (__typeof((l)) i = 0; i < (l); i++) { if (s[i] == ( ) open2++; if (s[i] == ) ) closed2++; if (s[i] == # && count < (hash - 1)) { ans.push_back(1); count++; } else if (s[i] == # ) { ans.push_back(open - count - closed); count += open - count - closed; } if (open2 < (closed2 + count)) { cout << -1 n ; return 0; } } for (__typeof(ans.begin()) it = ans.begin(); it != ans.end(); ++it) cout << *it << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_MS__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3 (
VPWR,
VGND,
Y ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
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