text
stringlengths 59
71.4k
|
|---|
`timescale 1ns / 1ps
module ad7390 #
(
parameter integer CLK_DIV = 250,
parameter integer DAC_WIDTH = 12,
parameter integer AXI_WIDTH = 16
)
(
input wire aclk,
input wire aresetn,
output reg s_axis_tready,
input wire [AXI_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg dac_clk,
output reg dac_sdi,
output reg dac_ld,
output reg dac_clr
);
reg [15:0] int_clk_div;
reg int_clk;
reg [DAC_WIDTH-1:0] data_reg;
reg data_rx;
reg [3:0] data_rx_bit;
always @(posedge aclk) begin
if (~aresetn) begin
// Reset clock divider
int_clk <= 1'b0;
int_clk_div <= 16'b0;
// Reset outputs
s_axis_tready <= 1'b0;
dac_clk <= 1'b0;
dac_sdi <= 1'b0;
dac_clr <= 1'b1;
dac_ld <= 1'b1;
// Reset internal state
data_rx <= 1'b0;
end else begin
// Accept a new AXI-Stream transfer when possible
if (~data_rx) begin
if (~s_axis_tready) begin
s_axis_tready <= 1'b1;
end else if (s_axis_tvalid) begin
s_axis_tready <= 1'b0;
data_reg <= s_axis_tdata[AXI_WIDTH-2:AXI_WIDTH-DAC_WIDTH-1];
dac_sdi <= s_axis_tdata[AXI_WIDTH-1];
data_rx <= 1'b1;
data_rx_bit <= DAC_WIDTH - 1;
dac_ld <= 1'b1;
// Reset clock divider
int_clk_div <= 1'b0;
int_clk <= 1'b0;
end
end
// Transmit data on negative edges
if (int_clk_div == CLK_DIV && dac_clk == 1) begin
if (data_rx) begin
if (data_rx_bit > 0) begin
data_rx_bit <= data_rx_bit - 1;
{dac_sdi, data_reg} <= {data_reg, 1'b0};
end else begin
dac_ld <= 1'b0;
dac_sdi <= 1'b0;
end
end
end
// Generate divided clock
if (int_clk_div == CLK_DIV) begin
int_clk_div <= 0;
int_clk <= ~int_clk;
if (data_rx && dac_ld) begin
dac_clk <= int_clk;
end else if (~dac_ld) begin
dac_ld <= 1'b1;
data_rx <= 1'b0;
end
end else begin
int_clk_div <= int_clk_div + 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mc[1 << 20]; list<int> th; struct f { long long x, k, m, ms[20]; } fs[100]; bool kcomp(f a, f b) { return a.k < b.k; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, m, b; cin >> n >> m >> b; for (int i = 0; i < n; i++) { cin >> fs[i].x >> fs[i].k >> fs[i].m; for (int j = 0; j < fs[i].m; j++) { cin >> fs[i].ms[j]; fs[i].ms[j]--; } } sort(fs, fs + n, kcomp); long long bst = -1; fill_n(mc, 1 << 20, -1); for (int i = 0; i < n; i++) { int tbt = 0; for (int mi = 0; mi < fs[i].m; mi++) { tbt |= 1 << fs[i].ms[mi]; } int old = mc[tbt]; mc[tbt] = mc[tbt] == -1 ? fs[i].x : min(mc[tbt], fs[i].x); if (old == mc[tbt]) continue; th.push_front(tbt); auto it = th.begin(); auto pe = th.end(); { auto it2 = it; ++it2; for (; it2 != pe; ++it2) { int bt = *it | *it2; if (mc[bt] == -1) th.push_back(bt); mc[bt] = mc[bt] == -1 ? mc[*it] + mc[*it2] : min(mc[bt], mc[*it] + mc[*it2]); } } for (int cpos = 0; it != th.end(); ++it, ++cpos) { auto it2 = pe; auto ce = th.end(); for (; it2 != ce; ++it2) { int bt = *it | *it2; if (mc[bt] == -1) th.push_back(bt); mc[bt] = mc[bt] == -1 ? mc[*it] + mc[*it2] : min(mc[bt], mc[*it] + mc[*it2]); } } if (mc[(1 << m) - 1] != -1) { bst = bst == -1 ? mc[(1 << m) - 1] + b * fs[i].k : min(bst, mc[(1 << m) - 1] + b * fs[i].k); } } cout << bst << n ; }
|
#include <bits/stdc++.h> using namespace std; pair<pair<int, int>, int> e[100010]; int parent[100010]; int Rank[100010]; int sz[100010]; vector<int> v[100010]; bool mark[100010]; bool mark1[100010]; int color[100010]; vector<int> out[2]; bool success[2]; int cnt[2]; int n, m; int find(int cur) { if (parent[cur] == cur) return cur; return parent[cur] = find(parent[cur]); } void Union(int x, int y) { int xroot = find(x); int yroot = find(y); if (xroot == yroot) return; if (Rank[xroot] < Rank[yroot]) parent[xroot] = yroot; else if (Rank[xroot] > Rank[yroot]) parent[yroot] = xroot; else { Rank[xroot]++; parent[yroot] = xroot; } } void init(int n) { int i; for (i = 0; i <= n; ++i) { Rank[i] = 0; parent[i] = i; sz[i] = 0; } } bool dfs(int cur, int c) { mark[cur] = 1; color[cur] = c; cnt[c] += sz[cur]; for (int i = 0; i < v[cur].size(); ++i) { if (mark[v[cur][i]]) { if (color[v[cur][i]] == c) return 0; continue; } if (!dfs(v[cur][i], 1 - c)) return 0; } return 1; } void dfs1(int cur) { mark1[cur] = 1; color[cur] = 1 - color[cur]; for (int i = 0; i < v[cur].size(); ++i) if (!mark1[v[cur][i]]) dfs1(v[cur][i]); } void solve(int f) { int i; init(n); success[f] = 0; for (i = 1; i <= n; ++i) v[i].clear(); for (i = 0; i < m; ++i) if (e[i].second == f) Union(e[i].first.first, e[i].first.second); for (i = 0; i < m; ++i) if (e[i].second != f) { int x = find(e[i].first.first), y = find(e[i].first.second); if (x == y) return; v[x].push_back(y); v[y].push_back(x); } for (i = 1; i <= n; ++i) sz[find(i)]++; memset(mark, 0, sizeof(mark)); memset(mark1, 0, sizeof(mark1)); for (i = 1; i <= n; ++i) { cnt[0] = cnt[1] = 0; if (mark[find(i)]) continue; if (!dfs(find(i), 0)) return; if (cnt[0] > cnt[1]) dfs1(find(i)); } success[f] = 1; for (i = 1; i <= n; ++i) if (color[find(i)] == 0) out[f].push_back(i); } int main() { int i, x, y, c; string s; scanf( %d , &n); scanf( %d , &m); for (i = 0; i < m; ++i) { scanf( %d , &x); scanf( %d , &y); cin >> s; if (s[0] == R ) c = 0; else c = 1; e[i] = make_pair(make_pair(x, y), c); } solve(0); solve(1); int minn = 1000000, minpos; for (i = 0; i < 2; ++i) if (success[i]) if ((int)out[i].size() < minn) { minn = (int)out[i].size(); minpos = i; } if (minn == 1000000) printf( %d n , -1); else { printf( %d n , minn); for (auto it : out[minpos]) printf( %d , it); printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100004; int n, m, c = 0; char s[24][24]; set<unsigned long long> st, ns; bool fun(int x, int y) { st.clear(); for (int i = 0; i < n; i += x) for (int j = 0; j < m; j += y) { ns.clear(); unsigned long long sum = 0; for (int u = 0; u < x; u++) { unsigned long long p = 0; for (int v = 0; v < y; v++) p = p * 131 + s[i + u][j + v]; sum = sum * 997 + p; } ns.insert(sum); sum = 0; for (int u = x - 1; u >= 0; u--) { unsigned long long p = 0; for (int v = y - 1; v >= 0; v--) p = p * 131 + s[i + u][j + v]; sum = sum * 997 + p; } ns.insert(sum); if (x == y) { sum = 0; for (int v = y - 1; v >= 0; v--) { unsigned long long p = 0; for (int u = 0; u < x; u++) p = p * 131 + s[i + u][j + v]; sum = sum * 997 + p; } ns.insert(sum); sum = 0; for (int v = 0; v < y; v++) { unsigned long long p = 0; for (int u = x - 1; u >= 0; u--) p = p * 131 + s[i + u][j + v]; sum = sum * 997 + p; } ns.insert(sum); } for (auto it = ns.begin(); it != ns.end(); it++) { if (st.count(*it)) return 0; st.insert(*it); } } return 1; } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); int x = 100, y = 100, ans = 40000; for (int i = 1; i <= n; i++) if (n % i == 0) for (int j = 1; j <= m; j++) if (m % j == 0) { if (fun(i, j)) { ++c; if (i * j < ans || i * j == ans && i < x) { ans = i * j; x = i; y = j; } } } printf( %d n%d %d n , c, x, y); }
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_rep_upload(//input
clk,
rst,
m_flits_rep,
v_m_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
m_flit_out,
v_m_flit_out,
m_ctrl_out,
m_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] m_flits_rep;
input v_m_flits_rep;
input [3:0] flits_max;
input en_flits_max;
input rep_fifo_rdy;
//output
output [15:0] m_flit_out;
output v_m_flit_out;
output [1:0] m_ctrl_out;
output m_rep_upload_state;
//parameter
parameter m_rep_upload_idle=1'b0;
parameter m_rep_upload_busy=1'b1;
//reg m_req_nstate;
reg m_rep_state;
reg [143:0] m_rep_flits;
reg [3:0] sel_cnt;
reg v_m_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
reg [3:0] flits_max_reg;
reg [1:0] m_ctrl_out;
assign m_rep_upload_state=m_rep_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_m_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
m_ctrl_out=2'b00;
case(m_rep_state)
m_rep_upload_idle:
begin
if(v_m_flits_rep)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
m_rep_upload_busy:
begin
if(rep_fifo_rdy)
begin
if(sel_cnt==flits_max_reg)
begin
fsm_rst=1'b1;
m_ctrl_out=2'b11;
end
else if(sel_cnt==3'b000)
m_ctrl_out=2'b01;
m_ctrl_out=2'b10;
inc_cnt=1'b1;
v_m_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_state<=1'b0;
else if(next)
m_rep_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_flits<=143'h0000;
else if(en_flits_in)
m_rep_flits<=m_flits_rep[175:32];
end
reg [15:0] m_flit_out;
always@(*)
begin
case(sel_cnt)
4'b0000:m_flit_out=m_rep_flits[143:128];
4'b0001:m_flit_out=m_rep_flits[127:112];
4'b0010:m_flit_out=m_rep_flits[111:96];
4'b0011:m_flit_out=m_rep_flits[95:80];
4'b0100:m_flit_out=m_rep_flits[79:64];
4'b0101:m_flit_out=m_rep_flits[63:48];
4'b0110:m_flit_out=m_rep_flits[47:32];
4'b0111:m_flit_out=m_rep_flits[31:16];
4'b1000:m_flit_out=m_rep_flits[15:0];
default:m_flit_out=m_rep_flits[143:128];
endcase
end
// flits_max
always@(posedge clk)
begin
if(rst||fsm_rst)
flits_max_reg<=4'b0000;
else if(en_flits_max)
flits_max_reg<=flits_max;
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=4'b0000;
else if(inc_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_BLACKBOX_V
`define SKY130_FD_SC_HD__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, a, b; int M[256 + 1]; int main() { scanf( %d %d %d , &n, &a, &b); if (a & 1) a++; if (b & 1) b++; int round = 1; for (;;) { a /= 2; b /= 2; if (a == b) break; round++; if (a & 1) a++; if (b & 1) b++; } if (round == (int)log2(n)) printf( Final! n ); else printf( %d n , round); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; long long int a[n + 2]; vector<long long int> pre(n + 2); for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { pre[i] = pre[i - 1] + a[i]; } int left = 1; int num = -1, occur = -1; for (int i = 1; i <= n; i++) { while ((a[i] * (i - left + 1) - (pre[i] - pre[left - 1])) > k) left++; if (occur < (i - left + 1)) { occur = i - left + 1; num = a[i]; } } cout << occur << << num << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = (long long)1e5 + 10; vector<long long> G[MAXN]; pair<long long, long long> p; vector<long long> v; long long n, x, y, k, ans, sum, flag; string s; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; v.push_back(x); v.push_back(y); } cin >> k; long long i = 0; while (!flag) { if (v[i] < k) { i++; } else { flag = 1; i--; } } cout << n - (i + 1) / 2; return 0; }
|
//Register File
module regfile (
clk, // Clock
x, //External Input
ld, //Whether or not to load destination register from extenral input
d, //Destination register
sa, //1st Source Register
sb, // 2nd Source Register
a, // Output a
b // Output b
);
parameter n = 16; //n bits per register
parameter k = 4; //2^k registers
//--- Input Ports ---
input clk;
input [n-1:0] x;
input ld;
input [k-1:0] d, sa, sb;
//--- Output Ports ---
output wire [n - 1:0] a, b;
//-- Internal Data ---
wire [n - 1:0] a0, a1, b0, b1;
wire ld0, ld1;
generate
// Base case of 2 regfiles left
if (k == 1) begin
regfile1 #(.n(n)) rfile1A(clk, x, ld0, a0, b0);
regfile1 #(.n(n)) rfile1B(clk, x, ld1, a1, b1);
// 2^k bit regfile
end else begin
regfile #(.k(k-1), .n(n)) rFileA(clk, x, ld0, d[k-2:0], sa[k-2:0], sb[k-2:0], a0, b0);
regfile #(.k(k-1), .n(n)) rFileB(clk, x, ld1, d[k-2:0], sa[k-2:0], sb[k-2:0], a1, b1);
end
endgenerate
function [n-1:0] mux1w;
input v;
input [n-1:0]x1;
input [n-1:0]x2;
begin
if (v) begin
mux1w = x2;
end else begin
mux1w = x1;
end
end
endfunction
assign ld0 = (!d[k-1]) & ld;
assign ld1 = d[k-1] & ld;
assign a = mux1w(sa[k-1], a0, a1);
assign b = mux1w(sb[k-1], b0, b1);
endmodule
module regfile1 (
clk, // Clock
x, //External Input
ld, //Whether or not to load destination register from external input
r, // Output a
r // Output b
);
parameter n = 16; //n bit register
//--- Inputs ---
input clk;
input [n - 1: 0] x;
input ld;
//--- Outputs ---
output reg [n-1:0] r;
always @(posedge clk) begin
if (ld) begin
r <= x;
end else begin
r <= r;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char arr[50][50]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if ((i % 2 == 0 || ((i % 4 == 1 && j == m - 1) || (i % 4 == 3 && j == 0)))) arr[i][j] = # ; else arr[i][j] = . ; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << arr[i][j]; cout << n ; } }
|
module Counter_TV1 #(
parameter Width = 16
) (
(* intersynth_port = "Reset_n_i" *)
input Reset_n_i,
(* intersynth_port = "Clk_i" *)
input Clk_i,
(* intersynth_conntype = "Bit" *)
input ResetSig_i,
(* intersynth_conntype = "Bit" *)
input Preset_i,
(* intersynth_conntype = "Bit" *)
input Enable_i,
(* intersynth_conntype = "Bit" *)
input Direction_i,
(* intersynth_conntype = "Word" *)
input[Width-1:0] PresetVal_i,
(* intersynth_conntype = "Word" *)
output[Width-1:0] D_o,
(* intersynth_conntype = "Bit" *)
output Overflow_o,
(* intersynth_conntype = "Bit" *)
output Zero_o
);
reg [Width-1:0] Value;
reg Ovfl;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Value <= 'd0;
Ovfl <= 1'd0;
end
else
begin
if (ResetSig_i) begin
Value <= 'd0;
Ovfl <= 1'b0;
end else if (Preset_i) begin
Value <= PresetVal_i;
Ovfl <= 1'b0;
end else if (Enable_i)
begin
if (!Direction_i)
{Ovfl, Value} <= Value + 1'b1;
else
{Ovfl, Value} <= Value - 1'b1;
end
end
end
assign D_o = Value;
assign Zero_o = (Value == 0 ? 1'b1 : 1'b0);
assign Overflow_o = Ovfl;
endmodule
|
#include <bits/stdc++.h> static const int MAXN = 2e5 + 10; int n, m; std::pair<int, int> p[MAXN]; int x_idx[MAXN], x[MAXN]; int a_i, l_i; inline int solve_query(int u, int len) { while (true) { int last_len = len; int p = std::upper_bound(x, x + n, x[u] + len) - x - 1; len -= (x[p] - x[u]); int q = std::lower_bound(x, x + n, x[p] - len) - x; len -= (x[p] - x[q]); if (p == q) return q; else if (u == q) len %= (last_len - len); u = q; } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d , &p[i].first); p[i].second = i + 1; } std::sort(p, p + n); for (int i = 0; i < n; ++i) { x[i] = p[i].first; x_idx[p[i].second] = i; } for (int i = 0; i < m; ++i) { scanf( %d%d , &a_i, &l_i); printf( %d n , p[solve_query(x_idx[a_i], l_i)].second); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; double n; cin >> t; while (t--) { cin >> n; if (n * n - 4 * n < 0) { cout << N << endl; continue; } if (n == 0) { double x = 0, y = 0; cout << Y << fixed << setprecision(9) << x << << y << endl; continue; } double x = n + sqrt(n * n - 4 * n); x /= 2; double y = x / (x - 1); cout << Y << fixed << setprecision(9) << x << << y << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string a, b; int main() { int n; while (cin >> n) { cin >> a >> b; long long ans = 0; long long x = 0, y = 0, p = 0, q = 0; for (int i = 0; i < n; i++) if (b[i] == 1 ) a[i] == 0 ? x++ : y++; for (int i = 0; i < n; i++) if (b[i] == 0 ) a[i] == 0 ? p++ : q++; for (int i = 0; i < n; i++) if (b[i] == 0 ) a[i] == 0 ? ans += y : ans += x; ans += (long long)p * q; cout << ans << endl; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// TxfifoBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
`include "wishBoneBus_h.v"
module TxfifoBI (
address, writeEn, strobe_i,
busClk,
usbClk,
rstSyncToBusClk,
fifoSelect,
busDataIn,
busDataOut,
fifoWEn,
forceEmptySyncToUsbClk,
forceEmptySyncToBusClk,
numElementsInFifo
);
input [2:0] address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
input rstSyncToBusClk;
input [7:0] busDataIn;
output [7:0] busDataOut;
output fifoWEn;
output forceEmptySyncToUsbClk;
output forceEmptySyncToBusClk;
input [15:0] numElementsInFifo;
input fifoSelect;
wire [2:0] address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
reg fifoWEn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoSelect;
reg forceEmptyReg;
reg forceEmpty;
reg forceEmptyToggle;
reg [2:0] forceEmptyToggleSyncToUsbClk;
//sync write
always @(posedge busClk)
begin
if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
forceEmpty <= 1'b1;
else
forceEmpty <= 1'b0;
end
//detect rising edge of 'forceEmpty', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClk == 1'b1) begin
forceEmptyReg <= 1'b0;
forceEmptyToggle <= 1'b0;
end
else begin
if (forceEmpty == 1'b1)
forceEmptyReg <= 1'b1;
else
forceEmptyReg <= 1'b0;
if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
forceEmptyToggle <= ~forceEmptyToggle;
end
end
assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
always @(posedge usbClk) begin
forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
end
assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
// async read mux
assign busDataOut = 8'h00;
//always @(address or fifoFull or numElementsInFifo)
//begin
// case (address)
// `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
// `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
// `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
// default: busDataOut <= 8'h00;
// endcase
//end
//generate fifo write strobe
always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
strobe_i == 1'b1 && fifoSelect == 1'b1)
fifoWEn <= 1'b1;
else
fifoWEn <= 1'b0;
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Audio Processing Unit.
***************************************************************************************************/
module apu(
input clk_in, // system clock signal
input rst_in, // reset signal
input [ 3:0] mute_in, // disable specific audio channels
input [15:0] a_in, // addr input bus
input [ 7:0] d_in, // data input bus
input r_nw_in, // read/write select
output audio_out, // pwm audio output
output [ 7:0] d_out // data output bus
);
localparam [15:0] PULSE0_CHANNEL_CNTL_MMR_ADDR = 16'h4000;
localparam [15:0] PULSE1_CHANNEL_CNTL_MMR_ADDR = 16'h4004;
localparam [15:0] TRIANGLE_CHANNEL_CNTL_MMR_ADDR = 16'h4008;
localparam [15:0] NOISE_CHANNEL_CNTL_MMR_ADDR = 16'h400C;
localparam [15:0] STATUS_MMR_ADDR = 16'h4015;
localparam [15:0] FRAME_COUNTER_CNTL_MMR_ADDR = 16'h4017;
// CPU cycle pulse. Ideally this would be generated in rp2a03 and shared by the apu and cpu.
reg [5:0] q_clk_cnt;
wire [5:0] d_clk_cnt;
wire cpu_cycle_pulse;
wire apu_cycle_pulse;
wire e_pulse;
wire l_pulse;
wire f_pulse;
reg q_pulse0_en;
wire d_pulse0_en;
reg q_pulse1_en;
wire d_pulse1_en;
reg q_triangle_en;
wire d_triangle_en;
reg q_noise_en;
wire d_noise_en;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_clk_cnt <= 6'h00;
q_pulse0_en <= 1'b0;
q_pulse1_en <= 1'b0;
q_triangle_en <= 1'b0;
q_noise_en <= 1'b0;
end
else
begin
q_clk_cnt <= d_clk_cnt;
q_pulse0_en <= d_pulse0_en;
q_pulse1_en <= d_pulse1_en;
q_triangle_en <= d_triangle_en;
q_noise_en <= d_noise_en;
end
end
assign d_clk_cnt = (q_clk_cnt == 6'h37) ? 6'h00 : q_clk_cnt + 6'h01;
assign d_pulse0_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[0] : q_pulse0_en;
assign d_pulse1_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[1] : q_pulse1_en;
assign d_triangle_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[2] : q_triangle_en;
assign d_noise_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[3] : q_noise_en;
assign cpu_cycle_pulse = (q_clk_cnt == 6'h00);
apu_div #(.PERIOD_BITS(1)) apu_pulse_gen(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse),
.reload_in(1'b0),
.period_in(1'b1),
.pulse_out(apu_cycle_pulse)
);
//
// Frame counter.
//
wire frame_counter_mode_wr;
apu_frame_counter apu_frame_counter_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.apu_cycle_pulse_in(apu_cycle_pulse),
.mode_in(d_in[7:6]),
.mode_wr_in(frame_counter_mode_wr),
.e_pulse_out(e_pulse),
.l_pulse_out(l_pulse),
.f_pulse_out(f_pulse)
);
assign frame_counter_mode_wr = ~r_nw_in && (a_in == FRAME_COUNTER_CNTL_MMR_ADDR);
//
// Pulse 0 channel.
//
wire [3:0] pulse0_out;
wire pulse0_active;
wire pulse0_wr;
apu_pulse #(.CHANNEL(0)) apu_pulse0_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse0_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse0_wr),
.pulse_out(pulse0_out),
.active_out(pulse0_active)
);
assign pulse0_wr = ~r_nw_in && (a_in[15:2] == PULSE0_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Pulse 1 channel.
//
wire [3:0] pulse1_out;
wire pulse1_active;
wire pulse1_wr;
apu_pulse #(.CHANNEL(1)) apu_pulse1_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse1_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse1_wr),
.pulse_out(pulse1_out),
.active_out(pulse1_active)
);
assign pulse1_wr = ~r_nw_in && (a_in[15:2] == PULSE1_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Triangle channel.
//
wire [3:0] triangle_out;
wire triangle_active;
wire triangle_wr;
apu_triangle apu_triangle_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_triangle_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(triangle_wr),
.triangle_out(triangle_out),
.active_out(triangle_active)
);
assign triangle_wr = ~r_nw_in && (a_in[15:2] == TRIANGLE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Noise channel.
//
wire [3:0] noise_out;
wire noise_active;
wire noise_wr;
apu_noise apu_noise_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_noise_en),
.apu_cycle_pulse_in(apu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(noise_wr),
.noise_out(noise_out),
.active_out(noise_active)
);
assign noise_wr = ~r_nw_in && (a_in[15:2] == NOISE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Mixer.
//
apu_mixer apu_mixer_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.mute_in(mute_in),
.pulse0_in(pulse0_out),
.pulse1_in(pulse1_out),
.triangle_in(triangle_out),
.noise_in(noise_out),
.audio_out(audio_out)
);
assign d_out = (r_nw_in && (a_in == STATUS_MMR_ADDR)) ?
{ 4'b0000, noise_active, triangle_active, pulse1_active, pulse0_active } : 8'h00;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; struct node { int s, r, no; } xx[500001], dance[500001], fire[500001]; bool cmp(node x, node y) { return x.s > y.s || (x.s == y.s && x.r > y.r); } int S[500001]; int ans[500001]; int mal = 0; int k; int q; bool yes[500001]; double eps = 1e-6; int h, t; map<int, int> X; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> xx[i].s >> xx[i].r; for (int i = 1; i <= n; i++) xx[i].no = i; sort(xx + 1, xx + n + 1, cmp); for (int i = 1; i <= n; i++) { if (mal > xx[i].r) continue; if (mal == xx[i].r && q == xx[i].s) { dance[++k] = xx[i]; continue; } if (q == xx[i].s) continue; if (mal == xx[i].r) continue; { dance[++k] = xx[i]; mal = xx[i].r; q = xx[i].s; } } h = 1; fire[++t] = dance[1]; for (int i = 2; i <= k; i++) { if (h <= t && dance[i].r <= fire[t].r) continue; while (h < t) { long long s1 = fire[t - 1].s, s2 = fire[t].s, r1 = fire[t - 1].r, r2 = fire[t].r; long long s3 = dance[i].s, r3 = dance[i].r; long long k1 = (s3 - s2) * (r1 - r2) * r3 * s1; long long k2 = (s1 - s2) * (r3 - r2) * r1 * s3; if (k1 < k2) t--; else break; } fire[++t] = dance[i]; } int xxx = 0; for (int i = 1; i <= t; i++) { X[fire[i].s] = fire[i].r; } for (int i = 1; i <= n; i++) { if (X[xx[i].s] == xx[i].r) ans[++xxx] = xx[i].no; } sort(ans + 1, ans + xxx + 1); for (int i = 1; i <= xxx; i++) cout << ans[i] << ; }
|
#include <bits/stdc++.h> const int maxn = 50; using namespace std; long long n, k, M; int a[maxn + 5], b[maxn * maxn]; void ok() { long long ans = 0, cot = 0, tot = 0, cnt = 0, sum = 0; sort(a + 1, a + k + 1); for (int i = 1; i <= k; i++) cot += a[i]; for (int i = 0; i <= n; i++) { tot = cot * i; if (tot > M) break; sum = tot, cnt = (k + 1) * i; for (int j = 1; j <= k; j++) { for (int r = i + 1; r <= n; r++) { sum += a[j]; cnt++; if (sum > M) { cnt--, j = k + 1; break; } } } ans = max(ans, cnt); } printf( %I64d n , ans); } int main() { while (~scanf( %I64d %I64d %I64d , &n, &k, &M)) { for (int i = 1; i <= k; i++) scanf( %d , &a[i]); ok(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; struct trie { int cnt, whole; trie *next[26]; trie() { cnt = 0; for (int i = 0; i < 26; ++i) next[i] = NULL; } } *root = new trie(); void ins(char *s) { trie *p = root; for (int i = 0; s[i]; ++i) { int c = s[i] - a ; if (p->next[c] == NULL) p->next[c] = new trie(); p = p->next[c]; } p->cnt++; } vector<int> *dp(trie *p, int dep) { int pos = -1, cnt = 0; for (int i = 0; i < 26; ++i) { if (p->next[i] != NULL) { pos = i; cnt++; } } if (cnt == 0) { vector<int> *ret = new vector<int>(p->cnt + 1); for (int i = 0; i <= p->cnt; ++i) (*ret)[i] = i * (i - 1) * dep / 2; return ret; } else if (cnt == 1 && p->whole == p->next[pos]->whole) { return dp(p->next[pos], dep + 1); } else { vector<int> *ret = new vector<int>(p->whole + 1, 0); for (int i = 0; i <= p->cnt; ++i) (*ret)[i] = i * (i - 1) * dep / 2; int lim = p->cnt; for (int i = 0; i < 26; ++i) { if (p->next[i] != NULL) { vector<int> *tmp = dp(p->next[i], dep + 1); for (int j = lim; j >= 0; --j) for (int k = 1; k < (int)tmp->size() && j + k <= lim + p->next[i]->whole; ++k) (*ret)[j + k] = max((*ret)[j + k], (*ret)[j] + (*tmp)[k] + (j * k * dep)); lim += p->next[i]->whole; } } return ret; } } int dfs(trie *p) { p->whole = p->cnt; for (int i = 0; i < 26; ++i) if (p->next[i] != NULL) p->whole += dfs(p->next[i]); return p->whole; } int main() { char s[512]; scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) { scanf( %s , s); ins(s); } dfs(root); printf( %d n , (*dp(root, 0))[k]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); template <class T> long long chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <class T> long long chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <class T> T sqr(T a) { return a * a; } template <class T> T mmin(T a, T b) { return a < b ? a : b; } template <class T> T mmax(T a, T b) { return a > b ? a : b; } template <class T> T aabs(T a) { return a < 0 ? -a : a; } template <class T> long long dcmp(T a, T b) { return a > b; } template <long long *a> long long cmp_a(long long first, long long second) { return a[first] < a[second]; } namespace io { const long long SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; long long f, qr; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char first) { *oS++ = first; if (oS == oT) flush(); } inline bool read(signed &first) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; else if (c == EOF) return 0; for (first = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) first = first * 10 + (c & 15); first *= f; return 1; } inline bool read(long long &first) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; else if (c == EOF) return 0; for (first = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) first = first * 10 + (c & 15); first *= f; return 1; } inline bool read(char &first) { first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); return first != EOF; } inline bool read(char *first) { while ((*first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) == n || *first == || *first == r ) if (*first == EOF) return 0; while (!(*first == n || *first == || *first == r || *first == EOF)) *(++first) = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); *first = 0; return 1; } template <typename A, typename... B> inline bool read(A &first, B &...second) { return read(first) && read(second...); } inline bool write(signed first) { if (!first) putc( 0 ); if (first < 0) putc( - ), first = -first; while (first) qu[++qr] = first % 10 + 0 , first /= 10; while (qr) putc(qu[qr--]); return 0; } inline bool write(long long first) { if (!first) putc( 0 ); if (first < 0) putc( - ), first = -first; while (first) qu[++qr] = first % 10 + 0 , first /= 10; while (qr) putc(qu[qr--]); return 0; } inline bool write(char first) { putc(first); return 0; } inline bool write(const char *first) { while (*first) { putc(*first); ++first; } return 0; } inline bool write(char *first) { while (*first) { putc(*first); ++first; } return 0; } template <typename A, typename... B> inline bool write(A first, B... second) { return write(first) || write(second...); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io ::putc; using io ::read; using io ::write; long long inf; struct _init_ { _init_() { memset(&inf, 0x3f, sizeof(inf)); } }; _init_ ___INIT__; long long a[20005], b[20005]; long long f[40005], beg[20005]; vector<long long> poly[40005]; long long t; const long long p = 998244353, g = 3; long long rev[1 << 18]; long long fpm(long long a, long long b) { long long c = 1; for (; b; b >>= 1, a = a * a % p) if (b & 1) c = c * a % p; return c; } void NTT(vector<long long> &a, long long n, long long flg) { for (long long i = 0; i < n; ++i) { rev[i] = (rev[i >> 1] >> 1) | ((i & 1) * (n >> 1)); if (i < rev[i]) swap(a[i], a[rev[i]]); } for (long long i = 1; i < n; i <<= 1) { long long ww = fpm(g, (p - 1) / i / 2 * (flg + p - 1)), w; for (long long j = 0; j < n; j += i + i) { w = 1; for (long long k = 0; k < i; ++k) { long long u = a[j + k], v = a[j + k + i] * w % p; a[j + k] = (u + v) % p; a[j + k + i] = (u - v + p) % p; w = w * ww % p; } } } if (flg == -1) { long long in = fpm(n, p - 2); for (long long i = 0; i < n; ++i) a[i] = a[i] * in % p; } } void Prod(vector<long long> &a, vector<long long> &b, vector<long long> &c) { long long first = a.size() + b.size(), n = 1; while (n < first) n <<= 1; a.resize(n); b.resize(n); c.resize(n); NTT(a, n, 1); NTT(b, n, 1); for (long long i = 0; i < n; ++i) c[i] = a[i] * b[i] % p; NTT(c, n, -1); c.resize(first - 1); a.clear(); b.clear(); } long long query(long long k) { long long l = 1; while (l < t) { Prod(poly[l], poly[l + 1], poly[++t]); l += 2; } return poly[t][k]; } signed main() { long long n, k; read(n, k); for (long long i = 1; i <= n; ++i) read(a[i]); long long q; long long tp, first, l, r, d; read(q); for (; q; --q) { read(tp, first, l); if (tp == 1) { read(d); for (long long i = 1; i <= n; ++i) { poly[i].clear(); poly[i].push_back(1); poly[i].push_back((first - (i == l ? d : a[i]) + 2 * p) % p); } } else { read(r, d); for (long long i = 1; i <= n; ++i) { poly[i].clear(); poly[i].push_back(1); poly[i].push_back((first - a[i] + 2 * p) % p); } for (long long i = l; i <= r; ++i) poly[i][1] = (poly[i][1] + 2 * p - d) % p; } t = n; write(query(k), n ); } return 0; }
|
`timescale 1ps/1ps
//Overivew
//========
//This file contains the verilog primitives produced by VPR's
//post-synthesis netlist writer.
//
//If you wish to do back-annotated timing simulation you will need
//to link with this file during simulation.
//
//To ensure currect result when performing back-annoatation with
//Modelsim see the notes at the end of this comment.
//
//Specifying Timing Edges
//=======================
//To perform timing back-annotation the simulator must know the delay
//dependancies (timing edges) between the ports on each primitive.
//
//During back-annotation the simulator will attempt to annotate SDF delay
//values onto the timing edges. It should give a warning if was unable
//to find a matching edge.
//
//
//In Verilog timing edges are specified using a specify block (delimited by the
//'specify' and 'endspecify' keywords.
//
//Inside the specify block a set of specify statements are used to describe
//the timing edges. For example consider:
//
// input [1:0] in;
// output [1:0] out;
// specify
// (in[0] => out[0]) = "";
// (in[1] => out[1]) = "";
// endspecify
//
//This states that there are the following timing edges (dependancies):
// * from in[0] to out[0]
// * from in[1] to out[1]
//
//We could (according to the Verilog standard) equivalently have used:
//
// input [1:0] in;
// output [1:0] out;
// specify
// (in => out) = "";
// endspecify
//
//However NOT ALL SIMULATORS TREAT MULTIBIT SPECIFY STATEMENTS CORRECTLY,
//at least by default (in particular ModelSim, see notes below).
//
//The previous examples use the 'parrallel connection' operator '=>', which
//creates parallel edges between the two operands (i.e. bit 0 to bit 0, bit
//1 to bit 1 etc.). Note that both operands must have the same bit-width.
//
//Verilog also supports the 'full connection' operator '*>' which will create
//a fully connected set of edges (e.g. from all-to-all). It does not require
//both operands to have the same bit-width. For example:
//
// input [1:0] in;
// output [2:0] out;
// specify
// (in *> out) = "";
// endspecify
//
//states that there are the following timing edges (dependancies):
// * from in[0] to out[0]
// * from in[0] to out[1]
// * from in[0] to out[2]
// * from in[1] to out[0]
// * from in[1] to out[1]
// * from in[1] to out[2]
//
//For more details on specify blocks see Section 14 "Specify Blocks" of the
//Verilog standard (IEEE 1364-2005).
//
//Back-annotation with Modelsim
//=============================
//
//Ensuring Multi-bit Specifies are Handled Correctly: Bit-blasting
//----------------------------------------------------------------
//
//ModelSim (tested on Modelsim SE 10.4c) ignores multi-bit specify statements
//by default.
//
//This causes SDF annotation errors such as:
//
// vsim-SDF-3261: Failed to find matching specify module path
//
//To force Modelsim to correctly interpret multi-bit specify statements you
//should provide the '+bitblast' option to the vsim executable.
//This forces it to apply specify statements using multi-bit operands to
//each bit of the operand (i.e. according to the Verilog standard).
//
//Confirming back-annotation is occuring correctly
//------------------------------------------------
//
//Another useful option is '+sdf_verbose' which produces extra output about
//SDF annotation, which can be used to verify annotation occured correctly.
//
//For example:
//
// Summary of Verilog design objects annotated:
//
// Module path delays = 5
//
// ******************************************************************************
//
// Summary of constructs read:
//
// IOPATH = 5
//
//shows that all 5 IOPATH constructs in the SDF were annotated to the verilog
//design.
//
//Example vsim Command Line
//--------------------------
//The following is an example command-line to vsim (where 'tb' is the name of your
//testbench):
//
// vsim -t 1ps -L rtl_work -L work -voptargs="+acc" +sdf_verbose +bitblast tb
//K-input Look-Up Table
module LUT_K #(
//The Look-up Table size (number of inputs)
parameter K=4,
//The lut mask.
//Left-most (MSB) bit corresponds to all inputs logic one.
//Defaults to always false.
parameter LUT_MASK={2**K{1'b0}}
) (
input [K-1:0] in,
output out
);
assign out = LUT_MASK[in];
endmodule
//D-FlipFlop module
module DFF #(
parameter INITIAL_VALUE=1'b0
) (
input clock,
input D,
output reg Q
);
initial begin
Q <= INITIAL_VALUE;
end
always@(posedge clock) begin
Q <= D;
end
endmodule
//Routing fpga_interconnect module
module fpga_interconnect(
input datain,
output dataout
);
assign dataout = datain;
endmodule
//2-to-1 mux module
module mux(
input select,
input x,
input y,
output z
);
assign z = (x & ~select) | (y & select);
endmodule
//n-bit adder
module adder #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input cin,
output cout,
output [WIDTH-1:0] sumout);
assign {cout, sumout} = a + b + cin;
endmodule
//nxn multiplier module
module multiply #(
//The width of input signals
parameter WIDTH = 1
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [2*WIDTH-1:0] out
);
assign out = a * b;
endmodule // mult
//single_port_ram module
module single_port_ram #(
parameter ADDR_WIDTH = 1,
parameter DATA_WIDTH = 1
) (
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] data,
input we,
input clock,
output reg [DATA_WIDTH-1:0] out
);
localparam MEM_DEPTH = 2 ** ADDR_WIDTH;
reg [DATA_WIDTH-1:0] Mem[MEM_DEPTH-1:0];
always@(posedge clock) begin
if(we) begin
Mem[addr] = data;
end
out = Mem[addr]; //New data read-during write behaviour (blocking assignments)
end
endmodule // single_port_RAM
//dual_port_ram module
module dual_port_ram #(
parameter ADDR_WIDTH = 1,
parameter DATA_WIDTH = 1
) (
input clock,
input [ADDR_WIDTH-1:0] addr1,
input [ADDR_WIDTH-1:0] addr2,
input [DATA_WIDTH-1:0] data1,
input [DATA_WIDTH-1:0] data2,
input we1,
input we2,
output reg [DATA_WIDTH-1:0] out1,
output reg [DATA_WIDTH-1:0] out2
);
localparam MEM_DEPTH = 2 ** ADDR_WIDTH;
reg [DATA_WIDTH-1:0] Mem[MEM_DEPTH-1:0];
always@(posedge clock) begin //Port 1
if(we1) begin
Mem[addr1] = data1;
end
out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
end
always@(posedge clock) begin //Port 2
if(we2) begin
Mem[addr2] = data2;
end
out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments)
end
endmodule // dual_port_ram
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fifo_32_to_8 #(
parameter DEPTH = 1024*4
) (
input wire CLK,
input wire RST,
input wire WRITE,
input wire READ,
input wire [31:0] DATA_IN,
output wire FULL,
output wire EMPTY,
output wire [7:0] DATA_OUT
);
reg [1:0] byte_cnt;
wire FIFO_EMPTY, READ_FIFO;
wire [31:0] FIFO_DATA_OUT;
assign EMPTY = byte_cnt==0 & FIFO_EMPTY;
assign READ_FIFO = (byte_cnt==0 & !FIFO_EMPTY && READ);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(DEPTH)
) fifo_i (
.clk(CLK),
.reset(RST),
.write(WRITE),
.read(READ_FIFO),
.data_in(DATA_IN),
.full(FULL),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA_OUT),
.size()
);
always @(posedge CLK)
if(RST)
byte_cnt <= 0;
else if (READ)
byte_cnt <= byte_cnt + 1;
reg [31:0] DATA_BUF;
always @(posedge CLK)
if(READ_FIFO)
DATA_BUF <= FIFO_DATA_OUT;
wire [7:0] FIFO_DATA_OUT_BYTE [3:0];
assign FIFO_DATA_OUT_BYTE[0] = FIFO_DATA_OUT[7:0];
assign FIFO_DATA_OUT_BYTE[1] = DATA_BUF[15:8];
assign FIFO_DATA_OUT_BYTE[2] = DATA_BUF[23:16];
assign FIFO_DATA_OUT_BYTE[3] = DATA_BUF[31:24];
assign DATA_OUT = FIFO_DATA_OUT_BYTE[byte_cnt];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s, r; cin >> s; int k, l, x, n; cin >> k; l = s.length(); if (l % k != 0) { cout << NO n ; return 0; } x = l / k; for (int i = 0; i < l; i += x) { r = s.substr(i, x); n = r.length() - 1; for (int j = 0; j <= n / 2; j++) { if (r[j] != r[n - j]) { cout << NO n ; return 0; } } } cout << YES n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int f[N]; void init() { for (int i = 1; i <= N; i++) { f[i] = f[i - 1] + i * 2 + (i - 1); if (f[i] >= 1e9) { break; } } } int Find(int x) { int l = 0, r = 25820; while (l < r) { int mid = (l + r + 1) / 2; if (f[mid] <= x) l = mid; else r = mid - 1; } return l; } int main() { int T; scanf( %d , &T); init(); while (T--) { int x; scanf( %d , &x); int ans = 0; while (true) { int t = Find(x); if (f[t] <= 0) break; x -= f[t]; ans++; } printf( %d n , ans); } return 0; }
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("tee_local.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 17;
reg [STACK_DEPTH:0] index = 1;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("tee_local_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#39
`assert(result, 2);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n); for (auto &i : arr) cin >> i; int maxx = 0; for (auto i : arr) maxx = max(maxx, i); cout << (maxx xor arr.back()); return 0; }
|
`timescale 1 ns / 1 ps
// BRAM PORTA input
// BRAM PORTB input
// BRAM PORTC output
module bram_switch #
(
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 15 // 2^11 = 2048 positions
)
(
// System signals
input wire switch,
// BRAM PORT A
input wire bram_porta_clk,
input wire bram_porta_rst,
input wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
input wire bram_porta_we,
// BRAM PORT B
input wire bram_portb_clk,
input wire bram_portb_rst,
input wire [BRAM_ADDR_WIDTH-1:0] bram_portb_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_portb_wrdata,
output wire [BRAM_DATA_WIDTH-1:0] bram_portb_rddata,
input wire bram_portb_we,
// BRAM PORT C
output wire bram_portc_clk,
output wire bram_portc_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_portc_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_portc_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_portc_rddata,
output wire bram_portc_we
);
// reg int_clk;
//assign bram_portc_clk = int_clk;
//assign bram_portc_clk = switch == 1 ? bram_porta_clk : bram_portb_clk;
//assign int_clk = switch == 1 ? bram_porta_clk : bram_portb_clk;
assign bram_portc_rst = switch == 1 ? bram_porta_rst : bram_portb_rst;
assign bram_portc_addr = switch == 1 ? bram_porta_addr : bram_portb_addr;
assign bram_portc_wrdata = switch == 1 ? bram_porta_wrdata : bram_portb_wrdata;
assign bram_portc_we = switch == 1 ? bram_porta_we: bram_portb_we;
assign bram_porta_rddata = switch == 1 ? bram_portc_rddata : {(BRAM_DATA_WIDTH){1'b0}};
assign bram_portb_rddata = switch == 0 ? bram_portc_rddata : {(BRAM_DATA_WIDTH){1'b0}};
// BUFGCTRL bugmux (.O(bram_portc_clk),
// .CE0(~switch),
// .CE1(switch),
// .I0(bram_portb_clk),
// .I1(bram_porta_clk),
// .IGNORE0(1'b0),
// .IGNORE1(1'b0),
// .S0(1'b1), // Clock select0 input
// .S1(1'b1) // Clock select1 input
// );
BUFGMUX #(
)
BUFGMUX_inst (
.O(bram_portc_clk), // 1-bit output: Clock output
.I0(bram_portb_clk), // 1-bit input: Clock input (S=0)
.I1(bram_porta_clk), // 1-bit input: Clock input (S=1)
.S(switch) // 1-bit input: Clock select
);
//(.INIT_OUT(0),
// .PRESELECT_I0(FALSE),
// .PRESELECT_I1(FALSE)
// )
//BUFG adc_clk_inst (.I(int_clk), .O(bram_portc_clk));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long abs(long long, long long); double dis(long long x1, long long y1, long long x2, long long y2) { double d = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); d = sqrt(d * 1.0); return d; } void solve() { long long w, h; cin >> w >> h; long long u1, d1, u2, d2; cin >> u1 >> d1 >> u2 >> d2; long long a = w; for (long long i = h; i > 0; i--) { a += i; if (i == d1) { a -= u1; if (a < 0) a = 0; } if (i == d2) { a -= u2; if (a < 0) a = 0; } } cout << a; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long TESTS = 1; while (TESTS--) { solve(); } return 0; } long long abs(long long a, long long b) { if (a > b) return a - b; else return b - a; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int max_n = 1e5 + 5; string q[max_n]; int dig[10][2]; int main() { string s; cin >> s; int n; scanf( %d , &n); for (int i = 1; i <= n; i++) cin >> q[i]; for (int i = 0; i <= 9; i++) { dig[i][0] = i; dig[i][1] = 10; } for (int i = n; i >= 1; i--) { int d = q[i][0] - 0 ; int len = q[i].length(); int sum = 0, pw = 1; for (int j = 3; j < len; j++) { int k = q[i][j] - 0 ; sum = (1LL * sum * dig[k][1] % mod + dig[k][0]) % mod; pw = 1LL * pw * dig[k][1] % mod; } dig[d][0] = sum; dig[d][1] = pw; } int len = s.length(); int ans = 0; for (int i = 0; i < len; i++) { int d = s[i] - 0 ; ans = (1LL * ans * dig[d][1] % mod + dig[d][0]) % mod; } printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_TB_V
`define SKY130_FD_SC_HS__MUX2_TB_V
/**
* mux2: 2-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A0 = 1'b1;
#140 A1 = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A0 = 1'b0;
#240 A1 = 1'b0;
#260 S = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 S = 1'b1;
#380 A1 = 1'b1;
#400 A0 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 S = 1'bx;
#480 A1 = 1'bx;
#500 A0 = 1'bx;
end
sky130_fd_sc_hs__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_TB_V
|
#include <bits/stdc++.h> using namespace std; int N; int K[1010]; pair<int, int> nex[1010][2520]; int P, Q; int num[1010][2520]; int vis[1010][2520]; class SCC { public: static const int MV = 1010 * 2520; vector<vector<int> > SC; int NV, GR[MV]; private: vector<int> E[MV], RE[MV], NUM; int vis[MV]; public: void init(int NV) { this->NV = NV; for (int i = 0; i < MV; i++) { E[i].clear(); RE[i].clear(); } } void add_edge(int x, int y) { E[x].push_back(y); RE[y].push_back(x); } void dfs(int cu) { vis[cu] = 1; for (int i = 0; i < E[cu].size(); i++) if (!vis[E[cu][i]]) dfs(E[cu][i]); NUM.push_back(cu); } void revdfs(int cu, int ind) { int i; vis[cu] = 1; GR[cu] = ind; SC[ind].push_back(cu); for (i = 0; i < (RE[cu].size()); i++) if (!vis[RE[cu][i]]) revdfs(RE[cu][i], ind); } void scc() { int c = 0; SC.clear(); SC.resize(MV); NUM.clear(); memset(vis, 0, sizeof(vis)); for (int i = 0; i < NV; i++) if (!vis[i]) dfs(i); memset(vis, 0, sizeof(vis)); for (int i = NUM.size() - 1; i >= 0; i--) if (!vis[NUM[i]]) { SC[c].clear(); revdfs(NUM[i], c); sort(SC[c].begin(), SC[c].end()); c++; } SC.resize(c); } }; int dfs(int v, int val, vector<int>& V) { if (vis[v][val] == 2) { set<int> S; int i; for (i = V.size() - 1; i >= 0; i--) { S.insert(V[i] / 2520); if (V[i] == v * 2520 + val) break; } num[v][val] = S.size(); } else if (vis[v][val] == 0) { vis[v][val] = 2; V.push_back(v * 2520 + val); num[v][val] = dfs(nex[v][val].first, nex[v][val].second, V); V.pop_back(); } vis[v][val] = 1; return num[v][val]; } void solve() { int i, j, k, l, r, x, y; string s; cin >> N; for (i = 0; i < (N); i++) { cin >> K[i]; K[i] = (K[i] % 2520 + 2520) % 2520; } for (i = 0; i < (N); i++) { vector<int> E; cin >> x; E.resize(x); for (j = 0; j < (x); j++) cin >> E[j]; for (j = 0; j < (2520); j++) { nex[i][j].first = E[(j + K[i]) % x] - 1; nex[i][j].second = (j + K[i]) % 2520; } } for (i = 0; i < (N); i++) for (j = 0; j < (2520); j++) if (vis[i][j] == 0) { vector<int> V; dfs(i, j, V); } cin >> Q; while (Q--) { cin >> x >> y; x--; y = (y % 2520 + 2520) % 2520; cout << num[x][y] << endl; } } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false), cin.tie(0); for (i = 0; i < (argc - 1); i++) s += argv[i + 1], s += n ; for (i = 0; i < (s.size()); i++) ungetc(s[s.size() - 1 - i], stdin); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin.tie(0), cout.tie(0); ; long long int a, b, t, n, m, k, i, j, l, sum = 0, sum1 = 0, ans = 0; vector<long long int> v; cin >> n; for (i = 0; i < n; i++) { cin >> a; v.push_back(a); if (i & 1) { sum1 += a; } else sum += a; } ans = max(sum1, sum); for (i = 0; i < n; i++) { if (i & 1) { sum1 -= v[i]; sum += v[i]; } else { sum -= v[i]; sum1 += v[i]; } ans = max(ans, max(sum, sum1)); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3F3F3F3F; const long long INF_LL = 0x3F3F3F3F3F3F3F3FLL; const int N = 4e5 + 50; bool check(const string &s, const string &t) { int match = 0; for (int i = 0; i < s.size() && match < t.size(); ++i) { if (s[i] == t[match]) ++match; } return match == t.size(); } int main() { string s, t; cin >> s >> t; int ans = 0; for (int i = 0; i < int(s.size()); ++i) { for (int j = i; j < int(s.size()); ++j) { string tmp = s; tmp.erase(tmp.begin() + i, tmp.begin() + j + 1); if (check(tmp, t)) ans = max(ans, j - i + 1); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> class big_integer { public: big_integer(int32_t v) { if (v >= base) { data_.push_back(v % base); data_.push_back(v / base); } else { data_.push_back(v); } } void inc() { int32_t carry = 1; size_t ptr = 0; while (carry != 0 && ptr < data_.size()) { data_[ptr] += 1; if (data_[ptr] == base) { data_[ptr] -= base; } else { carry = 0; } ptr += 1; } if (carry != 0) { data_.push_back(carry); } } void mult2() { int32_t carry = 0; for (size_t i = 0; i < data_.size(); ++i) { data_[i] = data_[i] * 2 + carry; if (data_[i] >= base) { data_[i] -= base; carry = 1; } else { carry = 0; } } if (carry != 0) { data_.push_back(carry); } } void print(std::ostream& os) const { os << data_.back(); for (size_t i = data_.size() - 2; i < data_.size(); --i) { os << std::setw(9) << std::setfill( 0 ) << data_[i]; } } private: std::vector<int32_t> data_; static const int32_t base = 1000000000; big_integer() {} }; struct operation { std::string op; int32_t x; }; std::istream& operator>>(std::istream& is, operation& o) { return is >> o.op >> o.x; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); size_t n; std::cin >> n; std::vector<operation> ops(n); std::vector<size_t> poss(2001, n); for (size_t i = 0; i < n; ++i) { std::cin >> ops[i]; if (ops[i].op == sell ) { poss[ops[i].x] = i; } } std::vector<int32_t> used(n); big_integer result(0); for (int32_t i = 2000; i >= 0; --i) { result.mult2(); if (poss[i] == n) { continue; } size_t pos = poss[i]; while (pos < n) { if (used[pos] || (ops[pos].op == win && ops[pos].x == i)) { break; } pos -= 1; } if (pos < n && !used[pos]) { for (size_t j = pos; j <= poss[i]; ++j) { used[j] = 1; } result.inc(); } } result.print(std::cout); std::cout << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_BEHAVIORAL_V
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 4-4-2019
*/
// VGM player for DE10-Nano board (MiSTer)
// This does not use the mister framework, only the board.
module vgm12(
);
wire signed [15:0] snd_right, snd_left;
wire [1:0] fm_addr;
wire [7:0] fm_din;
jt10 u_jt10(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
.cen ( fm_cen ), // optional clock enable, if not needed leave as 1'b1
.din ( fm_din ),
.addr ( fm_addr ),
.cs_n ( 1'b0 ),
input wr_n,
output [7:0] dout,
output irq_n,
// ADPCM pins
output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
output [3:0] adpcma_bank,
output adpcma_roe_n, // ADPCM-A ROM output enable
input [7:0] adpcma_data, // Data from RAM
output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
output adpcmb_roe_n, // ADPCM-B ROM output enable
// Separated output: unused
.psg_A ( ),
.psg_B ( ),
.psg_C ( ),
.fm_snd ( ),
// combined output
.snd_right ( snd_right ),
.snd_left ( snd_left ),
.snd_sample ( )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[1001]; int main() { int n; scanf( %d , &n); int m = n; int pos = 0; int k = 1; while (true) { if (a[pos] == 0) m--; if (m == 0) { printf( YES n ); return 0; } a[pos] = 1; if (pos == (pos + k) % n) { printf( NO n ); return 0; } pos = (pos + k) % n; k++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[300]; int main() { cin >> n; for (int i = 0; i < 2 * n; i++) { cin >> a[i]; } sort(a, a + 2 * n); if (a[n - 1] != a[n]) cout << YES << endl; else cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 112345; vector<int> v[N]; int read() { int x; scanf( %d , &x); return x; } int cnt[N]; bool used[N]; bool t[N]; bool never[N]; int main() { int n, m, i, j, x, y; n = read(); for (i = 2; i <= n; i++) { x = read(); y = read(); v[x].push_back(y); cnt[x]++; cnt[y]++; v[y].push_back(x); } queue<int> q; for (int i = 1; i <= n; i++) { if (cnt[i] == 1) { q.push(i); used[i] = 1; } } while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (!used[to]) { if (cnt[to] <= 2 && !t[x] && !never[to]) { used[to] = 1; q.push(to); } else if (cnt[to] == 3 && !t[x] && !never[to]) { t[to] = 1; } else { never[to] = 1; } cnt[to]--; } } } for (i = 1; i <= n; i++) { if (cnt[i] >= 3) { puts( no ); return 0; } } puts( yes ); }
|
`include "../network_params.h"
module pipeline_tb();
reg clock;
reg reset;
reg [`SCREEN_X_BITWIDTH:0] screen_x;
reg [`SCREEN_Y_BITWIDTH:0] screen_y;
wire [`CAMERA_PIXEL_BITWIDTH:0] pixel;
wire [`RECT_OUT_BITWIDTH:0] rect1;
wire [`RECT_OUT_BITWIDTH:0] rect2;
wire [`RECT_OUT_BITWIDTH:0] rect3;
wire [`RECT_OUT_BITWIDTH:0] rect4;
wire [`RECT_OUT_BITWIDTH:0] rect5;
wire [`RECT_OUT_BITWIDTH:0] rect6;
wire [`RECT_OUT_BITWIDTH:0] rect7;
wire [`RECT_OUT_BITWIDTH:0] rect0;
parameter X_RES_MAX = 600;
parameter Y_RES_MAX = 800;
// DUT
top top_inst(
.clock(clock),
.reset(reset),
.screen_x_pos(screen_x),
.screen_y_pos(screen_y),
.test_pixel(pixel),
.rect1(rect1),
.rect2(rect2),
.rect3(rect3),
.rect4(rect4),
.rect5(rect5),
.rect6(rect6),
.rect7(rect7),
.rect0(rect0)
);
always begin
#5 clock <= ~clock;
end
initial begin
clock = 1'b0;
reset = 1'b1;
//pixel = 9'b001000000; // 0.25
# $stop;
end
assign pixel = screen_x;
always@(posedge clock) begin
if(screen_x < X_RES_MAX) begin
screen_x <= screen_x + 1;
end else begin
screen_x <= 0;
if (screen_y < Y_RES_MAX)
screen_y <= screen_y+1;
else
screen_y <= 0;
end // reset
end // always
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 23:06:45 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_g8_1_0 -prefix
// system_rgb888_to_g8_1_0_ system_rgb888_to_g8_1_0_stub.v
// Design : system_rgb888_to_g8_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_1_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_pulse (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } int main() { int t, n, x; cin >> n; vector<pair<int, int>> arr; vector<int> arr2(n + 2, 0); set<int, greater<int>> st; for (int i = 1; i <= n; ++i) { cin >> x; arr2[x] = 1; arr.push_back(make_pair(i, x)); } for (int i = 1; i < arr2.size() - 1; ++i) { if (arr2[i] == 0) { st.insert(i); } } sort(arr.begin(), arr.end(), sortbysec); for (int i = 0; i < arr.size(); ++i) { for (auto j = st.begin(); j != st.end(); ++j) { if (*j == arr[i].first) { if (i == 0) swap(arr[i].first, arr[i + 1].first); else swap(arr[i].first, arr[i - 1].first); } arr[i].second = *j; st.erase(j); break; } } sort(arr.begin(), arr.end()); for (int i = 0; i < arr.size(); ++i) { cout << arr[i].second << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; k = min(k, 26); string s = ab ; for (int i = 0; i < k - 2; i++) { s += char(99 + i); } string s1 = ; for (int i = 0; i < n / k; i++) { s1 += s; } for (int i = 0; i < n % k; i++) { s1 = s1 + s[i]; } cout << s1 << endl; return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
`include "sia.vh"
// The sia_wb core provides a Wishbone B.4 pipelined compatible slave
// port to allow bus masters to talk to the SIA's receiver and transmitter.
// Additional status bits are exposed beyond those defined by Wishbone,
// providing support for things like interrupts, DMA transfer requests, etc.
//
// This Wishbone interface defines a 16-bit serial controller.
// See sia_wb.v for register definitions.
module sia_wb_tb();
reg clk_i, reset_i;
reg [11:0] story_to;
reg fault_to;
reg [3:1] wbs_adr_i;
reg wbs_we_i, wbs_cyc_i, wbs_stb_i;
reg [15:0] wbs_dat_i;
reg [1:0] wbs_sel_i;
wire [15:0] wbs_dat_o;
wire wbs_ack_o, wbs_stall_o;
wire [4:0] bits_o;
wire eedc_o;
wire eedd_o;
wire [2:0] txcmod_o;
wire rxcpol_o;
wire [4:0] intena_o;
wire [19:0] bitrat_o;
wire rxq_pop_o;
wire rxq_oe_o;
reg [15:0] rxq_dat_i;
reg rxq_full_i;
reg rxq_not_empty_i;
wire txq_we_o;
wire [15:0] txq_dat_o;
reg txq_not_full_i;
reg txq_empty_i;
reg txq_idle_i;
always begin
#5; clk_i <= ~clk_i;
end
sia_wb wbs(
.clk_i(clk_i),
.reset_i(reset_i),
.adr_i(wbs_adr_i),
.we_i(wbs_we_i),
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i),
.dat_i(wbs_dat_i),
.sel_i(wbs_sel_i),
.dat_o(wbs_dat_o),
.ack_o(wbs_ack_o),
.stall_o(wbs_stall_o),
.bits_o(bits_o),
.eedc_o(eedc_o),
.eedd_o(eedd_o),
.txcmod_o(txcmod_o),
.rxcpol_o(rxcpol_o),
.intena_o(intena_o),
.bitrat_o(bitrat_o),
.rxq_pop_o(rxq_pop_o),
.rxq_oe_o(rxq_oe_o),
.rxq_dat_i(rxq_dat_i),
.rxq_full_i(rxq_full_i),
.rxq_not_empty_i(rxq_not_empty_i),
.txq_we_o(txq_we_o),
.txq_dat_o(txq_dat_o),
.txq_not_full_i(txq_not_full_i),
.txq_empty_i(txq_empty_i),
.txq_idle_i(txq_idle_i)
);
`STANDARD_FAULT
`DEFASSERT(bits, 4, o)
`DEFASSERT(txcmod, 2, o)
`DEFASSERT(intena, 4, o)
`DEFASSERT(bitrat, 19, o)
`DEFASSERT(txq_dat, 15, o)
`DEFASSERT0(eedc, o)
`DEFASSERT0(eedd, o)
`DEFASSERT0(rxcpol, o)
`DEFASSERT0(rxq_oe, o)
`DEFASSERT0(rxq_pop, o)
`DEFASSERT0(txq_we, o)
`DEFASSERT(wbs_dat, 15, o)
`DEFASSERT0(wbs_ack, o)
`DEFASSERT0(wbs_stall, o)
initial begin
$dumpfile("sia_wb.vcd");
$dumpvars;
{txq_idle_i, wbs_adr_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_dat_i, clk_i, reset_i, fault_to, rxq_dat_i, rxq_full_i, rxq_not_empty_i, txq_not_full_i, txq_empty_i} <= 0;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_wbs_dat(0);
assert_wbs_ack(0);
assert_wbs_stall(0);
assert_bits(10); // 8N1 framing
assert_txcmod(3'b100);
assert_intena(0);
assert_bitrat(83332);
assert_eedc(1);
assert_eedd(1);
assert_rxcpol(0);
// Alter core configuration
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_CONFIG;
wbs_we_i <= 1;
wbs_dat_i <= 16'b00_1_111_11_000_01111;
wbs_sel_i <= 2'b11;
wait(~clk_i); wait(clk_i); #1;
wbs_stb_i <= 0;
wbs_we_i <= 0;
wbs_sel_i <= 0;
assert_wbs_ack(1);
wait(~clk_i); wait(clk_i); #1;
assert_wbs_ack(0);
assert_bits(15);
assert_txcmod(3'b111);
assert_intena(0);
assert_bitrat(83332);
assert_eedc(1);
assert_eedd(1);
assert_rxcpol(1);
wbs_cyc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
// Read back our configuration
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_we_i <= 0;
wbs_adr_i <= `SIA_ADR_CONFIG;
wbs_sel_i <= 2'b11;
wait(~clk_i); wait(clk_i); #1;
wbs_stb_i <= 0;
assert_wbs_ack(1);
assert_wbs_dat(16'h3F0F);
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
// Check core status
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_STATUS;
wbs_we_i <= 0;
wbs_sel_i <= 2'b11;
wait(~clk_i); wait(clk_i); #1;
rxq_not_empty_i <= 1;
txq_empty_i <= 1;
#1; assert_wbs_dat(16'h0000);
assert_wbs_ack(1);
wait(~clk_i); wait(clk_i); #1;
assert_wbs_dat(16'h8005);
assert_wbs_ack(1);
wbs_stb_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
// Alter and verify interrupt enable bits
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_INTENA;
wbs_we_i <= 1;
wbs_sel_i <= 2'b01;
wbs_dat_i <= 16'h000F;
wait(~clk_i); wait(clk_i); #1;
wbs_stb_i <= 0;
wbs_adr_i <= 0;
wbs_we_i <= 0;
wbs_sel_i <= 0;
wbs_dat_i <= 0;
assert_wbs_ack(1);
assert_intena(15);
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_INTENA;
wbs_we_i <= 0;
wbs_sel_i <= 2'b01;
wait(~clk_i); wait(clk_i); #1;
wbs_stb_i <= 0;
wbs_adr_i <= 0;
wbs_sel_i <= 0;
assert_wbs_ack(1);
assert_intena(15);
assert_wbs_dat(15);
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
// Attempt to read from the receive queue.
rxq_dat_i <= 16'hABCD;
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_TRXDAT;
wbs_we_i <= 0;
wbs_sel_i <= 2'b11;
wait(~clk_i); wait(clk_i); #1;
assert_wbs_ack(1);
assert_rxq_oe(1);
assert_rxq_pop(1);
assert_wbs_dat(16'hABCD);
wbs_stb_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
// Attempt to write to transmit queue, 8 bits at a time.
wbs_cyc_i <= 1;
wbs_stb_i <= 1;
wbs_adr_i <= `SIA_ADR_TRXDAT;
wbs_we_i <= 1;
wbs_sel_i <= 2'b01;
wbs_dat_i <= 16'hBEEF;
wait(~clk_i); wait(clk_i); #1;
assert_wbs_ack(1);
wbs_sel_i <= 2'b10;
wait(~clk_i); wait(clk_i); #1;
assert_wbs_ack(1);
assert_txq_we(1);
assert_txq_dat(16'hBEEF);
wbs_stb_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wbs_cyc_i <= 0;
#100;
$display("@I Done.");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp1[101010] = {0}, dp2[101010] = {0}; int main() { cin.sync_with_stdio(0); cin.tie(0); int n; cin >> n; int h[101010]; for (int i = 0; i < n; i++) cin >> h[i]; dp1[0] = 1; for (int i = 1; i < n - 1; i++) { dp1[i] = dp1[i - 1] + 1; dp1[i] = min(h[i], dp1[i]); if (h[i] > h[i - 1]) { dp1[i] = min(dp1[i], h[i - 1] + 1); } if (h[i] > h[i + 1]) { dp1[i] = min(dp1[i], h[i + 1] + 1); } } dp2[n - 1] = 1; for (int i = n - 2; i >= 1; i--) { dp2[i] = dp2[i + 1] + 1; dp2[i] = min(h[i], dp2[i]); if (h[i] > h[i - 1]) { dp2[i] = min(dp2[i], h[i - 1] + 1); } if (h[i] > h[i + 1]) { dp2[i] = min(dp2[i], h[i + 1] + 1); } } int ma = 1; for (int i = 0; i < n; i++) { ma = max(ma, min(dp1[i], dp2[i])); } cout << ma << endl; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2016-2020 NUDT, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//Vendor: NUDT
//Version: 0.1
//Filename: UM.v
//Target Device: Altera
//Dscription:
// 1)user difine module
// 2)a sdn network demo
// pkt type:
// pkt_site 2bit : 2'b01 pkt head / 2'b11 pkt body / 2'b10 pkt tail
// invalid 4bit : the invalid byte sum of every payload cycle
// payload 128bit : pkt payload
//
// rule type:
// ctrl 24bit : [31:29]:forwarding direction
// 0 discard
// 1 trans to CPU with thread id assignd by user /
// 2 trans to CPU with polling thread id /
// 3 trans to port
// port_id 8bit : outport id or thread id
//
//
//Author :
//Revision List:
// rn1: date: modifier: description:
// rn2: date: modifier: description:
//
module UM(
input clk,
input rst_n,
input [5:0] sys_max_cpuid,
//cdp
input cdp2um_data_wr,
input [133:0] cdp2um_data,
input cdp2um_valid_wr,
input cdp2um_valid,
output um2cdp_alf,
output um2cdp_data_wr,
output [133:0] um2cdp_data,
output um2cdp_valid_wr,
output um2cdp_valid,
input cdp2um_alf,
//npe
input npe2um_data_wr,
input [133:0] npe2um_data,
input npe2um_valid_wr,
input npe2um_valid,
output um2npe_alf,
output um2npe_data_wr,
output [133:0] um2npe_data,
output um2npe_valid_wr,
output um2npe_valid,
input npe2um_alf,
//localbus
input localbus_cs_n,
input localbus_rd_wr,
input [31:0] localbus_data,
input localbus_ale,
output localbus_ack_n,
output [31:0] localbus_data_out
);
wire slave2lookup_cs_n;
wire slave2lookup_rd_wr;
wire [31:0] slave2lookup_data;
wire slave2lookup_ale;
wire lookup2slave_ack_n;
wire [31:0] lookup2slave_data_out;
//to rule mgmt
wire slave2rule_cs;//high active
wire rule2slave_ack;//high active ;handshake with slave2rule_cs
wire slave2rule_rw;//0:read 1:write
wire [15:0] slave2rule_addr;
wire [31:0] slave2rule_wdata;
wire [31:0]rule2slave_rdata;
wire parser2lookup_key_wr;
wire [287:0] parser2lookup_key;
wire parser2exe_data_wr;
wire [133:0] parser2exe_data;
wire exe2parser_alf;
wire lookup2rule_index_wr;
wire [5:0] lookup2rule_index;
wire rule2exe_data_wr;//index read return valid
wire [31:0] rule2exe_data;
wire exe2disp_direction_req;
wire exe2disp_direction;//0:up cpu 1: down port
wire exe2disp_data_wr;
wire [133:0] exe2disp_data;
wire exe2disp_valid_wr;
wire exe2disp_valid;
wire disp2exe_alf;
wire disp2usermux_data_wr;
wire [133:0] disp2usermux_data;
wire disp2usermux_valid_wr;
wire disp2usermux_valid;
wire usermux2disp_alf;
user_mgmt_slave user_mgmt_slave(
.clk(clk),
.rst_n(rst_n),
//from localbus master
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),//0 write 1:read
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
//to bv lookup
.cfg2lookup_cs_n(slave2lookup_cs_n),
.cfg2lookup_rd_wr(slave2lookup_rd_wr),
.cfg2lookup_data(slave2lookup_data),
.cfg2lookup_ale(slave2lookup_ale),
.lookup2cfg_ack_n(lookup2slave_ack_n),
.lookup2cfg_data_out(lookup2slave_data_out),
//to rule mgmt
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
parser parser(
.clk(clk),
.rst_n(rst_n),
//input pkt from port
.port2parser_data_wr(cdp2um_data_wr),
.port2parser_data(cdp2um_data),
.port2parser_valid_wr(cdp2um_valid_wr),
.port2parser_valid(cdp2um_valid),
.parser2port_alf(um2cdp_alf),
//parse key which transmit to lookup
.parser2lookup_key_wr(parser2lookup_key_wr),
.parser2lookup_key(parser2lookup_key),
//transport to next module
.parser2next_data_wr(parser2exe_data_wr),
.parser2next_data(parser2exe_data),
.next2parser_alf(exe2parser_alf)
);
lookup BV_Search_engine(
.clk(clk),
.reset(rst_n),//low active
.localbus_cs_n(slave2lookup_cs_n),
.localbus_rd_wr(slave2lookup_rd_wr),//0 write 1:read
.localbus_data(slave2lookup_data),
.localbus_ale(slave2lookup_ale),
.localbus_ack_n(lookup2slave_ack_n),
.localbus_data_out(lookup2slave_data_out),
.metadata_valid(parser2lookup_key_wr),
.metadata(parser2lookup_key),
.countid_valid(lookup2rule_index_wr),
.countid(lookup2rule_index)//6bit width?
);
rule_access rule_access(
.clk(clk),
.rst_n(rst_n),
//lookup rule read index
.lookup2rule_index_wr(lookup2rule_index_wr),
.lookup2rule_index({10'b0,lookup2rule_index}),//16bit width
.rule2lookup_data_wr(rule2exe_data_wr),//index read return valid
.rule2lookup_data(rule2exe_data),
//user cfg require
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
executer executer(
.clk(clk),
.rst_n(rst_n),
.sys_max_cpuid(sys_max_cpuid),
//pkt waiting for rule
.parser2exe_data_wr(parser2exe_data_wr),
.parser2exe_data(parser2exe_data),
.exe2parser_alf(exe2parser_alf),
//rule from lookup engine(BV_search_engine)
.lookup2exe_rule_wr(rule2exe_data_wr),
.lookup2exe_rule(rule2exe_data),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to next module(dispatch)
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf)
);
dispatch dispatch(
.clk(clk),
.rst_n(rst_n),
//execute module's pkt waiting for transmit
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to up cpu
.disp2up_data_wr(um2npe_data_wr),
.disp2up_data(um2npe_data),
.disp2up_valid_wr(um2npe_valid_wr),
.disp2up_valid(um2npe_valid),
.up2disp_alf(npe2um_alf),
//transmit to down port
.disp2down_data_wr(disp2usermux_data_wr),
.disp2down_data(disp2usermux_data),
.disp2down_valid_wr(disp2usermux_valid_wr),
.disp2down_valid(disp2usermux_valid),
.down2disp_alf(usermux2disp_alf)
);
user_mux user_mux(
.clk(clk),
.rst_n(rst_n),
//lookup pkt waiting for transmit
.disp2usermux_data_wr(disp2usermux_data_wr),
.disp2usermux_data(disp2usermux_data),
.disp2usermux_valid_wr(disp2usermux_valid_wr),
.disp2usermux_valid(disp2usermux_valid),
.usermux2disp_alf(usermux2disp_alf),
//up cpu pkt waiting for transmit
.up2usermux_data_wr(npe2um_data_wr),
.up2usermux_data(npe2um_data),
.up2usermux_valid_wr(npe2um_valid_wr),
.up2usermux_valid(npe2um_valid),
.usermux2up_alf(um2npe_alf),
//transmit to down port
.usermux2down_data_wr(um2cdp_data_wr),
.usermux2down_data(um2cdp_data),
.usermux2down_valid_wr(um2cdp_valid_wr),
.usermux2down_valid(um2cdp_valid),
.down2usermux_alf(cdp2um_alf)
);
endmodule
/**********************************
Initial Inst
UM UM(
.clk();
.rst_n();
.sys_max_cpuid();
//cdp
.cdp2um_data_wr();
.cdp2um_data();
.cdp2um_valid_wr();
.cdp2um_valid();
.um2cdp_alf();
.um2cdp_data_wr();
.um2cdp_data();
.um2cdp_valid_wr();
.um2cdp_valid();
.cdp2um_alf();
//npe
.npe2um_data_wr();
.npe2um_data();
.npe2um_valid_wr();
.npe2um_valid();
.um2npe_alf();
.um2npe_data_wr();
.um2npe_data();
.um2npe_valid_wr();
.um2npe_valid();
.npe2um_alf();
//localbus
.localbus_cs_n();
.localbus_rd_wr();
.localbus_data();
.localbus_ale();
.localbus_ack_n();
.localbus_data_out()
);
**********************************/
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n), b(n), pa(n), pb(n); for (int i = 0; i < n; ++i) { cin >> a[i]; --a[i]; pa[a[i]] = i; } for (int i = 0; i < n; ++i) { cin >> b[i]; --b[i]; pb[b[i]] = i; } vector<int> ans(n, 999999); vector<vector<int>> evi(n), evo(n); multiset<int> segs; for (int i = 0; i < n; ++i) { int wh = (pb[i] - pa[i] + n) % n; int tol = n - pa[i], tor = pa[i]; evi[wh].push_back(wh); if ((wh + tor) % n < wh) { segs.insert(wh - n); evo[(wh + tor) % n].push_back(wh - n); } else { evo[(wh + tor) % n].push_back(wh); } } for (int i = 0; i < n; ++i) { for (int z : evi[i]) { segs.insert(z); } if (segs.size()) { auto it = segs.end(); --it; int x = *it; ans[i] = min(ans[i], (i - x) % n); } for (int z : evo[i]) { segs.erase(segs.find(z)); } } segs.clear(); evi.assign(n, vector<int>()); evo.assign(n, vector<int>()); for (int i = 0; i < n; ++i) { int wh = (pb[i] - pa[i] + n) % n; int tol = n - pa[i] - 1, tor = pa[i]; evi[wh].push_back(wh); if ((wh - tol + n) % n > wh) { segs.insert(wh + n); evo[(wh - tol + n) % n].push_back(wh + n); } else { evo[(wh - tol + n) % n].push_back(wh); } } for (int i = n - 1; i >= 0; --i) { for (int z : evi[i]) { segs.insert(z); } if (segs.size()) { int x = *segs.begin(); ans[i] = min(ans[i], (x - i) % n); } for (int z : evo[i]) { segs.erase(segs.find(z)); } } for (int i = 0; i < n; ++i) { cout << ans[i] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a == 0) return b; else if (b == 0) return a; else { a = a % b; return gcd(b, a); } } int main() { int n; int sum = 0, odd = 0; scanf( %d , &n); int t; for (int i = 0; i < n; i++) { scanf( %d , &t); sum += t; if (t % 2) odd++; } if (sum % 2) cout << odd; else cout << n - odd; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; struct node { int a; int b; int sum; }; int n, q; int nblock; node nums[300315]; int acum = 0; int fib[300315]; long long auxi; void add(int &a, int b) { a += b; if (a > 1000000009) a -= 1000000009; } inline int calcf(int x) { if (x <= 1 || fib[x] != 0) return fib[x]; fib[x] = 0; add(fib[x], calcf(x - 2)); add(fib[x], calcf(x - 1)); return fib[x]; } inline int sumfibo(int a, int b, int posx, int posy) { int x = 0; auxi = (1LL * calcf(posx - 1) * a) % (1LL * 1000000009); add(x, int(auxi)); auxi = (1LL * calcf(posx) * b) % (1LL * 1000000009); add(x, int(auxi)); int y = 0; auxi = (1LL * calcf(posy) * a) % (1LL * 1000000009); add(y, int(auxi)); auxi = (1LL * calcf(posy + 1) * b) % (1LL * 1000000009); add(y, int(auxi)); add(y, 1000000009 - x); return y; } inline void update(int ini, int fin) { int inc = 1; int acumblock = 0; if ((ini - 1) / nblock == (fin - 1) / nblock) { for (int i = 0; i < nblock; i++) { int j = i + ini; if (j <= fin) { add(acumblock, calcf(inc)); inc++; } if (((j - 1) / nblock) == (fin - 1) / nblock) { add(nums[j].sum, acumblock); } } } else { int iniblock; iniblock = ini - ((ini - 1) % nblock); int l = iniblock; if (ini % nblock != 1) { for (int i = ini; i < iniblock + nblock; i++) { add(acumblock, calcf(inc)); inc++; add(nums[i].sum, acumblock); } l = iniblock + nblock; } while (l + nblock <= fin + 1) { add(nums[l].a, calcf(inc)); add(nums[l].b, calcf(inc + 1)); inc += nblock; l += nblock; } acumblock = 0; for (int i = 0; i < nblock; i++) { int j = i + l; if (j <= fin) { add(acumblock, calcf(inc)); inc++; } if (((j - 1) / nblock) == (fin - 1) / nblock) add(nums[j].sum, acumblock); } } } inline int get(int ini, int fin) { int iniblock; int ans = 0; if ((ini - 1) / nblock == (fin - 1) / nblock) { iniblock = ini - ((ini - 1) % nblock); if (ini % nblock) { if (fin % nblock) add(ans, sumfibo(nums[iniblock].a, nums[iniblock].b, ini % nblock, fin % nblock)); else add(ans, sumfibo(nums[iniblock].a, nums[iniblock].b, ini % nblock, nblock)); } else add(ans, sumfibo(nums[iniblock].a, nums[iniblock].b, nblock, nblock)); add(ans, nums[fin].sum); if (ini % nblock != 1) { add(ans, 1000000009 - nums[ini - 1].sum); } return ans; } else { iniblock = ini - ((ini - 1) % nblock); if (ini % nblock) add(ans, sumfibo(nums[iniblock].a, nums[iniblock].b, ini % nblock, nblock)); else add(ans, sumfibo(nums[iniblock].a, nums[iniblock].b, nblock, nblock)); add(ans, nums[iniblock + nblock - 1].sum); if (ini % nblock != 1) { add(ans, 1000000009 - nums[ini - 1].sum); } int l = iniblock + nblock; while (l + nblock <= fin + 1) { add(ans, sumfibo(nums[l].a, nums[l].b, 1, nblock)); add(ans, nums[l + nblock - 1].sum); l += nblock; } if (l <= fin) { add(ans, nums[fin].sum); add(ans, sumfibo(nums[l].a, nums[l].b, 1, fin % nblock)); } return ans; } } int main() { fib[0] = 0; fib[1] = 1; fib[2] = 1; scanf( %d %d , &n, &q); nblock = int(sqrt(n * 1.0)); if (nblock * nblock != n) nblock++; for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); add(acum, x); nums[i].sum = acum; if (i % nblock == 0) acum = 0; } for (int i = 0; i < q; i++) { int x, y, z; scanf( %d %d %d , &x, &y, &z); if (x == 1) { update(y, z); } else if (x == 2) { printf( %d n , get(y, z)); } } return 0; }
|
// Filename: receive.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module that receives a 10-bit bus which is fed into a register.
// This data is also fed into a 9-bit parity generator. The ODD ouput
// is compared to the 10th data bit which is an even parity bit.
module receive(clk, data_in, data_out, data_valid);
input clk; // Clock to be generated in test bench with clk module
input[9:0] data_in; // Data coming from transmit, into reg and parity gen
output[8:0] data_out; // 9-bit bus coming out of reg
output data_valid; // Output of comparator
wire[8:0] data_out;
wire data_valid;
wire odd_in; // Even parity bit going to comparator
wire odd, even; // Outputs of parity generator
// 10-bit register
// Input from transmit module, output goes to output, parity gen, and comparator
register_10bit U4(clk, data_in, {odd_in, data_out});
// 9-bit parity generator
// Input from data_out, output to comparator
hc280 U5(data_out, even, odd);
// Parity bit comparator (XNOR gate). Since the hc280 outputs high on odd when
// there is an odd number of 1s in its input, this odd output is used as an even
// parity bit (odd number of 1s plus another 1 = even number of ones). So XNOR is
// used to check if there is either an odd number of ones and a high even parity
// bit or an even number of ones and a low even parity bit.
xnor U6(data_valid, odd, odd_in);
endmodule
|
//#############################################################################
//# Function: Clock domain crossing FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_cdc # (parameter DW = 104, //FIFO width
parameter DEPTH = 32, //FIFO depth (entries)
parameter TARGET = "GENERIC" //XILINX,ALTERA,GENERIC
)
(
input nreset, // shared domain async active low reset
input clk_in, // write clock
input access_in, // write access
input [DW-1:0] packet_in, // write packet
output wait_out, // write pushback
input clk_out, //read clock
output reg access_out, //read access
output [DW-1:0] packet_out, //read packet
input wait_in, // read pushback
output prog_full, // fifo is half full
output full, // fifo is full
output empty // fifo is empty
);
wire wr_en;
wire rd_en;
// FIFO control logic
assign wr_en = access_in;
assign rd_en = ~empty & ~wait_in;
assign wait_out = prog_full; //wait_out should stall access_in signal
//Holds access high while waiting
always @ (posedge clk_out or negedge nreset)
if(!nreset)
access_out <= 1'b0;
else if(~wait_in)
access_out <= rd_en;
//Read response fifo (from master)
oh_fifo_async #(.TARGET(TARGET),
.DW(DW),
.DEPTH(DEPTH))
fifo (.prog_full (prog_full),
.full (full),
.rd_count (),
.nreset (nreset),
.dout (packet_out[DW-1:0]),
.empty (empty),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en));
endmodule // oh_fifo_cdc
|
#include <bits/stdc++.h> using namespace std; const int N = 61; const int K = 22222; const int M = K + K + 5; int n, m; int a[N], b[N]; long long m1[M], m2[M]; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < m; i++) scanf( %d , &b[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { m1[a[i] + b[j] + K] |= 1LL << i; m2[a[i] + b[j] + K] |= 1LL << j; } } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int p = 0; p < n; p++) { for (int q = 0; q < m; q++) { int x = a[i] + b[j] + K; int y = a[p] + b[q] + K; int res1 = __builtin_popcountll(m1[x]) + __builtin_popcountll(m1[y]) - __builtin_popcountll(m1[x] & m1[y]); int res2 = __builtin_popcountll(m2[x]) + __builtin_popcountll(m2[y]) - __builtin_popcountll(m2[x] & m2[y]); ans = max(ans, res1 + res2); } } } } printf( %d n , ans); return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@brief Reports a fixed 32-bit identifier in the USER1 register.
We could use USERCODE for this, but that would prevent it from being used by an end-user design.
*/
module JtagUserIdentifier #(
parameter IDCODE_VID = 24'h000000,
parameter IDCODE_PID = 8'h00
)();
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The TAP interface for discovery (DEBUG_IDCODE register)
reg[31:0] tap_shreg = 0;
wire tap_active;
wire tap_shift;
wire tap_clear;
wire tap_tck_raw;
wire tap_tck_bufh;
//The TAP itself
JtagTAP #(
.USER_INSTRUCTION(1)
) tap_tap (
.instruction_active(tap_active),
.state_capture_dr(tap_clear),
.state_reset(),
.state_runtest(),
.state_shift_dr(tap_shift),
.state_update_dr(),
.tck(tap_tck_raw),
.tck_gated(),
.tms(),
.tdi(),
.tdo(tap_shreg[0])
);
//Buffer the clock b/c ISE is derpy and often won't instantiate a buffer (woo skew!)
//TODO: according to comments in older code BUFHs here sometimes won't work in spartan6?
ClockBuffer #(
.TYPE("LOCAL"),
.CE("NO")
) tap_tck_clkbuf (
.clkin(tap_tck_raw),
.clkout(tap_tck_bufh),
.ce(1'b1)
);
//The actual shift register
always @(posedge tap_tck_bufh) begin
if(!tap_active) begin
end
else if(tap_clear)
tap_shreg <= {IDCODE_VID, IDCODE_PID};
else if(tap_shift)
tap_shreg <= {1'b1, tap_shreg[31:1]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int maxn = 2e5 + 10; int a[maxn]; char s[maxn]; const char *t = LR ; int main() { int n; cin >> n; for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); scanf( %s , s); bool rev = s[0] == R ; int cnt = 0; for (int i = 1; i < n; i++) { cnt += s[i] == s[i - 1]; } printf( %d %c n , a[cnt], t[rev]); int l = cnt, r = cnt; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) l--, printf( %d %c n , a[l], t[((cnt - l) & 1) ^ rev]); else r++, printf( %d %c n , a[r], t[((r - cnt) & 1) ^ rev]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o311a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, m, a, b, x, cnt, ans; deque<long long> V; map<long long, long long> mp; long long arr[1000001]; int main() { cin >> n >> a >> b; for (int i = 1; i <= n; i++) { cin >> arr[i]; } sort(arr + 1, arr + n + 1); ans = (n - a) + 1; x = arr[ans] - arr[b]; cout << x << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 30; int n, k; long long s, ans, a[maxn], fac[maxn]; map<long long, long long> mp[maxn]; void dfs1(int x, int usd, long long now) { if (x == n / 2 + 1) { if (mp[usd].find(now) == mp[usd].end()) mp[usd].insert(make_pair(now, 1)); else mp[usd][now]++; return; } dfs1(x + 1, usd, now); if (now + a[x] <= s) dfs1(x + 1, usd, now + a[x]); if (fac[x] && usd < k && fac[x] + now <= s) dfs1(x + 1, usd + 1, fac[x] + now); } void dfs2(int x, int usd, long long now) { if (x == n + 1) { for (register int i = 0; i <= k - usd; i++) if (mp[i].find(s - now) != mp[i].end()) ans += mp[i][s - now]; return; } dfs2(x + 1, usd, now); if (now + a[x] <= s) dfs2(x + 1, usd, now + a[x]); if (fac[x] && usd < k && fac[x] + now <= s) dfs2(x + 1, usd + 1, fac[x] + now); } int main() { int i, j; scanf( %d%d%lld , &n, &k, &s); for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); fac[i] = 1; for (j = 1; j <= a[i]; j++) { fac[i] = 1ll * fac[i] * j; if (fac[i] > s) { fac[i] = 0; break; } } } dfs1(1, 0, 0); dfs2(n / 2 + 1, 0, 0); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int matrix[5][5]; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { cin >> matrix[i][j]; } } int row = 0; int col = 0; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { if (matrix[i][j] == 1) { row = i + 1; col = j + 1; } } } int swaps = 0; swaps += abs(3 - row); swaps += abs(3 - col); cout << swaps; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; long long Power(long long a, long long b) { if (b == 0) return 1; long long p = Power(a, b / 2); p = (p * p); if (b & 1) { p = (p * a); } return p; } long long Gcd(long long a, long long b) { if (b == 0) return a; if (a < b) return Gcd(b, a); return Gcd(b, a % b); } void Solve() { int n, m; long long l; cin >> n >> m >> l; vector<long long> arr(n), seg(n, -1); for (int i = 0; i < n; i++) cin >> arr[i]; int curr = 0, prev = -1; for (int i = 0; i < n; i++) { if (arr[i] > l) { seg[i] = 0; if (prev == -1) { curr++; } prev = 0; } else { prev = -1; seg[i] = -1; } } while (m--) { int t; cin >> t; if (t == 0) { cout << curr << n ; } else { int p; long long d; cin >> p >> d; p--; arr[p] += d; if (seg[p] == -1 && arr[p] > l) { seg[p] = 0; if (p == 0) { if (p + 1 < n && seg[p + 1] == -1) { curr++; } else if (n == 1) { curr++; } } else if (p == n - 1) { if (p - 1 >= 0 && seg[p - 1] == -1) { curr++; } else if (n == 1) { curr++; } } else { if (seg[p - 1] == 0 && seg[p + 1] == 0) { curr--; } else if (seg[p - 1] == -1 && seg[p + 1] == -1) { curr++; } } } } } } int main() { int t = 1; while (t--) { Solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> split, ans; int a[300002]; int p[300002][3]; long long max(long long a, long long b) { return a >= b ? a : b; } long long min(long long a, long long b) { return a <= b ? a : b; } int main() { int n, i, j, l, r; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , a + i); } a[0] = a[n + 1] = 0; long long _0, _1, _2, __0, __1, __2; _0 = a[1], _1 = 0, _2 = -1; for (i = 1; i <= n; i++) { p[i + 1][0] = p[i + 1][1] = p[i + 1][2] = -1; __0 = __1 = __2 = -1; if (~_0) { if (__1 == -1 || _0 < __1) { __1 = _0; p[i + 1][1] = 0; } } if (~_1) { if (__2 == -1 || _1 < __2) { __2 = _1; p[i + 1][2] = 1; } } if (~_2) { if (__0 == -1 || _2 + max(a[i], a[i + 1]) < __0) { __0 = _2 + max(a[i], a[i + 1]); p[i + 1][0] = 2; } if (__1 == -1 || _2 + a[i] < __1) { __1 = _2 + a[i]; p[i + 1][1] = 2; } } _0 = __0, _1 = __1, _2 = __2; } long long u; j = 0, u = __0; if (__1 < u) j = 1, u = __1; if (__2 < u) j = 2, u = __2; split.clear(); for (i = n + 1;; i--) { if (j == 0) { split.push_back(i - 1); } if (i == 1) break; j = p[i][j]; } ans.clear(); int t; for (i = 0; i < split.size(); i++) { j = split[i]; t = min(a[j], a[j + 1]); a[j] -= t, a[j + 1] -= t; if (t) ans.push_back(j); } for (i = split.size() - 1; i >= -1; i--) { l = i == split.size() - 1 ? 0 : split[i + 1] + 1, r = ~i ? split[i] : n + 1; for (j = l; j <= r; j += 2) { if (j >= 1 && min(a[j - 1], a[j])) { t = min(a[j - 1], a[j]); a[j - 1] -= t, a[j] -= t; ans.push_back(j - 1); } if (j <= n && min(a[j], a[j + 1])) { t = min(a[j], a[j + 1]); a[j] -= t, a[j + 1] -= t; ans.push_back(j); } } } printf( %d n , ans.size()); for (i = 0; i < ans.size(); i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; long long a[2]; cin >> a[0] >> a[1]; sort(a, a + 2); n = 2 * a[0]; if (n < a[1]) { n = a[1]; } n *= n; cout << n << endl; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
module dewater_mode_tb();
reg [31:0]clk;
wire [31:0]dewater_count;
wire [1:0]state;
reg start, power, dewater_start;
reg [2:0]weight;
wire dewater_end_sign, water_out_light, dewatering_light;
wire [2:0]water_level;
parameter TIME = 1000;
dewater_mode DEWATER_MODE (.power(power),
.start(start),
.clk(clk),
.weight(weight),
.dewater_start(dewater_start),
.dewatering_light(dewatering_light),
.dewater_end_sign(dewater_end_sign),
.water_out_light(water_out_light),
.water_level(water_level),
.dewater_count(dewater_count),
.state(state)
);
initial begin
power = 0;
clk[25] = 0;
clk[0] = 0;
start = 0;
weight = 5;
dewater_start = 0;
#TIME $finish;
end
always begin
#10 clk[25] = ~clk[25];
end
always begin
#1 clk[0] = ~clk[0];
end
always begin
#10 start = 1;
#20 power = 1;
#20 dewater_start = 1;
// #100 power = 0;
// #40 power = 1;
#950 ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int MAX = -1000000000000000000; const long long int MIN = 1000000000000000000; const long long int inf = 1000000000000000000; const long long int KOK = 100000; const long long int LOG = 30; const long long int li = 105; const long long int mod = 1000000007; long long int n, m, cev, b, a[li], k, dp[105][100005], PS[li][li]; string s; vector<int> v; long long int f(long long int sira, long long int topl) { long long int mn = inf; if (topl <= 0) return 0; if (sira > n) { return inf; } if (~dp[sira][topl]) return dp[sira][topl]; for (int i = sira; i <= n; i++) { mn = min(mn, f(i + 1, topl - PS[sira][i] + PS[sira][sira - 1]) + 1); } return dp[sira][topl] = mn; } int main() { memset(dp, -1, sizeof(dp)); scanf( %lld %lld , &n, &m); for (long long int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } sort(a + 1, a + n + 1); reverse(a + 1, a + n + 1); for (long long int i = 1; i <= n; i++) { long long int at = 0; for (long long int j = i; j <= n; j++) { PS[i][j] = PS[i][j - 1] + max(a[j] - at, 0ll); at++; } } long long int yess = f(1, m); if (yess >= inf) { printf( -1 n ); return 0; } printf( %lld n , yess); return 0; }
|
`timescale 1 ns / 1 ps
module spoonPacketDecoder(
input reset,
input clk,
input [63:0] data,
input push_in,
input ramIn,
output [63:0] value,
output [31:0] column,
output [31:0] row,
output push_out,
output stall);
reg [255:0] buffer;
reg [5:0] count, next_count;
reg [5:0] packetSize;
reg [63:0] r_value;
reg [31:0] r_column, r_row;
reg r_push_out;
reg [4:0] local_row;
reg [2:0] delta_size;
reg [63:0] delta;
integer i, j;
reg [7:0] ramAdr;
wire [63:0] ramDOut;
reg [7:0] ramCount;
reg fetchRam;
reg [63:0] valuePrime;
reg r_push_in;
reg [63:0] r_data;
reg r_ram_in;
always @(posedge clk) begin
r_push_in <= push_in;
r_data <= data;
r_ram_in <= ramIn;
end
bram64x256 bram(
.clk(clk),
.wr(r_ram_in),
.adr(ramAdr),
.din(r_data),
.dout(ramDOut));
always @* begin
if(r_ram_in)
ramAdr = ramCount;
else
ramAdr = buffer[15:8];
if(fetchRam)
valuePrime = ramDOut;
else
valuePrime = r_value;
end
always @(posedge clk)
fetchRam <= (buffer[2:0] < 5);
assign stall = count[4];
reg shift_buffer;
//1,2,3,5,8,10,12,16
always @(posedge clk) begin
if(count[4]) begin
case(buffer[2:0])
0:begin
buffer <= (buffer >> (1 * 8));
next_count = count - 1;
end
1:begin
buffer <= (buffer >> (2 * 8));
next_count = count - 2;
end
2:begin
buffer <= (buffer >> (3 * 8));
next_count = count - 3;
end
3:begin
buffer <= (buffer >> (5 * 8));
next_count = count - 5;
end
4:begin
buffer <= (buffer >> (7 * 8));
next_count = count - 7;
end
5:begin
buffer <= (buffer >> (9 * 8));
next_count = count - 9;
end
6:begin
buffer <= (buffer >> (11 * 8));
next_count = count - 11;
end
7:begin
buffer <= (buffer >> (14 * 8));
next_count = count - 14;
end
endcase
end else
next_count = count;
if(r_push_in) begin
for(i = 0; i < 64; i = i + 1)
buffer[{next_count, 3'H0} + i] <= r_data[i];
count <= next_count + 8;
end else
count <= next_count;
if(reset == 1)
count <= 0;
end
always @(posedge clk) begin
if(reset == 1)begin
r_push_out <= 0;
r_value <= 0;
r_column <= 0;
r_row <= 0;
//1,2,3,5,7,9,11,14
end else begin
//TODO:redo with new method
delta = 0;
delta[4:0] = buffer[7:3];
case(buffer[2:0])
0:begin
end
1:begin
end
2:begin
delta[12:5] = buffer[23:16];
end
3:begin
delta[28:5] = buffer[39:16];
end
4:begin
delta[44:5] = buffer[55:16];
end
5:begin
end
6:begin
delta[20:5] = buffer[87:72];
end
7:begin
delta[36:5] = buffer[103:72];
end
endcase
//TODO:the rest
r_value <= buffer[71:8];
if((buffer[2:0] > 0) && (count[4] == 1)) begin
r_push_out <= 1;
local_row = {1'H0,r_row[3:0]} + {1'H0, delta[3:0]};
r_row[3:0] <= local_row[3:0];
r_column <= r_column + delta[35:4] + local_row[4];
end else if((buffer[2:0] == 0) && (count[4] == 1)) begin
r_column <= 0;
r_row[3:0] <= 0;
r_row[31:4] <= r_row[31:4] + 1;
r_push_out <= 0;
end else
r_push_out <= 0;
end
end
always @(posedge clk) begin
if(reset) begin
ramCount <= 0;
end else begin
if(r_ram_in)
ramCount <= ramCount + 1;
end
end
assign push_out = r_push_out;
assign column = r_column;
assign row = r_row;
assign value = valuePrime;
endmodule
|
#include<bits/stdc++.h> #define fo(i,a,b) for(int i=a;i<=b;i++) #define gc (p1==p2&&(p2=(p1=fr)+fread(fr,1,1<<20,stdin))==p1?EOF:*p1++) #define fl fwrite(fw,1,p3-fw,stdout),p3=fw char ch,fr[1<<21],*p1=fr,*p2=fr,fw[1<<21],*p3=fw; void rd(int&x) { while(!isdigit(ch=gc));x=ch-48; while( isdigit(ch=gc)) x=ch-48+x*10; } void pc(char c) {*p3++=c; if(p3-fw==1<<20)fl;} void pt(int x) {if(x>9)pt(x/10); pc(x%10+48);} using namespace std; typedef pair<int,int>P; const int N=5e5+9; int T,n,m,X[N],Y[N],x,y,n1,c[N],sz[N],deg[N],t,d[N]; set<int>r,e[N],E[N]; struct Comp{bool operator()(const int&x,const int&y){return deg[x]>deg[y];}}; multiset<int,Comp>_; multiset<int,Comp>::iterator it; #define fi first #define se second P a[N],w[N]; void dg(int x) { int y; for(set<int>::iterator it=r.begin();it!=r.end();) if(e[x].find(y=*it)==e[x].end()) { E[x].insert(y); E[y].insert(x); r.erase(it); dg(y); it=r.lower_bound(y); } else it++; } int main() { for(rd(T);T--;) { rd(n),rd(m); _.clear(); fo(i,1,n) e[i].clear(), E[i].clear(), deg[i]=c[i]=sz[i]=0; fo(i,1,m) { rd(x),rd(y); deg[x]++,deg[y]++; X[i]=x,Y[i]=y; e[x].insert(y); e[y].insert(x); } fo(i,1,n) _.insert(i); n1=n; // n1=_.size(); while(!_.empty()) { if(deg[x=*_.begin()]<n1-1) break; _.erase(_.find(x)), n1--; for(int y:e[x]) { _.erase(_.find(y)); e[y].erase(x); deg[y]--; _.insert(y); } } // n1=_.size(); if(!n1) goto DW; r.clear(); r.insert(_.begin(),_.end()); for(int x:_) if(r.find(x)!=r.end()) r.erase(x),dg(x); if(!r.empty()) { puts( cyka blyat! ); printf( %d %d n ,n,m); fo(i,1,m) printf( %d %d n ,X[i],Y[i]); return 0; } for(int x:_) if(!c[x]) { UP:for(int y:E[x]) if(!c[y]) d[++t]=y; if(t) { for(sz[c[x]=x]=t+1;t;t--) c[d[t]]=x; continue; } y=*E[x].begin(); if(sz[c[y]]==2) {c[c[y]]=sz[c[y]]=0; x=y; goto UP;} else --sz[c[y]], sz[c[y]=c[x]=x]=2; } DW:int nw=0; for(int x:_) if(sz[x]) w[x]=a[x]=P(nw+sz[x],nw+1), nw+=sz[x]; for(int x:_) if((y=c[x])^x) w[y]=a[x]=P(w[y].fi-1,w[y].se==a[y].se?a[y].fi:w[y].se-1); // n1=_.size(); fo(i,1,n) if(_.find(i)==_.end()) ++nw,a[i]=P(nw,nw); fo(i,1,n) pt(a[i].fi),pc( ); pc( n ); fo(i,1,n) pt(a[i].se),pc( ); pc( n ); } fl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_V
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for NOW() system function.
module now_test;
logic gen_report;
now_entity dut(gen_report);
initial begin
gen_report = 0;
#5;
gen_report = 1;
#5;
gen_report = 0;
#5;
gen_report = 1;
#5;
gen_report = 0;
#5;
gen_report = 1;
end
endmodule
|
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
parameter N = 1;
parameter PW = 104;
//clock, reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transactoin
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
//tie offs for Dv
assign dut_active = 1'b1;
assign wait_out = 1'b0;
assign clk = clk1;
assign clkout = clk2;
oh_debouncer #(.CLKPERIOD(10))
oh_debouncer (.clean_out (clean_out),
.nreset (nreset),
.clk (clk),
.noisy_in (packet_in[PW-1])
);
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; signed main() { long long t; cin >> t; while (t--) { long long a, b; cin >> a >> b; if (a == b) { if (a == 0) cout << 0 << n ; else cout << 1 << n ; } else if ((a + b) % 2) cout << -1 << n ; else cout << 2 << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 65536 + 10; int n, deg[Maxn], s[Maxn]; vector<pair<int, int> > ans; set<pair<int, int> > mys; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d , °[i], &s[i]); mys.insert(make_pair(deg[i], i)); } while (!mys.empty()) { pair<int, int> p = *mys.begin(); mys.erase(p); if (p.first > 0) { ans.push_back(make_pair(p.second, s[p.second])); mys.erase(make_pair(deg[s[p.second]], s[p.second])); deg[s[p.second]]--; s[s[p.second]] ^= p.second; mys.insert(make_pair(deg[s[p.second]], s[p.second])); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) printf( %d %d n , ans[i].first, ans[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; if (n > 1) sort(a, a + n); int cont = 0; if (k == n) { cout << a[k - 1] << n ; } else if (k == 0) { if (a[0] - 1 >= 1) cout << a[0] - 1 << endl; else puts( -1 ); } else { k--; if (a[k] == a[k + 1]) cout << -1 << endl; else cout << a[k] << endl; } }
|
// This is written by Zhiyang Ong
// and Andrew Mattheisen
// for EE577b Troy WideWord Processor Project
module pipe3(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out,
regwren_in, regwren_out, rwraddrd_in, rwraddrd_out,
reginmuxop_in, reginmuxop_out, aluOut_in, aluOut_out,
instruction_in, instruction_out, clk, reset);
// INPUTS
input [0:127] dataOut_in;
input [0:15] wbyteen_in;
input regwren_in;
input [0:4] rwraddrd_in;
input reginmuxop_in;
input [0:127] aluOut_in;
input [0:31] instruction_in;
input clk, reset;
// OUTPUTS
output [0:127] dataOut_out;
output [0:15] wbyteen_out;
output regwren_out;
output [0:15] rwraddrd_out;
output reginmuxop_out;
output [0:127] aluOut_out;
output [0:31] instruction_out;
//REGISTERS
reg [0:127] dataOut_out;
reg [0:15] wbyteen_out;
reg regwren_out;
reg [0:4] rwraddrd_out;
reg reginmuxop_out;
reg [0:127] aluOut_out;
reg [0:31] instruction_out;
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
dataOut_out<=128'b0;
wbyteen_out<=16'b0;
regwren_out<=1'b0;
rwraddrd_out<=5'b0;
reginmuxop_out<=1'b0;
aluOut_out<=128'b0;
instruction_out<=32'b0;
end
else
begin
dataOut_out<=dataOut_in;
wbyteen_out<=wbyteen_in;
regwren_out<=regwren_in;
rwraddrd_out<=rwraddrd_in;
reginmuxop_out<=reginmuxop_in;
aluOut_out<=aluOut_in;
instruction_out<=instruction_in;
end
end
endmodule
|
//====================================================================
// bsg_idiv_iterative_controller.v
// 11/14/2016,
//====================================================================
//
// The controller of bsg_idiv_iterative module.
// Code refactored based on Sam Larser's work
`include "bsg_defines.v"
module bsg_idiv_iterative_controller #(parameter width_p=32)
(input clk_i
,input reset_i
,input v_i
,output ready_and_o
,input zero_divisor_i
,input signed_div_r_i
,input adder_result_is_neg_i
,input opA_is_neg_i
,input opC_is_neg_i
,output logic opA_sel_o
,output logic opA_ld_o
,output logic opA_inv_o
,output logic opA_clr_l_o
,output logic [2:0] opB_sel_o
,output logic opB_ld_o
,output logic opB_inv_o
,output logic opB_clr_l_o
,output logic [2:0] opC_sel_o
,output logic opC_ld_o
,output logic latch_signed_div_o
,output logic adder_cin_o
,output logic v_o
,input yumi_i
);
reg q_neg;
reg r_neg;
reg neg_ld;
reg add_neg_last;
typedef enum logic[5:0]
{WAIT, NEG0, NEG1, SHIFT,
CALC,
REPAIR, REMAIN,
QUOT,DONE } idiv_ctrl_stat;
idiv_ctrl_stat state, next_state;
always @(posedge clk_i) begin
add_neg_last <= adder_result_is_neg_i;
if (neg_ld) begin
// the quotient is negated if the signs of the operands differ
q_neg <= (opA_is_neg_i ^ opC_is_neg_i) & signed_div_r_i;
// the remainder is negated if the dividend is negative
r_neg <= opC_is_neg_i & signed_div_r_i;
end
end
logic [`BSG_SAFE_CLOG2(width_p+1)-1:0] calc_cnt;
wire calc_up_li = (state == CALC) && (calc_cnt < width_p);
wire calc_done = (calc_cnt == width_p);
bsg_counter_clear_up#(.max_val_p(width_p)
,.init_val_p(0)
,.disable_overflow_warning_p(1)) calc_counter
(.clk_i(clk_i)
,.reset_i(reset_i)
// We rely on natural overflow
,.clear_i(calc_done)
,.up_i(calc_up_li)
,.count_o(calc_cnt)
);
// synopsys sync_set_reset "reset_i"
always @(posedge clk_i) begin
if (reset_i) state <= WAIT;
else state <= next_state;
end
always_comb begin
opA_sel_o = 1'b0;
opA_ld_o = 1'b0;
opA_inv_o = !add_neg_last;
opA_clr_l_o = 1'b1;
opB_sel_o = 3'b001;
opB_ld_o = 1'b1;
opB_inv_o = 1'b0;
opB_clr_l_o = 1'b1;
opC_sel_o = 3'b001;
opC_ld_o = 1'b1;
adder_cin_o = !add_neg_last;
neg_ld = 1'b0;
latch_signed_div_o = 1'b0;
next_state = WAIT;
case (state)
WAIT: begin
if (v_i) begin
opA_ld_o = 1'b1;
opC_ld_o = 1'b1;
latch_signed_div_o = 1'b1;
next_state = NEG0;
end
opA_sel_o = 1'b1;
opC_sel_o = 3'b100;
end
NEG0: begin
next_state = (opC_is_neg_i & signed_div_r_i) ? NEG1 : SHIFT;
opA_inv_o = 1'b1;
opB_clr_l_o = 1'b0;
opB_sel_o = 3'b100;
opC_ld_o = 1'b0;
neg_ld = 1'b1;
adder_cin_o = 1'b1;
opA_ld_o = opA_is_neg_i & signed_div_r_i;
end
NEG1: begin
next_state = SHIFT;
opA_clr_l_o = 1'b0;
opB_inv_o = 1'b1;
opB_ld_o = 1'b0;
opC_sel_o = 3'b010;
adder_cin_o = 1'b1;
end
SHIFT: begin
next_state = CALC;
opA_clr_l_o = 1'b0;
opB_clr_l_o = 1'b0;
adder_cin_o = 1'b0;
end
CALC: begin
opB_sel_o = calc_done ? 3'b010 : 3'b001;
if (calc_done) begin
if (adder_result_is_neg_i) next_state = REPAIR;
else next_state = REMAIN;
end else
next_state = CALC;
end
REPAIR: begin
next_state = REMAIN;
opA_inv_o = 1'b0;
opB_sel_o = 3'b010;
opC_ld_o = 1'b0;
adder_cin_o = 1'b0;
end
REMAIN: begin
next_state = (zero_divisor_i | !q_neg) ? DONE: QUOT;
opA_ld_o = 1'b1;
opA_clr_l_o = 1'b0;
opB_sel_o = 3'b100;
opC_ld_o = 1'b0;
opB_inv_o = r_neg;
adder_cin_o = r_neg;
end
QUOT: begin
next_state = DONE;
opA_clr_l_o = 1'b0;
opB_inv_o = 1'b1;
opB_ld_o = 1'b0;
opC_sel_o = 3'b010;
adder_cin_o = 1'b1;
end
DONE:begin
if( yumi_i ) next_state = WAIT;
else next_state = DONE;
opA_ld_o = 1'b0;
opB_ld_o = 1'b0;
opC_ld_o = 1'b0;
end
endcase
end
assign ready_and_o = ( state == WAIT );
assign v_o = ( state == DONE );
endmodule // divide_control
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 7; const int INF = 0x7fffffff; long long c[maxn], s[maxn]; long long a[maxn], num[maxn]; int main() { long long n, x, y; while (cin >> n >> x >> y) { long long ans = n * x; memset(num, 0, sizeof(num)); for (int i = 1; i <= n; i++) { cin >> a[i]; num[a[i]]++; } c[0] = s[0] = 0; for (int i = 1; i <= 2e6; i++) { c[i] = c[i - 1] + num[i]; s[i] = s[i - 1] + i * num[i]; } long long p = (x + y - 1) / y; for (int i = 2; i <= 1e6; i++) { long long cur = 0; for (int j = i; j <= 1e6 + i && cur < ans; j += i) { int l = j - i, r = j; int k = r - p; k = max(k, l); long long temp = (c[r] - c[k]) * j - (s[r] - s[k]); cur += temp * y; cur += (c[k] - c[l]) * x; } ans = min(ans, cur); } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; getline(cin, s); long long n = s.length(), i = n - 1; while (1) { if ((s[i] >= 65 && s[i] <= 91) || (s[i] >= 97 && s[i] <= 122)) { if (s[i] == a || s[i] == y || s[i] == e || s[i] == i || s[i] == o || s[i] == u ) { cout << YES << endl; break; } else if (s[i] == A || s[i] == Y || s[i] == E || s[i] == I || s[i] == O || s[i] == U ) { cout << YES << endl; break; } else { cout << NO << endl; break; } } i--; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 7e3 + 11; int n; vector<int> s[2]; const int loose = 0; const int win = 1; bool vis[2][maxn][2]; int deg[maxn][2]; int32_t main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int k, i = 0; i < 2; i++) { cin >> k; s[i].resize(k); for (auto &x : s[i]) cin >> x; } queue<pair<int, int> > q[2]; q[loose].push({0, 0}); q[loose].push({0, 1}); vis[loose][0][0] = 1; vis[loose][0][1] = 1; while (!q[loose].empty()) { while (!q[loose].empty()) { pair<int, int> fr = q[loose].front(); q[loose].pop(); int player = fr.second ^ 1; int me = fr.first; for (auto x : s[player]) { int wp = me - x; while (wp < 0) wp += n; if (!vis[win][wp][player] && !vis[loose][wp][player]) { vis[win][wp][player] = 1; q[win].push({wp, player}); } } } while (!q[win].empty()) { pair<int, int> fr = q[win].front(); q[win].pop(); int player = fr.second ^ 1; int me = fr.first; for (auto x : s[player]) { int lp = me - x; while (lp < 0) lp += n; if (!vis[loose][lp][player] && !vis[win][lp][player] && ++deg[lp][player] == (int)(s[player]).size()) { vis[loose][lp][player] = 1; q[loose].push({lp, player}); } } } } for (int player = 0; player < 2; player++) { for (int i = 1; i < n; i++) { if (vis[win][i][player]) cout << Win ; else if (vis[loose][i][player]) cout << Lose ; else cout << Loop ; } cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER2_BEHAVIORAL_PP_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_BEHAVIORAL_PP_V
|
module Seven_seg(clk, reset, DAT_I, STB, DAT_O, ACK, WE, Segment, AN, debug_data_hold);
input clk, reset;
input [31: 0] DAT_I;
input STB;
input WE;
output reg [3: 0] AN;
output [7: 0] Segment;
output [31: 0] DAT_O;
output ACK;
output [15: 0] debug_data_hold;
reg [7: 0] digit_seg, digit;
reg [15: 0] data_hold = 16'h2333;
reg [31: 0] cnt = 0;
wire [1: 0] scan;
always @(posedge clk) begin
cnt <= cnt + 1;
end
assign scan = cnt[18: 17];
// I'm always ready when you need me ^_^
assign ACK = STB;
assign Segment = digit_seg;
assign DAT_O = Segment;
always @(posedge clk or posedge reset) begin
if (reset) data_hold <= 16'h2333;
else data_hold <= STB ? DAT_I : data_hold;
end
always @* begin
case(scan)
0: AN = 4'b1110;
1: AN = 4'b1101;
2: AN = 4'b1011;
3: AN = 4'b0111;
endcase
end
always @* begin
case(scan)
0: digit = data_hold[3: 0];
1: digit = data_hold[7: 4];
2: digit = data_hold[11: 8];
3: digit = data_hold[15: 12];
endcase
end
always @* begin
case(digit)
4'b0000: digit_seg = 8'b11000000;
4'b0001: digit_seg = 8'b11111001;
4'b0010: digit_seg = 8'b10100100;
4'b0011: digit_seg = 8'b10110000;
4'b0100: digit_seg = 8'b10011001;
4'b0101: digit_seg = 8'b10010010;
4'b0110: digit_seg = 8'b10000010;
4'b0111: digit_seg = 8'b11111000;
4'b1000: digit_seg = 8'b10000000;
4'b1001: digit_seg = 8'b10010000;
4'b1010: digit_seg = 8'b10001000;
4'b1011: digit_seg = 8'b10000011;
4'b1100: digit_seg = 8'b11000110;
4'b1101: digit_seg = 8'b10100001;
4'b1110: digit_seg = 8'b10000110;
4'b1111: digit_seg = 8'b10001110;
endcase
end
// debug signal
assign debug_data_hold = data_hold;
endmodule
|
`timescale 1ns / 1ps
module IDEX
(
// Input
input Clk,
input Reset,
input [31:0] PCIn,
input [31:0] DataIn1,
input [31:0] DataIn2,
input [4:0] rsIn,
input [31:0] ImmediateIn,
input [4:0] rtIn,
input [2:0] WBIn,
input [1:0] MIn,
input [4:0] EXIn,
// Output
output reg [31:0] PCOut,
output reg [31:0] DataOut1,
output reg [31:0] DataOut2,
output reg [4:0] rsOut,
(* equivalent_register_removal = "no" *) output reg [31:0] ImmediateOut,
output reg [4:0] rtOut,
(* equivalent_register_removal = "no" *) output reg [2:0] WBOut,
(* equivalent_register_removal = "no" *) output reg [1:0] MOut,
(* equivalent_register_removal = "no" *) output reg [4:0] EXOut
);
always @( posedge Clk or posedge Reset )
begin
if ( Reset )
begin
PCOut <= 32'b0;
DataOut1 <= 32'b0;
DataOut2 <= 32'b0;
rsOut <= 5'b0;
ImmediateOut <= 32'b0;
rtOut <= 5'b0;
WBOut <= 2'b0;
MOut <= 2'b0;
EXOut <= 4'b0;
end
else
begin
PCOut <= PCIn;
DataOut1 <= DataIn1;
DataOut2 <= DataIn2;
rsOut <= rsIn;
ImmediateOut <= ImmediateIn;
rtOut <= rtIn;
WBOut <= WBIn;
MOut <= MIn;
EXOut <= EXIn;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string start, end; cin >> start >> end; string srev = start; reverse(srev.begin(), srev.end()); vector<int> vs[26], vr[26]; int slen = start.length(); for (int i = 0; i < slen; i++) { vs[start[i] - a ].push_back(i); vr[srev[i] - a ].push_back(i); } int elen = end.length(); bool flag = true; for (int i = 0; i < elen; i++) { if (vs[end[i] - a ].size() == 0) { flag = false; break; } } if (!flag) cout << -1 << endl; else { int no = 0; vector<pair<int, int> > res; for (int i = 0; i < elen;) { int size = vs[end[i] - a ].size(); pair<int, int> p; int maxl, ans = 0, index, tmp; for (int j = 0; j < size; j++) { index = vs[end[i] - a ][j]; tmp = index; maxl = i; while ((index < slen - 1) && (maxl < elen - 1) && start[index + 1] == end[maxl + 1]) { index++; maxl++; } if (maxl - i + 1 > ans) { ans = maxl - i + 1; p = make_pair(tmp, index); } } maxl = i; for (int j = 0; j < size; j++) { index = vr[end[i] - a ][j]; tmp = index; maxl = i; while ((index < slen - 1) && (maxl < elen - 1) && srev[index + 1] == end[maxl + 1]) { index++; maxl++; } if (maxl - i + 1 > ans) { ans = maxl - i + 1; p = make_pair(slen - 1 - tmp, slen - 1 - index); } } i += ans; no++; res.push_back(p); } cout << no << endl; for (int i = 0; i < res.size(); i++) cout << res[i].first + 1 << << res[i].second + 1 << endl; } }
|
#include <bits/stdc++.h> #define rep(i, a, b) for (int i = a; i <= b; i++) #define per(i, a, b) for (int i = a; i >= b; i--) using namespace std; typedef unsigned long long ull; typedef pair <int, int> pii; typedef long long ll; template <typename T> inline void read(T &f) { f = 0; T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { fu = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } const int N = 3e5 + 5; struct seg_t { int mx[N << 2]; void build(int u, int l, int r) { mx[u] = 0; if (l == r) return; int mid = (l + r) >> 1; build(u << 1, l, mid); build(u << 1 | 1, mid + 1, r); } void modify(int u, int l, int r, int x, int y) { mx[u] = max(mx[u], y); if (l == r) return; int mid = (l + r) >> 1; if (mid >= x) modify(u << 1, l, mid, x, y); else modify(u << 1 | 1, mid + 1, r, x, y); } int query(int u, int L, int R, int l, int r) { if (l <= L && R <= r) return mx[u]; int mid = (L + R) >> 1, ans = 0; if (mid >= l) ans = max(ans, query(u << 1, L, mid, l, r)); if (mid + 1 <= r) ans = max(ans, query(u << 1 | 1, mid + 1, R, l, r)); return ans; } } tr, rmq; set <int> pos; set <int> :: iterator it; int a[N], cando[N], lpos[N], pre[N], ans[N]; int T, n; int main() { read(T); while (T--) { read(n); rmq.build(1, 1, n); for (int i = 1; i <= n; i++) read(a[i]), rmq.modify(1, 1, n, i, min(n, i + a[i])); tr.build(1, 1, n); for (int i = n; i >= 1; i--) { int r = min(i + a[i], n); if (i + 1 <= r) tr.modify(1, 1, n, i, tr.query(1, 1, n, i + 1, r)); else tr.modify(1, 1, n, i, i); } for (int i = 1; i <= n + 1; i++) cando[i] = 0; cando[1] = 1; pos.clear(); for (int i = 2; i <= n; i++) { if (cando[i - 1]) pos.insert(i - 1); it = pos.lower_bound(i - a[i]); if (it != pos.end()) { pre[i] = lpos[*it]; int r = i - 1; if (lpos[*it] != *it) r = rmq.query(1, 1, n, *it, i - 1); else if (*it + 1 <= i - 1) r = rmq.query(1, 1, n, *it + 1, i - 1); if (r >= i + 1) r = tr.query(1, 1, n, i + 1, r); if (!cando[r + 1]) { cando[r + 1] = 1; lpos[r + 1] = i; } if (r == n) break; } } if (cando[n + 1]) { printf( YES n ); for (int i = 1; i <= n; i++) ans[i] = 0; int now = lpos[n + 1]; while (now) { ans[now] = 1; now = pre[now]; } for (int i = 1; i <= n; i++) { if (ans[i]) putchar( L ); else putchar( R ); } putchar( n ); } else { printf( NO n ); } } return 0; }
|
`include "xorGate.v"
module xorGateTest ();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
// declare an instance of the module
xorGate xorGate (busADD, busA, busB);
// Running the GUI part of simulation
xorGatetester tester (busADD, busA, busB);
// file for gtkwave
initial
begin
$dumpfile("xorGatetest.vcd");
$dumpvars(1, xorGate);
end
endmodule
module xorGatetester (busADD, busA, busB);
input [31:0] busADD;
output reg [31:0] busA, busB;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t\t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t ", busADD, busA, busB, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const long double pi = acos(-1.0); const long double eps = 1e-6; const int INF = 1E9; const int MAXN = 5111; struct node { pair<int, int> key; int pr, cnt; node *l, *r; node(pair<int, int> _key) { key = _key; pr = rand(); cnt = 1; l = r = NULL; } }; int cnt(node *p) { return p ? p->cnt : 0; } void upd_cnt(node *&p) { if (p) p->cnt = 1 + cnt(p->l) + cnt(p->r); } void split(node *p, pair<int, int> key, node *&l, node *&r) { if (p == NULL) { l = r = NULL; return; } if (key < p->key) { split(p->l, key, l, p->l); r = p; } else { split(p->r, key, p->r, r); l = p; } upd_cnt(p); } void merge(node *&p, node *l, node *r) { if (l == NULL) p = r; else if (r == NULL) p = l; else if (l->pr < r->pr) { p = l; merge(l->r, l->r, r); } else { p = r; merge(r->l, l, r->l); } upd_cnt(p); } void insert(pair<int, int> key, int pr, node *&p) { if (p == NULL) { p = new node(key); p->pr = pr; return; } if (pr > p->pr) { if (key > p->key) insert(key, pr, p->r); else insert(key, pr, p->l); } else { node *t = new node(key); t->pr = pr; split(p, key, t->l, t->r); p = t; } upd_cnt(p); } void erase(pair<int, int> key, node *&p) { if (p == NULL) return; if (p->key == key) merge(p, p->l, p->r); else { if (key < p->key) erase(key, p->l); else erase(key, p->r); } upd_cnt(p); } int n, m; vector<int> color, used; vector<vector<int> > g, queries; vector<pair<int, int> > q; vector<node *> root; vector<map<int, int> > lib; vector<int> ans, link; void init() { color.resize(n); used.resize(n, 0); root.resize(n, NULL); g.resize(n); queries.resize(n); q.resize(m); ans.resize(m); link.resize(n); lib.resize(n); } void intersect(int vid, int wid, node *&w) { if (!w) return; if (w->l) intersect(vid, wid, w->l); if (w->r) intersect(vid, wid, w->r); int ckey = w->key.second; if (lib[link[vid]].find(ckey) == lib[link[vid]].end()) { lib[link[vid]][ckey] = w->key.first; insert(w->key, rand(), root[vid]); } else { erase(make_pair(lib[link[vid]][ckey], ckey), root[vid]); w->key.first += lib[link[vid]][ckey]; insert(w->key, rand(), root[vid]); lib[link[vid]][ckey] = w->key.first; } lib[link[wid]].erase(ckey); delete w; } void dfs(int v, int par) { used[v] = 1; for (int i = 0; i < (int)(g[v].size()); i++) { int w = g[v][i]; if (!used[w]) { dfs(w, v); } } if (v == 0) { v = v; } int maxid = -1; for (int i = 0; i < (int)(g[v].size()); i++) { int w = g[v][i]; if (w != par) { if (maxid == -1 || cnt(root[w]) > cnt(root[maxid])) maxid = w; } } if (maxid != -1) { link[v] = link[maxid]; root[v] = root[maxid]; for (int i = 0; i < (int)(g[v].size()); i++) { int w = g[v][i]; if (w != par && w != maxid) { intersect(v, w, root[w]); } } if (lib[link[v]].find(color[v]) == lib[link[v]].end()) { lib[link[v]][color[v]] = 1; insert(make_pair(1, color[v]), rand(), root[v]); } else { erase(make_pair(lib[link[v]][color[v]], color[v]), root[v]); lib[link[v]][color[v]]++; insert(make_pair(lib[link[v]][color[v]], color[v]), rand(), root[v]); } } else { root[v] = new node(make_pair(1, color[v])); link[v] = v; lib[link[v]][color[v]] = 1; } node *t1 = NULL, *t2 = NULL; for (int i = 0; i < queries[v].size(); i++) { int qid = queries[v][i]; split(root[v], make_pair(q[qid].second, 0), t1, t2); ans[qid] = cnt(t2); merge(root[v], t1, t2); } } int main() { cin >> n >> m; init(); for (int i = 0; i < (int)(n); i++) cin >> color[i]; for (int i = 0; i < (int)(n - 1); i++) { int a, b; scanf( %d%d , &a, &b); a--, b--; g[a].push_back(b); g[b].push_back(a); } for (int i = 0; i < (int)(m); i++) { cin >> q[i].first >> q[i].second; q[i].first--; queries[q[i].first].push_back(i); } dfs(0, 0); for (int i = 0; i < (int)(m); i++) printf( %d n , ans[i]); return 0; }
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
recF32ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(8, 24, 5, 11)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF64ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(11, 53, 5, 11)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF128ToRecF16 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(15, 113, 5, 11)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF16ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(5, 11, 8, 24)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF64ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(11, 53, 8, 24)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF128ToRecF32 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(15, 113, 8, 24)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF16ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(5, 11, 11, 53)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF32ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(8, 24, 11, 53)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF128ToRecF64 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(15, 113, 11, 53)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF16ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(5, 11, 15, 113)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF32ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(8, 24, 15, 113)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
module
recF64ToRecF128 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
recFNToRecFN#(11, 53, 15, 113)
recFNToRecFN(control, in, roundingMode, out, exceptionFlags);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_4_V
`define SKY130_FD_SC_LP__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, i; cin >> n; long long a[n + 1]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0, sum = 0; for (i = 0; i < n; i++) { if (sum <= a[i]) { ans++; sum += a[i]; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin>>t; while(t--) { long long int n; cin>>n; long long int sum=0; for(int i=0;i<n;i++) { long long int a; cin>>a; sum+=a; } sum%=n; long long int k=n-sum; cout<<sum*k<<endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:14 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_1/bram_1024_1_stub.v
// Design : bram_1024_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_1024_1(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S4_altera (
aclr,
address,
clken,
clock,
data,
wren,
q);
input aclr;
input [11:0] address;
input clken;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
parameter init_file = "";
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.clocken0 (clken),
.q_a (sub_wire0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "NORMAL",
altsyncram_component.init_file = init_file,
//altsyncram_component.init_file = "./sources_ngnp_multicore/src/lr0_0.mif",
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// wait generator for Z80
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zwait(
input wire rst_n,
input wire wait_start_gluclock,
input wire wait_start_comport,
input wire wait_end,
output reg [6:0] waits,
output wire wait_n,
output wire spiint_n
);
`ifdef SIMULATE
initial
begin
// force waits = 7'd0;
waits <= 7'd0;
end
`endif
wire wait_off_n;
assign wait_off_n = (~wait_end) & rst_n;
// RS-flipflops
//
always @(posedge wait_start_gluclock, negedge wait_off_n)
if( !wait_off_n )
waits[0] <= 1'b0;
else if( wait_start_gluclock )
waits[0] <= 1'b1;
//
always @(posedge wait_start_comport, negedge wait_off_n)
if( !wait_off_n )
waits[1] <= 1'b0;
else if( wait_start_comport )
waits[1] <= 1'b1;
always @(posedge wait_end) // just dummy for future extensions
begin
waits[6:2] <= 5'd0;
end
`ifndef SIMULATE
assign spiint_n = ~|waits;
assign wait_n = spiint_n ? 1'bZ : 1'b0;
`else
assign spiint_n = 1'b1;
assign wait_n = 1'bZ;
`endif
endmodule
|
// USED ONLY TO SELECT VC BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 5; //trunk number
parameter WB = 2; //max. number of links per trunk
parameter integer links[WA][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
integer i,j;
logic [WA*WB-1:0] selected;
always_comb begin
selected = '0;
for (i=0; i<WA; i=i+1)
for (j=0; j<links[i][OUT]; j=j+1)
selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
end //always_comb
assign selected_bit=|selected;
endmodule // unary_select_pair
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
|
#include <bits/stdc++.h> class Solver { public: Solver() = default; void read() { int n; std::cin >> n; int left = 0; int right = 0; for (int i = 0; i < n; ++i) { int x, y; std::cin >> x >> y; if (x < 0) left++; else right++; } if (left <= 1 || right <= 1) std::cout << Yes n ; else std::cout << No n ; } void solve() {} void write() {} }; int main() { Solver solver; solver.read(); solver.solve(); solver.write(); return 0; }
|
#include <bits/stdc++.h> template <typename T> bool ckmax(T& a, const T& b) { return b > a ? a = b, 1 : 0; } template <typename T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } const int MV = 1e5 + 10; const int MM = 1e5 + 10; const int MG = 450; const int INF = 0x3f3f3f3f; struct DSU { int p[MM], t[MM]; char r[MM]; void init(int M) { memset(p, -1, M * sizeof *p); memset(r, 0, M * sizeof *r); std::iota(t, t + M, 0); } int find(int v) { return ~p[v] ? p[v] = find(p[v]) : v; } bool merge(int a, int b) { a = find(a), b = find(b); if (a == b) return 0; t[a] = t[b]; if (r[a] < r[b]) std::swap(a, b); r[a] += r[a] == r[b]; p[a] = b; } } dsu; int M, v[MM], maxv[MM], dp[MM][2], ub[MV]; bool ok[MM]; int solve() { scanf( %d , &M); for (int i = 0; i < M; ++i) { scanf( %d , v + i); assert(v[i] > 0); } for (int i = 0, j = 0; i < MV; ++i) { while (j < M && v[j] == i) ++j; ub[i] = j; } memset(maxv, 0x3f, sizeof maxv); std::fill(ok, ok + M, 1); int f = 0; bool c = 0; for (int i = 0; f == i; ++i, c ^= 1) { dsu.init(M + 1); for (int j = M - 1; j >= 0; --j) { if (ok[j] &= (maxv[j] > 0)) ckmax(f, i + 1); dp[j][c] = v[j] * 2 - maxv[j]; ckmax(dp[j][c], 0); ckmin(dp[j][c], v[j] - 1); if (i) { ckmax(dp[j][c], dp[j][!c]); int x = ub[dp[j][!c]], y = ub[dp[j][c]]; for (int g = dsu.find(x), t; (t = dsu.t[g]) < y;) { maxv[t] = v[j]; dsu.merge(g, t + 1); g = dsu.find(g); } } } memset(maxv, 0, sizeof maxv); } return f; } int main() { int N, f = 0; scanf( %d , &N); for (int i = 0; i < N; ++i) f ^= solve(); if (f) printf( YES n ); else printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MX = 300000; int n, arr[MX], bit[MX], ans = 0, lis; void update(int x, int V) { while (x <= n) { bit[x] = max(bit[x], V); x += x & -x; } } int get(int x) { int ret = 0; while (x > 0) { ret = max(ret, bit[x]); x -= x & -x; } return ret; } int main() { scanf( %d , &n); memset(bit, 0, sizeof(bit)); for (int j = 1; j <= n; j++) { scanf( %d , &arr[j]); lis = get(arr[j]) + 1; update(arr[j] + 1, lis); ans = max(ans, lis); } cout << ans << endl; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.