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`timescale 1 ns / 1 ps
// LDAC is pulsed low after the 8 DAC registers are written
module precision_dac #
(
parameter CLK_DIV = 3
)
(
input wire clk,
input wire [16*4-1:0] data,
input wire valid,
input wire [4-1:0] cmd,
output reg sync,
output reg sclk,
output reg sdi,
output reg ldac
);
reg [16*8-1:0] data_reg;
reg [4-1:0] cmd_reg;
reg [CLK_DIV-1:0] cnt_clk = 0; // Divide by 2**CLK_DIV the clock frequency
reg [7-1: 0] cnt_sclk = 0;
initial sync = 1'b1;
always @(posedge clk) begin
if (valid == 1'b1) begin
cnt_clk <= cnt_clk + 1;
if (cnt_clk == {{1'b0}, {(CLK_DIV-1){1'b1}}}) begin
sclk <= 1'b1;
if (cnt_sclk == {(7){1'b0}}) begin
ldac <= 1'b1;
cmd_reg <= cmd;
data_reg <= data;
end
if (cnt_sclk[5-1:0] == {(5){1'b0}}) begin
sync <= 1'b0;
end
cnt_sclk <= cnt_sclk + 1;
if (sync == 1'b0 | cnt_sclk[5-1:0] == {(5){1'b0}}) begin
if (cnt_sclk[5-1:2] == 3'b000) begin
sdi <= cmd[3-cnt_sclk[2-1:0]]; // write command bits
end else if (cnt_sclk[5-1:2] == 3'b001) begin
sdi <= (cnt_sclk[7-1:5] == ~cnt_sclk[2-1:0]);
end else if (cnt_sclk[5-1:0] == 5'b11000) begin
sync <= 1'b1;
if (cnt_sclk[7-1:5] == 3'b11) begin
ldac <= 1'b0;
end
end else begin
sdi <= data_reg[16*cnt_sclk[7-1:5] + 23 - cnt_sclk[5-1:0]];
end
end
end
if (cnt_clk == {(CLK_DIV){1'b1}}) begin
//cnt_clk <= 2'b00;
sclk <= 1'b0;
end
end else begin // valid == 1'b0
cnt_clk <= 0;
cnt_sclk <= 0;
sync <= 1;
sdi <= 0;
ldac <= 0;
sclk <= 0;
end
end
endmodule
|
module bw_clk_cl_fpu_cmp ( so, dbginit_l, cluster_grst_l, rclk, si, se,
adbginit_l, gdbginit_l, arst_l, grst_l, cluster_cken, gclk );
input si, se, adbginit_l, gdbginit_l, arst_l, grst_l, cluster_cken, gclk;
output so, dbginit_l, cluster_grst_l, rclk;
wire \I0/sync_cluster_master/N3 , \I0/sync_cluster_slave/so_l ,
\I0/rst_repeater/pre_sync_out , \I0/dbginit_repeater/pre_sync_out ,
\I0/rst_repeater/repeater/i0/N10 , \I0/rst_repeater/syncff/i0/N10 ,
\I0/dbginit_repeater/repeater/i0/N10 ,
\I0/dbginit_repeater/syncff/i0/N10 , n10, n11, n12, n13, n14, n15,
n16;
assign \I0/sync_cluster_master/N3 = cluster_cken;
DFFX1 \I0/sync_cluster_master/q_r_reg ( .D(\I0/sync_cluster_master/N3 ),
.CLK(gclk), .QN(n11) );
LATCHX1 \I0/sync_cluster_slave/so_l_reg ( .CLK(n10), .D(n11), .Q(
\I0/sync_cluster_slave/so_l ) );
DFFARX1 \I0/rst_repeater/repeater/i0/q_reg ( .D(
\I0/rst_repeater/repeater/i0/N10 ), .CLK(gclk), .RSTB(arst_l), .Q(
\I0/rst_repeater/pre_sync_out ) );
LATCHX1 \I0/rst_repeater/lockup/so_l_reg ( .CLK(n10), .D(n15), .QN(n12) );
DFFARX1 \I0/rst_repeater/syncff/i0/q_reg ( .D(
\I0/rst_repeater/syncff/i0/N10 ), .CLK(rclk), .RSTB(arst_l), .Q(
cluster_grst_l) );
DFFARX1 \I0/dbginit_repeater/repeater/i0/q_reg ( .D(
\I0/dbginit_repeater/repeater/i0/N10 ), .CLK(gclk), .RSTB(adbginit_l),
.Q(\I0/dbginit_repeater/pre_sync_out ) );
LATCHX1 \I0/dbginit_repeater/lockup/so_l_reg ( .CLK(n10), .D(n14), .QN(n13)
);
DFFARX1 \I0/dbginit_repeater/syncff/i0/q_reg ( .D(
\I0/dbginit_repeater/syncff/i0/N10 ), .CLK(rclk), .RSTB(adbginit_l),
.Q(dbginit_l) );
INVX0 U11 ( .INP(se), .ZN(n16) );
OA221X1 U12 ( .IN1(se), .IN2(gdbginit_l), .IN3(n16), .IN4(cluster_grst_l),
.IN5(adbginit_l), .Q(\I0/dbginit_repeater/repeater/i0/N10 ) );
OA221X1 U13 ( .IN1(se), .IN2(\I0/dbginit_repeater/pre_sync_out ), .IN3(n16),
.IN4(n13), .IN5(adbginit_l), .Q(\I0/dbginit_repeater/syncff/i0/N10 )
);
OA221X1 U14 ( .IN1(se), .IN2(grst_l), .IN3(n16), .IN4(si), .IN5(arst_l), .Q(
\I0/rst_repeater/repeater/i0/N10 ) );
OA221X1 U15 ( .IN1(se), .IN2(\I0/rst_repeater/pre_sync_out ), .IN3(n16),
.IN4(n12), .IN5(arst_l), .Q(\I0/rst_repeater/syncff/i0/N10 ) );
NOR2X0 U16 ( .IN1(\I0/rst_repeater/pre_sync_out ), .IN2(n16), .QN(n15) );
NOR2X0 U17 ( .IN1(\I0/dbginit_repeater/pre_sync_out ), .IN2(n16), .QN(n14)
);
INVX0 U18 ( .INP(gclk), .ZN(n10) );
NOR2X0 U19 ( .IN1(\I0/sync_cluster_slave/so_l ), .IN2(n10), .QN(rclk) );
OR2X1 U20 ( .IN1(dbginit_l), .IN2(n16), .Q(so) );
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void out(T x) { cout << x << endl; exit(0); } const long long mod = 1e9 + 7; const int maxn = 1e6 + 5; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int n, start, x; int ans = 1e9 + 10; int beforeVal = -1; int beforeIdx; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> start >> x; beforeIdx = start; vector<int> v; for (int i = 1; i <= n; i++) { v.push_back(i); } shuffle(v.begin(), v.end(), rng); v.resize(min(n, 999)); for (int q : v) { cout << ? << q << endl; cout.flush(); int val; int nxt; cin >> val >> nxt; if (val >= x) { ans = min(ans, val); } else { if (val > beforeVal) { beforeVal = val; beforeIdx = nxt; } } } for (int i = 0; i < 1000; i++) { if (beforeIdx == -1) break; cout << ? << beforeIdx << endl; cout.flush(); int val; int nxt; cin >> val >> nxt; if (val >= x) { ans = min(ans, val); } beforeIdx = nxt; } if (ans == 1e9 + 10) ans = -1; cout << ! << ans << endl; cout.flush(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const long long INF = 1000 * 1000 * 1000 + 7; const long long LINF = INF * (long long)INF; const int MAX = 100 + 47; int A[MAX]; vector<int> B; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = (0); i < (n); i++) cin >> A[i]; int cnt = 0; int vid = 0; for (int i = (0); i < (n + 1); i++) { if ((A[i] < 0 && vid == 2) || i == n) { B.push_back(cnt); cnt = 1; vid = 1; continue; } cnt++; if (A[i] < 0) vid++; } cout << (int)B.size() << endl; for (int i = (0); i < ((int)B.size()); i++) { cout << B[i] << ; } cout << endl; }
|
// file: main_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___800.000______0.000_______N/A______205.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________25.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_dcm,clk_wiz_v4_1,{component_name=main_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=true,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=40.000,clkin2_period=40.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
module main_dcm
(// Clock in ports
input CLK_OSC,
// Clock out ports
output CLK_HASH,
// Dynamic reconfiguration ports
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE,
// Status and control signals
input RESET,
output CLK_VALID
);
parameter DCM_DIVIDER = 10;
parameter DCM_MULTIPLIER = 60;
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (CLK_OSC));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire locked_int;
wire [2:1] status_int;
wire clkfx;
wire clkfx180_unused;
wire clkfx_unused; // KRAMBLE was clkfxdv_unused
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (4), // KRAMBLE approx 50Mhz dcm_clk (for nominal 200MHz)
.CLKFX_DIVIDE (DCM_DIVIDER),
.CLKFX_MULTIPLY (DCM_MULTIPLIER),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (40.000),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (clkin1),
// Output clocks
.CLKFX (clkfx_unused),
.CLKFX180 (clkfx180_unused),
.CLKFXDV (clkfx), // KRAMBLE now using divided output
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET));
assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2] == 1'b 0 ) );
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_HASH),
.I (clkfx));
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP cache
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 9
)
(
input wire clk,
input wire rst,
/*
* Cache query
*/
input wire query_request_valid,
output wire query_request_ready,
input wire [31:0] query_request_ip,
output wire query_response_valid,
input wire query_response_ready,
output wire query_response_error,
output wire [47:0] query_response_mac,
/*
* Cache write
*/
input wire write_request_valid,
output wire write_request_ready,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
/*
* Configuration
*/
input wire clear_cache
);
reg mem_write = 0;
reg store_query = 0;
reg store_write = 0;
reg query_ip_valid_reg = 0, query_ip_valid_next;
reg [31:0] query_ip_reg = 0;
reg write_ip_valid_reg = 0, write_ip_valid_next;
reg [31:0] write_ip_reg = 0;
reg [47:0] write_mac_reg = 0;
reg clear_cache_reg = 0, clear_cache_next;
reg [CACHE_ADDR_WIDTH-1:0] wr_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, wr_ptr_next;
reg [CACHE_ADDR_WIDTH-1:0] rd_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, rd_ptr_next;
reg valid_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg query_request_ready_reg = 0, query_request_ready_next;
reg query_response_valid_reg = 0, query_response_valid_next;
reg query_response_error_reg = 0, query_response_error_next;
reg [47:0] query_response_mac_reg = 0;
reg write_request_ready_reg = 0, write_request_ready_next;
wire [31:0] query_request_hash;
wire [31:0] write_request_hash;
assign query_request_ready = query_request_ready_reg;
assign query_response_valid = query_response_valid_reg;
assign query_response_error = query_response_error_reg;
assign query_response_mac = query_response_mac_reg;
assign write_request_ready = write_request_ready_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
rd_hash (
.data_in(query_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(query_request_hash)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
wr_hash (
.data_in(write_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(write_request_hash)
);
integer i;
initial begin
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
valid_mem[i] = 1'b0;
ip_addr_mem[i] = 32'd0;
mac_addr_mem[i] = 48'd0;
end
end
always @* begin
mem_write = 1'b0;
store_query = 1'b0;
store_write = 1'b0;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
clear_cache_next = clear_cache_reg | clear_cache;
query_ip_valid_next = query_ip_valid_reg;
query_request_ready_next = (~query_ip_valid_reg || ~query_request_valid || query_response_ready) && !clear_cache_next;
query_response_valid_next = query_response_valid_reg & ~query_response_ready;
query_response_error_next = query_response_error_reg;
if (query_ip_valid_reg && (~query_request_valid || query_response_ready)) begin
query_response_valid_next = 1;
query_ip_valid_next = 0;
if (valid_mem[rd_ptr_reg] && ip_addr_mem[rd_ptr_reg] == query_ip_reg) begin
query_response_error_next = 0;
end else begin
query_response_error_next = 1;
end
end
if (query_request_valid && query_request_ready && (~query_ip_valid_reg || ~query_request_valid || query_response_ready)) begin
store_query = 1;
query_ip_valid_next = 1;
rd_ptr_next = query_request_hash[CACHE_ADDR_WIDTH-1:0];
end
write_ip_valid_next = write_ip_valid_reg;
write_request_ready_next = !clear_cache_next;
if (write_ip_valid_reg) begin
write_ip_valid_next = 0;
mem_write = 1;
end
if (write_request_valid && write_request_ready) begin
store_write = 1;
write_ip_valid_next = 1;
wr_ptr_next = write_request_hash[CACHE_ADDR_WIDTH-1:0];
end
if (clear_cache) begin
clear_cache_next = 1'b1;
wr_ptr_next = 0;
end else if (clear_cache_reg) begin
wr_ptr_next = wr_ptr_reg + 1;
clear_cache_next = wr_ptr_next != 0;
mem_write = 1;
end
end
always @(posedge clk) begin
if (rst) begin
query_ip_valid_reg <= 1'b0;
query_request_ready_reg <= 1'b0;
query_response_valid_reg <= 1'b0;
write_ip_valid_reg <= 1'b0;
write_request_ready_reg <= 1'b0;
clear_cache_reg <= 1'b1;
wr_ptr_reg <= 0;
end else begin
query_ip_valid_reg <= query_ip_valid_next;
query_request_ready_reg <= query_request_ready_next;
query_response_valid_reg <= query_response_valid_next;
write_ip_valid_reg <= write_ip_valid_next;
write_request_ready_reg <= write_request_ready_next;
clear_cache_reg <= clear_cache_next;
wr_ptr_reg <= wr_ptr_next;
end
query_response_error_reg <= query_response_error_next;
if (store_query) begin
query_ip_reg <= query_request_ip;
end
if (store_write) begin
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
rd_ptr_reg <= rd_ptr_next;
query_response_mac_reg <= mac_addr_mem[rd_ptr_reg];
if (mem_write) begin
valid_mem[wr_ptr_reg] <= !clear_cache_reg;
ip_addr_mem[wr_ptr_reg] <= write_ip_reg;
mac_addr_mem[wr_ptr_reg] <= write_mac_reg;
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
wasca_nios2_gen2_0_cpu_debug_slave_tck the_wasca_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
wasca_nios2_gen2_0_cpu_debug_slave_sysclk the_wasca_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic wasca_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[105], b[105]; int main() { int n, i, j, k, x, y; while (~scanf( %d , &n)) { for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } scanf( %d%d , &x, &y); for (i = 1, j = 0; i <= n; i++) { int count1 = 0, count2 = 0; for (k = 1; k <= n; k++) { if (k >= i) count1 += a[k]; else count2 += a[k]; } if ((count1 >= x && count1 <= y) && (count2 >= x && count2 <= y)) { b[j++] = i; break; } } if (j == 0) { printf( 0 n ); continue; } printf( %d n , b[0]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline bool smax(long long &a, long long b) { if (a < b) { a = b; return true; } else return false; } const long long MAXN = 1e5 + 100; long long dp[MAXN][4], par[MAXN][4], choose[MAXN][4], id[MAXN]; pair<long long, long long> p[MAXN], s; set<long long> sz; map<long long, long long> cost, toid; bool byP(long long x, long long y) { return greater<pair<long long, long long> >()(p[x], p[y]); } pair<long long, long long> ans[MAXN]; long long ansN; void get(long long i, long long j) { if (i) get(i - 1, par[i][j]); if (choose[i][j] != -1) ans[ansN++] = pair<long long, long long>(i - 1, choose[i][j]); } int main() { ios::sync_with_stdio(false); cout.tie(0); cin.tie(0); memset(dp, -63, sizeof dp); memset(choose, -1, sizeof choose); long long m; cin >> m; for (long long i = 0; i < m; i++) { cin >> s.second >> s.first; sz.insert(s.first); cost[s.first] = s.second; toid[s.first] = i; } long long n; cin >> n; for (long long i = 0; i < n; i++) cin >> p[i].second >> p[i].first, id[i] = i; p[n++] = pair<long long, long long>(-1, -1); id[n - 1] = n - 1; sort(id, id + n, byP); sort(p, p + n, greater<pair<long long, long long> >()); long long tmp = 0; if (sz.count(p[0].first)) tmp += 1; if (sz.count(p[0].first + 1)) tmp += 2; dp[0][tmp] = 0; cerr << bitset<2>(tmp) << endl; cost[-1] = 0; for (long long i = 0; i < n - 1; i++) for (long long j = 0; j < 4; j++) if (dp[i][j] >= 0) { long long cur = p[i].first; vector<long long> t; t.push_back(-1); if (j & 1) t.push_back(cur); if (j >> 1 & 1) t.push_back(cur + 1); for (long long k = 0; k < t.size(); k++) if (p[i].second >= cost[t[k]]) { long long newmask = 0, next = p[i + 1].first; if (sz.count(next) && t[k] != next) newmask += 1; if (sz.count(next + 1) && t[k] != next + 1) newmask += 2; if (next == cur) newmask &= j; if (next == cur - 1 && j % 2 == 0) newmask -= newmask / 2 * 2; if (smax(dp[i + 1][newmask], dp[i][j] + cost[t[k]])) { par[i + 1][newmask] = j; choose[i + 1][newmask] = t[k]; } } } get(n - 1, 0); cout << dp[n - 1][0] << n << ansN << n ; for (long long i = 0; i < ansN; i++) cout << id[ans[i].first] + 1 << << toid[ans[i].second] + 1 << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd3 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
|
`timescale 1ns / 1ns
module gui(clock,
reset,
keys,
mode,
//playback_keys
colour,
x,
y,
plot);
input clock;
input reset;
input [3:0] keys;
// input [3:0] playback_keys;
// input [1:0] mode;
output [2:0] colour;
output [7:0] x;
output [6:0] y;
output plot;
wire redraw;
wire [3:0] keys_pressed;
wire [14:0] clock_count;
controlgui g(
.clock(clock),
.reset(reset),
.plot(plot),
.keys(keys),
.redraw(redraw),
.clock_count(clock_count),
.keys_pressed(keys_pressed)
);
datapathgui d(
.clock(clock),
.reset(reset),
.redraw(redraw),
.keys_pressed(keys_pressed),
.playback_keys(playback_keys),
.clock_count(clock_count),
// .mode(mode),
.colour(colour),
.x(x),
.y(y)
);
endmodule
module controlgui(clock, reset, keys, plot, redraw, clock_count, keys_pressed);
input clock, reset;
input [3:0] keys;
//Remove unnecessary regs
output reg [3:0] keys_pressed;
output reg plot, redraw;
output reg [14:0] clock_count;
reg [2:0] current_state, next_state;
localparam REDRAW = 3'b000,
STATIONARY = 3'b001,
KEY_ONE_PRESSED = 3'b010,
KEY_TWO_PRESSED = 3'b011,
KEY_THREE_PRESSED = 3'b100,
KEY_FOUR_PRESSED = 3'b101;
/*
* Can be reset for testing purposes
*/
parameter PIXEL_COUNT = 15'b111100010100001;
always @(posedge clock) begin
if (!reset) begin
current_state <= REDRAW;
end
else begin
current_state <= next_state;
if (current_state != STATIONARY) begin
clock_count <= clock_count + 1'b1;
end
else begin
clock_count <= 15'b0;
end
end
end
always @(*)
begin: state_table
case (current_state)
REDRAW: next_state = clock_count == PIXEL_COUNT ? STATIONARY : REDRAW;
STATIONARY: begin
if (keys[0] == 1'b1) begin
next_state = KEY_ONE_PRESSED;
end
else if (keys[1] == 1'b1) begin
next_state = KEY_TWO_PRESSED;
end
else if (keys[2] == 1'b1) begin
next_state = KEY_THREE_PRESSED;
end
else if (keys[3] == 1'b1) begin
next_state = KEY_FOUR_PRESSED;
end
else begin
next_state = REDRAW;
end
end
KEY_ONE_PRESSED: next_state = clock_count == PIXEL_COUNT ? STATIONARY : KEY_ONE_PRESSED;
KEY_TWO_PRESSED:
default: next_state = REDRAW;
endcase
end
//datapath control signals
always @(*)
begin: signals
plot = 1'b0;
keys_pressed = 4'b0;
case (current_state)
REDRAW: begin
plot = 1'b1;
redraw = 1'b1;
end
KEY_ONE_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0001;
end
KEY_TWO_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0010;
end
KEY_THREE_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0100;
end
KEY_FOUR_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b1000;
end
endcase
end
endmodule
module datapathgui(clock,
reset,
redraw,
colour,
// mode,
x,
y,
clock_count);
input clock, reset, redraw;
// input [1:0] mode;
input [14:0] clock_count;
input [3:0] keys_pressed;
//Remove unnecessary regs
output reg [2:0] colour;
output reg [7:0] x;
output reg [6:0] y;
/*
* Don't need these
*/
reg [7:0] temp_x;
reg [6:0] temp_y;
localparam WHITE = 3'b111,
BLACK = 3'b000,
BLUE = 3'b001,
RED = 3'b100;
parameter FIRST_DIVIDER = 8'b00100111;
parameter SECOND_DIVIDER = 8'b01001111;
parameter THIRD_DIVIDER = 8'b01110111;
parameter MAX_X = 8'b10100000;
parameter MAX_Y = 7'b1111000;
always @(posedge clock) begin
if (!reset) begin
x <= 8'b0;
y <= 8'b0;
colour <= 3'b0;
temp_x <= 8'b0;
temp_y <= 7'b0;
end
else if (redraw) begin
// if (clock_count[1:0] < 3'b100 & clock_count[9:8] < 3'b100 & mode[1:0] > 1'b0) begin
// if (mode[1:0] == 2'b01) begin
// colour <= RED; //RECORDING
// end
// else begin
// colour <= GREEN; //PLAYBACK
// end
// end
if (clock_count[7:0] == FIRST_DIVIDER || clock_count[7:0] == SECOND_DIVIDER || clock_count[7:0] == THIRD_DIVIDER) begin
colour <= BLACK;
end
else begin
if (keys_pressed == 4'b0001 & clock_count[7:0] < FIRST_DIVIDER) begin // First key
colour <= BLUE;
end
else if (keys_pressed == 4'b0010 & clock_count[7:0] > FIRST_DIVIDER & clock_count[7:0] < SECOND_DIVIDER) begin // Second key
colour <= BLUE;
end
else if (keys_pressed == 4'b0100 & clock_count[7:0] > SECOND_DIVIDER & clock_count[7:0] < THIRD_DIVIDER) begin // Third key
colour <= BLUE;
end
else if (keys_pressed == 4'b1000 & clock_count[7:0] > THIRD_DIVIDER ) begin // Fourth key
colour <= BLUE;
end
else begin
colour <= WHITE;
end
end
if (!(clock_count[7:0] > MAX_X)) begin
x <= temp_x + clock_count[7:0];
end
if (!(clock_count[14:8] > MAX_Y)) begin
y <= temp_y + clock_count[14:8];
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 510; const int mod = 1e9 + 7; long long mi1[N], mi[N], C[N][N], dp[N][N]; int main() { int n, m; scanf( %d%d , &n, &m); mi[0] = mi1[0] = 1; for (int i = 1; i <= n; i++) { mi[i] = mi[i - 1] * m % mod; mi1[i] = mi1[i - 1] * (m - 1) % mod; } for (int i = 0; i <= n; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } for (int j = 1; j <= n; j++) dp[1][j] = C[n][j] * mi1[n - j] % mod; for (int i = 2; i <= n; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k <= j; k++) { long long V; V = (dp[i - 1][k] % mod * C[n - k][j - k] % mod * mi1[n - j] % mod * mi[k] % mod) % mod; dp[i][j] = (dp[i][j] + V) % mod; if (j == k) dp[i][j] = (dp[i][j] - mi1[n] * dp[i - 1][k] % mod + mod) % mod; } } } printf( %lld n , dp[n][n]); }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 5; int a[N], n; int dp[N][N / 2][2][2]; int solve(int idx, int lft, bool b4, bool b44) { if (lft < 0) return 1e9; if (idx == n) { if (lft) return 1e9; return 0; } int &ret = dp[idx][lft][b4][b44]; if (~ret) return ret; ret = solve(idx + 1, lft, 0, b4); if (!b4) { int x; int cost1 = 0, cost2 = 0; if (b44) { x = min(a[idx - 1], a[idx - 2] - 1); } else x = a[idx - 1]; if (idx) cost1 = max(0, x - (a[idx] - 1)); if (idx != n - 1) { cost2 = max(0, a[idx + 1] - (a[idx] - 1)); } ret = min(ret, solve(idx + 1, lft - 1, 1, 0) + cost1 + cost2); } return ret; } int main() { memset(dp, -1, sizeof dp); scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , a + i); for (int i = 1; i <= (n + 1) / 2; i++) { printf( %d , solve(0, i, 0, 0)); } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_64_12.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_64_12 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [11:0] data;
input rdreq;
input wrreq;
output empty;
output [11:0] q;
wire sub_wire0;
wire [11:0] sub_wire1;
wire empty = sub_wire0;
wire [11:0] q = sub_wire1[11:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_12_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
// Title : Pipelined multiplier.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_multiplier (
// ----- Inputs -----
clk_i,
rst_i,
stall_x,
stall_m,
operand_0,
operand_1,
// ----- Ouputs -----
result
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input stall_m; // Stall instruction in M stage
input [`LM32_WORD_RNG] operand_0; // Muliplicand
input [`LM32_WORD_RNG] operand_1; // Multiplier
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result; // Product of multiplication
reg [`LM32_WORD_RNG] result;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] muliplicand;
reg [`LM32_WORD_RNG] multiplier;
reg [`LM32_WORD_RNG] product;
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
multiplier <= {`LM32_WORD_WIDTH{1'b0}};
product <= {`LM32_WORD_WIDTH{1'b0}};
result <= {`LM32_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_x == `FALSE)
begin
muliplicand <= operand_0;
multiplier <= operand_1;
end
if (stall_m == `FALSE)
product <= muliplicand * multiplier;
result <= product;
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dmem16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dmem16 (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dmem16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int cnt = 0; int len = s.length(); for (int i = 0; i < len; i++) { if (s.at(i) == a ) cnt++; } int ltr = len - cnt; while (ltr >= cnt) { ltr--; len--; } cout << len; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_4_V
`define SKY130_FD_SC_HD__A41O_4_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41o_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41o_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_4_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int main() { int t; cin >> t; for (int tc = 0; tc < t; tc++) { long long a, b, c, d; cin >> a >> b >> c >> d; int temp = 1; if (a % 2) { temp *= -1; } if (b % 2) { temp *= -1; } if (temp == 1) { cout << Tidak Tidak ; if (b > 0 || c > 0) { cout << Ya ; } else { cout << Tidak ; } if (a > 0 || d > 0) { cout << Ya << endl; } else { cout << Tidak << endl; } } else { if (a > 0 || d > 0) { cout << Ya ; } else { cout << Tidak ; } if (b > 0 || c > 0) { cout << Ya ; } else { cout << Tidak ; } cout << Tidak Tidak << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int delta = 1e9 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int x; int d; cin >> x >> d; vector<long long int> ans; long long int cur = 1; for (int i = 31; i >= 0; i--) { long long int cnt = (1LL << i); while (x >= cnt) { x -= cnt; for (int j = 0; j < i; j++) { ans.push_back(cur); } cur += d; ans.push_back(cur); cur += d; } } cout << ans.size() << n ; for (auto a : ans) cout << a << ; cout << endl; ; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005, MAXM = 1000005, MAXT = 1 << 18; struct Edge { int to, val, next, id; } edge[MAXM]; struct MST { int u, v, w, id; } mst[MAXM]; int ppar[MAXN], head[MAXN], ist[MAXM], dep[MAXN], n, m, tot; void addedge(int u, int v, int w, int id) { edge[++tot] = (Edge){v, w, head[u], id}; head[u] = tot; } int find(int x) { return x == ppar[x] ? x : ppar[x] = find(ppar[x]); } void merge(int x, int y) { x = find(x), y = find(y); if (x != y) ppar[x] = y; } int mmn[MAXT], beg[MAXN], ed[MAXN], ans[MAXM], par[20][MAXN], mx[20][MAXN], dcnt; struct Que { int l, r, id; }; struct Mod { int p, w; }; vector<Que> qr1[MAXN], qr2[MAXN]; vector<Mod> md1[MAXN], md2[MAXN]; void dfs(int u, int fa) { beg[u] = ++dcnt; dep[u] = dep[fa] + 1; for (int i = head[u]; i; i = edge[i].next) { int v = edge[i].to; if (v == fa) continue; dfs(v, u); qr1[beg[v]].push_back((Que){beg[v], ed[v], edge[i].id}); qr2[ed[v]].push_back((Que){beg[v], ed[v], edge[i].id}); par[0][v] = u; mx[0][v] = edge[i].val; } ed[u] = dcnt; } void chk(int &x, int y) { x = x < y ? x : y; } void cxk(int &x, int y) { x = x > y ? x : y; } void upd(int x, int w, int l = 1, int r = n, int k = 1) { if (l == r) { chk(mmn[k], w); return; } int mid = (l + r) >> 1; if (x <= mid) upd(x, w, l, mid, k << 1); else upd(x, w, mid + 1, r, k << 1 | 1); chk(mmn[k], w); } int ask(int a, int b, int l = 1, int r = n, int k = 1) { if (a > r || b < l) return 1E9; if (a <= l && b >= r) return mmn[k]; int mid = (l + r) >> 1; return min(ask(a, b, l, mid, k << 1), ask(a, b, mid + 1, r, k << 1 | 1)); } int calc(int x, int y) { if (dep[x] > dep[y]) swap(x, y); int res = 0; for (int i = 19; ~i; i--) if (dep[par[i][y]] >= dep[x]) cxk(res, mx[i][y]), y = par[i][y]; if (x == y) return res; for (int i = 19; ~i; i--) if (par[i][x] != par[i][y]) cxk(res, mx[i][x]), cxk(res, mx[i][y]), x = par[i][x], y = par[i][y]; return max(res, max(mx[0][x], mx[0][y])); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); mst[i] = (MST){u, v, w, i}; ans[i] = 1E9; } sort(mst + 1, mst + 1 + m, [&](const MST &a, const MST &b) { return a.w < b.w; }); for (int i = 1; i <= n; i++) ppar[i] = i; for (int i = 1; i <= m; i++) { int u = mst[i].u, v = mst[i].v; if (find(u) != find(v)) { merge(u, v); ist[mst[i].id] = 1; addedge(u, v, mst[i].w, mst[i].id); addedge(v, u, mst[i].w, mst[i].id); } } for (int i = 0; i < MAXT; i++) mmn[i] = 1E9; dfs(1, 0); for (int i = 1; i < 20; i++) for (int j = 1; j <= n; j++) { par[i][j] = par[i - 1][par[i - 1][j]]; mx[i][j] = max(mx[i - 1][j], mx[i - 1][par[i - 1][j]]); } for (int i = 1; i <= m; i++) if (!ist[mst[i].id]) { int u = mst[i].u, v = mst[i].v; if (beg[u] > beg[v]) swap(u, v); md1[beg[u]].push_back((Mod){beg[v], mst[i].w}); md2[beg[v]].push_back((Mod){beg[u], mst[i].w}); ans[mst[i].id] = calc(u, v); } for (int i = 1; i <= n; i++) { for (Que q : qr1[i]) chk(ans[q.id], ask(q.l, q.r)); for (Mod d : md1[i]) upd(d.p, d.w); } for (int i = 0; i < MAXT; i++) mmn[i] = 1E9; for (int i = n; i > 0; i--) { for (Que q : qr2[i]) chk(ans[q.id], ask(q.l, q.r)); for (Mod d : md2[i]) upd(d.p, d.w); } for (int i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long labs(long long a) { return a < 0 ? (-a) : a; } long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } vector<long long> v; long long Intersect(pair<long long, long long> p1, pair<long long, long long> p2) { pair<long long, long long> res; res.first = max(p1.first, p2.first); res.second = min(p1.second, p2.second); if (res.first > res.second) return 0; return res.second - res.first + 1; } long long Len(pair<long long, long long> p) { return p.second - p.first + 1; } int main() { pair<long long, long long> p1, p2; int k; cin >> p1.first >> p1.second >> p2.first >> p2.second >> k; for (int len = 1; len < 11; len++) { for (long long mask = 0; mask < (1 << len); mask++) { long long a = mask; long long num = 0; for (int(i) = 0; (i) < (len); (i)++) { num = num * 10 + (a % 2 ? 4 : 7); a /= 2; } v.push_back(num); } } v.push_back(0); sort((v).begin(), (v).end()); while (v[v.size() - 2] > 1000000000) v.pop_back(); int i1 = 1; int i2 = k; double res = 0; for (; i2 < v.size() - 1; i1++, i2++) { pair<long long, long long> g1 = make_pair(v[i1 - 1] + 1, v[i1]); pair<long long, long long> g2 = make_pair(v[i2], v[i2 + 1] - 1); res += (double)Intersect(p1, g1) / (double)Len(p1) * (double)Intersect(p2, g2) / (double)Len(p2); res += (double)Intersect(p2, g1) / (double)Len(p2) * (double)Intersect(p1, g2) / (double)Len(p1); if (k == 1) { pair<long long, long long> pc = make_pair(v[i1], v[i1]); res -= (double)Intersect(p2, pc) / (double)Len(p2) * (double)Intersect(p1, pc) / (double)Len(p1); } } printf( %.10f , res); return 0; }
|
// vaziat meshki-ghermeze ! #include <bits/stdc++.h> #define pb push_back #define F first #define S second #define all(x) x.begin(), x.end() #define debug(x) cerr << #x << : << x << n using namespace std; typedef long long ll; typedef long double ld; typedef string str; typedef pair<ll, ll> pll; const ll Mod = 1000000007LL; const int N = 2e5 + 10; const ll Inf = 2242545357980376863LL; const ll Log = 30; pll A[N]; ll dis(ll i, ll j){ return (A[i].F - A[j].F)*(A[i].F - A[j].F) + (A[i].S - A[j].S)*(A[i].S - A[j].S); } ll mk[N]; int main(){ ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; pll mn = {Inf, Inf}; ll idx = -1; for(int i = 1; i <= n; i++){ cin >> A[i].F >> A[i].S; if(A[i] < mn){ mn = A[i]; idx = i; } } cout << idx << ; mk[idx] = 1; for(int i = 2; i <= n; i++){ ll mx = -1; ll id = -1; for(int j = 1; j <= n; j++){ if(mk[j]) continue; if(mx < dis(idx, j)){ mx = dis(idx, j); id = j; } } idx = id; mk[id] = 1; cout << idx << ; } cout << n ; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: rm_hdr.v
// Project: NF2.1
// Description: Removes any headers that might be on the packets
//
///////////////////////////////////////////////////////////////////////////////
module rm_hdr
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
in_data,
in_ctrl,
in_wr,
in_rdy,
out_data,
out_ctrl,
out_wr,
out_rdy,
// --- Misc
reset,
clk
);
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
input in_wr;
output in_rdy;
output [DATA_WIDTH-1:0] out_data;
output [CTRL_WIDTH-1:0] out_ctrl;
output reg out_wr;
input out_rdy;
// --- Misc
input reset;
input clk;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Regs/ wires -----------
reg in_pkt;
wire fifo_wr;
wire almost_full;
wire empty;
// ------------ Modules -------------
// hdr_fifo rm_hdr_fifo
// (
// .din({in_ctrl, in_data}),
// .wr_en(fifo_wr),
//
// .dout({out_ctrl, out_data}),
// .rd_en(out_rdy && !empty),
//
// .empty(empty),
// .full(),
// .almost_full(almost_full),
// .rst(reset),
// .clk(clk)
// ); xCG
hdr_fifo hdr_fifo_inst (
.aclr (reset),
.clock (clk),
.data ({in_ctrl, in_data}),
.rdreq (out_rdy && !empty),
.wrreq (fifo_wr),
.almost_full (almost_full),
.empty (empty),
.full (),
.q ({out_ctrl, out_data})
);
// ------------- Logic ------------
// Work out whether we're in a packet or not
always @(posedge clk) begin
if (reset)
in_pkt <= 1'b0;
else if (in_wr) begin
if (in_pkt && |in_ctrl)
in_pkt <= 1'b0;
else if (!in_pkt && !(|in_ctrl))
in_pkt <= 1'b1;
end
end
assign fifo_wr = in_wr && (!(|in_ctrl) || in_pkt);
always @(posedge clk)
out_wr <= out_rdy && !empty;
assign in_rdy = !almost_full;
endmodule // rm_hdr
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_LP_V
`define SKY130_FD_SC_LP__A22O_LP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_lp (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_lp (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_LP_V
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit #(
parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter enable_clock_gating_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
) (input clk_i
, input reset_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i
, input w_i
, output [`BSG_SAFE_MINUS(width_p, 1):0] data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
,.latch_last_read_p(latch_last_read_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.data_i
,.addr_i
,.v_i
,.w_mask_i
,.w_i
,.data_o
);
// synopsys translate_off
always_ff @(negedge clk_lo)
if (v_i === 1)
assert ((reset_i === 'X) || (reset_i === 1'b1) || (addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", addr_i, els_p, reset_i, v_i, clk_lo);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
#include <bits/stdc++.h> using namespace std; int main() { long sum, i, j; cin >> sum; vector<long> length(3); for (i = 0; i < 3; i++) cin >> length[i]; vector<vector<long> > dp(2, vector<long>(sum + 1, INT_MIN)); dp[3 % 2][0] = 0; for (i = 2; i >= 0; i--) { for (j = 0; j <= sum; j++) { dp[i % 2][j] = dp[(i + 1) % 2][j]; if (j - length[i] >= 0 && dp[i % 2][j - length[i]] != INT_MIN) dp[i % 2][j] = max(dp[i % 2][j], 1 + dp[i % 2][j - length[i]]); } } cout << dp[0][sum]; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long SZ = 107; const long long N = 1e6 + 7; const long long M = 1e4 + 7; long long n, m, c; void solve() { long long n; cin >> n; long long a[n]; vector<long long> b, c; for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long sm1 = 0, sm2 = 0; if (n % 2) { for (long long i = 0; i < n / 2; i++) { b.push_back(a[i]); sm1 += a[i]; } for (long long i = n / 2; i < n; i++) { c.push_back(a[i]); sm2 += a[i]; } } else { for (long long i = 0; i < n / 2; i++) { b.push_back(a[i]); sm1 += a[i]; } for (long long i = n / 2; i < n; i++) { c.push_back(a[i]); sm2 += a[i]; } } cout << sm1 * sm1 + sm2 * sm2 << n ; cout << n ; } signed main() { long long t = 1; for (long long i = 1; i <= t; i++) { solve(); } return 0; }
|
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Firmware/UART/Hardware/UATransmitter.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//==============================================================================
// Section: Includes
//==============================================================================
`include "Const.v"
//==============================================================================
//------------------------------------------------------------------------------
// Module: UATransmitter
// Desc: Standard Universal Asynchronous RS232/16550 type transmitter.
// Params: ClockFreq: Frequency (in Hz) of the "Clock" being fed to this
// module.
// Baud: Desired Baud rate. This is the rate at which this
// module will send bits, and should be at most 1/4th
// of the clock rate (or so).
// Width: Word width (in bits) of the words (bytes) send over
// the serial line.
// Parity: The type of parity bit to be appended to each word of
// data.
// 0: None
// 1: Even
// 2: Odd
// 3: Mark
// 4: Space
// StopBits:The number of bit-periods to send the stop condition.
// Generally 1 or 2, though larger numbers are possible.
// Ex: (27000000, 9600, 8, 0, 1) Standard 9600baud 8-N-1 serial port
// settings used as the default by many devices, based
// on a 27MHz clock.
//------------------------------------------------------------------------------
module UATransmitter(Clock, Reset, DataIn, DataInValid, DataInReady, SOut);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter ClockFreq = 27000000,
Baud = 115200,
Width = 8,
Parity = 0,
StopBits = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Local Parameters
//--------------------------------------------------------------------------
`ifdef MACROSAFE
localparam Divisor = ClockFreq / Baud,
DivWidth = `log2(Divisor),
Capture = (Divisor / 2),
BitCount = Width + StopBits + (Parity ? 1 : 0) + 1,
BCWidth = `log2(BitCount + 1),
ActualBaud = ClockFreq / Divisor;
`endif
`ifdef SIMULATION
localparam real MaxBaud = ClockFreq / ((Divisor * (BitCount - 0.5)) / BitCount),
MinBaud = ClockFreq / ((Divisor * (BitCount + 0.5)) / BitCount);
`endif
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Constant Debugging Statements
//--------------------------------------------------------------------------
`ifdef SIMULATION
initial begin
$display("DEBUG[%m @ %t]: UART Parameters", $time);
$display(" ClockFreq = %d", ClockFreq);
$display(" Baud = %d", Baud);
$display(" Width = %d", Width);
$display(" Parity = %d", Parity);
$display(" StopBits = %d", StopBits);
/*$display(" Divisor = %d", Divisor);
$display(" DivWidth = %d", DivWidth);
$display(" Capture = %d", Capture);
$display(" BitCount = %d", BitCount);
$display(" BCWidth = %d", BCWidth);*/
$display(" ActualBaud = %d", ActualBaud);
$display(" MaxBaud = %f", MaxBaud);
$display(" MinBaud = %f", MinBaud);
end
`endif
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// System Inputs
//--------------------------------------------------------------------------
input Clock, Reset;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Parallel Data Input
//--------------------------------------------------------------------------
input [Width-1:0] DataIn;
input DataInValid;
output DataInReady;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Serial Interface
//--------------------------------------------------------------------------
output SOut;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Wires and Regs
//--------------------------------------------------------------------------
wire IntSOut;
wire [DivWidth-1:0] TxDivCount;
wire [BCWidth-1:0] TxBitCount;
wire [BitCount-1:0] TxData;
wire TxShiftEnable, TxRunning, TxBit, TxStart, TxParity;
wire [BitCount-1:0] DataInAugmented;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Assigns and Decodes
//--------------------------------------------------------------------------
assign TxShiftEnable = (TxDivCount == (Divisor - 1));
assign TxRunning = (TxBitCount < BitCount);
assign TxBit = TxRunning & TxShiftEnable;
assign TxStart = DataInValid & DataInReady;
assign DataInReady = ~TxRunning & ~Reset;
assign DataInAugmented = Parity ? {{StopBits{1'b1}}, TxParity, DataIn, 1'b0} : {{StopBits{1'b1}}, DataIn, 1'b0};
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// IO Register
//--------------------------------------------------------------------------
IORegister IOR( .Clock( Clock),
.Reset( 1'b0),
.Set( 1'b0),
.Enable( 1'b1),
.In( IntSOut),
.Out( SOut));
defparam IOR.Width = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Clock Divider Counter
//--------------------------------------------------------------------------
Counter TxDivCounter(.Clock( Clock),
.Reset( Reset | (TxDivCount == (Divisor-1)) | TxStart),
.Set( 1'b0),
.Load( 1'b0),
.Enable( 1'b1),
.In( {DivWidth{1'bx}}),
.Count( TxDivCount));
defparam TxDivCounter.Width = DivWidth;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Bit Counter
//--------------------------------------------------------------------------
Counter TxBitCounter(.Clock( Clock),
.Reset( TxStart),
.Set( Reset),
.Load( 1'b0),
.Enable( TxBit),
.In( {BCWidth{1'bx}}),
.Count( TxBitCount));
defparam TxBitCounter.Width = BCWidth;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Shift Register and Bit Reversal
//--------------------------------------------------------------------------
ShiftRegister TxShift( .PIn( Reset ? {BitCount{1'b1}} : TxData),
.SIn( 1'b1),
.POut( ),
.SOut( IntSOut),
.Load( TxStart | Reset),
.Enable( TxShiftEnable),
.Clock( Clock),
.Reset( 1'b0));
defparam TxShift.PWidth = BitCount;
defparam TxShift.SWidth = 1;
Reverse TxReverse( .In( DataInAugmented),
.Out( TxData));
defparam TxReverse.Width = BitCount;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Parity Generator
//--------------------------------------------------------------------------
ParityGen TxParityGen(.In( DataIn),
.Out( TxParity));
defparam TxParityGen.Width = Width;
defparam TxParityGen.Parity = Parity;
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int M = 998244353; struct modint { int val = 0; modint() {} modint(int a) : val(a) { while (val < 0) { val += M; } while (val >= M) { val -= M; } } modint(long long a) : val(a % M) { if (val < 0) { val += M; } } modint operator+=(modint oth) { val += oth.val; val -= (val >= M) ? M : 0; return *this; } modint operator-=(modint oth) { val -= oth.val; val += (val < 0) ? M : 0; return *this; } modint operator*=(modint oth) { val = 1LL * val * oth.val % M; return *this; } void operator++() { ++val; if (val == M) { val = 0; } } void operator--() { --val; if (val == -1) { val = M - 1; } } modint operator-() { modint res; res.val = (val == 0) ? 0 : M - val; return res; } int mod() { return M; } modint pow(long long e) { modint base = val; modint res = 1; while (e > 0) { if (e % 2 == 1) { res *= base; } base *= base; e /= 2; } return res; } modint inv() { return pow(M - 2); } friend modint operator+(modint a, modint b) { return modint(a) += b; } friend modint operator-(modint a, modint b) { return modint(a) -= b; } friend modint operator*(modint a, modint b) { return modint(a) *= b; } friend bool operator==(modint a, modint b) { return a.val == b.val; } friend bool operator!=(modint a, modint b) { return a.val != b.val; } }; using mint = modint; void ntt(vector<mint> &a) { int n = a.size(); for (int i = 1, j = 0; i < n; ++i) { int k = n / 2; while ((j & k) > 0) { j ^= k; k /= 2; } j ^= k; if (i < j) { swap(a[i], a[j]); } } mint base = mint(3).pow((M - 1) / n); for (int len = 2; len <= n; len *= 2) { mint root = base.pow(n / len); for (int i = 0; i < n; i += len) { mint cur = 1; for (int j = 0; j < len / 2; ++j) { mint l = a[i + j]; mint r = a[i + j + len / 2] * cur; a[i + j] = l + r; a[i + j + len / 2] = l - r; cur *= root; } } } } vector<mint> mul(const vector<mint> &u, const vector<mint> &v) { int n = 1; while (n < int(u.size() + v.size())) { n *= 2; } vector<mint> a(u.begin(), u.end()); vector<mint> b(v.begin(), v.end()); a.resize(n); b.resize(n); ntt(a); ntt(b); for (int i = 0; i < n; ++i) { a[i] *= b[i]; } ntt(a); mint inv = mint(n).inv(); for (mint &i : a) { i *= inv; } reverse(a.begin() + 1, a.end()); return a; } void solve() { int n; string s; cin >> n >> s; vector<mint> v(n), k(n); for (int i = 0; i < n; ++i) { if (s[i] == V ) { v[i] = 1; } else if (s[i] == K ) { k[n - 1 - i] = 1; } } vector<bool> bad(n + 1); vector<mint> vk = mul(v, k); for (int i = 0; i < 2 * n; ++i) { if (vk[i] != 0) { bad[abs(n - 1 - i)] = true; } } vector<int> ans; for (int i = 1; i <= n; ++i) { bool good = true; for (int j = i; j <= n; j += i) { good &= !bad[j]; } if (good) { ans.push_back(i); } } cout << ans.size() << n ; for (auto i : ans) { cout << i << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { long n, d, a[100000], diff; long sum = 0; cin >> n >> d; for (long i = 0; i < n; i++) cin >> a[i]; for (long i = 1; i < n; i++) { if (a[i - 1] >= a[i]) { diff = a[i - 1] - a[i]; a[i] = a[i] + (diff / d + 1) * d; sum = sum + diff / d + 1; } } cout << sum; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long A, B, N; long long l, t, m; int main() { cin >> A >> B >> N; for (int i = 0; i < N; i++) { cin >> l >> t >> m; if (t < A + (l - 1) * B) { cout << -1 << endl; } else { long long left = l, right = (t - A) / B + 1; while (left <= right) { long long mid = (left + right) / 2; long long sum = (mid - l + 1) * (2 * A + B * (mid + l) - 2 * B) / 2; if (sum <= m * t) { left = mid + 1; } else { right = mid - 1; } } cout << right << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef pair<long long, long long> ll; typedef vector<long long> vl; typedef vector<ll> vll; typedef vector<vl> vvl; template <typename T> ostream &operator<<(ostream &o, vector<T> v) { if (v.size() > 0) o << v[0]; for (unsigned i = 1; i < v.size(); i++) o << << v[i]; return o << ; } template <typename U, typename V> ostream &operator<<(ostream &o, pair<U, V> p) { return o << ( << p.first << , << p.second << ) ; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (unsigned i = 0; i < v.size(); i++) in >> v[i]; return in; } template <typename T> istream &operator>>(istream &in, pair<T, T> &p) { in >> p.first; in >> p.second; return in; } template <typename T> ostream &operator<<(ostream &o, set<T> v) { for (auto &it : v) o << it << ; return o << n ; } template <typename T, typename U> ostream &operator<<(ostream &o, map<T, U> v) { for (auto &it : v) o << it << ; return o << n ; } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; int main(int argc, char *argv[]) { long long n, d; cin >> n >> d; vl a(n); cin >> a; long long m; cin >> m; sort((a).begin(), (a).end()); if (m <= n) { long long res = 0; for (long long i = (0); i < (long long)m; i++) res += a[i]; cout << res; } else { long long sum = accumulate((a).begin(), (a).end(), 0LL); cout << sum - (m - n) * d; } return 0; }
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#include <bits/stdc++.h> using namespace std; class IntTree { public: IntTree(int size) : nodes_(4 * size + 10, 0), size_(size) {} void Set(int pos, char ch) { Set(0, 1, size_, pos, ch); } int Count(int left, int right) { int mask = Mask(0, 1, size_, left, right); return CountBits(mask); } private: static int Left(int node) { return 2 * node + 1; } static int Right(int node) { return 2 * node + 2; } static int CountBits(int num); void Set(int node, int left, int right, int pos, char ch); int Mask(int node, int left, int right, int x, int y); vector<int> nodes_; int size_; }; int IntTree::CountBits(int num) { int count = 0; while (num > 0) { count += 1; num -= (num & -num); } return count; } void IntTree::Set(int node, int left, int right, int pos, char ch) { if (left == right) { nodes_[node] = (1 << (ch - a )); return; } int mid = left + (right - left) / 2; if (pos <= mid) { Set(Left(node), left, mid, pos, ch); } else { Set(Right(node), mid + 1, right, pos, ch); } nodes_[node] = (nodes_[Left(node)] | nodes_[Right(node)]); } int IntTree::Mask(int node, int left, int right, int x, int y) { if (x <= left && right <= y) { return nodes_[node]; } int mask = 0; int mid = left + (right - left) / 2; if (x <= mid) { mask |= Mask(Left(node), left, mid, x, y); } if (mid < y) { mask |= Mask(Right(node), mid + 1, right, x, y); } return mask; } int main() { string str; getline(cin, str); IntTree tree(str.size()); for (size_t i = 0; i < str.size(); i += 1) { tree.Set(i + 1, str[i]); } int queries; cin >> queries; for (int i = 0; i < queries; i += 1) { int type, x, y; char ch; cin >> type; if (type == 1) { cin >> x >> ch; tree.Set(x, ch); } else { cin >> x >> y; cout << tree.Count(x, y) << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; double pa[2020], pb[2020], pab[2020]; int n, a, b; double dp[2020]; int opt[2020]; pair<int, int> solve(double mida, double midb) { dp[0] = 0; opt[0] = 0; for (int i = 1; i <= n; i++) { double& d = dp[i]; int& o = opt[i]; d = dp[i - 1]; o = 0; if (d < dp[i - 1] + pa[i] - mida) { d = dp[i - 1] + pa[i] - mida; o = 1; } if (d < dp[i - 1] + pb[i] - midb) { d = dp[i - 1] + pb[i] - midb; o = 2; } if (d < dp[i - 1] + pab[i] - mida - midb) { d = dp[i - 1] + pab[i] - mida - midb; o = 3; } } pair<int, int> ans = make_pair(0, 0); for (int i = 1; i <= n; i++) { if (opt[i] & 1) { ans.first++; } if (opt[i] > 1) { ans.second++; } } return ans; } int main() { scanf( %d %d %d , &n, &a, &b); for (int i = 1; i <= n; i++) { scanf( %lf , &pa[i]); } for (int i = 1; i <= n; i++) { scanf( %lf , &pb[i]); } for (int i = 1; i <= n; i++) { pab[i] = pa[i] + pb[i] - pa[i] * pb[i]; } double lowa = 0, higha = 1; double lowb = 0, highb = 1; for (int it = 0; it < 100; it++) { double mida = (lowa + higha) / 2; lowb = 0; highb = 1; for (int itb = 0; itb < 100; itb++) { double midb = (lowb + highb) / 2; auto ans = solve(mida, midb); if (ans.second > b) { lowb = midb; } else { highb = midb; } } auto ans = solve(mida, highb); if (ans.first > a) { lowa = mida; } else { higha = mida; } } auto ret = solve(higha, highb); printf( %.10lf n , dp[n] + lowa * a + lowb * b); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); vector<pair<int, int>> vec; int n, a, b; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; if (a != b) { cout << rated ; return 0; } vec.push_back({a, b}); } for (int i = 0; i < vec.size() - 1; i++) { if (vec[i].first < vec[i + 1].first) { cout << unrated ; return 0; } } cout << maybe ; }
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#include <bits/stdc++.h> using namespace std; int read() { char ch = getchar(); int f = 0, x = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) x = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { f = (f << 1) + (f << 3) + ch - 0 ; ch = getchar(); } return f * x; } int ch[2000005][2], fa[2000005], w[2000005], mark[2000005]; int f[2000005], top, s[2000005], n, k, m; bool rev[2000005]; bool isroot(int x) { return ch[fa[x]][0] != x && ch[fa[x]][1] != x; } void pushdown(int x) { if (rev[x]) { rev[ch[x][0]] ^= 1; rev[ch[x][1]] ^= 1; swap(ch[x][0], ch[x][1]); rev[x] = 0; } if (mark[x]) { mark[ch[x][0]] = min(mark[ch[x][0]], mark[x]); mark[ch[x][1]] = min(mark[ch[x][1]], mark[x]); w[ch[x][0]] = min(w[ch[x][0]], mark[x]); w[ch[x][1]] = min(w[ch[x][1]], mark[x]); mark[x] = 2000000000; } } void rotate(int x) { int y = fa[x], z = fa[y], l, r; if (ch[y][0] == x) l = 0; else l = 1; r = l ^ 1; if (!isroot(y)) { if (ch[z][0] == y) ch[z][0] = x; else ch[z][1] = x; } fa[y] = x; fa[x] = z; fa[ch[x][r]] = y; ch[y][l] = ch[x][r]; ch[x][r] = y; } void splay(int x) { top = 0; s[++top] = x; for (int i = x; !isroot(i); i = fa[i]) s[++top] = fa[i]; while (top) pushdown(s[top--]); while (!isroot(x)) { int y = fa[x], z = fa[y]; if (!isroot(y)) { if (ch[z][0] == y ^ ch[y][0] == x) rotate(x); else rotate(y); } rotate(x); } } void access(int x) { for (int t = 0; x; t = x, x = fa[x]) { splay(x); ch[x][1] = t; } } void makeroot(int x) { access(x); splay(x); rev[x] ^= 1; } void link(int x, int y) { makeroot(x); fa[x] = y; } int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } void dfs(int x) { if (ch[x][0] && !isroot(ch[x][0])) { mark[ch[x][0]] = min(mark[ch[x][0]], mark[x]); w[ch[x][0]] = min(w[ch[x][0]], mark[x]); dfs(ch[x][0]); } if (ch[x][1] && !isroot(ch[x][1])) { mark[ch[x][1]] = min(mark[ch[x][1]], mark[x]); w[ch[x][1]] = min(w[ch[x][1]], mark[x]); dfs(ch[x][1]); } } int main() { memset(w, 0x7f7f7f7f, sizeof(w)); memset(mark, 0x7f7f7f7f, sizeof(mark)); n = read(); k = read(); m = read(); for (int i = 1; i <= n; i++) { f[i] = i; } for (int i = 1; i <= k; i++) { int u = read(), v = read(); link(u, n + i); link(n + i, v); f[find(u)] = find(v); } for (int i = 1; i <= m; i++) { int u = read(), v = read(), w1 = read(); int fu = find(u), fv = find(v); if (fu == fv) { makeroot(u); access(v); splay(v); mark[v] = min(mark[v], w1); w[v] = min(w[v], w1); } else { link(u, i + k + n); link(i + k + n, v); f[fu] = fv; } } long long ans = 0; for (int i = 1; i <= n + k + m; i++) { if (isroot(i)) { dfs(i); } } for (int i = 1; i <= k; i++) { if (w[i + n] >= 2000000000) { puts( -1 ); return 0; } ans += w[i + n]; } cout << ans; }
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`timescale 1 ns / 1 ps
`include "Video_PR_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_MAX_BURST_LENGTH 1
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_ADDRESS_BUS_WIDTH 32
`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8
module Video_PR_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S_AXI AXI4 Lite Local Reg
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_rd_data_lite;
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S_AXI_lite_response;
reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
reg [3-1:0] S_AXI_mtestProtection_lite;
integer S_AXI_mtestvectorlite; // Master side testvector
integer S_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S_AXI_mtestvectorlite = 0;
S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
S_AXI_mtestProtection_lite = 0;
S_AXI_mtestdatasizelite = `S_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S_AXI_mtestvectorlite = 0; S_AXI_mtestvectorlite <= 3; S_AXI_mtestvectorlite = S_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_test_data_lite[S_AXI_mtestvectorlite],
S_AXI_mtestdatasizelite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_rd_data_lite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_rd_data_lite,S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
COMPARE_LITE_DATA(S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_mtestvectorlite,S_AXI_mtestvectorlite);
S_AXI_mtestAddress = S_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_test_data_lite[0] = 32'h0101FFFF;
S_AXI_test_data_lite[1] = 32'habcd0001;
S_AXI_test_data_lite[2] = 32'hdead0011;
S_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_TEST();
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr;
reg r_reset_n;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
last_test_expr <= test_expr;
// check second clock after reset
if (r_reset_n && (last_test_expr != test_expr)) begin
temp_expr = {1'b0,last_test_expr} - {1'b0,test_expr};
// 2's complement result
if (temp_expr[width-1:0] != value) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is decreased by a value other than specified");
end
end
end
else begin
r_reset_n <= 0;
`ifdef OVL_INIT_REG
last_test_expr <= {width{1'b0}};
temp_expr = {(width+1){1'b0}};
`endif
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
module first_nns_seq
#
(
parameter W = 15
)
(
clk,
rst,
g_input,
e_input,
o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2=0; temp>0; log2=log2+1)
temp = temp>>1;
end
endfunction
localparam LOGW = log2(W);
input clk;
input rst;
input [W-1:0] g_input;
input [W-1:0] e_input;
output [W-1:0] o;
wire [LOGW-1:0] dist;
wire [W-1:0] min_val;
wire [LOGW-1:0] min_dist;
wire gt_dist;
reg [W-1:0] min_val_reg;
reg [LOGW-1:0] min_dist_reg;
COUNT
#(
.N(W)
)
COUNT_
(
.A(g_input ^ DBi),
.S(dist)
);
COMP
#(
.N(LOGW)
)
COMP_
(
.A(min_dist_reg),
.B(dist),
.O(gt_dist)
);
MUX
#(
.N(W)
)
MUX_1
(
.A(e_input),
.B(min_val_reg),
.S(gt_dist),
.O(min_val)
);
MUX
#(
.N(LOGW)
)
MUX_2
(
.A(dist),
.B(min_dist_reg),
.S(gt_dist),
.O(min_dist)
);
//assign min_val = (gt_dist)? e_input :min_val_reg;
//assign min_dist = (gt_dist)? dist :min_dist_reg;
assign o = min_val;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
min_val_reg <= 0;
min_dist_reg <= {LOGW{1'b1}};
end
else
begin
min_val_reg <= min_val;
min_dist_reg <= min_dist;
end
end
endmodule
|
// megafunction wizard: %LPM_CONSTANT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_constant
// ============================================================
// File Name: lpm_constant4.v
// Megafunction Name(s):
// lpm_constant
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module lpm_constant4 (
result);
output [0:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "SWAP"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Value NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=SWAP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL result[0..0]
// Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:49:29 11/17/2015
// Design Name: bit_ctrl
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/I2C_Module/bit_ctr2l_tst.v
// Project Name: I2C_Module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bit_ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bit_ctr2l_tst;
// Inputs
reg clk;
reg clk_frame;
reg rst;
reg en;
reg rw;
reg w_bit;
reg start_cond;
reg stop_cond;
// Outputs
wire r_bit;
wire busy;
wire SCL;
// Bidirs
wire SDA;
reg SDA_in, SDA_out, SDA_oen;
assign SDA = SDA_oen? 1'bz : SDA_out;
// Instantiate the Unit Under Test (UUT)
bit_ctrl uut (
.clk(clk),
.clk_frame(clk_frame),
.rst(rst),
.en(en),
.rw(rw),
.w_bit(w_bit),
.start_cond(start_cond),
.stop_cond(stop_cond),
.r_bit(r_bit),
.busy(busy),
.SDA(SDA),
.SCL(SCL)
);
initial begin
// Initialize Inputs
clk = 0;
clk_frame = 0;
rst = 1;
en = 0;
rw = 0;
w_bit = 0;
start_cond = 0;
stop_cond = 0;
SDA_oen = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
#15;
en = 1;
start_cond = 1;
while(!busy) #10;
en = 0;
start_cond = 0;
end
always #5 clk = ~clk;
always #55 clk_frame = ~clk_frame;
endmodule
|
#include <bits/stdc++.h> using namespace std; using Point = complex<int>; using ll = long long; ll cross(Point a, Point b) { return 1LL * a.real() * b.imag() - 1LL * b.real() * a.imag(); } ll det(Point a, Point b, Point c) { return cross(b - a, c - a); } namespace std { bool operator<(const Point& a, const Point& b) { return make_pair(a.real(), a.imag()) < make_pair(b.real(), b.imag()); } } // namespace std struct DynHull { struct Node { int bl, br, l, r, lc, rc; }; vector<Node> T = {{-1, -1, -1, -1, 0, 0}}; vector<Point> P; DynHull(vector<Point> P) : P(P) {} bool leaf(int x) { return T[x].l == T[x].r; } int combine(int lc, int rc, int ret = -1) { if (!lc || !rc) return lc + rc; if (ret == -1 || ret == lc || ret == rc) ret = T.size(), T.push_back({}); T[ret] = {-1, -1, T[lc].l, T[rc].r, lc, rc}; while (!leaf(lc) || !leaf(rc)) { int a = T[lc].bl, b = T[lc].br, c = T[rc].bl, d = T[rc].br; if (a != b && det(P[a], P[b], P[c]) > 0) { lc = T[lc].lc; } else if (c != d && det(P[b], P[c], P[d]) > 0) { rc = T[rc].rc; } else if (a == b) { rc = T[rc].lc; } else if (c == d) { lc = T[lc].rc; } else { auto s1 = det(P[a], P[b], P[c]), s2 = det(P[a], P[b], P[d]); assert(s1 >= s2); auto xc = P[c].real(), xd = P[d].real(), xm = P[T[rc].l].real(); if (s1 == s2 || s1 * xd - s2 * xc < (s1 - s2) * xm) { lc = T[lc].rc; } else { rc = T[rc].lc; } } } T[ret].bl = T[lc].l; T[ret].br = T[rc].l; return ret; } int Build(int b, int e) { if (e - b == 1) { T.push_back({b, b, b, b, 0, 0}); return T.size() - 1; } int m = (b + e) / 2; return combine(Build(b, m), Build(m, e)); } int Erase(int x, int pos) { if (!x || T[x].r < pos || T[x].l > pos) return x; return leaf(x) ? 0 : combine(Erase(T[x].lc, pos), Erase(T[x].rc, pos), x); } template <typename Callback> void Hull(int x, Callback&& cb, int l = 0, int r = 1e9) { if (!x || l > r) return; if (leaf(x)) { cb(T[x].l); return; } Hull(T[x].lc, cb, l, min(r, T[x].bl)); Hull(T[x].rc, cb, max(l, T[x].br), r); } }; inline ll area(Point a, Point b, Point c) { return (ll)(b.real() - a.real()) * (c.imag() - a.imag()) - (ll)(b.imag() - a.imag()) * (c.real() - a.real()); } vector<Point> convexHull(vector<Point> p) { int n = p.size(), m = 0; if (n < 3) return p; vector<Point> hull(n + n); sort(p.begin(), p.end()); for (int i = 0; i < n; ++i) { while (m > 1 and area(hull[m - 2], hull[m - 1], p[i]) <= 0) --m; hull[m++] = p[i]; } for (int i = n - 2, j = m + 1; i >= 0; --i) { while (m >= j and area(hull[m - 2], hull[m - 1], p[i]) <= 0) --m; hull[m++] = p[i]; } hull.resize(m - 1); return hull; } const int LG = 18; const int N = 100010; int q, par[LG][N]; inline int prv(int i, int n) { return (i ? i : n) - 1; } inline int nxt(int i, int n) { return i + 1 < n ? i + 1 : 0; } int kthPar(int u, int k) { for (int i = LG - 1; i >= 0; --i) { assert(u != -1); if (k & 1 << i) k ^= 1 << i, u = par[i][u]; } return u; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<pair<Point, int>> pts(n); map<Point, int> id; for (int i = 0; i < n; ++i) { int x, y; cin >> x >> y; pts[i] = make_pair(Point{x, y}, i); id[Point{x, y}] = i; } if (n == 1) { cin >> q; while (q--) cout << 1 << n ; return 0; } vector<pair<Point, int>> pts_copy = pts; sort(pts.begin(), pts.end()); vector<Point> P(n); vector<int> remap(n); for (int i = 0; i < n; ++i) { remap[i] = pts[i].second; P[i] = pts[i].first; } auto LH = DynHull(P); int lh = LH.Build(0, n); for (int i = 0; i < n; ++i) P[i] = -P[i]; reverse(P.begin(), P.end()); auto UH = DynHull(P); int uh = UH.Build(0, n); vector<int> layer(n, -1); for (int i = 0;; ++i) { vector<int> all; LH.Hull(lh, [&](int x) { all.push_back(x); }); UH.Hull(uh, [&](int x) { all.push_back(n - x - 1); }); if (all.empty()) break; for (auto x : all) { lh = LH.Erase(lh, x); uh = UH.Erase(uh, n - x - 1); layer[remap[x]] = i; } } int up = *max_element(layer.begin(), layer.end()) + 1; vector<vector<Point>> layers(up); for (int i = 0; i < n; ++i) { layers[layer[i]].emplace_back(pts_copy[i].first); } for (int i = 0; i < up; ++i) layers[i] = convexHull(layers[i]); vector<int> pf(up); for (int i = 0; i < up; ++i) { pf[i] = layers[i].size(); if (i) pf[i] += pf[i - 1]; } vector<int> whichLayer(n), whichPos(n); for (int i = 0; i < up; ++i) { for (int j = 0; j < layers[i].size(); ++j) { auto x = layers[i][j]; whichLayer[id[x]] = i, whichPos[id[x]] = j; } } memset(par, -1, sizeof par); for (int i = 0; i + 1 < up; ++i) { if (layers[i + 1].size() == 1) { int to = id[layers[i + 1][0]]; for (auto x : layers[i]) par[0][id[x]] = to; continue; } int k = 0, sz = layers[i + 1].size(); vector<int> to(layers[i].size()); for (int j = 0; j < layers[i].size(); ++j) { while (area(layers[i][j], layers[i + 1][k], layers[i + 1][nxt(k, sz)]) < 0) k = nxt(k, sz); while (area(layers[i][j], layers[i + 1][prv(k, sz)], layers[i + 1][k]) > 0) k = prv(k, sz); to[j] = k; } for (int j = 0; j < layers[i].size(); ++j) { int u = id[layers[i][j]], v = id[layers[i + 1][to[prv(j, layers[i].size())]]]; par[0][u] = v; } } for (auto x : layers[up - 1]) par[0][id[x]] = n; for (int j = 1; j < LG; ++j) { for (int i = 0; i <= n; ++i) if (par[j - 1][i] != -1) { par[j][i] = par[j - 1][par[j - 1][i]]; } } int sz = layers[0].size(); vector<pair<long double, int>> vec; for (int i = 0; i < sz; ++i) { Point cur = layers[0][nxt(i, sz)] - layers[0][i]; vec.emplace_back(atan2l(cur.imag(), cur.real()), i); } sort(vec.begin(), vec.end()); cin >> q; while (q--) { int dx, dy, k; cin >> dx >> dy >> k; long double ang = atan2l(dy, dx); int pos = -1; auto it = upper_bound(vec.begin(), vec.end(), make_pair(ang, 696969)); if (it == vec.end()) pos = vec[0].second; else pos = it->second; int where = lower_bound(pf.begin(), pf.end(), k) - pf.begin(); int ext = k - (where ? pf[where - 1] : 0); int at = kthPar(id[layers[0][pos]], where); assert(at != n); int final = (whichPos[at] + ext - 1) % (int)layers[where].size(); int ans = id[layers[where][final]]; printf( %d n , ans + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, a[55], P; double dp[55][55][55]; double fac(int n) { double ans = 1; for (int i = 0; i < (n); i++) ans *= (i + 1); return ans; } int main(int argc, char *argv[]) { scanf( %d , &N); for (int i = 0; i < (N); i++) scanf( %d , a + i); scanf( %d , &P); dp[0][0][0] = 1; for (int i = 0; i < (N); i++) for (int in = (0); in <= (N); in++) for (int p = (0); p <= (P); p++) if (dp[i][in][p]) { dp[i + 1][in][p] += dp[i][in][p]; if (p + a[i] <= P) dp[i + 1][in + 1][p + a[i]] += dp[i][in][p]; } double tmp = 0, ans = 0, sum; for (int in = (N); in >= (0); in--) { sum = 0; for (int p = (0); p <= (P); p++) sum += dp[N][in][p]; sum *= fac(in) * fac(N - in); ans += in * (sum - tmp); tmp = sum; } printf( %.9lf n , ans / fac(N)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, OO = 0x3f3f3f3f; const int mod = 1e9 + 7; int a[60][60]; int ans[60]; bool done[60]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { scanf( %d , &a[i][j]); } } for (int i = 1; i <= n; i++) { done[i] = false; } for (int x = 1; x <= n; x++) { for (int i = 1; i <= n; i++) { if (done[i]) continue; bool good = true; for (int j = 1; j <= n; j++) { good = good && (a[i][j] <= x); } if (good) { ans[i] = x; done[i] = true; break; } } } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); puts( ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off MULTIDRIVEN
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [15:0] out2; // From test of Test.v
// End of automatics
// verilator lint_on MULTIDRIVEN
Test test (
.en (crc[21:20]),
.a1 (crc[19:18]),
.a0 (crc[17:16]),
.d1 (crc[15:8]),
.d0 (crc[7:0]),
/*AUTOINST*/
// Outputs
.out (out[31:0]),
.out2 (out2[15:0]),
// Inputs
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {out2, 16'h0, out};
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
test.clear();
end
else if (cyc<10) begin
sum <= 64'h0;
test.clear();
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, en, a0, a1, d0, d1
);
input clk;
input [1:0] en;
input [1:0] a0;
input [1:0] a1;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN
task clear();
for (int i=0; i<4; ++i) mem[i] = 0;
endtask
always @(posedge clk) begin
if (en[0]) begin
mem[a0] <= d0;
out2[7:0] <= d0;
end
end
always @(negedge clk) begin
if (en[1]) begin
mem[a1] <= d1;
out2[15:8] <= d0;
end
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (a == b) cout << a << endl; else cout << 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; double p = 0, x = 0, m, n, i; cin >> m >> n; for (i = m; i >= 1; i--) { p += (1 - pow(((i - 1) / m), n) - x) * i; x += 1 - pow(((i - 1) / m), n) - x; } cout << fixed << setprecision(12) << p; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:39 11/19/2015
// Design Name:
// Module Name: ID_EX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ID_EX(
input clock,
input reset,
input syncClr,
input [4:0] rs,
input [4:0] rt,
input [4:0] rd,
input [4:0] sa,
input [3:0] aluOperation,
input [31:0] sigExt,
input [31:0] readData1,
input [31:0] readData2,
input aluSrc,
input aluShiftImm,
input regDst,
input loadImm,
input [3:0]memWrite,
input memToReg,
input[1:0] memReadWidth,
input regWrite,
output reg [3:0] aluOperationOut,
output reg [31:0] sigExtOut,
output reg [31:0] readData1Out,
output reg [31:0] readData2Out,
output reg aluSrcOut,
output reg aluShiftImmOut,
output reg [3:0]memWriteOut,
output reg memToRegOut,
output reg[1:0] memReadWidthOut,
output reg[4:0] rsOut,
output reg[4:0] rtOut,
output reg[4:0] rdOut,
output reg[4:0] saOut,
output reg regDstOut,
output reg loadImmOut,
output reg regWriteOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
aluOperationOut<=0;
sigExtOut<=0;
readData1Out<=0;
readData2Out<=0;
aluSrcOut<=0;
aluShiftImmOut<=0;
memWriteOut<=0;
memToRegOut<=0;
memReadWidthOut<=0;
regWriteOut<=0;
rsOut<=0;
rtOut<=0;
rdOut<=0;
saOut<=0;
regDstOut<=0;
loadImmOut<=0;
end
else if(syncClr)begin
aluOperationOut<=0;
sigExtOut<=0;
readData1Out<=0;
readData2Out<=0;
aluSrcOut<=0;
aluShiftImmOut<=0;
memWriteOut<=0;
memToRegOut<=0;
memReadWidthOut<=0;
regWriteOut<=0;
rsOut<=0;
rtOut<=0;
rdOut<=0;
saOut<=0;
regDstOut<=0;
loadImmOut<=0;
end
else begin
aluOperationOut<=aluOperation;
sigExtOut<=sigExt;
readData1Out<=readData1;
readData2Out<=readData2;
aluSrcOut<=aluSrc;
aluShiftImmOut<=aluShiftImm;
memWriteOut<=memWrite;
memToRegOut<= memToReg;
memReadWidthOut<=memReadWidth;
regWriteOut<=regWrite;
rsOut<=rs;
rtOut<=rt;
rdOut<=rd;
saOut<=sa;
regDstOut<=regDst;
loadImmOut<=loadImm;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_4_V
`define SKY130_FD_SC_HD__A2111OI_4_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_4_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1200; int x, y; bool run() { bool fox = true; while (1) { if (fox) { if (x == 0) { if (y >= 22) { y -= 22; } else { return false; } } else if (x == 1) { if (y >= 12) { y -= 12; } else { return false; } } else { if (y >= 2) { x -= 2; y -= 2; } else { return false; } } } else { if (y >= 22) { y -= 22; } else if (y >= 12) { y -= 12; if (x == 0) { return true; } else { x--; } } else if (y >= 2) { y -= 2; if (x < 2) { return true; } else { x -= 2; } } else { return true; } } fox ^= 1; } return false; } int main() { scanf( %d%d , &x, &y); if (run()) { puts( Ciel ); } else { puts( Hanako ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:64000000 ) int prec[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; const int mod = 1000000000 + 7; int n, k; long long doIt(int m, int bse) { int b[10]; for (int i = 0; i < 10; i++) b[i] = 0; int res = 0; while (!b[m]) { int can = true; for (int i = 0; i < m && can; i++) { int cur = i; int iter = m + 1; while (iter && cur) { cur = b[cur]; iter--; } can &= (cur == 0); } if (can) res++; int ind = 0; b[ind]++; while (b[ind] >= bse) { b[ind] = 0; ind++; b[ind]++; } } return res % mod; } int main() { cin >> n >> k; k = min(k, 8); long long res = 1; if (k > 1) res = doIt(k, k) % mod; for (int i = 0; i < n - k; i++) { res = res * 1LL * (n - k); res %= mod; } cout << res << endl; return 0; }
|
// This counter is a one hot counter; so exactly one output bit is set at all times.
// For example if the value of the counter is zero, then bit 0 will be set.
// This counter makes it extremely fast to detect whether the counter is a particular value.
// The logic is relatively expensive, since it scales with the number of values the counter can take on.
// It is most sensible when you need a decoder to select items in an array, and your access pattern through
// that array is sequential. It will minimize critical paths, and the cost is amortized because the
// alternative is a binary counter and a decoder.
//
// The interface of this counter is analogous to bsg_counter_clear_up:
//
// - the reset_i signal ensures that output to init_val_p; default is 2's complement 0 regardless of up_i or clear_i
// - the clear_i signal sets the 2's complement value to 0 (i.e. all bits except low bit are 0; low bit is 1)
// - the up_i signal increments the counter (corresponds to left rotate). it stacks on top of the clear_i
// so it is legal for the user to assert both clear_i and up_i simultaneous and the effects of both to be reflected.
//
`include "bsg_defines.v"
module bsg_counter_clear_up_one_hot
#(parameter `BSG_INV_PARAM(max_val_p), width_lp=max_val_p+1, init_val_p=(width_lp) ' (1))
(input clk_i
,input reset_i
,input clear_i
,input up_i
,output [width_lp-1:0] count_r_o
);
logic [width_lp-1:0] bits_r, bits_n;
always_comb
begin
bits_n = bits_r;
if (clear_i)
bits_n = (width_lp) ' (1);
// increment is a rotate operator
if (up_i)
bits_n = { bits_n[width_lp-2:0], bits_n[width_lp-1] };
if (reset_i)
bits_n = (width_lp) ' (init_val_p);
end
// clock gate, hopefully
always_ff @(posedge clk_i)
if (reset_i | up_i | clear_i)
bits_r <= bits_n;
assign count_r_o = bits_r;
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_clear_up_one_hot)
|
#include <bits/stdc++.h> using namespace std; void ins(long long int a[], long long int n, long long int i = 0) { for (long long int i = 0; i < n; i++) a[i] = i; } template <typename t> void ins(t a[], long long int n, t b = 0) { for (long long int i = 0; i < n; i++) a[i] = b; } void print(long long int a[], long long int n) { for (long long int i = 0; i < n; i++) cout << a[i] << ; ; cout << endl; } template <typename t> void print(t a[], long long int n) { for (long long int i = 0; i < n; i++) cout << a[i] << ; ; cout << endl; } void po(long long int a[], long long int n) { for (long long int i = 0; i < n; i++) { cin >> a[i]; } } template <typename t> void po(t a[], long long int n) { for (long long int i = 0; i < n; i++) { cin >> a[i]; } } long long int visited[100009]; vector<long long int> a[100009]; long long int n; long long int b[100009]; long long int c[100001]; void start() { cin >> n; for (long long int i = 0; i < n - 1; i++) { cin >> b[i + 1]; a[i + 2].push_back(b[i + 1]); a[b[i + 1]].push_back(i + 2); } for (long long int i = 0; i < n + 3; i++) { visited[i] = 0; c[i] = 0; } } void dfs(long long int s, long long int t) { visited[s] = 1; if (s != 1) c[t + 1] += a[s].size() - 1; else c[t + 1] += a[s].size(); for (long long int i = 0; i < a[s].size(); i++) { if (!visited[a[s][i]]) dfs(a[s][i], t + 1); } } int main() { start(); long long int count = 0; dfs(1, 0); for (long long int i = 0; i < n + 3; i++) { if (c[i] % 2 == 1) { count++; } } cout << count + 1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_BLACKBOX_V
|
/* Is not working :-( */
`include "DEF.v"
/*
module icachel2(address, data, read, out_address, out_data, out_read);
input [31:0] address;
input [127:0] out_data;
output [127:0] data;
output [31:0] out_address;
input read;
output out_read;
reg [127:0] icache [12'hFFF:0];
reg [31:0] tag [12'hFFF:0];
reg [127:0] r_data;
reg [31:0] r_out_address;
reg r_out_read;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_address = r_out_address;
always @(posedge read)
begin
r_out_read <= 0;
if(tag[address % 13'h1000] === address)
begin
r_data <= icache[address % 13'h1000];
end
else
begin
r_out_read <= 1;
r_out_address <= address;
#0.001
icache[address % 13'h1000] <= out_data;
tag[address % 13'h1000] <= address;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_address <= address / 64 * 64 + i;
#0.001
icache[out_address % 13'h1000] <= out_data;
tag[out_address % 13'h1000] <= out_address;
end
end
end
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; template <typename T> void maxtt(T& t1, T t2) { t1 = max(t1, t2); } template <typename T> void mintt(T& t1, T t2) { t1 = min(t1, t2); } bool debug = 0; int n, m, k; string direc = URDL ; const long long MOD2 = (long long)1000000007 * (long long)1000000007; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int& x, int y, int mod = 1000000007) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et(int x = -1) { printf( %d n , x); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { return y ? gcd1(y, x % y) : x; } int a[500135], cnt[500135], M, ps[500135], pre[500135]; long long ans; pair<int, int> b1, b2; void upt(pair<int, int> z) { if (z > b1) { b2 = b1; b1 = z; } else maxtt(b2, z); } void uptAns(long long x, long long y) { if (x >= 2) maxtt(ans, x * y); } void fmain(int tid) { scanf( %d , &n); for (int(i) = 1; (i) <= (int)(n); (i)++) { scanf( %d , a + i); cnt[a[i]]++; maxtt(M, a[i]); } for (int(i) = 1; (i) <= (int)(M); (i)++) { ps[i] = ps[i - 1] + cnt[i]; pre[i] = pre[i - 1]; if (cnt[i]) pre[i] = i; } for (int y = 2; y <= M; y++) { long long cntY = 0; for (int i = y; i <= M; i += y) { cntY += (long long)(ps[min(i + y - 1, M)] - ps[i - 1]) * (i / y); } b1 = {-1, -1}; b2 = {-1, -1}; for (int k = M / y, R = M + 1; k >= 0; R = k * y, k--) { int ky = k * y, ss = (b1.first >= 0) + (b2.first >= 0); if (pre[R - 1] >= ky) { pair<int, int> key = {pre[R - 1] % y, pre[R - 1]}; upt(key); if (cnt[pre[R - 1]] > 1) upt(key); else { int tmp = pre[pre[R - 1] - 1]; if (tmp >= ky) upt({tmp % y, tmp}); } } if (b1.first >= 0) { uptAns(min((long long)(b1.first + ky) / 2, cntY - k), y); } if (b2.second >= 0) { uptAns(min((long long)(b2.first + ky), cntY - k - k), y); if ((b1.second < R) + ss >= 2) { uptAns(min((long long)(b1.first + ky), cntY - k - k - 1), y); } } } } printf( %lld n , ans); } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; }
|
`include "hglobal.v"
`default_nettype none
module formal_top ();
wire cn_clk;
wire cn_req;
wire cn_ack;
wire [`ADDRESS_SIZE-1:0] cn_addr;
wire [`DATA_SIZE-1:0] cn_data;
wire cn_err;
wire [`DATA_SIZE-1:0] cn_o_data;
cellnet_source cn_src_1 (
.i_clk(cn_clk),
.o_addr(cn_addr),
.o_dat(cn_data),
.o_req(cn_req),
.i_ack(cn_ack)
);
cellnet_sink cn_snk_1 (
.i_clk(cn_clk),
.i_addr(cn_addr),
.i_dat(cn_data),
.i_req(cn_req),
.o_ack(cn_ack),
.o_dat(cn_o_data),
.o_err(cn_err)
);
`ifdef FORMAL
initial assert(cn_req == `OFF);
initial assert(cn_ack == `OFF);
initial assert(cn_err == `OFF);
initial assert(cn_data == 0);
initial assert(cn_o_data == 0);
reg f_past_valid;
initial f_past_valid = `OFF;
always @(posedge cn_clk) begin
f_past_valid <= `ON;
end
always @(posedge cn_clk) begin
if((! cn_req) && (! cn_ack)) begin
assert(cn_data == cn_o_data);
end
if(cn_req && (! cn_ack)) begin
end
if(cn_req && cn_ack) begin
end
if((! cn_req) && cn_ack) begin
end
if(f_past_valid) begin
if($past(cn_req) && cn_req) begin
assert(cn_data == $past(cn_data));
assert(cn_addr == $past(cn_addr));
end
if((! $past(cn_req)) && cn_req) begin
assert(cn_o_data == $past(cn_data));
end
if((! $past(cn_ack)) && cn_ack) begin
assert(cn_o_data == $past(cn_data));
end
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t, n, S, s, up, down, mid, mx, mn, a, b, k, l, r, ans, raod; pair<long long, long long> p[300005]; int main() { cin >> t; while (t--) { cin >> n >> S; mn = 1e10; mx = 0; for (k = 1; k <= n; k++) { cin >> a >> b; p[k].first = a; mn = min(mn, a); p[k].second = b; mx = max(mx, b); } ans = 0; sort(p + 1, p + n + 1); l = mn; r = mx; while (l <= r) { long long mid = (l + r + 1) / 2; up = 0; down = 0; s = 0; for (k = 1; k <= n; k++) if (p[k].first > mid) up++; else if (p[k].second < mid) down++; if (up >= n / 2 + 1) { l = mid + 1; } else if (down >= n / 2 + 1) r = mid - 1; else { raod = 0; for (k = n; k >= 1; k--) { if (raod <= n / 2 & p[k].second >= mid) { raod++; s += max(mid, p[k].first); } else s += p[k].first; } if (s <= S) { ans = mid; l = mid + 1; } else r = mid - 1; } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long n, m, i, ans = 0, z, j; pair<long long, long long> a[105]; vector<pair<long long, long long> > q; cin >> n >> m; for (i = 1; i <= n; i++) a[i].second = 0; for (i = 1; i <= n; i++) cin >> a[i].first; for (j = 1; j <= m; j++) { cin >> z; a[z].second = 1; } for (i = 1; i <= n; i++) q.push_back(a[i]); sort(q.begin(), q.end()); for (i = 0; i < n; i++) if (q[i].second == 0) ans += q[i].first; for (i = n - 1; i >= 0; i--) if (q[i].second == 1) ans = ans + max(ans, q[i].first); cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_SYMBOL_V
`define SKY130_FD_SC_HD__O21BA_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_cpx_rptr_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_cpx_rptr_2 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output [7:0] sctag_cpx_req_cq_buf; // sctag to processor request
//output sctag_cpx_atom_cq_buf;
//output [`CPX_WIDTH-1:0] sctag_cpx_data_ca_buf; // sctag to cpx data pkt
//output [7:0] cpx_sctag_grant_cx_buf;
//input [7:0] sctag_cpx_req_cq; // sctag to processor request
//input sctag_cpx_atom_cq;
//input [`CPX_WIDTH-1:0] sctag_cpx_data_ca; // sctag to cpx data pkt
//input [7:0] cpx_sctag_grant_cx;
//assign sctag_cpx_atom_cq_buf = sctag_cpx_atom_cq;
//assign sctag_cpx_data_ca_buf = sctag_cpx_data_ca;
//assign cpx_sctag_grant_cx_buf = cpx_sctag_grant_cx;
//assign sctag_cpx_req_cq_buf = sctag_cpx_req_cq;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[100], b[100], i, c = 0; cin >> n; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; if ((b[i] - a[i]) >= 2) c++; } cout << c; }
|
`timescale 1ns/10ps
module simpledpram(clock,
wraddress, wrdata, wren,
rdaddress, rddata);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "somefile.mif";
input clock;
input [(ADDR_WIDTH-1):0] rdaddress;
output reg [(DATA_WIDTH-1):0] rddata;
input [(DATA_WIDTH-1):0] wrdata;
input wren;
input [(ADDR_WIDTH-1):0] wraddress;
// Declare the RAM variable
(* ram_init_file = INIT_FILE *)
reg [DATA_WIDTH-1:0] ram[(1 << ADDR_WIDTH)-1:0];
always @ (posedge clock) begin
// Write
if (wren)
ram[wraddress] <= wrdata;
// Read (if rdaddress == wraddress, return OLD data). To return
// NEW data, use = (blocking write) rather than <= (non-blocking write)
// in the write assignment. NOTE: NEW data may require extra bypass
// logic around the RAM.
rddata <= ram[rdaddress];
end
initial $readmemh({INIT_FILE,".data"}, ram);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; struct { int x; int last; string it; } a; struct kek { string w, e, r, t; }; map<char, int> bak; vector<string> st[N + 5][7], q; vector<pair<string, string> > be, en; vector<kek> ans; int n, m; string ins; char c; bool frog = false; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); bak[ u ] = 1; bak[ a ] = 2; bak[ o ] = 3; bak[ e ] = 4; bak[ i ] = 5; cin >> n; for (int i = 1; i <= n; i++) { cin >> ins; m = ins.length(); a.x = 0; a.last = 0; for (int j = 0; j < m; j++) { if (ins[j] == u || ins[j] == a || ins[j] == o || ins[j] == e || ins[j] == i ) { a.x++; c = ins[j]; a.last = bak[c]; } } a.it = ins; st[a.x][a.last].push_back(ins); } for (int i = 1; i <= N; i++) { q.clear(); for (int j = 1; j <= 5; j++) { int k; for (k = 1; k < st[i][j].size(); k += 2) { en.push_back({st[i][j][k], st[i][j][k - 1]}); } if (k == st[i][j].size()) { q.push_back(st[i][j][k - 1]); } } for (int j = 1; j < q.size(); j += 2) { be.push_back({q[j], q[j - 1]}); } } while (!be.empty() && !en.empty()) { ans.push_back( {be.back().first, en.back().first, be.back().second, en.back().second}); en.pop_back(); be.pop_back(); } for (int i = 1; i < en.size(); i += 2) { ans.push_back( {en[i].first, en[i - 1].first, en[i].second, en[i - 1].second}); } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { cout << ans[i].w << << ans[i].e << endl << ans[i].r << << ans[i].t << endl; } }
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// button_debounce.v
// Created: 4.5.2012
// Modified: 4.5.2012
//
// Testbench for button_debounce.v.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(reset_n),
.button(button),
.debounce(debounce)
);
initial begin
clk = 1'bx; reset_n = 1'bx; button = 1'bx;
#10 reset_n = 1;
#10 reset_n = 0; clk = 0;
#10 reset_n = 1;
#10 button = 0;
end
always
#5 clk = ~clk;
always begin
#100 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int kappa[100]; void incc(int jj) { if (kappa[jj] > 9) { kappa[jj + 1]++; kappa[jj] %= 10; incc(jj + 1); } } void get_count(int a1, int a2, int a3) { int i, j; if (a2 - a3 == 2) { j = 0; for (i = a2; i >= a1; i--) { if (!(s[i] == . )) { kappa[j] += s[i] - 0 ; if (kappa[j] > 9) { kappa[j + 1]++; kappa[j] %= 10; } j++; } } } else { j = 2; for (i = a2; i >= a1; i--) { if (!(s[i] == . )) { kappa[j] += s[i] - 0 ; if (kappa[j] > 9) { kappa[j + 1]++; kappa[j] %= 10; } j++; } } } incc(j); } int main(void) { cout << setprecision(10); ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int i, i1, q, g, flag = 0, tt; for (i = 0; i < 100; i++) { kappa[i] = 0; } double k = 0; cin >> s; int leng; leng = s.length(); i = 0; while (i < leng) { if (flag == 0) { if (!(( z >= s[i]) && (s[i] >= a ))) { flag = 1; q = i; } } else { if (( z >= s[i]) && (s[i] >= a )) { flag = 0; g = i - 1; get_count(q, g, tt); } if (s[i] == . ) { tt = i; } } i++; } get_count(q, leng - 1, tt); for (i = 99; i > -1; i--) { if (kappa[i] > 0) { break; } } if ((kappa[0] == 0) && (kappa[1] == 0)) { for (i1 = i; i1 > 1; i1--) { cout << kappa[i1]; if ((i1 % 3 == 2) && (i1 > 2)) { cout << . ; } } } else { if (i > 1) { for (i1 = i; i1 > 1; i1--) { cout << kappa[i1]; if ((i1 % 3 == 2) && (i1 > 2)) { cout << . ; } } cout << . ; cout << kappa[1]; cout << kappa[0]; } else { cout << 0. ; cout << kappa[1]; cout << kappa[0]; } } return 0; }
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#include <bits/stdc++.h> using namespace std; char t[5][13] = { S , M , L , XL , XXL }; char s[13]; int a[5], p[] = {0, 1, -1, 2, -2, 3, -3, 4, -4}; int main() { for (int i = 0; i < (5); ++i) scanf( %d , &a[i]); int n; scanf( %d , &n); while (n--) { scanf( %s , s); int x = 0; for (int i = 0; i < (5); ++i) if (!strcmp(t[i], s)) x = i; for (int i = 0; i < (9); ++i) if (x + p[i] >= 0 && x + p[i] < 5 && a[x + p[i]]) { puts(t[x + p[i]]); a[x + p[i]]--; break; } } return 0; }
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#include <bits/stdc++.h> const double PI = 3.141592653589793238462643383279502884197169399375105820974944; using namespace std; const int MOD = 1e9 + 7; double gcd(double a, double b) { return a < 0.01 ? b : gcd(fmod(b, a), a); } template <typename T> T mymax(T a, T b) { return (a > b) ? a : b; } template <typename T> T mymax(T a, T b, T c) { return mymax(a, mymax(b, c)); } template <typename T> T mymin(T a, T b) { return (a < b) ? a : b; } template <typename T> T mymin(T a, T b, T c) { return mymin(a, mymin(b, c)); } template <typename T> T power(T x, T y) { T res = 1; x = x % MOD; while (y > 0) { if (y & 1) res = (res * x) % MOD; y = y >> 1; x = (x * x) % MOD; } return res; } template <typename T> void swap(T *x, T *y) { T temp; temp = *y; *y = *x; *x = temp; } template <typename T> T mod(T a) { if (a > 0) return a; else return -a; } template <typename T> T logg(T a) { T x = 0; while (a > 1) { x++; a /= 2; } return x; } typedef struct trie { int a, b, c; trie(int p1, int p2, int p3) { a = p1, b = p2, c = p3; } } tri; bool operator<(tri p, tri q) { if (p.a < q.a) { return 1; } else if (p.a > q.a) return 0; else { return (p.b < q.b); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, k1; cin >> n >> k1; multiset<pair<int, int>> k; vector<int> l(n), r(n); vector<tri> p; for (int i = 1; i <= n; i++) { cin >> l[i - 1] >> r[i - 1]; p.push_back({l[i - 1], -1, i - 1}); p.push_back({r[i - 1], 1, i - 1}); } int c = 0; sort(p.begin(), p.end()); vector<int> ans; for (tri p1 : p) { int a1 = p1.a, b1 = p1.b, c1 = p1.c; if (b1 == -1) { k.insert({r[c1], c1}); c++; if (c > k1) { pair<int, int> pk = *k.rbegin(); k.erase(k.find(pk)); ans.push_back(pk.second); c--; } } else { if (k.count({r[c1], c1})) { c--; k.erase(k.find({r[c1], c1})); } } } cout << ans.size() << n ; for (int pk : ans) { cout << pk + 1 << ; } cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long inf = 1e9; const long long inf64 = 1e18; const long long MOD = inf + 7; long long a[100005], p[100005]; long long n, m; bool check(long long mid) { long long last = 0; for (long long i = 0; i < (long long)n; i++) { if (last == m) return true; if (p[last] > a[i]) { while (last < m && p[last] - a[i] <= mid) last++; continue; } long long mn = a[i] - mid; if (mn > p[last]) return false; long long id1 = upper_bound(p, p + m, a[i] + mid - 2 * (a[i] - p[last])) - p; long long id2 = upper_bound(p, p + m, a[i] + (mid - (a[i] - p[last])) / 2) - p; last = max(last, id1); last = max(last, id2); } return (last == m); } int32_t main() { ios::sync_with_stdio(false), cin.tie(nullptr); ; cin >> n >> m; for (long long i = 0; i < (long long)n; i++) cin >> a[i]; for (long long i = 0; i < (long long)m; i++) cin >> p[i]; long long ans, low = 0, high = 1e18, mid; while (low <= high) { mid = (low + high) / 2; if (check(mid)) { ans = mid; high = mid - 1; } else { low = mid + 1; } } cout << ans << n ; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v; int n, a, b; int max(int a, int b) { if (a > b) return a; return b; } bool checkNorm(pair<int, int> f, pair<int, int> s) { int x1, y1; x1 = max(f.first, s.first), y1 = f.second + s.second; if (x1 <= a && y1 <= b) return 1; y1 = max(f.second, s.second), x1 = f.first + s.first; if (x1 <= a && y1 <= b) return 1; return 0; } pair<int, int> rotate(pair<int, int> p) { swap(p.first, p.second); return p; } int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); cin >> n >> a >> b; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back(make_pair(x, y)); } int mx = 0; for (int i = 1; i < n; i++) { for (int j = 0; j < i; j++) { if (checkNorm(v[i], v[j])) { mx = max(mx, v[i].first * v[i].second + v[j].first * v[j].second); } if (checkNorm(v[i], rotate(v[j]))) { mx = max(mx, v[i].first * v[i].second + v[j].first * v[j].second); } if (checkNorm(rotate(v[i]), (v[j]))) { mx = max(mx, v[i].first * v[i].second + v[j].first * v[j].second); } if (checkNorm(rotate(v[i]), rotate(v[j]))) { mx = max(mx, v[i].first * v[i].second + v[j].first * v[j].second); } } } cout << mx; return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> using min_heap = priority_queue<T, vector<T>, greater<T>>; void setupIO(const string &PROB = ) { ios::sync_with_stdio(false); cin.tie(nullptr); if (PROB.length() != 0) { ifstream infile(PROB + .in ); if (infile.good()) { freopen((PROB + .in ).c_str(), r , stdin); freopen((PROB + .out ).c_str(), w , stdout); } } } int main() { setupIO(); int n; cin >> n; int A[n][n]; for (int i = 0; i < (n); i++) { for (int j = 0; j < (n); j++) { char c; cin >> c; A[i][j] = c == 1 ; } } int B[n]; for (int i = 0; i < (n); i++) cin >> B[i]; bool C[n]; for (int i = 0; i < n; i++) C[i] = false; ; while (true) { int tgt = -1; for (int i = 0; i < (n); i++) { if (B[i] == 0) { tgt = i; break; } } if (tgt == -1) break; assert(!C[tgt]); for (int i = 0; i < (n); i++) { if (A[tgt][i]) B[i]--; } C[tgt] = true; } vector<int> ans; for (int i = 0; i < (n); i++) if (C[i]) ans.push_back(i); cout << ans.size() << endl; for (int i = 0; i < (ans.size()); i++) { if (i != 0) cout << ; cout << ans[i] + 1; } cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> T modpow(T base, T exp) { T result = 1; while (exp > 0) { if (exp & 1) result = (result * base); base = (base * base); exp >>= 1; } return result; } int main() { queue<string> poss; long long int n, q; string x, y, poss1; ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> q; map<string, vector<string> > m; for (long long int(i) = (0); (i) < (q); (i)++) { cin >> x >> y; m[y].push_back(x); } map<string, vector<string> >::iterator it; it = m.begin(); if ((*it).first != a ) { cout << 0 << endl; return 0; } else { for (long long int(i) = (0); (i) < (m[ a ].size()); (i)++) poss.push((m[ a ])[i]); int cnt = 2; while (cnt != n) { while ((poss.front()).length() != cnt + 1) { string c = (poss.front()).substr(0, 1); if (m.find(c) != m.end()) { string str = poss.front(); poss.pop(); str = str.substr(1, str.length() - 1); for (long long int(j) = (0); (j) < (m[c].size()); (j)++) poss.push(m[c][j] + str); } else poss.pop(); if (poss.empty()) { cout << 0 << endl; return 0; } } cnt++; } } cout << poss.size() << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; void small(long long m, long long s) { vector<long long> v; long long p = (s % 9 == 0) ? s / 9 - 1 : s / 9; for (long long i = 0; i < p; i++) { v.push_back(9); s -= 9; } if (m - p == 1) { v.push_back(s); } if (m - p >= 2) { s--; v.push_back(s); for (long long i = 0; i < m - p - 2; i++) { v.push_back(0); } v.push_back(1); } for (long long i = v.size() - 1; i >= 0; i--) { cout << v[i]; } cout << ; } void great(long long m, long long s) { vector<long long> v; long long k = s / 9; for (long long i = 0; i < k; i++) { v.push_back(9); s -= 9; } if (s > 0) { v.push_back(s); k++; } for (long long i = 0; i < m - k; i++) { v.push_back(0); } for (long long i = 0; i < v.size(); i++) { cout << v[i]; } } int main() { long long m, s, h; string k; vector<int> v; cin >> m >> s; if (s % 9 == 0) { long long t = 0; if (m == 1 && s == 0) { cout << 0 << 0 ; t = 1; } if (t == 0) { if (m < s / 9 || s == 0) { cout << -1 << -1 ; } else { small(m, s); great(m, s); } } } else if (s % 9 != 0) { long long t = 0; if (m == 1 && s == 0) { cout << 0 << 0 ; t = 1; } if (t == 0) { if (m < s / 9 + 1 || s == 0) { cout << -1 << -1 ; } else { small(m, s); great(m, s); } } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hd__udp_pwrgood_pp_g.v"
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hd__udp_pwrgood_pp_p.v"
`celldefine
module sky130_fd_sc_hd__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; int n, k; string s; long long md = 1000000007; int a[2100]; long long dp[2100][2100]; long long sdp[2100][2100]; int main() { cin >> n >> k >> s; for (int i = 0; i < n; i++) a[i] = s[i] - a ; dp[n][0] = 1; sdp[n][0] = 1; for (int i = n - 1; i >= 0; i--) { for (int j = 0; j <= k; j++) { sdp[i][j] = (dp[i + 1][j]) * ((long long)(a[i])); sdp[i][j] += sdp[i + 1][j]; sdp[i][j] %= md; int ll = i; for (int l = i; (l < n) && ((l - i + 1) * (n - l) <= j); l++, ll++) { dp[i][j] = (dp[i][j] + ((long long)(25 - a[l])) * dp[l + 1][j - (l - i + 1) * (n - l)]) % md; } for (int l = n - 1; (l >= ll) && ((l - i + 1) * (n - l) <= j); l--) { dp[i][j] = (dp[i][j] + ((long long)(25 - a[l])) * dp[l + 1][j - (l - i + 1) * (n - l)]) % md; } dp[i][j] += sdp[i][j]; dp[i][j] %= md; } } cout << dp[0][k] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; int main() { long long a, b; cin >> a >> b; if (a < b) puts( -1 ); else printf( %.12f n , (a + b) / (2. * ((a + b) / (2 * b)))); return 0; }
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#include <bits/stdc++.h> using namespace std; bool a[30][30]; void fun(int x, int y) { a[x][y] = a[y][x] = true; } int main() { ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { memset(a, false, sizeof a); int n, p; cin >> n >> p; if (n % 2 == 0) { for (int i = 1; i <= n; i++) { fun(i, i + 1); } fun(1, n); int last; for (int i = 1; i + 2 <= n; i += 2) { fun(i, i + 2); last = i + 2; } fun(2, last); for (int i = 2; i + 2 <= n - 2; i += 2) { if (i + 2 == n - 2) { fun(i, i + 4); last = i + 2; } else fun(i, i + 2); last = i + 2; } fun(last, last + 2); fun(1, last); for (int i = 1; i <= n; i++) for (int j = 1; j <= n and p > 0; j++) { if (i != j and a[i][j] == false) { p--; fun(i, j); } } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i < j and a[i][j]) cout << i << << j << endl; } else { for (int i = 1; i <= n; i++) { fun(i, i + 1); } fun(1, n); int last; for (int i = 1; i + 2 <= n; i += 2) { fun(i, i + 2); last = i + 2; } fun(2, last); for (int i = 2; i + 2 <= n; i += 2) { fun(i, i + 2); last = i + 2; } fun(1, last); for (int i = 1; i <= n; i++) for (int j = 1; j <= n and p > 0; j++) { if (i != j and a[i][j] == false) { p--; fun(i, j); } } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i < j and a[i][j]) cout << i << << j << endl; } } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 500; int n; long long a[maxn], ans; long long dfs(int l, int r, int now) { if (l == r) { return 1; } long long fenge = r + 1; for (int i = l; i <= r; i++) { if (a[i] & (1 << now)) { fenge = i; break; } } long long ans = 0; if (fenge == l || fenge == r + 1) { ans = dfs(l, r, now - 1); } else { ans = max(dfs(l, fenge - 1, now - 1), dfs(fenge, r, now - 1)) + 1; } return ans; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); ans = dfs(1, n, 30); cout << n - ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int arr[4]; int aux[100010]; int next(int x) { if (x == 0) { if (arr[1] > 0) return 1; else return -1; } if (x == 1) { if (arr[0] > 0) return 0; else if (arr[2] > 0) return 2; else return -1; } if (x == 2) { if (arr[1] > 0) return 1; else if (arr[3] > 0) return 3; else return -1; } if (x == 3) { if (arr[2] > 0) return 2; else return -1; } } int arrini[4]; int n; void ok() { cout << YES n ; for (int i = 0; i < n; i++) cout << aux[i] << ; cout << n ; } bool tenta(int ini) { for (int i = 0; i < 4; i++) arr[i] = arrini[i]; arr[ini]--; aux[0] = ini; for (int i = 1; i < n; i++) { int nex = next(aux[i - 1]); if (nex == -1) return false; aux[i] = nex; arr[nex]--; } return true; } int main() { ios_base::sync_with_stdio(false); cin >> arrini[0] >> arrini[1] >> arrini[2] >> arrini[3]; for (int i = 0; i < 4; i++) arr[i] = arrini[i]; n = arr[0] + arr[1] + arr[2] + arr[3]; if (arrini[0] > 0) { if (tenta(0)) { ok(); return 0; } } if (arrini[1] > 0) { if (tenta(1)) { ok(); return 0; } } if (arrini[2] > 0) { if (tenta(2)) { ok(); return 0; } } if (arrini[3] > 0) { if (tenta(3)) { ok(); return 0; } } cout << NO n ; }
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`include "mrfm.vh"
module mrfm_iir (input clock, input reset, input strobe_in,
input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
input wire [15:0] sample_in, output reg [15:0] sample_out);
wire [5:0] coeff_addr, coeff_wr_addr;
wire [4:0] data_addr, data_wr_addr;
reg [4:0] cur_offset, data_addr_int, data_wr_addr_int;
wire [15:0] coeff, coeff_wr_data, data, data_wr_data;
wire coeff_wr;
reg data_wr;
wire [30:0] product;
wire [33:0] accum;
wire [15:0] scaled_accum;
wire [7:0] shift;
reg [5:0] phase;
wire enable_mult, enable_acc, latch_out, select_input;
reg done, clear_acc;
setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr));
setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(shift),.changed());
ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data),
.rd_addr(coeff_addr),.rd_data(coeff));
ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data),
.rd_addr(data_addr),.rd_data(data));
mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() );
acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
.addend(product),.sum(accum) );
shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
assign data_wr_data = select_input ? sample_in : scaled_accum;
assign enable_mult = 1'b1;
always @(posedge clock)
if(reset)
cur_offset <= #1 5'd0;
else if(latch_out)
cur_offset <= #1 cur_offset + 5'd1;
assign data_addr = data_addr_int + cur_offset;
assign data_wr_addr = data_wr_addr_int + cur_offset;
always @(posedge clock)
if(reset)
done <= #1 1'b0;
else if(latch_out)
done <= #1 1'b1;
else if(strobe_in)
done <= #1 1'b0;
always @(posedge clock)
if(reset)
phase <= #1 6'd0;
else if(strobe_in)
phase <= #1 6'd0;
else if(!done)
phase <= #1 phase + 6'd1;
always @(phase)
case(phase)
6'd0 : data_addr_int = 5'd0;
default : data_addr_int = 5'd0;
endcase // case(phase)
assign coeff_addr = phase;
always @(phase)
case(phase)
6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02;
6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04;
6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05;
6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07;
6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08;
6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10;
6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11;
6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13;
6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14;
6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16;
6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17;
6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19;
default : data_addr_int = 5'd00;
endcase // case(phase)
always @(phase)
case(phase)
6'd0 : data_wr_addr_int = 5'd2;
6'd8 : data_wr_addr_int = 5'd5;
6'd14 : data_wr_addr_int = 5'd8;
6'd20 : data_wr_addr_int = 5'd11;
6'd26 : data_wr_addr_int = 5'd14;
6'd32 : data_wr_addr_int = 5'd17;
6'd38 : data_wr_addr_int = 5'd20;
default : data_wr_addr_int = 5'd0;
endcase // case(phase)
always @(phase)
case(phase)
6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1;
default : data_wr = 1'b0;
endcase // case(phase)
always @(phase)
case(phase)
6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1;
default : clear_acc = 1'b0;
endcase // case(phase)
assign enable_acc = ~clear_acc;
assign latch_out = (phase == 6'd38);
always @(posedge clock)
if(reset)
sample_out <= #1 16'd0;
else if(latch_out)
sample_out <= #1 scaled_accum;
endmodule // mrfm_iir
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 20:11:26 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tx_axis_gen_stub.v
// Design : tx_axis_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, almost_full,
empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[64:0],wr_en,rd_en,dout[64:0],full,almost_full,empty" */;
input clk;
input rst;
input [64:0]din;
input wr_en;
input rd_en;
output [64:0]dout;
output full;
output almost_full;
output empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; const int MOD = 998244353; int f[1002][1000]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<int> x(n); for (int i = 0; i < n; ++i) cin >> x[i]; sort(x.begin(), x.end()); int ans = 0; for (int t = 1; t <= (x[n - 1] - x[0]) / (k - 1); ++t) { for (int i = 0; i < n; ++i) { for (int j = 0; j < k; ++j) f[i][j] = 0; } f[0][0] = 1; int pre = -1; for (int i = 1; i < n; ++i) { while (x[pre + 1] <= x[i] - t) ++pre; f[i][0] = i + 1; if (pre == -1) continue; for (int j = 1; j < k; ++j) { f[i][j] = f[i - 1][j] + f[pre][j - 1]; if (f[i][j] >= MOD) f[i][j] -= MOD; } } ans += f[n - 1][k - 1]; if (ans >= MOD) ans -= MOD; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int nm = 100010; int n, k; long long x[nm], y[nm]; set<pair<long long, int> > ngang, doc; vector<int> xoa1, xoa2, xoa3, xoa4; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); x[i] = a + c; y[i] = b + d; ngang.insert(make_pair(y[i], i)); doc.insert(make_pair(x[i], i)); } long long res = LONG_LONG_MAX; for (int a = 0; a <= k; ++a) { for (int i = 1; i <= a; ++i) { int u = ngang.begin()->second; xoa1.push_back(u); ngang.erase(ngang.begin()); doc.erase(make_pair(x[u], u)); } for (int b = 0; a + b <= k; ++b) { for (int i = 1; i <= b; ++i) { multiset<pair<long long, int> >::iterator it = ngang.end(); it--; int u = it->second; xoa2.push_back(u); ngang.erase(it); doc.erase(make_pair(x[u], u)); } for (int c = 0; a + b + c <= k; ++c) { for (int i = 1; i <= c; ++i) { int u = doc.begin()->second; xoa3.push_back(u); doc.erase(doc.begin()); ngang.erase(make_pair(y[u], u)); } int d = k - a - b - c; for (int i = 1; i <= d; ++i) { multiset<pair<long long, int> >::iterator it = doc.end(); it--; int u = it->second; xoa4.push_back(u); doc.erase(it); ngang.erase(make_pair(y[u], u)); } multiset<pair<long long, int> >::iterator it = ngang.end(); it--; long long A = it->first - ngang.begin()->first; if (A & 1) A++; if (A == 0) A = 2; it = doc.end(); it--; long long B = it->first - doc.begin()->first; if (B & 1) B++; if (B == 0) B = 2; res = min(res, A * B); for (int i = int(xoa4.size()) - 1; i >= 0; --i) { int u = xoa4[i]; xoa4.pop_back(); doc.insert(make_pair(x[u], u)); ngang.insert(make_pair(y[u], u)); } for (int i = int(xoa3.size()) - 1; i >= 0; --i) { int u = xoa3[i]; xoa3.pop_back(); doc.insert(make_pair(x[u], u)); ngang.insert(make_pair(y[u], u)); } } for (int i = int(xoa2.size()) - 1; i >= 0; --i) { int u = xoa2[i]; xoa2.pop_back(); doc.insert(make_pair(x[u], u)); ngang.insert(make_pair(y[u], u)); } } for (int i = int(xoa1.size()) - 1; i >= 0; --i) { int u = xoa1[i]; xoa1.pop_back(); doc.insert(make_pair(x[u], u)); ngang.insert(make_pair(y[u], u)); } } printf( %I64d n , res / 4); }
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long a = 0; long long b = 0; void dfs(vector<vector<int>> &g, vector<bool> was, int v, int lvl) { was[v] = true; if (lvl % 2 == 0) a++; else b++; for (int x : g[v]) { if (!was[x]) dfs(g, was, x, lvl + 1); } } int main() { int n; cin >> n; unordered_set<string> names; for (int i = 0; i < n; i++) { string s; cin >> s; if (names.find(s) == names.end()) cout << NO << endl; else cout << YES << endl; names.insert(s); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = (int)1e5 + 15; bool isAns = 1; int n, m; vector<vector<int>> gr; vector<int> a, b; void in() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; gr.resize(n + 5); for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; gr[a].push_back(b); gr[b].push_back(a); } } void solution() { if (n == 1) { isAns = 0; return; } a.resize(n + 1); int last = 2; int ind = -1; for (int i = 1; i <= n; ++i) { if (gr[i].size() != n - 1) { ind = i; a[i] = 1; int cur = n; for (auto it : gr[i]) { a[it] = cur--; } break; } } if (ind == -1) { isAns = 0; return; } for (int i = 1; i <= n; ++i) { if (a[i] == 0) { a[i] = last++; } } b = a; pair<int, int> res = {0, 0}; int i = ind; int L = 1, R = n; for (auto it : gr[i]) { if (a[i] < a[it]) R = min(R, a[it] - 1); else L = max(L, a[it] + 1); } for (int j = L; j <= R; ++j) { if (j != a[i]) { res = {i, j}; break; } } if (res.first == 0) { isAns = 0; } else { b[res.first] = res.second; } } void out() { if (!isAns) { cout << NO n ; } else { cout << YES n ; for (int i = 1; i <= n; ++i) { cout << a[i] << ; } cout << n ; for (int i = 1; i <= n; ++i) { cout << b[i] << ; } cout << n ; } } int main() { in(); solution(); out(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int mex = 1e9; for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; mex = min(mex, r - l + 1); } cout << mex << n ; for (int i = 0; i < n; i++) { cout << i % mex << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int idx[2 * n + 1], chk = 2 * n; vector<long long int> coin; coin.push_back(0LL); for (long long int i = 1; i <= 2 * n; i++) { long long int x; cin >> x; idx[x] = i; } for (long long int i = 2 * n; i >= 1; i--) { if (idx[i] <= chk) { coin.push_back(chk - idx[i] + 1); chk = idx[i] - 1; } } long long int cost = n, coin_no = coin.size() - 1; long long int dp[coin_no + 1][cost + 1]; memset(dp, 0, sizeof(dp)); for (long long int i = 0; i <= coin_no; i++) dp[i][0] = 1; for (long long int i = 1; i <= coin_no; i++) { for (long long int j = 1; j <= cost; j++) { dp[i][j] = dp[i - 1][j]; if (coin[i] <= j) dp[i][j] |= dp[i - 1][j - coin[i]]; } } if (dp[coin_no][cost]) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ar[1000009]; int main() { long long a, s, d, f, g, h, j, k, l; cin >> a; k = 0; for (s = 1; s <= a; s++) { scanf( %d , &ar[s]); if (ar[s]) k++; } d = 0; l = 0; for (s = 1; s <= a; s++) { if (ar[s] == 1) { d = d + (a - k - l); } else l++; } f = 0; for (s = a; s >= 1; s--) { if (ar[s] == 0) f = f + k; else k--; } cout << min(d, f) << endl; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int prim[100000]; int main() { int a, b; cin >> a >> b; bool ok = false; int x = 0; for (int i = 3; i <= a; i++) { for (int j = 2; j < i / 2; j++) { if (i % j == 0) { ok = true; break; } } if (ok == false) { prim[x] = i; x++; } ok = false; } int sum = 0; int xx = 0; for (int i = 0; i < x; i++) { sum = prim[i] + prim[i + 1] + 1; for (int j = 0; j < x; j++) { if (sum == prim[j]) { xx++; break; } } } if (xx >= b) { cout << YES ; return 0; } else { cout << NO ; return 0; } }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { int n; cin >> n; long long int sum = 0; for (int i = 1; i < n; i++) { sum += ((n - i) * i); } cout << sum + n; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, n, k, r; cin >> n >> k; long long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } long long int *m = min_element(a, a + n); r = 0; for (i = 0; i < n; i++) { if ((a[i] - *m) % k == 0) { r += (a[i] - *m) / k; } else { cout << -1; return 0; } } cout << r; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> f, num; int Q; int find(int x) { if (!f.count(x)) return x; int fa = find(f[x]); num[x] ^= num[f[x]]; return f[x] = fa; } int main() { scanf( %d , &Q); int last = 0; while (Q--) { int opt, l, r, x; scanf( %d %d %d , &opt, &l, &r); l ^= last, r ^= last; if (l > r) swap(l, r); l--; if (opt & 1) { scanf( %d , &x); x ^= last; int fl = find(l), fr = find(r); if (fl != fr) f[fr] = fl, num[fr] = x ^ num[l] ^ num[r]; } else { int fl = find(l), fr = find(r); if (fl != fr) last = 1, printf( -1 n ); else last = num[l] ^ num[r], printf( %d n , last); } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:12:30 05/13/2015
// Design Name:
// Module Name: FSMinput
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSMinput(
clk, rst, in, in2, text, seven, EN
);
input clk, rst;
input in, in2;
input [6:1] text;
output [3:0] EN;
reg [64:1] out;
output [6:0] seven;
wire w, w2, w3, w4;
//wire clk, cclk;
//clk50 divider(.clk(nclk),.rst(rst),.clkdivided1hz(clk), .clkdivided2hz(cclk));
shift_reg r1 (clk,rst, in, w);
risingdge edge1 (~clk, rst, w, w2);
shift_reg r2 (clk,rst, in2, w3);
risingdge edge2 (~clk, rst, w3, w4);
//assign w2 = w;
reg [3:0] state, nextstate;
wire [64:1] dectext;
parameter [3:0] s0 = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0011, s4 = 4'b0100 , s5 = 4'b0101, s6 = 4'b0110, s7 = 4'b0111, s8 = 4'b1000 , s9 = 4'b1001, s10 = 4'b1010, s11 = 4'b1011;
always @ (w2 or state )
if(w2 == 4'b0) nextstate = state;
else
case (state)
s0:
begin
if(w2) begin nextstate = s1; out[6:1] <= text; end // seven <= 7'b0000001;end
//else nextstate = s0;
end
s1:
begin
if (w2) begin nextstate = s2; out[12:7] <= text;end // seven <= 7'b1001111; end
//else if (!w2[1]) nextstate = s1;
//else nextstate = s0;
end
s2:
begin
if (w2) begin nextstate = s3; out[18:13] <= text;end //seven <= 7'b0010010; end
//else if (!w2[2]) nextstate = s2;
//else nextstate = s0;
end
s3:
begin
if (w2) begin nextstate = s4; out[24:19] <= text;end // seven <= 7'b0000110; end
//else nextstate = s0;
end
s4:
begin
if (w2) begin nextstate = s5; out[30:25] <= text;end // seven <= 7'b1001100; end
//else nextstate = s0;
end
s5:
begin
if (w2) begin nextstate = s6; out[36:31] <= text;end // seven <= 7'b0100100;end
//else nextstate = s0;
end
s6:
begin
if (w2) begin nextstate = s7; out[42:37] <= text;end // seven <= 7'b0100000; end
//else nextstate = s0;
end
s7:
begin
if (w2) begin nextstate = s8; out[48:43] <= text;end // seven <= 7'b0001111;end
//else nextstate = s0;
end
s8:
begin
if (w2) begin nextstate = s9; out[54:49] <= text;end // seven <= 7'b0000000;end
//else nextstate = s0;
end
s9:
begin
if (w2) begin nextstate = s10; out[60:55] <= text;end // seven <= 7'b0000100;end
//else nextstate = s0;
end
s10:
begin
if (w2) begin nextstate = s11; out[64:61] <= text[4:1];end //seven <= 7'b0001000;end
//else nextstate = s0;
end
s11:
begin
if (w2) begin nextstate = s11; end
//else nextstate = s0;
end
default: begin
nextstate = 4'bx;
end
endcase
always @ (posedge clk or posedge rst)
begin
if (rst) begin state <= s0; end
else state <= nextstate;
end
wire sell;
assign sell = (state==s11)? 1:0;
DES_main d1(clk, 0, sell, out, 64'd1337,dectext);
wire [1:0] wee;
FSMup fg(clk, rst, w4, wee);
finalcounter fc (clk, 0,dectext,wee, seven, EN, sell);
//assign plain = out;
// DES_main d1(clk, rst, select, out,dectext);
//assign out = (state == s4) ? 7'b1000001 : 7'b1110001;
endmodule
|
#include <bits/stdc++.h> using namespace std; #define int long long #define pii pair<int, int> int32_t mod = 1e9 + 7; void solveCase() { int n = 0, m = 0; cin >> n >> m; vector<vector<int>> mp(m, vector<int>(26, 0)); for (int i = 0; i < n; i++) { string s; cin >> s; for (int i = 0; i < m; i++) mp[i][s[i] - a ]++; } for (int i = 0; i < n - 1; i++) { string s; cin >> s; for (int i = 0; i < m; i++) mp[i][s[i] - a ]--; } for (int i = 0; i < m; i++) for (int x = 0; x < 26; x++) if (mp[i][x]) cout << char( a + x); cout << n ; } int32_t main() { ios::sync_with_stdio(false), cin.tie(NULL); int t = 0; cin >> t; while (t--) solveCase(); }
|
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