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//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core top level. ////
//// ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
//
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_top (
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
int_o, // interrupt request
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
parameter SIM = 0;
parameter debug = 0;
input wb_clk_i;
// WISHBONE interface
input wb_rst_i;
input [2:0] wb_adr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_ack_o;
output int_o;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire [2:0] wb_adr_i;
wire [7:0] wb_dat_i;
wire [7:0] wb_dat_o;
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [2:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
//// WISHBONE interface module
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
// Registers
uart_regs #(.SIM (SIM)) regs(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
`endif
);
initial
begin
if(debug) begin
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; struct node { long long l, r; long long color; long long sum; long long change; } tree[maxn << 2]; long long n, m; int a[maxn]; void pushup(long long cur) { if (tree[cur * 2].color == tree[cur * 2 + 1].color) tree[cur].color = tree[cur * 2].color; tree[cur].sum = tree[cur * 2].sum + tree[cur * 2 + 1].sum; } void build(long long l, long long r, long long cur) { tree[cur].l = l; tree[cur].r = r; tree[cur].sum = 0; tree[cur].change = 0; tree[cur].color = 0; if (l == r) { tree[cur].color = l; return; } long long mid = (r + l) >> 1; build(l, mid, cur << 1); build(mid + 1, r, cur << 1 | 1); pushup(cur); } void pushdown(long long cur) { if (tree[cur].change) { tree[cur * 2].sum += tree[cur].change * (tree[cur * 2].r - tree[cur * 2].l + 1); tree[cur * 2 + 1].sum += tree[cur].change * (tree[cur * 2 + 1].r - tree[cur * 2 + 1].l + 1); tree[cur * 2].change += tree[cur].change; tree[cur * 2 + 1].change += tree[cur].change; tree[cur].change = 0; } if (tree[cur].color) tree[cur * 2].color = tree[cur * 2 + 1].color = tree[cur].color; tree[cur].color = 0; } void update(long long pl, long long pr, long long l, long long r, long long cur, long long x) { if ((pl <= l && r <= pr && tree[cur].color) || l == r) { tree[cur].sum += abs(x - tree[cur].color) * (r - l + 1); tree[cur].change += abs(x - tree[cur].color); tree[cur].color = x; return; } pushdown(cur); long long mid = (r + l) >> 1; if (pl <= mid) update(pl, pr, l, mid, cur << 1, x); if (pr > mid) update(pl, pr, mid + 1, r, cur << 1 | 1, x); pushup(cur); } long long query(long long pl, long long pr, long long l, long long r, long long cur) { if (pl <= l && r <= pr) { return tree[cur].sum; } pushdown(cur); long long mid = (r + l) >> 1; long long res = 0; if (pl <= mid) res += query(pl, pr, l, mid, cur << 1); if (pr > mid) res += query(pl, pr, mid + 1, r, cur << 1 | 1); return res; } int main() { while (~scanf( %lld%lld , &n, &m)) { build(1, n, 1); long long op, l, r, x; while (m--) { scanf( %lld%lld%lld , &op, &l, &r); if (op == 1) { scanf( %lld , &x); update(l, r, 1, n, 1, x); } else { printf( %lld n , query(l, r, 1, n, 1)); } } } return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : buf_ram_2p_64x32.v
// Author : Yibo FAN
// Created : 2014-04-07
// Description : buf ram for coefficient
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module buf_ram_2p_64x32 (
clk ,
a_we ,
a_addr ,
a_data_i ,
b_re ,
b_addr ,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
// PORT A
input [1:0] a_we ;
input [4:0] a_addr ;
input [`PIXEL_WIDTH*8-1:0] a_data_i ;
// PORT B
input b_re ;
input [4:0] b_addr ;
output [`PIXEL_WIDTH*8-1:0] b_data_o ;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [7:0] a_wen ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin a_wen=8'hff ; end
2'b01: begin a_wen={4'hf, 4'h0} ; end
2'b10: begin a_wen={4'b0, 4'hf} ; end
2'b11: begin a_wen=8'h00 ; end
endcase
end
`ifndef FPGA_MODEL
rf_2p_be #(.Addr_Width(5), .Word_Width(`PIXEL_WIDTH*8))
u_ram_2p_64x32 (
.clka ( clk ),
.cena_i ( ~b_re ),
.addra_i ( b_addr ),
.dataa_o ( b_data_o ),
.clkb ( clk ),
.cenb_i ( !(|a_we) ),
.wenb_i ( a_wen ),
.addrb_i ( a_addr ),
.datab_i ( a_data_i )
);
`endif
`ifdef FPGA_MODEL
ram_2p_64x32 u_ram_2p_64x32(
.byteena_a ( ~a_wen ),
.clock ( clk ),
.data ( a_data_i ),
.rdaddress ( b_addr ),
.wraddress ( a_addr ),
.wren ( |a_we ),
.q ( b_data_o )
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 2e9 + 1e8; const long long INF = 2e18 + 1e17; const int mod = 998244353; const int MOD = 1e9 + 7; long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } bool is_prime(int x) { if (x <= 1 || (x % 2 == 0 && x > 2)) return false; for (int i = 3; i * i <= x; i += 2) { if (!(x % i)) { return false; } } return true; } const int MAXN = 40010; int N; string str; vector<int> arr; int ans; int main() { cin >> N >> str; arr.resize(N); int sum = 0; for (int i = 0; i < str.length(); i++) { arr[i] = (str[i] == ) ? -1 : 1); sum += arr[i]; } if (sum != 0) { cout << -1 << endl; return 0; } int cur = 0, last = 0; bool bad = false; for (int i = 0; i < N; i++) { cur += arr[i]; if (!bad && cur < 0) { bad = true; last = i; } else if (cur == 0 && bad) { ans += (i - last + 1); bad = false; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const int INF = 1e9; using namespace std; void dfs(int v, int p, vector<vector<int> > &graph, vector<int> &sz) { sz[v] = 1; for (auto u : graph[v]) if (u != p) { dfs(u, v, graph, sz); sz[v] += sz[u]; } } void dfs(int v, int p, vector<vector<int> > &graph, vector<int> &c, int C) { c[v] = C; for (auto u : graph[v]) if (u != p) { dfs(u, v, graph, c, C); } } signed main() { int n; cin >> n; vector<vector<int> > graph(n); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; graph[a].push_back(b); graph[b].push_back(a); } vector<int> sz(n); dfs(0, 0, graph, sz); vector<int> cen; long long ans = 0; for (int i = 0; i < n; i++) { if ((n - sz[i]) * 2 <= n) { int t = 1; for (auto u : graph[i]) { if (sz[u] < sz[i]) { if (2 * sz[u] <= n) continue; t = 0; } } if (t) cen.push_back(i); } } for (int i = 0; i < n; i++) { ans += 2 * min(sz[i], n - sz[i]); } cout << ans << n ; if (cen.size() == 2) { int v = cen[0], u = cen[1]; vector<int> c(n); dfs(v, u, graph, c, 0); dfs(u, v, graph, c, 1); vector<int> p0, p1; for (int i = 0; i < n; i++) { if (c[i] == 0) p0.push_back(i); if (c[i] == 1) p1.push_back(i); } vector<int> ans(n); for (int i = 0; i < n / 2; i++) { ans[p0[i]] = p1[i]; ans[p1[i]] = p0[i]; } for (int i = 0; i < n; i++) { cout << ans[i] + 1 << ; } return 0; } else { dfs(cen[0], cen[0], graph, sz); int C = 0, idC = 0; vector<int> c(n); c[cen[0]] = -1; int maxsz = 0; for (auto u : graph[cen[0]]) { dfs(u, cen[0], graph, c, C); maxsz = max(maxsz, sz[u]); if (maxsz == sz[u]) idC = C; C++; } vector<pair<int, int> > q; for (int i = 0; i < n; i++) { if (i != cen[0] && c[i] != idC) q.push_back({c[i], i}); } for (int i = 0; i < n; i++) { if (i != cen[0] && c[i] == idC) q.push_back({INF, i}); } q.push_back({INF + 1, cen[0]}); sort((q).begin(), (q).end()); vector<int> ans(n); for (int i = 0; i < n; i++) { ans[q[i].second] = q[(i + maxsz) % q.size()].second; } for (int i = 0; i < n; i++) { assert(c[ans[i]] != c[i]); cout << ans[i] + 1 << ; } } }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3fLL; const long long mod = 1e9 + 7; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long pct(long long x) { return __builtin_popcount(x); } long long bit(long long x) { return 31 - __builtin_clz(x); } long long cdiv(long long a, long long b) { return a / b + !(a < 0 || a % b == 0); } void DBG() { cerr << ] << endl; } template <class H, class... T> void DBG(H h, T... t) { cerr << to_string(h); if (sizeof...(t)) cerr << , ; DBG(t...); } const long long maxn = 1e5 * 3 + 20; long long n, _, q, k; void solve() { cin >> _; while (_--) { cin >> n; long long sm = 0; vector<long long> a(n); vector<long long> b(n); for (signed i = 0; i < n; i++) { cin >> a[i]; } for (signed i = 0; i < n; i++) { cin >> b[i]; sm += b[i]; } vector<long long> order(n); iota(order.begin(), order.end(), 0); sort(begin(order), end(order), [&a](long long i, long long j) { return a[i] < a[j]; }); long long ans = sm; for (long long x : order) { long long tmp = max(sm - b[x], a[x]); if (tmp < ans) { sm -= b[x]; ans = tmp; } } cout << ans << endl; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_fcmp_32ns_32ns_1_1
#(parameter
ID = 5,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 1
)(
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
input wire [4:0] opcode,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Parameter----------------------
// AutoESL opcode
localparam [4:0]
AP_OEQ = 5'b00001,
AP_OGT = 5'b00010,
AP_OGE = 5'b00011,
AP_OLT = 5'b00100,
AP_OLE = 5'b00101,
AP_ONE = 5'b00110,
AP_UNO = 5'b01000;
// FPV6 opcode
localparam [7:0]
OP_EQ = 8'b00010100,
OP_GT = 8'b00100100,
OP_GE = 8'b00110100,
OP_LT = 8'b00001100,
OP_LE = 8'b00011100,
OP_NE = 8'b00101100,
OP_UO = 8'b00000100;
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire op_tvalid;
reg [7:0] op_tdata;
wire r_tvalid;
wire [7:0] r_tdata;
//------------------------Instantiation------------------
feedforward_ap_fcmp_0_no_dsp_32 feedforward_ap_fcmp_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.s_axis_operation_tvalid ( op_tvalid ),
.s_axis_operation_tdata ( op_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign b_tvalid = 1'b1;
assign b_tdata = din1==='bx ? 'b0 : din1;
assign op_tvalid = 1'b1;
assign dout = r_tdata[0];
always @(*) begin
case (opcode)
AP_OEQ : op_tdata = OP_EQ;
AP_OGT : op_tdata = OP_GT;
AP_OGE : op_tdata = OP_GE;
AP_OLT : op_tdata = OP_LT;
AP_OLE : op_tdata = OP_LE;
AP_ONE : op_tdata = OP_NE;
AP_UNO : op_tdata = OP_UO;
default : op_tdata = OP_EQ;
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory Windows
// File : hbi_mw.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This block implements the memory window read and write caches, and yuv
// conversion.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module hbi_mw
(
// from PCI
input hb_clk,
input mclock,
input hb_soft_reset_n,
input frame_n, // PCI FRAME#
input sobn_n, // start of burst
input irdy_n, // PCI IRDY#
input [25:2] hbi_mac, // pci address, from counter
input [31:0] hbi_data_in, // pci data, one flop from pin, swizzled
input [3:0] mw_be, // pci byte enables, one flop, swizzled
input hb_write, // read(0)/write(1) indicator.
// from REGBLOCK
input cs_mem0_n, // decode for window 0
input cs_mem1_n, // decode for window 0
input [24:0] mw0_ctrl_reg, // memory win 0 control reg
input [24:0] mw1_ctrl_reg, // memory win 1 control reg
input [3:0] mw0_sz, // memory win 0 size reg
input [3:0] mw1_sz, // memory win 1 size reg
input [25:12] mw0_org, // memory win 0 origin reg
input [25:12] mw1_org, // memory win 1 origin reg
// from MC
input hst_push, // data strobe to load read cache
input hst_pop, // data strobe to select next location
input [1:0] hst_mw_addr, // Memory window address for RAM
input mc_ready_p, // mc is ready to accept a command
input [127:0] pix_in_dbus, // data bus from mc to read cache
// from CRT
input crt_vertical_intrp_n, // vertical interrupt
input hbi_mwflush, // any memory window ctrl register decode
input cs_de_xy1_n, // 2d trigger register decode
input cs_dl_cntl, // cache flush request from DLP
// to PCI
output [31:0] hb_rcache_dout, // readback data from mc, via read cache
output window0_busy_n, // status for polling
output window1_busy_n, // status for polling
output mw_trdy, // trdy, one flop from the pin
output mw_stop, // stop, one flop from the pin
// to DLP
output mw_dlp_fip, // memory window write cache is dirty
// to DE
output mw_de_fip, // flush initiated by DE trigger
// to MC
output [22:0] linear_origin, // memory address
output [127:0] hb_pdo, // memory data
output [15:0] mem_mask_bus, // byte enables
output read, // memory read=1, write=0
output hb_mc_request_p, // request a memory cycle
output full
);
/*
* wires
*/
wire [3:0] wc_be, wc_be_d;
wire clr_wc0;
wire clr_wc1;
wire ld_wc0;
wire ld_wc1;
wire [2:0] sub_buf_sel;
wire [31:0] pci_data;
wire [7:0] lut_v0_index;
wire [7:0] lut_u0_index;
wire [9:0] lut_v0;
wire [9:0] lut_v1;
wire [9:0] lut_u0;
wire [9:0] lut_u1;
wire [3:0] rcache_sel;
wire rst_rc_ptr;
wire [2:0] mw_dp_mode;
wire wcregs_addr;
wire wcregs_we;
wire mc_done;
wire [1:0] push_count;
wire [3:0] read_addr;
wire yuv_ycrcb;
wire select; // select which half to write 422_32 to
/*
* Memory Window Control
*/
hbi_mw_ctl U_MW_CTL
(
.hb_clk (hb_clk),
.hb_soft_reset_n (hb_soft_reset_n),
.frame_n (frame_n),
.sobn_n (sobn_n),
.irdy_n (irdy_n),
.hbi_mac (hbi_mac),
.mw_be (mw_be),
.hb_write (hb_write),
.cs_mem0_n (cs_mem0_n),
.cs_mem1_n (cs_mem1_n),
.mw0_ctrl_reg (mw0_ctrl_reg),
.mw1_ctrl_reg (mw1_ctrl_reg),
.mw0_sz (mw0_sz),
.mw1_sz (mw1_sz),
.mw0_org (mw0_org),
.mw1_org (mw1_org),
.mc_rdy (mc_ready_p),
.mc_done (mc_done),
.crt_vertical_intrp_n(crt_vertical_intrp_n),
.hbi_mwflush (hbi_mwflush),
.cs_de_xy1_n (cs_de_xy1_n),
.cs_dl_cntl (cs_dl_cntl),
.window0_busy_n (window0_busy_n),
.window1_busy_n (window1_busy_n),
.mw_dlp_fip (mw_dlp_fip),
.mw_de_fip (mw_de_fip),
.mw_trdy (mw_trdy),
.mw_stop (mw_stop),
.linear_origin (linear_origin),
.mc_rw (read),
.mc_req (hb_mc_request_p),
.clr_wc0 (clr_wc0),
.clr_wc1 (clr_wc1),
.ld_wc0 (ld_wc0),
.ld_wc1 (ld_wc1),
.wcregs_addr (wcregs_addr),
.wcregs_we (wcregs_we),
.sub_buf_sel (sub_buf_sel),
.wc_be (wc_be),
.wc_be_d (wc_be_d),
.yuv_ycrcb (yuv_ycrcb),
.mw_dp_mode (mw_dp_mode),
.read_addr (read_addr),
.select_del (select),
.full (full)
);
/*
* Write Cache Registers
*/
hbi_wcregs U_WCREGS
(
.hb_clk (hb_clk),
.hb_soft_reset_n (hb_soft_reset_n),
.pci_data (pci_data),
.wc_be (wc_be),
.wc_be_d (wc_be_d),
.clr_wc0 (clr_wc0),
.clr_wc1 (clr_wc1),
.ld_wc0 (ld_wc0),
.ld_wc1 (ld_wc1),
.wcregs_addr (wcregs_addr),
.wcregs_we (wcregs_we),
.sub_buf_sel (sub_buf_sel),
.mclock (mclock),
.hst_pop (hst_pop),
.hst_push (hst_push),
.hst_mw_addr (hst_mw_addr),
.select (select),
.hb_pdo (hb_pdo),
.hst_md (mem_mask_bus),
.mc_done (mc_done),
.push_count (push_count)
);
/*
* Read Cache Registers
*/
ram_128_32x32_dp U_RCREGS
(
.data (pix_in_dbus),
.wren (hst_push),
.wraddress (push_count),
.wrclock (mclock),
.rdclock (hb_clk),
.rdaddress (read_addr),
.q (hb_rcache_dout)
);
/*
* YUV to RGB Converter. Note bit-blasting of yuv_adr register.
*/
hbi_yuv2rgb U_YUV2RGB
(
.hb_clk (hb_clk),
.hbi_din (hbi_data_in),
.mw_dp_mode (mw_dp_mode),
.lut_v0 (lut_v0),
.lut_v1 (lut_v1),
.lut_u0 (lut_u0),
.lut_u1 (lut_u1),
.ycbcr_sel_n (yuv_ycrcb),
.select (select),
.pci_data (pci_data),
.lut_u0_index (lut_u0_index),
.lut_v0_index (lut_v0_index)
);
/*
* V/Cr look-up table
*/
hbi_lut_v U_LUTV0
(
.hb_clk (hb_clk),
.lut_v_index (lut_v0_index[7:0]),
.lut_v0_dout (lut_v0[9:0]),
.lut_v1_dout (lut_v1[9:0])
);
/*
* U/Cb look-up table
*/
hbi_lut_u U_LUTU0
(
.hb_clk (hb_clk),
.lut_u_index (lut_u0_index[7:0]),
.lut_u0_dout (lut_u0[9:0]),
.lut_u1_dout (lut_u1[9:0])
);
endmodule // HBI_MW
|
`timescale 1 ns / 1 ps
`include "Eight_Digit_Seven_Segment_Display_v2_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Eight_Digit_Seven_Segment_Display_v2_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:41:39 04/21/2015
// Design Name: e_finder
// Module Name: H:/Users/ll024/Downloads/PrimeFactorization (1)/PrimeFactorization/PrimeFactorization/test_e_finder.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: e_finder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_e_finder;
// Inputs
reg clk;
reg [7:0] boundary;
// Outputs
wire [64:0] e;
wire done;
// Instantiate the Unit Under Test (UUT)
e_finder uut (
.clk(clk),
.boundary(boundary),
.e(e),
.done(done)
);
always #1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
boundary = 100;
// Wait 100 ns for global reset to finish
#3000;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, d, res; int a[200005]; int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; if (a[i] == 2) d++; } if (d <= n / 2) { res += d; n -= 2 * d; res += n / 3; cout << res; return 0; } else { cout << n - d; } }
|
#include <bits/stdc++.h> using namespace std; int n, k, l[50 + 1]; void Answer() { int j = 1, s = n; for (int i = 1; i <= k; i++) { if (i > s) s += n - (++j) + 1; cout << j << ; for (int u = n - 1; u > n - j; u--) cout << l[u] << ; cout << l[s - i] << endl; } } int main() { cin >> n >> k; for (int i = 0; i < n; i++) cin >> l[i]; sort(l, l + n); Answer(); return 0; }
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg empty_reg ;
reg [width - 1 : 0] D_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
module FSM(reset,clk,enable,count18,count32,reset_int,done, en_bclk);
input wire reset;
input wire clk;
input wire enable;
input wire count18;
input wire count32;
output reg reset_int;
output reg done;
output reg en_bclk;
localparam e_reset = 2'b00;
localparam e_espera = 2'b01;
localparam e_leer = 2'b11;
reg [1:0] next_state = e_reset;
reg [1:0] state = e_reset;
always@(reset, enable, count18, count32, state)
begin
if(reset)
next_state = e_reset;
else
if((state == e_reset) && enable)
next_state = e_espera;
else
if((state == e_espera) && count18)
next_state = e_leer;
else
if((state == e_leer) && count32)
next_state = e_espera;
else
next_state = state;
end
always@(posedge clk)
if(reset)
state = e_reset;
else
state = next_state;
always@(state)
case (state)
e_reset:
begin
done = 1'b0;
reset_int = 1'b1;
en_bclk = 1'b0;
end
e_espera:
begin
done = 1'b0;
reset_int = 1'b0;
en_bclk = 1'b1;
end
e_leer:
begin
done = 1'b1;
reset_int = 1'b0;
en_bclk = 1'b1;
end
default:
begin
done = 1'b0;
reset_int = 1'b1;
en_bclk = 1'b0;
end
endcase
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:102400000,102400000 ) using namespace std; int lowbit(int x) { return (x & -x); } template <class T_> T_ f_abs(T_ x) { return x < 0 ? -x : x; } template <class T_> T_ f_max(T_ a, T_ b) { return a > b ? a : b; } template <class T_> T_ f_min(T_ a, T_ b) { return a < b ? a : b; } template <class T_> void chkmax(T_ &a, T_ b) { if (a == -1 || a < b) a = b; } template <class T_> void chkmin(T_ &a, T_ b) { if (a == -1 || a > b) a = b; } template <class T_> T_ gcd(T_ a, T_ b) { while (T_ t = a % b) a = b, b = t; return b; } template <class T_> void f_swap(T_ &a, T_ &b) { T_ t = a; a = b; b = t; } const double eps = 1e-9; const int dx[] = {-1, 1, 0, 0, -1, -1, 1, 1}, dy[] = {0, 0, -1, 1, -1, 1, -1, 1}; const int inf = 0x7fffffff; const int mod = 1000000007; const int N = 100003; const int MAXV = 100003; int n, m, cnt, who[N], dsu[N]; bool vis[N], tree[N << 2]; vector<pair<int, int> > vt[N], qu[N]; struct Oper { int tp, x, y; bool tag; Oper() {} Oper(int tp_, int x_, int y_) { tp = tp_; x = x_; y = y_; } } op[N]; struct Edge { int to, next; } edg[MAXV << 1]; int total, idx, root, first[MAXV]; int siz[MAXV]; int dep[MAXV]; int top[MAXV]; int fa[MAXV]; int son[MAXV]; int id[MAXV]; void Dfs_1(int u) { int e, v, i; siz[u] = 1; son[u] = 0; for (e = 0; e < (int)vt[u].size(); ++e) { v = vt[u][e].first; i = vt[u][e].second; op[i].tag = !vis[v]; } vis[u] = true; for (e = first[u]; ~e; e = edg[e].next) { v = edg[e].to; if (v != fa[u]) { fa[v] = u; dep[v] = dep[u] + 1; Dfs_1(v); if (son[u] == 0 || siz[v] > siz[son[u]]) son[u] = v; siz[u] += siz[v]; } } for (e = 0; e < (int)vt[u].size(); ++e) { v = vt[u][e].first; i = vt[u][e].second; if (op[i].tag && !vis[v]) op[i].tag = false; } } void Dfs_2(int u, int tp) { id[u] = ++idx; top[u] = tp; if (son[u] != 0) Dfs_2(son[u], top[u]); for (int e = first[u]; ~e; e = edg[e].next) { int v = edg[e].to; if (v != son[u] && v != fa[u]) Dfs_2(v, v); } } void BuildChain() { Dfs_1(root); Dfs_2(root, root); } void Build(int l, int r, int root) { tree[root] = false; if (l == r) return; int mid = ((l + r) >> 1); Build(l, mid, (root << 1)); Build(mid + 1, r, (root << 1 | 1)); } void Update(int p, int l, int r, int root) { if (l == r) { tree[root] = true; return; } int mid = ((l + r) >> 1); if (p <= mid) Update(p, l, mid, (root << 1)); else Update(p, mid + 1, r, (root << 1 | 1)); tree[root] = (tree[(root << 1)] && tree[(root << 1 | 1)]); } bool Query(int L, int R, int l, int r, int root) { if (L <= l && r <= R) return tree[root]; int mid = ((l + r) >> 1); bool res = true; if (L <= mid) res = (res && Query(L, R, l, mid, (root << 1))); if (R > mid) res = (res && Query(L, R, mid + 1, r, (root << 1 | 1))); return res; } bool FindChain(int u, int v) { int u_top = top[u], v_top = top[v], L, R; while (u_top != v_top) { if (dep[u_top] < dep[v_top]) { f_swap(u_top, v_top); f_swap(u, v); } L = id[u_top]; R = id[u]; if (!Query(L, R, 1, idx, 1)) return false; u = fa[u_top]; u_top = top[u]; } if (u != v) { if (dep[u] > dep[v]) f_swap(u, v); L = id[son[u]]; R = id[v]; if (!Query(L, R, 1, idx, 1)) return false; } return true; } void addedge(int from, int to) { edg[total].to = to; edg[total].next = first[from]; first[from] = total++; } void Init() { cnt = 0; root = n + 1; total = idx = fa[root] = dep[root] = 0; for (int i = 1; i <= n + 1; ++i) { first[i] = -1; dsu[i] = i; vt[i].clear(); vis[i] = false; } } void GetData() { int tp, x, y; for (int i = 0; i < m; ++i) { scanf( %d%d , &tp, &x); if (tp != 2) scanf( %d , &y); if (tp == 1) { dsu[x] = y; addedge(y, x); } else if (tp == 2) { y = -1; who[++cnt] = x; qu[cnt].clear(); } else { vt[x].push_back(make_pair(who[y], i)); qu[y].push_back(make_pair(x, i)); } op[i] = Oper(tp, x, y); } } void Solve() { int i, j, tp, p; bool flag; for (i = 1; i <= n; ++i) { if (dsu[i] == i) addedge(n + 1, i); } BuildChain(); Build(1, idx, 1); for (i = cnt = 0; i < m; ++i) { tp = op[i].tp; if (tp == 1) Update(id[op[i].x], 1, idx, 1); else if (tp == 2) { ++cnt; for (j = 0; j < (int)qu[cnt].size(); ++j) { p = qu[cnt][j].second; if (op[p].tag) flag = FindChain(who[cnt], qu[cnt][j].first); else flag = false; vis[p] = flag; } } } for (i = 0; i < m; ++i) { if (op[i].tp == 3) puts(vis[i] ? YES : NO ); } } int main() { while (~scanf( %d%d , &n, &m)) { Init(); GetData(); Solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_TB_V
`define SKY130_FD_SC_HS__O21AI_TB_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1 = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1 = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1 = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1 = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__o21ai dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_TB_V
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10000 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=5000 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK1" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=frame_rate" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="counter_frame_rate_frame_rate0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module frame_rate_altpll1
(
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 10000,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 5000,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk1",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "on",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = wire_pll1_locked;
endmodule //frame_rate_altpll1
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; if (n & (n - 1)) { cout << NO << n ; } else { cout << YES << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_BLACKBOX_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_0_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd0),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; const long long linf = 4000000000000000000LL; const long long inf = 998244353; const long double pi = 3.1415926535; void pv(vector<int> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<long long> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<vector<int>> a) { for (int i = (0); i < (int(a.size())); ++i) { cout << i << n ; pv(a[i]); cout << n ; } } void pv(vector<vector<long long>> a) { for (int i = (0); i < (int(a.size())); ++i) { cout << i << n ; pv(a[i]); } cout << n ; } void pv(vector<string> a) { for (auto& x : a) cout << x << n ; cout << n ; } void build_primes(vector<int>& primes, int size) { vector<int> visited; visited.resize(size, 0); for (int i = (2); i < (size); ++i) { if (visited[i] == 0) { primes.push_back(i); int a = i; while (a < size) { visited[a] = 1; a += i; } } } } vector<vector<long long>> matrix_mult(vector<vector<long long>>& a, vector<vector<long long>>& b) { int n = a.size(); vector<vector<long long>> answer; answer.resize(n); for (int i = 0; i < n; i++) answer[i].resize(n, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { for (int k = 0; k < n; k++) answer[i][j] = (answer[i][j] + a[i][k] * b[k][j]) % inf; } } return answer; } int modInverse(int a, int m) { int m0 = m; int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { int q = a / m; int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long power(long long x, long long y) { long long k = 1LL << 60; long long z = 1; while (k != 0) { z *= z; z %= inf; if (y >= k) { z *= x; z %= inf; y -= k; } k >>= 1; } return z; } struct point { long double x, y; bool operator<(const point& rhs) const { if (x == rhs.x) return y < rhs.y; return x < rhs.x; } }; struct pt { long long x, y; bool operator<(const point& rhs) const { if (x == rhs.x) return y < rhs.y; return x < rhs.x; } }; long double area(point x, point y, point z) { return (x.y * y.x + y.y * z.x + z.y * x.x - x.x * y.y - y.x * z.y - z.x * x.y) / 2.0; } bool clockwise(point x, point y, point z) { return area(x, y, z) > 0; } long double area(pt x, pt y, pt z) { return (x.y * y.x + y.y * z.x + z.y * x.x - x.x * y.y - y.x * z.y - z.x * x.y) / 2.0; } bool clockwise(pt x, pt y, pt z) { return area(x, y, z) > 0; } long long gcd(long long a, long long b) { if (a > b) swap(a, b); if (a == 0) return b; return gcd(a, b % a); } int popcount(long long a) { int count = 0; while (a) { count += (a & 1); a >>= 1; } return count; } long long choose(long long n, long long r) { long long p = 1, k = 1; if (n - r < r) r = n - r; if (r != 0) { while (r) { p *= n; k *= r; long long m = gcd(p, k); p /= m; k /= m; n--; r--; } } else p = 1; return p; } vector<long long> prefix_hash(string& a, vector<long long>& powers) { int n = int(a.size()); vector<long long> prefix(n + 1); for (int i = (0); i < (n); ++i) prefix[i + 1] = (prefix[i] + powers[i] * (a[i] - a + 1)) % inf; return prefix; } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } uint64_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; struct custom_hash_fast { uint64_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); x ^= FIXED_RANDOM; return x ^ (x >> 16); } }; void setIO(string second) { ios_base::sync_with_stdio(0); cin.tie(0); } int main() { setIO( ); int testc; cin >> testc; while (testc--) { int n; cin >> n; string a; cin >> a; int i = n - 1; for (; i >= 0; i--) if ((a[i] - 0 ) & 1) break; if (i == -1) { cout << -1 << n ; continue; } int j = 0; for (; j < i; j++) { if ((a[j] - 0 ) % 2 == 1) break; } if (j == i) { cout << -1 << n ; continue; } cout << a[j] << a[i] << n ; } }
|
#include <bits/stdc++.h> long long p[2750131 + 5]; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } long long left = 0, right = n - 1, past = 0; string s = ; long long flag = 1; while (left < right && flag) { if (a[left] < a[right]) { if (a[left] > past) { s += L ; past = a[left]; left++; } else if (a[right] > past) { s += R ; past = a[right]; right--; } else { flag = 0; } } else if (a[right] < a[left]) { if (a[right] > past) { s += R ; past = a[right]; right--; } else if (a[left] > past) { s += L ; past = a[left]; left++; } else { flag = 0; } } else { if (a[left] <= past) { flag = 0; continue; } past = a[left]; left++; long long sum1 = 1; while (a[left] > past) { sum1++; past = a[left]; left++; } past = a[right]; right--; long long sum2 = 1; while (a[right] > past) { sum2++; past = a[right]; right--; } if (sum1 > sum2) { while (sum1--) { s += L ; } } else { while (sum2--) { s += R ; } } flag = 0; } } if (left == right && flag && a[left] > past) { s += L ; } cout << s.size() << n ; cout << s << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_TB_V
`define SKY130_FD_SC_LP__SRDLXTP_TB_V
/**
* srdlxtp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlxtp.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 SLEEP_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SLEEP_B = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SLEEP_B = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__srdlxtp dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e10; set<long long> s; void bt(long long x) { if (x >= M) return; s.insert(x); bt(x * 10 + 4); bt(x * 10 + 7); } int main() { bt(0); int l, r; cin >> l >> r; long long c = 0; for (set<long long>::iterator it = s.begin(); it != s.end(); it++) { if (*it >= l) { if (r <= *it) { c += (r - l + 1) * *it; break; } else c += (*it - l + 1) * *it; l = *it + 1; } } cout << c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const double pi = acos(-1); void print() { cout << n ; } template <typename T, typename... Params> void print(const T& var1, const Params&... var2) { cout << var1 << ; print(var2...); } template <typename T> void pr(const T& v) { for (auto c : v) cout << c << ; cout << n ; } long long int power(long long int a, long long int b, long long int p) { if (b == 0) return 1; long long int c = power(a, b / 2, p); if (b % 2 == 0) return (c * c) % p; else return (((c * c) % p) * a) % p; } long long int invmod(long long int n, long long int p) { return power(n, p - 2, p); } bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } const int maxN = 100001; int tree[4 * maxN][2]; int A[100000], n; void build(int node, int start, int end) { if (start == end) tree[node][0] = A[start], tree[node][1] = start; else { int mid = (start + end) / 2; build(2 * node, start, mid); build(2 * node + 1, mid + 1, end); tree[node][0] = min(tree[2 * node][0], tree[2 * node + 1][0]); if (tree[2 * node][0] < tree[2 * node + 1][0]) tree[node][1] = tree[2 * node][1]; else tree[node][1] = tree[2 * node + 1][1]; } } pair<int, int> query(int node, int start, int end, int l, int r) { if (r < start or end < l) { return {1e9, 1e9}; } if (l <= start and end <= r) { return make_pair(tree[node][0], tree[node][1]); } int mid = (start + end) / 2; pair<int, int> p1 = query(2 * node, start, mid, l, r); pair<int, int> p2 = query(2 * node + 1, mid + 1, end, l, r); if (p1.first < p2.first) return p1; else return p2; } vector<pair<int, int> > v; int count(int l, int r, int val) { if (l > r) return 0; pair<int, int> q = query(1, 0, n - 1, l, r); int mini = q.first; int idx = q.second; mini -= val; for (long long int i = 0; i < mini; i++) v.push_back({l + 1, r + 1}); return (mini + count(l, idx - 1, val + mini) + count(idx + 1, r, val + mini)); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (long long int i = 0; i < n; i++) cin >> A[i]; build(1, 0, n - 1); print(count(0, n - 1, 0)); for (long long int i = 0; i < ((long long int)(v).size()); i++) print(v[i].first, v[i].second); return 0; }
|
#include <bits/stdc++.h> int n, g, c[6010]; bool p(int x) { if (x == 1) return 0; for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } int main() { scanf( %d , &n); g = n * (n + 1) / 2; if ((g & 1) && (n > 2) && !p(g - 2)) c[3] = 2, g -= 3; for (int i = 0; i < n + 1; i++) if (!c[i] && p(i) && p(g - i)) { c[i] = 1; break; } for (int i = 0; i < n; i++) printf( %d , c[i + 1] + 1); }
|
#include <bits/stdc++.h> using namespace std; #pragma optimize( -O3 ) string to_string(string s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(const bool& b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(const A& v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) res += , ; first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T> inline void _read(T& x) { cin >> x; } template <typename A, typename B> inline void _read(pair<A, B>& x) { _read(x.first); _read(x.second); } template <typename T> inline void _read(vector<T>& x) { for (auto& v : x) _read(v); } void R() {} template <typename T, typename... U> void R(T& head, U&... tail) { _read(head); R(tail...); } template <typename T> inline void _write(const T& x) { cout << x << ; } template <typename A, typename B> inline void _write(const pair<A, B>& x) { _write(x.first); _write(x.second); } template <typename T> inline void _write(const vector<T>& in) { for (const auto& x : in) _write(x); } void W() { cout << n ; } template <typename T, typename... U> void W(const T& head, const U&... tail) { _write(head); W(tail...); } void go(); int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); go(); return 0; } const int M = 1 << 4; const int N = 1 << 17; const int K = 4; const int mod = 1e9 + 7; int dp[N][M][1 << K]; void go() { int n, k, m; R(n, k, m); dp[0][0][0] = 1; for (int i = 0; i < n; i++) for (int j = 0; j <= k; j++) for (int s = 0; s < (1 << m); s++) { int t = (s << 1) % (1 << m); (dp[i + 1][j][t] += dp[i][j][s]) %= mod; if (j < k) { int w = __builtin_popcount(s) + 1; (dp[i + 1][j + 1][t | 1] += 1LL * w * dp[i][j][s] % mod) %= mod; } } long long ans = 0; for (int s = 0; s < (1 << m); s++) (ans += dp[n][k][s]) %= mod; W(ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct ans { int s, t; }; const int nmax = 100006; int n, v[nmax], s1[nmax], s2[nmax], rasp, acts, fp1[nmax], fp2[nmax]; ans vrasp[nmax]; bool ver; int compar(ans a, ans b) { if (a.t != b.t) return a.t < b.t; else return a.s < b.s; } int main() { int player_unu = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i]; s1[i] = s1[i - 1]; s2[i] = s2[i - 1]; if (v[i] == 1) { s1[i]++; fp1[s1[i]] = i; } else { s2[i]++; fp2[s2[i]] = i; } } if (v[n] == 2) for (int i = 1; i <= n; i++) { v[i] = 3 - v[i]; swap(s1[i], s2[i]); swap(fp1[i], fp2[i]); } for (int i = n; i > 0; i--) { if (s1[n] - s1[i - 1] > s2[n] - s2[i - 1] && v[i] == 1) { acts = s1[n] - s1[i - 1]; int nrs1 = 0, nrs2 = 0, pozact = i; ver = 0; for (int j = 0; j < n;) { if (s1[j] + acts > s1[n] && s2[j] + acts > s2[n]) { ver = 1; break; } if (s2[j] + acts > s2[n]) { nrs1++; j = fp1[s1[j] + acts]; continue; } if (s1[j] + acts > s1[n]) { nrs2++; j = fp2[s2[j] + acts]; continue; } if (fp1[s1[j] + acts] < fp2[s2[j] + acts]) { nrs1++; j = fp1[s1[j] + acts]; } else { nrs2++; j = fp2[s2[j] + acts]; } } if (ver == 0 && nrs1 > nrs2) { vrasp[rasp].s = acts; vrasp[rasp].t = nrs1; rasp++; } } } sort(vrasp, vrasp + rasp, compar); cout << rasp << n ; for (int i = 0; i < rasp; i++) cout << vrasp[i].t << << vrasp[i].s << n ; return player_unu; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:48 04/28/2015
// Design Name:
// Module Name: BlackInner
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BlackInner(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
if(((CurrentY < 40) && (CurrentX < 260)) || ((CurrentY < 40) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end
else if(CurrentX < 40) begin
mColor[7:0] <= wall;
end
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int m, long long int n) { if (n == 0) return m; return gcd(n, m % n); } int MOD = 1000000000; long long int powmod(long long int a, long long int b) { if (b == 0) return 1; long long int x = powmod(a, b / 2); long long int y = (x * x) % MOD; if (b % 2) return (a * y) % MOD; return y % MOD; } int main() { std::ios::sync_with_stdio(false); int n, k; cin >> n >> k; int z; int a[10000]; for (int i = 0; i < n; i++) cin >> a[i]; int ans = 0; for (int i = 0; i < n - 1; i++) { if (a[i] > 8) { a[i + 1] = a[i + 1] + a[i] - 8; k = k - 8; } else k = k - a[i]; if (k <= 0) { cout << i + 1 << endl; return 0; } } if (k - min(a[n - 1], 8) > 0) cout << -1 << endl; else cout << n << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:11:12 05/19/2015
// Design Name: top
// Module Name: E:/mips_pipeline/code/test_top.v
// Project Name: mips_pipeline
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_top;
// Inputs
reg CCLK;
reg [3:0] SW;
reg BTNN;
reg BTNE;
reg BTNS;
reg BTNW;
// Outputs
wire [7:0] LED;
wire LCDE;
wire LCDRS;
wire LCDRW;
wire [3:0] LCDDAT;
// Instantiate the Unit Under Test (UUT)
top uut (
.CCLK(CCLK),
.SW(SW),
.BTNN(BTNN),
.BTNE(BTNE),
.BTNS(BTNS),
.BTNW(BTNW),
.LED(LED),
.LCDE(LCDE),
.LCDRS(LCDRS),
.LCDRW(LCDRW),
.LCDDAT(LCDDAT)
);
initial begin
// Initialize Inputs
CCLK = 0;
SW = 0;
BTNN = 0;
BTNE = 0;
BTNS = 0;
BTNW = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#5 BTNE = 1; #5 BTNE = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
end
always #1 CCLK=~CCLK;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, mx = 0, i, j, value; cin >> n; vector<int> v(n + 1, 0); for (i = 1; i <= n; i++) { cin >> v[i]; v[i] += v[i - 1]; } for (i = 1; i <= n; i++) { for (j = 0; j < i; j++) { if ((v[i] - v[j]) > (100 * (i - j))) { mx = max(mx, i - j); break; } } } cout << mx << endl; return 0; }
|
#include <bits/stdc++.h> bool office[25][25]; size_t m, n; bool check(size_t x1, size_t y1, size_t x2, size_t y2) { for (size_t x = x1; x <= x2; ++x) { for (size_t y = y1; y <= y2; ++y) { if (office[x][y]) { return false; } } } return true; } bool check(size_t x, size_t y) { for (size_t i = 0; i < m - x; ++i) { for (size_t j = 0; j < n - y; ++j) { if (check(i, j, i + x, j + y)) { return true; } } } return false; } int main() { std::cin >> m >> n; std::string row; size_t i = 0; while (std::cin >> row) { for (size_t j = 0; j < row.size(); ++j) { office[i][j] = row[j] == 1 ; } ++i; } size_t best = 4; for (size_t x = 0; x < m; ++x) { for (size_t y = 0; y < n; ++y) { size_t p = (x + y + 2) * 2; if (p > best && check(x, y)) { best = p; } } } std::cout << best; }
|
#include <bits/stdc++.h> using namespace std; int t, k; int a, b; int dp[100005]; int sum[100005]; int main() { scanf( %d%d , &t, &k); for (int i = 1; i <= k - 1; i++) { dp[i] = 1; } dp[k] = 2; for (int i = k + 1; i <= 100000; i++) { dp[i] = (dp[i - 1] + dp[i - k]) % 1000000007; } for (int i = 1; i <= 100000; i++) { sum[i] = (sum[i - 1] + dp[i]) % 1000000007; } for (int i = 0; i < t; i++) { scanf( %d%d , &a, &b); printf( %d n , (sum[b] - sum[a - 1] + 1000000007) % 1000000007); } }
|
#include <bits/stdc++.h> using namespace std; int n, x, y; set<pair<int, int> > S, T; int solve(set<pair<int, int> >& s, set<pair<int, int> >& t) { set<pair<int, int> >::iterator it1, it2, it3, it4; it1 = s.begin(); it2 = s.end(); it2--; it3 = t.begin(); it4 = t.end(); it4--; while (it1->first < it2->first || it3->first < it4->first) { int x = it1->first; int xx = (++it1)->first; if (xx > x + 1) { set<pair<int, int> > res_s; set<pair<int, int> > res_t; while (1) { it1 = s.begin(); if (it1->first == xx) break; res_s.insert(make_pair(it1->first, it1->second)); res_t.insert(make_pair(it1->second, it1->first)); s.erase(make_pair(it1->first, it1->second)); t.erase(make_pair(it1->second, it1->first)); } return solve(s, t) + solve(res_s, res_t); } x = it2->first; xx = (--it2)->first; if (xx < x - 1) { set<pair<int, int> > res_s; set<pair<int, int> > res_t; while (1) { it2 = s.end(); it2--; if (it2->first == xx) break; res_s.insert(make_pair(it2->first, it2->second)); res_t.insert(make_pair(it2->second, it2->first)); s.erase(make_pair(it2->first, it2->second)); t.erase(make_pair(it2->second, it2->first)); } return solve(s, t) + solve(res_s, res_t); } int y = it3->first; int yy = (++it3)->first; if (yy > y + 1) { set<pair<int, int> > res_s; set<pair<int, int> > res_t; while (1) { it3 = t.begin(); if (it3->first == yy) break; res_s.insert(make_pair(it3->second, it3->first)); res_t.insert(make_pair(it3->first, it3->second)); s.erase(make_pair(it3->second, it3->first)); t.erase(make_pair(it3->first, it3->second)); } return solve(s, t) + solve(res_s, res_t); } y = it4->first; yy = (--it4)->first; if (yy < y - 1) { set<pair<int, int> > res_s; set<pair<int, int> > res_t; while (1) { it4 = t.end(); it4--; if (it4->first == yy) break; res_s.insert(make_pair(it4->second, it4->first)); res_t.insert(make_pair(it4->first, it4->second)); s.erase(make_pair(it4->second, it4->first)); t.erase(make_pair(it4->first, it4->second)); } return solve(s, t) + solve(res_s, res_t); } } return 1; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); S.insert(make_pair(x, y)); T.insert(make_pair(y, x)); } printf( %d n , solve(S, T)); return 0; }
|
module testbench();
reg [6:0] in_val; //7 bit
reg tb_clk;
wire [31:0] ADDER;
note2dds dds_adder(tb_clk, in_val, ADDER);
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator >>> 4
//; Add input / 64 to accumulator >>> 6
//; Add input / 256 to accumulator >>> 8
//; Add input / 1024 to accumulator >>> 10
//ìóòü, ïðîùå ñäåëàòü case
wire [3:0] x_div12 = (in_val < 12) ? 0 :
(in_val < 24) ? 1 :
(in_val < 36) ? 2 :
(in_val < 48) ? 3 :
(in_val < 60) ? 4 :
(in_val < 72) ? 5 :
(in_val < 84) ? 6 :
(in_val < 96) ? 7 :
(in_val < 108) ? 8 :
(in_val < 120) ? 9 : 10 ;
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting testbench!!!!");
in_val = 0;
repeat (128) begin
#20;
$display("in=", in_val, " div 12 = ", x_div12, " mod12 = ", );
in_val = in_val + 1'b1;
end
$display("finished OK!");
$finish;
end
initial
begin
tb_clk <= 0;
repeat (200000) begin
#1;
tb_clk <= 1;
#1;
tb_clk <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 10; const double pi = acos(-1.0); const double eps = 1e-8; struct node1 { int y, x1, x2; } a[5050]; int tp1; struct node2 { int x, y1, y2; } b[5050]; int tp2; bitset<5050> bs[5050]; int main() { int n; tp1 = tp2 = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { int x1, y1, x2, y2; scanf( %d %d %d %d , &x1, &y1, &x2, &y2); if (x1 == x2) { b[++tp2].x = x1; if (y1 > y2) swap(y1, y2); b[tp2].y1 = y1; b[tp2].y2 = y2; } else { a[++tp1].y = y1; if (x1 > x2) swap(x1, x2); a[tp1].x1 = x1; a[tp1].x2 = x2; } } if (tp1 > tp2) { int tp = max(tp1, tp2); for (int i = 1; i <= tp; i++) { int tmp = a[i].y; a[i].y = b[i].x; b[i].x = tmp; tmp = a[i].x1; a[i].x1 = b[i].y1; b[i].y1 = tmp; tmp = a[i].x2; a[i].x2 = b[i].y2; b[i].y2 = tmp; } swap(tp1, tp2); } for (int i = 1; i <= tp1; i++) { for (int j = 1; j <= tp2; j++) { if (a[i].y >= b[j].y1 && a[i].y <= b[j].y2 && b[j].x >= a[i].x1 && b[j].x <= a[i].x2) { bs[i][j] = 1; } } } long long ans = 0; for (int i = 1; i < tp1; i++) { if (bs[i].count() == 0) continue; for (int j = i + 1; j <= tp1; j++) { bitset<5050> bb = bs[i] & bs[j]; int tmp = bb.count(); ans += tmp * (tmp - 1) / 2; } } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int maxSize = 1 << 16; map<string, int> t; int a[maxSize]; vector<string> s; vector<vector<int> > v; int main() { int n, k; scanf( %d%d , &n, &k); v.resize(n); s.resize(n); for (int i = 0; i < n; i++) { cin >> s[i]; t[s[i]] = i; } for (int i = 0; i < k; i++) { string s1, s2; cin >> s1 >> s2; int x, y; x = t[s1], y = t[s2]; v[x].push_back(y); v[y].push_back(x); } int res = 0, ans = 0; for (int i = 0; i < maxSize; i++) { int cnt = 0; for (int j = 0; j < n; j++) if (i & (1 << j)) cnt++; for (int j = 0; j < n; j++) if (i & (1 << j)) for (int x = 0; x < v[j].size(); x++) if (i & (1 << v[j][x])) { cnt = 0; break; } if (cnt > ans) res = i, ans = cnt; } printf( %d n , ans); set<string> st; for (int i = 0; i < n; i++) if (res & (1 << i)) st.insert(s[i]); for (auto e : st) cout << e << endl; return 0; }
|
//
//
//
//
`define NM1 32'd466 //bB_freq
`define NM2 32'd523 //C_freq
`define NM3 32'd587 //D_freq
`define NM4 32'd622 //bE_freq
`define NM5 32'd698 //F_freq
`define NM6 32'd784 //G_freq
`define NM7 32'd880 //A_freq
`define NM0 32'd20000 //slience (over freq.)
module Music (
input [7:0] ibeatNum,
input clk,
output reg [31:0] tone
);
parameter C = 523;
parameter D = 587;
parameter E = 660;
parameter F = 698;
parameter Fs = 745;
parameter G = 784;
parameter A = 880;
parameter As = 932;
parameter B = 988;
parameter ss = 20000;
always @(posedge clk) begin
case(ibeatNum)
0:tone<=ss;
1:tone<=G;
2:tone<=Fs;
3:tone<=G;
4:tone<=A;
5:tone<=G;
6:tone<=G;
7:tone<=ss;
8:tone<=G;
9:tone<=Fs;
10:tone<=G;
11:tone<=A;
12:tone<=G;
13:tone<=G;
14:tone<=ss;
15:tone<=G;
16:tone<=G;
17:tone<=G;
18:tone<=A;
19:tone<=As;
20:tone<=B;
21:tone<=B;
22:tone<=G;
23:tone<=G;
24:tone<=ss;
25:tone<=C<<1;
26:tone<=B;
27:tone<=C<<1;
28:tone<=B;
29:tone<=C<<1;
30:tone<=C<<1;
31:tone<=B;
32:tone<=C<<1;
33:tone<=B;
34:tone<=A;
35:tone<=G;
36:tone<=A;
37:tone<=G;
38:tone<=A;
39:tone<=A;
40:tone<=G;
41:tone<=A;
42:tone<=B;
43:tone<=C<<1;
44:tone<=B;
45:tone<=C<<1;
46:tone<=B;
47:tone<=C<<1;
48:tone<=C<<1;
49:tone<=B;
50:tone<=C<<1;
51:tone<=B;
52:tone<=A;
53:tone<=G;
54:tone<=A;
55:tone<=G;
56:tone<=A;
57:tone<=A;
58:tone<=G;
59:tone<=A;
60:tone<=B;
61:tone<=C<<1;
62:tone<=B;
63:tone<=C<<1;
64:tone<=B;
65:tone<=C<<1;
66:tone<=C<<1;
67:tone<=B;
68:tone<=C<<1;
69:tone<=B;
70:tone<=A;
71:tone<=G;
72:tone<=A;
73:tone<=G;
74:tone<=A;
75:tone<=A;
76:tone<=G;
77:tone<=A;
78:tone<=B;
79:tone<=C<<1;
80:tone<=B;
81:tone<=C<<1;
82:tone<=B;
83:tone<=C<<1;
84:tone<=C<<1;
85:tone<=B;
86:tone<=C<<1;
87:tone<=B;
88:tone<=A;
89:tone<=G;
90:tone<=A;
91:tone<=G;
92:tone<=A;
93:tone<=A;
94:tone<=G;
95:tone<=A;
96:tone<=B;
97:tone<=E;
98:tone<=E;
99:tone<=F;
100:tone<=G;
101:tone<=C;
102:tone<=C<<1;
103:tone<=B;
104:tone<=A;
105:tone<=G;
106:tone<=F;
107:tone<=F;
108:tone<=F;
109:tone<=D;
110:tone<=D;
111:tone<=E;
112:tone<=F;
113:tone<=B>>1;
114:tone<=B;
115:tone<=A;
116:tone<=G;
117:tone<=A;
118:tone<=G;
119:tone<=G;
120:tone<=G;
121:tone<=E;
122:tone<=E;
123:tone<=F;
124:tone<=G;
125:tone<=C;
126:tone<=C<<1;
127:tone<=B;
128:tone<=A;
129:tone<=G;
130:tone<=F;
131:tone<=F;
132:tone<=F;
133:tone<=F;
134:tone<=G;
135:tone<=A;
136:tone<=B;
137:tone<=B;
138:tone<=G;
139:tone<=G;
140:tone<=A;
141:tone<=A;
142:tone<=B;
143:tone<=B;
144:tone<=C<<1;
145:tone<=C<<1;
146:tone<=C<<1;
147:tone<=ss;
148:tone<=C<<1;
149:tone<=B;
150:tone<=As;
151:tone<=A;
152:tone<=A;
153:tone<=C<<1;
154:tone<=C<<1;
155:tone<=D<<1;
156:tone<=D<<1;
157:tone<=C<<1;
158:tone<=C<<1;
159:tone<=G;
160:tone<=G;
161:tone<=G;
162:tone<=ss;
163:tone<=C<<1;
164:tone<=B;
165:tone<=As;
166:tone<=A;
167:tone<=A;
168:tone<=C<<1;
169:tone<=C<<1;
170:tone<=D<<1;
171:tone<=D<<1;
172:tone<=C<<1;
173:tone<=C<<1;
174:tone<=G;
175:tone<=G;
176:tone<=G;
177:tone<=ss;
178:tone<=C<<1;
179:tone<=B;
180:tone<=As;
181:tone<=A;
182:tone<=A;
183:tone<=C<<1;
184:tone<=C<<1;
185:tone<=D<<1;
186:tone<=D<<1;
187:tone<=C<<1;
188:tone<=D<<1;
189:tone<=E<<1;
190:tone<=D<<1;
191:tone<=E<<1;
192:tone<=C<<1;
193:tone<=C<<1;
194:tone<=ss;
195:tone<=C<<1;
196:tone<=D<<1;
197:tone<=E<<1;
198:tone<=F<<1;
199:tone<=F<<1;
200:tone<=G;
201:tone<=G;
202:tone<=B;
203:tone<=B;
204:tone<=D<<1;
205:tone<=D<<1;
206:tone<=C<<1;
207:tone<=C<<1;
//default:tone<=ss;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long TC = 1; cin >> TC; while (TC--) { int n, f = 1, c = 0; cin >> n; int a[n], feq[110] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; feq[a[i]]++; } sort(a, a + n); for (int i = 0; i < n - 1; i++) { if (a[i + 1] - a[i] > 1) f = 0; } if (f) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, ans = 0, i, temp; vector<int> a; cin >> n; for (i = 0; i < n; i++) { cin >> temp; a.push_back(temp); } sort(a.begin(), a.end()); for (i = 0; i < n; i = i + 2) { if (a[i] != a[i + 1]) { ans += (a[i + 1] - a[i]); } } cout << ans << endl; return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module rxmac_to_ll8
(input clk, input reset, input clear,
input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy );
reg [2:0] xfer_state;
localparam XFER_IDLE = 0;
localparam XFER_ACTIVE = 1;
localparam XFER_ERROR = 2;
localparam XFER_ERROR2 = 3;
localparam XFER_OVERRUN = 4;
localparam XFER_OVERRUN2 = 5;
assign ll_data = rx_data;
assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
| (xfer_state == XFER_ERROR)
| (xfer_state == XFER_OVERRUN));
assign ll_sof = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN);
always @(posedge clk)
if(reset | clear)
xfer_state <= XFER_IDLE;
else
case(xfer_state)
XFER_IDLE :
if(rx_valid)
xfer_state <= XFER_ACTIVE;
XFER_ACTIVE :
if(rx_error)
xfer_state <= XFER_ERROR;
else if(~rx_valid)
xfer_state <= XFER_IDLE;
else if(~ll_dst_rdy)
xfer_state <= XFER_OVERRUN;
XFER_ERROR :
if(ll_dst_rdy)
xfer_state <= XFER_ERROR2;
XFER_ERROR2 :
if(~rx_error)
xfer_state <= XFER_IDLE;
XFER_OVERRUN :
if(ll_dst_rdy)
xfer_state <= XFER_OVERRUN2;
XFER_OVERRUN2 :
if(~rx_valid)
xfer_state <= XFER_IDLE;
endcase // case (xfer_state)
endmodule // rxmac_to_ll8
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits
(
In1,
Out1
);
input [35:0] In1; // ufix36
output [17:0] Out1; // ufix18
wire [17:0] MATLAB_Function_out1; // ufix18
// <S12>/MATLAB Function
controllerHdl_MATLAB_Function u_MATLAB_Function (.u(In1), // ufix36
.y(MATLAB_Function_out1) // ufix18
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module altera_up_audio_bit_counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [ 4: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5005, P = 1e9 + 7; int ad(int k1, int k2) { return k1 += k2 - P, k1 += k1 >> 31 & P; } int su(int k1, int k2) { return k1 -= k2, k1 += k1 >> 31 & P; } int mu(int k1, int k2) { return 1LL * k1 * k2 % P; } void uad(int& k1, int k2) { k1 += k2 - P, k1 += k1 >> 31 & P; } void usu(int& k1, int k2) { k1 -= k2, k1 += k1 >> 31 & P; } template <typename... T> int ad(int k1, T... k2) { return ad(k1, ad(k2...)); } template <typename... T> void uad(int& k1, T... k2) { return uad(k1, ad(k2...)); } template <typename... T> void usu(int& k1, T... k2) { return usu(k1, ad(k2...)); } template <typename... T> int mu(int k1, T... k2) { return mu(k1, mu(k2...)); } int po(int k1, int k2) { int k3 = 1; for (; k2; k2 >>= 1, k1 = mu(k1, k1)) if (k2 & 1) k3 = mu(k3, k1); return k3; } int n, K, a[N], f[N]; int main() { scanf( %d%d , &n, &K); for (int i = (1); i <= (n); ++i) scanf( %d , &a[i]); f[0] = 1; for (int i = (1); i <= (n); ++i) { for (int j = (N - 1); j >= (0); --j) { f[j] = su(mu(f[j], a[i]), j ? f[j - 1] : 0); } } int down = 1, pw = 1, in = po(n, P - 2), ans = 0; for (int i = (0); i <= (N - 1); ++i) { if (i) down = mu(down, K - i + 1), pw = mu(pw, in); ans = ad(ans, mu(down, pw, f[i])); } printf( %d n , su(f[0], ans)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100050; struct node { int sa, ea, sb, eb; } a[N]; int t[N << 1], rt1[N << 1], rt2[N << 1], lc[N * 80], rc[N * 80], tot, n, m1, m2; bool cnt[N * 80], addv[N * 80]; inline bool cmp1(const node &a, const node &b) { return a.ea < b.ea; } inline bool cmp2(const node &a, const node &b) { return a.sa < b.sa; } int add(int pre, int L, int R, int x, int y) { if (addv[pre]) return pre; int o = ++tot; cnt[o] = 1; if (x <= L && y >= R) { addv[o] = 1; lc[o] = lc[pre]; rc[o] = rc[pre]; } else { int M = L + R >> 1; addv[o] = 0; if (x <= M) lc[o] = add(lc[pre], L, M, x, y); else lc[o] = lc[pre]; if (y > M) rc[o] = add(rc[pre], M + 1, R, x, y); else rc[o] = rc[pre]; } return o; } bool ask(int o, int L, int R, int x, int y) { if (addv[o]) return 0; if (x <= L && y >= R) return !cnt[o]; int M = L + R >> 1; return (x > M || ask(lc[o], L, M, x, y)) && (y <= M || ask(rc[o], M + 1, R, x, y)); } inline bool check() { int i, k = 1; memset(rt1, 0, sizeof(rt1)); memset(rt2, 0, sizeof(rt2)); tot = 0; sort(a + 1, a + n + 1, cmp1); for (i = 1; i <= (m1); ++i) { rt1[i] = rt1[i - 1]; for (; k <= n && a[k].ea == i; ++k) rt1[i] = add(rt1[i], 1, m2, a[k].sb, a[k].eb); } sort(a + 1, a + n + 1, cmp2); k = n; for (i = m1; i >= (1); --i) { rt2[i] = rt2[i + 1]; for (; k && a[k].sa == i; --k) rt2[i] = add(rt2[i], 1, m2, a[k].sb, a[k].eb); } for (i = 1; i <= (n); ++i) if (!ask(rt1[a[i].sa - 1], 1, m2, a[i].sb, a[i].eb) || !ask(rt2[a[i].ea + 1], 1, m2, a[i].sb, a[i].eb)) { puts( NO ); return 0; } return 1; } int main() { int i; scanf( %d , &n); for (i = 1; i <= (n); ++i) { scanf( %d%d%d%d , &a[i].sa, &a[i].ea, &a[i].sb, &a[i].eb); t[(i << 1) - 1] = a[i].sa; t[i << 1] = a[i].ea; } sort(t + 1, t + (n << 1) + 1); m1 = unique(t + 1, t + (n << 1) + 1) - t - 1; for (i = 1; i <= (n); ++i) { a[i].sa = lower_bound(t + 1, t + m1 + 1, a[i].sa) - t; a[i].ea = lower_bound(t + 1, t + m1 + 1, a[i].ea) - t; } for (i = 1; i <= (n); ++i) { t[(i << 1) - 1] = a[i].sb; t[i << 1] = a[i].eb; } sort(t + 1, t + (n << 1) + 1); m2 = unique(t + 1, t + (n << 1) + 1) - t - 1; for (i = 1; i <= (n); ++i) { a[i].sb = lower_bound(t + 1, t + m2 + 1, a[i].sb) - t; a[i].eb = lower_bound(t + 1, t + m2 + 1, a[i].eb) - t; } if (!check()) return 0; for (i = 1; i <= (n); ++i) { swap(a[i].sa, a[i].sb); swap(a[i].ea, a[i].eb); } swap(m1, m2); if (check()) puts( YES ); return 0; }
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: intern_sync
*******************************************************************/
`timescale 1ns/1ns
module intern_sync
(
input clk ,
input rstn ,
//-- to/from core----
input rc_is_idle,
//-- to/from reconfiguration controller----
input rc_reqn,
output reg rc_ackn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
/* reconfiguration fsm */
reg [1:0] state_c, state_n;
//-------------------------------------------------------------------
// RC FSM - reconfiguration add-on: decide a safe state
//-------------------------------------------------------------------
localparam [1:0]
RC_Idle = 4'd0,
RC_ReqAck = 4'd1;
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= RC_Idle;
else
state_c <= state_n;
end
always @(*) begin
{rc_ackn} = {1'b1};
/*
mealy fsm:
the ack must rise at the same clock when is_idle comes in
so that the static part can assert reset at the next cycle
when the prm is (potentially) just about to leave the idle state
timing diagram:
reqn => -1- _0_ _0_ _0_ -1- -1-
is_idle <= -1- -1- -1- _0_ -1- -1-
ackn <= -1- -1- -1- _0_ -1- -1-
restn => -1- -1- -1- -1- _0_ _0_
clk edge | | | | | |
*/
case (state_c)
RC_Idle: begin state_n = (~rc_reqn)? RC_ReqAck:RC_Idle; end
RC_ReqAck:begin
if(rc_is_idle) begin
state_n = RC_Idle;
rc_ackn = 1'b0;
end else begin
state_n = RC_ReqAck;
end
end
default: begin state_n = RC_Idle; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, aid = 1, did = 1, atk[105], def[105], c[105]; char s[10]; int main() { cin >> n >> m; for (long long i = 1; i <= n; i++) { scanf( %s , s); if (s[0] == A ) scanf( %lld , &atk[aid++]); else scanf( %lld , &def[did++]); } for (long long i = 1; i <= m; i++) { scanf( %lld , &c[i]); } sort(atk + 1, atk + aid); sort(c + 1, c + m + 1, greater<long long>()); long long indx = 1, sum = 0, off = 0; for (long long i = 1; i <= m; i++) { if (i >= aid) break; if (c[i] < atk[i]) { off = 1; break; } sum += (c[i] - atk[i]); indx = i + 1; } multiset<long long> cel; bool flag = 1; if (off == 1 || indx > m) { goto p; return 0; } for (long long i = indx; i <= m; i++) cel.insert(c[i]); for (long long i = 1; i < did; i++) { auto it = cel.upper_bound(def[i]); if (it == cel.end()) { goto p; } cel.erase(it); } while (!cel.empty()) { auto it = cel.begin(); sum += *it; cel.erase(it); } p: long long sum2 = 0, cnt = 0; multiset<long long> cel2; for (long long i = 1; i <= m; i++) cel2.insert(c[i]); for (long long i = 1; i < did; i++) { auto it = cel2.upper_bound(def[i]); if (it == cel2.end()) continue; cnt++; cel2.erase(it); } for (long long i = 1; i < aid; i++) { auto it = cel2.upper_bound(atk[i]); if (it == cel2.end()) continue; cnt++; sum2 += (*it - atk[i]); cel2.erase(it); } while (!cel2.empty() && cnt == n) { auto it = cel2.begin(); sum2 += *it; cel2.erase(it); } cout << max(sum, sum2) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m; long long getans(long long n) { if (n == 1) return 3 % m; long long k = getans(n / 2); k *= k; if (n % 2) k *= 3; return k % m; } int main() { while (~scanf( %I64d%I64d , &n, &m)) { long long ans = getans(n) - 1; if (ans == -1) ans = m - 1; printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; auto n = 19; auto t = 1; while (true) { auto temp = n; auto sum = 0; while (temp > 0) { auto a = temp % 10; temp = temp / 10; sum = sum + a; } if (sum == 10) { if (t == k) { break; } else { t++; } } n++; } cout << n << n ; }
|
#include <bits/stdc++.h> using namespace std; int power(int a, int b, int c) { long long x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y) % c; } y = (y * y) % c; b /= 2; } return x % c; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } int dp[26][1 << 21]; int main() { long long int n, m; string str1, str2; memset(dp, 0, sizeof(dp)); long long int ans = 0, i; cin >> n >> m; cin >> str1 >> str2; long long int g = gcd(int((str1).size()), int((str2).size())); for (i = 0; i < int((str1).size()); i++) { dp[str1[i] - a ][i % g]++; } for (i = 0; i < int((str2).size()); i++) { ans += dp[str2[i] - a ][i % g]; } ans = int((str2).size()) * m - ans * gcd(n, m); cout << ans << endl; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin( AAtest.in.txt ); long long n, p, t[4][ T ], su; string s; int main() { ios::sync_with_stdio(0); cin >> n; for (int(i) = (0); ((i)) < ((n)); ((i))++) { cin >> s; p = s.size(); p--; t[p][s[p]]++; su++; } for (int(i) = (0); ((i)) < ((n)); ((i))++) { cin >> s; p = s.size(); p--; su -= abs(t[p][s[p]]); t[p][s[p]]--; su += abs(t[p][s[p]]); } cout << su / 2; }
|
/*
*******************************************************************************
* File Name : ada_iaif_stage.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 8th, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Pipeline register: from Instruction Address to Instruction
* Fetch
*******************************************************************************
*/
`include "ada_defines.v"
module ada_iaif_stage(
input clk, // main clock
input rst, // main reset
input [31:0] pc_in, // New PC.
input if_stall, // Stall signal
output reg [31:0] pc_out // PC to IF stage
);
//--------------------------------------------------------------------------
// A simple register
// Do not update PC if IF stage is stalled.
//--------------------------------------------------------------------------
always @(posedge clk ) begin
pc_out <= (rst) ? `ADA_RESET_DEFAULT : ((if_stall) ? pc_out : pc_in);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, ans = -1; cin >> n; pair<int, int> g[n]; for (i = 0; i < n; i++) { cin >> g[i].first >> g[i].second; } sort(g, g + n); for (i = 0; i < n; i++) { if (ans <= g[i].second) ans = g[i].second; else ans = g[i].first; } cout << ans; }
|
/***************************************************************************************************
* *
* Module: Altera_UP_PS2_Command_Out *
* Description: *
* This module sends commands out to the PS2 core. *
* Retrived from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html *
***************************************************************************************************/
module Altera_UP_PS2_Command_Out (
// Inputs
clk,
reset,
the_command,
send_command,
ps2_clk_posedge,
ps2_clk_negedge,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
command_was_sent,
error_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_101US = 5050;
parameter NUMBER_OF_BITS_FOR_101US = 13;
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001;
//parameter CLOCK_CYCLES_FOR_101US = 50;
//parameter NUMBER_OF_BITS_FOR_101US = 6;
//parameter COUNTER_INCREMENT_FOR_101US = 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter NUMBER_OF_BITS_FOR_15MS = 20;
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 100000;
parameter NUMBER_OF_BITS_FOR_2MS = 17;
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [7:0] the_command;
input send_command;
input ps2_clk_posedge;
input ps2_clk_negedge;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output reg command_was_sent;
output reg error_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [3:0] cur_bit;
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
// State Machine Registers
reg [2:0] ns_ps2_transmitter;
reg [2:0] s_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_transmitter <= PS2_STATE_0_IDLE;
else
s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
// Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1)
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
ps2_command <= 9'h000;
else if (s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else
begin
if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if (transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
cur_bit <= 4'h0;
else if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_was_sent <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if (send_command == 1'b0)
command_was_sent <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
error_communication_timed_out <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if (send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK =
(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
1'b0 :
1'bz;
assign PS2_DAT =
(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2005, mod = 998244353; int n, a[N][N], f[N][N], jie[N], ans, vis1[N], vis2[N], c[N], c2[N], vis3[N]; inline int qpow(int a, int b, int res = 1) { for (; b; b >>= 1, a = 1ll * a * a % mod) if (b & 1) res = 1ll * res * a % mod; return res; } void init() { jie[0] = 1; for (register int i = 1; i <= n; ++i) jie[i] = 1ll * jie[i - 1] * i % mod; f[0][0] = 1, f[1][1] = 1; for (register int i = 2; i <= n; i++) { f[i][0] = 1ll * (i - 1) * (f[i - 1][0] + f[i - 2][0]) % mod; for (register int j = 1; j <= i; j++) f[i][j] = (f[i][j - 1] + f[i - 1][j - 1]) % mod; } } inline int lowbit(int x) { return x & -x; } inline void add(int x, int y) { for (; x <= n; x += lowbit(x)) c[x] += y; } inline int get(int x, int res = 0) { for (; x; x -= lowbit(x)) res += c[x]; return res; } inline void add2(int x, int y) { for (; x <= n; x += lowbit(x)) c2[x] += y; } inline int get2(int x, int res = 0) { for (; x; x -= lowbit(x)) res += c2[x]; return res; } signed main() { scanf( %d , &n); init(); for (register int i = 1; i <= n; ++i) { int tmp = qpow(f[n][0], n - i), res = 0, num = 0; memset(vis1, 0, sizeof(vis1)), memset(vis2, 0, sizeof(vis2)); memset(vis3, 0, sizeof(vis3)); memset(c, 0, sizeof(c)), memset(c2, 0, sizeof(c2)); for (register int j = 1; j <= n; ++j) add(j, 1), add2(j, 1); for (register int j = 1; j <= n; ++j) { scanf( %d , &a[i][j]); if (i == 1) { int cnt = get(a[i][j] - 1); res = (res + 1ll * cnt * jie[n - j] % mod) % mod; add(a[i][j], -1); } else { vis1[a[i - 1][j]] = 1; if (vis3[a[i - 1][j]] == 0) add2(a[i - 1][j], -1), vis3[a[i - 1][j]] = 1; if (vis2[a[i - 1][j]]) num--; int cnt = get(a[i][j] - 1); if (a[i - 1][j] < a[i][j] && get(a[i - 1][j]) - get(a[i - 1][j] - 1)) cnt--; int cnt1 = get2(a[i][j] - 1), cnt2 = 0; if (a[i - 1][j] < a[i][j] && get2(a[i - 1][j]) - get2(a[i - 1][j] - 1)) cnt1--; cnt2 = cnt - cnt1; res = (res + 1ll * cnt1 * f[n - j][num + 1] % mod) % mod; res = (res + 1ll * cnt2 * f[n - j][num] % mod) % mod; vis2[a[i][j]] = 1; add(a[i][j], -1); if (!vis3[a[i][j]]) add2(a[i][j], -1), vis3[a[i][j]] = 1; if (!vis1[a[i][j]]) num++; } } ans = (ans + 1ll * res * tmp % mod) % mod; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int K, N; long double XX, YY, P[101], PP, arr[101][101], obj[101][2], EPS = 1e-9; double calk(int n, int k) { if (arr[n][k] != -1) return arr[n][k]; double retAns = 0; if (n == 1 && k == 1) arr[n][k] = P[1]; else if (n == 1 && k == 0) arr[n][k] = 1 - P[1]; else if (n == 0 || k > n || k < 0) arr[n][k] = 0; else { double v1 = calk(n - 1, k - 1) * P[n]; double v2 = calk(n - 1, k) * (1 - P[n]); arr[n][k] = calk(n - 1, k - 1) * P[n] + calk(n - 1, k) * (1 - P[n]); } return arr[n][k]; } double calcDist(double x, double y) { return (x - XX) * (x - XX) + (y - YY) * (y - YY); } double calk2(double r) { double retAns = 0; for (int i = 0; i <= N; i++) { for (int j = 0; j <= N; j++) arr[i][j] = -1; if (i) { double t = calcDist(obj[i][0], obj[i][1]); if (r * r > EPS && t > r * r) P[i] = exp(1.0 - t / (r * r)); else P[i] = 1.0; } } int g; for (int k = K; k <= N; k++) retAns += calk(N, k); return retAns; } double binS(double l, double r) { if (fabs(l - r) < EPS) return l; double mid = l + (r - l) / 2.0; if (calk2(mid) > PP) return binS(l, mid); else return binS(mid, r); } int main() { cin >> N >> K; double tp; cin >> tp; tp /= 1000; tp = 1.0 - tp; PP = tp; cin >> XX >> YY; for (int i = 1; i <= N; i++) cin >> obj[i][0] >> obj[i][1]; cout.setf(ios::fixed); cout.precision(10); cout << binS(0, 10000); return 0; }
|
//Test Bench for Multiplier Functional Unit
module MultiplierTB;
reg clk, reset;
wire [15:0] result;
reg [7:0] x, y;
wire ready;
//Data containing 0
reg [7:0] test0Data = 8'b00000000;
//Data containing 1
reg [7:0] test1Data = 8'b00000001;
//Data for testing left and right multiplication with identity (1)
//gives the data
reg [7:0] testLeftIdentity = 8'd67;
reg [7:0] testRightIdentity = 8'd96;
// Data for testing multiplying by 0 on lhs and rhs still gives 0
reg [7:0] testLHS0Data = 8'd37;
reg [7:0] testRHS0Data = 8'd96;
// Data for testing 2 regular numbers multiply correctly
reg [7:0] testRegularData1 = 8'd20;
reg [7:0] testRegularData2 = 8'd10;
reg [7:0] test2RegularData1 = 8'd255;
reg [7:0] test2RegularData2= 8'd255;
defparam m1.bits = 8;
multiplier m1 (clk, reset, x, y, result, ready);
initial begin
clk = 0;
reset = 0;
end
initial begin
$monitor("time:%t\treset: %b\tready: %b\tresult: %d\nx: %d\ty: %d", $time, reset, ready, result, x, y);
end
initial begin
#50 begin $display("Starting test 1"); reset = 1; x = testRegularData1; y = testRegularData2; end
#11 reset = 0;
#70 begin $display("Starting test 2"); reset = 1; x = test2RegularData1; y = test2RegularData2; end
#11 reset = 0;
#200 begin $display("Starting test 3"); reset = 1; x = test0Data; y = test0Data; end //Test 0x0 == 0
#11 reset = 0;
#50 begin $display("Starting test 4"); reset = 1; x = testLHS0Data; y = test0Data; end //Test x*0 == 0
#11 reset = 0;
#50 begin $display("Starting test 5"); reset = 1; x = test0Data; y = testRHS0Data; end //Test 0*x == 0
#11 reset = 0;
#50 begin $display("Starting test 6"); reset = 1; x = test1Data; y = testLeftIdentity; end //Test 1*x == x
#11 reset = 0;
#50 begin $display("Starting test 7"); reset = 1;x = testRightIdentity; y = test1Data; end //Test x*1 == x
#11 reset = 0;
#80 $finish;
end
//Simulate Clock
always begin
#5 clk = !clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = (int)1e6 + 10; int mod = (int)1e9 + 7; int sum(int a, int b) { int s = a + b; if (s >= mod) s -= mod; return s; } int n; int mult(int a, int b) { return (1LL * a * b) % mod; } int a[maxN]; int inv[maxN]; int fact; void calc() { inv[1] = 1; for (int i = 2; i < maxN; i++) { inv[i] = mult((mod - (mod / i)), inv[mod % i]); } fact = 1; for (int i = 2; i <= n; i++) fact = mult(fact, i); } int main() { ios_base::sync_with_stdio(false); srand(time(0)); srand(time(0)); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } calc(); sort(a + 1, a + n + 1); int mx = a[n]; int ans = 0; int x = 0; int prv = 0; int sz = 1; for (int i = 1; i <= n; i++) { if (a[i] == mx) break; if (i > 1) { if (a[i] == a[i - 1]) sz++; else { prv = prv + sz; sz = 1; } } ans = sum(ans, mult(mult(a[i], fact), inv[n - prv])); } cout << ans << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e6 + 1; const int INF = 2e9 + 1; const int MOD = (1e9 + 7); void bye(string s = ) { cout << s << n ; exit(0); } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; cin >> t; while (t--) { int n; cin >> n; vector<int> arr(2); for (int i = 0; i < n; i++) { int a; cin >> a; arr[a % 2]++; } if (arr[1] % 2 || (arr[1] && arr[0])) { cout << YES n ; } else { cout << NO n ; } } bye(); }
|
#include <bits/stdc++.h> const double PI = 3.1415926; const int KL = 1e6; using namespace std; long long q, x, y, z, n, m, p[KL], mn = 1e9, mx = -1e9, ans; string t; vector<int> vec[KL]; set<int> s; map<int, int> M; int pr[KL], sz[KL]; int prfind(int node) { if (pr[node] == node) return node; else return pr[node] = prfind(pr[node]); } void make_group(int node1, int node2) { int fa1 = prfind(node1); int fa2 = prfind(node2); if (fa1 == fa2) return; if (sz[fa1] >= sz[fa2]) { pr[fa2] = fa1; sz[fa1] += sz[fa2]; } else { pr[fa1] = fa2; sz[fa2] += sz[fa1]; } } int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &x); for (int j = 0; j < x; j++) { scanf( %d , &y); vec[i].push_back(y); } } for (int i = 1; i <= n; i++) { pr[i] = i; sz[i] = 1; } for (int i = 0; i < m; i++) { for (int j = 1; j < vec[i].size(); j++) { make_group(vec[i][j], vec[i][j - 1]); } } for (int i = 1; i <= n; i++) { cout << sz[prfind(i)] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; unsigned int dp[100100]; char s[100100]; int main() { unsigned int n; cin >> n; if (n & 1) { return !printf( 0 ); } scanf( %s , s + 1); int m = n / 2; dp[0] = 1; for (int i = 1; i <= n; i++) { if (s[i] == ? ) { for (int j = i / 2; j >= max(1, i - m); j--) dp[j] += dp[j - 1]; } } for (int i = 1; i <= n; i++) { if (s[i] == ? ) continue; m--; } for (int i = 1; i <= m; i++) dp[n / 2] *= 25; cout << dp[n / 2] << n ; return 0; }
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Three-clause BSD Licence
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* - The names of contributors may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*)
Require Import Eqdep List Omega.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Abort to backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => try rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
#include <bits/stdc++.h> using namespace std; int FASTBUFFER; const int N = 1005; const int INF = 1000000000; char str[N][N]; int n, m, l[N], r[N]; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , str[i] + 1); } for (int i = 1; i <= n; i++) { int ll = m + 1, rr = 0; for (int j = 1; j <= m; j++) { if (str[i][j] == X ) { ll = j; break; } } for (int j = m; j >= 1; j--) { if (str[i][j] == X ) { rr = j; break; } } for (int j = ll; j <= rr; j++) { if (str[i][j] != X ) { printf( -1 n ); return 0; } } l[i] = ll, r[i] = rr; } int st, end; for (int i = 1; i <= n; i++) { if (l[i] != m + 1) { st = i; break; } } for (int i = n; i >= 1; i--) { if (l[i] != m + 1) { end = i; break; } } for (int i = st; i <= end; i++) { if (l[i] == m + 1) { printf( -1 n ); return 0; } } int ans1 = -1, ans2 = -1, flag = 0; for (int i = st + 1; i <= end; i++) { if (l[i] < l[i - 1] || r[i] < r[i - 1]) { printf( -1 n ); return 0; } if (l[i] > r[i - 1]) { printf( -1 n ); return 0; } if (r[i] > r[i - 1]) { flag = 1; } if (l[i] > l[i - 1] && ans1 == -1) { int last; for (last = i - 1; last >= st; last--) { if (r[last] != r[i]) { break; } } if (last < st) { last++; } ans1 = r[last] - l[i] + 1; } } int ans = INF; if (ans1 == -1) { if (st == end) { printf( 1 n ); return 0; } else { if (flag) { ans1 = r[st] - l[st] + 1; } else { printf( %d n , min(end - st + 1, r[st] - l[st] + 1)); return 0; } } } for (int ans1 = 1; ans1 <= r[st] - l[st] + 1; ans1++) { for (int ans2 = 1; ans2 <= end - st + 1; ans2++) { int ok = 1; for (int i = st; i <= st + ans2 - 1; i++) { if (l[i] != l[st]) { ok = 0; break; } } if (ok) { int top = st, bo = st + ans2 - 1, now = l[st]; while (bo < end) { while (r[top] > now + ans1 - 1) { now++; } top++; bo++; if (now + ans1 - 1 > r[top]) { ok = 0; } if (now != l[bo]) { ok = 0; } } for (int i = top; i <= bo; i++) { if (r[i] != r[top]) { ok = 0; } } } if (ok) { ans = min(ans, ans1 * ans2); } } } if (ans == INF) { printf( -1 n ); return 0; } else { printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_4_V
`define SKY130_FD_SC_HD__A31O_4_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_4_V
|
parameter DW = 16;
parameter AW = 8;
module pllclk (input ext_clock, output pll_clock, input nrst, output lock);
wire dummy_out;
wire bypass, lock1;
assign bypass = 1'b0;
// DIVR=0 DIVF=71 DIVQ=3 freq=12/1*72/8 = 108 MHz
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"), .PLLOUT_SELECT("GENCLK"),
.DIVR(4'd0), .DIVF(7'b1000111), .DIVQ(3'b011),
.FILTER_RANGE(3'b001)
) mypll1 (.REFERENCECLK(ext_clock),
.PLLOUTGLOBAL(pll_clock), .PLLOUTCORE(dummy_out), .LOCK(lock1),
.RESETB(nrst), .BYPASS(bypass));
endmodule
module dff #(parameter W=1)
(input wire[W-1:0] D, input clk, output reg[W-1:0] Q);
always @(posedge clk)
Q <= D;
endmodule // dff
module synchroniser #(parameter W=1)
(input wire[W-1:0] D, input clk, output wire[W-1:0] Q);
wire[W-1:0] M;
dff #(W) first_reg(D, clk, M);
dff #(W) last_reg(M, clk, Q);
endmodule
module clocked_bus_slave #(parameter ADRW=1, DATW=1)
(input aNE, aNOE, aNWE,
input wire [ADRW-1:0] aAn, input wire[DATW-1:0] aDn,
input clk,
output wire[ADRW-1:0] r_adr, output wire[ADRW-1:0] w_adr,
output reg do_read, input wire[DATW-1:0] read_data,
output reg do_write, output reg[DATW-1:0] w_data,
output io_output, output wire[DATW-1:0] io_data);
wire sNE, sNOE, sNWE;
reg[ADRW-1:0] sAn_r;
reg[ADRW-1:0] sAn_w;
reg[DATW-1:0] rDn;
reg[DATW-1:0] wDn;
wire[ADRW-1:0] next_sAn_r;
wire[ADRW-1:0] next_sAn_w;
wire[DATW-1:0] next_rDn;
wire[DATW-1:0] next_wDn;
wire next_do_write, next_do_read;
// States for one-hot state machine.
reg st_idle=1, st_write=0, st_read1=0, st_read2=0;
wire next_st_idle, next_st_write, next_st_read1, next_st_read2;
synchroniser sync_NE(aNE, clk, sNE);
synchroniser sync_NOE(aNOE, clk, sNOE);
synchroniser sync_NWE(aNWE, clk, sNWE);
always @(posedge clk) begin
st_idle <= next_st_idle;
st_write <= next_st_write;
st_read1 <= next_st_read1;
st_read2 <= next_st_read2;
do_write <= next_do_write;
do_read <= next_do_read;
sAn_r <= next_sAn_r;
sAn_w <= next_sAn_w;
wDn <= next_wDn;
rDn <= next_rDn;
end
/* Latch the address on the falling edge of NOE (read) or NWE (write).
We can use the external address unsynchronised, as it will be stable
when NOE/NWE toggles.
*/
assign next_sAn_r = st_idle & ~sNE & ~sNOE ? aAn : sAn_r;
assign next_sAn_w = st_idle & ~sNE & ~sNWE ? aAn : sAn_w;
/* Incoming write. */
/* Latch the write data on the falling edge of NWE. NWE is synchronised,
so the synchronisation delay is enough to ensure that the async external
data signal is stable at this point.
*/
assign next_wDn = st_idle & ~sNE & ~sNWE ? aDn : wDn;
// Trigger a register write when NWE goes low.
assign next_do_write = st_idle & ~sNE & ~sNWE;
assign next_st_write = (st_idle | st_write) & (~sNE & ~sNWE);
/* Incoming read. */
assign next_do_read = st_idle & ~sNE & ~sNOE;
/* Wait one cycle for register read data to become available. */
assign next_st_read1 = st_idle & ~sNE & ~sNOE;
/* Put read data on the bus while NOE is asserted. */
assign next_st_read2 = (st_read1 | st_read2) & ~sNE & ~sNOE;
assign next_st_idle = ((st_read1 | st_read2) & (sNOE | sNE)) |
(st_write & (sNWE | sNE)) |
(st_idle & (sNE | (sNOE & sNWE)));
/* Latch register read data one cycle after asserting do_read. */
assign next_rDn = st_read1 ? read_data : rDn;
/* Output data during read after latching read data. */
assign io_output = st_read2 & next_st_read2;
assign io_data = rDn;
assign r_adr = sAn_r;
assign w_adr = sAn_w;
assign w_data = wDn;
endmodule // clocked_bus_slave
module top (
/* FSMC */
input crystal_clk,
input STM32_PIN,
input aNE, aNOE, aNWE,
input [AW-1:0] aA,
inout [DW-1:0] aD,
//output [7:0] LED,
input uart_tx_in, output uart_tx_out,
/* VGA */
output [2:0] red, green, blue,
output hsync, vsync
);
wire clk;
wire nrst, lock;
wire [7:0] pulse_counter;
wire[DW-1:0] aDn_output;
wire[DW-1:0] aDn_input;
wire io_d_output;
wire do_write;
wire[AW-1:0] r_adr;
wire[AW-1:0] w_adr;
wire[DW-1:0] w_data;
wire do_read;
wire[DW-1:0] register_data;
wire chk_err;
wire[7:0] err_count;
/* Type 101001 is output with tristate/enable and simple input. */
SB_IO #(.PIN_TYPE(6'b1010_01), .PULLUP(1'b0))
io_Dn[DW-1:0](.PACKAGE_PIN(aD),
.OUTPUT_ENABLE(io_d_output),
.D_OUT_0(aDn_output),
.D_IN_0(aDn_input)
);
assign nrst = 1'b1;
pllclk my_pll(crystal_clk, clk, nrst, lock);
clocked_bus_slave #(.ADRW(AW), .DATW(DW))
my_bus_slave(aNE, aNOE, aNWE,
aA, aDn_input,
clk, r_adr, w_adr,
do_read, register_data,
do_write, w_data,
io_d_output, aDn_output);
/* The clocked_bus_slave asserts do_read once per read transaction on the
external bus (synchronous on clk). This can be used to have side effects
on read (eg. clear "data ready" on read of data register). However, in
this particular case we have no such side effects, so can just decode
the read data continously (clocked_bus_slave latches the read value).
*/
always @(*) begin
case (r_adr)
default: register_data <= 0;
endcase // case (r_adr)
end
reg [15:0] chadr;
reg [7:0] chdata;
reg chbuf_w;
reg chadr_inc;
always @(posedge clk) begin
if (do_write) begin
case (w_adr)
8'h00: begin
// Write charbuf address
chadr <= w_data;
end
8'h02: begin
// Write charbuf data
chdata <= w_data[7:0];
chbuf_w <= 1'b1;
end
8'h03: begin
// Write charbuf data with auto-increment of address
chdata <= w_data[7:0];
chbuf_w <= 1'b1;
chadr_inc <= 1'b1;
end
endcase
end else begin
if (chbuf_w == 1'b1) begin
chbuf_w <= 1'b0;
end
if (chadr_inc == 1'b1) begin
chadr <= chadr + 1;
chadr_inc <= 1'b0;
end
end
end // always @ (posedge_clk)
/* For debugging, proxy an UART Tx signal to the FTDI chip. */
assign uart_tx_out = uart_tx_in;
/* vga stuff */
wire vga_clk = clk;
wire [11:0] x, y;
wire fb_enable, fb_reset;
wire i_hsync, i_vsync;
wire [11:0] pixel_count, line_count;
vga_blank blank(vga_clk, pixel_count, line_count, i_hsync, i_vsync, fb_reset, fb_enable);
vga_adr_trans #(.FB_X_MAX(1280), .FB_Y_MAX(1024)) trans(vga_clk, pixel_count, line_count, fb_reset, fb_enable, x, y);
wire [7:0] w_col, w_row;
wire [7:0] buf_out;
assign w_col = w_adr;
char_buf buffer(vga_clk, chbuf_w, y[10:4], x[10:3], chadr[13:0], chdata, buf_out);
wire [7:0] pixels;
font_rom rom(vga_clk, y[3:0], buf_out, pixels);
reg pixel;
reg [2:0] ascii_x;
always @(posedge vga_clk) begin
pixel <= pixels[ascii_x];
ascii_x <= ~(x[2:0]-1);
end
// Buffer output lines.
always @(posedge vga_clk) begin
red <= ~fb_enable ? 0 : (pixel ? 'b11 : 0);
green <= ~fb_enable ? 0 : (pixel ? 'b11 : 0);
blue <= 0;
hsync <= i_hsync;
vsync <= i_vsync;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_FAST_t_opr_core_buf_val_0_V_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1927;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_FAST_t_opr_core_buf_val_0_V(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1927;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
image_filter_FAST_t_opr_core_buf_val_0_V_ram image_filter_FAST_t_opr_core_buf_val_0_V_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ans, k, d, cnt1, cnt2, l, r; int a[200050]; struct node { int x, b; }; node s[200050]; int main() { k = 1; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } l = 1, r = n, s[0].x = 0; d = 0; while ((a[l] > s[d].x || a[r] > s[d].x) && l <= r) { if (a[l] != a[r]) { if (a[l] < a[r] && a[l] > s[d].x || (a[l] > a[r] && a[r] <= s[d].x)) { d++; s[d].x = a[l]; s[d].b = 0; ans = d; l++; continue; } if (a[r] > s[d].x) { d++; s[d].x = a[r]; s[d].b = 1; ans = d; r--; continue; } } if (a[l] == a[r] && l != r) { k = 0; cnt1 = 0, cnt2 = 0; for (int j = l; j <= r - 1; ++j) { if (a[j + 1] > a[j]) cnt1++; else break; } for (int j = r; j >= l + 1; --j) { if (a[j] < a[j - 1]) cnt2++; else break; } if (cnt1 >= cnt2) { ans += cnt1 + 1; printf( %d n , ans); for (int j = 1; j <= ans - cnt1 - 1; ++j) { if (s[j].b == 0) printf( L ); else printf( R ); } for (int j = 0; j < cnt1 + 1; ++j) { printf( L ); } break; } if (cnt1 < cnt2) { ans += cnt2 + 1; printf( %d n , ans); for (int j = 1; j <= ans - cnt2 - 1; ++j) { if (s[j].b == 0) printf( L ); else printf( R ); } for (int j = 0; j < cnt2 + 1; ++j) { printf( R ); } break; } } if (l == r && k == 1) { ans++; s[ans].b = 1; break; } } if (k == 1) { printf( %d n , ans); for (int i = 1; i <= ans; ++i) { if (s[i].b == 0) printf( L ); else printf( R ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int up, down; int people = 0; int max = 0; cin >> n; while (n--) { cin >> up >> down; people = people - up + down; if (people > max) max = people; } cout << max << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[15]; char rr[15]; char ans[15]; int main() { int maxx = -99; cin >> a; int len = strlen(a); for (int i = 1; i < 1 << len; i++) { int cnt = 0; for (int j = 0; j <= len - 1; j++) { if (i >> j & 1) rr[++cnt] = a[j]; } int flag = 0; for (int l = 1, r = cnt; l <= r; l++, r--) { if (rr[l] != rr[r]) { flag = 1; break; } } if (flag == 0) { if (strcmp(ans + 1, rr + 1) < 0) { for (int i = 1; i <= 14; i++) { if (i <= cnt) ans[i] = rr[i]; else ans[i] = 0 ; } } } } cout << ans + 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long dx[] = {-1, 0, 1, 0}; long long dy[] = {0, -1, 0, 1}; vector<long long> v(10); string s; set<string> st; void call(string s, long long pos) { if (pos == 10) { sort(s.begin(), s.end()); st.insert(s); return; } if (v[pos] == 0) { call(s, pos + 1); return; } for (long long i = 1; i <= v[pos]; i++) { char c = 0 + pos; string x = string(i, c); call(s + x, pos + 1); } } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); vector<long long> f(20); f[0] = f[1] = 1; for (long long i = 2; i < 20; i++) { f[i] = f[i - 1] * i; } cin >> s; for (long long i = 0; i < s.size(); i++) v[s[i] - 0 ]++; string x = ; call(x, 0); long long ans = 0; for (auto i : st) { string &x = i; vector<long long> cnt(10); for (long long i = 0; i < x.size(); i++) { cnt[x[i] - 0 ]++; } long long val = f[x.size()]; for (long long i = 0; i < 10; i++) { val = val / f[cnt[i]]; } ans += val; if (v[0] > 0) { long long val1 = f[x.size() - 1]; cnt[0]--; for (long long i = 0; i < 10; i++) val1 = val1 / f[cnt[i]]; ans -= val1; } } cout << ans << n ; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: register.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: A simple parameterized register
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module register
#(parameter C_WIDTH = 1,
parameter C_VALUE = 0
)
(input CLK,
input RST_IN,
output [C_WIDTH-1:0] RD_DATA,
input [C_WIDTH-1:0] WR_DATA,
input WR_EN
);
reg [C_WIDTH-1:0] rData;
assign RD_DATA = rData;
always @(posedge CLK) begin
if(RST_IN) begin
rData <= C_VALUE;
end else if(WR_EN) begin
rData <= WR_DATA;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
int cnt_ar2d;
// sizes
int siz_bit ;
int siz_byte;
int siz_int ;
int siz_ar1d;
int siz_ar2d;
// add all counters
assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
// finish report
always @ (posedge clk)
if (cnt == 5) begin
if (siz_bit != 1) $stop();
if (siz_byte != 8) $stop();
if (siz_int != 32) $stop();
if (siz_ar1d != 24) $stop();
if (siz_ar2d != 16) $stop();
end else if (cnt > 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
// instances with various types
mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit );
mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int );
mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
endmodule : t
module mod_typ #(
parameter type TYP = byte
)(
input logic clk,
output TYP cnt,
output int siz
);
initial cnt = 0;
always @ (posedge clk)
cnt <= cnt + 1;
assign siz = $bits (cnt);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ans[16]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; if (!(n & 1)) { cout << 0 << n ; return 0; } ans[1] = 1; ans[3] = 18; ans[5] = 1800; ans[7] = 670320; ans[9] = 734832000; ans[11] = 890786230; ans[13] = 695720788; ans[15] = 150347555; cout << ans[n] << n ; return 0; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lcd_display (
// inputs:
address,
begintransfer,
read,
write,
writedata,
// outputs:
LCD_E,
LCD_RS,
LCD_RW,
LCD_data,
readdata
)
;
output LCD_E;
output LCD_RS;
output LCD_RW;
inout [ 7: 0] LCD_data;
output [ 7: 0] readdata;
input [ 1: 0] address;
input begintransfer;
input read;
input write;
input [ 7: 0] writedata;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [ 7: 0] LCD_data;
wire [ 7: 0] readdata;
assign LCD_RW = address[0];
assign LCD_RS = address[1];
assign LCD_E = read | write;
assign LCD_data = (address[0]) ? 8'bz : writedata;
assign readdata = LCD_data;
//control_slave, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n, i; scanf( %d , &n); printf( %d , n); for ((i) = 0; (i) < (int)(n - 1); (i)++) printf( %d , i + 1); printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_TB_V
`define SKY130_FD_SC_MS__DLXBP_TB_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; void solve() { string s; cin >> s; int cntr1 = 10, cntr2 = 10; int wt1 = 0, wt2 = 0; for (int i = 0; i < 10; i++) { if (i % 2 == 0) { if (s[i] == 1 || s[i] == ? ) wt1++; } else { if (s[i] == 1 ) wt2++; } int left_t1 = 0, left_t2 = 0; for (int j = i + 1; j < 10; j++) { if (j % 2 == 0) { left_t1++; } else { left_t2++; } } if (wt1 > wt2 + left_t2) { cntr1 = i + 1; break; } if (wt2 > wt1 + left_t1) { cntr1 = i + 1; break; } } wt1 = 0, wt2 = 0; for (int i = 0; i < 10; i++) { if (i % 2 == 0) { if (s[i] == 1 ) wt1++; } else { if (s[i] == 1 || s[i] == ? ) wt2++; } int left_t1 = 0, left_t2 = 0; for (int j = i + 1; j < 10; j++) { if (j % 2 == 0) { left_t1++; } else { left_t2++; } } if (wt1 > wt2 + left_t2) { cntr2 = i + 1; break; } if (wt2 > wt1 + left_t1) { cntr2 = i + 1; break; } } cout << min(cntr1, cntr2); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t-- > 0) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int y, ne; } e[200010]; int f[100005], h[100005], np, vis[100005], s; long long dp[100005], r[100005]; long long saya(int n) { if (dp[n] != -1) return dp[n]; vis[n] = 1; long long ans = 0, res = 0; vector<long long> v; for (int i = h[n]; i; i = e[i].ne) { if (!vis[e[i].y]) { v.push_back(saya(e[i].y)); res += r[e[i].y]; } } sort(v.begin(), v.end()); int j = f[n] - 1; if (n == s) j++; for (int i = v.size() - 1; i >= 0 && j > 0; i--, j--) { ans += v[i]; } if (j != 0) { ans += 2 * min(res, 1ll * j); r[n] = j - min(res, 1ll * j); } ans += f[n] - j; return dp[n] = ans; } void add(int a, int b) { e[np].y = b; e[np].ne = h[a]; h[a] = np; np++; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &f[i]); np = 1; for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); add(a, b); add(b, a); } scanf( %d , &s); memset(dp, -1, sizeof(dp)); printf( %I64d n , saya(s)); }
|
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Firmware/UART/Hardware/UAReceiver.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//==============================================================================
// Section: Includes
//==============================================================================
`include "Const.v"
//==============================================================================
//------------------------------------------------------------------------------
// Module: UAReceiver
// Desc: Standard Universal Asynchronous RS232/16550 type receiver.
// Params: ClockFreq: Frequency (in Hz) of the "Clock" being fed to this
// module.
// Baud: Desired Baud rate. This is the rate at which this
// module will send bits, and should be at most 1/4th
// of the clock rate (or so).
// Width: Word width (in bits) of the words (bytes) send over
// the serial line.
// Parity: The type of parity bit to be appended to each word of
// data.
// 0: None
// 1: Even
// 2: Odd
// 3: Mark
// 4: Space
// StopBits:The number of bit-periods to send the stop condition.
// Generally 1 or 2, though larger numbers are possible.
// Ex: (27000000, 9600, 8, 0, 1) Standard 9600baud 8-N-1 serial port
// settings used as the default by many devices, based
// on a 27MHz clock.
//------------------------------------------------------------------------------
module UAReceiver(Clock, Reset, DataOut, DataOutValid, DataOutReady, SIn);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter ClockFreq = 27000000,
Baud = 115200,
Width = 8,
Parity = 0,
StopBits = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Local Parameters
//--------------------------------------------------------------------------
`ifdef MACROSAFE
localparam Divisor = ClockFreq / Baud,
DivWidth = `log2(Divisor),
Capture = (Divisor / 2),
BitCount = Width + StopBits + (Parity ? 1 : 0) + 1,
BCWidth = `log2(BitCount + 1),
ActualBaud = ClockFreq / Divisor;
`endif
`ifdef SIMULATION
localparam real MaxBaud = ClockFreq / ((Divisor * (BitCount - 0.5)) / BitCount),
MinBaud = ClockFreq / ((Divisor * (BitCount + 0.5)) / BitCount);
`endif
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Constant Debugging Statements
//--------------------------------------------------------------------------
`ifdef SIMULATION
initial begin
$display("DEBUG[%m @ %t]: UART Parameters", $time);
$display(" ClockFreq = %d", ClockFreq);
$display(" Baud = %d", Baud);
$display(" Width = %d", Width);
$display(" Parity = %d", Parity);
$display(" StopBits = %d", StopBits);
/*$display(" Divisor = %d", Divisor);
$display(" DivWidth = %d", DivWidth);
$display(" Capture = %d", Capture);
$display(" BitCount = %d", BitCount);
$display(" BCWidth = %d", BCWidth);*/
$display(" ActualBaud = %d", ActualBaud);
$display(" MaxBaud = %f", MaxBaud);
$display(" MinBaud = %f", MinBaud);
end
`endif
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// System Inputs
//--------------------------------------------------------------------------
input Clock, Reset;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Parallel Data Output
//--------------------------------------------------------------------------
output [Width-1:0] DataOut;
output DataOutValid;
input DataOutReady;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Serial Interface
//--------------------------------------------------------------------------
input SIn;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Wires and Regs
//--------------------------------------------------------------------------
wire IntSIn;
wire [DivWidth-1:0] RxDivCount;
wire [BCWidth-1:0] RxBitCount;
wire [BitCount-1:0] RxData;
wire RxShiftEnable, RxRunning, RxBit, RxStart, RxTransfered;
wire RxStartBit, RxActualParity;
wire [StopBits-1:0] RxStopBits;
wire RxParity;
wire [Width-1:0] RxDataStripped;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Assigns and Decodes
//--------------------------------------------------------------------------
assign RxShiftEnable = (RxDivCount == Capture);
assign RxRunning = (RxBitCount < BitCount);
assign RxBit = RxRunning & RxShiftEnable;
assign RxStart = ~IntSIn & ~RxRunning;
assign RxStartBit = RxData[BitCount-1];
assign RxActualParity = RxData[StopBits];
assign RxStopBits = RxData[StopBits-1:0];
assign DataOutValid = (~RxStartBit) & (&RxStopBits) & ~RxTransfered & (Parity ? ~(RxParity ^ RxActualParity) : 1'b1);
assign RxDataStripped = Parity ? RxData[BitCount-2:StopBits+1] : RxData[BitCount-2:StopBits];
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// IO Register
//--------------------------------------------------------------------------
IORegister IOR( .Clock( Clock),
.Reset( 1'b0),
.Set( 1'b0),
.Enable( 1'b1),
.In( SIn),
.Out( IntSIn));
defparam IOR.Width = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Clock Divider Counter
//--------------------------------------------------------------------------
Counter RxDivCounter(.Clock( Clock),
.Reset( Reset | (RxDivCount == (Divisor-1)) | RxStart),
.Set( 1'b0),
.Load( 1'b0),
.Enable( 1'b1),
.In( {DivWidth{1'bx}}),
.Count( RxDivCount));
defparam RxDivCounter.Width = DivWidth;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Bit Counter
//--------------------------------------------------------------------------
Counter RxBitCounter(.Clock( Clock),
.Reset( RxStart),
.Set( Reset),
.Load( 1'b0),
.Enable( RxBit),
.In( {BCWidth{1'bx}}),
.Count( RxBitCount));
defparam RxBitCounter.Width = BCWidth;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Shift Register and Bit Reversal
//--------------------------------------------------------------------------
ShiftRegister RxShift( .PIn( {BitCount{1'b1}}),
.SIn( IntSIn),
.POut( RxData),
.SOut( ),
.Load( Reset),
.Enable( RxShiftEnable),
.Clock( Clock),
.Reset( 1'b0));
defparam RxShift.PWidth = BitCount;
defparam RxShift.SWidth = 1;
Reverse RxReverse( .In( RxDataStripped),
.Out( DataOut));
defparam RxReverse.Width = Width;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Register
//--------------------------------------------------------------------------
Register RXTR( .Clock( Clock),
.Reset( 1'b0),
.Set( Reset | (DataOutReady & DataOutValid)),
.Enable( RxShiftEnable),
.In( (RxBitCount != (BitCount - 1))),
.Out( RxTransfered));
defparam RXTR.Width = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Parity Generator
//--------------------------------------------------------------------------
ParityGen RxParityGen(.In( DataOut),
.Out( RxParity));
defparam RxParityGen.Width = Width;
defparam RxParityGen.Parity = Parity;
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; struct rua { long double x, y; } m; set<pair<long double, long double> > p; vector<pair<long double, long double> > del; vector<long double> d; set<long double> mm; int n, ans; long double x, y; bool tt; bool check(rua T) { d.clear(); rua M = {(T.x + x) / 2, (T.y + y) / 2}; rua mM = {M.x - m.x, M.y - m.y}; rua r0 = {mM.y, -mM.x}; if (!r0.x) if (tt) return false; else tt = true; long double k = r0.y / r0.x; if (mm.count(k)) return false; else mm.insert(k); long double R = pow(r0.x * r0.x + r0.y * r0.y, 0.5); for (auto i = p.begin(); i != p.end(); i++) { rua mP = {(*i).first - m.x, (*i).second - m.y}; long double t = r0.x * mP.x + r0.y * mP.y; t /= r0.x * r0.x + r0.y * r0.y; if (t) d.push_back(t); } long double _ = (r0.x * mM.x + r0.y * mM.y) / R; int l = 0, r = d.size() - 1; sort(d.begin(), d.end()); while (l <= r && d[l] + d[r] == 0) l++, r--; return l > r; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { cin >> x >> y; p.insert(make_pair(x, y)); m.x += x, m.y += y; } m.x = m.x * 1.0 / n, m.y = m.y * 1.0 / n; for (auto i = p.begin(); i != p.end(); i++) { x = (*i).first, y = (*i).second; if (p.count(make_pair(2 * m.x - x, 2 * m.y - y))) del.push_back(make_pair(2 * m.x - x, 2 * m.y - y)), del.push_back(*i); } for (int i = 0; i < del.size(); i++) if (p.count(del[i])) p.erase(del[i]); if (!p.size()) return printf( -1 n ), 0; x = (*p.begin()).first, y = (*p.begin()).second; for (auto i = p.begin(); i != p.end(); i++) if (check({(*i).first, (*i).second})) ans++; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } int dis[4][1001][1001], n, m; ; queue<pair<int, int> > Q; char pp[1011][1011]; int nxt[4][2] = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}}; void go(int c) { while (!Q.empty()) Q.pop(); for (int i = (0); i < (n); ++i) { for (int j = (0); j < (m); ++j) if (pp[i][j] == 0 + c) { dis[c][i][j] = 0; Q.push(make_pair(i, j)); } } while (!Q.empty()) { pair<int, int> p = Q.front(); Q.pop(); for (int i = (0); i < (4); ++i) { int x = p.first + nxt[i][0], y = p.second + nxt[i][1]; if (x < 0 || x >= n || y < 0 || y >= m || pp[x][y] == # ) continue; if (dis[c][x][y] <= dis[c][p.first][p.second] + 1) continue; dis[c][x][y] = dis[c][p.first][p.second] + 1; Q.push(make_pair(x, y)); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = (0); i < (n); ++i) cin >> pp[i]; memset(dis, 126, sizeof dis); go(1); go(2); go(3); int res = INT_MAX / 3; for (int i = (1); i < (4); ++i) { int dd[4]; memset(dd, 126, sizeof dd); dd[i] = 1; for (int j = (0); j < (n); ++j) { for (int k = (0); k < (m); ++k) { if (pp[j][k] >= 1 && pp[j][k] <= 3 && pp[j][k] != 0 + i) dd[pp[j][k] - 0 ] = min(dd[pp[j][k] - 0 ], dis[i][j][k]); } } long long sum = 0; for (int j = (1); j < (4); ++j) sum += dd[j] - 1; if (sum < res) res = sum; } for (int i = (0); i < (n); ++i) { for (int j = (0); j < (m); ++j) { if (pp[i][j] != . ) continue; long long sum = 1; for (int k = (1); k < (4); ++k) { sum += dis[k][i][j] - 1; } if (sum < res) res = sum; } } if (res > 10000000) cout << -1 << endl; else cout << res << endl; }
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#include <bits/stdc++.h> using namespace std; int sqr(int v) { return v * v; } int main() { int x1, y1, x2, y2, r1, r2; cin >> x1 >> y1 >> r1 >> x2 >> y2 >> r2; if (r1 < r2) swap(x1, x2), swap(y1, y2), swap(r1, r2); int t1 = sqr(x1 - x2) + sqr(y1 - y2); long double ans(0); if (t1 < sqr(r1 - r2)) ans = r1 - r2 - sqrt((long double)t1); else if (t1 > sqr(r1 + r2)) ans = sqrt((long double)t1) - r1 - r2; cout << fixed << setprecision(20) << ans / 2 << endl; }
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// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
// Note; 1) Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
// 2) Please specify access time by defining tAC_10 or tAC_12.
`define OEb
`define tAC_10 //tAC_10 or tAC_12 defines different parameters
`timescale 1ns/1ns
module is61lv25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter dqbits = 16;
parameter memdepth = 262143;
parameter addbits = 18;
parameter Toha = 2;
parameter Tsa = 2;
`ifdef tAC_10 //if "`define tAC_10 " at beginning,sentences below are compiled
parameter Taa = 10,
Thzce = 3,
Thzwe = 5;
`endif
`ifdef tAC_12 //if "`define tAC_12 " at beginning,sentences below are compiled
parameter Taa = 12,
Thzce = 5,
Thzwe = 6;
`endif
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
//array to simulate SRAM
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_); //WE=1,CE=OE=0 Read
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); //WE=CE=0,LB or UB="0",OE=x Write
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
initial
$timeformat (-9, 0.1, " ns", 10); //show current simulation time
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
always @(A or w_en)
begin
#Tsa //address setup time
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
// Timing Check
`ifdef tAC_10
specify //sepcify delay
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
`else
`ifdef tAC_12
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 12,
tPWE1 = 8,
tPBW = 8;
`endif
`endif
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
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#include <bits/stdc++.h> using namespace std; struct bign { int len, s[109]; bign() { memset(s, 0, sizeof(s)); len = 1; } bign(int num) { *this = num; } bign(const char *num) { *this = num; } bign operator=(const int num) { char s[109]; sprintf(s, %d , num); *this = s; return *this; } bign operator=(const char *num) { for (int i = 0; num[i] == 0 ; num++) ; len = strlen(num); for (int i = 0; i < len; i++) s[i] = num[len - i - 1] - 0 ; return *this; } bign operator+(const bign &b) const { bign c; c.len = 0; for (int i = 0, g = 0; g || i < max(len, b.len); i++) { int x = g; if (i < len) x += s[i]; if (i < b.len) x += b.s[i]; c.s[c.len++] = x % 10; g = x / 10; } return c; } bign operator+=(const bign &b) { *this = *this + b; return *this; } void clean() { while (len > 1 && !s[len - 1]) len--; } bign operator*(const bign &b) { bign c; c.len = len + b.len; for (int i = 0; i < len; i++) { for (int j = 0; j < b.len; j++) { c.s[i + j] += s[i] * b.s[j]; } } for (int i = 0; i < c.len; i++) { c.s[i + 1] += c.s[i] / 10; c.s[i] %= 10; } c.clean(); return c; } bign operator*=(const bign &b) { *this = *this * b; return *this; } bign operator-(const bign &b) { bign c; c.len = 0; for (int i = 0, g = 0; i < len; i++) { int x = s[i] - g; if (i < b.len) x -= b.s[i]; if (x >= 0) g = 0; else { g = 1; x += 10; } c.s[c.len++] = x; } c.clean(); return c; } bign operator-=(const bign &b) { *this = *this - b; return *this; } bign operator/(const bign &b) { bign c, f = 0; for (int i = len - 1; i >= 0; i--) { f = f * 10; f.s[0] = s[i]; while (f >= b) { f -= b; c.s[i]++; } } c.len = len; c.clean(); return c; } bign operator/=(const bign &b) { *this = *this / b; return *this; } bign operator%(const bign &b) { bign r = *this / b; r = *this - r * b; return r; } bign operator%=(const bign &b) { *this = *this % b; return *this; } bool operator<(const bign &b) { if (len != b.len) return len < b.len; for (int i = len - 1; i >= 0; i--) { if (s[i] != b.s[i]) return s[i] < b.s[i]; } return false; } bool operator>(const bign &b) { if (len != b.len) return len > b.len; for (int i = len - 1; i >= 0; i--) { if (s[i] != b.s[i]) return s[i] > b.s[i]; } return false; } bool operator==(const bign &b) { return !(*this > b) && !(*this < b); } bool operator!=(const bign &b) { return !(*this == b); } bool operator<=(const bign &b) { return *this < b || *this == b; } bool operator>=(const bign &b) { return *this > b || *this == b; } string str() const { string res = ; for (int i = 0; i < len; i++) res = char(s[i] + 0 ) + res; return res; } }; map<int, bool> mp; const int MAX = 5e4 + 5; int n, m, Tot, tot; int a[MAX], b[MAX], pm[MAX], pim[MAX]; bool use[MAX]; void dfs(int n, int I = 0, int tot = 0, int qwq = 0) { if (qwq == n - 1) { printf( YES n ); printf( %d n , tot); for (int i = 0; i < tot; ++i) printf( %d %d n , a[i], b[i]); exit(0); } if (mp[qwq]) return; mp[qwq] = 1; for (int i = I + 1; i <= Tot; ++i) { if (i == Tot) { int qaq = min((int)((long long)(n - 1 - qwq) * pm[i] / n), pm[i] - 1); if (qwq + n / pm[i] * qaq != n - 1) continue; else a[tot] = qaq, b[tot] = pm[i], dfs(n, i, tot + 1, qwq + n / pm[i] * qaq); } else { for (int j = min((int)((long long)(n - 1 - qwq) * (long long)pm[i] / (long long)n), pm[i] - 1); j >= 1; --j) if (qwq + n / pm[i] * j <= n - 1) a[tot] = j, b[tot] = pm[i], dfs(n, i, tot + 1, qwq + n / pm[i] * j); else break; } } } bool look(int x) { if (x == 1) return 0; if (x == 2) return 1; for (int i = 2; i <= sqrt(x); ++i) if (x % i == 0) return 0; return 1; } void ss(int *pm) { use[1] = 1; for (int i = 2; i <= m; ++i) { if (!use[i]) pm[++tot] = i; for (int j = 1; j <= tot && pm[j] * i <= m; ++j) { use[i * pm[j]] = 1; if (i % pm[j] == 0) break; } } } bool work(int x) { int a = n; while (a % x == 0) a /= x; return a == 1; } int main() { scanf( %d , &n), m = sqrt(n); if (n % 2 == 0 && (n / 2) % 2 == 1 && n != 2) { cout << YES << endl << 2 << endl << 1 2 << endl; cout << (n / 2 - 1) / 2 << << n / 2 << endl; return 0; } if (look(n)) return printf( NO ), 0; ss(pim); for (int i = 1; i <= tot; ++i) if (work(pim[i])) return printf( NO ), 0; for (int i = 2; i <= m; ++i) if (n % i == 0) { pm[++Tot] = i; if (i != n / i) pm[++Tot] = n / i; } if (Tot + 2 < 4) return printf( NO ), 0; sort(pm + 1, pm + 1 + Tot), dfs(n); return printf( NO ), 0; } istream &operator>>(istream &in, bign &x) { string s; in >> s; x = s.c_str(); return in; } ostream &operator<<(ostream &out, const bign &x) { out << x.str(); return out; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, mod = 1e9 + 7; int a[N], st[N][20], pos[N][20]; int seg_query(int l, int r) { int k = log2(r - l + 1); if (st[l][k] > st[r - (1 << k) + 1][k]) return pos[l][k]; else return pos[r - (1 << k) + 1][k]; } long long f[N]; signed main() { int n; scanf( %d , &n); for (int i = 1; i <= n - 1; ++i) scanf( %d , a + i), st[i][0] = a[i], pos[i][0] = i; a[n] = n, st[n][0] = pos[n][0] = n; for (int j = 1; j <= 17; ++j) for (int i = 1; i + (1 << j) - 1 <= n; ++i) if (st[i][j - 1] > st[i + (1 << (j - 1))][j - 1]) st[i][j] = st[i][j - 1], pos[i][j] = pos[i][j - 1]; else st[i][j] = st[i + (1 << (j - 1))][j - 1], pos[i][j] = pos[i + (1 << (j - 1))][j - 1]; long long ans = 0; for (int i = n - 1; i >= 1; --i) { int k = seg_query(i + 1, a[i]); f[i] = f[k] + n - i - (a[i] - k); ans += f[i]; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; char s[N]; int a[N], b[N], n; int f[N][2][2]; pair<int, int> g1[N][2][2], g2[N][2][2]; void solve() { for (int l = 0, r = n + 1; l <= r; l++, r--) { if (l + 1 == r || l == r) break; int i = l; for (int j = 0; j < 2; j++) { for (int k = 0; k < 2; k++) { if (!f[i][j][k]) continue; for (int x = 0; x < 10; x++) { int y = (a[l + 1] - x - k + 10) % 10; if (r - 1 == n && y == 0) continue; for (int j2 = 0; j2 < 2; j2++) { if (j && (x + y + j2) < 10) continue; if (!j && (x + y + j2) >= 10) continue; if (a[r - 1] != (x + y + j2) % 10) continue; int k2 = (x + y + k) >= 10 ? 1 : 0; if (l + 2 < r - 1) { f[i + 1][j2][k2] = 1; g1[i + 1][j2][k2] = {x, y}; g2[i + 1][j2][k2] = {j, k}; } else if (l + 2 == r - 1) { if (j2 == k2) { f[i + 1][j2][k2] = 1; g1[i + 1][j2][k2] = {x, y}; g2[i + 1][j2][k2] = {j, k}; } } else if (l + 1 == r - 1) { if (j == k2 && j2 == k && x == y) { f[i + 1][j2][k2] = 1; g1[i + 1][j2][k2] = {x, y}; g2[i + 1][j2][k2] = {j, k}; } } } } } } } int x = (n + 1) / 2, j, k; for (int _ = 0; _ < 2; _++) for (int __ = 0; __ < 2; __++) if (f[x][_][__]) j = _, k = __; if (!f[x][j][k]) return; for (int l = x, r = x + (n % 2 == 0 ? 1 : 0); l >= 1; l--, r++) { int i = l; b[l] = g1[i][j][k].first, b[r] = g1[i][j][k].second; int _ = g2[i][j][k].first, __ = g2[i][j][k].second; j = _, k = __; } for (int i = n; i >= 1; i--) cout << b[i]; cout << endl; exit(0); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> (s + 1); n = strlen(s + 1); reverse(s + 1, s + n + 1); for (int i = 1; i <= n; i++) a[i] = s[i] - 0 ; f[0][0][0] = 1; solve(); if (a[n] == 1 && n > 1) { memset(f, 0, sizeof(f)); memset(g1, 0, sizeof(g1)); memset(g2, 0, sizeof(g2)); f[0][1][0] = 1; --n; solve(); } cout << 0 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long MAX = 1000000000; long long MOD = 1000000007; pair<long long, long long> p[100010]; void solve() { long long n; cin >> n; long long d; cin >> d; ; for (long long i = (0); i < (n); i++) { long long in1; cin >> in1; long long in2; cin >> in2; ; p[i] = {in1, in2}; } sort(p, p + n); long long j = 0, sum = 0, ans = 0; for (long long i = (0); i < (n); i++) { while (p[j].first - p[i].first < d and j < n) { sum += p[j].second; j++; } ans = max(ans, sum); sum -= p[i].second; } cout << ans; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long test = 1; while (test--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; bool sortp(const pair<int, int> a, const pair<int, int> b) { if (a.first > b.first) return 0; else if (a.first < b.first) return 1; else return a.second > b.second; } int main() { int n, m; cin >> n >> m; pair<int, int> b; vector<pair<int, int>> a; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; b.first = x; b.second = y; a.push_back(b); } sort(a.begin(), a.end(), sortp); int flag = 0; for (int i = 0; i < m; i++) { if (n <= a[i].first) { cout << NO << endl; flag = 1; break; } else { n += a[i].second; } } if (flag == 0) { cout << YES << endl; } }
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#include <bits/stdc++.h> using namespace std; char a[105]; char temp[105]; int main() { int n; scanf( %d%*c , &n); while (n--) { int cnt = 0; bool flag = false; bool first = false; gets(a); int len = strlen(a); for (int i = len - 5; i <= len; i++) temp[cnt++] = a[i]; if (strncmp(a, miao. , 5) == 0) first = true; if (strcmp(temp, lala. ) == 0) flag = true; if (first && !flag) printf( Rainbow s n ); else if (!first && flag) printf( Freda s n ); else printf( OMG>.< I don t know! n ); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_TB_V
`define SKY130_FD_SC_LS__FAHCIN_TB_V
/**
* fahcin: Full adder, inverted carry in.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fahcin.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__fahcin dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_TB_V
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`include "async_receiver.v"
`include "async_transmitter.v"
// by teknohog, replaces virtual_wire by rs232
module serial_receive(clk, RxD, midstate, data2);
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver deserializer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
output [255:0] midstate;
output [255:0] data2;
// 256 bits midstate + 256 bits data at the same time = 64 bytes
// Might be a good idea to add some fixed start and stop sequences,
// so we really know we got all the data and nothing more. If a
// test for these fails, should ask for new data, so it needs more
// logic on the return side too. The check bits could be legible
// 7seg for quick feedback :)
reg [511:0] input_buffer;
reg [511:0] input_copy;
reg [6:0] demux_state = 7'b0000000;
assign midstate = input_copy[511:256];
assign data2 = input_copy[255:0];
// we probably don't need a busy signal here, just read the latest
// complete input that is available.
always @(posedge clk)
case (demux_state)
7'b1000000:
begin
input_copy <= input_buffer;
demux_state <= 0;
end
default:
if(RxD_data_ready)
begin
input_buffer <= input_buffer << 8;
input_buffer[7:0] <= RxD_data;
demux_state <= demux_state + 1;
end
endcase // case (demux_state)
endmodule // serial_receive
module serial_transmit (clk, TxD, busy, send, word);
// split 4-byte output into bytes
wire TxD_start;
wire TxD_busy;
reg [7:0] out_byte;
reg serial_start;
reg [3:0] mux_state = 4'b0000;
assign TxD_start = serial_start;
input clk;
output TxD;
input [31:0] word;
input send;
output busy;
reg [31:0] word_copy;
assign busy = (|mux_state);
always @(posedge clk)
begin
/*
case (mux_state)
4'b0000:
if (send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
4'b1000: out_byte <= word_copy[31:24];
4'b1010: out_byte <= word_copy[23:16];
4'b1100: out_byte <= word_copy[15:8];
4'b1110: out_byte <= word_copy[7:0];
default: mux_state <= 4'b0000;
endcase // case (mux_state)
*/
// Testing for busy is problematic if we are keeping the
// module busy all the time :-/ So we need some wait stages
// between the bytes.
if (!busy && send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
else if (mux_state[3] && ~mux_state[0] && !TxD_busy)
begin
serial_start <= 1;
mux_state <= mux_state + 1;
out_byte <= word_copy[31:24];
word_copy <= (word_copy << 8);
end
// wait stages
else if (mux_state[3] && mux_state[0])
begin
serial_start <= 0;
if (!TxD_busy) mux_state <= mux_state + 1;
end
end
async_transmitter serializer(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_data(out_byte), .TxD_busy(TxD_busy));
endmodule // serial_send
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#include <bits/stdc++.h> using namespace std; int n, a[1000005], r[3], cnt; bool up, down; set<int> s; int main() { srand(75435); scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); if (n <= 2) { cout << -1; return 0; } for (int i = 0; i < n; i++) { if (s.find(a[i]) == s.end()) { if (cnt < 3) r[cnt++] = i; s.insert(a[i]); } } if (cnt == 3) { if (r[0] > r[1]) swap(r[0], r[1]); if (r[0] > r[2]) swap(r[0], r[2]); if (r[1] > r[2]) swap(r[1], r[2]); if ((a[r[1]] > a[r[0]] && a[r[1]] > a[r[2]]) || (a[r[1]] < a[r[0]] && a[r[1]] < a[r[2]])) { cout << r[0] + 1 << << r[2] + 1; return 0; } cout << r[0] + 1 << << r[1] + 1 << endl; return 0; } for (int i = 0; i < n - 1; i++) if (a[i] != a[i + 1]) { swap(a[i], a[i + 1]); up = true; down = true; for (int j = 0; j < n - 1; j++) if (a[j] > a[j + 1]) up = false; else if (a[j] < a[j + 1]) down = false; if (!down && !up) { cout << i + 1 << << i + 2; return 0; } swap(a[i], a[i + 1]); } cout << -1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_PP_BLACKBOX_V
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