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#include <bits/stdc++.h> using namespace std; int n, k; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; vector<vector<int>> g(n); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } vector<int> color(n); vector<int> d(n); vector<int> sub(n); int iter = 0; function<void(int, int, int, int)> dfs_to_color = [&](int v, int p, int c, int pr) { color[v] = c; for (int i : g[v]) { if (i == p || color[i] != pr) continue; dfs_to_color(i, v, c, pr); } }; function<void(int, int, int)> dfs_on_color = [&](int v, int p, int c) { if (~p) d[v] = d[p] ^ 1; else d[v] = 0; sub[v] = 1; for (int i : g[v]) { if (color[i] != c || i == p) continue; dfs_on_color(i, v, c); sub[v] += sub[i]; } }; vector<pair<int, int>> ret; function<void(vector<int>)> solve = [&](vector<int> nodes) { int sz = nodes.size(); if (sz <= 4) return; int root = nodes[0]; int c = color[root]; dfs_on_color(root, -1, c); int pr = -1; while (true) { int nxt = -1; for (int i : g[root]) { if (color[i] != c || i == pr) continue; if (sub[i] > sz / 2) nxt = i; } if (nxt == -1) break; pr = root; root = nxt; } for (int i : g[root]) { if (color[i] != c) continue; iter++; dfs_to_color(i, root, iter, c); } map<int, vector<int>> to_color; for (int i : nodes) { if (i == root) continue; to_color[color[i]].push_back(i); } int pos = -1; int cd = 0; for (auto it : to_color) { int id = it.first; vector<int> nxt = it.second; solve(nxt); for (int i : nxt) color[i] = id; dfs_on_color(nxt[0], -1, id); if ((int)nxt.size() > cd) { cd = nxt.size(); pos = id; } } for (auto it : to_color) { int id = it.first; vector<int> vertices = it.second; vector<int> to_root; if (id != pos) to_root = vertices; else { vector<int> cnt(2); for (int i : vertices) cnt[d[i]]++; int chosen = cnt[1] < cnt[0]; for (int i : vertices) { if (d[i] == chosen) to_root.push_back(i); } } for (int i : to_root) { ret.emplace_back(i, root); } } }; vector<int> foo(n); iota(foo.begin(), foo.end(), 0); solve(foo); assert((int)ret.size() <= 10 * n); cout << ret.size() << endl; for (auto i : ret) { cout << i.first + 1 << << i.second + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v[200005]; vector<int> par(200005, -1); vector<int> ran(200005, 1); int fi(int c) { while (1) { if (par[c] == -1) return c; else c = par[c]; } } int main() { int n, m; cin >> n >> m; long long int a[n]; long long int val = 10000000000000000; int in; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] < val) { val = a[i]; in = i; } } vector<pair<long long int, pair<int, int> > > v; for (int i = 0; i < n; i++) { if (i != in) { v.push_back({a[i] + val, {i, in}}); } } long long int sum = 0; while (m--) { int x, y; cin >> x >> y; long long int z; cin >> z; x--, y--; v.push_back({z, {x, y}}); } sort(v.begin(), v.end()); int s = v.size(); for (int i = 0; i < s; i++) { int t1 = v[i].second.first; int t2 = v[i].second.second; int t3 = fi(t1); int t4 = fi(t2); if (t3 != t4) { if (ran[t3] > ran[t4]) { par[t4] = t3; ran[t3] += ran[t4]; } else { par[t3] = t4; ran[t4] += ran[t3]; } sum += v[i].first; } } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int q = 0; q < t; q++) { long long n, m; cin >> n >> m; if (n % m == 0) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename t> t in(t q) { cin >> q; return q; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << [ ; for (int i = 0; i < ((int)(v).size()); ++i) { os << v[i]; if (i != ((int)(v).size()) - 1) os << , ; } os << ] ; return os; } template <typename T, typename S> ostream &operator<<(ostream &os, const map<T, S> &v) { for (auto it : v) os << ( << it.first << : << it.second << ) ; return os; } template <typename T, typename S> ostream &operator<<(ostream &os, const pair<T, S> &v) { os << ( << v.first << , << v.second << ) ; return os; } const long double PI = acosl(-1); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rng64(chrono::steady_clock::now().time_since_epoch().count()); inline int rand(int l, int r) { return uniform_int_distribution<int>(l, r)(rng); } inline long long rand(long long l, long long r) { return uniform_int_distribution<long long>(l, r)(rng64); } using namespace std; const int N = 200005, M = 1005; const long long MOD = 1e9 + 7; const int OO = 1e9; int a[11][11]; void solve() { int n; cin >> n; for (int i = 0; i <= n; i++) { a[i][1] = 1; a[1][i] = 1; } for (int i = 2; i <= n; i++) { for (int j = 2; j <= n; j++) { a[i][j] = a[i - 1][j]; a[i][j] += a[i][j - 1]; } } cout << a[n][n] << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << n ; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Sean Moore.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] tripline = crc[7:0];
/*AUTOWIRE*/
wire valid;
wire [3-1:0] value;
PriorityChoice #(.OCODEWIDTH(3))
pe (.out(valid), .outN(value[2:0]), .tripline(tripline));
// Aggregate outputs into a single result vector
wire [63:0] result = {59'h0, valid, value};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc5fc632f816568fb
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module PriorityChoice (out, outN, tripline);
parameter OCODEWIDTH = 1;
localparam CODEWIDTH=OCODEWIDTH-1;
localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH;
output reg out;
output reg [OCODEWIDTH-1:0] outN;
input wire [(1<<OCODEWIDTH)-1:0] tripline;
wire left;
wire [SCODEWIDTH-1:0] leftN;
wire right;
wire [SCODEWIDTH-1:0] rightN;
generate
if(OCODEWIDTH==1) begin
assign left = tripline[1];
assign right = tripline[0];
always @(*) begin
out <= left || right ;
if(right) begin outN <= {1'b0}; end
else begin outN <= {1'b1}; end
end
end else begin
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
leftMap
(
.out(left),
.outN(leftN),
.tripline(tripline[(2<<CODEWIDTH)-1:(1<<CODEWIDTH)])
);
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
rightMap
(
.out(right),
.outN(rightN),
.tripline(tripline[(1<<CODEWIDTH)-1:0])
);
always @(*) begin
if(right) begin
out <= right;
outN <= {1'b0, rightN[OCODEWIDTH-2:0]};
end else begin
out <= left;
outN <= {1'b1, leftN[OCODEWIDTH-2:0]};
end
end
end
endgenerate
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:41:20 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, a[maxn], ans; int gcd(int x, int y) { if (y == 0) return x; return gcd(y, x % y); } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int x = gcd(a[1], a[2]); for (int i = 3; i <= n; i++) if (x > 1) { x = gcd(x, a[i]); } if (x > 1) { cout << YES << endl; cout << 0 << endl; } else { for (int i = 1; i < n; i++) { if (a[i] % 2 == 0) continue; else if (a[i + 1] % 2 == 0) ans += 2, a[i] = 0; else ans++, a[i + 1] = 0, a[i] = 0; } if (a[n] % 2 == 0) { cout << YES << endl; cout << ans << endl; } else { cout << YES << endl; cout << ans + 2 << endl; } } }
|
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [15:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 17333) //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 415999
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sum(int a) { int s = 0; while (a > 0) { s += (a % 10); a = a / 10; } return s; } int main() { int n, a, b; cin >> n; while (sum(n) % 4 != 0) { n++; } cout << n << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_1_V
`define SKY130_FD_SC_HVL__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_1_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; map<string, int> m; for (__typeof((n)) i = (0); i < (n); i++) { cin >> s; if (m[s]) cout << YES << endl; else cout << NO << endl; m[s]++; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x, res, p[(1 << 20)]; int main() { for (cin >> n; n--;) scanf( %d , &x), p[x]++; for (int i = 0; i < (1 << 20); i++) res += p[i] & 1, p[i + 1] += p[i] / 2; cout << res << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR2B_BEHAVIORAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2b (
X ,
A ,
B_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
// Local signals
wire X not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_TB_V
`define SKY130_FD_SC_MS__CLKINV_TB_V
/**
* clkinv: Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_TB_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : alu.v
//Project Name : azpr_soc
//Description : the alu module.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/cpu/alu.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.12.01 - lichangbeiju - Change the coding style : part 2.
//2016.11.22 - lichangbeiju - Change the coding style : part 1.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "cpu.h"
module gpr(
input wire clk ,
input wire reset ,
//read port 0
input wire [`RegAddrBus] rd_addr_0 ,//5 write data
output wire [`WordDataBus] rd_data_0 ,//32
//read port 1
input wire [`RegAddrBus] rd_addr_1 ,//5 write data
output wire [`WordDataBus] rd_data_1 ,//32
//write port
input wire we_n ,//1
input wire [`WordAddrBus] wr_addr ,//32
input wire [`WordDataBus] wr_data //32
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal variable
//------------------------------------------------------------------------------------------------
reg [`WordDataBus] gpr [`REG_NUM-1:0];
integer i;
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the read logic
//------------------------------------------------------------------------------------------------
assign rd_data_0 = ((we_n == `ENABLE_N) && (wr_addr == rd_addr_0)) ? wr_data : gpr[rd_addr_0];
assign rd_data_1 = ((we_n == `ENABLE_N) && (wr_addr == rd_addr_1)) ? wr_data : gpr[rd_addr_1];
//------------------------------------------------------------------------------------------------
// 3.2 the write logic
//------------------------------------------------------------------------------------------------
always @(posedge clk or `RESET_EDGE reset) begin : OWNER_CTRL
if(reset == `RESET_ENABLE)
begin
for(i=0;i<`REG_NUM;i=i+1) begin : GPR_INIT
gpr[i] <= `WORD_DATA_W'h0;
end
end
else begin
if(we_n == `ENABLE_N)
begin
gpr[wr_addr] <= wr_data;
end
end
end
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_1_V
`define SKY130_FD_SC_HS__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_1_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; vector<vector<long long>> g; vector<long long> a; vector<long long> ans; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; g = vector<vector<long long>>(n + 1); a = vector<long long>(n + 1); ans = vector<long long>(n + 1, LLONG_MAX); for (int i = 1; i <= n; i++) { cin >> a[i]; if (i - a[i] >= 1) { g[i - a[i]].push_back(i); } if (i + a[i] <= n) { g[i + a[i]].push_back(i); } } set<long long> toUp; for (int i = 1; i <= n; i++) { for (auto x : g[i]) { if (a[x] % 2 != a[i] % 2) { ans[x] = 1; toUp.insert(x); } } } while (!toUp.empty()) { vector<long long> temp(toUp.begin(), toUp.end()); toUp.clear(); for (auto i : temp) { for (auto x : g[i]) { if (ans[x] > ans[i] + 1) { ans[x] = ans[i] + 1; toUp.insert(x); } } } } for (int i = 1; i <= n; i++) { if (ans[i] == LLONG_MAX) cout << -1 ; else cout << ans[i] << ; } return 0; }
|
// pr_region_default_onchip_memory2_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module pr_region_default_onchip_memory2_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [6:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [31:0] readdata, // .readdata
input wire [31:0] writedata, // .writedata
input wire [3:0] byteenable // .byteenable
);
pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy onchip_memory2_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 7, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 32, .readdata
.writedata (writedata), // input, width = 32, .writedata
.byteenable (byteenable), // input, width = 4, .byteenable
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double kEps(1e-8); #pragma gcc optimize(2) int gcd(int x, int y) { while (y ^= x ^= y ^= x %= y) ; return x; } void write(int x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } int qpow(int m, int n) { int res = 1; while (n) { if (n & 1) { res *= m; } n >>= 1; m *= m; } return res; } int max(int a, int b) { if (a > b) { return a; } else return b; } int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x * f; } signed main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long ans = 1; map<long long, long long> mp; for (long long i = 2; i < n; ++i) { if (i * i > n) { break; } else { if (i * i <= n) { ans++; } if (i * i * i <= n) { ans++; } mp[i * i]++; mp[i * i * i]++; } } long long temp = 0; for (auto it : mp) { if (it.second > 1) { temp++; } } mp.clear(); cout << ans - temp << n ; } }
|
#include <bits/stdc++.h> using namespace std; int N, n, m; long long a[1 << 20], b[1 << 20]; int g[21][100001]; void FWT(long long *P, int opt) { for (int i = 2; i <= N; i <<= 1) for (int p = i >> 1, j = 0; j < N; j += i) for (int k = j; k < j + p; ++k) { long long x = P[k], y = P[k + p]; P[k] = x + y; P[k + p] = x - y; if (opt == -1) P[k] /= 2, P[k + p] /= 2; } } int main() { cin >> n >> m; N = 1 << n; char ch[100001]; for (int i = 1; i <= n; ++i) { scanf( %s , ch + 1); for (int j = 1; j <= m; ++j) g[i][j] = ch[j] - 48; } for (int i = 1; i <= m; ++i) { int x = 0; for (int j = 1; j <= n; ++j) x = (x << 1) | g[j][i]; a[x]++; } for (int i = 0; i < N; ++i) b[i] = b[i >> 1] + (i & 1); for (int i = 0; i < N; ++i) b[i] = min(b[i], n - b[i]); FWT(a, 1); FWT(b, 1); for (int i = 0; i < N; ++i) a[i] *= b[i]; FWT(a, -1); long long ans = n * m; for (int i = 0; i < N; ++i) ans = min(ans, a[i]); printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int mat[4005][4005]; int acum[4005][4005]; int dp[4005][805]; int step(int n, int k, int min_i, int max_i) { dp[n][k] = dp[min_i - 1][k - 1] + (acum[n][n] + acum[min_i - 1][min_i - 1] - acum[n][min_i - 1] - acum[min_i - 1][n]) / 2; for (int i = min_i + 1; i <= max_i; i++) { if (dp[i - 1][k - 1] + (acum[n][n] + acum[i - 1][i - 1] - acum[n][i - 1] - acum[i - 1][n]) / 2 < dp[n][k]) { dp[n][k] = dp[i - 1][k - 1] + (acum[n][n] + acum[i - 1][i - 1] - acum[n][i - 1] - acum[i - 1][n]) / 2; min_i = i; } } return min_i; } void conquer(int min_n, int max_n, int k, int min_i, int max_i) { if (min_n > max_n) return; max_i = min(max_n, max_i); if (min_n == max_n) { step(min_n, k, min_i, max_i); return; } if (min_i == max_i) { for (int i = min_n; i <= max_n; i++) step(i, k, min_i, max_i); return; } int mid = (min_n + max_n) / 2; int i = step(mid, k, min_i, min(max_i, mid)); conquer(min_n, mid - 1, k, min_i, i); conquer(mid + 1, max_n, k, i, max_i); } char buff[100005]; int main() { int n, k; scanf( %d %d n , &n, &k); for (int i = 1; i <= n; i++) { int acum2 = 0; gets(buff); for (int j = 1; j <= n; j++) { acum2 += buff[j * 2 - 2] - 0 ; acum[i][j] = acum[i - 1][j] + acum2; } } for (int i = 1; i <= n; i++) { dp[i][1] = acum[i][i] / 2; } for (int j = 2; j <= k; j++) { conquer(1, n, j, j - 1, n); } printf( %d n , dp[n][k]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_crc.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= #1 32'hffffffff;
else
if(Initialize)
Crc <= #Tp 32'hffffffff;
else
Crc <= #Tp CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; void solve() { int n, k, d; cin >> n >> k >> d; vector<int> a(n); map<int, int> used; for (int i = 0; i < n; i++) cin >> a[i]; int cnt = 0, ans = INF; for (int i = 0; i < d; i++) { if (used[a[i]] == 0) cnt++; used[a[i]]++; } for (int i = d; i < n; i++) { ans = min(ans, cnt); used[a[i - d]]--; if (used[a[i - d]] == 0) cnt--; if (used[a[i]] == 0) cnt++; used[a[i]]++; } ans = min(cnt, ans); cout << ans << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int _t; cin >> _t; for (int _q = 0; _q < _t; _q++) solve(); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/05/06 14:34:16
// Design Name:
// Module Name: configuration
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module configuration(
input [31:0] data_config_i,
input [31:0] addr_config_i,
input req_config_i,
input rw_config_i,
output reg ack_config_o,
output reg [31:0]data_config_o,
input clk,
input reset,
output reg config_sw_ok
);
reg [2:0]cur_st,nxt_st;
localparam IDLE=0,
ACK=1;
always@(posedge clk)
if(reset)
cur_st<=0;
else cur_st<=nxt_st;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
IDLE:if(req_config_i) nxt_st=ACK;
ACK:nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(*)
if(reset)
ack_config_o=0;
else if(cur_st==ACK)
ack_config_o=1;
else ack_config_o=0;
always@(posedge clk)
if(reset)
config_sw_ok<=0;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_SW_STARTED} && rw_config_i==0)
config_sw_ok<=data_config_i[0];
`ifdef ONETS20
begin
always@(*)
if(reset)
data_config_o=0;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_SW_STARTED} && rw_config_i)
data_config_o=config_sw_ok;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_CARD} && rw_config_i)
data_config_o=20;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_VERSION} && rw_config_i)
data_config_o=`VERSION;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_TABLE_NUM} && rw_config_i)
data_config_o=`TABLE_NUM;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_DEPTH} && rw_config_i)
data_config_o=`T0_OPENFLOW_WILDCARD_TABLE_SIZE;
else data_config_o=32'hdeadbeef;
end
`elsif ONETS30
begin
always@(*)
if(reset)
data_config_o=0;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_SW_STARTED} && rw_config_i)
data_config_o=config_sw_ok;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_CARD} && rw_config_i)
data_config_o=30;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_VERSION} && rw_config_i)
data_config_o=`VERSION;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_TABLE_NUM} && rw_config_i)
data_config_o=`TABLE_NUM;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_DEPTH} && rw_config_i)
data_config_o=`T0_OPENFLOW_WILDCARD_TABLE_SIZE;
else data_config_o=32'hdeadbeef;
end
`elsif ONETS45
begin
always@(*)
if(reset)
data_config_o=0;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_SW_STARTED} && rw_config_i)
data_config_o=config_sw_ok;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_CARD} && rw_config_i)
data_config_o=45;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_VERSION} && rw_config_i)
data_config_o=`VERSION;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_TABLE_NUM} && rw_config_i)
data_config_o=`TABLE_NUM;
else if(cur_st==ACK && addr_config_i[23:0]=={16'h0,`CONFIG_DEPTH} && rw_config_i)
data_config_o=`T0_OPENFLOW_WILDCARD_TABLE_SIZE;
else data_config_o=32'hdeadbeef;
end
`endif
endmodule
|
module iop_fpga(reset_l, gclk,
spc_pcx_req_pq,
spc_pcx_atom_pq,
spc_pcx_data_pa,
pcx_spc_grant_px,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2
);
output [4:0] spc_pcx_req_pq;
output spc_pcx_atom_pq;
output [123:0] spc_pcx_data_pa;
input [4:0] pcx_spc_grant_px;
input cpx_spc_data_rdy_cx2;
input [144:0] cpx_spc_data_cx2;
input reset_l;
input gclk;
// WIRE Definitions for unused outputs
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid = 4'b0000;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// Reset Related Signals
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
reg reset_l_int;
reg sync;
// Reset Logic
assign cmp_arst_l = reset_l_int;
assign adbginit_l = reset_l_int;
reg [7:0] reset_delay;
// Synchronize the incoming reset net into the gclk domain
always @(posedge gclk) begin
{reset_l_int, sync} <= {sync, reset_l};
end
always @(posedge gclk) begin
if(~reset_l_int) begin
reset_delay <= 8'b0;
end else
if(reset_delay != 8'hff)
reset_delay <= reset_delay + 8'b1;
end
assign cluster_cken = (reset_delay > 8'd20) ? 1'b1 : 1'b0;
assign ctu_tst_pre_grst_l = (reset_delay > 8'd60) ? 1'b1 : 1'b0;
assign gdbginit_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
assign cmp_grst_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7117 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w513,
w4104,
w3591,
w64,
w65,
w7182,
w7117;
assign w1 = i_data0;
assign w3591 = w4104 - w513;
assign w4104 = w513 << 3;
assign w512 = w1 << 9;
assign w513 = w1 + w512;
assign w64 = w1 << 6;
assign w65 = w1 + w64;
assign w7117 = w7182 - w65;
assign w7182 = w3591 << 1;
assign o_data0 = w7117;
//multiplier_block area estimate = 7497.70553614559;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k, arr[105][105]; int check(int c[105], int ctC, int secRow) { int ans = INT_MAX; if (ctC > 10) return ans; for (int i = 0; i < (1 << ctC); i++) { int ct = 0; for (int r = 2; r <= n; r++) { if (r != secRow) { int same = 0; for (int j = 1; j <= m; j++) { int row1El = c[j] >= 0 && (i & (1 << c[j])) ? 1 - arr[1][j] : arr[1][j]; if (row1El == arr[r][j]) same++; } ct += min(same, m - same); } } ans = min(ctC + ct, ans); } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> arr[i][j]; } } if (n == 1 || m == 1) { cout << 0 << endl; return 0; } int ans = INT_MAX; for (int secRow = 2; secRow <= min(15, n); secRow++) { int ctA = 0, ctB = 0; int a[105], b[105]; memset(a, -1, sizeof(a)); memset(b, -1, sizeof(b)); for (int j = 1; j <= m; j++) { if ((arr[1][j] ^ arr[secRow][j]) == 1) { a[j] = ctA; ctA++; } else { b[j] = ctB; ctB++; } } ans = min(check(a, ctA, secRow), check(b, ctB, secRow)); } cout << (ans > k ? -1 : ans) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); ; int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int mi = *min_element(a, a + n); int p = -1; int f = 0; int ans = INT_MAX; for (int i = 0; i < n; i++) { if (a[i] == mi and !f) { f = 1; p = i; } else if (a[i] == mi and f) { ans = min(ans, i - p); p = i; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 3005; int a[MAX], b[MAX], c[MAX], dp[MAX][2]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= n; i++) cin >> c[i]; dp[1][0] = a[1]; dp[1][1] = b[1]; for (int i = 2; i <= n; i++) { dp[i][0] = dp[i - 1][0] + b[i]; dp[i][1] = dp[i - 1][0] + c[i]; dp[i][0] = max(dp[i][0], dp[i - 1][1] + a[i]); dp[i][1] = max(dp[i][1], dp[i - 1][1] + b[i]); } cout << dp[n][0] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int N = 1e6 + 10; signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, m; cin >> n >> m; int g[n]; for (int i = 0; i < n; ++i) cin >> g[i]; sort(g, g + (sizeof(g) / sizeof(*g))); long long d[n]; fill(d, d + (sizeof(d) / sizeof(*d)), 0); for (int i = m; i < n; ++i) d[i] = g[i - m] + d[i - m]; long long sm = 0; for (int i = 0; i < n; ++i) { sm += g[i] + d[i]; cout << sm << ; } return 0; }
|
#include <bits/stdc++.h> const int maxx = 2e6 + 5; using namespace std; long long a[maxx]; long long biaoji[maxx] = {0}; int main() { long long t, i, j, m, n; cin >> n; long long maxl = 0; for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); maxl = max(maxl, a[i]); biaoji[a[i]]++; } long long sum1 = 0, sum2 = 0; long long cishu = 0; long long weizhi = 0; for (i = 1; i <= maxl + 1; i++) { if (biaoji[i] > 0) { if (biaoji[i + 1] > 0 && biaoji[i + 2] > 0) { sum1++; i += 2; } else if (biaoji[i + 1] > 0) { sum1++; i++; } else if (biaoji[i + 2] > 0) { sum1++; i += 2; } else { sum1++; i += 2; } } } for (i = 0; i <= maxl + 1; i++) { if (i >= 1 && biaoji[i - 1] >= 1) { sum2++; } else if (biaoji[i] == 0) { if (biaoji[i + 1] >= 1) { biaoji[i + 1]--; sum2++; } } else if (biaoji[i] >= 1) { biaoji[i]--; sum2++; } } printf( %lld %lld n , sum1, sum2); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: prnf5ccc.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module prnf5ccc (
address,
clock,
q);
input [15:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "prn5.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "50000"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "prn5.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "50000"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module testit;
reg clk;
reg a_i;
reg b_i;
reg a_o;
reg b_o;
reg rst_n;
reg [7:0] shreg;
//== State enumeration
parameter [2:0] // synopsys enum state_info
SM_IDLE = 3'b000,
SM_SEND = 3'b001,
SM_WAIT1 = 3'b010;
//== State variables
reg [2:0] /* synopsys enum state_info */
state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */
state_e1;
//== ASCII state decoding
/*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
// Beginning of automatic ASCII enum decoding
reg [39:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: _stateascii_r = "idle ";
SM_SEND: _stateascii_r = "send ";
SM_WAIT1: _stateascii_r = "wait1";
default: _stateascii_r = "%Erro";
endcase
end
// End of automatics
initial begin
clk = 0;
a_i = 0;
b_i = 0;
rst_n = 0;
#20 rst_n = 1;
end
always #5 clk = ~clk;
always @(posedge clk or rst_n) begin
if (~rst_n) begin
a_o <= 0;
b_o <= 0;
shreg <= 8'b00110011;
end
else begin
a_o <= a_i;
b_o <= b_i;
shreg <= {shreg[6:0], shreg[7]};
end
end
task set_a_i;
begin
a_i = shreg[0];
end
endtask // set_a_i
always @(shreg & a_o) begin
set_a_i;
end
initial begin
$vcdpluson;
#500 $finish;
end
endmodule // testit
|
#include <bits/stdc++.h> using namespace std; template <class T> int len(const T &c) { return (int)c.size(); } template <class T> void cmin(T &a, T b) { if (b < a) a = b; } template <class T> void cmax(T &a, T b) { if (b > a) a = b; } int n; int main() { cin >> n; if (n == 3) { cout << 5; return 0; } int t; for (int i = 1;; i += 2) { t = i * i; t++; t /= 2; if (t >= n) { cout << i << endl; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, i, sum = 0, x, y; cin >> n >> t; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n - 1; i++) { if ((a[i] >= 0 && a[i + 1] >= 0) || (a[i] <= 0 && a[i + 1] <= 0)) { x = abs(a[i] - a[i + 1]) / t; y = abs(a[i] - a[i + 1]) % t; } else if (a[i] < 0 && a[i + 1] > 0) { x = ((a[i] * -1) + a[i + 1]) / t; y = ((a[i] * -1) + a[i + 1]) % t; } if (x > 2) { sum += 2; } else if (x == 2 && y == 0) sum += 1; else if (x == 2 && y != 0) sum += 2; } sum += 2; cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, a[100100], d[100100]; int main() { cin >> n; int mn = 1000111222, mx = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); mn = min(mn, a[i]); mx = max(mx, a[i]); } for (int i = 0; i < n; i++) { a[i] -= mn; if (a[i] > n) { puts( NO ); return 0; } d[a[i]]++; } mx -= mn; d[0]--; d[mx]--; for (int i = 1; i <= mx - 1; i++) if (d[i] < 2) { puts( NO ); return 0; } else d[i] -= 2; for (int i = 0; i <= mx; i++) if (d[i]) { if (d[i] > d[i + 1]) { puts( NO ); return 0; } d[i + 1] -= d[i]; } puts( YES ); }
|
#include<bits/stdc++.h> #define pii pair<int,int> #define fi first #define sc second #define pb push_back #define ll long long #define trav(v,x) for(auto v:x) using namespace std; const int N = 1e6 + 100; const ll mod = 998244353; int n, m, need; int sa[N], rnk[N]; ll fac[N], ifac[N]; ll C(ll x, ll y) {return 1LL * fac[x] * ifac[y] % mod * ifac[x - y] % mod;} ll qpow(ll x, ll y = mod - 2) { ll res = 1; while(y) { if(y & 1)res = res * x % mod; x = x * x % mod, y >>= 1; } return res; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for(int i = 1; i <= n; i++) cin >> sa[i], ++sa[i], rnk[sa[i]] = i; need = 1; sa[n + 1] = 0; for(int i = 2; i <= n; i++) { int bf_ps = sa[i - 1], nw_ps = sa[i]; if(rnk[bf_ps + 1] < rnk[nw_ps + 1]); else ++need; } m -= need; // cerr << !! << m << n ; ll ans = 0; fac[0] = 1; for(int i = 1; i < N; i++)fac[i] = fac[i - 1] * i % mod; ifac[N - 1] = qpow(fac[N - 1]); for(int i = N - 2; i >= 0; i--)ifac[i] = ifac[i + 1] * (i + 1) % mod; for(ll x = 0; x <= m; x++) ans = (ans + C(x + n - 1, n - 1)) % mod; cout << ans << n ; return 0; }
|
/**
* bsg_mesh_router_buffered.v
*
*/
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
module bsg_mesh_router_buffered
import bsg_mesh_router_pkg::*;
#(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(x_cord_width_p )
, parameter `BSG_INV_PARAM(y_cord_width_p )
, parameter debug_p = 0
, parameter ruche_factor_X_p = 0
, parameter ruche_factor_Y_p = 0
, parameter dims_p = 2
, parameter dirs_lp = (2*dims_p)+1
, parameter stub_p = { dirs_lp {1'b0}} // SNEWP
, parameter XY_order_p = 1
, parameter bsg_ready_and_link_sif_width_lp=`bsg_ready_and_link_sif_width(width_p)
// select whether to buffer the output
, parameter repeater_output_p = { dirs_lp {1'b0}} // SNEWP
// credit interface
, parameter use_credits_p = {dirs_lp{1'b0}}
, parameter int fifo_els_p[dirs_lp-1:0] = '{2,2,2,2,2}
)
(
input clk_i
, input reset_i
, input [dirs_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_i
, output [dirs_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_o
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
);
`declare_bsg_ready_and_link_sif_s(width_p,bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [dirs_lp-1:0] link_i_cast, link_o_cast;
assign link_i_cast =link_i;
assign link_o = link_o_cast;
logic [dirs_lp-1:0] fifo_valid;
logic [dirs_lp-1:0][width_p-1:0] fifo_data;
logic [dirs_lp-1:0] fifo_yumi;
genvar i;
//synopsys translate_off
if (debug_p)
for (i = 0; i < dirs_lp;i=i+1)
begin
always_ff @(negedge clk_i)
$display("%m x=%d y=%d SNEWP[%d] v_i=%b ready_o=%b v_o=%b ready_i=%b %b"
,my_x_i,my_y_i,i,link_i_cast[i].v,link_o_cast[i].ready_and_rev,
link_o_cast[i].v,link_i_cast[i].ready_and_rev,link_i[i]);
end
//synopsys translate_on
for (i = 0; i < dirs_lp; i=i+1) begin: rof
if (stub_p[i]) begin: fi
assign fifo_data [i] = width_p ' (0);
assign fifo_valid [i] = 1'b0;
// accept no data from outside of stubbed port
assign link_o_cast[i].ready_and_rev = 1'b0;
// synopsys translate_off
always @(negedge clk_i)
if (link_o_cast[i].v)
$display("## warning %m: stubbed port %x received word %x",i,link_i_cast[i].data);
// synopsys translate_on
end
else begin: fi
logic fifo_ready_lo;
bsg_fifo_1r1w_small #(
.width_p(width_p)
,.els_p(fifo_els_p[i])
) fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i (link_i_cast[i].v )
,.data_i (link_i_cast[i].data )
,.ready_o (fifo_ready_lo)
,.v_o (fifo_valid[i])
,.data_o (fifo_data [i])
,.yumi_i (fifo_yumi [i])
);
if (use_credits_p[i]) begin: cr
bsg_dff_reset #(
.width_p(1)
,.reset_val_p(0)
) dff0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(fifo_yumi[i])
,.data_o(link_o_cast[i].ready_and_rev)
);
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (link_i_cast[i].v) begin
assert(fifo_ready_lo)
else $error("Trying to enque when there is no space in FIFO, while using credit interface. i =%d", i);
end
end
end
// synopsys translate_on
end
else begin
assign link_o_cast[i].ready_and_rev = fifo_ready_lo;
end
end
end
// router does not have symmetric interfaces;
// so we do not use bsg_ready_and_link_sif
// and manually convert. support for arrays
// of interfaces in systemverilog would
// fix this.
logic [dirs_lp-1:0] valid_lo;
logic [dirs_lp-1:0][width_p-1:0] data_lo;
logic [dirs_lp-1:0] ready_li;
for (i = 0; i < dirs_lp; i=i+1)
begin: rof2
assign link_o_cast[i].v = valid_lo[i];
if (repeater_output_p[i] & ~stub_p[i])
begin : macro
wire [width_p-1:0] tmp;
// synopsys translate_off
initial
begin
$display("%m with buffers on %d",i);
end
// synopsys translate_on
bsg_inv #(.width_p(width_p),.vertical_p(i < 3)) data_lo_inv
(.i (data_lo[i] )
,.o(tmp)
);
bsg_inv #(.width_p(width_p),.vertical_p(i < 3)) data_lo_rep
(.i (tmp)
,.o(link_o_cast[i].data)
);
end
else
assign link_o_cast[i].data = data_lo [i];
assign ready_li[i] = link_i_cast[i].ready_and_rev;
end
bsg_mesh_router #( .width_p (width_p )
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.ruche_factor_X_p(ruche_factor_X_p)
,.ruche_factor_Y_p(ruche_factor_Y_p)
,.dims_p (dims_p)
,.XY_order_p (XY_order_p )
) bmr
(.clk_i
,.reset_i
,.v_i (fifo_valid)
,.data_i (fifo_data )
,.yumi_o (fifo_yumi )
,.v_o (valid_lo)
,.data_o(data_lo)
// this will be hardwired to 1 by inside of this module
// if port is stubbed
,.ready_i(ready_li)
,.my_x_i
,.my_y_i
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesh_router_buffered)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> dp; long long fastPow(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret = (ret * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return ret; } long long cc(long long y) { if (dp.find(y) != dp.end()) return dp[y]; dp[y] = fastPow(2, y - 1); for (int i = 2; i * i <= y; i++) { if (!(y % i)) { dp[y] = (dp[y] - cc(i) + 1000000007) % 1000000007; if (i != y / i) { dp[y] = (dp[y] - cc(y / i) + 1000000007) % 1000000007; } } } dp[y]--; return dp[y]; } int main() { long long x, y; cin >> x >> y; if (!(y % x)) { y /= x; if (y == 1) { cout << 1 << endl; return 0; } cout << cc(y) << endl; return 0; } cout << 0 << endl; return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// ,
//
// Create Date: 14:32:00 18/03/2014
// Design Name: stimulus_gen
// Module Name: stimulus_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Stimulus signal generation for gates test - for Testbench
// Used .txt file read function
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module stimulus_gen(clk, rst, req, stm_value, rsb, gnt);
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
input clk;
input rst;
input req;
output [INPUT_PORTS-1: 0] stm_value;
output rsb;
output gnt;
reg rsb;
reg gnt;
reg [INPUT_PORTS-1:0] data;
integer fd;
integer code, dummy;
reg [(INPUT_PORTS)*8-1:0] str;
assign stm_value = data;
initial begin
rsb = 1'b0;
gnt = 1'b0;
@(posedge clk);
#100;
@(posedge clk);
wait (req == 1'b1);
@(posedge clk);
//@(posedge clk);
if(RESET_PORT == 0) begin
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added because of <CR><LF> of .txt file
rsb = 1'b0;
$monitor("data = %b", data);
@(posedge clk);
end
end
else if(RESET_PORT == 1) begin
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added because of <CR><LF> of .txt file
rsb = 1'b0; // Reset generation to 0
$monitor("data = %b", data);
@(posedge clk);
end
// close the file for next file open
$fclose(fd);
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added to remove <CR><LF> of .txt file
rsb = 1'b1; // Reset generation to 1
$monitor("data = %b", data);
@(posedge clk);
end
$fclose(fd);
end
@(posedge clk);
gnt = 1'b1;
@(posedge clk);
gnt = 1'b0;
#100;
end
endmodule
//////////////////////////////////////////////////////////
// Example
//////////////////////////////////////////////////////////
// 3-input stimulus example
// Null to Data sequence
// 000
// ->
// 001 010 100
// -> -> ->
// 011 101 011 110 101 110
// -> -> -> -> -> ->
// 111 111 111 111 111 111
// 000
// 001
// 011
// 111
// 000
// 001
// 101
// 111
// 000
// 010
// 011
// 111
// 000
// 010
// 110
// 111
// 000
// 100
// 101
// 111
// 000
// 100
// 110
// 111
// Alse we need to check more than two value change cases
// 000
// 011
// 111
// 000
// 110
// 111
// 000
// 101
// 111
// 000
// 111
// Data to Null sequence
// 111
// ->
// 110 101 011
// -> -> ->
// 100 010 100 001 010 001
// -> -> -> -> -> ->
// 000 000 000 000 000 000
// 111
// 110
// 100
// 000
// 111
// 110
// 010
// 000
// 111
// 101
// 100
// 000
// 111
// 101
// 001
// 000
// 111
// 011
// 010
// 000
// 111
// 011
// 001
// 000
// Alse we need to check more than two value change cases
// 111
// 100
// 000
// 111
// 001
// 000
// 111
// 010
// 000
// 111
// 000
// NCL doesn't allow these type of signal changes
// 0000
// 0100
// 0010 -> This is illegal
// 0011
// 1100 -> This is illegal
|
#include <bits/stdc++.h> using namespace std; const double eps(1e-8); const double pi(3.14159265358979); const int K = 33, mod = 1000000007; struct matrix { long long a[K][K]; } t[K] = {}, ans = {{}}, pre[K] = {}, suf[K] = {}; long long n; int k; inline void multi(const matrix &m1, const matrix &m2, matrix &to) { static matrix tmp = {{}}; for (int i = 0; i <= k; ++i) for (int j = 0; j <= k; ++j) { tmp.a[i][j] = 0; for (int p = 0; p <= k; ++p) (tmp.a[i][j] += m1.a[i][p] * m2.a[p][j]) %= mod; } to = tmp; } void init() { cin >> n >> k; for (int i = 0; i <= k; ++i) for (int j = 0; j <= k; ++j) ans.a[i][j] = i == j; for (int p = 0; p < k; ++p) for (int i = 0; i <= k; ++i) for (int j = 0; j <= k; ++j) t[p].a[i][j] = i == j || i == p; } void work() { vector<int> bit; for (; n; n /= k) bit.push_back(n % k); bit.push_back(0); partial_sum(bit.rbegin(), bit.rend(), bit.rbegin()); for (auto p = 0u; p < bit.size() - 1; ++p) { for (int i = bit[p] - 1; i >= bit[p + 1]; --i) multi(t[i % k], ans, ans); pre[0] = t[0]; for (int i = 1; i < k; ++i) multi(pre[i - 1], t[i], pre[i]); suf[k - 1] = t[k - 1]; for (int i = k - 2; i >= 0; --i) multi(t[i], suf[i + 1], suf[i]); t[0] = suf[0]; for (int i = 1; i < k; ++i) multi(suf[i], pre[i - 1], t[i]); } long long sum = 0; for (int i = 0; i <= k; ++i) sum += ans.a[i][k]; cout << sum % mod << endl; } int main() { init(); work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, c, a[2], r = 0; int main() { cin >> n >> c >> a[0]; for (int i = 1; i < n; i++) cin >> a[i % 2], r = max(r, a[i % 2 ^ 1] - a[i % 2] - c); cout << r; }
|
module top;
reg pass;
reg [2:-1] vec;
initial begin
pass = 1'b1;
vec = 4'bxxxx;
assign vec[1'bx] = 1'b1;
if (vec !== 4'bxxx) begin
$display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx];
vec = 4'bxxxx;
assign vec[1'bx:0] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx:0];
vec = 4'bxxxx;
assign vec[0:1'bx] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[0:1'bx];
vec = 4'bxxxx;
assign vec[1'bx:1'bx] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx:1'bx];
vec = 4'bxxxx;
assign vec[1'bx+:1] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx+:1];
vec = 4'bxxxx;
assign vec[1'bx+:2] = 2'b01;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx+:2];
vec = 4'bxxxx;
assign vec[1'bx-:1] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx-:1];
vec = 4'bxxxx;
assign vec[1'bx-:2] = 2'b01;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
deassign vec[1'bx-:2];
if (pass) $display("PASSED");
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for cic_interpolator
*/
module test_cic_interpolator;
// Parameters
parameter WIDTH = 16;
parameter RMAX = 4;
parameter M = 1;
parameter N = 2;
parameter REG_WIDTH = WIDTH+$max(N, $clog2(((RMAX*M)**N)/RMAX));
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_tdata = 0;
reg input_tvalid = 0;
reg output_tready = 0;
reg [$clog2(RMAX+1)-1:0] rate = 0;
// Outputs
wire input_tready;
wire [REG_WIDTH-1:0] output_tdata;
wire output_tvalid;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_tdata,
input_tvalid,
output_tready,
rate);
$to_myhdl(input_tready,
output_tdata,
output_tvalid);
// dump file
$dumpfile("test_cic_interpolator.lxt");
$dumpvars(0, test_cic_interpolator);
end
cic_interpolator #(
.WIDTH(WIDTH),
.RMAX(RMAX),
.M(M),
.N(N)
)
UUT (
.clk(clk),
.rst(rst),
.input_tdata(input_tdata),
.input_tvalid(input_tvalid),
.input_tready(input_tready),
.output_tdata(output_tdata),
.output_tvalid(output_tvalid),
.output_tready(output_tready),
.rate(rate)
);
endmodule
|
module RAMB16_S9_S9(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [10:0] ADDRA,
input [7:0] DIA,
input DIPA,
// output [3:0] DOPA,
output [7:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [10:0] ADDRB,
input [7:0] DIB,
input DIPB,
// output [3:0] DOPB,
output [7:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(8),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(DIPA),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(DIPB),.DOB(DOB));
endmodule
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : ethernet_controller.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Ethernet Controller Module
//
//--------------------------------------------------------------------------------
// (c) Copyright 2004-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
`timescale 1 ps/1 ps
//------------------------------------------------------------------------------
// The entity declaration for the example_design level wrapper.
//------------------------------------------------------------------------------
module v7_ethernet_controller #(
parameter tx_dst_addr = 48'h001F293A10FD,
tx_src_addr = 48'hAABBCCDDEEFF,
tx_max_data_size = 16'd1024,
rx_dst_addr=48'hAABBCCDDEEFF)
(
// asynchronous reset
input glbl_rst,
// 200MHz clock input from board
input clkin200,
output phy_resetn,
//added SGMII serial data and reference clock ports
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
input loop_back_en,
// AXI stream i/f
//-----------------------------
output o_axi_rx_clk,
output o_axi_rx_rst_n,
output [7:0] o_axi_rx_tdata,
output o_axi_rx_data_tvalid,
output o_axi_rx_data_tlast,
input i_axi_rx_data_tready,
output o_axi_tx_clk,
output o_axi_tx_rst_n,
input [7:0] i_axi_tx_tdata,
input i_axi_tx_data_tvalid,
output o_axi_tx_data_tready,
input i_axi_tx_data_tlast,
output o_tx_mac_count
);
//----------------------------------------------------------------------------
// internal signals used in this top level wrapper.
//----------------------------------------------------------------------------
wire rx_fifo_clock;
wire rx_fifo_resetn;
wire rx_axis_fifo_tvalid;
wire [7:0] rx_axis_fifo_tdata;
wire rx_axis_fifo_tlast;
wire rx_axis_fifo_tready;
wire tx_fifo_clock;
wire tx_fifo_resetn;
wire [7:0] tx_axis_fifo_tdata;
wire tx_axis_fifo_tvalid;
wire tx_axis_fifo_tlast;
wire tx_axis_fifo_tready;
reg phy_init_d1;
//----------------------------------------------------------------------------
// Instantiate the V6 Hard EMAC core fifo block wrapper
//----------------------------------------------------------------------------
v7_emac_controller ec(
.glbl_rst(glbl_rst),
.clkin200(clkin200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_i),
.mdio_t(mdio_t),
.mdio_o(mdio_o),
.mdc(mdc),
.rx_fifo_clk(rx_fifo_clock),
.rx_fifo_rstn(rx_fifo_resetn),
.rx_axis_fifo_tdata(rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid(rx_axis_fifo_tvalid),
.rx_axis_fifo_tready(rx_axis_fifo_tready),
.rx_axis_fifo_tlast(rx_axis_fifo_tlast),
.tx_fifo_clk(tx_fifo_clock),
.tx_fifo_rstn(tx_fifo_resetn),
.tx_axis_fifo_tdata(tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid(tx_axis_fifo_tvalid),
.tx_axis_fifo_tready(tx_axis_fifo_tready),
.tx_axis_fifo_tlast(tx_axis_fifo_tlast),
.o_tx_mac_count(o_tx_mac_count),
.loop_back_en(loop_back_en)
);
//Eth receive side unpacking
eth_rcr_unpack #(
.unpack_dst_addr(rx_dst_addr)
)
eth_unpack
(
.i_axi_rx_clk(rx_fifo_clock),
.i_axi_rx_rst_n(rx_fifo_resetn),
.i_rx_axis_fifo_tvalid(rx_axis_fifo_tvalid),
.i_rx_axis_fifo_tdata(rx_axis_fifo_tdata),
.i_rx_axis_fifo_tlast(rx_axis_fifo_tlast),
.o_rx_axis_fifo_tready(rx_axis_fifo_tready),
.o_axi_rx_clk(o_axi_rx_clk),
.o_axi_rx_rst_n(o_axi_rx_rst_n),
.o_axi_rx_tdata(o_axi_rx_tdata),
.o_axi_rx_data_tvalid(o_axi_rx_data_tvalid),
.i_axi_rx_data_tready(i_axi_rx_data_tready),
.o_axi_rx_data_tlast(o_axi_rx_data_tlast),
.loop_back(loop_back_en)
);
eth_tcr_pack #(
.dst_addr(tx_dst_addr),
.src_addr(tx_src_addr),
.max_data_size(tx_max_data_size)
)
eth_pack(
.o_axi_tx_clk(o_axi_tx_clk),
.o_axi_tx_rst_n(o_axi_tx_rst_n),
.i_axi_tx_tdata(i_axi_tx_tdata),
.i_axi_tx_data_tvalid(i_axi_tx_data_tvalid),
.o_axi_tx_data_tready(o_axi_tx_data_tready),
.i_axi_tx_data_tlast(i_axi_tx_data_tlast),
.i_axi_tx_clk(tx_fifo_clock),
.i_axi_tx_rst_n(tx_fifo_resetn),
.o_tx_axis_fifo_tvalid(tx_axis_fifo_tvalid),
.o_tx_axis_fifo_tdata(tx_axis_fifo_tdata),
.o_tx_axis_fifo_tlast(tx_axis_fifo_tlast),
.i_tx_axis_fifo_tready(tx_axis_fifo_tready)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file inside CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of register file memories ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_rf(
// Clock and reset
clk, rst,
// Write i/f
supv, wb_freeze, addrw, dataw, we, flushpipe,
// Read i/f
id_freeze, addra, addrb, dataa, datab, rda, rdb,
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Write i/f
//
input supv;
input wb_freeze;
input [aw-1:0] addrw;
input [dw-1:0] dataw;
input we;
input flushpipe;
//
// Read i/f
//
input id_freeze;
input [aw-1:0] addra;
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
//
// SPR access for debugging purposes
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [dw-1:0] from_rfa;
wire [dw-1:0] from_rfb;
reg [dw:0] dataa_saved;
reg [dw:0] datab_saved;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrw;
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
reg rf_we_allow;
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(posedge rst or posedge clk)
if (rst)
rf_we_allow <= #1 1'b1;
else if (~wb_freeze)
rf_we_allow <= #1 ~flushpipe;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
// assign rf_ena = 1'b1; // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze | spr_valid;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
dataa_saved <= #1 33'b0;
end
else if (id_freeze & !dataa_saved[32]) begin
dataa_saved <= #1 {1'b1, from_rfa};
end
else if (!id_freeze)
dataa_saved <= #1 33'b0;
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
datab_saved <= #1 33'b0;
end
else if (id_freeze & !datab_saved[32]) begin
datab_saved <= #1 {1'b1, from_rfb};
end
else if (!id_freeze)
datab_saved <= #1 33'b0;
`ifdef OR1200_RFRAM_TWOPORT
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
.di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
.di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
`else
`ifdef OR1200_RFRAM_DUALPORT
//
// Instantiation of register file two-port RAM A
//
or1200_dpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.oe_a(1'b1),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
//
// Instantiation of register file two-port RAM B
//
or1200_dpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.oe_a(1'b1),
.addr_a(addrb),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
`else
`ifdef OR1200_RFRAM_GENERIC
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
// Clock and reset
.clk(clk),
.rst(rst),
// Port A
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.ce_b(rf_enb),
.addr_b(addrb),
.do_b(from_rfb),
// Port W
.ce_w(rf_we),
.we_w(rf_we),
.addr_w(rf_addrw),
.di_w(rf_dataw)
);
`else
//
// RFRAM type not specified
//
initial begin
$display("Define RFRAM type.");
$finish;
end
`endif
`endif
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 500; const int maxm = 500000 + 10; struct Edge { int next, v; Edge() {} Edge(int next, int v) : next(next), v(v) {} } e[maxm << 1]; int n, m, timer, num, len; int head[maxm], cnt; int dfn[maxn], low[maxn], belo[maxn]; bool inst[maxn], used[maxn]; int st[maxm], top, q[maxm], front, tail; char org[27], s[maxn], ans[maxn], res[maxn]; int val[128]; inline int read() { int x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } inline void AddEdge(int u, int v) { e[++cnt] = Edge(head[u], v); head[u] = cnt; } void tarjan(int u) { dfn[u] = low[u] = ++timer; st[++top] = u; inst[u] = 1; for (int i = head[u]; i; i = e[i].next) { int v = e[i].v; if (!dfn[v]) { tarjan(v); low[u] = min(low[u], low[v]); } else if (inst[v]) low[u] = min(low[u], dfn[v]); } if (dfn[u] == low[u]) { num++; int v; do { v = st[top--]; belo[v] = num; inst[v] = 0; } while (u != v); } } inline bool judge(int tot) { for (int i = 2; i <= tot; i++) if (!dfn[i]) tarjan(i); for (int i = 2; i < tot; i += 2) if (belo[i] == belo[i + 1]) return 0; return 1; } inline char find(int pos, char ch) { for (int i = pos + 1; i < len; i++) if (org[i] == ch) return a + i; return -1; } int main() { scanf( %s , org); len = strlen(org); for (int i = 0; i < len; i++) if (org[i] == C ) val[ a + i] = 1; n = read(), m = read(); char op1[10], op2[10]; int x, y; while (m--) { x = read(), scanf( %s , op1); y = read(), scanf( %s , op2); x = x << 1 | (op1[0] == C ); y = y << 1 | (op2[0] == C ); AddEdge(x, y); AddEdge(y ^ 1, x ^ 1); } scanf( %s , s + 1); if (!judge(n << 1 | 1)) { puts( -1 ); return 0; } bool exis = 0; res[1] = -1; for (int pos = n + 1; pos >= 1; pos--) { for (int a = pos << 1; a <= (pos << 1 | 1); a++) { strcpy(ans + 1, s + 1); if (pos <= n) { char tp = find(s[pos] - a , a & 1 ? V : C ); if (tp == -1) continue; ans[pos] = tp; } for (int i = pos + 1; i <= n; i++) ans[i] = a ; bool flag = 1; memset(used, 0, sizeof(used)); for (int i = 1; i <= n && flag; i++) { x = i << 1 | val[ans[i]]; if (used[x]) continue; used[x] = 1; front = tail = 0; q[++tail] = x; while (front != tail) { x = q[++front]; used[x] = 1; if (used[x ^ 1]) { flag = 0; break; } if ((x >> 1) <= pos && val[ans[x >> 1]] != (x & 1)) { flag = 0; break; } if ((x >> 1) > pos) { char tp = find(-1, x & 1 ? C : V ); if (tp == -1) { flag = 0; break; } ans[x >> 1] = tp; } for (int j = head[x]; j; j = e[j].next) { int v = e[j].v; if (!used[v]) { used[v] = 1; q[++tail] = v; } } } } if (!flag) continue; exis = 1; if (res[1] == -1) strcpy(res + 1, ans + 1); else if (strcmp(res + 1, ans + 1) > 0) strcpy(res + 1, ans + 1); } if (exis) break; } if (exis) puts(res + 1); else puts( -1 ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int N, dp[5000][5001], cumlcp[5000][5000]; vector<int> sa, ra, rsa, lcp; string s; void saInit() { int l = (int)s.size(); sa.resize(l); iota(sa.begin(), sa.end(), 0); ra.assign(s.begin(), s.end()); for (int k = 1; k < l; k *= 2) { sort(sa.begin(), sa.end(), [&](int a, int b) { if (ra[a] != ra[b]) return ra[a] < ra[b]; int ak = a + k < l ? ra[a + k] : -1; int bk = b + k < l ? ra[b + k] : -1; return ak < bk; }); vector<int> ra2(l); int x = 0; for (int i = 1; i < l; i++) { if (ra[sa[i]] != ra[sa[i - 1]] || sa[i - 1] + k >= l || ra[sa[i] + k] != ra[sa[i - 1] + k]) x++; ra2[sa[i]] = x; } ra = ra2; } rsa.resize(l); for (int i = 0; i < int(l); i++) rsa[sa[i]] = i; } void saLCP() { int l = (int)s.size(); lcp.resize(l); vector<int> p(l); for (int i = 0; i < l; i++) { p[sa[i]] = (i) ? sa[i - 1] : -1; } int x = 0; for (int i = 0; i < l; i++) { while (p[i] != -1 && p[i] + x < l && s[i + x] == s[p[i] + x] && s[i + x] != $ ) x++; lcp[rsa[i]] = x; if (x) x--; } for (int i = 0; i < int(l); i++) { cumlcp[i][i] = INT_MAX; for (int j = i + 1; j < int(l); j++) cumlcp[i][j] = min(cumlcp[i][j - 1], lcp[j]); } } bool ism(int a, int b, int n) { int as = a - n + 1, bs = b - n + 1; if (as < 0) return false; if (rsa[bs] <= rsa[as]) return false; return cumlcp[rsa[as]][rsa[bs]] < n; } int main() { cin >> N >> s; saInit(); saLCP(); for (int i = 0; i < int(N); i++) for (int j = 1; j < int(5001); j++) { int& ans = dp[i][j]; ans = dp[i][j - 1]; if (j > i + 1) { continue; } else if (s[i - j + 1] == 0 ) { } else if (j == i + 1) { ans = (ans + 1) % MOD; } else if (ism(i - j, i, j)) { ans = (ans + dp[i - j][j]) % MOD; } else { ans = (ans + dp[i - j][j - 1]) % MOD; } } cout << dp[N - 1][N] << endl; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 10; int SL[MAXN], SR[MAXN]; int A[MAXN][2], n; int main() { while (~scanf( %d , &n)) { SL[0] = SR[0] = 0; for (int i = 1; i <= n; i++) { scanf( %d%d , &A[i][0], &A[i][1]); SL[i] = A[i][0] + SL[i - 1]; SR[i] = A[i][1] + SR[i - 1]; } int maxn = abs(SL[n] - SR[n]); int ans = 0; for (int i = 1; i <= n; i++) { int _SL = SL[n] - A[i][0] + A[i][1]; int _SR = SR[n] - A[i][1] + A[i][0]; int _ans = abs(_SL - _SR); if (maxn < _ans) { maxn = _ans; ans = i; } } printf( %d n , ans); } return 0; }
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// /**
// *
// */
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : altpcierd_npcred_monitor
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_npcred_monitor.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
//
// Description: This module monitors NonPosted header credits.
// It implements the algorithm for sampling tx_cred from
// the core, and accounts for in-flight TLPs.
//-----------------------------------------------------------------------------
// Copyright © 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_npcred_monitor # (
parameter CRED_LAT = 10 // # clks for np_sent to be reflected on np_cred_hip
) (
input clk_in,
input rstn,
input [2:0] np_cred, // from HIP.
input np_sent, // this is NP TLP being issued from source logic that is doing credit check gating
input np_tx_sent, // indicates NP TLP has been transmitted onto AV-ST (xx clks later, will be reflected on np_cred)
output reg have_cred // indicates to source logic that there is atleast 1 NP credit.
);
localparam LATCH_CRED = 2'h0;
localparam GRANT_CRED = 2'h1;
localparam WAIT_LAST_NP_TX = 2'h2;
localparam WAIT_CRED_UPD = 2'h3;
reg[2:0] cred_sm;
reg[2:0] local_creds_avail;
reg[7:0] creds_granted;
reg[7:0] latency_counter;
reg[7:0] creds_sent_on_tx; // count # of NPs that made it out onto AV-ST interface
wire update_creds;
assign update_creds = (cred_sm==LATCH_CRED) & (np_cred > 0);
always @ (negedge rstn or posedge clk_in) begin
if (rstn==1'b0) begin
cred_sm <= LATCH_CRED;
local_creds_avail <= 3'h0;
creds_sent_on_tx <= 8'h0;
creds_granted <= 8'h0;
end
else begin
//-------------------------------------
// track NP TLPs being sent on AV-ST TX
if (update_creds) begin
creds_sent_on_tx <= 8'h0;
end
else if (np_tx_sent) begin
creds_sent_on_tx <= creds_sent_on_tx + 8'h1;
end
//----------------------------
// monitor available TX creds
case (cred_sm)
LATCH_CRED: begin
latency_counter <= 8'h0;
local_creds_avail <= np_cred;
creds_granted <= np_cred;
if (np_cred > 0) begin
cred_sm <= GRANT_CRED;
have_cred <= 1'b1;
end
else begin
cred_sm <= cred_sm;
have_cred <= 1'b0;
// have_cred <= 1'b1;
end
end
GRANT_CRED: begin
// Grant credits until
// all all creds used
local_creds_avail <= np_sent ? local_creds_avail-3'h1 : local_creds_avail;
have_cred <= (local_creds_avail==3'h1) & np_sent ? 1'b0 : 1'b1;
if ((local_creds_avail==3'h1) & np_sent) begin
cred_sm <= WAIT_LAST_NP_TX;
end
else begin
cred_sm <= cred_sm;
end
end
WAIT_LAST_NP_TX: begin
// wait for all NP's to be
// transmitted on AV-ST
if (creds_sent_on_tx == creds_granted) begin
cred_sm <= WAIT_CRED_UPD;
end
else begin
cred_sm <= cred_sm;
end
end
WAIT_CRED_UPD: begin
latency_counter <= latency_counter + 8'h1;
if (latency_counter==CRED_LAT) begin
cred_sm <= LATCH_CRED;
end
else begin
cred_sm <= cred_sm;
end
end
endcase
end
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module small_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [71:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [71:0] q;
output [2:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL data[71..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL q[71..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: USED_PORT: usedw 0 0 3 0 OUTPUT NODEFVAL usedw[2..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 3 0 @usedw 0 0 3 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, i, j, k, l1 = 1, l2 = 1, s, r[7], z = 0; cin >> n >> m; for (i = 7; i < n; i *= 7) l1++; for (i = 7; i < m; i *= 7) l2++; if (l1 + l2 < 8) for (i = 0; i < n; ++i) for (j = 0; j < m; ++j) { for (k = 0; k < 7; ++k) r[k] = 0; for (s = i, k = 0; k < l1; s /= 7, ++k) r[s % 7]++; for (s = j, k = 0; k < l2; s /= 7, ++k) r[s % 7]++; for (k = 0; k < 7; k++) if (r[k] > 1) break; if (k == 7) z++; } cout << z; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/15/2015 07:58:09 AM
// Design Name:
// Module Name: SerialServo_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SerialHandler_tb;
parameter POSITION_WIDTH = 11;
reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [POSITION_WIDTH-1:0] position_output;
reg [7:0] data_in [1:0];
SerialHandler U0(
.clk100MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.ser_pos(position_output)
);
integer i = 0;
integer state = 0;
initial
begin
ext_clk = 0;
rst = 1;
ext_flush = 0;
serial = 0;
//serial_register[0] = 16'b0_00000_1111111111;
data_in[0] = 8'b11111_111;
data_in[1] = 8'b1111_1111;
#5
ext_flush = 1;
rst = 0;
#5
ext_flush = 0;
state = 1;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[0][7-i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
state = 2;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][7-i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
state = 3;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
#5
ext_flush = 1;
#5
ext_flush = 0;
#50
#10 $stop;
#5 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int B, n, m; int li[500008], ri[500008], mx[500008], tag[500008]; short g[480][100008]; int bel[500008], de[500008], ai[500008], pa[500008]; short size[500008]; int find(int x) { if (pa[x] == x) return x; return pa[x] = find(pa[x]); } void link(int x, int y) { if (x == y) return; if (size[x] > size[y]) swap(x, y); pa[x] = y; size[y] += size[x]; } int tot; int lst[500008], stamp[500008]; void makeup(int id) { ++tot; mx[id] = 0; for (int i = li[id]; i <= ri[id]; i++) pa[i] = i, size[i] = 1; for (int i = li[id]; i <= ri[id]; i++) { int x = ai[i]; mx[id] = max(mx[id], x); if (stamp[x] != tot) stamp[x] = tot, g[id][x] = lst[x] = i - li[id]; else link(i, g[id][x] + li[id]), g[id][x] = find(g[id][x] + li[id]) - li[id]; } } void pushdown(int id) { for (int i = li[id]; i <= ri[id]; i++) g[id][ai[i]] = -1; for (int i = li[id]; i <= ri[id]; i++) { g[id][ai[i] + de[i]] = -1; if (find(i) == i) ai[i] = ai[i] + de[i] - tag[id]; de[i] = 0; } for (int i = li[id]; i <= ri[id]; i++) ai[i] = ai[find(i)]; tag[id] = 0; } void refresh(int id) { while (-1 == g[id][mx[id]]) mx[id]--; } int cnt = 0; void subtract(int id, int x) { if (mx[id] - tag[id] <= x) return; if (mx[id] - tag[id] > x * 2 + 1 and 1) { for (int i = tag[id] + 1; i <= x + tag[id]; i++) if (g[id][i] != -1) { int j = i + x; de[g[id][i] + li[id]] += x; if (g[id][j] != -1) link(g[id][i] + li[id], g[id][j] + li[id]), g[id][j] = find(g[id][j] + li[id]) - li[id]; else g[id][j] = g[id][i]; g[id][i] = -1; } tag[id] += x; } else { for (int i = x + 1 + tag[id]; i <= mx[id]; i++) if (g[id][i] != -1) { int j = i - x; de[g[id][i] + li[id]] -= x; if (g[id][j] != -1) link(g[id][j] + li[id], g[id][i] + li[id]), g[id][j] = find(g[id][j] + li[id]) - li[id]; else g[id][j] = g[id][i]; g[id][i] = -1; } refresh(id); } } int ask(int id, int x) { if (x + tag[id] > 100001) return 0; if (g[id][x + tag[id]] == -1) return 0; g[id][x + tag[id]] = find(g[id][x + tag[id]] + li[id]) - li[id]; return size[g[id][x + tag[id]] + li[id]]; } signed main() { memset(g, -1, sizeof g); scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &ai[i]); B = sqrt(n); B = max(B, n / 475); memset(li, 0x3f, sizeof li); for (int i = 1; i <= n; i++) { bel[i] = i / B; li[bel[i]] = min(li[bel[i]], i); ri[bel[i]] = i; } for (int i = 0; i <= n / B; i++) makeup(i); while (m--) { int op, l, r, x; scanf( %d%d%d%d , &op, &l, &r, &x); if (op == 1) { if (bel[l] == bel[r]) { pushdown(bel[l]); for (int i = l; i <= r; i++) if (ai[i] > x) ai[i] -= x; makeup(bel[l]); } else { pushdown(bel[l]); for (int i = l; i <= ri[bel[l]]; i++) if (ai[i] > x) ai[i] -= x; pushdown(bel[r]); for (int i = li[bel[r]]; i <= r; i++) if (ai[i] > x) ai[i] -= x; makeup(bel[l]); makeup(bel[r]); for (int i = bel[l] + 1; i < bel[r]; i++) subtract(i, x); } } else { int ans = 0; if (bel[l] == bel[r]) { pushdown(bel[l]); for (int i = l; i <= r; i++) if (ai[i] == x) ans++; makeup(bel[l]); printf( %d n , ans); } else { pushdown(bel[l]); for (int i = l; i <= ri[bel[l]]; i++) ans += (ai[i] == x); pushdown(bel[r]); for (int i = li[bel[r]]; i <= r; i++) ans += (ai[i] == x); makeup(bel[l]); makeup(bel[r]); for (int i = bel[l] + 1; i < bel[r]; i++) ans += ask(i, x); printf( %d n , ans); } } ++cnt; if (cnt < -7) { for (int i = 0; i <= n / B; i++) pushdown(i); for (int i = 1; i <= n; i++) cout << ai[i] << ; cout << g[2][30] << : n n ; for (int i = 0; i <= n / B; i++) makeup(i); } } return 0; }
|
module Microfono(clk, reset, rec, play, bclk, lrsel, data_in, data_out, ampSD, rd, wr, emptyLED, fullLED);
input wire clk;
input wire reset;
input wire rec;
input wire play;
output wire bclk;
output wire lrsel;
input wire data_in;
output wire data_out;
output wire ampSD;
output wire rd;
output wire wr;
output wire emptyLED;
output wire fullLED;
wire empty;
wire full;
wire RstN;
wire FClrN;
wire F_LastN;
wire F_SLastN;
wire F_FirstN;
reg [5:0] fifo_counter = 0;
reg fclk = 1'b0;
assign FClrN = 1'b1;
assign emptyLED = ~empty;
assign fullLED = ~full;
always @(posedge bclk) // bclk = 1MHz
begin
if (reset)
begin
fifo_counter = 0;
fclk = 1'b1;
end
else
if (fifo_counter == 2) // fclk = 500KHz
begin
fifo_counter = 1;
fclk = ~fclk;
end
else
begin
fifo_counter = fifo_counter + 1;
fclk = fclk;
end
end
assign lrsel = 1'b0; //mic LRSel
assign ampSD = 1'b1;
DivFreq _DivFreq(
.reset(reset),
.clk(clk),
.bclk(bclk) // reloj de 1MHz
);
fifo _fifo(
.Clk(bclk), // reloj de la fifo
.RstN(~reset),
.Data_In(data_in),
.FClrN(FClrN),
.FInN(~wr),
.FOutN(~rd),
.F_Data(data_out),
.F_FullN(full),
.F_LastN(F_LastN),
.F_SLastN(F_SLastN),
.F_FirstN(F_FirstN),
.F_EmptyN(empty)
);
FSM _FSM(
.reset(reset),
.clk(clk),
.full(~full),
.empty(~empty),
.rec(rec),
.play(play),
.wr(wr),
.rd(rd)
);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous SDR output
*/
module ssio_sdr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(clk),
.d1(1'b0),
.d2(1'b1),
.q(output_clk)
);
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk) begin
output_q_reg <= input_d;
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_SYMBOL_V
`define SKY130_FD_SC_HS__NAND4BB_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0); int n; cin >> n; int ats = 0; list<int> kruv; int kur = 1; for (int i = 0; i < 2 * n; i++) { string c; cin >> c; if (c[0] == a ) { int nr; cin >> nr; kruv.push_front(nr); } else { if (kruv.size() > 0 and *kruv.begin() != kur) { ats++; kruv.erase(kruv.begin(), kruv.end()); } else if (kruv.size() > 0) kruv.erase(kruv.begin()); kur++; } } cout << ats; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_streeOg_DSP48_3(
input [9 - 1:0] in0,
input [23 - 1:0] in1,
input [31 - 1:0] in2,
output [32 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $signed(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_streeOg(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_streeOg_DSP48_3 hls_contrast_streeOg_DSP48_3_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; struct edge { int v, next; }; int ans, ans2, f[1005][1 << 12]; int Pow(int a, int b) { int rec = 1; for (; b; b >>= 1, a = 1ll * a * a % mod) if (b & 1) rec = 1ll * rec * a % mod; return rec; } struct nade { int head[1005], edgenum, d[1005][1005], num[1005], sta[1005], n; edge e[1005 << 1]; void add(int u, int v) { e[++edgenum] = edge{v, head[u]}; head[u] = edgenum; } void dfs(int u, int fa) { num[u] = sta[u] = 0; for (int i = head[u], v; i; i = e[i].next) if ((v = e[i].v) ^ fa) { dfs(d[u][num[u]++] = v, u); sta[u] |= 1 << v - 1; } } } s, t; int dfs(int u, int i, int sta) { if (!i) return !sta; int &rec = f[s.d[u][i - 1]][sta]; if (rec != -1) return rec; rec = dfs(u, i - 1, sta); for (int v = s.d[u][i - 1], k = 0; k < t.n; k++) if (sta >> k & 1) rec = (rec + 1ll * dfs(u, i - 1, sta ^ (1 << k)) * dfs(v, s.num[v], t.sta[k + 1])) % mod; return rec; } int main() { scanf( %d , &s.n); for (int i = 1, u, v; i < s.n; i++) { scanf( %d%d , &u, &v); s.add(u, v); s.add(v, u); } scanf( %d , &t.n); for (int i = 1, u, v; i < t.n; i++) { scanf( %d%d , &u, &v); t.add(u, v); t.add(v, u); } s.dfs(1, 0); memset(f, -1, sizeof f); for (int r = 1; r <= t.n; r++) { t.dfs(r, 0); for (int i = 1; i <= s.n; i++) ans = (ans + dfs(i, s.num[i], t.sta[r])) % mod; memset(f, -1, sizeof f); } s = t; s.dfs(1, 0); for (int r = 1; r <= t.n; r++) { t.dfs(r, 0); ans2 = (ans2 + dfs(1, s.num[1], t.sta[r])) % mod; memset(f, -1, sizeof f); } ans = 1ll * ans * Pow(ans2, mod - 2) % mod; printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int cycl[N], set_val[N], cycl_size[N]; int main() { int h, m, n; cin >> h >> m >> n; vector<int> strt; bool vis[h]; memset(vis, false, sizeof vis); int kk = 0; set<int> dmm[h + 1]; for (long long i = 0; i < m; i++) { if (vis[i]) { continue; } int ii = i; int jp = 0; while (1) { if (vis[ii]) { break; } set_val[ii] = jp; cycl[ii] = kk; dmm[kk].insert(jp); vis[ii] = true; ii += m; ii %= h; jp++; } cycl_size[kk] = jp; kk++; } map<int, int> hash; map<int, int> final; long long cnt = 0; while (n--) { char ch; scanf( %c , &ch); if (ch == + ) { int id, t; scanf( %d%d , &id, &t); hash[id] = t; if (dmm[cycl[t]].find(set_val[t]) != dmm[cycl[t]].end()) { final[id] = set_val[t]; dmm[cycl[t]].erase(set_val[t]); continue; } set<int>::iterator it, it1; it = dmm[cycl[t]].lower_bound(set_val[t]); int xx1; if (it == dmm[cycl[t]].end()) { it = dmm[cycl[t]].begin(); xx1 = cycl_size[cycl[t]] + *it - set_val[t]; int jj = *it; final[id] = jj; dmm[cycl[t]].erase(jj); } else { xx1 = *it - set_val[t]; int jj = *it; final[id] = jj; dmm[cycl[t]].erase(jj); } cnt += (long long)xx1; } else { int id; scanf( %d , &id); dmm[cycl[hash[id]]].insert(final[id]); } } cout << cnt << endl; }
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFSTP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_SYMBOL_V
|
#include <bits/stdc++.h> const int N = 100005; int K, n, maxb, t; int c[N]; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void update(int x, int d) { while (x <= maxb) { if (d > c[x]) c[x] = d; x += x & -x; } } int get(int x) { int ans = 0; while (x > 0) { ans = std::max(ans, c[x]); x -= x & -x; } return ans; } int a[N], ans[N]; int cal() { memset(c, 0, sizeof(c)); memset(ans, 0, sizeof(ans)); for (int i = 1; i <= t; i++) for (int j = 1; j <= n; j++) { int k = get(a[j] - 1) + 1; if (k > ans[j]) { ans[j] = k; update(a[j], k); } } return *std::max_element(ans + 1, ans + n + 1); } int main() { K = read(), n = read(), maxb = read(), t = read(); t = std::min(maxb, t); while (K--) { for (int i = 1; i <= n; i++) a[i] = read(); printf( %d n , cal()); } }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.3 2007/03/05 13:33:59 wig Exp $
// $Date: 2007/03/05 13:33:59 $
// $Log: ent_ae.v,v $
// Revision 1.3 2007/03/05 13:33:59 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No user `defines in this module
module ent_ae
//
// Generated Module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
reg [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; bitset<300000005> pr; int uke[20000005]; int anti_uke(int l, int r) { int ans = 0; for (register int i = 5; i <= r; i += 4) { if (i >= l && pr[i] == 0) ++ans; } if (l <= 2 && r >= 2) ++ans; return ans; } int main() { int l, r; scanf( %d %d , &l, &r); pr[0] = pr[1] = 1; int cnt = 0; for (register int i = 2; i <= r; i++) { if (pr[i] == 0) uke[++cnt] = i; for (register int j = 1; j <= cnt && i * uke[j] <= r; j++) { pr[i * uke[j]] = 1; if (i % uke[j] == 0) break; } } printf( %d n , anti_uke(l, r)); return 0; }
|
#include <bits/stdc++.h> int start, n, m; bool edge[25][25]; long long memory[25][(1 << 19) + 5]; long long dfs(int u, int mask) { if (memory[u][mask] != -1) return memory[u][mask]; int visit = 0; for (int i = 0; i < n; i++) { if (mask & (1 << i)) visit++; } long long result = 0; if (visit >= 3 && edge[u][start]) result = 1; for (int v = 0; v <= start; v++) { if (!edge[u][v]) { continue; } if (mask & (1 << v)) { continue; } result += dfs(v, mask | (1 << v)); } memory[u][mask] = result; return result; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d%d , &u, &v); u--; v--; edge[u][v] = edge[v][u] = true; } long long answer = 0; for (start = 0; start < n; start++) { for (int i = 0; i < n; i++) { for (int j = 0; j < 1 << n; j++) { memory[i][j] = -1; } } answer += dfs(start, 1 << start); } printf( %lld n , answer / 2); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; long long res = 0; while (a >= 1 && b >= 1) { if (a < b) swap(a, b); res += a / b; a %= b; } cout << res; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:14:33 05/25/2015
// Design Name:
// Module Name: seven_segment_leds_x_4_no_leading_zeros
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Note that the segments are a_to_g with a in position 6, b in position 5 etc
// The ucf should label cathode a to be seg[6], cathode b to be seg[5], etc.
// Note: to turn off decimal point set the corresponding bit high.
//////////////////////////////////////////////////////////////////////////////////
module seven_segment_leds_x_4_no_leading_zeros(
input [15:0] bcd_in,
input [3:0] decimal_points,
input clk,
output reg [6:0] a_to_g,
output reg decimal_point,
output reg [3:0] anode
);
wire [1:0] counter;
reg [3:0] digit;
reg [19:0] clkdiv;
assign counter = clkdiv[19:18]; //count every 2.6 ms (with 100 MHz clock)
//quad 4 to 1 MUX
always @(*)
case(counter)
0: {digit, decimal_point} = {bcd_in[3:0], decimal_points[0]};
1: {digit, decimal_point} = {bcd_in[7:4], decimal_points[1]};
2: {digit, decimal_point} = {bcd_in[11:8], decimal_points[2]};
3: {digit, decimal_point} = {bcd_in[15:12], decimal_points[3]};
endcase
//7-segment decoder
always @(*)
case(digit)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
default: a_to_g = 7'b0000001; //default to 0
endcase
//digit selector
always @(*)
case(counter)
0: anode = 4'b1110;
1: anode = {2'b11,!(| bcd_in[15:4]),1'b1};
2: anode = {1'b1,!(| bcd_in[15:8]),2'b11};
3: anode = {!(| bcd_in[15:12]),3'b111};
default: anode = 4'b1111; //all blank
endcase
//clock divider
always @ (posedge clk)
begin
clkdiv <= clkdiv + 20'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int v[N]; int n, k; int main() { scanf( %d %d , &n, &k); n--; for (int i = 1; i <= n; ++i) scanf( %d , v + i), v[i] += v[i - 1]; int ans = 0x3F3F3F3F; for (int i = k; i <= n; ++i) ans = min(ans, v[i] - v[i - k]); printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int A[5][5], x, y, p, q, sum; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { cin >> A[i][j]; if (A[i][j] == 1) { x = i; y = j; } } cout << endl; } if (x == 2 && y == 2) { p = 0; q = 0; } else if (x >= 2 && y >= 2) { p = x - 2; q = y - 2; } else if (x >= 2 && y <= 2) { p = x - 2; q = 2 - y; } else if (x <= 2 && y >= 2) { p = 2 - x; q = y - 2; } else if (x <= 2 && y <= 2) { p = 2 - x; q = 2 - y; } sum = p + q; cout << sum; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> a; int main() { int n, x, ans; cin >> n >> x; ans = x; a.resize(n); for (int i = 0; i < (int)(n); i++) { cin >> a[i]; } for (int i = 0; i < (int)(n); i++) { for (int j = i; j < n; j++) { ans = max(ans, (x / a[i]) * a[j] + (x % a[i])); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void DBGpair(T a, string s = ) { cerr << s << (s == ? : : ) << a.first << , << a.second << n ; } template <class T> void DBGvec(vector<T> a) { for (T i : a) cerr << i << ; cerr << n ; } int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; char dir[] = { R , L , D , U }; const int MOD = 1e9 + 7; const long long INF = 1e9; void setIO(string filename) { if (fopen((filename + .in ).c_str(), r )) { freopen((filename + .in ).c_str(), r , stdin); freopen((filename + .out ).c_str(), w , stdout); } } struct bit { vector<long long> tree; bit(int n) { tree = vector<long long>(n + 5, 0); } long long rsq(int idx) { long long sum = 0; while (idx > 0) { sum += tree[idx]; idx -= idx & -idx; } return sum; } long long rsq(int a, int b) { a++; b++; return rsq(b) - (a == 1 ? 0 : rsq(a - 1)); } void upd(int idx, int val) { idx++; while (idx < tree.size() - 1) { tree[idx] += val; idx += idx & -idx; } } }; void solve() { int n; cin >> n; vector<long long> a(n); for (auto &i : a) cin >> i; vector<long long> t(n); for (auto &i : t) cin >> i; vector<long long> psums(n + 1); for (int i = 1; i <= n; i++) psums[i] = psums[i - 1] + t[i - 1]; bit tree(n); vector<long long> pos(n + 1); for (int i = 0; i < n; i++) tree.upd(i, 1); for (int i = 0; i < n; i++) { int idx = upper_bound((psums).begin(), (psums).end(), a[i] + psums[i]) - psums.begin(); if (idx == psums.size()) continue; idx--; pos[idx] += a[i] + psums[i] - psums[idx]; tree.upd(idx, -1); } for (int i = 0; i < n; i++) { long long ans = tree.rsq(0, i) * t[i] + pos[i]; cout << ans << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; for (int i = 1; i <= t; i++) solve(); }
|
#include <bits/stdc++.h> using namespace std; vector<int> e[200010]; vector<int> a; int n; int siz[200010]; int id[200010]; int d[200010]; int c[200010]; int f[200010]; int dfn; void dfs(int x, int fa) { id[x] = ++dfn; siz[x]++; for (int i = 0; i < e[x].size(); i++) { if (e[x][i] == fa) continue; dfs(e[x][i], x); siz[x] += siz[e[x][i]]; } } void dfs(int x, int fa, int *y) { int temp = (n - siz[x]); bool flag = true; for (int i = 0; i < e[x].size(); i++) { if (e[x][i] == fa) continue; dfs(e[x][i], x, y); if (temp != siz[e[x][i]]) { flag = false; } } if (flag && siz[x] > 1) { *y = x; } } bool judge(int x, int fa, int dep) { if (c[x] != -1 && f[x] != fa && c[x] != fa) return false; f[x] = -1; for (int i = 0; i < e[x].size(); i++) { int nt = e[x][i]; if (nt == fa) continue; int son_siz = siz[nt]; if (id[x] > id[nt]) son_siz = n - siz[x]; if (d[dep] == -1) { d[dep] = son_siz; } if (d[dep] != son_siz) { c[x] = nt; return false; } f[x] = nt; } for (int i = 0; i < e[x].size(); i++) { int nt = e[x][i]; if (nt == fa) continue; if (!judge(nt, x, dep + 1)) { c[x] = nt; return false; } f[x] = nt; } f[x] = -1; return true; } inline bool scan_d(int &num) { char in; bool IsN = false; in = getchar(); if (in == EOF) return false; while (in != - && (in < 0 || in > 9 )) in = getchar(); if (in == - ) { IsN = true; num = 0; } else num = in - 0 ; while (in = getchar(), in >= 0 && in <= 9 ) { num *= 10, num += in - 0 ; } if (IsN) num = -num; return true; } int main() { int x = -1, u, v, k = -1; scanf( %d , &n); for (int i = 1; i < n; i++) { scan_d(u); scan_d(v); if (k == -1) k = u; e[u].push_back(v); e[v].push_back(u); } dfs(1, 1); dfs(1, 1, &x); for (int i = 1; i <= n; i++) { if (e[i].size() <= 1) { a.push_back(i); } } if (x != -1) { a.push_back(x); } memset(d, -1, sizeof(d)); memset(c, -1, sizeof(c)); memset(f, -1, sizeof(f)); for (int i = 0; i < a.size(); i++) { if (judge(a[i], a[i], 1)) { printf( %d n , a[i]); return 0; } for (int i = 1;; i++) { if (d[i] == -1) break; d[i] = -1; } } printf( -1 n ); return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
/**
* top_sio_macro: sky130_fd_io__sio_macro consists of two SIO cells
* and a reference generator cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio_macro (
//# {{data|Data Signals}}
input DFT_REFGEN ,
input [1:0] SLOW ,
output [1:0] IN ,
input [1:0] INP_DIS ,
output [1:0] IN_H ,
input [1:0] OUT ,
inout [1:0] PAD ,
inout [1:0] PAD_A_ESD_0_H ,
inout [1:0] PAD_A_ESD_1_H ,
inout [1:0] PAD_A_NOESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input [2:0] DM0 ,
input [2:0] DM1 ,
input ENABLE_H ,
input ENABLE_VDDA_H ,
input [1:0] HLD_H_N ,
input HLD_H_N_REFGEN ,
input [1:0] HLD_OVR ,
input [1:0] IBUF_SEL ,
input IBUF_SEL_REFGEN ,
input [1:0] OE_N ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input [1:0] VREG_EN ,
input VREG_EN_REFGEN ,
input [1:0] VTRIP_SEL ,
input VTRIP_SEL_REFGEN,
inout VSWITCH ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VINREF_DFT ,
input VOHREF ,
inout VOUTREF_DFT ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q ,
output [1:0] TIE_LO_ESD
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; for (int i = 1; i <= t; i++) { int n, k, d; cin >> n >> k >> d; int mn = n; int a[n + 10]; for (int j = 1; j <= n; j++) cin >> a[j]; for (int j = 1; j <= n - d + 1; j++) { set<int> s; for (int q = j; q <= j + d - 1; q++) s.insert(a[q]); int z = s.size(); mn = min(mn, z); } cout << mn << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, cnt = 1; string s; bool ok = true, mtest = true; void solve() { cin >> b; vector<int> v(b), vc(b); for (auto& i : v) cin >> i; for (auto& i : vc) cin >> i; sort(v.begin(), v.end()); sort(vc.begin(), vc.end()); for (auto i : v) cout << i << ; cout << n ; for (auto i : vc) cout << i << ; cout << n ; } int main() { cin >> a; while (a--) solve(); cerr << nTime elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_1_V
`define SKY130_FD_SC_HDLL__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_1_V
|
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input clk,
input reset
);
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
// byte sum (unsigned)
wire [31:0] cfu0;
assign cfu0[31:0] = cmd_payload_inputs_0[7:0] + cmd_payload_inputs_1[7:0] +
cmd_payload_inputs_0[15:8] + cmd_payload_inputs_1[15:8] +
cmd_payload_inputs_0[23:16] + cmd_payload_inputs_1[23:16] +
cmd_payload_inputs_0[31:24] + cmd_payload_inputs_1[31:24];
// byte swap
wire [31:0] cfu1;
assign cfu1[31:24] = cmd_payload_inputs_0[7:0];
assign cfu1[23:16] = cmd_payload_inputs_0[15:8];
assign cfu1[15:8] = cmd_payload_inputs_0[23:16];
assign cfu1[7:0] = cmd_payload_inputs_0[31:24];
// bit reverse
wire [31:0] cfu2;
genvar n;
generate
for (n=0; n<32; n=n+1) begin
assign cfu2[n] = cmd_payload_inputs_0[31-n];
end
endgenerate
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[1] ? cfu2 :
( cmd_payload_function_id[0] ? cfu1 : cfu0);
endmodule
|
#include <bits/stdc++.h> using namespace std; void setIo(string nom) { ios_base::sync_with_stdio(0); cin.tie(0); freopen((nom + .in ).c_str(), r , stdin); freopen((nom + .out ).c_str(), w , stdout); } struct Reine { int x, y, id; vector<int> tris; int indTri; void init(int i) { cin >> x >> y; id = i; tris = {x, y - x, y, -x - y}; } bool operator<(const Reine& autre) const { if (indTri != 0) return x < autre.x; else return y < autre.y; } }; const int N = 2e5; int ans[N], comptes[N]; signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int cote, nReines; cin >> cote >> nReines; vector<Reine> reines(nReines); map<int, vector<Reine>> idems; int ind = 0; for (Reine& reine : reines) reine.init(ind++); for (int indTri = 0; indTri < 4; ++indTri) { for (Reine& reine : reines) { reine.indTri = indTri; idems[reine.tris[indTri]].push_back(reine); } for (auto& etage : idems) { sort(etage.second.begin(), etage.second.end()); for (int i = 0; i < (int)etage.second.size(); ++i) { ans[etage.second[i].id] += (i != 0) + (i != ((int)etage.second.size() - 1)); } } idems.clear(); } for (ind = 0; ind < nReines; ++ind) { comptes[ans[ind]]++; } cout << endl; for (int i = 0; i < 9; ++i) cout << comptes[i] << ; cout << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 13:33:41
// Design Name:
// Module Name: down_counter_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module down_counter_tb(
);
parameter COUNT = 100;
parameter DELAY = 10;
parameter TIME = (COUNT * DELAY);
reg clk, start;
wire cnt_done;
integer i;
down_counter #(5) DUT (start, clk, cnt_done);
initial begin
#TIME $finish;
end
initial begin
clk = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY clk = ~clk;
end
end
initial begin
start = 0;
#DELAY start = 1;
#DELAY start = 0;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 1. Squate waves with variable timer, frequency, envelope functions and frequency sweep.
////////////////////////////////////////////////////////////////////////////////////
module osc2
(
input wire iClock,
input wire iReset,
output wire oOut131k,
output wire oOut262k
);
reg [4:0] rOscCounter; // log2(/131072*2) = log2(16)= 4. Last bit corresponds to the output.
always @ (posedge iClock) begin
if (iReset) begin
rOscCounter <= 0;
end
else begin
rOscCounter <= rOscCounter+1;
end
end
assign oOut131k = rOscCounter[4];
assign oOut262k = rOscCounter[3];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
/**
* sleep_pargate_plv: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_pargate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_SYMBOL_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Set_Acceleration.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Set_Acceleration
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Set_Acceleration
(
CLK_IN,
reset,
enb_1_2000_0,
v_target,
v_current,
a
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] v_target; // sfix18_En8
input signed [31:0] v_current; // sfix32_En22
output signed [17:0] a; // sfix18_En10
wire signed [31:0] Relational_Operator_1_cast; // sfix32_En22
wire Relational_Operator_relop1;
wire current_less_than_target;
wire current_less_than_target_1;
wire current_greater_than_target;
wire target_has_changed;
wire Latch_out1;
reg Delay1_out1;
wire Latch_out1_1;
wire negative_direction;
wire switch_compare_1;
wire signed [17:0] Acceleration1_out1; // sfix18_En10
wire signed [18:0] Neg_cast; // sfix19_En10
wire signed [18:0] Neg_cast_1; // sfix19_En10
wire signed [35:0] Neg_cast_2; // sfix36_En27
wire signed [17:0] Neg_out1; // sfix18_En10
wire current_greater_than_target_1;
wire stop_positive_acceleration;
wire current_less_than_target_2;
wire stop_negative_acceleration;
wire stop_positive_acceleration_1;
wire stop_accelerating;
wire signed [17:0] positive_accleration; // sfix18_En10
wire signed [17:0] accleration; // sfix18_En10
wire signed [17:0] Constant_out1; // sfix18_En10
wire signed [17:0] Switch_Stop_out1; // sfix18_En10
// Set Acceleration
// <S29>/Relational Operator
assign Relational_Operator_1_cast = {v_target, 14'b00000000000000};
assign Relational_Operator_relop1 = (Relational_Operator_1_cast > v_current ? 1'b1 :
1'b0);
assign current_less_than_target = Relational_Operator_relop1;
// <S29>/NOT2
assign current_less_than_target_1 = ~ current_less_than_target;
assign current_greater_than_target = current_less_than_target_1;
// <S29>/Detect_Change
controllerHdl_Detect_Change u_Detect_Change (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.x(v_target), // sfix18_En8
.y(target_has_changed)
);
// <S29>/Delay1
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 1'b0;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= Latch_out1;
end
end
// <S29>/Latch
//
// <S29>/Signal Specification
assign Latch_out1 = (target_has_changed == 1'b0 ? Delay1_out1 :
current_less_than_target);
// <S29>/NOT3
assign Latch_out1_1 = ~ Latch_out1;
assign negative_direction = Latch_out1_1;
assign switch_compare_1 = (Latch_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S29>/Acceleration1
assign Acceleration1_out1 = 18'sb001010000000000000;
// <S29>/Neg
assign Neg_cast = Acceleration1_out1;
assign Neg_cast_1 = - (Neg_cast);
assign Neg_cast_2 = {Neg_cast_1, 17'b00000000000000000};
assign Neg_out1 = Neg_cast_2[34:17];
// <S29>/AND_Pos
assign current_greater_than_target_1 = current_greater_than_target & Latch_out1;
assign stop_positive_acceleration = current_greater_than_target_1;
// <S29>/AND_Neg
assign current_less_than_target_2 = current_less_than_target & negative_direction;
assign stop_negative_acceleration = current_less_than_target_2;
// <S29>/OR_SAT1
assign stop_positive_acceleration_1 = stop_positive_acceleration | stop_negative_acceleration;
assign stop_accelerating = stop_positive_acceleration_1;
// <S29>/Acceleration
assign positive_accleration = 18'sb001010000000000000;
// <S29>/Switch_Dir
assign accleration = (switch_compare_1 == 1'b0 ? Neg_out1 :
positive_accleration);
// <S29>/Constant
assign Constant_out1 = 18'sb000000000000000000;
// <S29>/Switch_Stop
assign Switch_Stop_out1 = (stop_accelerating == 1'b0 ? accleration :
Constant_out1);
assign a = Switch_Stop_out1;
endmodule // controllerHdl_Set_Acceleration
|
#include <bits/stdc++.h> using namespace std; int q, ans; char s[300010]; set<int> len, hs[300010]; int p[300010], v[300010]; int main() { int i, l, op; for (i = 1, p[0] = 1; i <= 300000; ++i) p[i] = 1LL * p[i - 1] * 27 % 1000000007; scanf( %d , &q); while (q--) { scanf( %d%s , &op, s + 1); l = strlen(s + 1); for (i = 1, v[0] = 0; i <= l; ++i) v[i] = (1LL * v[i - 1] * 27 + s[i] - a + 1) % 1000000007; if (op == 1) { len.insert(l); hs[l].insert(v[l]); } else if (op == 2) hs[l].erase(v[l]); else { ans = 0; for (auto it = len.begin(); it != len.end(); it++) for (i = *it; i <= l; i++) ans += (hs[*it].find((v[i] - 1LL * v[i - *it] * p[*it] % 1000000007 + 1000000007) % 1000000007) != hs[*it].end()); printf( %d n , ans); fflush(stdout); } } return 0; }
|
#include <bits/stdc++.h> const long double eps = 1e-6; struct Point { long long x, y; Point(long long _x = 0, long long _y = 0) : x(_x), y(_y) {} Point operator-(const Point &B) const { return Point(x - B.x, y - B.y); } long double operator*(const Point &B) const { return (long double)x * B.y - (long double)y * B.x; } } stk[1023000]; int top; long long k, b; long long calc(Point A) { return A.y + k * A.x + b; } inline int read() { int n = 0; char a; bool z = false; while (a = getchar()) { if (a > 9 || a < 0 ) if (z) break; else continue; if (!z) z = true; n = (n << 3) + (n << 1) + (a ^ 48); } return n; } int main() { long long n = read(); int Q = read(), opt; Point now; stk[top = 1] = Point(); while (Q--) { opt = read(); switch (opt) { case 1: stk[top = 1] = Point(); n += read(); k = b = 0; break; case 2: now = Point(n, -(n * k + b)); n += read(); while (top > 1 && (now - stk[top - 1]) * (stk[top] - stk[top - 1]) > -eps) --top; stk[++top] = now; break; case 3: b += read(); k += read(); break; } while (top > 1 && calc(stk[top]) >= calc(stk[top - 1])) --top; printf( %lld %lld n , stk[top].x + 1, calc(stk[top])); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 10200; const int mod = 1e9 + 7; int dp[N]; int len[N]; inline int get_len(int x) { if (x == 0) return 1; int res = 0; while (x) res++, x /= 10; return res; } vector<int> del[N]; vector<int> calc_prefix(string s) { int n = (int)s.length(); vector<int> pi(n); for (int i = 1; i < n; ++i) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) ++j; pi[i] = j; } return pi; } int main() { ios::sync_with_stdio(0); cin.tie(0); string s; cin >> s; int n = s.length(); for (int i = 0; i <= n; ++i) len[i] = get_len(i); for (int i = 1; i <= n; ++i) for (int j = i; j <= n; j += i) del[j].push_back(i); for (int i = 1; i <= n; ++i) dp[i] = 1e9; dp[0] = 0; string t; vector<int> p; for (int i = 1; i <= n; ++i) { int cur_len = 0, times; int period; t = ; for (int j = i; j <= n; ++j) t += s[j - 1]; p = calc_prefix(t); for (int j = i; j <= n; ++j) { cur_len++; dp[j] = min(dp[j], dp[i - 1] + cur_len + 1); period = cur_len - p[j - i]; if (cur_len % period != 0) continue; dp[j] = min(dp[j], dp[i - 1] + len[cur_len / period] + period); } } cout << dp[n]; return 0; }
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module basys3_demo (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
// Input 100MHz clock through a BUFG
wire clk100;
BUFG bufg100 (.I(clk), .O(clk100));
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk100) begin
reset_cnt <= reset_cnt + !resetn;
end
// A simple GPIO peripheral connected to LEDs
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
always @(posedge clk100) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
// The picosoc
picosoc_noflash soc (
.clk (clk100),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_LP_V
`define SKY130_FD_SC_LP__O32AI_LP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_lp (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_LP_V
|
//----------------------------------------------------------------------
// Title : Configuration Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : configuration_tb.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: Management
//
// This testbench will exercise the ports of the generic
// host interface to configure the EMAC.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module configuration_tb (
reset,
//----------------------------------------------------------------
// Host interface
//----------------------------------------------------------------
host_clk,
host_opcode,
host_req,
host_miim_sel,
host_addr,
host_wr_data,
host_miim_rdy,
host_rd_data,
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
configuration_busy,
monitor_finished_1g,
monitor_finished_100m,
monitor_finished_10m,
monitor_error
);
// Port declarations
output reg reset;
output reg host_clk;
output reg [1:0] host_opcode;
output reg host_req;
output reg host_miim_sel;
output reg [9:0] host_addr;
output reg [31:0] host_wr_data;
input host_miim_rdy;
input [31:0] host_rd_data;
output reg configuration_busy;
input monitor_finished_1g;
input monitor_finished_100m;
input monitor_finished_10m;
input monitor_error;
//---------------------------------------------------------------------------
// Register map constants
//---------------------------------------------------------------------------
// Management configuration register address (0x340)
reg [8:0] config_management_address;
// Flow control configuration register address (0x2C0)
reg [8:0] config_flow_control_address;
// Receiver configuration register address (0x240)
reg [8:0] receiver_address;
// Transmitter configuration register address (0x280)
reg [8:0] transmitter_address;
// EMAC configuration register address (0x300)
reg [8:0] emac_config_add;
initial
begin
// Management configuration register address (0x340)
config_management_address = 9'b101000000;
// Flow control configuration register address (0x2C0)
config_flow_control_address = 9'b011000000;
// Receiver configuration register address (0x240)
receiver_address = 9'b001000000;
// Transmitter configuration register address (0x280)
transmitter_address = 9'b010000000;
// EMAC configuration register address (0x300)
emac_config_add = 9'b100000000;
end
//--------------------------------------------------------------------
// Host clock driver
//--------------------------------------------------------------------
// Drive host clock at one third the frequency of GTX_CLK
initial
begin
host_clk <= 1'b0;
#2000;
forever
begin
host_clk <= 1'b1;
#12000;
host_clk <= 1'b0;
#12000;
end
end
//------------------------------------------------------------------
// EMAC host configuration write procedure
//------------------------------------------------------------------
task config_write;
input [8:0] address;
input [31:0] data;
begin
@(negedge host_clk)
host_addr[9] <= 1'b1;
host_addr[8:0] <= address;
host_miim_sel <= 1'b0;
host_opcode <= 2'b1;
host_wr_data <= data;
@(negedge host_clk)
host_addr[9] <= 1'b1;
host_miim_sel <= 1'b0;
host_opcode <= 2'b11;
host_wr_data <= 32'b0;
@(negedge host_clk);
end
endtask
//------------------------------------------------------------------
// EMAC host configuration read procedure
//------------------------------------------------------------------
task config_read;
input [8:0] address;
begin
@(negedge host_clk)
host_addr[9] <= 1'b1;
host_addr[8:0] <= address;
host_miim_sel <= 1'b0;
host_opcode <= 2'b11;
@(negedge host_clk);
@(posedge host_clk);
end
endtask
//------------------------------------------------------------------
// Configuration through the host interface
//------------------------------------------------------------------
initial
begin : tb_configuration
configuration_busy <= 0;
// Initialize the host bus
host_req <= 1'b0;
host_addr[9] <= 1'b1;
host_addr[8:0] <= 9'b0;
host_miim_sel <= 1'b0;
host_opcode <= 2'b11;
host_wr_data <= 32'b0;
// Reset the core
$display("Resetting the design...");
$display("Timing checks are not valid");
reset <= 1'b1;
#;
reset <= 1'b0;
#200000;
$display("Timing checks are valid");
configuration_busy <= 1;
// wait for EMAC host interface to initialize
while (host_miim_rdy !== 1)
@(negedge host_clk);
//--------------------------------------------------------------------------
// Configuration: initialization of EMAC
//--------------------------------------------------------------------------
// Disable flow control. Set top 3 bits of the flow control
// configuration register (0x2C0) to zero therefore disabling Tx
// and Rx flow control.
//------------------------------------------------------------------------
$display("Disabling Tx and Rx flow control...");
// Read the current configuration value from the register
config_read (config_flow_control_address);
// Now turn off the relevant bits and write back into the register
config_write (config_flow_control_address, {3'b0, host_rd_data[28:0]});
// Setting the Tx configuration bit to enable the transmitter
// and set to full duplex mode.
// Write to transmittter configuration register (0x280).
//------------------------------------------------------------------------
$display("Setting Tx configuration...");
// Read the current configuration value from the register
config_read (transmitter_address);
// Now set the relevant bits and write back into the register
config_write (transmitter_address,
{1'b0, host_rd_data[30:29], 1'b1,
host_rd_data[27], 1'b0, host_rd_data[25:0]});
// Setting the Rx configuration bit to enable the receiver
// and set to full duplex mode.
// Write to receiver configuration register (0x240).
//-----------------------------------------------------------------------
$display("Setting Rx configuration...");
// Read the current configuration value from the register
config_read (receiver_address);
// Now set the relevant bits and write back into the register
config_write (receiver_address,
{1'b0, host_rd_data[30:29], 1'b1,
host_rd_data[27], 1'b0, host_rd_data[25:0]});
//--------------------------------------------------------------------------
// Setting the speed to 1 Gb/s
//--------------------------------------------------------------------------
// Write to EMAC configuration fegister (0x300)
$display("Setting speed to 1 Gb/s...");
// Read the current configuration value from the register
config_read (emac_config_add);
// Now set the relevant bits and write back into the register
config_write (emac_config_add, {2'b10, host_rd_data[29:0]});
configuration_busy <= 0;
// Wait for 1 Gb/s frames to complete
wait (monitor_finished_1g == 1);
#100000
if (monitor_error == 1'b1)
begin
$display("*************************");
$display("ERROR: Simulation Failed.");
$display("*************************");
end
else begin
$display("****************************");
$display("PASS: Simulation Successful.");
$display("****************************");
end
$display("Simulation complete.");
$stop;
end
//------------------------------------------------------------------
// If the simulation is still going after 2 ms
// then something has gone wrong
//------------------------------------------------------------------
initial
begin : p_end_simulation
#
$display("ERROR - Testbench timed out");
$stop;
end
endmodule
|
`timescale 1ns / 1ps
module COUNT
#(
parameter N=7
)
(
A,
S
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2=0; temp>0; log2=log2+1)
temp = temp>>1;
end
endfunction
localparam K = log2(N);
localparam K2 = log2(N - 2**(K-1));
input [N-1:0] A;
output [K-1:0] S;
wire [K-2:0] S1;
wire [K-2:0] S2pad;
wire [K2-1:0] S2;
generate
if(K2==0) begin: g1
assign S2pad = {(K-1){1'b0}};
end else if (K-K2-1>0) begin: g2
assign S2pad = {{(K-K2-1){1'b0}}, S2};
end else begin: g3
assign S2pad = S2;
end
endgenerate
generate
if(N==1) begin: g4
assign S=A[0];
end else if(N==2) begin: g5
ADD
#(
.N(1)
)
ADD_3
(
.A(A[1]),
.B({1'b0}),
.CI(A[0]),
.S(S[0]),
.CO(S[1])
);
end else if(N==3) begin: g6
ADD
#(
.N(1)
)
ADD_3
(
.A(A[1]),
.B(A[2]),
.CI(A[0]),
.S(S[K-2:0]),
.CO(S[K-1])
);
end else if (N>3) begin: g7
COUNT
#(
.N(2**(K-1)-1)
)
COUNT_1
(
.A(A[N-1:N-2**(K-1)+1]),
.S(S1)
);
if(N-2**(K-1)>0) begin: g8
COUNT
#(
.N(N-2**(K-1))
)
COUNT_2
(
.A(A[N-2**(K-1):1]),
.S(S2)
);
end
ADD
#(
.N(K-1)
)
ADD_
(
.A(S1),
.B(S2pad),
.CI(A[0]),
.S(S[K-2:0]),
.CO(S[K-1])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int q; long long int input; long long int lastSum[20]; long long int limit[20]; long long int targetSum(int digit, long long int target) { long long int ret = lastSum[digit - 1] * target; ret += target * (target + 1) * digit / 2; return ret; } long long int targetSubSum(long long int target) { if (target == 0) return 0; int digit = 0; long long int tmp = target, ret = 0, mul = 1; while (tmp) digit++, tmp /= 10, mul *= 10; ret += lastSum[digit - 1]; target -= (mul / 10) - 1; ret += target * digit; return ret; } int main() { long long int mul = 9; for (int digit = 1; digit < 10; digit++) { lastSum[digit] = lastSum[digit - 1] + digit * mul; limit[digit] = limit[digit - 1] + lastSum[digit - 1] * mul + digit * mul * (mul + 1) / 2; mul *= 10; } scanf( %d , &q); while (q) { scanf( %lld , &input); int digit = 1; long long int low = 0, high = 9, answer = 1; while (limit[digit] < input) digit++, high *= 10; input -= limit[digit - 1]; while (low <= high) { long long int mid = (low + high) / 2; if (targetSum(digit, mid) <= input) { answer = mid; low = mid + 1; } else high = mid - 1; } long long int mul = 1; for (int i = 1; i < digit; i++) mul *= 10; input -= targetSum(digit, answer); if (input == 0) printf( %lld n , (answer + mul - 1) % 10); else { low = 0, high = answer + mul - 1, answer = 0; while (low <= high) { long long int mid = (low + high) / 2; if (targetSubSum(mid) <= input) { answer = mid; low = mid + 1; } else high = mid - 1; } input -= targetSubSum(answer); if (input == 0) printf( %lld n , answer % 10); else { stack<int> s; answer++; while (answer) { s.push(answer % 10); answer /= 10; } for (int i = 1; i < input; i++) s.pop(); printf( %d n , s.top()); } } q--; } }
|
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